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FPPS4
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This commit is contained in:
Pavel 2025-05-29 23:45:18 +03:00
parent b6bf97c51a
commit a9c65e098c
2 changed files with 41 additions and 33 deletions
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17
chip/pm4_pfp.pas
View File

@ -8,8 +8,6 @@ interface
uses uses
sysutils, sysutils,
mqueue, mqueue,
bittype,
pm4_ring,
pm4defs, pm4defs,
pm4_stream, pm4_stream,
time, time,
@ -1518,18 +1516,17 @@ begin
end; end;
procedure onSetPredication(pctx:p_pfp_ctx;Body:PPM4CMDSETPREDICATION); procedure onSetPredication(pctx:p_pfp_ctx;Body:PPM4CMDSETPREDICATION);
var const
addr:QWORD; c_pred_b:array[0..1] of PChar=('DrawIfNotVisible','DrawIfVisible');
c_hint_v:array[0..1] of PChar=('Wait','Draw');
begin begin
Assert(pctx^.stream_type=stGfxDcb); Assert(pctx^.stream_type=stGfxDcb);
addr:=QWORD(Body^.startAddress); if (Body^.predOp<>0) then
if (addr<>0) then
if p_print_gpu_ops then
begin begin
Writeln(' startAddress=0x',HexStr(addr,16)); Writeln(' startAddress=0x',HexStr(Body^.startAddress,10));
Writeln(' pred =',Body^.predicationBoolean); Writeln(' pred =',c_pred_b[Body^.predicationBoolean]);
Writeln(' hint =',Body^.hint); Writeln(' hint =',c_hint_v[Body^.hint]);
Writeln(' predOp =',Body^.predOp); Writeln(' predOp =',Body^.predOp);
Writeln(' continueBit =',Body^.continueBit); Writeln(' continueBit =',Body^.continueBit);
end; end;

57
chip/pm4defs.pas
View File

@ -373,12 +373,15 @@ type
TPM4CMDSETPREDICATION=bitpacked record TPM4CMDSETPREDICATION=bitpacked record
header :PM4_TYPE_3_HEADER; header :PM4_TYPE_3_HEADER;
startAddress :bit40; // < start address startAddress :bit40; // < start address
predicationBoolean:bit1; // < predication boolean //8
predicationBoolean:bit1; // < predication boolean (DrawIfNotVisible=0,DrawIfVisible=1)
reserved1 :bit3; reserved1 :bit3;
hint :bit1; // < hint //12
hint :bit1; // < hint (Wait = 0,Draw = 1)
// < (only valid for Zpass/Occlusion Predicate) // < (only valid for Zpass/Occlusion Predicate)
reserved2 :bit3; reserved2 :bit3;
predOp :bit3; // < predicate operation //16
predOp :bit3; // < predicate operation (SET_PRED_ZPASS)
reserved3 :bit12; reserved3 :bit12;
continueBit :bit1; // < continue set predication continueBit :bit1; // < continue set predication
end; end;
@ -526,27 +529,35 @@ const
EVENT_WRITE_INDEX_CACHE_FLUSH_EVENT = 7; EVENT_WRITE_INDEX_CACHE_FLUSH_EVENT = 7;
type type
PTPM4CMDEVENTWRITE=^TPM4CMDEVENTWRITE; PTPM4CMDEVENTWRITE=^PM4CMDEVENTWRITE;
TPM4CMDEVENTWRITE=bitpacked record PM4CMDEVENTWRITE=bitpacked record
header :PM4_TYPE_3_HEADER; header :PM4_TYPE_3_HEADER;
eventType :bit6; ///< event type written to VGT_EVENT_INITIATOR eventType :bit6; // event type written to VGT_EVENT_INITIATOR
reserved1 :bit2; ///< reserved reserved1 :bit2; // reserved
eventIndex :bit4; ///< event index eventIndex :bit4; // event index
///< 0000: Any non-Time Stamp/non-Fence/non-Trap EVENT_TYPE not listed. // 0000: Any non-Time Stamp/non-Fence/non-Trap EVENT_TYPE not listed.
///< 0001: ZPASS_DONE // 0001: ZPASS_DONE
///< 0010: SAMPLE_PIPELINESTATS // 0010: SAMPLE_PIPELINESTATS
///< 0011: SAMPLE_STREAMOUTSTAT[S|S1|S2|S3] // 0011: SAMPLE_STREAMOUTSTAT[S|S1|S2|S3]
///< 0100: [CS|VS|PS]_PARTIAL_FLUSH // 0100: [CS|VS|PS]_PARTIAL_FLUSH
///< 0101: Reserved for EVENT_WRITE_EOP time stamp/fence event types // 0101: Reserved for EVENT_WRITE_EOP time stamp/fence event types
///< 0110: Reserved for EVENT_WRITE_EOS packet // 0110: Reserved for EVENT_WRITE_EOS packet
///< 0111: CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT // 0111: CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
///< 1000 - 1111: Reserved for future use. // 1000 - 1111: Reserved for future use.
reserved2 :bit8; ///< reserved reserved2 :bit20; // reserved
invalidateL2 :bit1; ///< Send WBINVL2 op to the TC L2 cache when eventIndex = 0111. u:bitpacked record
reserved3 :bit3; case Byte of
ATC :bit1; ///< needed by Sample_PipelineStats (compute engine) //PIXEL_PIPE_STAT_DUMP
reserved4 :bit6; ///< reserved 0:(address:QWORD); // 8 byte aligned (40bit)
offload_enable :bit1; ///< Offload queue until EOP queue goes empty, only works for MEC. ///< Setting this bit on graphics/ME will do nothing/be masked out. //PIXEL_PIPE_STAT_CONTROL
1:(
reserved2 :bit3;
counter_id :bit6;
stride :bit2;
instance_enable:bit16;
reserved3 :bit5;
);
end;
end; end;
const const