mirror of https://github.com/red-prig/fpPS4.git
This commit is contained in:
Pavel
parent
e239da9978
commit
90cf5fe6ff
215
chip/pm4_pfp.pas
215
chip/pm4_pfp.pas
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@ -110,12 +110,6 @@ begin
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ib_base:=QWORD(buf^.ibBase);
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ib_size:=QWORD(buf^.ibSize)*sizeof(DWORD);
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case op of
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$c0023300:Writeln('INDIRECT_BUFFER (ccb) 0x',HexStr(ib_base,10));
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$c0023f00:Writeln('INDIRECT_BUFFER (dcb) 0x',HexStr(ib_base,10));
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else;
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end;
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addr:=nil;
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size:=0;
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@ -150,6 +144,8 @@ var
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begin
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Result:=0;
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pctx^.LastSetReg:=0;
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i:=ibuf^.bpos;
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buff:=ibuf^.buff+i;
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i:=ibuf^.size-i;
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@ -841,6 +837,9 @@ begin
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end;
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end;
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const
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ShdrType:array[0..1] of Pchar=('(GX)','(CS)');
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function pm4_parse_ccb(pctx:p_pfp_ctx;token:DWORD;buff:Pointer):Integer;
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begin
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Result:=0;
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@ -858,7 +857,9 @@ begin
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if (PM4_TYPE_3_HEADER(token).opcode<>IT_NOP) or
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(not pctx^.print_hint) then
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begin
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Writeln('IT_',get_op_name(PM4_TYPE_3_HEADER(token).opcode),' len:',PM4_LENGTH(token));
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Writeln('IT_',get_op_name(PM4_TYPE_3_HEADER(token).opcode),
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' ',ShdrType[PM4_TYPE_3_HEADER(token).shaderType],
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' len:',PM4_LENGTH(token));
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end;
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case PM4_TYPE_3_HEADER(token).opcode of
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@ -902,11 +903,21 @@ end;
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procedure onEventWriteEop(pctx:p_pfp_ctx;Body:PPM4CMDEVENTWRITEEOP);
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var
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addr:Pointer;
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size:QWORD;
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begin
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DWORD(pctx^.CX_REG.VGT_EVENT_INITIATOR):=Body^.eventType;
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Case Body^.eventType of
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kEopFlushCbDbCaches:;
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kEopFlushAndInvalidateCbDbCaches:;
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kEopCbDbReadsDone:;
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else
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Assert(False,'EventWriteEop: eventType=0x'+HexStr(Body^.eventType,1));
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end;
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Assert(Body^.EVENT_INDEX=EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP);
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if (Body^.eventIndex<>EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP) then
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begin
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Assert(False,'EventWriteEop: eventIndex=0x'+HexStr(Body^.eventIndex,1));
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end;
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DWORD(pctx^.CX_REG.VGT_EVENT_INITIATOR):=Body^.eventType;
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Writeln(' eventType =0x',HexStr(Body^.eventType,2));
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Writeln(' interrupt =0x',HexStr(Body^.intSel shr 1,2));
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@ -929,11 +940,10 @@ begin
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}
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addr:=nil;
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size:=0;
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if (Body^.dataSel in [1..4]) then
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begin
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if get_dmem_ptr(Pointer(Body^.address),@addr,@size) then
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if get_dmem_ptr(Pointer(Body^.address),@addr,nil) then
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begin
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//
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end else
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@ -942,7 +952,162 @@ begin
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end;
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end;
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pctx^.stream_dcb.EventWriteEop(addr,Body^.DATA,Body^.dataSel,(Body^.intSel shr 1));
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pctx^.stream_dcb.EventWriteEop(addr,Body^.DATA,Body^.eventType,Body^.dataSel,(Body^.intSel shr 1));
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end;
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procedure onEventWriteEos(pctx:p_pfp_ctx;Body:PPM4CMDEVENTWRITEEOS);
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var
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addr:Pointer;
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begin
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Case Body^.eventType of
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CS_DONE:;
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PS_DONE:;
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else
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Assert(False,'EventWriteEos: eventType=0x'+HexStr(Body^.eventType,1));
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end;
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if (Body^.eventIndex<>EVENT_WRITE_INDEX_ANY_EOS_TIMESTAMP) then
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begin
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Assert(False,'EventWriteEos: eventIndex=0x'+HexStr(Body^.eventIndex,1));
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end;
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DWORD(pctx^.CX_REG.VGT_EVENT_INITIATOR):=Body^.eventType;
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if get_dmem_ptr(Pointer(Body^.address),@addr,nil) then
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begin
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//
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end else
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begin
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Assert(false,'addr:0x'+HexStr(Body^.address,16)+' not in dmem!');
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end;
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pctx^.stream_dcb.EventWriteEos(addr,Body^.data,Body^.eventType,Body^.command);
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end;
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procedure onDmaData(pctx:p_pfp_ctx;Body:PPM4DMADATA);
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var
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adrSrc,adrDst:QWORD;
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byteCount:DWORD;
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srcSel,dstSel:Byte;
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begin
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srcSel:=((PDWORD(Body)[1] shr $1d) and 3) or ((PDWORD(Body)[6] shr $19) and 8) or ((PDWORD(Body)[6] shr $18) and 4);
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dstSel:=((PDWORD(Body)[1] shr $14) and 1) or ((PDWORD(Body)[6] shr $1a) and 8) or ((PDWORD(Body)[6] shr $19) and 4);
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adrSrc:=Body^.srcAddr;
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adrDst:=Body^.dstAddr;
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byteCount:=Body^.Flags2.byteCount;
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case dstSel of
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kDmaDataDstRegister,
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kDmaDataDstRegisterNoIncrement:
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if (DWORD(adrDst)=$3022C) then
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begin
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//prefetchIntoL2
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Exit;
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end;
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else;
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end;
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Case Body^.Flags1.engine of
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CP_DMA_ENGINE_ME:
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begin
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pctx^.stream_dcb.DmaData(dstSel,adrDst,srcSel,adrSrc,byteCount,Body^.Flags1.cpSync);
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end;
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CP_DMA_ENGINE_PFP:
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begin
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//Execute on the parser side
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case (srcSel or (dstSel shl 4)) of
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(kDmaDataSrcMemory or (kDmaDataDstMemory shl 4)),
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(kDmaDataSrcMemoryUsingL2 or (kDmaDataDstMemory shl 4)),
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(kDmaDataSrcMemory or (kDmaDataDstMemoryUsingL2 shl 4)),
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(kDmaDataSrcMemoryUsingL2 or (kDmaDataDstMemoryUsingL2 shl 4)):
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begin
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Move(Pointer(adrSrc)^,Pointer(adrDst)^,byteCount);
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end;
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(kDmaDataSrcData or (kDmaDataDstMemory shl 4)),
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(kDmaDataSrcData or (kDmaDataDstMemoryUsingL2 shl 4)):
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begin
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FillDWORD(Pointer(adrDst)^,(byteCount div 4),DWORD(adrSrc));
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end;
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else
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Assert(false,'DmaData: srcSel=0x'+HexStr(srcSel,1)+' dstSel=0x'+HexStr(dstSel,1));
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end;
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end;
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else
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Assert(false,'DmaData: engine=0x'+HexStr(Body^.Flags1.engine,1));
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end;
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end;
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procedure onWriteData(pctx:p_pfp_ctx;Body:PPM4CMDWRITEDATA);
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var
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addr:PDWORD;
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count:Word;
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engineSel:Byte;
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dstSel:Byte;
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begin
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Assert(Body^.CONTROL.wrOneAddr=0,'WriteData: wrOneAddr<>0');
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count:=Body^.header.count;
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if (count<3) then Exit;
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engineSel:=Body^.CONTROL.engineSel;
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dstSel:=Body^.CONTROL.dstSel;
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Case engineSel of
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WRITE_DATA_ENGINE_ME:
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begin
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pctx^.stream_dcb.WriteData(dstSel,QWORD(addr),QWORD(@Body^.DATA),count);
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end;
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WRITE_DATA_ENGINE_PFP:
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begin
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case dstSel of
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WRITE_DATA_DST_SEL_MEMORY_SYNC, //writeDataInline
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WRITE_DATA_DST_SEL_TCL2, //writeDataInlineThroughL2
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WRITE_DATA_DST_SEL_MEMORY_ASYNC:
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begin
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count:=count-2;
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addr:=Pointer(Body^.dstAddr);
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Move(Body^.DATA,addr^,count*SizeOf(DWORD));
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end;
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else
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Assert(false,'WriteData: dstSel=0x'+HexStr(dstSel,1));
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end;
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end;
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else
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Assert(false,'WriteData: engineSel=0x'+HexStr(engineSel,1));
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end;
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end;
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procedure onWaitRegMem(pctx:p_pfp_ctx;Body:PPM4CMDWAITREGMEM);
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begin
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Case Body^.memSpace of
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WAIT_REG_MEM_SPACE_MEMORY:;
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else
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Assert(False,'WaitRegMem: memSpace=0x'+HexStr(Body^.memSpace,1));
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end;
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Case Body^.engine of
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WAIT_REG_MEM_ENGINE_ME:
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begin
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pctx^.stream_dcb.WaitRegMem(Body^.pollAddress,Body^.reference,Body^.mask,Body^.compareFunc);
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end;
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WAIT_REG_MEM_ENGINE_PFP:
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begin
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Assert(false,'WaitRegMem: engine=0x'+HexStr(Body^.engine,1));
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end;
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else
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Assert(false,'WaitRegMem: engine=0x'+HexStr(Body^.engine,1));
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end;
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end;
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@ -1260,13 +1425,13 @@ begin
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OP_HINT_PUSH_MARKER:
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if pctx^.print_hint then
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begin
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onPushMarker(@Body[1]);
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onPushMarker(@Body[2]);
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end;
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OP_HINT_SET_MARKER:
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if pctx^.print_hint then
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begin
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onSetMarker(@Body[1]);
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onSetMarker(@Body[2]);
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end;
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OP_HINT_PREPARE_FLIP_LABEL:
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@ -1313,15 +1478,19 @@ begin
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if (PM4_TYPE_3_HEADER(token).opcode<>IT_NOP) or
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(not pctx^.print_hint) then
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begin
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Writeln('IT_',get_op_name(PM4_TYPE_3_HEADER(token).opcode),' len:',PM4_LENGTH(token));
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Writeln('IT_',get_op_name(PM4_TYPE_3_HEADER(token).opcode),
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' ',ShdrType[PM4_TYPE_3_HEADER(token).shaderType],
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' len:',PM4_LENGTH(token));
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end;
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case PM4_TYPE_3_HEADER(token).opcode of
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IT_NOP :onNop(pctx,buff);
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IT_WRITE_DATA :onWriteData (pctx,buff);
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IT_EVENT_WRITE :onEventWrite (pctx,buff);
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IT_EVENT_WRITE_EOP :onEventWriteEop (pctx,buff);
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IT_EVENT_WRITE_EOS :Assert(false);
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IT_DMA_DATA :Assert(false);
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IT_EVENT_WRITE_EOS :onEventWriteEos (pctx,buff);
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IT_DMA_DATA :onDmaData (pctx,buff);
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IT_WAIT_REG_MEM :onWaitRegMem (pctx,buff);
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IT_ACQUIRE_MEM :onAcquireMem (pctx,buff);
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IT_CONTEXT_CONTROL :onContextControl (buff);
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IT_DRAW_PREAMBLE :onDrawPreamble (pctx,buff);
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@ -1335,12 +1504,10 @@ begin
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IT_INDEX_BASE :onIndexBase (pctx,buff);
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IT_NUM_INSTANCES :onNumInstances (pctx,buff);
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IT_DRAW_INDEX_2 :onDrawIndex2 (pctx,buff);
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IT_DRAW_INDEX_AUTO :Assert(false);
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IT_DRAW_INDEX_OFFSET_2:Assert(false);
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IT_DISPATCH_DIRECT :Assert(false);
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IT_WAIT_REG_MEM :Assert(false);
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IT_WRITE_DATA :Assert(false);
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IT_PFP_SYNC_ME :Assert(false);
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IT_DRAW_INDEX_AUTO :Assert(false,'IT_DRAW_INDEX_AUTO');
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IT_DRAW_INDEX_OFFSET_2:Assert(false,'IT_DRAW_INDEX_OFFSET_2');
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IT_DISPATCH_DIRECT :Assert(false,'IT_DISPATCH_DIRECT');
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IT_PFP_SYNC_ME :Assert(false,'IT_PFP_SYNC_ME');
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IT_SET_BASE :onSetBase(buff);
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IT_SET_PREDICATION :onSetPredication(buff);
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@ -54,6 +54,10 @@ type
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ntLoadConstRam,
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ntEventWrite,
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ntEventWriteEop,
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ntEventWriteEos,
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ntDmaData,
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ntWriteData,
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ntWaitRegMem,
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ntFastClear,
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ntResolve,
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ntDrawIndex2
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@ -66,23 +70,58 @@ type
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end;
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p_pm4_node_LoadConstRam=^t_pm4_node_LoadConstRam;
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t_pm4_node_LoadConstRam=object(t_pm4_node)
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t_pm4_node_LoadConstRam=packed object(t_pm4_node)
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addr :Pointer;
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num_dw:Word;
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offset:Word;
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end;
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p_pm4_node_EventWrite=^t_pm4_node_EventWrite;
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t_pm4_node_EventWrite=object(t_pm4_node)
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t_pm4_node_EventWrite=packed object(t_pm4_node)
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eventType:Byte;
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end;
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p_pm4_node_EventWriteEop=^t_pm4_node_EventWriteEop;
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t_pm4_node_EventWriteEop=object(t_pm4_node)
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addr :Pointer;
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data :QWORD;
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dataSel:Byte;
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intSel :Byte;
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t_pm4_node_EventWriteEop=packed object(t_pm4_node)
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addr :Pointer;
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data :QWORD;
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eventType:Byte;
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dataSel :Byte;
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intSel :Byte;
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end;
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p_pm4_node_EventWriteEos=^t_pm4_node_EventWriteEos;
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t_pm4_node_EventWriteEos=packed object(t_pm4_node)
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addr :Pointer;
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data :DWORD;
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eventType:Byte;
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command :Byte;
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end;
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p_pm4_node_DmaData=^t_pm4_node_DmaData;
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t_pm4_node_DmaData=packed object(t_pm4_node)
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dst :QWORD;
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src :QWORD;
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numBytes:DWORD;
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srcSel :Byte;
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dstSel :Byte;
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cpSync :Byte;
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end;
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p_pm4_node_WriteData=^t_pm4_node_WriteData;
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t_pm4_node_WriteData=packed object(t_pm4_node)
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dst :QWORD;
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src :QWORD;
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num_dw:Word;
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dstSel:Byte;
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end;
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p_pm4_node_WaitRegMem=^t_pm4_node_WaitRegMem;
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t_pm4_node_WaitRegMem=packed object(t_pm4_node)
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pollAddr :QWORD;
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refValue :DWORD;
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mask :DWORD;
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compareFunc :Byte;
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end;
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p_pm4_node_FastClear=^t_pm4_node_FastClear;
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@ -119,7 +158,11 @@ type
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//
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procedure LoadConstRam (addr:Pointer;num_dw,offset:Word);
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procedure EventWrite (eventType:Byte);
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procedure EventWriteEop(addr:Pointer;data:QWORD;dataSel,intSel:Byte);
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procedure EventWriteEop(addr:Pointer;data:QWORD;eventType,dataSel,intSel:Byte);
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procedure EventWriteEos(addr:Pointer;data:DWORD;eventType,command:Byte);
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procedure DmaData (dstSel:Byte;dst:QWORD;srcSel:Byte;srcOrData:QWORD;numBytes:DWORD;isBlocking:Byte);
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procedure WriteData (dstSel:Byte;dst,src:QWORD;num_dw:Word);
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procedure WaitRegMem (pollAddr:QWORD;refValue,mask:DWORD;compareFunc:Byte);
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procedure FastClear (var CX_REG:TCONTEXT_REG_GROUP);
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procedure Resolve (var CX_REG:TCONTEXT_REG_GROUP);
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function ColorControl (var CX_REG:TCONTEXT_REG_GROUP):Boolean;
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@ -181,23 +224,86 @@ var
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begin
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node:=allocator.Alloc(SizeOf(t_pm4_node_EventWrite));
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node^.ntype :=ntEventWrite;
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node^.ntype :=ntEventWrite;
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node^.eventType:=eventType;
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add_node(node);
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end;
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procedure t_pm4_stream.EventWriteEop(addr:Pointer;data:QWORD;dataSel,intSel:Byte);
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procedure t_pm4_stream.EventWriteEop(addr:Pointer;data:QWORD;eventType,dataSel,intSel:Byte);
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var
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node:p_pm4_node_EventWriteEop;
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begin
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node:=allocator.Alloc(SizeOf(t_pm4_node_EventWriteEop));
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node^.ntype :=ntEventWriteEop;
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node^.addr :=addr;
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node^.data :=data;
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node^.dataSel:=dataSel;
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node^.intSel :=intSel;
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node^.ntype :=ntEventWriteEop;
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node^.addr :=addr;
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node^.data :=data;
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node^.eventType:=eventType;
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node^.dataSel :=dataSel;
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node^.intSel :=intSel;
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add_node(node);
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end;
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procedure t_pm4_stream.EventWriteEos(addr:Pointer;data:DWORD;eventType,command:Byte);
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var
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node:p_pm4_node_EventWriteEos;
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begin
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node:=allocator.Alloc(SizeOf(t_pm4_node_EventWriteEos));
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node^.ntype :=ntEventWriteEos;
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node^.addr :=addr;
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node^.data :=data;
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node^.eventType:=eventType;
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node^.command :=command;
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add_node(node);
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end;
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procedure t_pm4_stream.DmaData(dstSel:Byte;dst:QWORD;srcSel:Byte;srcOrData:QWORD;numBytes:DWORD;isBlocking:Byte);
|
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var
|
||||
node:p_pm4_node_DmaData;
|
||||
begin
|
||||
node:=allocator.Alloc(SizeOf(t_pm4_node_DmaData));
|
||||
|
||||
node^.ntype :=ntDmaData;
|
||||
node^.dst :=dst;
|
||||
node^.src :=srcOrData;
|
||||
node^.numBytes:=numBytes;
|
||||
node^.srcSel :=srcSel;
|
||||
node^.dstSel :=dstSel;
|
||||
node^.cpSync :=isBlocking;
|
||||
|
||||
add_node(node);
|
||||
end;
|
||||
|
||||
procedure t_pm4_stream.WriteData(dstSel:Byte;dst,src:QWORD;num_dw:Word);
|
||||
var
|
||||
node:p_pm4_node_WriteData;
|
||||
begin
|
||||
node:=allocator.Alloc(SizeOf(t_pm4_node_WriteData));
|
||||
|
||||
node^.ntype :=ntWriteData;
|
||||
node^.dst :=dst;
|
||||
node^.src :=src;
|
||||
node^.num_dw:=num_dw;
|
||||
node^.dstSel:=dstSel;
|
||||
|
||||
add_node(node);
|
||||
end;
|
||||
|
||||
procedure t_pm4_stream.WaitRegMem(pollAddr:QWORD;refValue,mask:DWORD;compareFunc:Byte);
|
||||
var
|
||||
node:p_pm4_node_WaitRegMem;
|
||||
begin
|
||||
node:=allocator.Alloc(SizeOf(t_pm4_node_WaitRegMem));
|
||||
|
||||
node^.ntype :=ntWaitRegMem;
|
||||
node^.pollAddr :=pollAddr;
|
||||
node^.refValue :=refValue;
|
||||
node^.mask :=mask;
|
||||
node^.compareFunc:=compareFunc;
|
||||
|
||||
add_node(node);
|
||||
end;
|
||||
|
|
|
|||
|
|
@ -265,7 +265,7 @@ type
|
|||
PPM4_TYPE_3_HEADER=^PM4_TYPE_3_HEADER;
|
||||
PM4_TYPE_3_HEADER=bitpacked record
|
||||
predicate :bit1; //1
|
||||
shaderType:bit1; //1
|
||||
shaderType:bit1; //1 < 0: Graphics, 1: Compute Shader
|
||||
reserved :bit6; //6
|
||||
opcode :Byte; //8
|
||||
count :bit14; //14
|
||||
|
|
@ -339,10 +339,10 @@ type
|
|||
|
||||
PPM4CMDDRAWPREAMBLE=^TPM4CMDDRAWPREAMBLE;
|
||||
TPM4CMDDRAWPREAMBLE=bitpacked record
|
||||
header :PM4_TYPE_3_HEADER;
|
||||
control1 :TVGT_PRIMITIVE_TYPE; //< writes to VGT_PRIMITIVE_TYPE reg
|
||||
control2 :TIA_MULTI_VGT_PARAM; //< writes to IA_MULTI_VGT_PARAM reg
|
||||
control3 :TVGT_LS_HS_CONFIG; //< writes to VGT_LS_HS_CONFIG reg
|
||||
header :PM4_TYPE_3_HEADER;
|
||||
control1:TVGT_PRIMITIVE_TYPE; //< writes to VGT_PRIMITIVE_TYPE reg
|
||||
control2:TIA_MULTI_VGT_PARAM; //< writes to IA_MULTI_VGT_PARAM reg
|
||||
control3:TVGT_LS_HS_CONFIG; //< writes to VGT_LS_HS_CONFIG reg
|
||||
end;
|
||||
|
||||
// WRITE_DATA DST_SEL and ENGINE definitions
|
||||
|
|
@ -362,8 +362,8 @@ const
|
|||
WRITE_DATA_ENGINE_CE =2;
|
||||
|
||||
type
|
||||
PTPM4CMDWRITEDATA=^TPM4CMDWRITEDATA;
|
||||
TPM4CMDWRITEDATA=packed record
|
||||
PPM4CMDWRITEDATA=^PM4CMDWRITEDATA;
|
||||
PM4CMDWRITEDATA=packed record
|
||||
header :PM4_TYPE_3_HEADER;
|
||||
CONTROL:bitpacked record
|
||||
reserved1 :bit8;
|
||||
|
|
@ -379,8 +379,7 @@ type
|
|||
reserved5 :bit2;
|
||||
engineSel :bit2; ///< engine select
|
||||
end;
|
||||
dstAddrLo:DWORD;
|
||||
dstAddrHi:DWORD;
|
||||
dstAddr:QWORD;
|
||||
data:packed record end;
|
||||
end;
|
||||
|
||||
|
|
@ -410,7 +409,7 @@ type
|
|||
|
||||
eventType :bit6; //00 // < event type written to VGT_EVENT_INITIATOR
|
||||
Reserved1 :bit2; //06
|
||||
EVENT_INDEX :bit4; //08 // < event index [0x5]
|
||||
eventIndex :bit4; //08 // < event index [0x5]
|
||||
|
||||
tcL1VolActionEna:bit1; //12 //(cacheAction & 0x3f) [0x00,0x10,0x33,0x38,0x3B]
|
||||
tcVolActionEna :bit1; //13 //(cacheAction & 0x3f)
|
||||
|
|
@ -442,23 +441,20 @@ type
|
|||
end;
|
||||
|
||||
const
|
||||
EVENT_WRITE_EOS_INDEX_CSDONE_PSDONE=6;
|
||||
|
||||
EVENT_WRITE_EOS_CMD_STORE_APPEND_COUNT_TO_MEMORY=0;
|
||||
EVENT_WRITE_EOS_CMD_STORE_GDS_DATA_TO_MEMORY =1;
|
||||
EVENT_WRITE_EOS_CMD_STORE_32BIT_DATA_TO_MEMORY =2;
|
||||
|
||||
type
|
||||
PTPM4CMDEVENTWRITEEOS=^TPM4CMDEVENTWRITEEOS;
|
||||
TPM4CMDEVENTWRITEEOS=bitpacked record
|
||||
PPM4CMDEVENTWRITEEOS=^PM4CMDEVENTWRITEEOS;
|
||||
PM4CMDEVENTWRITEEOS=bitpacked record
|
||||
header :PM4_TYPE_3_HEADER;
|
||||
eventType :bit6; ///< event type written to VGT_EVENT_INITIATOR
|
||||
eventType :bit6; ///< event type written to VGT_EVENT_INITIATOR (CS_DONE, PS_DONE)
|
||||
reserved1 :bit2; ///< reserved
|
||||
eventIndex :bit4; ///< event index
|
||||
eventIndex :bit4; ///< event index (EVENT_WRITE_INDEX_ANY_EOS_TIMESTAMP)
|
||||
reserved2 :bit20; ///< reserved
|
||||
addressLo :DWORD; ///< low bits of address, must be 4 byte aligned
|
||||
addressHi :bit29; ///< high bits of address
|
||||
command :bit3; ///< command
|
||||
address :bit61; ///< bits of address, must be 4 byte aligned
|
||||
command :bit3; ///< command (EVENT_WRITE_EOS_CMD_*)
|
||||
Case byte of
|
||||
0:(
|
||||
gdsIndex:Word; ///< indexed offset into GDS partition
|
||||
|
|
@ -516,6 +512,7 @@ const
|
|||
//DmaDataDst
|
||||
kDmaDataDstMemory = $0; ///< Destination is a GPU-visible memory address.
|
||||
kDmaDataDstGds = $1; ///< Destination is an offset into Global Data Store (GDS).
|
||||
kDmaDataDstMemoryUsingL2 = $3;
|
||||
kDmaDataDstRegister = $4; ///< Destination is a GPU register offset (auto-increment enabled for multi-register DMAs).
|
||||
kDmaDataDstRegisterNoIncrement = $C; ///< Destination is a GPU register offset (auto-increment disabled for multi-register DMAs).
|
||||
|
||||
|
|
@ -523,14 +520,27 @@ const
|
|||
CP_DMA_ENGINE_ME = 0;
|
||||
CP_DMA_ENGINE_PFP = 1;
|
||||
|
||||
CPDMA_ADDR_SPACE_MEM = 0;
|
||||
CPDMA_ADDR_SPACE_REG = 1;
|
||||
|
||||
//CPDMA_SRC_SEL
|
||||
CPDMA_SRC_SEL_SRC_ADDR = 0;
|
||||
CPDMA_SRC_SEL_GDS = 1;
|
||||
CPDMA_SRC_SEL_DATA = 2;
|
||||
CPDMA_SRC_SEL_SRC_ADDR_USING_L2 = 3;
|
||||
|
||||
//CPDMA_DST_SEL
|
||||
CPDMA_DST_SEL_DST_ADDR = 0;
|
||||
CPDMA_DST_SEL_GDS = 1;
|
||||
CPDMA_DST_SEL_DST_ADDR_USING_L2 = 3;
|
||||
|
||||
type
|
||||
PTPM4DMADATA=^TPM4DMADATA;
|
||||
TPM4DMADATA=packed record
|
||||
PPM4DMADATA=^PM4DMADATA;
|
||||
PM4DMADATA=packed record
|
||||
header:PM4_TYPE_3_HEADER;
|
||||
|
||||
|
||||
Flags1:bitpacked record
|
||||
engine :bit1;
|
||||
engine :bit1; //CP_DMA_ENGINE_PFP, CP_DMA_ENGINE_ME
|
||||
reserved1 :bit11;
|
||||
srcATC :bit1;
|
||||
srcCachePolicy :bit2;
|
||||
|
|
@ -543,21 +553,19 @@ type
|
|||
dstVolatile :bit1;
|
||||
reserved4 :bit1;
|
||||
srcSel :bit2;
|
||||
cpSync :bit1;
|
||||
cpSync :bit1; //Synchronize the transfer (isBlocking)
|
||||
end;
|
||||
|
||||
srcAddrLo:DWORD;
|
||||
srcAddrHi:DWORD;
|
||||
dstAddrLo:DWORD;
|
||||
dstAddrHi:DWORD;
|
||||
srcAddr:QWORD;
|
||||
dstAddr:QWORD;
|
||||
|
||||
Flags2:bitpacked record
|
||||
byteCount :bit21;
|
||||
disWC :bit1;
|
||||
byteCount :bit21; //Number of bytes to copy
|
||||
disWC :bit1; //disable write-confirm
|
||||
srcSwap :bit2;
|
||||
dstSwap :bit2;
|
||||
sas :bit1;
|
||||
das :bit1;
|
||||
sas :bit1; //CPDMA_ADDR_SPACE_MEM, CPDMA_ADDR_SPACE_REG
|
||||
das :bit1; //CPDMA_ADDR_SPACE_MEM, CPDMA_ADDR_SPACE_REG
|
||||
saic :bit1;
|
||||
daic :bit1;
|
||||
rawWait :bit1;
|
||||
|
|
@ -610,30 +618,29 @@ const
|
|||
}
|
||||
|
||||
type
|
||||
PPM4CMDWAITREGMEM=^TPM4CMDWAITREGMEM;
|
||||
TPM4CMDWAITREGMEM=bitpacked record
|
||||
PPM4CMDWAITREGMEM=^PM4CMDWAITREGMEM;
|
||||
PM4CMDWAITREGMEM=bitpacked record
|
||||
header :PM4_TYPE_3_HEADER;
|
||||
compareFunc :bit3; ///< function. WAIT_REG_MEM_FUNC_XXXX
|
||||
reserved1 :bit1; ///< reserved
|
||||
memSpace :bit2; ///< memory space (0 = register, 1 = memory, 2=TC/L2, 3 = reserved)
|
||||
operation__CI :bit2; ///< operation:
|
||||
operation :bit2; ///< operation:
|
||||
///< 00: WAIT_REG_MEM - Wait on Masked Register/Memory value to equal reference value.
|
||||
///< 01: WR_WAIT_WR_REG (PFP only)
|
||||
///< Writes REFERENCE value to POLL_ADDRESS_LO
|
||||
///< Waits for REFERENCE = POLL_ADDRESS_HI
|
||||
///< Write REFERENCE to POLL_ADDRESS_HI.
|
||||
engine :bit2; ///< 0 = ME, 1 = PFP, 2 = CE
|
||||
uncached__VI :bit1; ///< When set the memory read will always use MTYPE 3 (uncached)
|
||||
uncached :bit1; ///< When set the memory read will always use MTYPE 3 (uncached)
|
||||
/// Only applies when executed on MEC (ACE).
|
||||
/// WAIT_REG_MEM on PFP or ME are always uncached.
|
||||
reserved2 :bit13; ///< reserved
|
||||
atc__CI :bit1; ///< ATC steting for MC read transactions
|
||||
cachePolicy__CI :bit2; ///< Reserved for future use of CACHE_POLICY
|
||||
volatile__CI :bit1; ///< Reserved for future use of VOLATILE
|
||||
atc :bit1; ///< ATC steting for MC read transactions
|
||||
cachePolicy :bit2; ///< Reserved for future use of CACHE_POLICY
|
||||
volatile :bit1; ///< Reserved for future use of VOLATILE
|
||||
reserved3 :bit4; ///< reserved
|
||||
|
||||
pollAddressLo :DWORD; ///< lower portion of Address to poll or register offset
|
||||
pollAddressHi :DWORD; ///< high portion of Address to poll, dont care for regs
|
||||
pollAddress :QWORD; ///< Address to poll or register offset
|
||||
reference :DWORD; ///< reference value
|
||||
mask :DWORD; ///< mask for comparison
|
||||
pollInterval :DWORD; ///< interval to wait when issuing new poll requests
|
||||
|
|
|
|||
|
|
@ -5,15 +5,15 @@ unit bittype;
|
|||
interface
|
||||
|
||||
type
|
||||
bit1=0..1;
|
||||
bit2=0..3;
|
||||
bit3=0..7;
|
||||
bit4=0..15;
|
||||
bit5=0..31;
|
||||
bit6=0..63;
|
||||
bit7=0..127;
|
||||
bit8=Byte;
|
||||
bit9=0..511;
|
||||
bit1 =0..1;
|
||||
bit2 =0..3;
|
||||
bit3 =0..7;
|
||||
bit4 =0..15;
|
||||
bit5 =0..31;
|
||||
bit6 =0..63;
|
||||
bit7 =0..127;
|
||||
bit8 =Byte;
|
||||
bit9 =0..511;
|
||||
bit10=0..1023;
|
||||
bit11=0..2047;
|
||||
bit12=0..4095;
|
||||
|
|
@ -36,13 +36,39 @@ type
|
|||
bit29=0..536870911;
|
||||
bit30=0..1073741823;
|
||||
bit31=0..2147483647;
|
||||
bit32=DWORD;
|
||||
bit32=DWord;
|
||||
bit33=0..8589934591;
|
||||
bit34=0..17179869183;
|
||||
bit35=0..34359738367;
|
||||
bit36=0..68719476735;
|
||||
bit37=0..137438953471;
|
||||
bit38=0..274877906943;
|
||||
bit39=0..549755813887;
|
||||
bit40=0..1099511627775;
|
||||
bit41=0..2199023255551;
|
||||
bit42=0..4398046511103;
|
||||
bit43=0..8796093022207;
|
||||
bit44=0..17592186044415;
|
||||
bit45=0..35184372088831;
|
||||
bit46=0..70368744177663;
|
||||
bit47=0..140737488355327;
|
||||
bit48=0..281474976710655;
|
||||
bit64=QWORD;
|
||||
bit49=0..562949953421311;
|
||||
bit50=0..1125899906842623;
|
||||
bit51=0..2251799813685247;
|
||||
bit52=0..4503599627370495;
|
||||
bit53=0..9007199254740991;
|
||||
bit54=0..18014398509481983;
|
||||
bit55=0..36028797018963967;
|
||||
bit56=0..72057594037927935;
|
||||
bit57=0..144115188075855871;
|
||||
bit58=0..288230376151711743;
|
||||
bit59=0..576460752303423487;
|
||||
bit60=0..1152921504606846975;
|
||||
bit61=0..2305843009213693951;
|
||||
bit62=0..4611686018427387903;
|
||||
bit63=0..9223372036854775807;
|
||||
bit64=QWord;
|
||||
|
||||
implementation
|
||||
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ begin
|
|||
begin
|
||||
if pctx^.print_ops then
|
||||
begin
|
||||
Writeln('INDIRECT_BUFFER_CNST (ccb)');
|
||||
Writeln('INDIRECT_BUFFER (ccb) 0x',HexStr(PPM4CMDINDIRECTBUFFER(buff)^.ibBase,10));
|
||||
end;
|
||||
if pm4_ibuf_init(@ibuf,buff,@pm4_parse_ccb) then
|
||||
begin
|
||||
|
|
@ -151,7 +151,7 @@ begin
|
|||
begin
|
||||
if pctx^.print_ops then
|
||||
begin
|
||||
Writeln('INDIRECT_BUFFER (dcb)');
|
||||
Writeln('INDIRECT_BUFFER (dcb) 0x',HexStr(PPM4CMDINDIRECTBUFFER(buff)^.ibBase,10));
|
||||
end;
|
||||
if pm4_ibuf_init(@ibuf,buff,@pm4_parse_dcb) then
|
||||
begin
|
||||
|
|
|
|||
|
|
@ -266,6 +266,12 @@ begin
|
|||
VK_FORMAT_R8G8B8A8_UINT :Result:=4;
|
||||
VK_FORMAT_R8G8B8A8_SINT :Result:=4;
|
||||
|
||||
VK_FORMAT_B8G8R8A8_UNORM :Result:=4;
|
||||
VK_FORMAT_B8G8R8A8_SRGB :Result:=4;
|
||||
VK_FORMAT_B8G8R8A8_SNORM :Result:=4;
|
||||
VK_FORMAT_B8G8R8A8_UINT :Result:=4;
|
||||
VK_FORMAT_B8G8R8A8_SINT :Result:=4;
|
||||
|
||||
VK_FORMAT_R16_UNORM :Result:=2;
|
||||
VK_FORMAT_R16_SNORM :Result:=2;
|
||||
VK_FORMAT_R16_UINT :Result:=2;
|
||||
|
|
|
|||
|
|
@ -407,20 +407,65 @@ begin
|
|||
|
||||
end;
|
||||
|
||||
{
|
||||
Match the physical representation of the final pixel (RGBA)
|
||||
to the output component number in shader export (0123)
|
||||
}
|
||||
|
||||
//SWAP_STD (R=>0)
|
||||
//SWAP_ALT (G=>0)
|
||||
//SWAP_STD_REV (B=>0)
|
||||
//SWAP_ALT_REV (A=>0)
|
||||
|
||||
//SWAP_STD (R=>0, G=>1)
|
||||
//SWAP_ALT (R=>0, A=>1)
|
||||
//SWAP_STD_REV (G=>0, R=>1)
|
||||
//SWAP_ALT_REV (A=>0, R=>1)
|
||||
|
||||
//SWAP_STD (R=>0, G=>1, B=>2)
|
||||
//SWAP_ALT (R=>0, G=>1, A=>2)
|
||||
//SWAP_STD_REV (B=>0, G=>1, R=>2)
|
||||
//SWAP_ALT_REV (A=>0, G=>1, R=>2)
|
||||
|
||||
//SWAP_STD (R=>0, G=>1, B=>2, A=>3)
|
||||
//SWAP_ALT (B=>0, G=>1, R=>2, A=>3).
|
||||
//SWAP_ALT (B=>0, G=>1, R=>2, A=>3)
|
||||
//SWAP_STD_REV (A=>0, B=>1, G=>2, R=>3)
|
||||
//SWAP_ALT_REV (A=>0, R=>1, G=>2, B=>3)
|
||||
end;
|
||||
|
||||
const
|
||||
VK_SWIZZLE_I=ord(VK_COMPONENT_SWIZZLE_IDENTITY);
|
||||
VK_SWIZZLE_Z=ord(VK_COMPONENT_SWIZZLE_ZERO );
|
||||
VK_SWIZZLE_O=ord(VK_COMPONENT_SWIZZLE_ONE );
|
||||
VK_SWIZZLE_R=ord(VK_COMPONENT_SWIZZLE_R );
|
||||
VK_SWIZZLE_G=ord(VK_COMPONENT_SWIZZLE_G );
|
||||
VK_SWIZZLE_B=ord(VK_COMPONENT_SWIZZLE_B );
|
||||
VK_SWIZZLE_A=ord(VK_COMPONENT_SWIZZLE_A );
|
||||
|
||||
shader_swizzle_map:array[1..4,SWAP_STD..SWAP_ALT_REV] of TvDstSel=(
|
||||
(
|
||||
(r:VK_SWIZZLE_R;g:VK_SWIZZLE_O;b:VK_SWIZZLE_O;a:VK_SWIZZLE_O),
|
||||
(r:VK_SWIZZLE_G;g:VK_SWIZZLE_O;b:VK_SWIZZLE_O;a:VK_SWIZZLE_O),
|
||||
(r:VK_SWIZZLE_B;g:VK_SWIZZLE_O;b:VK_SWIZZLE_O;a:VK_SWIZZLE_O),
|
||||
(r:VK_SWIZZLE_A;g:VK_SWIZZLE_O;b:VK_SWIZZLE_O;a:VK_SWIZZLE_O)
|
||||
),(
|
||||
(r:VK_SWIZZLE_R;g:VK_SWIZZLE_G;b:VK_SWIZZLE_O;a:VK_SWIZZLE_O),
|
||||
(r:VK_SWIZZLE_R;g:VK_SWIZZLE_A;b:VK_SWIZZLE_O;a:VK_SWIZZLE_O),
|
||||
(r:VK_SWIZZLE_G;g:VK_SWIZZLE_R;b:VK_SWIZZLE_O;a:VK_SWIZZLE_O),
|
||||
(r:VK_SWIZZLE_A;g:VK_SWIZZLE_R;b:VK_SWIZZLE_O;a:VK_SWIZZLE_O)
|
||||
),(
|
||||
(r:VK_SWIZZLE_R;g:VK_SWIZZLE_G;b:VK_SWIZZLE_B;a:VK_SWIZZLE_O),
|
||||
(r:VK_SWIZZLE_R;g:VK_SWIZZLE_G;b:VK_SWIZZLE_A;a:VK_SWIZZLE_O),
|
||||
(r:VK_SWIZZLE_B;g:VK_SWIZZLE_G;b:VK_SWIZZLE_R;a:VK_SWIZZLE_O),
|
||||
(r:VK_SWIZZLE_A;g:VK_SWIZZLE_G;b:VK_SWIZZLE_R;a:VK_SWIZZLE_O)
|
||||
),(
|
||||
(r:VK_SWIZZLE_R;g:VK_SWIZZLE_G;b:VK_SWIZZLE_B;a:VK_SWIZZLE_A),
|
||||
(r:VK_SWIZZLE_B;g:VK_SWIZZLE_G;b:VK_SWIZZLE_R;a:VK_SWIZZLE_A),
|
||||
(r:VK_SWIZZLE_A;g:VK_SWIZZLE_B;b:VK_SWIZZLE_G;a:VK_SWIZZLE_R),
|
||||
(r:VK_SWIZZLE_A;g:VK_SWIZZLE_R;b:VK_SWIZZLE_G;a:VK_SWIZZLE_B)
|
||||
)
|
||||
);
|
||||
|
||||
Function TGPU_REGS.GET_RT_BLEND(i:Byte):TVkPipelineColorBlendAttachmentState; //0..7
|
||||
var
|
||||
RENDER_TARGET:TRENDER_TARGET;
|
||||
|
|
@ -749,10 +794,6 @@ begin
|
|||
|
||||
end;
|
||||
|
||||
//
|
||||
//FORMAT :=RENDER_TARGET[i].INFO.FORMAT;
|
||||
//NUMBER_TYPE:=RENDER_TARGET[i].INFO.NUMBER_TYPE;
|
||||
|
||||
Function TGPU_REGS.GET_RT_INFO(i:Byte):TRT_INFO; //0..7
|
||||
var
|
||||
RENDER_TARGET:TRENDER_TARGET;
|
||||
|
|
@ -1708,14 +1749,14 @@ end;
|
|||
function _get_dst_sel_swizzle(b:Byte):Byte;
|
||||
begin
|
||||
Case b of
|
||||
0:Result:=ord(VK_COMPONENT_SWIZZLE_ZERO);
|
||||
1:Result:=ord(VK_COMPONENT_SWIZZLE_ONE);
|
||||
4:Result:=ord(VK_COMPONENT_SWIZZLE_R);
|
||||
5:Result:=ord(VK_COMPONENT_SWIZZLE_G);
|
||||
6:Result:=ord(VK_COMPONENT_SWIZZLE_B);
|
||||
7:Result:=ord(VK_COMPONENT_SWIZZLE_A);
|
||||
0:Result:=VK_SWIZZLE_Z;
|
||||
1:Result:=VK_SWIZZLE_O;
|
||||
4:Result:=VK_SWIZZLE_R;
|
||||
5:Result:=VK_SWIZZLE_G;
|
||||
6:Result:=VK_SWIZZLE_B;
|
||||
7:Result:=VK_SWIZZLE_A;
|
||||
else
|
||||
Result:=ord(VK_COMPONENT_SWIZZLE_IDENTITY);
|
||||
Result:=VK_SWIZZLE_I;
|
||||
end;
|
||||
end;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue