mirror of https://github.com/red-prig/fpPS4.git
VOP2?40
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@ -38,6 +38,7 @@ type
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procedure emit_V_BCNT_U32_B32;
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procedure emit_V_MMX(OpId:DWORD;rtype:TsrDataType);
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procedure emit_V_LDEXP_F32;
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procedure emit_V_ADDC_U32;
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end;
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implementation
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@ -423,6 +424,39 @@ begin
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Op2(Op.OpFMul,dtFloat32,dst,src[0],src[1]);
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end;
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procedure TEmit_VOP2.emit_V_ADDC_U32;
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Var
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dst,car:PsrRegSlot;
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src:array[0..2] of PsrRegNode;
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exc:PsrRegNode;
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begin
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dst:=get_vdst8(FSPI.VOP2.VDST);
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car:=get_vcc0;
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src[0]:=fetch_ssrc9(FSPI.VOP2.SRC0 ,dtUint32);
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src[1]:=fetch_vsrc8(FSPI.VOP2.VSRC1,dtUint32);
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src[2]:=MakeRead(get_vcc0,dtUInt32);
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src[2]:=OpAndTo(src[2],1);
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src[2]^.PrepType(ord(dtUInt32));
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OpIAddExt(dst,car,src[0],src[1]); //src0+src1
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src[0]:=MakeRead(dst,dtUInt32);
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src[1]:=MakeRead(car,dtUInt32); //save car1
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OpIAddExt(dst,car,src[0],src[2]); //(src0+src1)+src2
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src[0]:=MakeRead(car,dtUInt32);
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OpBitwiseOr(car,src[1],src[0]); //car1 or car2
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src[0]:=MakeRead(car,dtUInt32);
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exc:=MakeRead(get_exec0,dtUnknow);
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OpBitwiseAnd(car,src[0],exc); //carry_out & EXEC
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end;
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procedure TEmit_VOP2.emit_VOP2;
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begin
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@ -479,6 +513,8 @@ begin
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V_LDEXP_F32: emit_V_LDEXP_F32;
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V_ADDC_U32: emit_V_ADDC_U32;
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else
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Assert(false,'VOP2?'+IntToStr(FSPI.VOP2.OP));
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end;
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