From 3dfcab813e0bce55664826ed98b37d35493e17df Mon Sep 17 00:00:00 2001
From: red-prig <vdpasha@mail.ru>
Date: Wed, 5 Apr 2023 18:23:38 +0300
Subject: [PATCH] VOP1?43/bugfixes

---
 spirv/emit_post.pas    |  2 ++
 spirv/emit_post_op.pas | 56 ++++++++++++++++++++++++++++++++++++++++++
 spirv/emit_vop1.pas    |  1 +
 spirv/emit_vop3.pas    |  1 +
 4 files changed, 60 insertions(+)

diff --git a/spirv/emit_post.pas b/spirv/emit_post.pas
index 63166148..23fde86d 100644
--- a/spirv/emit_post.pas
+++ b/spirv/emit_post.pas
@@ -433,6 +433,8 @@ begin
   Op.OpSelect            :Result:=EnumLineRegs(@RegSTStrict,node);
   Op.OpIAddCarry         ,
   Op.OpISubBorrow        ,
+  Op.OpUMulExtended      ,
+  Op.OpSMulExtended      ,
   Op.OpCompositeConstruct:Result:=EnumLineRegs(@RegVTStrict,node);
   else;
  end;
diff --git a/spirv/emit_post_op.pas b/spirv/emit_post_op.pas
index bb99836d..23ff11aa 100644
--- a/spirv/emit_post_op.pas
+++ b/spirv/emit_post_op.pas
@@ -1088,6 +1088,27 @@ var
  dtype:TsrDataType;
  dst:PsrRegNode;
  src:array[0..1] of PsrRegNode;
+
+ cst:array[0..1] of PsrConst;
+
+ pLine:PSpirvOp;
+
+ procedure _SetConst(dtype:TsrDataType;value:QWORD);
+ begin
+  dst^.pWriter:=ConstList.Fetch(dtype,value);
+  node^.mark_not_used;
+  node^.pDst:=nil;
+  Inc(Result);
+ end;
+
+ procedure _SetReg(src:PsrRegNode);
+ begin
+  dst^.pWriter:=src;
+  node^.mark_not_used;
+  node^.pDst:=nil;
+  Inc(Result);
+ end;
+
 begin
  Result:=0;
  dst:=node^.pDst^.AsType(ntReg);
@@ -1096,6 +1117,41 @@ begin
 
  if (dst=nil) or (src[0]=nil) or (src[1]=nil) then Exit;
 
+ cst[0]:=RegDown(src[0])^.AsConst;
+ cst[1]:=RegDown(src[1])^.AsConst;
+ if (cst[0]<>nil) and (cst[1]<>nil) then
+ begin
+
+  if (cst[0]^.GetData=cst[1]^.GetData) then
+  begin
+   _SetConst(dst^.dtype,cst[0]^.GetData);
+   Exit;
+  end;
+
+  if (dst^.dtype=dtBool) and
+     (cst[0]^.dtype=dtBool) and
+     (cst[1]^.dtype=dtBool) then
+  begin
+   if (cst[0]^.AsBool=True) and (cst[1]^.AsBool=False) then
+   begin
+    src[0]:=node^.ParamNode(0)^.AsReg;
+    _SetReg(src[0]);
+    Exit;
+   end else
+   if (cst[0]^.AsBool=False) and (cst[1]^.AsBool=True) then
+   begin
+    src[0]:=node^.ParamNode(0)^.AsReg;
+    pLine:=src[0]^.pLine;
+    src[1]:=OpNotTo(src[0],@pLine);
+    src[1]^.PrepType(ord(dtBool));
+    _SetReg(src[1]);
+    Exit;
+   end;
+  end;
+
+
+ end;
+
  dtype:=LazyType3(dst^.dtype,src[0]^.dtype,src[1]^.dtype);
 
  if (node^.pType^.dtype<>dtype) then
diff --git a/spirv/emit_vop1.pas b/spirv/emit_vop1.pas
index 9f7a2d8a..0d14da18 100644
--- a/spirv/emit_vop1.pas
+++ b/spirv/emit_vop1.pas
@@ -274,6 +274,7 @@ begin
   V_COS_F32  : emit_V_SIN_COS(GlslOp.Cos);
 
   V_RCP_F32  : emit_V_RCP_F32;
+  V_RCP_IFLAG_F32: emit_V_RCP_F32;
 
   V_FFBL_B32 : emit_V_FFBL_B32;
 
diff --git a/spirv/emit_vop3.pas b/spirv/emit_vop3.pas
index d6158252..52d5106c 100644
--- a/spirv/emit_vop3.pas
+++ b/spirv/emit_vop3.pas
@@ -1212,6 +1212,7 @@ begin
   384+V_COS_F32  : emit_V_SIN_COS(GlslOp.Cos);
 
   384+V_RCP_F32  : emit_V_RCP_F32;
+  384+V_RCP_IFLAG_F32: emit_V_RCP_F32;
 
   else
    Assert(false,'VOP3a?'+IntToStr(FSPI.VOP3a.OP));