diff --git a/.gitignore b/.gitignore index fb01256f..d496f0a1 100644 --- a/.gitignore +++ b/.gitignore @@ -12,9 +12,11 @@ *.prx *.sprx *.dump +*.h link.res lib/ backup/ shader_dump/* avplayer_dump/* savedata/* +tools/vop_generator/vnode_if.* diff --git a/sys/fs/deadfs/dead_vnops.pas b/sys/fs/deadfs/dead_vnops.pas index 7a89d512..af0e002f 100644 --- a/sys/fs/deadfs/dead_vnops.pas +++ b/sys/fs/deadfs/dead_vnops.pas @@ -6,7 +6,7 @@ unit dead_vnops; interface uses - vfs_vnode, + vnode, vfs_default, vnode_if; diff --git a/sys/fs/devfs/devfs.pas b/sys/fs/devfs/devfs.pas index 1b35f3ff..99926005 100644 --- a/sys/fs/devfs/devfs.pas +++ b/sys/fs/devfs/devfs.pas @@ -10,7 +10,7 @@ uses mqueue, vfile, vdirent, - vfs_vnode, + vnode, vmount, time, kern_conf, diff --git a/sys/fs/devfs/devfs_devs.pas b/sys/fs/devfs/devfs_devs.pas index c9182810..5b0bfb9d 100644 --- a/sys/fs/devfs/devfs_devs.pas +++ b/sys/fs/devfs/devfs_devs.pas @@ -41,7 +41,7 @@ implementation uses time, vdirent, - vfs_vnode, + vnode, kern_mtx, kern_sx, vfs_vnops, @@ -145,7 +145,11 @@ begin end; break; end; - Assert((de=nil) or ((de^.de_flags and DE_DOOMED)=0),'devfs_find: Exiting a doomed entry'); + + if (de<>nil) then + begin + Assert((de^.de_flags and DE_DOOMED)=0,'devfs_find: Exiting a doomed entry'); + end; Exit(de); end; diff --git a/sys/fs/devfs/devfs_vfsops.pas b/sys/fs/devfs/devfs_vfsops.pas index 6723db01..42372215 100644 --- a/sys/fs/devfs/devfs_vfsops.pas +++ b/sys/fs/devfs/devfs_vfsops.pas @@ -6,7 +6,7 @@ unit devfs_vfsops; interface uses - vfs_vnode, + vnode, vmount, devfs, kern_id; @@ -41,8 +41,6 @@ const vfs_extattrctl :nil; vfs_sysctl :nil; vfs_susp_clean :nil; - vfs_reclaim_lowervp:nil; - vfs_unlink_lowervp :nil; ); var diff --git a/sys/fs/devfs/devfs_vnops.pas b/sys/fs/devfs/devfs_vnops.pas index d210cde1..3861d707 100644 --- a/sys/fs/devfs/devfs_vnops.pas +++ b/sys/fs/devfs/devfs_vnops.pas @@ -16,7 +16,7 @@ uses vstat, vuio, vfcntl, - vfs_vnode, + vnode, vnamei, vnode_if, vfs_default, @@ -71,7 +71,7 @@ function devfs_stat_f(fp:p_file;sb:p_stat):Integer; function devfs_symlink(ap:p_vop_symlink_args):Integer; function devfs_truncate_f(fp:p_file;length:Int64):Integer; function devfs_write_f(fp:p_file;uio:p_uio;flags:Integer):Integer; -function dev2udev(x:p_cdev):DWORD; +function dev2udev(x:p_cdev):Integer; const devfs_vnodeops:vop_vector=( @@ -370,6 +370,7 @@ begin sx_xunlock(@dmp^.dm_lock); vn_lock(vp, locked or LK_RETRY); sx_xlock(@dmp^.dm_lock); + if DEVFS_DMP_DROP(dmp) then begin sx_xunlock(@dmp^.dm_lock); @@ -640,8 +641,13 @@ loop: Inc(dev^.si_usecount,vp^.v_usecount); { Special casing of ttys for deadfs. Probably redundant. } dsw:=dev^.si_devsw; - if (dsw<>nil) and ((dsw^.d_flags and D_TTY)<>0) then + + if (dsw<>nil) then + if ((dsw^.d_flags and D_TTY)<>0) then + begin vp^.v_vflag:=vp^.v_vflag or VV_ISTTY; + end; + dev_unlock(); VI_UNLOCK(vp); if ((dev^.si_flags and SI_ETERNAL)<>0) then @@ -739,7 +745,8 @@ begin } oldvp:=nil; //sx_xlock(@proctree_lock); - //if (td<>nil) and (vp=td^.td_proc^.p_session^.s_ttyvp) then + //if (td<>nil) then + //if (vp=td^.td_proc^.p_session^.s_ttyvp) then //begin // SESS_LOCK(td^.td_proc^.p_session); // VI_LOCK(vp); @@ -1041,6 +1048,8 @@ begin end; function devfs_lookupx(ap:p_vop_lookup_args;dm_unlock:PInteger):Integer; +label + _or; var td:p_kthread; cnp:p_componentname; @@ -1157,15 +1166,23 @@ begin dev_lock(); dde:=@cdev2priv(cdev)^.cdp_dirents[dmp^.dm_idx]; - if (dde<>nil) and (dde^<>nil) then + + if (dde<>nil) then + if (dde^<>nil) then + begin de:=dde^; + end; + dev_unlock(); dev_rel(cdev); break; end; - if (de=nil) or ((de^.de_flags and DE_WHITEOUT)<>0) then + if (de=nil) then goto _or; + + if ((de^.de_flags and DE_WHITEOUT)<>0) then begin + _or: if ((nameiop=CREATE) or (nameiop=RENAME)) and ((flags and (LOCKPARENT or WANTPARENT))<>0) and ((flags and ISLASTCN)<>0) then @@ -1943,7 +1960,7 @@ begin Exit(error); end; -function dev2udev(x:p_cdev):DWORD; +function dev2udev(x:p_cdev):Integer; begin if (x=nil) then Exit(NODEV); diff --git a/sys/fs/fdescfs/fdesc_vfsops.pas b/sys/fs/fdescfs/fdesc_vfsops.pas index b7381d04..ebe6a717 100644 --- a/sys/fs/fdescfs/fdesc_vfsops.pas +++ b/sys/fs/fdescfs/fdesc_vfsops.pas @@ -8,8 +8,8 @@ interface uses vmount, vfs_mount, - vfs_vnode, - fdesc; + vnode, + fdescfs; { * /dev/fd Filesystem @@ -37,8 +37,6 @@ const vfs_extattrctl :nil; vfs_sysctl :nil; vfs_susp_clean :nil; - vfs_reclaim_lowervp:nil; - vfs_unlink_lowervp :nil; ); //VFS_SET(fdesc_vfsops, fdescfs, VFCF_SYNTHETIC); diff --git a/sys/fs/fdescfs/fdesc_vnops.pas b/sys/fs/fdescfs/fdesc_vnops.pas index 8ead4c5e..4eeb4159 100644 --- a/sys/fs/fdescfs/fdesc_vnops.pas +++ b/sys/fs/fdescfs/fdesc_vnops.pas @@ -8,10 +8,10 @@ interface uses mqueue, vmount, - vfs_vnode, + vnode, vfs_default, vnode_if, - fdesc; + fdescfs; { * /dev/fd Filesystem @@ -156,6 +156,7 @@ end; function fdesc_allocvp(ftype:fdntype;fd_fd,ix:Integer;mp:p_mount;vpp:pp_vnode):Integer; label + _or, loop; var fmp:p_fdescmount; @@ -174,7 +175,14 @@ loop: * protected by the hashmtx. } fmp:=p_fdescmount(mp^.mnt_data); - if (fmp=nil) or ((fmp^.flags and FMNT_UNMOUNTF)<>0) then + + if (fmp=nil) then + begin + mtx_unlock(fdesc_hashmtx); + Exit(-1); + end; + + if ((fmp^.flags and FMNT_UNMOUNTF)<>0) then begin mtx_unlock(fdesc_hashmtx); Exit(-1); @@ -230,8 +238,12 @@ loop: * protected by the hashmtx. } fmp:=p_fdescmount(mp^.mnt_data); - if (fmp=nil) or ((fmp^.flags and FMNT_UNMOUNTF)<>0) then + + if (fmp=nil) then goto _or; + + if ((fmp^.flags and FMNT_UNMOUNTF)<>0) then begin + _or: mtx_unlock(fdesc_hashmtx); vgone(vp); vput(vp); diff --git a/sys/fs/fdescfs/fdesc.pas b/sys/fs/fdescfs/fdescfs.pas similarity index 98% rename from sys/fs/fdescfs/fdesc.pas rename to sys/fs/fdescfs/fdescfs.pas index e76a4e5f..0d2b121e 100644 --- a/sys/fs/fdescfs/fdesc.pas +++ b/sys/fs/fdescfs/fdescfs.pas @@ -1,4 +1,4 @@ -unit fdesc; +unit fdescfs; {$mode ObjFPC}{$H+} {$CALLING SysV_ABI_CDecl} @@ -8,7 +8,7 @@ interface uses mqueue, vmount, - vfs_vnode, + vnode, kern_mtx, subr_hash; diff --git a/sys/fs/nullfs/null_subr.pas b/sys/fs/nullfs/null_subr.pas new file mode 100644 index 00000000..5c3d864f --- /dev/null +++ b/sys/fs/nullfs/null_subr.pas @@ -0,0 +1,280 @@ +unit null_subr; + +{$mode ObjFPC}{$H+} +{$CALLING SysV_ABI_CDecl} + +interface + +uses + mqueue, + vmount, + vnode, + nullfs, + kern_mtx, + subr_hash; + +{ + * null layer cache: + * Each cache entry holds a reference to the lower vnode + * along with a pointer to the alias vnode. When an + * entry is added the lower vnode is VREF'd. When the + * alias is removed the lower vnode is vrele'd. + } +function nullfs_init(vfsp:p_vfsconf):Integer; +function nullfs_uninit(vfsp:p_vfsconf):Integer; + +function null_hashget(mp:p_mount;lowervp:p_vnode):p_vnode; +function null_hashins(mp:p_mount;xp:p_null_node):p_vnode; +procedure null_destroy_proto(vp:p_vnode;xp:Pointer); +procedure null_insmntque_dtr(vp:p_vnode;xp:Pointer); +function null_nodeget(mp:p_mount;lowervp:p_vnode;vpp:pp_vnode):Integer; +procedure null_hashrem(xp:p_null_node); + + +type + p_null_node_hashhead=^t_null_node_hashhead; + t_null_node_hashhead=LIST_HEAD; //null_node + +var + null_node_hashtbl:p_null_node_hashhead=nil; + null_hash_mask :QWORD=0; + null_hashmtx:mtx; + +implementation + +uses + errno, + vfs_subr, + vfs_vnops, + dead_vnops, + vnode_if, + null_vnops; + +function vfs_hash_index(vp:p_vnode):DWORD; +begin + Result:=(vp^.v_hash + p_mount(vp^.v_mount)^.mnt_hashseed); +end; + +function NULL_NHASH(vp:p_vnode):Pointer; +begin + Result:=@null_node_hashtbl[vfs_hash_index(vp) and null_hash_mask]; +end; + +{ + * Initialise cache headers + } +function nullfs_init(vfsp:p_vfsconf):Integer; +const + desiredvnodes=64; +begin + null_node_hashtbl:=hashinit(desiredvnodes, @null_hash_mask); + mtx_init(null_hashmtx, 'nullhs'); + Exit(0); +end; + +function nullfs_uninit(vfsp:p_vfsconf):Integer; +begin + mtx_destroy(null_hashmtx); + hashdestroy(null_node_hashtbl, null_hash_mask); + Exit(0); +end; + +{ + * Exita VREF'ed alias for lower vnode if already exists, else 0. + * Lower vnode should be locked on entry and will be left locked on exit. + } +function null_hashget(mp:p_mount;lowervp:p_vnode):p_vnode; +var + hd:Pointer; + a:p_null_node; + vp:p_vnode; +begin + ASSERT_VOP_LOCKED(lowervp, 'nil_hashget'); + + { + * Find hash base, and then search the (two-way) linked + * list looking for a nil_node structure which is referencing + * the lower vnode. If found, the increment the nil_node + * reference count (but NOT the lower vnode's VREF counter). + } + hd:=NULL_NHASH(lowervp); + mtx_lock(null_hashmtx); + + a:=LIST_FIRST(hd); + while (a<>nil) do + begin + if (a^.null_lowervp=lowervp) and (NULLTOV(a)^.v_mount=mp) then + begin + { + * Since we have the lower node locked the nilfs + * node can not be in the process of recycling. If + * it had been recycled before we grabed the lower + * lock it would not have been found on the hash. + } + vp:=NULLTOV(a); + vref(vp); + mtx_unlock(null_hashmtx); + Exit(vp); + end; + a:=LIST_NEXT(a,@a^.null_hash); + end; + mtx_unlock(null_hashmtx); + Exit(nil); +end; + +{ + * Act like nil_hashget, but add passed null_node to hash if no existing + * node found. + } +function null_hashins(mp:p_mount;xp:p_null_node):p_vnode; +var + hd:Pointer; + oxp:p_null_node; + ovp:p_vnode; +begin + hd:=NULL_NHASH(xp^.null_lowervp); + mtx_lock(null_hashmtx); + oxp:=LIST_FIRST(hd); + while (oxp<>nil) do + begin + if (oxp^.null_lowervp=xp^.null_lowervp) and + (NULLTOV(oxp)^.v_mount=mp) then + begin + { + * See nil_hashget for a description of this + * operation. + } + ovp:=NULLTOV(oxp); + vref(ovp); + mtx_unlock(null_hashmtx); + Exit(ovp); + end; + oxp:=LIST_NEXT(oxp,@oxp^.null_hash); + end; + LIST_INSERT_HEAD(hd, xp,@xp^.null_hash); + mtx_unlock(null_hashmtx); + Exit(nil); +end; + +procedure null_destroy_proto(vp:p_vnode;xp:Pointer); +begin + mtx_lock(vp^.v_lock); + //lockmgr(@vp^.v_lock, LK_EXCLUSIVE, nil); + VI_LOCK(vp); + vp^.v_data :=nil; + vp^.v_vnlock:=@vp^.v_lock; + vp^.v_op :=@dead_vnodeops; + VI_UNLOCK(vp); + vgone(vp); + vput(vp); + + FreeMem(xp); +end; + +procedure null_insmntque_dtr(vp:p_vnode;xp:Pointer); +begin + vput(p_null_node(xp)^.null_lowervp); + null_destroy_proto(vp, xp); +end; + +{ + * Make a new or get existing nilfs node. + * Vp is the alias vnode, lowervp is the lower vnode. + * + * The lowervp assumed to be locked and having 'spare' reference. This routine + * vrele lowervp if nilfs node was taken from hash. Otherwise it 'transfers' + * the caller's 'spare' reference to created nilfs vnode. + } +function null_nodeget(mp:p_mount;lowervp:p_vnode;vpp:pp_vnode):Integer; +var + xp:p_null_node; + vp:p_vnode; + error:Integer; +begin + ASSERT_VOP_LOCKED(lowervp, 'lowervp'); + Assert(lowervp^.v_usecount >= 1,'Unreferenced vnode %p'); + + { Lookup the hash firstly. } + vpp^:=null_hashget(mp, lowervp); + if (vpp^<>nil) then + begin + vrele(lowervp); + Exit(0); + end; + + { + * The insmntque1() call below requires the exclusive lock on + * the nilfs vnode. Upgrade the lock now if hash failed to + * provide ready to use vnode. + } + if (VOP_ISLOCKED(lowervp)<>LK_EXCLUSIVE) then + begin + Assert((MOUNTTONULLMOUNT(mp)^.nullm_flags and NULLM_CACHE)<>0,'lowervp %p is not excl locked and cache is disabled'); + vn_lock(lowervp, LK_UPGRADE or LK_RETRY); + if ((lowervp^.v_iflag and VI_DOOMED)<>0) then + begin + vput(lowervp); + Exit(ENOENT); + end; + end; + + { + * We do not serialize vnode creation, instead we will check for + * duplicates later, when adding new vnode to hash. + * Note that duplicate can only appear in hash if the lowervp is + * locked LK_SHARED. + * + * Do the MALLOC before the getnewvnode since doing so afterward + * might cause a bogus v_data pointer to get dereferenced + * elsewhere if MALLOC should block. + } + xp:=AllocMem(sizeof(t_null_node)); + + error:=getnewvnode('nil', mp, @null_vnodeops, @vp); + if (error<>0) then + begin + vput(lowervp); + FreeMem(xp); + Exit(error); + end; + + xp^.null_vnode :=vp; + xp^.null_lowervp:=lowervp; + xp^.null_flags :=0; + + vp^.v_type :=lowervp^.v_type; + vp^.v_data :=xp; + vp^.v_vnlock:=lowervp^.v_vnlock; + + error:=insmntque1(vp, mp, @null_insmntque_dtr, xp); + if (error<>0) then + Exit(error); + { + * Atomically insert our new node into the hash or vget existing + * if someone else has beaten us to it. + } + vpp^:=null_hashins(mp, xp); + if (vpp^<>nil) then + begin + vrele(lowervp); + null_destroy_proto(vp, xp); + Exit(0); + end; + vpp^:=vp; + + Exit(0); +end; + +{ + * Remove node from hash. + } +procedure null_hashrem(xp:p_null_node); +begin + mtx_lock(null_hashmtx); + LIST_REMOVE(xp,@xp^.null_hash); + mtx_unlock(null_hashmtx); +end; + + +end. + diff --git a/sys/fs/nullfs/null_vfsops.pas b/sys/fs/nullfs/null_vfsops.pas new file mode 100644 index 00000000..bf3abd57 --- /dev/null +++ b/sys/fs/nullfs/null_vfsops.pas @@ -0,0 +1,350 @@ +unit null_vfsops; + +{$mode ObjFPC}{$H+} +{$CALLING SysV_ABI_CDecl} + +interface + +uses + mqueue, + vnode, + vmount, + nullfs, + null_subr; + +function nullfs_mount(mp:p_mount):Integer; +function nullfs_unmount(mp:p_mount;mntflags:Integer):Integer; +function nullfs_root(mp:p_mount;flags:Integer;vpp:pp_vnode):Integer; +function nullfs_quotactl(mp:p_mount;cmd,uid:Integer;arg:Pointer):Integer; +function nullfs_statfs(mp:p_mount;sbp:p_statfs):Integer; +function nullfs_sync(mp:p_mount;waitfor:Integer):Integer; +function nullfs_vget(mp:p_mount;ino:DWORD;flags:Integer;vpp:pp_vnode):Integer; +function nullfs_fhtovp(mp:p_mount;fidp:p_fid;flags:Integer;vpp:pp_vnode):Integer; +function nullfs_extattrctl(mp:p_mount;cmd:Integer;filename_vp:p_vnode;namespace:Integer;attrname:PChar):Integer; + +const + _null_vfsops:vfsops=( + vfs_mount :@nullfs_mount; + vfs_cmount :nil; + vfs_unmount :@nullfs_unmount; + vfs_root :@nullfs_root; + vfs_quotactl :@nullfs_quotactl; + vfs_statfs :@nullfs_statfs; + vfs_sync :@nullfs_sync; + vfs_vget :@nullfs_vget; + vfs_fhtovp :@nullfs_fhtovp; + vfs_checkexp :nil; + vfs_init :@nullfs_init; + vfs_uninit :@nullfs_uninit; + vfs_extattrctl :@nullfs_extattrctl; + vfs_sysctl :nil; + vfs_susp_clean :nil; + ); + + //VFS_SET(null_vfsops, nullfs, VFCF_LOOPBACK or VFCF_JAIL); + nullfs_vfsconf:vfsconf=( + vfc_version :VFS_VERSION; + vfc_name :'nullfs'; + vfc_vfsops :@_null_vfsops; + vfc_typenum :-1; + vfc_refcount:0; + vfc_flags :VFCF_LOOPBACK or VFCF_JAIL; + vfc_opts :nil; + vfc_list :(tqe_next:nil;tqe_prev:nil) + ); + +implementation + +uses + errno, + vuio, + vnamei, + vfs_mount, + vfs_lookup, + vfs_vnops, + vfs_subr, + vnode_if, + null_vnops, + kern_thr, + kern_mtx, + kern_synch; + +{ + * Mount null layer + } +function nullfs_mount(mp:p_mount):Integer; +var + error:Integer; + lowerrootvp,vp,nullm_rootvp:p_vnode; + xmp:p_null_mount; + target:PChar; + isvnunlocked,len:Integer; + nd:t_nameidata; + ndp:p_nameidata; +begin + error:=0; + isvnunlocked:=0; + ndp:=@nd; + + //if (prison_allow(td^.td_ucred, PR_ALLOW_MOUNT_NULLFS)=0) then + // Exit(EPERM); + + //if ((mp^.mnt_flag and MNT_ROOTFS)<>0) then + // Exit(EOPNOTSUPP); + + { + * Update is a no-op + } + if ((mp^.mnt_flag and MNT_UPDATE)<>0) then + begin + { + * Only support update mounts for NFS export. + } + if (vfs_flagopt(mp^.mnt_optnew, 'export', nil, 0)<>0) then + Exit(0) + else + Exit(EOPNOTSUPP); + end; + + { + * Get argument + } + error:=vfs_getopt(mp^.mnt_optnew, {'target'} 'fspath', @target, @len); + if (error<>0) or (target[len - 1]<>#0) then + Exit(EINVAL); + + { + * Unlock lower node to avoid possible deadlock. + } + if (mp^.mnt_vnodecovered^.v_op=@null_vnodeops) and + (VOP_ISLOCKED(mp^.mnt_vnodecovered)=LK_EXCLUSIVE) then + begin + VOP_UNLOCK(mp^.mnt_vnodecovered, 0); + isvnunlocked:=1; + end; + { + * Find lower node + } + NDINIT(ndp, LOOKUP, FOLLOW or LOCKLEAF, UIO_SYSSPACE, target, curkthread); + error:=nd_namei(ndp); + + { + * Re-lock vnode. + * XXXKIB This is deadlock-prone as well. + } + if (isvnunlocked<>0) then + vn_lock(mp^.mnt_vnodecovered, LK_EXCLUSIVE or LK_RETRY); + + if (error<>0) then + Exit(error); + + NDFREE(ndp, NDF_ONLY_PNBUF); + + { + * Sanity check on lower vnode + } + lowerrootvp:=ndp^.ni_vp; + + { + * Check multi null mount to avoid `lock against myself' panic. + } + if (lowerrootvp=VTONULL(mp^.mnt_vnodecovered)^.null_lowervp) then + begin + vput(lowerrootvp); + Exit(EDEADLK); + end; + + xmp:=AllocMem(sizeof(t_null_mount)); + + { + * Save reference to underlying FS + } + xmp^.nullm_vfs:=lowerrootvp^.v_mount; + + { + * Save reference. Each mount also holds + * a reference on the root vnode. + } + error:=null_nodeget(mp, lowerrootvp, @vp); + { + * Make sure the node alias worked + } + if (error<>0) then + begin + FreeMem(xmp); + Exit(error); + end; + + { + * Keep a held reference to the root vnode. + * It is vrele'd in nullfs_unmount. + } + nullm_rootvp:=vp; + nullm_rootvp^.v_vflag:=nullm_rootvp^.v_vflag or VV_ROOT; + xmp^.nullm_rootvp:=nullm_rootvp; + + { + * Unlock the node (either the lower or the alias) + } + VOP_UNLOCK(vp, 0); + + if ((p_mount(NULLVPTOLOWERVP(nullm_rootvp)^.v_mount)^.mnt_flag and MNT_LOCAL)<>0) then + begin + MNT_ILOCK(mp); + mp^.mnt_flag:=mp^.mnt_flag or MNT_LOCAL; + MNT_IUNLOCK(mp); + end; + + xmp^.nullm_flags:=xmp^.nullm_flags or NULLM_CACHE; + + if (vfs_getopt(mp^.mnt_optnew, 'nocache', nil, nil)=0) then + xmp^.nullm_flags:=xmp^.nullm_flags and (not NULLM_CACHE); + + MNT_ILOCK(mp); + if ((xmp^.nullm_flags and NULLM_CACHE)<>0) then + begin + mp^.mnt_kern_flag:=mp^.mnt_kern_flag or + (p_mount(lowerrootvp^.v_mount)^.mnt_kern_flag and (MNTK_MPSAFE or MNTK_SHARED_WRITES or MNTK_LOOKUP_SHARED or MNTK_EXTENDED_SHARED)); + end; + mp^.mnt_kern_flag:=mp^.mnt_kern_flag or MNTK_LOOKUP_EXCL_DOTDOT; + MNT_IUNLOCK(mp); + mp^.mnt_data:= xmp; + vfs_getnewfsid(mp); + if ((xmp^.nullm_flags and NULLM_CACHE)<>0) then + begin + MNT_ILOCK(xmp^.nullm_vfs); + TAILQ_INSERT_TAIL(@xmp^.nullm_vfs^.mnt_uppers,mp,@mp^.mnt_upper_link); + MNT_IUNLOCK(xmp^.nullm_vfs); + end; + + vfs_mountedfrom(mp, target); + + Exit(0); +end; + +{ + * Free reference to null layer + } +function nullfs_unmount(mp:p_mount;mntflags:Integer):Integer; +var + mntdata:p_null_mount; + ump:p_mount; + error,flags:Integer; +begin + if ((mntflags and MNT_FORCE)<>0) then + flags:=FORCECLOSE + else + flags:=0; + + { There is 1 extra root vnode reference (nullm_rootvp). } + error:=vflush(mp, 1, flags); + if (error<>0) then + Exit(error); + + { + * Finally, throw away the null_mount structure + } + mntdata:=mp^.mnt_data; + ump:=mntdata^.nullm_vfs; + if ((mntdata^.nullm_flags and NULLM_CACHE)<>0) then + begin + MNT_ILOCK(ump); + while ((ump^.mnt_kern_flag and MNTK_VGONE_UPPER)<>0) do + begin + ump^.mnt_kern_flag:=ump^.mnt_kern_flag or MNTK_VGONE_WAITER; + msleep(@ump^.mnt_uppers, @ump^.mnt_mtx, 0, 'vgnupw', 0); + end; + TAILQ_REMOVE(@ump^.mnt_uppers,mp,@mp^.mnt_upper_link); + MNT_IUNLOCK(ump); + end; + mp^.mnt_data:=nil; + + FreeMem(mntdata); + Exit(0); +end; + +function nullfs_root(mp:p_mount;flags:Integer;vpp:pp_vnode):Integer; +var + vp:p_vnode; +begin + { + * Exitlocked reference to root. + } + vp:=MOUNTTONULLMOUNT(mp)^.nullm_rootvp; + VREF(vp); + + //ASSERT_VOP_UNLOCKED(vp, 'root vnode is locked'); + vn_lock(vp, flags or LK_RETRY); + vpp^:=vp; + Exit(0); +end; + +function nullfs_quotactl(mp:p_mount;cmd,uid:Integer;arg:Pointer):Integer; +begin + Exit(VFS_QUOTACTL(MOUNTTONULLMOUNT(mp)^.nullm_vfs, cmd, uid, arg)); +end; + +function nullfs_statfs(mp:p_mount;sbp:p_statfs):Integer; +var + error:Integer; + mstat:t_statfs; +begin + FillChar(mstat,sizeof(mstat),0); + + error:=VFS_STATFS(MOUNTTONULLMOUNT(mp)^.nullm_vfs, @mstat); + if (error<>0) then + Exit(error); + + { now copy across the 'interesting' information and fake the rest } + sbp^.f_type :=mstat.f_type; + sbp^.f_flags :=mstat.f_flags; + sbp^.f_bsize :=mstat.f_bsize; + sbp^.f_iosize:=mstat.f_iosize; + sbp^.f_blocks:=mstat.f_blocks; + sbp^.f_bfree :=mstat.f_bfree; + sbp^.f_bavail:=mstat.f_bavail; + sbp^.f_files :=mstat.f_files; + sbp^.f_ffree :=mstat.f_ffree; + + Exit(0); +end; + +function nullfs_sync(mp:p_mount;waitfor:Integer):Integer; +begin + { + * XXX - Assumes no data cached at null layer. + } + Exit(0); +end; + +function nullfs_vget(mp:p_mount;ino:DWORD;flags:Integer;vpp:pp_vnode):Integer; +var + error:Integer; +begin + Assert((flags and LK_TYPE_MASK)<>0, + ('nullfs_vget: no lock requested')); + + error:=VFS_VGET(MOUNTTONULLMOUNT(mp)^.nullm_vfs, ino, flags, vpp); + if (error<>0) then + Exit(error); + + Exit(null_nodeget(mp, vpp^, vpp)); +end; + +function nullfs_fhtovp(mp:p_mount;fidp:p_fid;flags:Integer;vpp:pp_vnode):Integer; +var + error:Integer; +begin + error:=VFS_FHTOVP(MOUNTTONULLMOUNT(mp)^.nullm_vfs, fidp, flags, vpp); + if (error<>0) then + Exit(error); + Exit(null_nodeget(mp, vpp^, vpp)); +end; + +function nullfs_extattrctl(mp:p_mount;cmd:Integer;filename_vp:p_vnode;namespace:Integer;attrname:PChar):Integer; +begin + Exit(VFS_EXTATTRCTL(MOUNTTONULLMOUNT(mp)^.nullm_vfs, cmd, filename_vp, namespace, attrname)); +end; + +end. + diff --git a/sys/fs/nullfs/null_vnops.pas b/sys/fs/nullfs/null_vnops.pas new file mode 100644 index 00000000..c6d481e3 --- /dev/null +++ b/sys/fs/nullfs/null_vnops.pas @@ -0,0 +1,888 @@ +unit null_vnops; + +{$mode ObjFPC}{$H+} +{$CALLING SysV_ABI_CDecl} + +interface + +uses + vnode, + vnode_if, + vfs_default; + +function null_bypass(ap:p_vop_generic_args):Integer; +function null_add_writecount(ap:p_vop_add_writecount_args):Integer; +function null_lookup(ap:p_vop_lookup_args):Integer; +function null_open(ap:p_vop_open_args):Integer; +function null_setattr(ap:p_vop_setattr_args):Integer; +function null_getattr(ap:p_vop_getattr_args):Integer; +function null_access(ap:p_vop_access_args):Integer; +function null_accessx(ap:p_vop_accessx_args):Integer; +function null_remove(ap:p_vop_remove_args):Integer; +function null_rename(ap:p_vop_rename_args):Integer; +function null_rmdir(ap:p_vop_rmdir_args):Integer; +function null_lock(ap:p_vop_lock1_args):Integer; +function null_unlock(ap:p_vop_unlock_args):Integer; +function null_inactive(ap:p_vop_inactive_args):Integer; +function null_reclaim(ap:p_vop_reclaim_args):Integer; +function null_print(ap:p_vop_print_args):Integer; +function null_getwritemount(ap:p_vop_getwritemount_args):Integer; +function null_vptofh(ap:p_vop_vptofh_args):Integer; +function null_vptocnp(ap:p_vop_vptocnp_args):Integer; +function null_link(ap:p_vop_link_args):Integer; + +const + null_vnodeops:vop_vector=( + vop_default :nil; + vop_bypass :@null_bypass; + + vop_islocked :@vop_stdislocked; + vop_lookup :@null_lookup; + vop_cachedlookup :nil; + vop_create :nil; + vop_whiteout :nil; + vop_mknod :nil; + vop_open :@null_open; + vop_close :nil; + vop_access :@null_access; + vop_accessx :@null_accessx; + vop_getattr :@null_getattr; + vop_setattr :@null_setattr; + vop_markatime :nil; + vop_read :nil; + vop_write :nil; + vop_ioctl :nil; + vop_poll :nil; + vop_kqfilter :nil; + vop_revoke :nil; + vop_fsync :nil; + vop_remove :@null_remove; + vop_link :@null_link; + vop_rename :@null_rename; + vop_mkdir :nil; + vop_rmdir :@null_rmdir; + vop_symlink :nil; + vop_readdir :nil; + vop_readlink :nil; + vop_inactive :@null_inactive; + vop_reclaim :@null_reclaim; + vop_lock1 :@null_lock; + vop_unlock :@null_unlock; + vop_bmap :@VOP_EOPNOTSUPP; + vop_strategy :@VOP_EOPNOTSUPP; + vop_getwritemount :@null_getwritemount; + vop_print :@null_print; + vop_pathconf :nil; + vop_advlock :nil; + vop_advlockasync :nil; + vop_advlockpurge :@vop_stdadvlockpurge; + vop_reallocblks :nil; + vop_getpages :nil; + vop_putpages :nil; + vop_getacl :nil; + vop_setacl :nil; + vop_aclcheck :nil; + vop_closeextattr :nil; + vop_getextattr :nil; + vop_listextattr :nil; + vop_openextattr :nil; + vop_deleteextattr :nil; + vop_setextattr :nil; + vop_setlabel :nil; + vop_vptofh :@null_vptofh; + vop_vptocnp :@null_vptocnp; + vop_allocate :nil; + vop_advise :nil; + vop_unp_bind :nil; + vop_unp_connect :nil; + vop_unp_detach :nil; + vop_is_text :nil; + vop_set_text :nil; + vop_unset_text :nil; + vop_get_writecount:nil; + vop_add_writecount:@null_add_writecount; + ); + +implementation + +uses + sysutils, + nullfs, + null_subr, + errno, + vnamei, + vmount, + vfs_subr, + vfs_vnops, + kern_mtx; + +type + ppp_vnode=^pp_vnode; + +function null_bypass(ap:p_vop_generic_args):Integer; +label + _out, + _nxt, + _err; +var + this_vp_p:pp_vnode; + error:Integer; + old_vps:array[0..VDESC_MAX_VPS-1] of p_vnode; + vps_p :array[0..VDESC_MAX_VPS-1] of pp_vnode; + vppp:ppp_vnode; + descp:p_vnodeop_desc; + reles,i:Integer; +begin + descp:=ap^.a_desc; + + { + * Map the vnodes going in. + * Later, we'll invoke the operation based on + * the first mapped vnode's operation vector. + } + reles:=descp^.vdesc_flags; + i:=0; + while (i < VDESC_MAX_VPS) do + begin + if (descp^.vdesc_vp_offsets[i]=Byte(-1)) then + break; { bail out at end of list } + + this_vp_p:=VOPARG_OFFSETTO(descp^.vdesc_vp_offsets[i],ap); + vps_p[i]:=this_vp_p; + { + * We're not guaranteed that any but the first vnode + * are of our type. Check for and don't map any + * that aren't. (We must always map first vp or vclean fails.) + } + if (i<>0) then + begin + if (this_vp_p^=nil) then + begin + old_vps[i]:=nil; + goto _nxt; + end; + if (this_vp_p^^.v_op<>@null_vnodeops) then + begin + old_vps[i]:=nil; + goto _nxt; + end; + end; + + old_vps[i]:=this_vp_p^; + vps_p[i]^:=NULLVPTOLOWERVP(this_vp_p^); + { + * XXX - Several operations have the side effect + * of vrele'ing their vp's. We must account for + * that. (This should go away in the future.) + } + if ((reles and VDESC_VP0_WILLRELE)<>0) then + VREF(this_vp_p^); + + // + _nxt: + reles:=reles shr 1; + Inc(i); + end; + + { + * Call the operation on the lower layer + * with the modified argument structure. + } + if (vps_p[0]=nil) then goto _err; + + if (vps_p[0]^<>nil) then + begin + error:=VCALL(ap); + end else + begin + _err: + Writeln(Format('null_bypass: no map for %s',[descp^.vdesc_name])); + error:=EINVAL; + end; + + { + * Maintain the illusion of call-by-value + * by restoring vnodes in the argument structure + * to their original value. + } + reles:=descp^.vdesc_flags; + i:=0; + while (i < VDESC_MAX_VPS) do + begin + if (descp^.vdesc_vp_offsets[i]=Byte(-1)) then + break; { bail out at end of list } + if (old_vps[i]<>nil) then + begin + vps_p[i]^:=old_vps[i]; + if ((reles and VDESC_VP0_WILLRELE)<>0) then + vrele((vps_p[i])^); + end; + // + reles:=reles shr 1; + Inc(i); + end; + + { + * Map the possible out-going vpp + * (Assumes that the lower layer always Exits + * a VREF'ed vpp unless it gets an error.) + } + if (descp^.vdesc_vpp_offset<>VDESC_NO_OFFSET) and + ((descp^.vdesc_flags and VDESC_NOMAP_VPP)=0) and + (error=0) then + begin + { + * XXX - even though some ops have vpp Exited vp's, + * several ops actually vrele this before Exiting. + * We must avoid these ops. + * (This should go away when these ops are regularized.) + } + if ((descp^.vdesc_flags and VDESC_VPP_WILLRELE)<>0) then + goto _out; + + vppp:=VOPARG_OFFSETTO(descp^.vdesc_vpp_offset,ap); + + if (vppp^<>nil) then + error:=null_nodeget(old_vps[0]^.v_mount,vppp^^,vppp^); + end; + +_out: + Exit(error); +end; + +function null_add_writecount(ap:p_vop_add_writecount_args):Integer; +var + lvp,vp:p_vnode; + error:Integer; +begin + vp:=ap^.a_vp; + lvp:=NULLVPTOLOWERVP(vp); + Assert(vp^.v_writecount + ap^.a_inc >= 0,'wrong writecount inc'); + if (vp^.v_writecount > 0) and (vp^.v_writecount + ap^.a_inc=0) then + error:=VOP_ADD_WRITECOUNT(lvp, -1) + else + if (vp^.v_writecount=0) and (vp^.v_writecount + ap^.a_inc > 0) then + error:=VOP_ADD_WRITECOUNT(lvp, 1) + else + error:=0; + if (error=0) then + Inc(vp^.v_writecount,ap^.a_inc); + Exit(error); +end; + +{ + * We have to carry on the locking protocol on the null layer vnodes + * as we progress through the tree. We also have to enforce read-only + * if this layer is mounted read-only. + } +function null_lookup(ap:p_vop_lookup_args):Integer; +var + cnp:p_componentname; + dvp:p_vnode; + flags:Integer; + vp,ldvp,lvp:p_vnode; + error:Integer; +begin + cnp:=ap^.a_cnp; + dvp:=ap^.a_dvp; + flags:=cnp^.cn_flags; + + if ((flags and ISLASTCN)<>0) and + ((p_mount(dvp^.v_mount)^.mnt_flag and MNT_RDONLY)<>0) and + ((cnp^.cn_nameiop=DELETE) or (cnp^.cn_nameiop=RENAME)) then + Exit(EROFS); + { + * Although it is possible to call null_bypass(), we'll do + * a direct call to reduce overhead + } + ldvp:=NULLVPTOLOWERVP(dvp); + vp:=nil; + lvp:=nil; + error:=VOP_LOOKUP(ldvp, @lvp, cnp); + + if (error=EJUSTRETURN) and + ((flags and ISLASTCN)<>0) and + ((p_mount(dvp^.v_mount)^.mnt_flag and MNT_RDONLY)<>0) and + ((cnp^.cn_nameiop=CREATE) or (cnp^.cn_nameiop=RENAME)) then + error:=EROFS; + + if ((error=0) or (error=EJUSTRETURN)) and (lvp<>nil) then + begin + if (ldvp=lvp) then + begin + ap^.a_vpp^:=dvp; + VREF(dvp); + vrele(lvp); + end else + begin + error:=null_nodeget(dvp^.v_mount, lvp, @vp); + if (error=0) then + ap^.a_vpp^:=vp; + end; + end; + Exit(error); +end; + +function null_open(ap:p_vop_open_args):Integer; +var + retval:Integer; + vp,ldvp:p_vnode; +begin + vp:=ap^.a_vp; + ldvp:=NULLVPTOLOWERVP(vp); + retval:=null_bypass(Pointer(ap)); + //if (retval=0) then + // vp^.v_object:=ldvp^.v_object; + Exit(retval); +end; + +{ + * Setattr call. Disallow write attempts if the layer is mounted read-only. + } +function null_setattr(ap:p_vop_setattr_args):Integer; +var + vp:p_vnode; + vap:p_vattr; +begin + vp:=ap^.a_vp; + vap:=ap^.a_vap; + + if ((vap^.va_flags<>QWORD(VNOVAL)) or + (vap^.va_uid<>Integer(VNOVAL)) or + (vap^.va_gid<>Integer(VNOVAL)) or + (vap^.va_atime.tv_sec<>VNOVAL) or + (vap^.va_mtime.tv_sec<>VNOVAL) or + (vap^.va_mode<>Word(VNOVAL)) + ) and + ((p_mount(vp^.v_mount)^.mnt_flag and MNT_RDONLY)<>0) then + Exit(EROFS); + + if (vap^.va_size<>QWORD(VNOVAL)) then + begin + case (vp^.v_type) of + VDIR: + begin + Exit(EISDIR); + end; + VCHR, + VBLK, + VSOCK, + VFIFO: + begin + if (vap^.va_flags<>QWORD(VNOVAL)) then + Exit(EOPNOTSUPP); + Exit(0); + end; + else + begin + { + * Disallow write attempts if the filesystem is + * mounted read-only. + } + if ((p_mount(vp^.v_mount)^.mnt_flag and MNT_RDONLY)<>0) then + Exit(EROFS); + end; + end; + end; + + Exit(null_bypass(Pointer(ap))); +end; + +{ + * We handle getattr only to change the fsid. + } +function null_getattr(ap:p_vop_getattr_args):Integer; +var + error:Integer; +begin + error:=null_bypass(Pointer(ap)); + + if (error<>0) then + Exit(error); + + ap^.a_vap^.va_fsid:=p_mount(ap^.a_vp^.v_mount)^.mnt_stat.f_fsid.val[0]; + Exit(0); +end; + +{ + * Handle to disallow write access if mounted read-only. + } +function null_access(ap:p_vop_access_args):Integer; +var + vp:p_vnode; + accmode:accmode_t; +begin + vp:=ap^.a_vp; + accmode:=ap^.a_accmode; + + { + * Disallow write attempts on read-only layers; + * unless the file is a socket, fifo, or a block or + * character device resident on the filesystem. + } + if ((accmode and VWRITE)<>0) then + begin + case (vp^.v_type) of + VDIR, + VLNK, + VREG: + begin + if ((p_mount(vp^.v_mount)^.mnt_flag and MNT_RDONLY)<>0) then + Exit(EROFS); + end; + else; + end; + end; + + Exit(null_bypass(Pointer(ap))); +end; + +function null_accessx(ap:p_vop_accessx_args):Integer; +var + vp:p_vnode; + accmode:accmode_t; +begin + vp:=ap^.a_vp; + accmode:=ap^.a_accmode; + + { + * Disallow write attempts on read-only layers; + * unless the file is a socket, fifo, or a block or + * character device resident on the filesystem. + } + if ((accmode and VWRITE)<>0) then + begin + case (vp^.v_type) of + VDIR, + VLNK, + VREG: + begin + if ((p_mount(vp^.v_mount)^.mnt_flag and MNT_RDONLY)<>0) then + Exit(EROFS); + end; + else; + end; + end; + + Exit(null_bypass(Pointer(ap))); +end; + +{ + * Increasing refcount of lower vnode is needed at least for the case + * when lower FS is NFS to do sillyrename if the file is in use. + * Unfortunately v_usecount is incremented in many places in + * the kernel and, as such, there may be races that result in + * the NFS client doing an extraneous silly rename, but that seems + * preferable to not doing a silly rename when it is needed. + } +function null_remove(ap:p_vop_remove_args):Integer; +var + retval,vreleit:Integer; + lvp,vp:p_vnode; + tnn:p_null_node; +begin + vp:=ap^.a_vp; + if (vrefcnt(vp) > 1) then + begin + lvp:=NULLVPTOLOWERVP(vp); + VREF(lvp); + vreleit:=1; + end else + vreleit:=0; + + tnn:=VTONULL(vp); + tnn^.null_flags:=tnn^.null_flags or NULLV_DROP; + + retval:=null_bypass(@ap^.a_gen); + if (vreleit<>0) then + vrele(lvp); + + Exit(retval); +end; + +{ + * We handle this to eliminate null FS to lower FS + * file moving. Don't know why we don't allow this, + * possibly we should. + } +function null_rename(ap:p_vop_rename_args):Integer; +label + _cross; +var + tdvp,fvp,fdvp,tvp:p_vnode; + tnn:p_null_node; +begin + tdvp:=ap^.a_tdvp; + fvp:=ap^.a_fvp; + fdvp:=ap^.a_fdvp; + tvp:=ap^.a_tvp; + + if (tvp<>nil) then + begin + if (fvp^.v_mount<>tvp^.v_mount) then goto _cross; + end; + + { Check for cross-device rename. } + if (fvp^.v_mount<>tdvp^.v_mount) then + begin + _cross: + if (tdvp=tvp) then + vrele(tdvp) + else + vput(tdvp); + + if (tvp<>nil) then + vput(tvp); + vrele(fdvp); + vrele(fvp); + Exit(EXDEV); + end; + + if (tvp<>nil) then + begin + tnn:=VTONULL(tvp); + tnn^.null_flags:=tnn^.null_flags or NULLV_DROP; + end; + + Exit(null_bypass(Pointer(ap))); +end; + +function null_rmdir(ap:p_vop_rmdir_args):Integer; +var + tnn:p_null_node; +begin + tnn:=VTONULL(ap^.a_vp); + tnn^.null_flags:=tnn^.null_flags or NULLV_DROP; + Exit(null_bypass(Pointer(ap))); +end; + +{ + * We need to process our own vnode lock and then clear the + * interlock flag as it applies only to our vnode, not the + * vnodes below us on the stack. + } +function null_lock(ap:p_vop_lock1_args):Integer; +var + vp:p_vnode; + flags:Integer; + nn:p_null_node; + lvp:p_vnode; + error:Integer; +begin + vp:=ap^.a_vp; + flags:=ap^.a_flags; + + if ((flags and LK_INTERLOCK)=0) then + begin + VI_LOCK(vp); + flags:=flags or LK_INTERLOCK; + ap^.a_flags:=flags; + end; + nn:=VTONULL(vp); + { + * If we're still active we must ask the lower layer to + * lock as ffs has special lock considerations in it's + * vop lock. + } + if (nn<>nil) then + begin + lvp:=NULLVPTOLOWERVP(vp); + if (lvp<>nil) then + begin + VI_LOCK(lvp); + VI_UNLOCK(vp); + { + * We have to hold the vnode here to solve a potential + * reclaim race. If we're forcibly vgone'd while we + * still have refs, a thread could be sleeping inside + * the lowervp's vop_lock routine. When we vgone we will + * drop our last ref to the lowervp, which would allow it + * to be reclaimed. The lowervp could then be recycled, + * in which case it is not legal to be sleeping in it's VOP. + * We prevent it from being recycled by holding the vnode + * here. + } + vholdl(lvp); + error:=VOP_LOCK(lvp,flags,{$INCLUDE %FILE%},{$INCLUDE %LINENUM%}); + + { + * We might have slept to get the lock and someone might have + * clean our vnode already, switching vnode lock from one in + * lowervp to v_lock in our own vnode structure. Handle this + * case by reacquiring correct lock in requested mode. + } + if (VTONULL(vp)=nil) and (error=0) then + begin + ap^.a_flags:=ap^.a_flags and (not (LK_TYPE_MASK or LK_INTERLOCK)); + case (flags and LK_TYPE_MASK) of + LK_SHARED: + begin + ap^.a_flags:=ap^.a_flags or LK_SHARED; + end; + LK_UPGRADE, + LK_EXCLUSIVE: + begin + ap^.a_flags:=ap^.a_flags or LK_EXCLUSIVE; + end; + else + Assert(False,'Unsupported lock request'); + end; + VOP_UNLOCK(lvp, 0); + error:=vop_stdlock(ap); + end; + vdrop(lvp); + end else + error:=vop_stdlock(ap); + end else + error:=vop_stdlock(ap); + + Exit(error); +end; + +{ + * We need to process our own vnode unlock and then clear the + * interlock flag as it applies only to our vnode, not the + * vnodes below us on the stack. + } +function null_unlock(ap:p_vop_unlock_args):Integer; +label + _else; +var + vp:p_vnode; + flags:Integer; + mtxlkflag:Integer; + nn:p_null_node; + lvp:p_vnode; + error:Integer; +begin + vp:=ap^.a_vp; + flags:=ap^.a_flags; + mtxlkflag:=0; + + if ((flags and LK_INTERLOCK)<>0) then + mtxlkflag:=1 + else + if (not mtx_owned(VI_MTX(vp)^)) then + begin + VI_LOCK(vp); + mtxlkflag:=2; + end; + nn:=VTONULL(vp); + if (nn<>nil) then + begin + lvp:=NULLVPTOLOWERVP(vp); + if (lvp=nil) then goto _else; + + VI_LOCK(lvp); + flags:=flags or LK_INTERLOCK; + vholdl(lvp); + VI_UNLOCK(vp); + error:=VOP_UNLOCK(lvp, flags); + vdrop(lvp); + if (mtxlkflag=0) then + VI_LOCK(vp); + end else + begin + _else: + if (mtxlkflag=2) then + VI_UNLOCK(vp); + error:=vop_stdunlock(ap); + end; + + Exit(error); +end; + +{ + * Do not allow the VOP_INACTIVE to be passed to the lower layer, + * since the reference count on the lower vnode is not related to + * ours. + } +function null_inactive(ap:p_vop_inactive_args):Integer; +var + vp,lvp:p_vnode; + xp:p_null_node; + mp:p_mount; + xmp:p_null_mount; +begin + vp:=ap^.a_vp; + xp:=VTONULL(vp); + lvp:=NULLVPTOLOWERVP(vp); + mp:=vp^.v_mount; + xmp:=MOUNTTONULLMOUNT(mp); + + if ((xmp^.nullm_flags and NULLM_CACHE)=0) or + ((xp^.null_flags and NULLV_DROP)<>0) or + ((lvp^.v_vflag and VV_NOSYNC)<>0) then + begin + { + * If this is the last reference and caching of the + * nullfs vnodes is not enabled, or the lower vnode is + * deleted, then free up the vnode so as not to tie up + * the lower vnodes. + } + //vp^.v_object:=nil; + vrecycle(vp); + end; + Exit(0); +end; + +{ + * Now, the nullfs vnode and, due to the sharing lock, the lower + * vnode, are exclusively locked, and we shall destroy the null vnode. + } +function null_reclaim(ap:p_vop_reclaim_args):Integer; +var + vp:p_vnode; + xp:p_null_node; + lowervp:p_vnode; +begin + vp:=ap^.a_vp; + xp:=VTONULL(vp); + lowervp:=xp^.null_lowervp; + + Assert((lowervp<>nil) and (vp^.v_vnlock<>@vp^.v_lock),'Reclaiming incomplete null vnode'); + + null_hashrem(xp); + { + * Use the interlock to protect the clearing of v_data to + * prevent faults in null_lock(). + } + mtx_lock(vp^.v_lock); + //lockmgr(@vp^.v_lock, LK_EXCLUSIVE, nil); + + VI_LOCK(vp); + vp^.v_data:=nil; + //vp^.v_object:=nil; + vp^.v_vnlock:=@vp^.v_lock; + VI_UNLOCK(vp); + + { + * If we were opened for write, we leased one write reference + * to the lower vnode. If this is a reclamation due to the + * forced unmount, undo the reference now. + } + if (vp^.v_writecount > 0) then + VOP_ADD_WRITECOUNT(lowervp, -1); + + if ((xp^.null_flags and NULLV_NOUNLOCK)<>0) then + vunref(lowervp) + else + vput(lowervp); + + FreeMem(xp); + + Exit(0); +end; + +function null_print(ap:p_vop_print_args):Integer; +var + vp:p_vnode; +begin + vp:=ap^.a_vp; + + Writeln(Format('vp=%p, lowervp=%p', [vp,VTONULL(vp)^.null_lowervp])); + Exit(0); +end; + +{ ARGSUSED } +function null_getwritemount(ap:p_vop_getwritemount_args):Integer; +label + _else; +var + xp:p_null_node; + lowervp:p_vnode; + vp:p_vnode; +begin + vp:=ap^.a_vp; + VI_LOCK(vp); + xp:=VTONULL(vp); + if (xp<>nil) then + begin + lowervp:=xp^.null_lowervp; + if (lowervp=nil) then goto _else; + + VI_LOCK(lowervp); + VI_UNLOCK(vp); + vholdl(lowervp); + VI_UNLOCK(lowervp); + VOP_GETWRITEMOUNT(lowervp, ap^.a_mpp); + vdrop(lowervp); + end else + begin + _else: + VI_UNLOCK(vp); + ap^.a_mpp^:=nil; + end; + Exit(0); +end; + +function null_vptofh(ap:p_vop_vptofh_args):Integer; +var + lvp:p_vnode; +begin + lvp:=NULLVPTOLOWERVP(ap^.a_vp); + Exit(VOP_VPTOFH(lvp, ap^.a_fhp)); +end; + +function null_vptocnp(ap:p_vop_vptocnp_args):Integer; +var + vp:p_vnode; + dvp:pp_vnode; + lvp,ldvp:p_vnode; + error,locked:Integer; +begin + vp:=ap^.a_vp; + dvp:=ap^.a_vpp; + + if (vp^.v_type=VDIR) then + Exit(vop_stdvptocnp(ap)); + + locked:=VOP_ISLOCKED(vp); + lvp:=NULLVPTOLOWERVP(vp); + vhold(lvp); + VOP_UNLOCK(vp, 0); { vp is held by vn_vptocnp_locked that called us } + ldvp:=lvp; + vref(lvp); + error:=0; + Assert(False,'TODO vn_vptocnp'); + //error:=vn_vptocnp(@ldvp, ap^.a_buf, ap^.a_buflen); + vdrop(lvp); + if (error<>0) then + begin + vn_lock(vp, locked or LK_RETRY); + Exit(ENOENT); + end; + + { + * Exclusive lock is required by insmntque1 call in + * null_nodeget() + } + error:=vn_lock(ldvp, LK_EXCLUSIVE); + if (error<>0) then + begin + vrele(ldvp); + vn_lock(vp, locked or LK_RETRY); + Exit(ENOENT); + end; + vref(ldvp); + error:=null_nodeget(vp^.v_mount, ldvp, dvp); + if (error=0) then + begin + VOP_UNLOCK(dvp^, 0); { keep reference on *dvp } + end; + vn_lock(vp, locked or LK_RETRY); + Exit(error); +end; + +function null_link(ap:p_vop_link_args):Integer; +begin + if (ap^.a_tdvp^.v_mount<>ap^.a_vp^.v_mount) then + Exit(EXDEV); + + Exit(null_bypass(Pointer(ap))); +end; + + + +end. + diff --git a/sys/fs/nullfs/nullfs.pas b/sys/fs/nullfs/nullfs.pas new file mode 100644 index 00000000..25bdc949 --- /dev/null +++ b/sys/fs/nullfs/nullfs.pas @@ -0,0 +1,63 @@ +unit nullfs; + +{$mode ObjFPC}{$H+} +{$CALLING SysV_ABI_CDecl} + +interface + +uses + mqueue, + vmount, + vnode; + +const + NULLM_CACHE=$0001; + + NULLV_NOUNLOCK=$0001; + NULLV_DROP =$0002; + +type + p_null_mount=^t_null_mount; + t_null_mount=packed record + nullm_vfs :p_mount; + nullm_rootvp:p_vnode; { Reference to root null_node } + nullm_flags :QWORD; + end; + + p_null_node=^t_null_node; + t_null_node=packed record + null_hash :LIST_ENTRY; { Hash list } + null_lowervp:p_vnode; { VREFed once } + null_vnode :p_vnode; { Back pointer } + null_flags :DWORD; + end; + +function MOUNTTONULLMOUNT(mp:p_mount):p_null_mount; +function VTONULL(vp:p_vnode):p_null_node; +function NULLTOV(xp:p_null_node):p_vnode; +function NULLVPTOLOWERVP(vp:p_vnode):p_vnode; + +implementation + +function MOUNTTONULLMOUNT(mp:p_mount):p_null_mount; +begin + Result:=mp^.mnt_data; +end; + +function VTONULL(vp:p_vnode):p_null_node; +begin + Result:=vp^.v_data; +end; + +function NULLTOV(xp:p_null_node):p_vnode; +begin + Result:=xp^.null_vnode; +end; + +function NULLVPTOLOWERVP(vp:p_vnode):p_vnode; +begin + Result:=VTONULL(vp)^.null_lowervp; +end; + +end. + diff --git a/sys/kern/systm.pas b/sys/kern/systm.pas index 4d583b88..624bba39 100644 --- a/sys/kern/systm.pas +++ b/sys/kern/systm.pas @@ -9,8 +9,8 @@ uses ntapi; const - IOSIZE_MAX =High(Int64); - DEVFS_IOSIZE_MAX=High(Int64); + IOSIZE_MAX =High(Integer); + DEVFS_IOSIZE_MAX=High(Integer); function copystr(from,_to:Pointer;maxlen:ptruint;lencopied:pptruint):Integer; function copyin(udaddr,kaddr:Pointer;len:ptruint):Integer; inline; diff --git a/sys/sys_sysinit.pas b/sys/sys_sysinit.pas index 0796435f..6734a79f 100644 --- a/sys/sys_sysinit.pas +++ b/sys/sys_sysinit.pas @@ -31,6 +31,7 @@ uses devfs_devs, devfs_vfsops, fdesc_vfsops, + null_vfsops, kern_descrip, vfs_mountroot; @@ -44,6 +45,7 @@ procedure module_init; begin vfs_register(@devfs_vfsconf); vfs_register(@fdescfs_vfsconf); + vfs_register(@nullfs_vfsconf); vfs_mountroot.vfs_mountroot(); fildesc_drvinit; end; diff --git a/sys/test/project1.lpi b/sys/test/project1.lpi index 50ee633e..a31023ed 100644 --- a/sys/test/project1.lpi +++ b/sys/test/project1.lpi @@ -257,10 +257,6 @@ - - - - @@ -453,10 +449,6 @@ - - - - @@ -469,6 +461,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + @@ -479,7 +495,7 @@ - + diff --git a/sys/test/project1.lpr b/sys/test/project1.lpr index 55ad5d6a..0ae0e015 100644 --- a/sys/test/project1.lpr +++ b/sys/test/project1.lpr @@ -39,7 +39,6 @@ uses thr_stack, sys_mmap, kern_synch, - vfs_vnode, murmurhash, hamt, vfs_subr, @@ -63,10 +62,15 @@ uses vstat, vfcntl, vdirent, - fdesc, fdesc_vfsops, fdesc_vnops, - kern_descrip; + fdescfs, + kern_descrip, + vnode, + nullfs, + null_subr, + null_vnops, + null_vfsops; var mtx:umutex; diff --git a/sys/time.pas b/sys/time.pas index 22e8fd99..a452b5f2 100644 --- a/sys/time.pas +++ b/sys/time.pas @@ -69,16 +69,16 @@ procedure timevalfix(t1:ptimeval); procedure timevaladd(t1,t2:ptimeval); procedure timevalsub(t1,t2:ptimeval); -function timespeccmp_lt(tvp,uvp:ptimespec):Integer; inline; +function timespeccmp_lt(tvp,uvp:ptimespec):Integer; -procedure TIMEVAL_TO_TIMESPEC(tv:ptimeval;ts:ptimespec); inline; -procedure TIMESPEC_TO_TIMEVAL(tv:ptimeval;ts:ptimespec); inline; +procedure TIMEVAL_TO_TIMESPEC(tv:ptimeval;ts:ptimespec); +procedure TIMESPEC_TO_TIMEVAL(tv:ptimeval;ts:ptimespec); -function TIMESPEC_TO_UNIT(ts:ptimespec):Int64; inline; //Unit -function TIMEVAL_TO_UNIT (tv:ptimeval ):Int64; inline; //Unit -function USEC_TO_UNIT (usec:QWORD ):Int64; inline; //Unit +function TIMESPEC_TO_UNIT(ts:ptimespec):Int64; //Unit +function TIMEVAL_TO_UNIT (tv:ptimeval ):Int64; //Unit +function USEC_TO_UNIT (usec:QWORD ):Int64; //Unit -function tvtohz(time:Int64):Int64; inline; +function tvtohz(time:Int64):Int64; procedure usec2timespec(ts:ptimespec;timeo:DWORD); procedure TIMESPEC_ADD(dst,src,val:ptimespec); @@ -158,7 +158,7 @@ begin timevalfix(t1); end; -function timespeccmp_lt(tvp,uvp:ptimespec):Integer; inline; +function timespeccmp_lt(tvp,uvp:ptimespec):Integer; begin if (tvp^.tv_sec=uvp^.tv_sec) then begin @@ -169,34 +169,34 @@ begin end; end; -procedure TIMEVAL_TO_TIMESPEC(tv:ptimeval;ts:ptimespec); inline; +procedure TIMEVAL_TO_TIMESPEC(tv:ptimeval;ts:ptimespec); begin ts^.tv_sec :=tv^.tv_sec; ts^.tv_nsec:=tv^.tv_usec * 1000; end; -procedure TIMESPEC_TO_TIMEVAL(tv:ptimeval;ts:ptimespec); inline; +procedure TIMESPEC_TO_TIMEVAL(tv:ptimeval;ts:ptimespec); begin tv^.tv_sec :=ts^.tv_sec; tv^.tv_usec:=ts^.tv_nsec div 1000; end; -function TIMESPEC_TO_UNIT(ts:ptimespec):Int64; inline; //Unit +function TIMESPEC_TO_UNIT(ts:ptimespec):Int64; //Unit begin Result:=(QWORD(ts^.tv_sec)*10000000)+(QWORD(ts^.tv_nsec) div 100); end; -function TIMEVAL_TO_UNIT(tv:ptimeval):Int64; inline; //Unit +function TIMEVAL_TO_UNIT(tv:ptimeval):Int64; //Unit begin Result:=(QWORD(tv^.tv_sec)*10000000)+(QWORD(tv^.tv_usec)*10); end; -function USEC_TO_UNIT(usec:QWORD):Int64; inline; //Unit +function USEC_TO_UNIT(usec:QWORD):Int64; //Unit begin Result:=(usec*10); end; -function tvtohz(time:Int64):Int64; inline; +function tvtohz(time:Int64):Int64; begin Result:=time; end; diff --git a/sys/vfs/kern_conf.pas b/sys/vfs/kern_conf.pas index d27026ca..fbb0bf32 100644 --- a/sys/vfs/kern_conf.pas +++ b/sys/vfs/kern_conf.pas @@ -10,7 +10,7 @@ uses vmount, vfile, vuio, - vfs_vnode, + vnode, time, vm, vm_object, @@ -1159,6 +1159,7 @@ function make_dev_physpath_alias(flags:Integer; pdev,old_alias:p_cdev; physpath:PChar):Integer; label + _ret, _out; var devfspath:PChar; @@ -1203,8 +1204,11 @@ begin R:=Format('%s/%s',[physpath,pdev^.si_name]); Move(PChar(R)^,devfspath^,Length(R)+1); - if (old_alias<>nil) and (strcomp(old_alias^.si_name, devfspath)=0) then + if (old_alias=nil) then goto _ret; + + if (strcomp(old_alias^.si_name, devfspath)=0) then begin + _ret: { Retain the existing alias. } cdev^:=old_alias; old_alias:=nil; @@ -1271,8 +1275,9 @@ begin csw:=dev^.si_devsw; dev^.si_devsw:=nil; { already nil for SI_ALIAS } - while (csw<>nil) and (csw^.d_purge<>nil) and (dev^.si_threadcount<>0) do + while (csw<>nil) and (dev^.si_threadcount<>0) do begin + if (csw^.d_purge=nil) then Break; csw^.d_purge(dev); msleep(csw, @devmtx, PRIBIO, 'devprg', hz div 10); if (dev^.si_threadcount<>0) then diff --git a/sys/vfs/kern_descrip.pas b/sys/vfs/kern_descrip.pas index c893eaf0..ad88cf54 100644 --- a/sys/vfs/kern_descrip.pas +++ b/sys/vfs/kern_descrip.pas @@ -15,7 +15,7 @@ uses vfcntl, vfilio, vmount, - vfs_vnode, + vnode, vsocketvar; const diff --git a/sys/vfs/sys_capability.pas b/sys/vfs/sys_capability.pas index b35d844f..a9f97196 100644 --- a/sys/vfs/sys_capability.pas +++ b/sys/vfs/sys_capability.pas @@ -135,6 +135,7 @@ var c:p_capability; error:Integer; begin + if (fp_cap=nil) then Exit(EINVAL); if (fp_cap^.f_type<>DTYPE_CAPABILITY) then begin fpp^:=fp_cap; diff --git a/sys/vfs/vfile.pas b/sys/vfs/vfile.pas index c036c5be..06bd183f 100644 --- a/sys/vfs/vfile.pas +++ b/sys/vfs/vfile.pas @@ -8,7 +8,7 @@ interface uses vstat, vuio, - vfs_vnode, + vnode, kern_thr, kern_id; diff --git a/sys/vfs/vfiledesc.pas b/sys/vfs/vfiledesc.pas index c93e690a..a29ea934 100644 --- a/sys/vfs/vfiledesc.pas +++ b/sys/vfs/vfiledesc.pas @@ -7,7 +7,7 @@ interface uses vfile, - vfs_vnode, + vnode, kern_rwlock, kern_id; diff --git a/sys/vfs/vfs_default.pas b/sys/vfs/vfs_default.pas index 9aa78c77..9e7dd829 100644 --- a/sys/vfs/vfs_default.pas +++ b/sys/vfs/vfs_default.pas @@ -7,7 +7,7 @@ interface uses sysutils, - vfs_vnode, + vnode, vnode_if, vdirent, vuio, @@ -17,7 +17,6 @@ uses vnamei, vfcntl, vpoll, - vsocketvar, kern_thr, kern_mtx; @@ -573,6 +572,8 @@ var begin vp:=ap^.a_vp; + //Writeln('vop_std lock:',HexStr(ap^.a_vp^.v_vnlock)); + Result:=lockmgr(vp^.v_vnlock,ap^.a_flags,VI_MTX(vp)); //Exit(_lockmgr_args(vp^.v_vnlock, ap^.a_flags, VI_MTX(vp), @@ -587,6 +588,8 @@ var begin vp:=ap^.a_vp; + //Writeln('vop_stdunlock:',HexStr(ap^.a_vp^.v_vnlock)); + Result:=lockmgr(vp^.v_vnlock,ap^.a_flags or LK_RELEASE,VI_MTX(vp)); //Exit(lockmgr(vp^.v_vnlock, ap^.a_flags or LK_RELEASE, VI_MTX(vp))); @@ -596,6 +599,8 @@ end; function vop_stdislocked(ap:p_vop_islocked_args):Integer; begin + //Writeln('vop_stdislocked:',HexStr(ap^.a_vp^.v_vnlock),':',mtx_owned(ap^.a_vp^.v_vnlock^)); + if mtx_owned(ap^.a_vp^.v_vnlock^) then Exit(LK_EXCLUSIVE) else diff --git a/sys/vfs/vfs_lookup.pas b/sys/vfs/vfs_lookup.pas index 12cf02f0..f4d3642e 100644 --- a/sys/vfs/vfs_lookup.pas +++ b/sys/vfs/vfs_lookup.pas @@ -13,7 +13,7 @@ uses vfile, vfiledesc, vfcntl, - vfs_vnode, + vnode, vnode_if, vnamei, vmount, @@ -316,13 +316,20 @@ end; function compute_cn_lkflags(mp:p_mount;lkflags,cnflags:Integer):Integer; begin - if (mp=nil) or (((lkflags and LK_SHARED)<>0) and + if (mp=nil) then + begin + lkflags:=lkflags and (not LK_SHARED); + lkflags:=lkflags or LK_EXCLUSIVE; + Exit(lkflags); + end; + + if (((lkflags and LK_SHARED)<>0) and (((mp^.mnt_kern_flag and MNTK_LOOKUP_SHARED)=0) or (((cnflags and ISDOTDOT)<>0) and ((mp^.mnt_kern_flag and MNTK_LOOKUP_EXCL_DOTDOT)<>0)))) then begin lkflags:=lkflags and (not LK_SHARED); - lkflags:=lkflags or LK_EXCLUSIVE; + lkflags:=lkflags or LK_EXCLUSIVE; end; Exit(lkflags); end; @@ -348,11 +355,12 @@ begin } if ((flags and ISOPEN)<>0) then begin - if (mp<>nil) and - ((mp^.mnt_kern_flag and MNTK_EXTENDED_SHARED)<>0) then + if (mp<>nil) then + if ((mp^.mnt_kern_flag and MNTK_EXTENDED_SHARED)<>0) then + begin Exit(0) - else - Exit(1); + end; + Exit(1); end; { @@ -674,8 +682,8 @@ unionlookup: if (error=ENOENT) and ((dp^.v_vflag and VV_ROOT)<>0) and - (dp^.v_mount<>nil) and - ((p_mount(dp^.v_mount)^.mnt_flag and MNT_UNION)<>0) then + (dp^.v_mount<>nil) then + if ((p_mount(dp^.v_mount)^.mnt_flag and MNT_UNION)<>0) then begin tdp:=dp; dp:=p_mount(dp^.v_mount)^.mnt_vnodecovered; @@ -684,9 +692,7 @@ unionlookup: VREF(dp); vput(tdp); VFS_UNLOCK_GIANT(tvfslocked); - vn_lock(dp, - compute_cn_lkflags(dp^.v_mount, cnp^.cn_lkflags or - LK_RETRY, cnp^.cn_flags)); + vn_lock(dp,compute_cn_lkflags(dp^.v_mount, cnp^.cn_lkflags or LK_RETRY, cnp^.cn_flags)); goto unionlookup; end; @@ -883,8 +889,8 @@ success: * Because of lookup_shared we may have the vnode shared locked, but * the caller may want it to be exclusively locked. } - if (needs_exclusive_leaf(dp^.v_mount, cnp^.cn_flags) and - VOP_ISLOCKED(dp)<>LK_EXCLUSIVE) then + if (needs_exclusive_leaf(dp^.v_mount, cnp^.cn_flags)<>0) and + (VOP_ISLOCKED(dp)<>LK_EXCLUSIVE) then begin vn_lock(dp, LK_UPGRADE or LK_RETRY); if ((dp^.v_iflag and VI_DOOMED)<>0) then diff --git a/sys/vfs/vfs_mount.pas b/sys/vfs/vfs_mount.pas index 67823b6b..d9ff1df3 100644 --- a/sys/vfs/vfs_mount.pas +++ b/sys/vfs/vfs_mount.pas @@ -14,7 +14,7 @@ uses kern_mtx, kern_synch, kern_thr, - vfs_vnode, + vnode, vfs_init, vfs_lookup, vnode_if; @@ -103,6 +103,7 @@ function kernel_mount(ma:p_mntarg;flags:QWORD):Integer; implementation uses + murmurhash, errno, systm, vfs_vnops, @@ -723,6 +724,18 @@ begin mtx_destroy(mp^.mnt_mtx); end; +var + mnt_hashseed:QWORD=QWORD($FEEDBABEFEEDBABE); + +function get_mnt_hashseed:DWORD; +var + i:QWORD; +begin + i:=MurmurHash64A(@mnt_hashseed,SizeOf(mnt_hashseed),mnt_hashseed); + mnt_hashseed:=i; + Result:=DWORD(i); +end; + function vfs_mount_alloc(vp :p_vnode; vfsp :p_vfsconf; fspath:PChar):p_mount; @@ -755,7 +768,8 @@ begin //mac_mount_init(mp); //mac_mount_create(cred, mp); - mp^.mnt_hashseed:=$FEEDBABE; //arc4rand + //arc4rand(&mp->mnt_hashseed, sizeof mp->mnt_hashseed, 0); + mp^.mnt_hashseed:=get_mnt_hashseed; TAILQ_INIT(@mp^.mnt_uppers); Result:=mp; diff --git a/sys/vfs/vfs_mountroot.pas b/sys/vfs/vfs_mountroot.pas index 75a6981e..01790260 100644 --- a/sys/vfs/vfs_mountroot.pas +++ b/sys/vfs/vfs_mountroot.pas @@ -19,7 +19,7 @@ uses errno, vuio, vnamei, - vfs_vnode, + vnode, vnode_if, vfiledesc, vfs_subr, @@ -68,7 +68,10 @@ var val,val_arg:PChar; opts:PChar; begin - if (options=nil) or (options[0]=#0) then + if (options=nil) then + Exit(ma); + + if (options[0]=#0) then Exit(ma); p:=strdup(options); @@ -165,11 +168,11 @@ begin mpp^:=mp; set_rootvnode(); - error:=kern_symlink('/', 'dev', UIO_SYSSPACE); - if (error<>0) then - begin - Writeln('kern_symlink /dev / returns ',error); - end; + //error:=kern_symlink('/', 'dev', UIO_SYSSPACE); + //if (error<>0) then + //begin + // Writeln('kern_symlink /dev / returns ',error); + //end; Exit(error); end; @@ -296,9 +299,9 @@ begin begin vfs_unbusy(mpdevfs); { Unlink the no longer needed /dev/dev ^. / symlink } - error:=kern_unlink('/dev/dev', UIO_SYSSPACE); - if (error<>0) then - Writeln('mountroot: unable to unlink /dev/dev ', error); + //error:=kern_unlink('/dev/dev', UIO_SYSSPACE); + //if (error<>0) then + // Writeln('mountroot: unable to unlink /dev/dev ', error); end; Exit(0); @@ -332,26 +335,23 @@ begin end; procedure vfs_mountroot(); +label + _end; var mp:p_mount; - //opt:p_vfsoptlist; error:Integer; begin mtx_lock(VFS_Giant); error:=vfs_mountroot_devfs(@mp); + if (error<>0) then goto _end; - //opt:=nil; - //vfs_domount('fdescfs','/dev/fd',MNT_RDONLY,@opt); + error:=vfs_mountroot_simple('nullfs','/','',nil,MNT_RDONLY or MNT_ROOTFS); + if (error<>0) then goto _end; - //error:=vfs_mountroot_simple('fdescfs','/dev/fd','',nil,0); - //error:=vfs_mountroot_simple('fdescfs','/fd','',nil,0); - - //if (error=0) then - //begin - // error:=vfs_mountroot_shuffle(mp); - //end; + error:=vfs_mountroot_shuffle(mp); +_end: mtx_unlock(VFS_Giant); end; diff --git a/sys/vfs/vfs_subr.pas b/sys/vfs/vfs_subr.pas index 03d94a47..5c7d5292 100644 --- a/sys/vfs/vfs_subr.pas +++ b/sys/vfs/vfs_subr.pas @@ -10,7 +10,7 @@ uses vmount, vfile, vstat, - vfs_vnode, + vnode, vnode_if, vdirent, vfcntl, @@ -45,14 +45,14 @@ procedure vgone(vp:p_vnode); function vget(vp:p_vnode;flags:Integer):Integer; procedure vref(vp:p_vnode); +function vrefcnt(vp:p_vnode):Integer; procedure vrele(vp:p_vnode); procedure vput(vp:p_vnode); +procedure vunref(vp:p_vnode); procedure vinactive(vp:p_vnode); function vflush(mp:p_mount;rootrefs,flags:Integer):Integer; -procedure vfs_notify_upper(vp:p_vnode;event:Integer); - procedure assert_vi_locked (vp:p_vnode;str:PChar); procedure assert_vi_unlocked (vp:p_vnode;str:PChar); procedure assert_vop_locked (vp:p_vnode;str:PChar); @@ -122,18 +122,6 @@ procedure __mnt_vnode_markerfree_active(mvp:pp_vnode;mp:p_mount); procedure vntblinit; //SYSINIT(vfs, SI_SUB_VFS, SI_ORDER_FIRST, vntblinit, NULL); procedure vnlru_proc(); //SYSINIT(vnlru, SI_SUB_KTHREAD_UPDATE, SI_ORDER_FIRST, kproc_start, @vnlru_kp); -implementation - -uses - errno, - vfs_vnops, - subr_uio, - vm_object, - vsys_generic, - dead_vnops, - rtprio, - kern_conf; - { * List of vnodes that are ready for recycling. } @@ -180,6 +168,18 @@ var freevnodes :Integer=0; vnlru_nowhere :Integer=0; +implementation + +uses + errno, + vfs_vnops, + subr_uio, + vm_object, + vsys_generic, + dead_vnops, + rtprio, + kern_conf; + { * Macros to control when a vnode is freed and recycled. All require * the vnode interlock. @@ -406,8 +406,9 @@ begin while (count<>0) do begin vp:=TAILQ_FIRST(@mp^.mnt_nvnodelist); - while (vp<>nil) and (vp^.v_type=VMARKER) do + while (vp<>nil) do begin + if (vp^.v_type<>VMARKER) then Break; vp:=TAILQ_NEXT(vp,@vp^.v_nmntvnodes); end; if (vp=nil) then @@ -705,7 +706,7 @@ var td:p_kthread; vp:p_vnode; //struct bufobj *bo; - error:Integer; + error,susp:Integer; begin vp:=nil; td:=curkthread; @@ -723,7 +724,13 @@ begin } if (freevnodes > wantfreevnodes) then vnlru_free(1); - error:=getnewvnode_wait(ord((mp<>nil) and ((mp^.mnt_kern_flag and MNTK_SUSPEND)<>0))); + + susp:=ord(False); + if (mp<>nil) then + begin + susp:=ord(((mp^.mnt_kern_flag and MNTK_SUSPEND)<>0)); + end; + error:=getnewvnode_wait(susp); System.InterlockedIncrement64(numvnodes); mtx_unlock(vnode_free_list_mtx); @@ -785,7 +792,7 @@ begin * E.g., nilfs uses vfs_hash_index() on the lower vnode for * its own hashing. } - vp^.v_hash:=ptrint(vp) shr vnsz2log; + vp^.v_hash:=ptruint(vp) shr vnsz2log; vpp^:=vp; Exit(0); @@ -2233,7 +2240,8 @@ begin } obj:=nil; //obj:=vp^.v_object; - if (obj<>nil) and ((obj^.flags and OBJ_MIGHTBEDIRTY)<>0) then + if (obj<>nil) then + if ((obj^.flags and OBJ_MIGHTBEDIRTY)<>0) then begin VM_OBJECT_LOCK(obj); //vm_object_page_clean(obj, 0, 0, OBJPC_NOSYNC); @@ -2432,87 +2440,6 @@ begin VI_UNLOCK(vp); end; -procedure notify_lowervp_vfs_dummy(mp:p_mount;lowervp:p_vnode); -begin -end; - -const - vgonel_vfsops:vfsops=( - vfs_mount :nil; - vfs_cmount :nil; - vfs_unmount :nil; - vfs_root :nil; - vfs_quotactl :nil; - vfs_statfs :nil; - vfs_sync :nil; - vfs_vget :nil; - vfs_fhtovp :nil; - vfs_checkexp :nil; - vfs_init :nil; - vfs_uninit :nil; - vfs_extattrctl :nil; - vfs_sysctl :nil; - vfs_susp_clean :nil; - vfs_reclaim_lowervp:@notify_lowervp_vfs_dummy; - vfs_unlink_lowervp :@notify_lowervp_vfs_dummy - ); - -{ - * Notify upper mounts about reclaimed or unlinked vnode. - } -procedure vfs_notify_upper(vp:p_vnode;event:Integer); -label - unlock; -var - mp,ump,mmp:p_mount; -begin - mp:=vp^.v_mount; - if (mp=nil) then - Exit; - - MNT_ILOCK(mp); - if TAILQ_EMPTY(@mp^.mnt_uppers) then - goto unlock; - MNT_IUNLOCK(mp); - mmp:=AllocMem(SizeOf(t_mount)); - mmp^.mnt_op:=@vgonel_vfsops; - mmp^.mnt_kern_flag:=mmp^.mnt_kern_flag or MNTK_MARKER; - MNT_ILOCK(mp); - mp^.mnt_kern_flag:=mmp^.mnt_kern_flag or MNTK_VGONE_UPPER; - - ump:=TAILQ_FIRST(@mp^.mnt_uppers); - while (ump<>nil) do - begin - if ((ump^.mnt_kern_flag and MNTK_MARKER)<>0) then - begin - ump:=TAILQ_NEXT(ump,@ump^.mnt_upper_link); - continue; - end; - TAILQ_INSERT_AFTER(@mp^.mnt_uppers, ump, mmp,@mmp^.mnt_upper_link); - MNT_IUNLOCK(mp); - case event of - VFS_NOTIFY_UPPER_RECLAIM: - VFS_RECLAIM_LOWERVP(ump, vp); - VFS_NOTIFY_UPPER_UNLINK: - VFS_UNLINK_LOWERVP(ump, vp); - else - Assert(false, 'invalid event'); - end; - MNT_ILOCK(mp); - ump:=TAILQ_NEXT(mmp,@mmp^.mnt_upper_link); - TAILQ_REMOVE(@mp^.mnt_uppers, mmp,@mmp^.mnt_upper_link); - end; - FreeMem(mmp); - mp^.mnt_kern_flag:=mp^.mnt_kern_flag and (not MNTK_VGONE_UPPER); - if ((mp^.mnt_kern_flag and MNTK_VGONE_WAITER)<>0) then - begin - mp^.mnt_kern_flag:=mp^.mnt_kern_flag and (not MNTK_VGONE_WAITER); - wakeup(@mp^.mnt_uppers); - end; -unlock: - MNT_IUNLOCK(mp); -end; - { * vgone, with the vp interlock held. } @@ -2540,7 +2467,6 @@ begin active:=vp^.v_usecount; oweinact:=(vp^.v_iflag and VI_OWEINACT); VI_UNLOCK(vp); - vfs_notify_upper(vp, VFS_NOTIFY_UPPER_RECLAIM); { * Clean out any buffers associated with the vnode. @@ -3074,6 +3000,7 @@ end; procedure vfs_badlock(msg,str:PChar;vp:p_vnode); begin + Writeln(msg,' ',str); Assert(false,RawByteString(msg)+' '+RawByteString(str)); end; @@ -3573,8 +3500,12 @@ begin mp:=vp^.v_mount; VFS_ASSERT_GIANT(mp); ASSERT_VOP_LOCKED(vp,'vfs_mark_atime'); - if (mp<>nil) and ((mp^.mnt_flag and (MNT_NOATIME or MNT_RDONLY))=0) then + + if (mp<>nil) then + if ((mp^.mnt_flag and (MNT_NOATIME or MNT_RDONLY))=0) then + begin VOP_MARKATIME(vp); + end; end; { @@ -3642,9 +3573,11 @@ begin MNT_ILOCK(mp); Assert(mvp^^.v_mount=mp, 'marker vnode mount list mismatch'); vp:=TAILQ_NEXT(mvp^,@mvp^^.v_nmntvnodes); - while (vp<>nil) and - ((vp^.v_type=VMARKER) or ((vp^.v_iflag and VI_DOOMED)<>0)) do + while (vp<>nil) do + begin + if not ((vp^.v_type=VMARKER) or ((vp^.v_iflag and VI_DOOMED)<>0)) then Break; vp:=TAILQ_NEXT(vp,@vp^.v_nmntvnodes); + end; { Check if we are done } if (vp=nil) then diff --git a/sys/vfs/vfs_syscalls.pas b/sys/vfs/vfs_syscalls.pas index 424c6383..cfffaace 100644 --- a/sys/vfs/vfs_syscalls.pas +++ b/sys/vfs/vfs_syscalls.pas @@ -18,7 +18,7 @@ uses vfilio, vdisk, vfs_mount, - vfs_vnode, + vnode, vfs_vnops, vfs_subr, vfs_lookup; @@ -100,8 +100,7 @@ uses kern_synch, kern_descrip, vnode_if, - sys_capability, - vm_object; + sys_capability; { * Sync each mounted filesystem. @@ -1395,7 +1394,6 @@ begin //if (error) // goto _out; - vfs_notify_upper(vp, VFS_NOTIFY_UPPER_UNLINK); error:=VOP_REMOVE(nd.ni_dvp, vp, @nd.ni_cnd); _out: @@ -2694,7 +2692,6 @@ restart: Exit(error); goto restart; end; - vfs_notify_upper(vp, VFS_NOTIFY_UPPER_UNLINK); error:=VOP_RMDIR(nd.ni_dvp, nd.ni_vp, @nd.ni_cnd); vn_finished_write(mp); _out: diff --git a/sys/vfs/vfs_vnops.pas b/sys/vfs/vfs_vnops.pas index 81ed55a7..1bd73e3b 100644 --- a/sys/vfs/vfs_vnops.pas +++ b/sys/vfs/vfs_vnops.pas @@ -13,7 +13,7 @@ uses vuio, vmparam, vfilio, - vfs_vnode; + vnode; function vn_lock(vp:p_vnode;flags:Integer):Integer; @@ -414,13 +414,15 @@ var mp:p_mount; error, lock_flags:Integer; begin + lock_flags:=LK_EXCLUSIVE; + if (vp^.v_type<>VFIFO) and ((flags and FWRITE)=0) and - (vp^.v_mount<>nil) and - ((p_mount(vp^.v_mount)^.mnt_kern_flag and MNTK_EXTENDED_SHARED)<>0) then - lock_flags:=LK_SHARED - else - lock_flags:=LK_EXCLUSIVE; + (vp^.v_mount<>nil) then + if ((p_mount(vp^.v_mount)^.mnt_kern_flag and MNTK_EXTENDED_SHARED)<>0) then + begin + lock_flags:=LK_SHARED; + end; VFS_ASSERT_GIANT(vp^.v_mount); @@ -714,8 +716,8 @@ begin __end:=uio^.uio_offset - 1; mtxp:=mtx_pool_find(mtxpool_sleep, fp); mtx_lock(mtxp^); - if (fp^.f_advice<>nil) and - (p_fadvise_info(fp^.f_advice)^.fa_advice=POSIX_FADV_NOREUSE) then + if (fp^.f_advice<>nil) then + if (p_fadvise_info(fp^.f_advice)^.fa_advice=POSIX_FADV_NOREUSE) then begin if (start<>0) and (p_fadvise_info(fp^.f_advice)^.fa_prevend + 1=start) then begin @@ -761,15 +763,26 @@ begin // bwillwrite(); ioflag:=IO_UNIT; if (vp^.v_type=VREG) and ((fp^.f_flag and O_APPEND)<>0) then + begin ioflag:=ioflag or IO_APPEND; + end; if ((fp^.f_flag and FNONBLOCK)<>0) then + begin ioflag:=ioflag or IO_NDELAY; + end; if ((fp^.f_flag and O_DIRECT)<>0) then + begin ioflag:=ioflag or IO_DIRECT; - if ((fp^.f_flag and O_FSYNC)<>0) or - ((vp^.v_mount<>nil) and - ((p_mount(vp^.v_mount)^.mnt_flag and MNT_SYNCHRONOUS)<>0)) then + end; + if ((fp^.f_flag and O_FSYNC)<>0) then + begin ioflag:=ioflag or IO_SYNC; + end; + if (vp^.v_mount<>nil) then + if ((p_mount(vp^.v_mount)^.mnt_flag and MNT_SYNCHRONOUS)<>0) then + begin + ioflag:=ioflag or IO_SYNC; + end; mp:=nil; if (vp^.v_type<>VCHR) then begin @@ -817,8 +830,8 @@ begin __end:=uio^.uio_offset - 1; mtxp:=mtx_pool_find(mtxpool_sleep, fp); mtx_lock(mtxp^); - if (fp^.f_advice<>nil) and - (p_fadvise_info(fp^.f_advice)^.fa_advice=POSIX_FADV_NOREUSE) then + if (fp^.f_advice<>nil) then + if (p_fadvise_info(fp^.f_advice)^.fa_advice=POSIX_FADV_NOREUSE) then begin if (start<>0) and (p_fadvise_info(fp^.f_advice)^.fa_prevend + 1=start) then begin @@ -872,10 +885,15 @@ begin foffset_lock_uio(fp, uio, flags); mp:=vp^.v_mount; + if (mp<>nil) then + if ((mp^.mnt_kern_flag and MNTK_NO_IOPF)=0) then + begin + error:=doio(fp, uio, flags or FOF_OFFSET); + goto out_last; + end; + if (uio^.uio_segflg<>UIO_USERSPACE) or (vp^.v_type<>VREG) or - ((mp<>nil) and - ((mp^.mnt_kern_flag and MNTK_NO_IOPF)=0)) or {(not vn_io_fault_enable)} false then begin error:=doio(fp, uio, flags or FOF_OFFSET); diff --git a/sys/vfs/vmount.pas b/sys/vfs/vmount.pas index 3757eb22..b3eb79b2 100644 --- a/sys/vfs/vmount.pas +++ b/sys/vfs/vmount.pas @@ -11,7 +11,7 @@ uses kern_mtx, kern_synch, kern_sig, - vfs_vnode; + vnode; const DFLTPHYS=(64*1024); @@ -240,7 +240,7 @@ type vfs_cmount_t =function (ma,data:Pointer;flags:QWORD):Integer; vfs_unmount_t =function (mp:p_mount;mntflags:Integer):Integer; vfs_root_t =function (mp:p_mount;flags:Integer;vpp:pp_vnode):Integer; - vfs_quotactl_t =function (mp:p_mount;cmds:Integer;uid:Integer;arg:Pointer):Integer; + vfs_quotactl_t =function (mp:p_mount;cmds,uid:Integer;arg:Pointer):Integer; vfs_statfs_t =function (mp:p_mount;sbp:p_statfs):Integer; vfs_sync_t =function (mp:p_mount;waitfor:Integer):Integer; vfs_vget_t =function (mp:p_mount;ino:DWORD;flags:Integer;vpp:pp_vnode):Integer; @@ -256,23 +256,21 @@ type p_vfsops=^vfsops; vfsops=packed record - vfs_mount :vfs_mount_t ; - vfs_cmount :vfs_cmount_t ; - vfs_unmount :vfs_unmount_t ; - vfs_root :vfs_root_t ; - vfs_quotactl :vfs_quotactl_t ; - vfs_statfs :vfs_statfs_t ; - vfs_sync :vfs_sync_t ; - vfs_vget :vfs_vget_t ; - vfs_fhtovp :vfs_fhtovp_t ; - vfs_checkexp :vfs_checkexp_t ; - vfs_init :vfs_init_t ; - vfs_uninit :vfs_uninit_t ; - vfs_extattrctl :vfs_extattrctl_t ; - vfs_sysctl :vfs_sysctl_t ; - vfs_susp_clean :vfs_susp_clean_t ; - vfs_reclaim_lowervp:vfs_notify_lowervp_t; - vfs_unlink_lowervp :vfs_notify_lowervp_t; + vfs_mount :vfs_mount_t ; + vfs_cmount :vfs_cmount_t ; + vfs_unmount :vfs_unmount_t ; + vfs_root :vfs_root_t ; + vfs_quotactl :vfs_quotactl_t ; + vfs_statfs :vfs_statfs_t ; + vfs_sync :vfs_sync_t ; + vfs_vget :vfs_vget_t ; + vfs_fhtovp :vfs_fhtovp_t ; + vfs_checkexp :vfs_checkexp_t ; + vfs_init :vfs_init_t ; + vfs_uninit :vfs_uninit_t ; + vfs_extattrctl:vfs_extattrctl_t; + vfs_sysctl :vfs_sysctl_t ; + vfs_susp_clean:vfs_susp_clean_t; end; { @@ -286,7 +284,7 @@ type vfsconf=packed record vfc_version :DWORD ; // ABI version number - vfc_name :array[0..MFSNAMELEN-1] of Char; // filesystem type name + vfc_name :array[0..MFSNAMELEN-1+4] of Char; // filesystem type name vfc_vfsops :p_vfsops ; // filesystem operations vector vfc_typenum :Integer ; // historic filesystem type number vfc_refcount:Integer ; // number mounted of this type @@ -397,12 +395,12 @@ function MNT_MTX(mp:p_mount):p_mtx; inline; procedure MNT_REF(mp:p_mount); inline; procedure MNT_REL(mp:p_mount); inline; -function VFS_NEEDSGIANT(mp:p_mount):Boolean; inline; +function VFS_NEEDSGIANT(mp:p_mount):Boolean; function VFS_LOCK_GIANT(mp:p_mount):Integer; procedure VFS_UNLOCK_GIANT(locked:Integer); procedure VFS_ASSERT_GIANT(mp:p_mount); -function VFS_PROLOGUE(mp:p_mount):Boolean; inline; +function VFS_PROLOGUE(mp:p_mount):Boolean; procedure VFS_EPILOGUE(_enable_stops:Boolean); inline; function VFS_MOUNT(mp:p_mount):Integer; @@ -411,8 +409,9 @@ function VFS_ROOT(mp:p_mount;flags:Integer;vpp:pp_vnode):Integer; function VFS_STATFS(mp:p_mount;sbp:p_statfs):Integer; function VFS_SYNC(mp:p_mount;WAIT:Integer):Integer; function VFS_VGET(mp:p_mount;ino:QWORD;flags:Integer;vpp:pp_vnode):Integer; -procedure VFS_RECLAIM_LOWERVP(mp:p_mount;vp:p_vnode); -procedure VFS_UNLINK_LOWERVP(mp:p_mount;vp:p_vnode); +function VFS_QUOTACTL(mp:p_mount;c,u:Integer;a:Pointer):Integer; +function VFS_FHTOVP(mp:p_mount;fidp:p_fid;flags:Integer;vpp:pp_vnode):Integer; +function VFS_EXTATTRCTL(mp:p_mount;c:Integer;fn:p_vnode;ns:Integer;n:PChar):Integer; procedure VFS_KNOTE_LOCKED(vp:p_vnode;hint:Integer); procedure VFS_KNOTE_UNLOCKED(vp:p_vnode;hint:Integer); @@ -464,9 +463,15 @@ begin end; end; -function VFS_NEEDSGIANT(mp:p_mount):Boolean; inline; +function VFS_NEEDSGIANT(mp:p_mount):Boolean; begin - Result:=(mp<>nil) and ((mp^.mnt_kern_flag and MNTK_MPSAFE)=0) ; + if (mp<>nil) then + begin + Result:=((mp^.mnt_kern_flag and MNTK_MPSAFE)=0); + end else + begin + Result:=False; + end; end; function VFS_LOCK_GIANT(mp:p_mount):Integer; @@ -491,9 +496,15 @@ begin mtx_assert(VFS_Giant); end; -function VFS_PROLOGUE(mp:p_mount):Boolean; inline; +function VFS_PROLOGUE(mp:p_mount):Boolean; begin - Result:=(mp<>nil) and ((mp^.mnt_vfc^.vfc_flags and VFCF_SBDRY)<>0) and (sigdeferstop<>0); + if (mp<>nil) then + begin + Result:=((mp^.mnt_vfc^.vfc_flags and VFCF_SBDRY)<>0) and (sigdeferstop<>0); + end else + begin + Result:=False; + end; end; procedure VFS_EPILOGUE(_enable_stops:Boolean); inline; @@ -559,28 +570,31 @@ begin VFS_EPILOGUE(_enable_stops); end; -procedure VFS_RECLAIM_LOWERVP(mp:p_mount;vp:p_vnode); +function VFS_QUOTACTL(mp:p_mount;c,u:Integer;a:Pointer):Integer; var _enable_stops:Boolean; begin - if (mp^.mnt_op^.vfs_reclaim_lowervp<>nil) then - begin - _enable_stops:=VFS_PROLOGUE(MP); - mp^.mnt_op^.vfs_reclaim_lowervp(mp,vp); - VFS_EPILOGUE(_enable_stops); - end; + _enable_stops:=VFS_PROLOGUE(MP); + Result:=mp^.mnt_op^.vfs_quotactl(mp,c,u,a); + VFS_EPILOGUE(_enable_stops); end; -procedure VFS_UNLINK_LOWERVP(mp:p_mount;vp:p_vnode); +function VFS_FHTOVP(mp:p_mount;fidp:p_fid;flags:Integer;vpp:pp_vnode):Integer; var _enable_stops:Boolean; begin - if (mp^.mnt_op^.vfs_unlink_lowervp<>nil) then - begin - _enable_stops:=VFS_PROLOGUE(MP); - mp^.mnt_op^.vfs_unlink_lowervp(mp,vp); - VFS_EPILOGUE(_enable_stops); - end; + _enable_stops:=VFS_PROLOGUE(MP); + Result:=mp^.mnt_op^.vfs_fhtovp(mp,fidp,flags,vpp); + VFS_EPILOGUE(_enable_stops); +end; + +function VFS_EXTATTRCTL(mp:p_mount;c:Integer;fn:p_vnode;ns:Integer;n:PChar):Integer; +var + _enable_stops:Boolean; +begin + _enable_stops:=VFS_PROLOGUE(MP); + Result:=mp^.mnt_op^.vfs_extattrctl(mp,c,fn,ns,n); + VFS_EPILOGUE(_enable_stops); end; procedure VFS_KNOTE_LOCKED(vp:p_vnode;hint:Integer); diff --git a/sys/vfs/vnamei.pas b/sys/vfs/vnamei.pas index ba4e00be..4b4bea6a 100644 --- a/sys/vfs/vnamei.pas +++ b/sys/vfs/vnamei.pas @@ -9,7 +9,7 @@ uses vcapability, vfcntl, vuio, - vfs_vnode, + vnode, kern_thr; const diff --git a/sys/vfs/vfs_vnode.pas b/sys/vfs/vnode.pas similarity index 77% rename from sys/vfs/vfs_vnode.pas rename to sys/vfs/vnode.pas index 2fc28c06..2d27bd8e 100644 --- a/sys/vfs/vfs_vnode.pas +++ b/sys/vfs/vnode.pas @@ -1,4 +1,4 @@ -unit vfs_vnode; +unit vnode; {$mode ObjFPC}{$H+} {$CALLING SysV_ABI_CDecl} @@ -85,7 +85,7 @@ const VSTAT_PERMS =VREAD_ATTRIBUTES or VREAD_ACL; //Permissions that allow to change the state of the file in any way. - VMODIFY_PERMS =VWRITE or VAPPEND or VADMIN_PERMS or VDELETE_CHILD or VDELETE; + VMODIFY_PERMS =VWRITE or VAPPEND or VADMIN_PERMS or VDELETE_CHILD or VDELETE; // vn_open_flags VN_OPEN_NOAUDIT=$00000001; @@ -116,10 +116,51 @@ const DFLTPHYS =(64 * 1024); MAXPHYS =(128 * 1024); + //Flags for vdesc_flags: + VDESC_MAX_VPS=16; + // Low order 16 flag bits are reserved for willrele flags for vp arguments. + VDESC_VP0_WILLRELE=$0001; + VDESC_VP1_WILLRELE=$0002; + VDESC_VP2_WILLRELE=$0004; + VDESC_VP3_WILLRELE=$0008; + VDESC_NOMAP_VPP =$0100; + VDESC_VPP_WILLRELE=$0200; + + { + * VDESC_NO_OFFSET is used to identify the end of the offset list + * and in places where no such field exists. + } + VDESC_NO_OFFSET=-1; + type p_accmode_t=^accmode_t; accmode_t=Integer; + { This structure describes the vnode operation taking place. } + p_vnodeop_desc=^t_vnodeop_desc; + t_vnodeop_desc=record + vdesc_name :PChar; { a readable name for debugging } + vdesc_call :Pointer; { Function to call } + + { + * These ops are used by bypass routines to map and locate arguments. + * Creds and procs are not needed in bypass routines, but sometimes + * they are useful to (for example) transport layers. + * Nameidata is useful because it has a cred in it. + } + vdesc_vp_offsets :PByte; { list ended by VDESC_NO_OFFSET } + vdesc_flags :Integer; { VDESC_* flags } + vdesc_vpp_offset :Integer; { return vpp location } + end; + + p_vop_generic_args=^t_vop_generic_args; + t_vop_generic_args=record + a_desc:p_vnodeop_desc; + //other random data follows, presumably + end; + + vop_bypass_t=function(ap:Pointer):Integer; + pp_vnode=^p_vnode; p_vnode=^t_vnode; @@ -262,12 +303,15 @@ type va_vaflags :DWORD; end; +function VOPARG_OFFSETTO(s_offset:Integer;struct_p:Pointer):Pointer; +function VCALL(c:Pointer):Integer; + procedure VI_LOCK(vp:p_vnode); function VI_TRYLOCK(vp:p_vnode):Boolean; procedure VI_UNLOCK(vp:p_vnode); function VI_MTX(vp:p_vnode):p_mtx; inline; -function IGNORE_LOCK(vp:p_vnode):Boolean; inline; +function IGNORE_LOCK(vp:p_vnode):Boolean; procedure vn_rangelock_unlock(vp:p_vnode;cookie:Pointer); procedure vn_rangelock_unlock_range(vp:p_vnode;cookie:Pointer;start,__end:Int64); @@ -279,6 +323,68 @@ var implementation +uses + vmount; + +function VOPARG_OFFSETTO(s_offset:Integer;struct_p:Pointer):Pointer; +begin + Result:=struct_p+s_offset; +end; + +function get_vp_cb(vp:p_vnode;offset:Pointer):Pointer; inline; +var + v:p_vop_vector; + p:Pointer; +begin + Result:=nil; + if (vp=nil) then Exit; + v:=vp^.v_op; + while (v<>nil) do + begin + p:=PPointer(Pointer(v)+ptrint(offset))^; + if (p<>nil) then + begin + Exit(p); + end; + p:=v^.vop_bypass; + if (p<>nil) then + begin + Exit(p); + end; + v:=v^.vop_default; + end; +end; + +function vcall_panic:Integer; inline; +begin + Assert(false,'filesystem goof: vcall_panic'); + Exit(2); +end; + +type + p_vop_vcall_args=^t_vop_vcall_args; + t_vop_vcall_args=record + a_desc:p_vnodeop_desc; + a_vp :p_vnode; + end; + +function VCALL(c:Pointer):Integer; +var + ap:p_vop_vcall_args; + s:Boolean; +begin + if (c=nil) then Exit(vcall_panic); + ap:=c; + if (ap^.a_desc=nil) then Exit(vcall_panic); + if (ap^.a_vp=nil) then Exit(vcall_panic); + if (ap^.a_desc^.vdesc_call=nil) then Exit(vcall_panic); + c:=get_vp_cb(ap^.a_vp,ap^.a_desc^.vdesc_call); + Assert(c<>nil,'VCALL'); + s:=VFS_PROLOGUE(ap^.a_vp^.v_mount); + Result:=vop_bypass_t(c)(ap); + VFS_EPILOGUE(s); +end; + procedure VI_LOCK(vp:p_vnode); begin mtx_lock(vp^.v_interlock); @@ -299,9 +405,10 @@ begin Result:=@vp^.v_interlock; end; -function IGNORE_LOCK(vp:p_vnode):Boolean; inline; +function IGNORE_LOCK(vp:p_vnode):Boolean; begin - Result:=(vp=nil) or (vp^.v_type=VCHR) or (vp^.v_type=VBAD); + if (vp=nil) then Exit(True); + Result:=(vp^.v_type=VCHR) or (vp^.v_type=VBAD); end; procedure vn_rangelock_unlock(vp:p_vnode;cookie:Pointer); diff --git a/sys/vfs/vnode_if.pas b/sys/vfs/vnode_if.pas index fa7aeaa0..8dda3bb6 100644 --- a/sys/vfs/vnode_if.pas +++ b/sys/vfs/vnode_if.pas @@ -1,3 +1,5 @@ +{This file is automatically generated by "vop_generator"} + unit vnode_if; interface @@ -6,7 +8,7 @@ interface {$CALLING SysV_ABI_CDecl} uses - vfs_vnode, + vnode, vnamei, vfile, vuio, @@ -29,11 +31,13 @@ type p_vop_islocked_args=^vop_islocked_args; vop_islocked_args=record - a_vp:p_vnode; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; end; p_vop_lookup_args=^vop_lookup_args; vop_lookup_args=record + a_gen:p_vnodeop_desc; a_dvp:p_vnode; a_vpp:pp_vnode; a_cnp:p_componentname; @@ -41,6 +45,7 @@ type p_vop_cachedlookup_args=^vop_cachedlookup_args; vop_cachedlookup_args=record + a_gen:p_vnodeop_desc; a_dvp:p_vnode; a_vpp:pp_vnode; a_cnp:p_componentname; @@ -48,6 +53,7 @@ type p_vop_create_args=^vop_create_args; vop_create_args=record + a_gen:p_vnodeop_desc; a_dvp:p_vnode; a_vpp:pp_vnode; a_cnp:p_componentname; @@ -56,6 +62,7 @@ type p_vop_whiteout_args=^vop_whiteout_args; vop_whiteout_args=record + a_gen :p_vnodeop_desc; a_dvp :p_vnode; a_cnp :p_componentname; a_flags:Integer; @@ -63,6 +70,7 @@ type p_vop_mknod_args=^vop_mknod_args; vop_mknod_args=record + a_gen:p_vnodeop_desc; a_dvp:p_vnode; a_vpp:pp_vnode; a_cnp:p_componentname; @@ -71,6 +79,7 @@ type p_vop_open_args=^vop_open_args; vop_open_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_mode:Integer; a_fp :p_file; @@ -78,41 +87,48 @@ type p_vop_close_args=^vop_close_args; vop_close_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_fflag:Integer; end; p_vop_access_args=^vop_access_args; vop_access_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_accmode:accmode_t; end; p_vop_accessx_args=^vop_accessx_args; vop_accessx_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_accmode:accmode_t; end; p_vop_getattr_args=^vop_getattr_args; vop_getattr_args=record + a_gen:p_vnodeop_desc; a_vp :p_vnode; a_vap:p_vattr; end; p_vop_setattr_args=^vop_setattr_args; vop_setattr_args=record + a_gen:p_vnodeop_desc; a_vp :p_vnode; a_vap:p_vattr; end; p_vop_markatime_args=^vop_markatime_args; vop_markatime_args=record - a_vp:p_vnode; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; end; p_vop_read_args=^vop_read_args; vop_read_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_uio :p_uio; a_ioflag:Integer; @@ -120,6 +136,7 @@ type p_vop_write_args=^vop_write_args; vop_write_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_uio :p_uio; a_ioflag:Integer; @@ -127,6 +144,7 @@ type p_vop_ioctl_args=^vop_ioctl_args; vop_ioctl_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_command:PtrUint; a_data :Pointer; @@ -135,30 +153,35 @@ type p_vop_poll_args=^vop_poll_args; vop_poll_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_events:Integer; end; p_vop_kqfilter_args=^vop_kqfilter_args; vop_kqfilter_args=record - a_vp:p_vnode; - a_kn:p_knote; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; + a_kn :p_knote; end; p_vop_revoke_args=^vop_revoke_args; vop_revoke_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_flags:Integer; end; p_vop_fsync_args=^vop_fsync_args; vop_fsync_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_waitfor:Integer; end; p_vop_remove_args=^vop_remove_args; vop_remove_args=record + a_gen:p_vnodeop_desc; a_dvp:p_vnode; a_vp :p_vnode; a_cnp:p_componentname; @@ -166,6 +189,7 @@ type p_vop_link_args=^vop_link_args; vop_link_args=record + a_gen :p_vnodeop_desc; a_tdvp:p_vnode; a_vp :p_vnode; a_cnp :p_componentname; @@ -173,6 +197,7 @@ type p_vop_rename_args=^vop_rename_args; vop_rename_args=record + a_gen :p_vnodeop_desc; a_fdvp:p_vnode; a_fvp :p_vnode; a_fcnp:p_componentname; @@ -183,6 +208,7 @@ type p_vop_mkdir_args=^vop_mkdir_args; vop_mkdir_args=record + a_gen:p_vnodeop_desc; a_dvp:p_vnode; a_vpp:pp_vnode; a_cnp:p_componentname; @@ -191,6 +217,7 @@ type p_vop_rmdir_args=^vop_rmdir_args; vop_rmdir_args=record + a_gen:p_vnodeop_desc; a_dvp:p_vnode; a_vp :p_vnode; a_cnp:p_componentname; @@ -198,6 +225,7 @@ type p_vop_symlink_args=^vop_symlink_args; vop_symlink_args=record + a_gen :p_vnodeop_desc; a_dvp :p_vnode; a_vpp :pp_vnode; a_cnp :p_componentname; @@ -207,6 +235,7 @@ type p_vop_readdir_args=^vop_readdir_args; vop_readdir_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_uio :p_uio; a_eofflag :PInteger; @@ -216,22 +245,26 @@ type p_vop_readlink_args=^vop_readlink_args; vop_readlink_args=record + a_gen:p_vnodeop_desc; a_vp :p_vnode; a_uio:p_uio; end; p_vop_inactive_args=^vop_inactive_args; vop_inactive_args=record - a_vp:p_vnode; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; end; p_vop_reclaim_args=^vop_reclaim_args; vop_reclaim_args=record - a_vp:p_vnode; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; end; p_vop_lock1_args=^vop_lock1_args; vop_lock1_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_flags:Integer; a_file :PChar; @@ -240,12 +273,14 @@ type p_vop_unlock_args=^vop_unlock_args; vop_unlock_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_flags:Integer; end; p_vop_bmap_args=^vop_bmap_args; vop_bmap_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_bn :daddr_t; a_bop :pp_bufobj; @@ -256,23 +291,27 @@ type p_vop_strategy_args=^vop_strategy_args; vop_strategy_args=record - a_vp:p_vnode; - a_bp:p_buf; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; + a_bp :p_buf; end; p_vop_getwritemount_args=^vop_getwritemount_args; vop_getwritemount_args=record + a_gen:p_vnodeop_desc; a_vp :p_vnode; a_mpp:pp_mount; end; p_vop_print_args=^vop_print_args; vop_print_args=record - a_vp:p_vnode; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; end; p_vop_pathconf_args=^vop_pathconf_args; vop_pathconf_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_name :Integer; a_retval:PPtrUint; @@ -280,6 +319,7 @@ type p_vop_advlock_args=^vop_advlock_args; vop_advlock_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_id :Pointer; a_op :Integer; @@ -289,6 +329,7 @@ type p_vop_advlockasync_args=^vop_advlockasync_args; vop_advlockasync_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_id :Pointer; a_op :Integer; @@ -300,17 +341,20 @@ type p_vop_advlockpurge_args=^vop_advlockpurge_args; vop_advlockpurge_args=record - a_vp:p_vnode; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; end; p_vop_reallocblks_args=^vop_reallocblks_args; vop_reallocblks_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_buflist:p_cluster_save; end; p_vop_getpages_args=^vop_getpages_args; vop_getpages_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_m :p_vm_page_t; a_count :Integer; @@ -320,6 +364,7 @@ type p_vop_putpages_args=^vop_putpages_args; vop_putpages_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_m :p_vm_page_t; a_count :Integer; @@ -330,6 +375,7 @@ type p_vop_getacl_args=^vop_getacl_args; vop_getacl_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_type:acl_type_t; a_aclp:p_acl; @@ -337,6 +383,7 @@ type p_vop_setacl_args=^vop_setacl_args; vop_setacl_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_type:acl_type_t; a_aclp:p_acl; @@ -344,6 +391,7 @@ type p_vop_aclcheck_args=^vop_aclcheck_args; vop_aclcheck_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_type:acl_type_t; a_aclp:p_acl; @@ -351,12 +399,14 @@ type p_vop_closeextattr_args=^vop_closeextattr_args; vop_closeextattr_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_commit:Integer; end; p_vop_getextattr_args=^vop_getextattr_args; vop_getextattr_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_attrnamespace:Integer; a_name :PChar; @@ -366,6 +416,7 @@ type p_vop_listextattr_args=^vop_listextattr_args; vop_listextattr_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_attrnamespace:Integer; a_uio :p_uio; @@ -374,11 +425,13 @@ type p_vop_openextattr_args=^vop_openextattr_args; vop_openextattr_args=record - a_vp:p_vnode; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; end; p_vop_deleteextattr_args=^vop_deleteextattr_args; vop_deleteextattr_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_attrnamespace:Integer; a_name :PChar; @@ -386,6 +439,7 @@ type p_vop_setextattr_args=^vop_setextattr_args; vop_setextattr_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_attrnamespace:Integer; a_name :PChar; @@ -394,18 +448,21 @@ type p_vop_setlabel_args=^vop_setlabel_args; vop_setlabel_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_label:p_label; end; p_vop_vptofh_args=^vop_vptofh_args; vop_vptofh_args=record + a_gen:p_vnodeop_desc; a_vp :p_vnode; a_fhp:p_fid; end; p_vop_vptocnp_args=^vop_vptocnp_args; vop_vptocnp_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_vpp :pp_vnode; a_buf :PChar; @@ -414,6 +471,7 @@ type p_vop_allocate_args=^vop_allocate_args; vop_allocate_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_offset:PPtrUint; a_len :PPtrUint; @@ -421,6 +479,7 @@ type p_vop_advise_args=^vop_advise_args; vop_advise_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_start :PtrUint; a___end :PtrUint; @@ -429,44 +488,52 @@ type p_vop_unp_bind_args=^vop_unp_bind_args; vop_unp_bind_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_socket:p_socket; end; p_vop_unp_connect_args=^vop_unp_connect_args; vop_unp_connect_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_socket:pp_socket; end; p_vop_unp_detach_args=^vop_unp_detach_args; vop_unp_detach_args=record - a_vp:p_vnode; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; end; p_vop_is_text_args=^vop_is_text_args; vop_is_text_args=record - a_vp:p_vnode; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; end; p_vop_set_text_args=^vop_set_text_args; vop_set_text_args=record - a_vp:p_vnode; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; end; p_vop_unset_text_args=^vop_unset_text_args; vop_unset_text_args=record - a_vp:p_vnode; + a_gen:p_vnodeop_desc; + a_vp :p_vnode; end; p_vop_get_writecount_args=^vop_get_writecount_args; vop_get_writecount_args=record + a_gen :p_vnodeop_desc; a_vp :p_vnode; a_writecount:PInteger; end; p_vop_add_writecount_args=^vop_add_writecount_args; vop_add_writecount_args=record + a_gen:p_vnodeop_desc; a_vp :p_vnode; a_inc:Integer; end; @@ -537,678 +604,1078 @@ type vop_get_writecount_t=function(ap:p_vop_get_writecount_args):Integer; vop_add_writecount_t=function(ap:p_vop_add_writecount_args):Integer; -function VOP_ISLOCKED(vp:p_vnode):Integer; -function VOP_LOOKUP(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname):Integer; -function VOP_CACHEDLOOKUP(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname):Integer; -function VOP_CREATE(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr):Integer; -function VOP_WHITEOUT(dvp:p_vnode;cnp:p_componentname;flags:Integer):Integer; -function VOP_MKNOD(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr):Integer; -function VOP_OPEN(vp:p_vnode;mode:Integer;fp:p_file):Integer; -function VOP_CLOSE(vp:p_vnode;fflag:Integer):Integer; -function VOP_ACCESS(vp:p_vnode;accmode:accmode_t):Integer; -function VOP_ACCESSX(vp:p_vnode;accmode:accmode_t):Integer; -function VOP_GETATTR(vp:p_vnode;vap:p_vattr):Integer; -function VOP_SETATTR(vp:p_vnode;vap:p_vattr):Integer; -function VOP_MARKATIME(vp:p_vnode):Integer; -function VOP_READ(vp:p_vnode;uio:p_uio;ioflag:Integer):Integer; -function VOP_WRITE(vp:p_vnode;uio:p_uio;ioflag:Integer):Integer; -function VOP_IOCTL(vp:p_vnode;command:PtrUint;data:Pointer;fflag:Integer):Integer; -function VOP_POLL(vp:p_vnode;events:Integer):Integer; -function VOP_KQFILTER(vp:p_vnode;kn:p_knote):Integer; -function VOP_REVOKE(vp:p_vnode;flags:Integer):Integer; -function VOP_FSYNC(vp:p_vnode;waitfor:Integer):Integer; -function VOP_REMOVE(dvp:p_vnode;vp:p_vnode;cnp:p_componentname):Integer; -function VOP_LINK(tdvp:p_vnode;vp:p_vnode;cnp:p_componentname):Integer; -function VOP_RENAME(fdvp:p_vnode;fvp:p_vnode;fcnp:p_componentname;tdvp:p_vnode;tvp:p_vnode;tcnp:p_componentname):Integer; -function VOP_MKDIR(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr):Integer; -function VOP_RMDIR(dvp:p_vnode;vp:p_vnode;cnp:p_componentname):Integer; -function VOP_SYMLINK(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr;target:PChar):Integer; -function VOP_READDIR(vp:p_vnode;uio:p_uio;eofflag:PInteger;ncookies:PInteger;cookies:PPPtrUint):Integer; -function VOP_READLINK(vp:p_vnode;uio:p_uio):Integer; -function VOP_INACTIVE(vp:p_vnode):Integer; -function VOP_RECLAIM(vp:p_vnode):Integer; -function VOP_LOCK(vp:p_vnode;flags:Integer;_file:PChar;line:Integer):Integer; -function VOP_UNLOCK(vp:p_vnode;flags:Integer):Integer; -function VOP_BMAP(vp:p_vnode;bn:daddr_t;bop:pp_bufobj;bnp:p_daddr_t;runp:PInteger;runb:PInteger):Integer; -function VOP_STRATEGY(vp:p_vnode;bp:p_buf):Integer; -function VOP_GETWRITEMOUNT(vp:p_vnode;mpp:pp_mount):Integer; -function VOP_PRINT(vp:p_vnode):Integer; -function VOP_PATHCONF(vp:p_vnode;name:Integer;retval:PPtrUint):Integer; -function VOP_ADVLOCK(vp:p_vnode;id:Pointer;op:Integer;fl:p_flock;flags:Integer):Integer; -function VOP_ADVLOCKASYNC(vp:p_vnode;id:Pointer;op:Integer;fl:p_flock;flags:Integer;task:p_task;cookiep:PPointer):Integer; -function VOP_ADVLOCKPURGE(vp:p_vnode):Integer; -function VOP_REALLOCBLKS(vp:p_vnode;buflist:p_cluster_save):Integer; -function VOP_GETPAGES(vp:p_vnode;m:p_vm_page_t;count:Integer;reqpage:Integer;offset:PtrUint):Integer; -function VOP_PUTPAGES(vp:p_vnode;m:p_vm_page_t;count:Integer;sync:Integer;rtvals:PInteger;offset:PtrUint):Integer; -function VOP_GETACL(vp:p_vnode;_type:acl_type_t;aclp:p_acl):Integer; -function VOP_SETACL(vp:p_vnode;_type:acl_type_t;aclp:p_acl):Integer; -function VOP_ACLCHECK(vp:p_vnode;_type:acl_type_t;aclp:p_acl):Integer; -function VOP_CLOSEEXTATTR(vp:p_vnode;commit:Integer):Integer; -function VOP_GETEXTATTR(vp:p_vnode;attrnamespace:Integer;name:PChar;uio:p_uio;size:PPtrUint):Integer; -function VOP_LISTEXTATTR(vp:p_vnode;attrnamespace:Integer;uio:p_uio;size:PPtrUint):Integer; -function VOP_OPENEXTATTR(vp:p_vnode):Integer; -function VOP_DELETEEXTATTR(vp:p_vnode;attrnamespace:Integer;name:PChar):Integer; -function VOP_SETEXTATTR(vp:p_vnode;attrnamespace:Integer;name:PChar;uio:p_uio):Integer; -function VOP_SETLABEL(vp:p_vnode;_label:p_label):Integer; -function VOP_VPTOFH(vp:p_vnode;fhp:p_fid):Integer; -function VOP_VPTOCNP(vp:p_vnode;vpp:pp_vnode;buf:PChar;buflen:PInteger):Integer; -function VOP_ALLOCATE(vp:p_vnode;offset:PPtrUint;len:PPtrUint):Integer; -function VOP_ADVISE(vp:p_vnode;start:PtrUint;__end:PtrUint;advice:Integer):Integer; -function VOP_UNP_BIND(vp:p_vnode;socket:p_socket):Integer; -function VOP_UNP_CONNECT(vp:p_vnode;socket:pp_socket):Integer; -function VOP_UNP_DETACH(vp:p_vnode):Integer; -function VOP_IS_TEXT(vp:p_vnode):Integer; -function VOP_SET_TEXT(vp:p_vnode):Integer; -function VOP_UNSET_TEXT(vp:p_vnode):Integer; +function VOP_ISLOCKED (vp:p_vnode):Integer; +function VOP_LOOKUP (dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname):Integer; +function VOP_CACHEDLOOKUP (dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname):Integer; +function VOP_CREATE (dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr):Integer; +function VOP_WHITEOUT (dvp:p_vnode;cnp:p_componentname;flags:Integer):Integer; +function VOP_MKNOD (dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr):Integer; +function VOP_OPEN (vp:p_vnode;mode:Integer;fp:p_file):Integer; +function VOP_CLOSE (vp:p_vnode;fflag:Integer):Integer; +function VOP_ACCESS (vp:p_vnode;accmode:accmode_t):Integer; +function VOP_ACCESSX (vp:p_vnode;accmode:accmode_t):Integer; +function VOP_GETATTR (vp:p_vnode;vap:p_vattr):Integer; +function VOP_SETATTR (vp:p_vnode;vap:p_vattr):Integer; +function VOP_MARKATIME (vp:p_vnode):Integer; +function VOP_READ (vp:p_vnode;uio:p_uio;ioflag:Integer):Integer; +function VOP_WRITE (vp:p_vnode;uio:p_uio;ioflag:Integer):Integer; +function VOP_IOCTL (vp:p_vnode;command:PtrUint;data:Pointer;fflag:Integer):Integer; +function VOP_POLL (vp:p_vnode;events:Integer):Integer; +function VOP_KQFILTER (vp:p_vnode;kn:p_knote):Integer; +function VOP_REVOKE (vp:p_vnode;flags:Integer):Integer; +function VOP_FSYNC (vp:p_vnode;waitfor:Integer):Integer; +function VOP_REMOVE (dvp:p_vnode;vp:p_vnode;cnp:p_componentname):Integer; +function VOP_LINK (tdvp:p_vnode;vp:p_vnode;cnp:p_componentname):Integer; +function VOP_RENAME (fdvp:p_vnode;fvp:p_vnode;fcnp:p_componentname;tdvp:p_vnode;tvp:p_vnode;tcnp:p_componentname):Integer; +function VOP_MKDIR (dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr):Integer; +function VOP_RMDIR (dvp:p_vnode;vp:p_vnode;cnp:p_componentname):Integer; +function VOP_SYMLINK (dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr;target:PChar):Integer; +function VOP_READDIR (vp:p_vnode;uio:p_uio;eofflag:PInteger;ncookies:PInteger;cookies:PPPtrUint):Integer; +function VOP_READLINK (vp:p_vnode;uio:p_uio):Integer; +function VOP_INACTIVE (vp:p_vnode):Integer; +function VOP_RECLAIM (vp:p_vnode):Integer; +function VOP_LOCK (vp:p_vnode;flags:Integer;_file:PChar;line:Integer):Integer; +function VOP_UNLOCK (vp:p_vnode;flags:Integer):Integer; +function VOP_BMAP (vp:p_vnode;bn:daddr_t;bop:pp_bufobj;bnp:p_daddr_t;runp:PInteger;runb:PInteger):Integer; +function VOP_STRATEGY (vp:p_vnode;bp:p_buf):Integer; +function VOP_GETWRITEMOUNT (vp:p_vnode;mpp:pp_mount):Integer; +function VOP_PRINT (vp:p_vnode):Integer; +function VOP_PATHCONF (vp:p_vnode;name:Integer;retval:PPtrUint):Integer; +function VOP_ADVLOCK (vp:p_vnode;id:Pointer;op:Integer;fl:p_flock;flags:Integer):Integer; +function VOP_ADVLOCKASYNC (vp:p_vnode;id:Pointer;op:Integer;fl:p_flock;flags:Integer;task:p_task;cookiep:PPointer):Integer; +function VOP_ADVLOCKPURGE (vp:p_vnode):Integer; +function VOP_REALLOCBLKS (vp:p_vnode;buflist:p_cluster_save):Integer; +function VOP_GETPAGES (vp:p_vnode;m:p_vm_page_t;count:Integer;reqpage:Integer;offset:PtrUint):Integer; +function VOP_PUTPAGES (vp:p_vnode;m:p_vm_page_t;count:Integer;sync:Integer;rtvals:PInteger;offset:PtrUint):Integer; +function VOP_GETACL (vp:p_vnode;_type:acl_type_t;aclp:p_acl):Integer; +function VOP_SETACL (vp:p_vnode;_type:acl_type_t;aclp:p_acl):Integer; +function VOP_ACLCHECK (vp:p_vnode;_type:acl_type_t;aclp:p_acl):Integer; +function VOP_CLOSEEXTATTR (vp:p_vnode;commit:Integer):Integer; +function VOP_GETEXTATTR (vp:p_vnode;attrnamespace:Integer;name:PChar;uio:p_uio;size:PPtrUint):Integer; +function VOP_LISTEXTATTR (vp:p_vnode;attrnamespace:Integer;uio:p_uio;size:PPtrUint):Integer; +function VOP_OPENEXTATTR (vp:p_vnode):Integer; +function VOP_DELETEEXTATTR (vp:p_vnode;attrnamespace:Integer;name:PChar):Integer; +function VOP_SETEXTATTR (vp:p_vnode;attrnamespace:Integer;name:PChar;uio:p_uio):Integer; +function VOP_SETLABEL (vp:p_vnode;_label:p_label):Integer; +function VOP_VPTOFH (vp:p_vnode;fhp:p_fid):Integer; +function VOP_VPTOCNP (vp:p_vnode;vpp:pp_vnode;buf:PChar;buflen:PInteger):Integer; +function VOP_ALLOCATE (vp:p_vnode;offset:PPtrUint;len:PPtrUint):Integer; +function VOP_ADVISE (vp:p_vnode;start:PtrUint;__end:PtrUint;advice:Integer):Integer; +function VOP_UNP_BIND (vp:p_vnode;socket:p_socket):Integer; +function VOP_UNP_CONNECT (vp:p_vnode;socket:pp_socket):Integer; +function VOP_UNP_DETACH (vp:p_vnode):Integer; +function VOP_IS_TEXT (vp:p_vnode):Integer; +function VOP_SET_TEXT (vp:p_vnode):Integer; +function VOP_UNSET_TEXT (vp:p_vnode):Integer; function VOP_GET_WRITECOUNT(vp:p_vnode;writecount:PInteger):Integer; function VOP_ADD_WRITECOUNT(vp:p_vnode;inc:Integer):Integer; +const + vop_islocked_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_islocked_args(nil)^.a_vp)),Byte(-1)); + vop_lookup_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_lookup_args(nil)^.a_dvp)),Byte(-1)); + vop_cachedlookup_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_cachedlookup_args(nil)^.a_dvp)),Byte(-1)); + vop_create_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_create_args(nil)^.a_dvp)),Byte(-1)); + vop_whiteout_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_whiteout_args(nil)^.a_dvp)),Byte(-1)); + vop_mknod_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_mknod_args(nil)^.a_dvp)),Byte(-1)); + vop_open_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_open_args(nil)^.a_vp)),Byte(-1)); + vop_close_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_close_args(nil)^.a_vp)),Byte(-1)); + vop_access_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_access_args(nil)^.a_vp)),Byte(-1)); + vop_accessx_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_accessx_args(nil)^.a_vp)),Byte(-1)); + vop_getattr_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_getattr_args(nil)^.a_vp)),Byte(-1)); + vop_setattr_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_setattr_args(nil)^.a_vp)),Byte(-1)); + vop_markatime_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_markatime_args(nil)^.a_vp)),Byte(-1)); + vop_read_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_read_args(nil)^.a_vp)),Byte(-1)); + vop_write_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_write_args(nil)^.a_vp)),Byte(-1)); + vop_ioctl_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_ioctl_args(nil)^.a_vp)),Byte(-1)); + vop_poll_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_poll_args(nil)^.a_vp)),Byte(-1)); + vop_kqfilter_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_kqfilter_args(nil)^.a_vp)),Byte(-1)); + vop_revoke_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_revoke_args(nil)^.a_vp)),Byte(-1)); + vop_fsync_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_fsync_args(nil)^.a_vp)),Byte(-1)); + vop_remove_vp_offsets :array[0..2] of Byte=(Byte(ptrint(@p_vop_remove_args(nil)^.a_dvp)),Byte(ptrint(@p_vop_remove_args(nil)^.a_vp)),Byte(-1)); + vop_link_vp_offsets :array[0..2] of Byte=(Byte(ptrint(@p_vop_link_args(nil)^.a_tdvp)),Byte(ptrint(@p_vop_link_args(nil)^.a_vp)),Byte(-1)); + vop_rename_vp_offsets :array[0..4] of Byte=(Byte(ptrint(@p_vop_rename_args(nil)^.a_fdvp)),Byte(ptrint(@p_vop_rename_args(nil)^.a_fvp)),Byte(ptrint(@p_vop_rename_args(nil)^.a_tdvp)),Byte(ptrint(@p_vop_rename_args(nil)^.a_tvp)),Byte(-1)); + vop_mkdir_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_mkdir_args(nil)^.a_dvp)),Byte(-1)); + vop_rmdir_vp_offsets :array[0..2] of Byte=(Byte(ptrint(@p_vop_rmdir_args(nil)^.a_dvp)),Byte(ptrint(@p_vop_rmdir_args(nil)^.a_vp)),Byte(-1)); + vop_symlink_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_symlink_args(nil)^.a_dvp)),Byte(-1)); + vop_readdir_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_readdir_args(nil)^.a_vp)),Byte(-1)); + vop_readlink_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_readlink_args(nil)^.a_vp)),Byte(-1)); + vop_inactive_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_inactive_args(nil)^.a_vp)),Byte(-1)); + vop_reclaim_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_reclaim_args(nil)^.a_vp)),Byte(-1)); + vop_lock1_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_lock1_args(nil)^.a_vp)),Byte(-1)); + vop_unlock_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_unlock_args(nil)^.a_vp)),Byte(-1)); + vop_bmap_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_bmap_args(nil)^.a_vp)),Byte(-1)); + vop_strategy_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_strategy_args(nil)^.a_vp)),Byte(-1)); + vop_getwritemount_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_getwritemount_args(nil)^.a_vp)),Byte(-1)); + vop_print_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_print_args(nil)^.a_vp)),Byte(-1)); + vop_pathconf_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_pathconf_args(nil)^.a_vp)),Byte(-1)); + vop_advlock_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_advlock_args(nil)^.a_vp)),Byte(-1)); + vop_advlockasync_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_advlockasync_args(nil)^.a_vp)),Byte(-1)); + vop_advlockpurge_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_advlockpurge_args(nil)^.a_vp)),Byte(-1)); + vop_reallocblks_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_reallocblks_args(nil)^.a_vp)),Byte(-1)); + vop_getpages_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_getpages_args(nil)^.a_vp)),Byte(-1)); + vop_putpages_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_putpages_args(nil)^.a_vp)),Byte(-1)); + vop_getacl_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_getacl_args(nil)^.a_vp)),Byte(-1)); + vop_setacl_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_setacl_args(nil)^.a_vp)),Byte(-1)); + vop_aclcheck_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_aclcheck_args(nil)^.a_vp)),Byte(-1)); + vop_closeextattr_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_closeextattr_args(nil)^.a_vp)),Byte(-1)); + vop_getextattr_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_getextattr_args(nil)^.a_vp)),Byte(-1)); + vop_listextattr_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_listextattr_args(nil)^.a_vp)),Byte(-1)); + vop_openextattr_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_openextattr_args(nil)^.a_vp)),Byte(-1)); + vop_deleteextattr_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_deleteextattr_args(nil)^.a_vp)),Byte(-1)); + vop_setextattr_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_setextattr_args(nil)^.a_vp)),Byte(-1)); + vop_setlabel_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_setlabel_args(nil)^.a_vp)),Byte(-1)); + vop_vptofh_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_vptofh_args(nil)^.a_vp)),Byte(-1)); + vop_vptocnp_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_vptocnp_args(nil)^.a_vp)),Byte(-1)); + vop_allocate_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_allocate_args(nil)^.a_vp)),Byte(-1)); + vop_advise_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_advise_args(nil)^.a_vp)),Byte(-1)); + vop_unp_bind_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_unp_bind_args(nil)^.a_vp)),Byte(-1)); + vop_unp_connect_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_unp_connect_args(nil)^.a_vp)),Byte(-1)); + vop_unp_detach_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_unp_detach_args(nil)^.a_vp)),Byte(-1)); + vop_is_text_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_is_text_args(nil)^.a_vp)),Byte(-1)); + vop_set_text_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_set_text_args(nil)^.a_vp)),Byte(-1)); + vop_unset_text_vp_offsets :array[0..1] of Byte=(Byte(ptrint(@p_vop_unset_text_args(nil)^.a_vp)),Byte(-1)); + vop_get_writecount_vp_offsets:array[0..1] of Byte=(Byte(ptrint(@p_vop_get_writecount_args(nil)^.a_vp)),Byte(-1)); + vop_add_writecount_vp_offsets:array[0..1] of Byte=(Byte(ptrint(@p_vop_add_writecount_args(nil)^.a_vp)),Byte(-1)); + + vop_default_desc:t_vnodeop_desc=( + vdesc_name :'default'; + vdesc_call :nil; + vdesc_vp_offsets :nil; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_islocked_desc:t_vnodeop_desc=( + vdesc_name :'vop_islocked'; + vdesc_call :@p_vop_vector(nil)^.vop_islocked; + vdesc_vp_offsets :@vop_islocked_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_lookup_desc:t_vnodeop_desc=( + vdesc_name :'vop_lookup'; + vdesc_call :@p_vop_vector(nil)^.vop_lookup; + vdesc_vp_offsets :@vop_lookup_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :Integer(ptrint(@p_vop_lookup_args(nil)^.a_vpp)); + ); + + vop_cachedlookup_desc:t_vnodeop_desc=( + vdesc_name :'vop_cachedlookup'; + vdesc_call :@p_vop_vector(nil)^.vop_cachedlookup; + vdesc_vp_offsets :@vop_cachedlookup_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :Integer(ptrint(@p_vop_cachedlookup_args(nil)^.a_vpp)); + ); + + vop_create_desc:t_vnodeop_desc=( + vdesc_name :'vop_create'; + vdesc_call :@p_vop_vector(nil)^.vop_create; + vdesc_vp_offsets :@vop_create_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :Integer(ptrint(@p_vop_create_args(nil)^.a_vpp)); + ); + + vop_whiteout_desc:t_vnodeop_desc=( + vdesc_name :'vop_whiteout'; + vdesc_call :@p_vop_vector(nil)^.vop_whiteout; + vdesc_vp_offsets :@vop_whiteout_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_mknod_desc:t_vnodeop_desc=( + vdesc_name :'vop_mknod'; + vdesc_call :@p_vop_vector(nil)^.vop_mknod; + vdesc_vp_offsets :@vop_mknod_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :Integer(ptrint(@p_vop_mknod_args(nil)^.a_vpp)); + ); + + vop_open_desc:t_vnodeop_desc=( + vdesc_name :'vop_open'; + vdesc_call :@p_vop_vector(nil)^.vop_open; + vdesc_vp_offsets :@vop_open_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_close_desc:t_vnodeop_desc=( + vdesc_name :'vop_close'; + vdesc_call :@p_vop_vector(nil)^.vop_close; + vdesc_vp_offsets :@vop_close_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_access_desc:t_vnodeop_desc=( + vdesc_name :'vop_access'; + vdesc_call :@p_vop_vector(nil)^.vop_access; + vdesc_vp_offsets :@vop_access_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_accessx_desc:t_vnodeop_desc=( + vdesc_name :'vop_accessx'; + vdesc_call :@p_vop_vector(nil)^.vop_accessx; + vdesc_vp_offsets :@vop_accessx_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_getattr_desc:t_vnodeop_desc=( + vdesc_name :'vop_getattr'; + vdesc_call :@p_vop_vector(nil)^.vop_getattr; + vdesc_vp_offsets :@vop_getattr_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_setattr_desc:t_vnodeop_desc=( + vdesc_name :'vop_setattr'; + vdesc_call :@p_vop_vector(nil)^.vop_setattr; + vdesc_vp_offsets :@vop_setattr_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_markatime_desc:t_vnodeop_desc=( + vdesc_name :'vop_markatime'; + vdesc_call :@p_vop_vector(nil)^.vop_markatime; + vdesc_vp_offsets :@vop_markatime_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_read_desc:t_vnodeop_desc=( + vdesc_name :'vop_read'; + vdesc_call :@p_vop_vector(nil)^.vop_read; + vdesc_vp_offsets :@vop_read_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_write_desc:t_vnodeop_desc=( + vdesc_name :'vop_write'; + vdesc_call :@p_vop_vector(nil)^.vop_write; + vdesc_vp_offsets :@vop_write_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_ioctl_desc:t_vnodeop_desc=( + vdesc_name :'vop_ioctl'; + vdesc_call :@p_vop_vector(nil)^.vop_ioctl; + vdesc_vp_offsets :@vop_ioctl_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_poll_desc:t_vnodeop_desc=( + vdesc_name :'vop_poll'; + vdesc_call :@p_vop_vector(nil)^.vop_poll; + vdesc_vp_offsets :@vop_poll_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_kqfilter_desc:t_vnodeop_desc=( + vdesc_name :'vop_kqfilter'; + vdesc_call :@p_vop_vector(nil)^.vop_kqfilter; + vdesc_vp_offsets :@vop_kqfilter_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_revoke_desc:t_vnodeop_desc=( + vdesc_name :'vop_revoke'; + vdesc_call :@p_vop_vector(nil)^.vop_revoke; + vdesc_vp_offsets :@vop_revoke_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_fsync_desc:t_vnodeop_desc=( + vdesc_name :'vop_fsync'; + vdesc_call :@p_vop_vector(nil)^.vop_fsync; + vdesc_vp_offsets :@vop_fsync_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_remove_desc:t_vnodeop_desc=( + vdesc_name :'vop_remove'; + vdesc_call :@p_vop_vector(nil)^.vop_remove; + vdesc_vp_offsets :@vop_remove_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_link_desc:t_vnodeop_desc=( + vdesc_name :'vop_link'; + vdesc_call :@p_vop_vector(nil)^.vop_link; + vdesc_vp_offsets :@vop_link_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_rename_desc:t_vnodeop_desc=( + vdesc_name :'vop_rename'; + vdesc_call :@p_vop_vector(nil)^.vop_rename; + vdesc_vp_offsets :@vop_rename_vp_offsets; + vdesc_flags :VDESC_VP0_WILLRELE or VDESC_VP1_WILLRELE or VDESC_VP2_WILLRELE or VDESC_VP3_WILLRELE; + vdesc_vpp_offset :-1; + ); + + vop_mkdir_desc:t_vnodeop_desc=( + vdesc_name :'vop_mkdir'; + vdesc_call :@p_vop_vector(nil)^.vop_mkdir; + vdesc_vp_offsets :@vop_mkdir_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :Integer(ptrint(@p_vop_mkdir_args(nil)^.a_vpp)); + ); + + vop_rmdir_desc:t_vnodeop_desc=( + vdesc_name :'vop_rmdir'; + vdesc_call :@p_vop_vector(nil)^.vop_rmdir; + vdesc_vp_offsets :@vop_rmdir_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_symlink_desc:t_vnodeop_desc=( + vdesc_name :'vop_symlink'; + vdesc_call :@p_vop_vector(nil)^.vop_symlink; + vdesc_vp_offsets :@vop_symlink_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :Integer(ptrint(@p_vop_symlink_args(nil)^.a_vpp)); + ); + + vop_readdir_desc:t_vnodeop_desc=( + vdesc_name :'vop_readdir'; + vdesc_call :@p_vop_vector(nil)^.vop_readdir; + vdesc_vp_offsets :@vop_readdir_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_readlink_desc:t_vnodeop_desc=( + vdesc_name :'vop_readlink'; + vdesc_call :@p_vop_vector(nil)^.vop_readlink; + vdesc_vp_offsets :@vop_readlink_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_inactive_desc:t_vnodeop_desc=( + vdesc_name :'vop_inactive'; + vdesc_call :@p_vop_vector(nil)^.vop_inactive; + vdesc_vp_offsets :@vop_inactive_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_reclaim_desc:t_vnodeop_desc=( + vdesc_name :'vop_reclaim'; + vdesc_call :@p_vop_vector(nil)^.vop_reclaim; + vdesc_vp_offsets :@vop_reclaim_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_lock1_desc:t_vnodeop_desc=( + vdesc_name :'vop_lock1'; + vdesc_call :@p_vop_vector(nil)^.vop_lock1; + vdesc_vp_offsets :@vop_lock1_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_unlock_desc:t_vnodeop_desc=( + vdesc_name :'vop_unlock'; + vdesc_call :@p_vop_vector(nil)^.vop_unlock; + vdesc_vp_offsets :@vop_unlock_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_bmap_desc:t_vnodeop_desc=( + vdesc_name :'vop_bmap'; + vdesc_call :@p_vop_vector(nil)^.vop_bmap; + vdesc_vp_offsets :@vop_bmap_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_strategy_desc:t_vnodeop_desc=( + vdesc_name :'vop_strategy'; + vdesc_call :@p_vop_vector(nil)^.vop_strategy; + vdesc_vp_offsets :@vop_strategy_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_getwritemount_desc:t_vnodeop_desc=( + vdesc_name :'vop_getwritemount'; + vdesc_call :@p_vop_vector(nil)^.vop_getwritemount; + vdesc_vp_offsets :@vop_getwritemount_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_print_desc:t_vnodeop_desc=( + vdesc_name :'vop_print'; + vdesc_call :@p_vop_vector(nil)^.vop_print; + vdesc_vp_offsets :@vop_print_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_pathconf_desc:t_vnodeop_desc=( + vdesc_name :'vop_pathconf'; + vdesc_call :@p_vop_vector(nil)^.vop_pathconf; + vdesc_vp_offsets :@vop_pathconf_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_advlock_desc:t_vnodeop_desc=( + vdesc_name :'vop_advlock'; + vdesc_call :@p_vop_vector(nil)^.vop_advlock; + vdesc_vp_offsets :@vop_advlock_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_advlockasync_desc:t_vnodeop_desc=( + vdesc_name :'vop_advlockasync'; + vdesc_call :@p_vop_vector(nil)^.vop_advlockasync; + vdesc_vp_offsets :@vop_advlockasync_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_advlockpurge_desc:t_vnodeop_desc=( + vdesc_name :'vop_advlockpurge'; + vdesc_call :@p_vop_vector(nil)^.vop_advlockpurge; + vdesc_vp_offsets :@vop_advlockpurge_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_reallocblks_desc:t_vnodeop_desc=( + vdesc_name :'vop_reallocblks'; + vdesc_call :@p_vop_vector(nil)^.vop_reallocblks; + vdesc_vp_offsets :@vop_reallocblks_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_getpages_desc:t_vnodeop_desc=( + vdesc_name :'vop_getpages'; + vdesc_call :@p_vop_vector(nil)^.vop_getpages; + vdesc_vp_offsets :@vop_getpages_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_putpages_desc:t_vnodeop_desc=( + vdesc_name :'vop_putpages'; + vdesc_call :@p_vop_vector(nil)^.vop_putpages; + vdesc_vp_offsets :@vop_putpages_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_getacl_desc:t_vnodeop_desc=( + vdesc_name :'vop_getacl'; + vdesc_call :@p_vop_vector(nil)^.vop_getacl; + vdesc_vp_offsets :@vop_getacl_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_setacl_desc:t_vnodeop_desc=( + vdesc_name :'vop_setacl'; + vdesc_call :@p_vop_vector(nil)^.vop_setacl; + vdesc_vp_offsets :@vop_setacl_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_aclcheck_desc:t_vnodeop_desc=( + vdesc_name :'vop_aclcheck'; + vdesc_call :@p_vop_vector(nil)^.vop_aclcheck; + vdesc_vp_offsets :@vop_aclcheck_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_closeextattr_desc:t_vnodeop_desc=( + vdesc_name :'vop_closeextattr'; + vdesc_call :@p_vop_vector(nil)^.vop_closeextattr; + vdesc_vp_offsets :@vop_closeextattr_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_getextattr_desc:t_vnodeop_desc=( + vdesc_name :'vop_getextattr'; + vdesc_call :@p_vop_vector(nil)^.vop_getextattr; + vdesc_vp_offsets :@vop_getextattr_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_listextattr_desc:t_vnodeop_desc=( + vdesc_name :'vop_listextattr'; + vdesc_call :@p_vop_vector(nil)^.vop_listextattr; + vdesc_vp_offsets :@vop_listextattr_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_openextattr_desc:t_vnodeop_desc=( + vdesc_name :'vop_openextattr'; + vdesc_call :@p_vop_vector(nil)^.vop_openextattr; + vdesc_vp_offsets :@vop_openextattr_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_deleteextattr_desc:t_vnodeop_desc=( + vdesc_name :'vop_deleteextattr'; + vdesc_call :@p_vop_vector(nil)^.vop_deleteextattr; + vdesc_vp_offsets :@vop_deleteextattr_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_setextattr_desc:t_vnodeop_desc=( + vdesc_name :'vop_setextattr'; + vdesc_call :@p_vop_vector(nil)^.vop_setextattr; + vdesc_vp_offsets :@vop_setextattr_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_setlabel_desc:t_vnodeop_desc=( + vdesc_name :'vop_setlabel'; + vdesc_call :@p_vop_vector(nil)^.vop_setlabel; + vdesc_vp_offsets :@vop_setlabel_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_vptofh_desc:t_vnodeop_desc=( + vdesc_name :'vop_vptofh'; + vdesc_call :@p_vop_vector(nil)^.vop_vptofh; + vdesc_vp_offsets :@vop_vptofh_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_vptocnp_desc:t_vnodeop_desc=( + vdesc_name :'vop_vptocnp'; + vdesc_call :@p_vop_vector(nil)^.vop_vptocnp; + vdesc_vp_offsets :@vop_vptocnp_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :Integer(ptrint(@p_vop_vptocnp_args(nil)^.a_vpp)); + ); + + vop_allocate_desc:t_vnodeop_desc=( + vdesc_name :'vop_allocate'; + vdesc_call :@p_vop_vector(nil)^.vop_allocate; + vdesc_vp_offsets :@vop_allocate_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_advise_desc:t_vnodeop_desc=( + vdesc_name :'vop_advise'; + vdesc_call :@p_vop_vector(nil)^.vop_advise; + vdesc_vp_offsets :@vop_advise_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_unp_bind_desc:t_vnodeop_desc=( + vdesc_name :'vop_unp_bind'; + vdesc_call :@p_vop_vector(nil)^.vop_unp_bind; + vdesc_vp_offsets :@vop_unp_bind_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_unp_connect_desc:t_vnodeop_desc=( + vdesc_name :'vop_unp_connect'; + vdesc_call :@p_vop_vector(nil)^.vop_unp_connect; + vdesc_vp_offsets :@vop_unp_connect_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_unp_detach_desc:t_vnodeop_desc=( + vdesc_name :'vop_unp_detach'; + vdesc_call :@p_vop_vector(nil)^.vop_unp_detach; + vdesc_vp_offsets :@vop_unp_detach_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_is_text_desc:t_vnodeop_desc=( + vdesc_name :'vop_is_text'; + vdesc_call :@p_vop_vector(nil)^.vop_is_text; + vdesc_vp_offsets :@vop_is_text_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_set_text_desc:t_vnodeop_desc=( + vdesc_name :'vop_set_text'; + vdesc_call :@p_vop_vector(nil)^.vop_set_text; + vdesc_vp_offsets :@vop_set_text_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_unset_text_desc:t_vnodeop_desc=( + vdesc_name :'vop_unset_text'; + vdesc_call :@p_vop_vector(nil)^.vop_unset_text; + vdesc_vp_offsets :@vop_unset_text_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_get_writecount_desc:t_vnodeop_desc=( + vdesc_name :'vop_get_writecount'; + vdesc_call :@p_vop_vector(nil)^.vop_get_writecount; + vdesc_vp_offsets :@vop_get_writecount_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + + vop_add_writecount_desc:t_vnodeop_desc=( + vdesc_name :'vop_add_writecount'; + vdesc_call :@p_vop_vector(nil)^.vop_add_writecount; + vdesc_vp_offsets :@vop_add_writecount_vp_offsets; + vdesc_flags :0; + vdesc_vpp_offset :-1; + ); + implementation uses + errno, vfs_subr; -function VOP_ISLOCKED(vp:p_vnode):Integer; +function get_vp_cb(vp:p_vnode;offset:Pointer):Pointer; inline; var v:p_vop_vector; - s:Boolean; + p:Pointer; begin + Result:=nil; + if (vp=nil) then Exit; v:=vp^.v_op; while (v<>nil) do begin - if (v^.vop_islocked<>nil) or (v^.vop_bypass<>nil) then Break; + p:=PPointer(Pointer(v)+ptrint(offset))^; + if (p<>nil) then + begin + Exit(p); + end; + p:=v^.vop_bypass; + if (p<>nil) then + begin + Exit(p); + end; v:=v^.vop_default; end; - Assert(v<>nil,'VOP_ISLOCKED'); +end; + +function VOP_ISLOCKED(vp:p_vnode):Integer; +var + c:Pointer; + a:vop_islocked_args; + s:Boolean; +begin + c:=get_vp_cb(vp,vop_islocked_desc.vdesc_call); + Assert(c<>nil,'VOP_ISLOCKED'); + a.a_gen:=@vop_islocked_desc; + a.a_vp :=vp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_islocked<>nil) then - begin - Result:=vop_islocked_t(v^.vop_islocked)(@vp); - end else - begin - Result:=vop_islocked_t(v^.vop_bypass)(@vp); - end; + Result:=vop_islocked_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_LOOKUP(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_lookup_args; s:Boolean; begin - v:=dvp^.v_op; - while (v<>nil) do - begin - if (v^.vop_lookup<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_LOOKUP'); + c:=get_vp_cb(dvp,vop_lookup_desc.vdesc_call); + Assert(c<>nil,'VOP_LOOKUP'); + a.a_gen:=@vop_lookup_desc; a.a_dvp:=dvp; a.a_vpp:=vpp; a.a_cnp:=cnp; s:=VFS_PROLOGUE(dvp^.v_mount); - if (v^.vop_lookup<>nil) then - begin - Result:=vop_lookup_t(v^.vop_lookup)(@a); - end else - begin - Result:=vop_lookup_t(v^.vop_bypass)(@a); - end; + Result:=vop_lookup_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_CACHEDLOOKUP(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_cachedlookup_args; s:Boolean; begin - v:=dvp^.v_op; - while (v<>nil) do - begin - if (v^.vop_cachedlookup<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_CACHEDLOOKUP'); + c:=get_vp_cb(dvp,vop_cachedlookup_desc.vdesc_call); + Assert(c<>nil,'VOP_CACHEDLOOKUP'); + a.a_gen:=@vop_cachedlookup_desc; a.a_dvp:=dvp; a.a_vpp:=vpp; a.a_cnp:=cnp; s:=VFS_PROLOGUE(dvp^.v_mount); - if (v^.vop_cachedlookup<>nil) then - begin - Result:=vop_cachedlookup_t(v^.vop_cachedlookup)(@a); - end else - begin - Result:=vop_cachedlookup_t(v^.vop_bypass)(@a); - end; + Result:=vop_cachedlookup_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_CREATE(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_create_args; s:Boolean; begin - v:=dvp^.v_op; - while (v<>nil) do - begin - if (v^.vop_create<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_CREATE'); + c:=get_vp_cb(dvp,vop_create_desc.vdesc_call); + Assert(c<>nil,'VOP_CREATE'); + a.a_gen:=@vop_create_desc; a.a_dvp:=dvp; a.a_vpp:=vpp; a.a_cnp:=cnp; a.a_vap:=vap; s:=VFS_PROLOGUE(dvp^.v_mount); - if (v^.vop_create<>nil) then - begin - Result:=vop_create_t(v^.vop_create)(@a); - end else - begin - Result:=vop_create_t(v^.vop_bypass)(@a); - end; + Result:=vop_create_t(c)(@a); VFS_EPILOGUE(s); vop_create_post(@a,Result); end; function VOP_WHITEOUT(dvp:p_vnode;cnp:p_componentname;flags:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_whiteout_args; s:Boolean; begin - v:=dvp^.v_op; - while (v<>nil) do - begin - if (v^.vop_whiteout<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_WHITEOUT'); + c:=get_vp_cb(dvp,vop_whiteout_desc.vdesc_call); + Assert(c<>nil,'VOP_WHITEOUT'); + a.a_gen :=@vop_whiteout_desc; a.a_dvp :=dvp; a.a_cnp :=cnp; a.a_flags:=flags; s:=VFS_PROLOGUE(dvp^.v_mount); - if (v^.vop_whiteout<>nil) then - begin - Result:=vop_whiteout_t(v^.vop_whiteout)(@a); - end else - begin - Result:=vop_whiteout_t(v^.vop_bypass)(@a); - end; + Result:=vop_whiteout_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_MKNOD(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_mknod_args; s:Boolean; begin - v:=dvp^.v_op; - while (v<>nil) do - begin - if (v^.vop_mknod<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_MKNOD'); + c:=get_vp_cb(dvp,vop_mknod_desc.vdesc_call); + Assert(c<>nil,'VOP_MKNOD'); + a.a_gen:=@vop_mknod_desc; a.a_dvp:=dvp; a.a_vpp:=vpp; a.a_cnp:=cnp; a.a_vap:=vap; s:=VFS_PROLOGUE(dvp^.v_mount); - if (v^.vop_mknod<>nil) then - begin - Result:=vop_mknod_t(v^.vop_mknod)(@a); - end else - begin - Result:=vop_mknod_t(v^.vop_bypass)(@a); - end; + Result:=vop_mknod_t(c)(@a); VFS_EPILOGUE(s); vop_mknod_post(@a,Result); end; function VOP_OPEN(vp:p_vnode;mode:Integer;fp:p_file):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_open_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_open<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_OPEN'); + c:=get_vp_cb(vp,vop_open_desc.vdesc_call); + Assert(c<>nil,'VOP_OPEN'); + a.a_gen :=@vop_open_desc; a.a_vp :=vp; a.a_mode:=mode; a.a_fp :=fp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_open<>nil) then - begin - Result:=vop_open_t(v^.vop_open)(@a); - end else - begin - Result:=vop_open_t(v^.vop_bypass)(@a); - end; + Result:=vop_open_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_CLOSE(vp:p_vnode;fflag:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_close_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_close<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_CLOSE'); + c:=get_vp_cb(vp,vop_close_desc.vdesc_call); + Assert(c<>nil,'VOP_CLOSE'); + a.a_gen :=@vop_close_desc; a.a_vp :=vp; a.a_fflag:=fflag; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_close<>nil) then - begin - Result:=vop_close_t(v^.vop_close)(@a); - end else - begin - Result:=vop_close_t(v^.vop_bypass)(@a); - end; + Result:=vop_close_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_ACCESS(vp:p_vnode;accmode:accmode_t):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_access_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_access<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_ACCESS'); + c:=get_vp_cb(vp,vop_access_desc.vdesc_call); + Assert(c<>nil,'VOP_ACCESS'); + a.a_gen :=@vop_access_desc; a.a_vp :=vp; a.a_accmode:=accmode; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_access<>nil) then - begin - Result:=vop_access_t(v^.vop_access)(@a); - end else - begin - Result:=vop_access_t(v^.vop_bypass)(@a); - end; + Result:=vop_access_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_ACCESSX(vp:p_vnode;accmode:accmode_t):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_accessx_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_accessx<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_ACCESSX'); + c:=get_vp_cb(vp,vop_accessx_desc.vdesc_call); + Assert(c<>nil,'VOP_ACCESSX'); + a.a_gen :=@vop_accessx_desc; a.a_vp :=vp; a.a_accmode:=accmode; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_accessx<>nil) then - begin - Result:=vop_accessx_t(v^.vop_accessx)(@a); - end else - begin - Result:=vop_accessx_t(v^.vop_bypass)(@a); - end; + Result:=vop_accessx_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_GETATTR(vp:p_vnode;vap:p_vattr):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_getattr_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_getattr<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_GETATTR'); + c:=get_vp_cb(vp,vop_getattr_desc.vdesc_call); + Assert(c<>nil,'VOP_GETATTR'); + a.a_gen:=@vop_getattr_desc; a.a_vp :=vp; a.a_vap:=vap; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_getattr<>nil) then - begin - Result:=vop_getattr_t(v^.vop_getattr)(@a); - end else - begin - Result:=vop_getattr_t(v^.vop_bypass)(@a); - end; + Result:=vop_getattr_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_SETATTR(vp:p_vnode;vap:p_vattr):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_setattr_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_setattr<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_SETATTR'); + c:=get_vp_cb(vp,vop_setattr_desc.vdesc_call); + Assert(c<>nil,'VOP_SETATTR'); + a.a_gen:=@vop_setattr_desc; a.a_vp :=vp; a.a_vap:=vap; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_setattr<>nil) then - begin - Result:=vop_setattr_t(v^.vop_setattr)(@a); - end else - begin - Result:=vop_setattr_t(v^.vop_bypass)(@a); - end; + Result:=vop_setattr_t(c)(@a); VFS_EPILOGUE(s); vop_setattr_post(@a,Result); end; function VOP_MARKATIME(vp:p_vnode):Integer; var - v:p_vop_vector; + c:Pointer; + a:vop_markatime_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_markatime<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_MARKATIME'); + c:=get_vp_cb(vp,vop_markatime_desc.vdesc_call); + Assert(c<>nil,'VOP_MARKATIME'); + a.a_gen:=@vop_markatime_desc; + a.a_vp :=vp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_markatime<>nil) then - begin - Result:=vop_markatime_t(v^.vop_markatime)(@vp); - end else - begin - Result:=vop_markatime_t(v^.vop_bypass)(@vp); - end; + Result:=vop_markatime_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_READ(vp:p_vnode;uio:p_uio;ioflag:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_read_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_read<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_READ'); + c:=get_vp_cb(vp,vop_read_desc.vdesc_call); + Assert(c<>nil,'VOP_READ'); + a.a_gen :=@vop_read_desc; a.a_vp :=vp; a.a_uio :=uio; a.a_ioflag:=ioflag; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_read<>nil) then - begin - Result:=vop_read_t(v^.vop_read)(@a); - end else - begin - Result:=vop_read_t(v^.vop_bypass)(@a); - end; + Result:=vop_read_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_WRITE(vp:p_vnode;uio:p_uio;ioflag:Integer):Integer; var osize,ooffset:Int64; - v:p_vop_vector; + c:Pointer; a:vop_write_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_write<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_WRITE'); + c:=get_vp_cb(vp,vop_write_desc.vdesc_call); + Assert(c<>nil,'VOP_WRITE'); + a.a_gen :=@vop_write_desc; a.a_vp :=vp; a.a_uio :=uio; a.a_ioflag:=ioflag; VOP_WRITE_PRE(@a,osize,ooffset); s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_write<>nil) then - begin - Result:=vop_write_t(v^.vop_write)(@a); - end else - begin - Result:=vop_write_t(v^.vop_bypass)(@a); - end; + Result:=vop_write_t(c)(@a); VFS_EPILOGUE(s); VOP_WRITE_POST(@a,Result,osize,ooffset); end; function VOP_IOCTL(vp:p_vnode;command:PtrUint;data:Pointer;fflag:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_ioctl_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_ioctl<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_IOCTL'); + c:=get_vp_cb(vp,vop_ioctl_desc.vdesc_call); + Assert(c<>nil,'VOP_IOCTL'); + a.a_gen :=@vop_ioctl_desc; a.a_vp :=vp; a.a_command:=command; a.a_data :=data; a.a_fflag :=fflag; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_ioctl<>nil) then - begin - Result:=vop_ioctl_t(v^.vop_ioctl)(@a); - end else - begin - Result:=vop_ioctl_t(v^.vop_bypass)(@a); - end; + Result:=vop_ioctl_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_POLL(vp:p_vnode;events:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_poll_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_poll<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_POLL'); + c:=get_vp_cb(vp,vop_poll_desc.vdesc_call); + Assert(c<>nil,'VOP_POLL'); + a.a_gen :=@vop_poll_desc; a.a_vp :=vp; a.a_events:=events; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_poll<>nil) then - begin - Result:=vop_poll_t(v^.vop_poll)(@a); - end else - begin - Result:=vop_poll_t(v^.vop_bypass)(@a); - end; + Result:=vop_poll_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_KQFILTER(vp:p_vnode;kn:p_knote):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_kqfilter_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_kqfilter<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_KQFILTER'); - a.a_vp:=vp; - a.a_kn:=kn; + c:=get_vp_cb(vp,vop_kqfilter_desc.vdesc_call); + Assert(c<>nil,'VOP_KQFILTER'); + a.a_gen:=@vop_kqfilter_desc; + a.a_vp :=vp; + a.a_kn :=kn; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_kqfilter<>nil) then - begin - Result:=vop_kqfilter_t(v^.vop_kqfilter)(@a); - end else - begin - Result:=vop_kqfilter_t(v^.vop_bypass)(@a); - end; + Result:=vop_kqfilter_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_REVOKE(vp:p_vnode;flags:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_revoke_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_revoke<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_REVOKE'); + c:=get_vp_cb(vp,vop_revoke_desc.vdesc_call); + Assert(c<>nil,'VOP_REVOKE'); + a.a_gen :=@vop_revoke_desc; a.a_vp :=vp; a.a_flags:=flags; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_revoke<>nil) then - begin - Result:=vop_revoke_t(v^.vop_revoke)(@a); - end else - begin - Result:=vop_revoke_t(v^.vop_bypass)(@a); - end; + Result:=vop_revoke_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_FSYNC(vp:p_vnode;waitfor:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_fsync_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_fsync<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_FSYNC'); + c:=get_vp_cb(vp,vop_fsync_desc.vdesc_call); + Assert(c<>nil,'VOP_FSYNC'); + a.a_gen :=@vop_fsync_desc; a.a_vp :=vp; a.a_waitfor:=waitfor; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_fsync<>nil) then - begin - Result:=vop_fsync_t(v^.vop_fsync)(@a); - end else - begin - Result:=vop_fsync_t(v^.vop_bypass)(@a); - end; + Result:=vop_fsync_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_REMOVE(dvp:p_vnode;vp:p_vnode;cnp:p_componentname):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_remove_args; s:Boolean; begin - v:=dvp^.v_op; - while (v<>nil) do - begin - if (v^.vop_remove<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_REMOVE'); + c:=get_vp_cb(dvp,vop_remove_desc.vdesc_call); + Assert(c<>nil,'VOP_REMOVE'); + a.a_gen:=@vop_remove_desc; a.a_dvp:=dvp; a.a_vp :=vp; a.a_cnp:=cnp; s:=VFS_PROLOGUE(dvp^.v_mount); - if (v^.vop_remove<>nil) then - begin - Result:=vop_remove_t(v^.vop_remove)(@a); - end else - begin - Result:=vop_remove_t(v^.vop_bypass)(@a); - end; + Result:=vop_remove_t(c)(@a); VFS_EPILOGUE(s); vop_remove_post(@a,Result); end; function VOP_LINK(tdvp:p_vnode;vp:p_vnode;cnp:p_componentname):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_link_args; s:Boolean; begin - v:=tdvp^.v_op; - while (v<>nil) do - begin - if (v^.vop_link<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_LINK'); + c:=get_vp_cb(tdvp,vop_link_desc.vdesc_call); + Assert(c<>nil,'VOP_LINK'); + a.a_gen :=@vop_link_desc; a.a_tdvp:=tdvp; a.a_vp :=vp; a.a_cnp :=cnp; s:=VFS_PROLOGUE(tdvp^.v_mount); - if (v^.vop_link<>nil) then - begin - Result:=vop_link_t(v^.vop_link)(@a); - end else - begin - Result:=vop_link_t(v^.vop_bypass)(@a); - end; + Result:=vop_link_t(c)(@a); VFS_EPILOGUE(s); vop_link_post(@a,Result); end; function VOP_RENAME(fdvp:p_vnode;fvp:p_vnode;fcnp:p_componentname;tdvp:p_vnode;tvp:p_vnode;tcnp:p_componentname):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_rename_args; s:Boolean; begin - v:=fdvp^.v_op; - while (v<>nil) do - begin - if (v^.vop_rename<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_RENAME'); + c:=get_vp_cb(fdvp,vop_rename_desc.vdesc_call); + Assert(c<>nil,'VOP_RENAME'); + a.a_gen :=@vop_rename_desc; a.a_fdvp:=fdvp; a.a_fvp :=fvp; a.a_fcnp:=fcnp; @@ -1217,272 +1684,176 @@ begin a.a_tcnp:=tcnp; vop_rename_pre(@a); s:=VFS_PROLOGUE(fdvp^.v_mount); - if (v^.vop_rename<>nil) then - begin - Result:=vop_rename_t(v^.vop_rename)(@a); - end else - begin - Result:=vop_rename_t(v^.vop_bypass)(@a); - end; + Result:=vop_rename_t(c)(@a); VFS_EPILOGUE(s); vop_rename_post(@a,Result); end; function VOP_MKDIR(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_mkdir_args; s:Boolean; begin - v:=dvp^.v_op; - while (v<>nil) do - begin - if (v^.vop_mkdir<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_MKDIR'); + c:=get_vp_cb(dvp,vop_mkdir_desc.vdesc_call); + Assert(c<>nil,'VOP_MKDIR'); + a.a_gen:=@vop_mkdir_desc; a.a_dvp:=dvp; a.a_vpp:=vpp; a.a_cnp:=cnp; a.a_vap:=vap; s:=VFS_PROLOGUE(dvp^.v_mount); - if (v^.vop_mkdir<>nil) then - begin - Result:=vop_mkdir_t(v^.vop_mkdir)(@a); - end else - begin - Result:=vop_mkdir_t(v^.vop_bypass)(@a); - end; + Result:=vop_mkdir_t(c)(@a); VFS_EPILOGUE(s); vop_mkdir_post(@a,Result); end; function VOP_RMDIR(dvp:p_vnode;vp:p_vnode;cnp:p_componentname):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_rmdir_args; s:Boolean; begin - v:=dvp^.v_op; - while (v<>nil) do - begin - if (v^.vop_rmdir<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_RMDIR'); + c:=get_vp_cb(dvp,vop_rmdir_desc.vdesc_call); + Assert(c<>nil,'VOP_RMDIR'); + a.a_gen:=@vop_rmdir_desc; a.a_dvp:=dvp; a.a_vp :=vp; a.a_cnp:=cnp; s:=VFS_PROLOGUE(dvp^.v_mount); - if (v^.vop_rmdir<>nil) then - begin - Result:=vop_rmdir_t(v^.vop_rmdir)(@a); - end else - begin - Result:=vop_rmdir_t(v^.vop_bypass)(@a); - end; + Result:=vop_rmdir_t(c)(@a); VFS_EPILOGUE(s); vop_rmdir_post(@a,Result); end; function VOP_SYMLINK(dvp:p_vnode;vpp:pp_vnode;cnp:p_componentname;vap:p_vattr;target:PChar):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_symlink_args; s:Boolean; begin - v:=dvp^.v_op; - while (v<>nil) do - begin - if (v^.vop_symlink<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_SYMLINK'); + c:=get_vp_cb(dvp,vop_symlink_desc.vdesc_call); + Assert(c<>nil,'VOP_SYMLINK'); + a.a_gen :=@vop_symlink_desc; a.a_dvp :=dvp; a.a_vpp :=vpp; a.a_cnp :=cnp; a.a_vap :=vap; a.a_target:=target; s:=VFS_PROLOGUE(dvp^.v_mount); - if (v^.vop_symlink<>nil) then - begin - Result:=vop_symlink_t(v^.vop_symlink)(@a); - end else - begin - Result:=vop_symlink_t(v^.vop_bypass)(@a); - end; + Result:=vop_symlink_t(c)(@a); VFS_EPILOGUE(s); vop_symlink_post(@a,Result); end; function VOP_READDIR(vp:p_vnode;uio:p_uio;eofflag:PInteger;ncookies:PInteger;cookies:PPPtrUint):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_readdir_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_readdir<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_READDIR'); + c:=get_vp_cb(vp,vop_readdir_desc.vdesc_call); + Assert(c<>nil,'VOP_READDIR'); + a.a_gen :=@vop_readdir_desc; a.a_vp :=vp; a.a_uio :=uio; a.a_eofflag :=eofflag; a.a_ncookies:=ncookies; a.a_cookies :=cookies; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_readdir<>nil) then - begin - Result:=vop_readdir_t(v^.vop_readdir)(@a); - end else - begin - Result:=vop_readdir_t(v^.vop_bypass)(@a); - end; + Result:=vop_readdir_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_READLINK(vp:p_vnode;uio:p_uio):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_readlink_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_readlink<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_READLINK'); + c:=get_vp_cb(vp,vop_readlink_desc.vdesc_call); + Assert(c<>nil,'VOP_READLINK'); + a.a_gen:=@vop_readlink_desc; a.a_vp :=vp; a.a_uio:=uio; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_readlink<>nil) then - begin - Result:=vop_readlink_t(v^.vop_readlink)(@a); - end else - begin - Result:=vop_readlink_t(v^.vop_bypass)(@a); - end; + Result:=vop_readlink_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_INACTIVE(vp:p_vnode):Integer; var - v:p_vop_vector; + c:Pointer; + a:vop_inactive_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_inactive<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_INACTIVE'); + c:=get_vp_cb(vp,vop_inactive_desc.vdesc_call); + Assert(c<>nil,'VOP_INACTIVE'); + a.a_gen:=@vop_inactive_desc; + a.a_vp :=vp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_inactive<>nil) then - begin - Result:=vop_inactive_t(v^.vop_inactive)(@vp); - end else - begin - Result:=vop_inactive_t(v^.vop_bypass)(@vp); - end; + Result:=vop_inactive_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_RECLAIM(vp:p_vnode):Integer; var - v:p_vop_vector; + c:Pointer; + a:vop_reclaim_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_reclaim<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_RECLAIM'); + c:=get_vp_cb(vp,vop_reclaim_desc.vdesc_call); + Assert(c<>nil,'VOP_RECLAIM'); + a.a_gen:=@vop_reclaim_desc; + a.a_vp :=vp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_reclaim<>nil) then - begin - Result:=vop_reclaim_t(v^.vop_reclaim)(@vp); - end else - begin - Result:=vop_reclaim_t(v^.vop_bypass)(@vp); - end; + Result:=vop_reclaim_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_LOCK(vp:p_vnode;flags:Integer;_file:PChar;line:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_lock1_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_lock1<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_LOCK'); + c:=get_vp_cb(vp,vop_lock1_desc.vdesc_call); + Assert(c<>nil,'VOP_LOCK'); + a.a_gen :=@vop_lock1_desc; a.a_vp :=vp; a.a_flags:=flags; a.a_file :=_file; a.a_line :=line; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_lock1<>nil) then - begin - Result:=vop_lock1_t(v^.vop_lock1)(@a); - end else - begin - Result:=vop_lock1_t(v^.vop_bypass)(@a); - end; + Result:=vop_lock1_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_UNLOCK(vp:p_vnode;flags:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_unlock_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_unlock<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_UNLOCK'); + c:=get_vp_cb(vp,vop_unlock_desc.vdesc_call); + Assert(c<>nil,'VOP_UNLOCK'); + a.a_gen :=@vop_unlock_desc; a.a_vp :=vp; a.a_flags:=flags; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_unlock<>nil) then - begin - Result:=vop_unlock_t(v^.vop_unlock)(@a); - end else - begin - Result:=vop_unlock_t(v^.vop_bypass)(@a); - end; + Result:=vop_unlock_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_BMAP(vp:p_vnode;bn:daddr_t;bop:pp_bufobj;bnp:p_daddr_t;runp:PInteger;runb:PInteger):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_bmap_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_bmap<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_BMAP'); + c:=get_vp_cb(vp,vop_bmap_desc.vdesc_call); + Assert(c<>nil,'VOP_BMAP'); + a.a_gen :=@vop_bmap_desc; a.a_vp :=vp; a.a_bn :=bn; a.a_bop :=bop; @@ -1490,160 +1861,102 @@ begin a.a_runp:=runp; a.a_runb:=runb; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_bmap<>nil) then - begin - Result:=vop_bmap_t(v^.vop_bmap)(@a); - end else - begin - Result:=vop_bmap_t(v^.vop_bypass)(@a); - end; + Result:=vop_bmap_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_STRATEGY(vp:p_vnode;bp:p_buf):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_strategy_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_strategy<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_STRATEGY'); - a.a_vp:=vp; - a.a_bp:=bp; + c:=get_vp_cb(vp,vop_strategy_desc.vdesc_call); + Assert(c<>nil,'VOP_STRATEGY'); + a.a_gen:=@vop_strategy_desc; + a.a_vp :=vp; + a.a_bp :=bp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_strategy<>nil) then - begin - Result:=vop_strategy_t(v^.vop_strategy)(@a); - end else - begin - Result:=vop_strategy_t(v^.vop_bypass)(@a); - end; + Result:=vop_strategy_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_GETWRITEMOUNT(vp:p_vnode;mpp:pp_mount):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_getwritemount_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_getwritemount<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_GETWRITEMOUNT'); + c:=get_vp_cb(vp,vop_getwritemount_desc.vdesc_call); + Assert(c<>nil,'VOP_GETWRITEMOUNT'); + a.a_gen:=@vop_getwritemount_desc; a.a_vp :=vp; a.a_mpp:=mpp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_getwritemount<>nil) then - begin - Result:=vop_getwritemount_t(v^.vop_getwritemount)(@a); - end else - begin - Result:=vop_getwritemount_t(v^.vop_bypass)(@a); - end; + Result:=vop_getwritemount_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_PRINT(vp:p_vnode):Integer; var - v:p_vop_vector; + c:Pointer; + a:vop_print_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_print<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_PRINT'); + c:=get_vp_cb(vp,vop_print_desc.vdesc_call); + Assert(c<>nil,'VOP_PRINT'); + a.a_gen:=@vop_print_desc; + a.a_vp :=vp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_print<>nil) then - begin - Result:=vop_print_t(v^.vop_print)(@vp); - end else - begin - Result:=vop_print_t(v^.vop_bypass)(@vp); - end; + Result:=vop_print_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_PATHCONF(vp:p_vnode;name:Integer;retval:PPtrUint):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_pathconf_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_pathconf<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_PATHCONF'); + c:=get_vp_cb(vp,vop_pathconf_desc.vdesc_call); + Assert(c<>nil,'VOP_PATHCONF'); + a.a_gen :=@vop_pathconf_desc; a.a_vp :=vp; a.a_name :=name; a.a_retval:=retval; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_pathconf<>nil) then - begin - Result:=vop_pathconf_t(v^.vop_pathconf)(@a); - end else - begin - Result:=vop_pathconf_t(v^.vop_bypass)(@a); - end; + Result:=vop_pathconf_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_ADVLOCK(vp:p_vnode;id:Pointer;op:Integer;fl:p_flock;flags:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_advlock_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_advlock<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_ADVLOCK'); + c:=get_vp_cb(vp,vop_advlock_desc.vdesc_call); + Assert(c<>nil,'VOP_ADVLOCK'); + a.a_gen :=@vop_advlock_desc; a.a_vp :=vp; a.a_id :=id; a.a_op :=op; a.a_fl :=fl; a.a_flags:=flags; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_advlock<>nil) then - begin - Result:=vop_advlock_t(v^.vop_advlock)(@a); - end else - begin - Result:=vop_advlock_t(v^.vop_bypass)(@a); - end; + Result:=vop_advlock_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_ADVLOCKASYNC(vp:p_vnode;id:Pointer;op:Integer;fl:p_flock;flags:Integer;task:p_task;cookiep:PPointer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_advlockasync_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_advlockasync<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_ADVLOCKASYNC'); + c:=get_vp_cb(vp,vop_advlockasync_desc.vdesc_call); + Assert(c<>nil,'VOP_ADVLOCKASYNC'); + a.a_gen :=@vop_advlockasync_desc; a.a_vp :=vp; a.a_id :=id; a.a_op :=op; @@ -1652,107 +1965,69 @@ begin a.a_task :=task; a.a_cookiep:=cookiep; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_advlockasync<>nil) then - begin - Result:=vop_advlockasync_t(v^.vop_advlockasync)(@a); - end else - begin - Result:=vop_advlockasync_t(v^.vop_bypass)(@a); - end; + Result:=vop_advlockasync_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_ADVLOCKPURGE(vp:p_vnode):Integer; var - v:p_vop_vector; + c:Pointer; + a:vop_advlockpurge_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_advlockpurge<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_ADVLOCKPURGE'); + c:=get_vp_cb(vp,vop_advlockpurge_desc.vdesc_call); + Assert(c<>nil,'VOP_ADVLOCKPURGE'); + a.a_gen:=@vop_advlockpurge_desc; + a.a_vp :=vp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_advlockpurge<>nil) then - begin - Result:=vop_advlockpurge_t(v^.vop_advlockpurge)(@vp); - end else - begin - Result:=vop_advlockpurge_t(v^.vop_bypass)(@vp); - end; + Result:=vop_advlockpurge_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_REALLOCBLKS(vp:p_vnode;buflist:p_cluster_save):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_reallocblks_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_reallocblks<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_REALLOCBLKS'); + c:=get_vp_cb(vp,vop_reallocblks_desc.vdesc_call); + Assert(c<>nil,'VOP_REALLOCBLKS'); + a.a_gen :=@vop_reallocblks_desc; a.a_vp :=vp; a.a_buflist:=buflist; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_reallocblks<>nil) then - begin - Result:=vop_reallocblks_t(v^.vop_reallocblks)(@a); - end else - begin - Result:=vop_reallocblks_t(v^.vop_bypass)(@a); - end; + Result:=vop_reallocblks_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_GETPAGES(vp:p_vnode;m:p_vm_page_t;count:Integer;reqpage:Integer;offset:PtrUint):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_getpages_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_getpages<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_GETPAGES'); + c:=get_vp_cb(vp,vop_getpages_desc.vdesc_call); + Assert(c<>nil,'VOP_GETPAGES'); + a.a_gen :=@vop_getpages_desc; a.a_vp :=vp; a.a_m :=m; a.a_count :=count; a.a_reqpage:=reqpage; a.a_offset :=offset; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_getpages<>nil) then - begin - Result:=vop_getpages_t(v^.vop_getpages)(@a); - end else - begin - Result:=vop_getpages_t(v^.vop_bypass)(@a); - end; + Result:=vop_getpages_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_PUTPAGES(vp:p_vnode;m:p_vm_page_t;count:Integer;sync:Integer;rtvals:PInteger;offset:PtrUint):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_putpages_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_putpages<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_PUTPAGES'); + c:=get_vp_cb(vp,vop_putpages_desc.vdesc_call); + Assert(c<>nil,'VOP_PUTPAGES'); + a.a_gen :=@vop_putpages_desc; a.a_vp :=vp; a.a_m :=m; a.a_count :=count; @@ -1760,588 +2035,372 @@ begin a.a_rtvals:=rtvals; a.a_offset:=offset; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_putpages<>nil) then - begin - Result:=vop_putpages_t(v^.vop_putpages)(@a); - end else - begin - Result:=vop_putpages_t(v^.vop_bypass)(@a); - end; + Result:=vop_putpages_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_GETACL(vp:p_vnode;_type:acl_type_t;aclp:p_acl):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_getacl_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_getacl<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_GETACL'); + c:=get_vp_cb(vp,vop_getacl_desc.vdesc_call); + Assert(c<>nil,'VOP_GETACL'); + a.a_gen :=@vop_getacl_desc; a.a_vp :=vp; a.a_type:=_type; a.a_aclp:=aclp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_getacl<>nil) then - begin - Result:=vop_getacl_t(v^.vop_getacl)(@a); - end else - begin - Result:=vop_getacl_t(v^.vop_bypass)(@a); - end; + Result:=vop_getacl_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_SETACL(vp:p_vnode;_type:acl_type_t;aclp:p_acl):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_setacl_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_setacl<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_SETACL'); + c:=get_vp_cb(vp,vop_setacl_desc.vdesc_call); + Assert(c<>nil,'VOP_SETACL'); + a.a_gen :=@vop_setacl_desc; a.a_vp :=vp; a.a_type:=_type; a.a_aclp:=aclp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_setacl<>nil) then - begin - Result:=vop_setacl_t(v^.vop_setacl)(@a); - end else - begin - Result:=vop_setacl_t(v^.vop_bypass)(@a); - end; + Result:=vop_setacl_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_ACLCHECK(vp:p_vnode;_type:acl_type_t;aclp:p_acl):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_aclcheck_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_aclcheck<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_ACLCHECK'); + c:=get_vp_cb(vp,vop_aclcheck_desc.vdesc_call); + Assert(c<>nil,'VOP_ACLCHECK'); + a.a_gen :=@vop_aclcheck_desc; a.a_vp :=vp; a.a_type:=_type; a.a_aclp:=aclp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_aclcheck<>nil) then - begin - Result:=vop_aclcheck_t(v^.vop_aclcheck)(@a); - end else - begin - Result:=vop_aclcheck_t(v^.vop_bypass)(@a); - end; + Result:=vop_aclcheck_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_CLOSEEXTATTR(vp:p_vnode;commit:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_closeextattr_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_closeextattr<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_CLOSEEXTATTR'); + c:=get_vp_cb(vp,vop_closeextattr_desc.vdesc_call); + Assert(c<>nil,'VOP_CLOSEEXTATTR'); + a.a_gen :=@vop_closeextattr_desc; a.a_vp :=vp; a.a_commit:=commit; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_closeextattr<>nil) then - begin - Result:=vop_closeextattr_t(v^.vop_closeextattr)(@a); - end else - begin - Result:=vop_closeextattr_t(v^.vop_bypass)(@a); - end; + Result:=vop_closeextattr_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_GETEXTATTR(vp:p_vnode;attrnamespace:Integer;name:PChar;uio:p_uio;size:PPtrUint):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_getextattr_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_getextattr<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_GETEXTATTR'); + c:=get_vp_cb(vp,vop_getextattr_desc.vdesc_call); + Assert(c<>nil,'VOP_GETEXTATTR'); + a.a_gen :=@vop_getextattr_desc; a.a_vp :=vp; a.a_attrnamespace:=attrnamespace; a.a_name :=name; a.a_uio :=uio; a.a_size :=size; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_getextattr<>nil) then - begin - Result:=vop_getextattr_t(v^.vop_getextattr)(@a); - end else - begin - Result:=vop_getextattr_t(v^.vop_bypass)(@a); - end; + Result:=vop_getextattr_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_LISTEXTATTR(vp:p_vnode;attrnamespace:Integer;uio:p_uio;size:PPtrUint):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_listextattr_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_listextattr<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_LISTEXTATTR'); + c:=get_vp_cb(vp,vop_listextattr_desc.vdesc_call); + Assert(c<>nil,'VOP_LISTEXTATTR'); + a.a_gen :=@vop_listextattr_desc; a.a_vp :=vp; a.a_attrnamespace:=attrnamespace; a.a_uio :=uio; a.a_size :=size; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_listextattr<>nil) then - begin - Result:=vop_listextattr_t(v^.vop_listextattr)(@a); - end else - begin - Result:=vop_listextattr_t(v^.vop_bypass)(@a); - end; + Result:=vop_listextattr_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_OPENEXTATTR(vp:p_vnode):Integer; var - v:p_vop_vector; + c:Pointer; + a:vop_openextattr_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_openextattr<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_OPENEXTATTR'); + c:=get_vp_cb(vp,vop_openextattr_desc.vdesc_call); + Assert(c<>nil,'VOP_OPENEXTATTR'); + a.a_gen:=@vop_openextattr_desc; + a.a_vp :=vp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_openextattr<>nil) then - begin - Result:=vop_openextattr_t(v^.vop_openextattr)(@vp); - end else - begin - Result:=vop_openextattr_t(v^.vop_bypass)(@vp); - end; + Result:=vop_openextattr_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_DELETEEXTATTR(vp:p_vnode;attrnamespace:Integer;name:PChar):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_deleteextattr_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_deleteextattr<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_DELETEEXTATTR'); + c:=get_vp_cb(vp,vop_deleteextattr_desc.vdesc_call); + Assert(c<>nil,'VOP_DELETEEXTATTR'); + a.a_gen :=@vop_deleteextattr_desc; a.a_vp :=vp; a.a_attrnamespace:=attrnamespace; a.a_name :=name; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_deleteextattr<>nil) then - begin - Result:=vop_deleteextattr_t(v^.vop_deleteextattr)(@a); - end else - begin - Result:=vop_deleteextattr_t(v^.vop_bypass)(@a); - end; + Result:=vop_deleteextattr_t(c)(@a); VFS_EPILOGUE(s); vop_deleteextattr_post(@a,Result); end; function VOP_SETEXTATTR(vp:p_vnode;attrnamespace:Integer;name:PChar;uio:p_uio):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_setextattr_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_setextattr<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_SETEXTATTR'); + c:=get_vp_cb(vp,vop_setextattr_desc.vdesc_call); + Assert(c<>nil,'VOP_SETEXTATTR'); + a.a_gen :=@vop_setextattr_desc; a.a_vp :=vp; a.a_attrnamespace:=attrnamespace; a.a_name :=name; a.a_uio :=uio; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_setextattr<>nil) then - begin - Result:=vop_setextattr_t(v^.vop_setextattr)(@a); - end else - begin - Result:=vop_setextattr_t(v^.vop_bypass)(@a); - end; + Result:=vop_setextattr_t(c)(@a); VFS_EPILOGUE(s); vop_setextattr_post(@a,Result); end; function VOP_SETLABEL(vp:p_vnode;_label:p_label):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_setlabel_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_setlabel<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_SETLABEL'); + c:=get_vp_cb(vp,vop_setlabel_desc.vdesc_call); + Assert(c<>nil,'VOP_SETLABEL'); + a.a_gen :=@vop_setlabel_desc; a.a_vp :=vp; a.a_label:=_label; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_setlabel<>nil) then - begin - Result:=vop_setlabel_t(v^.vop_setlabel)(@a); - end else - begin - Result:=vop_setlabel_t(v^.vop_bypass)(@a); - end; + Result:=vop_setlabel_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_VPTOFH(vp:p_vnode;fhp:p_fid):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_vptofh_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_vptofh<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_VPTOFH'); + c:=get_vp_cb(vp,vop_vptofh_desc.vdesc_call); + Assert(c<>nil,'VOP_VPTOFH'); + a.a_gen:=@vop_vptofh_desc; a.a_vp :=vp; a.a_fhp:=fhp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_vptofh<>nil) then - begin - Result:=vop_vptofh_t(v^.vop_vptofh)(@a); - end else - begin - Result:=vop_vptofh_t(v^.vop_bypass)(@a); - end; + Result:=vop_vptofh_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_VPTOCNP(vp:p_vnode;vpp:pp_vnode;buf:PChar;buflen:PInteger):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_vptocnp_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_vptocnp<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_VPTOCNP'); + c:=get_vp_cb(vp,vop_vptocnp_desc.vdesc_call); + Assert(c<>nil,'VOP_VPTOCNP'); + a.a_gen :=@vop_vptocnp_desc; a.a_vp :=vp; a.a_vpp :=vpp; a.a_buf :=buf; a.a_buflen:=buflen; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_vptocnp<>nil) then - begin - Result:=vop_vptocnp_t(v^.vop_vptocnp)(@a); - end else - begin - Result:=vop_vptocnp_t(v^.vop_bypass)(@a); - end; + Result:=vop_vptocnp_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_ALLOCATE(vp:p_vnode;offset:PPtrUint;len:PPtrUint):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_allocate_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_allocate<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_ALLOCATE'); + c:=get_vp_cb(vp,vop_allocate_desc.vdesc_call); + Assert(c<>nil,'VOP_ALLOCATE'); + a.a_gen :=@vop_allocate_desc; a.a_vp :=vp; a.a_offset:=offset; a.a_len :=len; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_allocate<>nil) then - begin - Result:=vop_allocate_t(v^.vop_allocate)(@a); - end else - begin - Result:=vop_allocate_t(v^.vop_bypass)(@a); - end; + Result:=vop_allocate_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_ADVISE(vp:p_vnode;start:PtrUint;__end:PtrUint;advice:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_advise_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_advise<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_ADVISE'); + c:=get_vp_cb(vp,vop_advise_desc.vdesc_call); + Assert(c<>nil,'VOP_ADVISE'); + a.a_gen :=@vop_advise_desc; a.a_vp :=vp; a.a_start :=start; a.a___end :=__end; a.a_advice:=advice; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_advise<>nil) then - begin - Result:=vop_advise_t(v^.vop_advise)(@a); - end else - begin - Result:=vop_advise_t(v^.vop_bypass)(@a); - end; + Result:=vop_advise_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_UNP_BIND(vp:p_vnode;socket:p_socket):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_unp_bind_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_unp_bind<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_UNP_BIND'); + c:=get_vp_cb(vp,vop_unp_bind_desc.vdesc_call); + Assert(c<>nil,'VOP_UNP_BIND'); + a.a_gen :=@vop_unp_bind_desc; a.a_vp :=vp; a.a_socket:=socket; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_unp_bind<>nil) then - begin - Result:=vop_unp_bind_t(v^.vop_unp_bind)(@a); - end else - begin - Result:=vop_unp_bind_t(v^.vop_bypass)(@a); - end; + Result:=vop_unp_bind_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_UNP_CONNECT(vp:p_vnode;socket:pp_socket):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_unp_connect_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_unp_connect<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_UNP_CONNECT'); + c:=get_vp_cb(vp,vop_unp_connect_desc.vdesc_call); + Assert(c<>nil,'VOP_UNP_CONNECT'); + a.a_gen :=@vop_unp_connect_desc; a.a_vp :=vp; a.a_socket:=socket; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_unp_connect<>nil) then - begin - Result:=vop_unp_connect_t(v^.vop_unp_connect)(@a); - end else - begin - Result:=vop_unp_connect_t(v^.vop_bypass)(@a); - end; + Result:=vop_unp_connect_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_UNP_DETACH(vp:p_vnode):Integer; var - v:p_vop_vector; + c:Pointer; + a:vop_unp_detach_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_unp_detach<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_UNP_DETACH'); + c:=get_vp_cb(vp,vop_unp_detach_desc.vdesc_call); + Assert(c<>nil,'VOP_UNP_DETACH'); + a.a_gen:=@vop_unp_detach_desc; + a.a_vp :=vp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_unp_detach<>nil) then - begin - Result:=vop_unp_detach_t(v^.vop_unp_detach)(@vp); - end else - begin - Result:=vop_unp_detach_t(v^.vop_bypass)(@vp); - end; + Result:=vop_unp_detach_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_IS_TEXT(vp:p_vnode):Integer; var - v:p_vop_vector; + c:Pointer; + a:vop_is_text_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_is_text<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_IS_TEXT'); + c:=get_vp_cb(vp,vop_is_text_desc.vdesc_call); + Assert(c<>nil,'VOP_IS_TEXT'); + a.a_gen:=@vop_is_text_desc; + a.a_vp :=vp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_is_text<>nil) then - begin - Result:=vop_is_text_t(v^.vop_is_text)(@vp); - end else - begin - Result:=vop_is_text_t(v^.vop_bypass)(@vp); - end; + Result:=vop_is_text_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_SET_TEXT(vp:p_vnode):Integer; var - v:p_vop_vector; + c:Pointer; + a:vop_set_text_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_set_text<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_SET_TEXT'); + c:=get_vp_cb(vp,vop_set_text_desc.vdesc_call); + Assert(c<>nil,'VOP_SET_TEXT'); + a.a_gen:=@vop_set_text_desc; + a.a_vp :=vp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_set_text<>nil) then - begin - Result:=vop_set_text_t(v^.vop_set_text)(@vp); - end else - begin - Result:=vop_set_text_t(v^.vop_bypass)(@vp); - end; + Result:=vop_set_text_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_UNSET_TEXT(vp:p_vnode):Integer; var - v:p_vop_vector; + c:Pointer; + a:vop_unset_text_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_unset_text<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_UNSET_TEXT'); + c:=get_vp_cb(vp,vop_unset_text_desc.vdesc_call); + Assert(c<>nil,'VOP_UNSET_TEXT'); + a.a_gen:=@vop_unset_text_desc; + a.a_vp :=vp; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_unset_text<>nil) then - begin - Result:=vop_unset_text_t(v^.vop_unset_text)(@vp); - end else - begin - Result:=vop_unset_text_t(v^.vop_bypass)(@vp); - end; + Result:=vop_unset_text_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_GET_WRITECOUNT(vp:p_vnode;writecount:PInteger):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_get_writecount_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_get_writecount<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_GET_WRITECOUNT'); + c:=get_vp_cb(vp,vop_get_writecount_desc.vdesc_call); + Assert(c<>nil,'VOP_GET_WRITECOUNT'); + a.a_gen :=@vop_get_writecount_desc; a.a_vp :=vp; a.a_writecount:=writecount; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_get_writecount<>nil) then - begin - Result:=vop_get_writecount_t(v^.vop_get_writecount)(@a); - end else - begin - Result:=vop_get_writecount_t(v^.vop_bypass)(@a); - end; + Result:=vop_get_writecount_t(c)(@a); VFS_EPILOGUE(s); end; function VOP_ADD_WRITECOUNT(vp:p_vnode;inc:Integer):Integer; var - v:p_vop_vector; + c:Pointer; a:vop_add_writecount_args; s:Boolean; begin - v:=vp^.v_op; - while (v<>nil) do - begin - if (v^.vop_add_writecount<>nil) or (v^.vop_bypass<>nil) then Break; - v:=v^.vop_default; - end; - Assert(v<>nil,'VOP_ADD_WRITECOUNT'); + c:=get_vp_cb(vp,vop_add_writecount_desc.vdesc_call); + Assert(c<>nil,'VOP_ADD_WRITECOUNT'); + a.a_gen:=@vop_add_writecount_desc; a.a_vp :=vp; a.a_inc:=inc; s:=VFS_PROLOGUE(vp^.v_mount); - if (v^.vop_add_writecount<>nil) then - begin - Result:=vop_add_writecount_t(v^.vop_add_writecount)(@a); - end else - begin - Result:=vop_add_writecount_t(v^.vop_bypass)(@a); - end; + Result:=vop_add_writecount_t(c)(@a); VFS_EPILOGUE(s); end; diff --git a/sys/vfs/vsys_generic.pas b/sys/vfs/vsys_generic.pas index 2c350a80..1e480ead 100644 --- a/sys/vfs/vsys_generic.pas +++ b/sys/vfs/vsys_generic.pas @@ -18,7 +18,7 @@ uses vuio, vfile, vcapability, - vfs_vnode, + vnode, vfcntl, vfilio, vfiledesc, @@ -1134,7 +1134,7 @@ begin continue; end; fp:=fget_unlocked(fd^.fd); - if (fp=nil) or (cap_funwrap(fp, CAP_POLL_EVENT, @fp)<>0) then + if (cap_funwrap(fp, CAP_POLL_EVENT, @fp)<>0) then begin if (fp<>nil) then fdrop(fp); @@ -1208,7 +1208,7 @@ begin end else begin fp:=fget_unlocked(fds^.fd); - if ((fp=nil) or (cap_funwrap(fp, CAP_POLL_EVENT, @fp)<>0)) then + if (cap_funwrap(fp, CAP_POLL_EVENT, @fp)<>0) then begin fds^.revents:=POLLNVAL; Inc(n); diff --git a/sys/vm/vm_map.pas b/sys/vm/vm_map.pas index 81c2d3ef..ede22fb4 100644 --- a/sys/vm/vm_map.pas +++ b/sys/vm/vm_map.pas @@ -482,10 +482,16 @@ end; procedure vm_map_entry_set_max_free(entry:vm_map_entry_t); begin entry^.max_free:=entry^.adj_free; - if (entry^.left<>nil) and (entry^.left^.max_free>entry^.max_free) then + if (entry^.left<>nil) then + if (entry^.left^.max_free>entry^.max_free) then + begin entry^.max_free:=entry^.left^.max_free; - if (entry^.right<>nil) and (entry^.right^.max_free>entry^.max_free) then + end; + if (entry^.right<>nil) then + if (entry^.right^.max_free>entry^.max_free) then + begin entry^.max_free:=entry^.right^.max_free; + end; end; { @@ -999,6 +1005,8 @@ function vm_map_findspace(map :vm_map_t; start :vm_offset_t; length:vm_size_t; addr :p_vm_offset_t):Integer; +label + _nxt; var entry:vm_map_entry_t; st:vm_offset_t; @@ -1052,7 +1060,11 @@ begin { With max_free, can immediately tell if no solution. } entry:=map^.root^.right; - if (entry=nil) or (length>entry^.max_free) then + + if (entry=nil) then + Exit(1); + + if (length>entry^.max_free) then Exit(1); { @@ -1062,16 +1074,20 @@ begin } while (entry<>nil) do begin - if (entry^.left<>nil) and (entry^.left^.max_free>=length) then + if (entry^.left<>nil) then begin + if not (entry^.left^.max_free>=length) then goto _nxt; entry:=entry^.left; end else - if (entry^.adj_free>=length) then begin - addr^:=entry^.__end; - Exit(0); - end else - entry:=entry^.right; + _nxt: + if (entry^.adj_free>=length) then + begin + addr^:=entry^.__end; + Exit(0); + end else + entry:=entry^.right; + end; end; { Can't get here, so panic if we do. } @@ -1124,11 +1140,16 @@ label var alignment,initial_addr,start:vm_offset_t; begin - if (find_space=VMFS_OPTIMAL_SPACE) and - ((_object=nil) or - ((_object^.flags and OBJ_COLORED)=0)) then + if (find_space=VMFS_OPTIMAL_SPACE) then begin - find_space:=VMFS_ANY_SPACE; + if (_object=nil) then + begin + find_space:=VMFS_ANY_SPACE; + end else + if ((_object^.flags and OBJ_COLORED)=0) then + begin + find_space:=VMFS_ANY_SPACE; + end; end; if ((find_space shr 8)<>0) then begin @@ -2123,6 +2144,7 @@ end; } function vm_map_growstack(addr:vm_offset_t):Integer; label + _or, _out; var next_entry, prev_entry:vm_map_entry_t; @@ -2340,12 +2362,15 @@ begin grow_amount:=addr - stack_entry^.__end; { Grow the underlying object if applicable. } - if ((stack_entry^._object=nil) or - vm_object_coalesce(stack_entry^._object, - stack_entry^.offset, - vm_size_t(stack_entry^.__end - stack_entry^.start), - vm_size_t(grow_amount), false)) then + + if (stack_entry^._object=nil) then goto _or; + + if vm_object_coalesce(stack_entry^._object, + stack_entry^.offset, + vm_size_t(stack_entry^.__end - stack_entry^.start), + vm_size_t(grow_amount), false) then begin + _or: map^.size:=map^.size+(addr - stack_entry^.__end); { Update the current entry. } stack_entry^.__end:=addr; diff --git a/sys/vm/vm_mmap.pas b/sys/vm/vm_mmap.pas index 68a78bd6..6abaa0ff 100644 --- a/sys/vm/vm_mmap.pas +++ b/sys/vm/vm_mmap.pas @@ -45,7 +45,7 @@ uses vstat, vfile, vfcntl, - vfs_vnode, + vnode, vfs_subr, vnode_if; @@ -457,10 +457,13 @@ begin vp:=fp^.f_vnode; - if (vp^.v_mount<>nil) and ((p_mount(vp^.v_mount)^.mnt_flag and MNT_NOEXEC)<>0) then - maxprot:=VM_PROT_NONE - else - maxprot:=VM_PROT_EXECUTE; + maxprot:=VM_PROT_EXECUTE; + + if (vp^.v_mount<>nil) then + if ((p_mount(vp^.v_mount)^.mnt_flag and MNT_NOEXEC)<>0) then + begin + maxprot:=VM_PROT_NONE; + end; if ((fp^.f_flag and FREAD)<>0) then begin diff --git a/sys/vm/vm_pmap.pas b/sys/vm/vm_pmap.pas index 5bb885d6..5b6699dc 100644 --- a/sys/vm/vm_pmap.pas +++ b/sys/vm/vm_pmap.pas @@ -114,8 +114,11 @@ var superpage_offset:vm_offset_t; begin if (size < NBPDR) then Exit; - //if (_object<>nil) and ((_object^.flags and OBJ_COLORED)<>0) then + //if (_object<>nil) then + //if ((_object^.flags and OBJ_COLORED)<>0) then + //begin // offset:=offset+ptoa(_object^.pg_color); + //end; superpage_offset:=offset and PDRMASK; if (size - ((NBPDR - superpage_offset) and PDRMASK) < NBPDR) or ((addr^ and PDRMASK)=superpage_offset) then diff --git a/tools/gfx6_chip/si_ci_vi_merged_enum.h b/tools/gfx6_chip/si_ci_vi_merged_enum.h deleted file mode 100644 index 710026f9..00000000 --- a/tools/gfx6_chip/si_ci_vi_merged_enum.h +++ /dev/null @@ -1,10181 +0,0 @@ -/* - *********************************************************************************************************************** - * - * Copyright (c) 2014-2021 Advanced Micro Devices, Inc. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - **********************************************************************************************************************/ - -#if !defined (__SI__CI__VI_MERGED_ENUM_HEADER) -#define __SI__CI__VI_MERGED_ENUM_HEADER - -namespace Pal -{ -namespace Gfx6 -{ -inline namespace Chip -{ - -typedef enum ArrayMode { -ARRAY_LINEAR_GENERAL = 0x00000000, -ARRAY_LINEAR_ALIGNED = 0x00000001, -ARRAY_1D_TILED_THIN1 = 0x00000002, -ARRAY_1D_TILED_THICK = 0x00000003, -ARRAY_2D_TILED_THIN1 = 0x00000004, -ARRAY_2D_TILED_THIN2__SI = 0x00000005, -ARRAY_PRT_TILED_THIN1__CI__VI = 0x00000005, -ARRAY_2D_TILED_THIN4__SI = 0x00000006, -ARRAY_PRT_2D_TILED_THIN1__CI__VI = 0x00000006, -ARRAY_2D_TILED_THICK = 0x00000007, -ARRAY_2D_TILED_XTHICK = 0x00000008, -ARRAY_2B_TILED_THIN2__SI = 0x00000009, -ARRAY_PRT_TILED_THICK__CI__VI = 0x00000009, -ARRAY_2B_TILED_THIN4__SI = 0x0000000a, -ARRAY_PRT_2D_TILED_THICK__CI__VI = 0x0000000a, -ARRAY_2B_TILED_THICK__SI = 0x0000000b, -ARRAY_PRT_3D_TILED_THIN1__CI__VI = 0x0000000b, -ARRAY_3D_TILED_THIN1 = 0x0000000c, -ARRAY_3D_TILED_THICK = 0x0000000d, -ARRAY_3D_TILED_XTHICK = 0x0000000e, -ARRAY_POWER_SAVE__SI = 0x0000000f, -ARRAY_PRT_3D_TILED_THICK__CI__VI = 0x0000000f, -} ArrayMode; - -typedef enum BUF_DATA_FORMAT { -BUF_DATA_FORMAT_INVALID = 0x00000000, -BUF_DATA_FORMAT_8 = 0x00000001, -BUF_DATA_FORMAT_16 = 0x00000002, -BUF_DATA_FORMAT_8_8 = 0x00000003, -BUF_DATA_FORMAT_32 = 0x00000004, -BUF_DATA_FORMAT_16_16 = 0x00000005, -BUF_DATA_FORMAT_10_11_11 = 0x00000006, -BUF_DATA_FORMAT_11_11_10 = 0x00000007, -BUF_DATA_FORMAT_10_10_10_2 = 0x00000008, -BUF_DATA_FORMAT_2_10_10_10 = 0x00000009, -BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a, -BUF_DATA_FORMAT_32_32 = 0x0000000b, -BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c, -BUF_DATA_FORMAT_32_32_32 = 0x0000000d, -BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e, -BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f, -} BUF_DATA_FORMAT; - -typedef enum BUF_NUM_FORMAT { -BUF_NUM_FORMAT_UNORM = 0x00000000, -BUF_NUM_FORMAT_SNORM = 0x00000001, -BUF_NUM_FORMAT_USCALED = 0x00000002, -BUF_NUM_FORMAT_SSCALED = 0x00000003, -BUF_NUM_FORMAT_UINT = 0x00000004, -BUF_NUM_FORMAT_SINT = 0x00000005, -BUF_NUM_FORMAT_SNORM_OGL__SI__CI = 0x00000006, -BUF_NUM_FORMAT_RESERVED_6__VI = 0x00000006, -BUF_NUM_FORMAT_FLOAT = 0x00000007, -} BUF_NUM_FORMAT; - -typedef enum BankHeight { -ADDR_SURF_BANK_HEIGHT_1 = 0x00000000, -ADDR_SURF_BANK_HEIGHT_2 = 0x00000001, -ADDR_SURF_BANK_HEIGHT_4 = 0x00000002, -ADDR_SURF_BANK_HEIGHT_8 = 0x00000003, -} BankHeight; - -typedef enum BankInterleaveSize { -ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, -ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, -ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, -ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, -} BankInterleaveSize; - -typedef enum BankSwapBytes { -CONFIG_128B_SWAPS = 0x00000000, -CONFIG_256B_SWAPS = 0x00000001, -CONFIG_512B_SWAPS = 0x00000002, -CONFIG_1KB_SWAPS = 0x00000003, -} BankSwapBytes; - -typedef enum BankTiling { -CONFIG_4_BANK = 0x00000000, -CONFIG_8_BANK = 0x00000001, -} BankTiling; - -typedef enum BankWidth { -ADDR_SURF_BANK_WIDTH_1 = 0x00000000, -ADDR_SURF_BANK_WIDTH_2 = 0x00000001, -ADDR_SURF_BANK_WIDTH_4 = 0x00000002, -ADDR_SURF_BANK_WIDTH_8 = 0x00000003, -} BankWidth; - -typedef enum BankWidthHeight { -ADDR_SURF_BANK_WH_1 = 0x00000000, -ADDR_SURF_BANK_WH_2 = 0x00000001, -ADDR_SURF_BANK_WH_4 = 0x00000002, -ADDR_SURF_BANK_WH_8 = 0x00000003, -} BankWidthHeight; - -typedef enum BlendOp { -BLEND_ZERO = 0x00000000, -BLEND_ONE = 0x00000001, -BLEND_SRC_COLOR = 0x00000002, -BLEND_ONE_MINUS_SRC_COLOR = 0x00000003, -BLEND_SRC_ALPHA = 0x00000004, -BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005, -BLEND_DST_ALPHA = 0x00000006, -BLEND_ONE_MINUS_DST_ALPHA = 0x00000007, -BLEND_DST_COLOR = 0x00000008, -BLEND_ONE_MINUS_DST_COLOR = 0x00000009, -BLEND_SRC_ALPHA_SATURATE = 0x0000000a, -BLEND_BOTH_SRC_ALPHA = 0x0000000b, -BLEND_BOTH_INV_SRC_ALPHA = 0x0000000c, -BLEND_CONSTANT_COLOR = 0x0000000d, -BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000e, -BLEND_SRC1_COLOR = 0x0000000f, -BLEND_INV_SRC1_COLOR = 0x00000010, -BLEND_SRC1_ALPHA = 0x00000011, -BLEND_INV_SRC1_ALPHA = 0x00000012, -BLEND_CONSTANT_ALPHA = 0x00000013, -BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000014, -} BlendOp; - -typedef enum BlendOpt { -FORCE_OPT_AUTO = 0x00000000, -FORCE_OPT_DISABLE = 0x00000001, -FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002, -FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003, -FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004, -FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005, -FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006, -FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007, -} BlendOpt; - -typedef enum CBMode { -CB_DISABLE = 0x00000000, -CB_NORMAL = 0x00000001, -CB_ELIMINATE_FAST_CLEAR = 0x00000002, -CB_RESOLVE = 0x00000003, -CB_DECOMPRESS = 0x00000004, -CB_FMASK_DECOMPRESS = 0x00000005, -CB_DCC_DECOMPRESS__VI = 0x00000006, -} CBMode; - -typedef enum CBPerfClearFilterSel { -CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000, -CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001, -} CBPerfClearFilterSel; - -typedef enum CBPerfOpFilterSel { -CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000, -CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001, -CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002, -CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003, -CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004, -CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005, -} CBPerfOpFilterSel; - -typedef enum CBPerfSel { -CB_PERF_SEL_NONE = 0x00000000, -CB_PERF_SEL_BUSY = 0x00000001, -CB_PERF_SEL_CORE_SCLK_VLD = 0x00000002, -CB_PERF_SEL_REG_SCLK0_VLD = 0x00000003, -CB_PERF_SEL_REG_SCLK1_VLD = 0x00000004, -CB_PERF_SEL_DRAWN_QUAD = 0x00000005, -CB_PERF_SEL_DRAWN_PIXEL = 0x00000006, -CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000007, -CB_PERF_SEL_DRAWN_TILE = 0x00000008, -CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x00000009, -CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0x0000000a, -CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0x0000000b, -CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0x0000000c, -CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0x0000000d, -CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0x0000000e, -CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0x0000000f, -CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x00000010, -CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x00000011, -CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012, -CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x00000013, -CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x00000014, -CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x00000015, -CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x00000016, -CB_PERF_SEL_LQUAD_NO_TILE = 0x00000017, -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x00000018, -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019, -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a, -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b, -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c, -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d, -CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f, -CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020, -CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022, -CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023, -CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x00000024, -CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x00000025, -CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x00000026, -CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x00000027, -CB_PERF_SEL_FOP_IN_VALID_READY = 0x00000028, -CB_PERF_SEL_FOP_IN_VALID_READYB = 0x00000029, -CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x0000002a, -CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x0000002b, -CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x0000002c, -CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x0000002d, -CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x0000002e, -CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f, -CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x00000030, -CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x00000031, -CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x00000032, -CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x00000033, -CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x00000034, -CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x00000035, -CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x00000036, -CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x00000037, -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038, -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039, -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a, -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b, -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c, -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d, -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e, -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f, -CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x00000040, -CB_PERF_SEL_CM_CACHE_HIT = 0x00000041, -CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x00000042, -CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x00000043, -CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x00000044, -CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046, -CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x00000048, -CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x00000049, -CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x0000004a, -CB_PERF_SEL_CM_CACHE_STALL = 0x0000004b, -CB_PERF_SEL_CM_CACHE_FLUSH = 0x0000004c, -CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x0000004d, -CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x0000004e, -CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f, -CB_PERF_SEL_FC_CACHE_HIT = 0x00000050, -CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x00000051, -CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x00000052, -CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x00000053, -CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055, -CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x00000057, -CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x00000058, -CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x00000059, -CB_PERF_SEL_FC_CACHE_STALL = 0x0000005a, -CB_PERF_SEL_FC_CACHE_FLUSH = 0x0000005b, -CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x0000005c, -CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x0000005d, -CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e, -CB_PERF_SEL_CC_CACHE_HIT = 0x0000005f, -CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000060, -CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000061, -CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000062, -CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064, -CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000066, -CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000067, -CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x00000068, -CB_PERF_SEL_CC_CACHE_STALL = 0x00000069, -CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000006a, -CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x0000006b, -CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000006c, -CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d, -CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e, -CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY__SI__CI = 0x0000006f, -CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC__VI = 0x0000006f, -CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB__SI__CI = 0x00000070, -CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY__VI = 0x00000070, -CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY__SI__CI = 0x00000071, -CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB__VI = 0x00000071, -CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB__SI__CI = 0x00000072, -CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY__VI = 0x00000072, -CB_PERF_SEL_CM_MC_WRITE_REQUEST__SI__CI = 0x00000073, -CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB__VI = 0x00000073, -CB_PERF_SEL_FC_MC_WRITE_REQUEST__SI__CI = 0x00000074, -CB_PERF_SEL_CM_MC_WRITE_REQUEST__VI = 0x00000074, -CB_PERF_SEL_CC_MC_WRITE_REQUEST__SI__CI = 0x00000075, -CB_PERF_SEL_FC_MC_WRITE_REQUEST__VI = 0x00000075, -CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT__SI__CI = 0x00000076, -CB_PERF_SEL_CC_MC_WRITE_REQUEST__VI = 0x00000076, -CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT__SI__CI = 0x00000077, -CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000077, -CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT__SI__CI = 0x00000078, -CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000078, -CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY__SI__CI = 0x00000079, -CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000079, -CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB__SI__CI = 0x0000007a, -CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY__VI = 0x0000007a, -CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY__SI__CI = 0x0000007b, -CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB__VI = 0x0000007b, -CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB__SI__CI = 0x0000007c, -CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY__VI = 0x0000007c, -CB_PERF_SEL_CM_MC_READ_REQUEST__SI__CI = 0x0000007d, -CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB__VI = 0x0000007d, -CB_PERF_SEL_FC_MC_READ_REQUEST__SI__CI = 0x0000007e, -CB_PERF_SEL_CM_MC_READ_REQUEST__VI = 0x0000007e, -CB_PERF_SEL_CC_MC_READ_REQUEST__SI__CI = 0x0000007f, -CB_PERF_SEL_FC_MC_READ_REQUEST__VI = 0x0000007f, -CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT__SI__CI = 0x00000080, -CB_PERF_SEL_CC_MC_READ_REQUEST__VI = 0x00000080, -CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT__SI__CI = 0x00000081, -CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000081, -CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT__SI__CI = 0x00000082, -CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000082, -CB_PERF_SEL_CM_TQ_FULL__SI__CI = 0x00000083, -CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000083, -CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL__SI__CI = 0x00000084, -CB_PERF_SEL_CM_TQ_FULL__VI = 0x00000084, -CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL__SI__CI = 0x00000085, -CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL__VI = 0x00000085, -CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL__SI__CI = 0x00000086, -CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL__VI = 0x00000086, -CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL__SI__CI = 0x00000087, -CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL__VI = 0x00000087, -CB_PERF_SEL_FOP_FMASK_RAW_STALL__SI__CI = 0x00000088, -CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL__VI = 0x00000088, -CB_PERF_SEL_FOP_FMASK_BYPASS_STALL__SI__CI = 0x00000089, -CB_PERF_SEL_FOP_FMASK_RAW_STALL__VI = 0x00000089, -CB_PERF_SEL_CC_SF_FULL__SI__CI = 0x0000008a, -CB_PERF_SEL_FOP_FMASK_BYPASS_STALL__VI = 0x0000008a, -CB_PERF_SEL_CC_RB_FULL__SI__CI = 0x0000008b, -CB_PERF_SEL_CC_SF_FULL__VI = 0x0000008b, -CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL__SI__CI = 0x0000008c, -CB_PERF_SEL_CC_RB_FULL__VI = 0x0000008c, -CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL__SI__CI = 0x0000008d, -CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL__VI = 0x0000008d, -CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL__SI__CI = 0x0000008e, -CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL__VI = 0x0000008e, -CB_PERF_SEL_EVENT__SI__CI = 0x0000008f, -CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL__VI = 0x0000008f, -CB_PERF_SEL_EVENT_CACHE_FLUSH_TS__SI__CI = 0x00000090, -CB_PERF_SEL_EVENT__VI = 0x00000090, -CB_PERF_SEL_EVENT_CONTEXT_DONE__SI__CI = 0x00000091, -CB_PERF_SEL_EVENT_CACHE_FLUSH_TS__VI = 0x00000091, -CB_PERF_SEL_EVENT_CACHE_FLUSH__SI__CI = 0x00000092, -CB_PERF_SEL_EVENT_CONTEXT_DONE__VI = 0x00000092, -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__SI__CI = 0x00000093, -CB_PERF_SEL_EVENT_CACHE_FLUSH__VI = 0x00000093, -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT__SI__CI = 0x00000094, -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__VI = 0x00000094, -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS__SI__CI = 0x00000095, -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT__VI = 0x00000095, -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META__SI__CI = 0x00000096, -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS__VI = 0x00000096, -CB_PERF_SEL_CC_SURFACE_SYNC__SI__CI = 0x00000097, -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META__VI = 0x00000097, -CB_PERF_SEL_CMASK_READ_DATA_0xC__SI__CI = 0x00000098, -CB_PERF_SEL_CC_SURFACE_SYNC__VI = 0x00000098, -CB_PERF_SEL_CMASK_READ_DATA_0xD__SI__CI = 0x00000099, -CB_PERF_SEL_CMASK_READ_DATA_0xC__VI = 0x00000099, -CB_PERF_SEL_CMASK_READ_DATA_0xE__SI__CI = 0x0000009a, -CB_PERF_SEL_CMASK_READ_DATA_0xD__VI = 0x0000009a, -CB_PERF_SEL_CMASK_READ_DATA_0xF__SI__CI = 0x0000009b, -CB_PERF_SEL_CMASK_READ_DATA_0xE__VI = 0x0000009b, -CB_PERF_SEL_CMASK_WRITE_DATA_0xC__SI__CI = 0x0000009c, -CB_PERF_SEL_CMASK_READ_DATA_0xF__VI = 0x0000009c, -CB_PERF_SEL_CMASK_WRITE_DATA_0xD__SI__CI = 0x0000009d, -CB_PERF_SEL_CMASK_WRITE_DATA_0xC__VI = 0x0000009d, -CB_PERF_SEL_CMASK_WRITE_DATA_0xE__SI__CI = 0x0000009e, -CB_PERF_SEL_CMASK_WRITE_DATA_0xD__VI = 0x0000009e, -CB_PERF_SEL_CMASK_WRITE_DATA_0xF__SI__CI = 0x0000009f, -CB_PERF_SEL_CMASK_WRITE_DATA_0xE__VI = 0x0000009f, -CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT__SI__CI = 0x000000a0, -CB_PERF_SEL_CMASK_WRITE_DATA_0xF__VI = 0x000000a0, -CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT__SI__CI = 0x000000a1, -CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT__VI = 0x000000a1, -CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT__SI__CI = 0x000000a2, -CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT__VI = 0x000000a2, -CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__SI__CI = 0x000000a3, -CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT__VI = 0x000000a3, -CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a4, -CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__VI = 0x000000a4, -CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a5, -CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a5, -CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a6, -CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a6, -CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a7, -CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a7, -CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a8, -CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a8, -CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000a9, -CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000a9, -CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__SI__CI = 0x000000aa, -CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000aa, -CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__SI__CI = 0x000000ab, -CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__VI = 0x000000ab, -CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000ac, -CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__VI = 0x000000ac, -CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000ad, -CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__VI = 0x000000ad, -CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000ae, -CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__VI = 0x000000ae, -CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000af, -CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__VI = 0x000000af, -CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000b0, -CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b0, -CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000b1, -CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b1, -CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__SI__CI = 0x000000b2, -CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b2, -CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT__SI__CI = 0x000000b3, -CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__VI = 0x000000b3, -CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS__SI__CI = 0x000000b4, -CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT__VI = 0x000000b4, -CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS__SI__CI = 0x000000b5, -CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS__VI = 0x000000b5, -CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS__SI__CI = 0x000000b6, -CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS__VI = 0x000000b6, -CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS__SI__CI = 0x000000b7, -CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS__VI = 0x000000b7, -CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS__SI__CI = 0x000000b8, -CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS__VI = 0x000000b8, -CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS__SI__CI = 0x000000b9, -CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS__VI = 0x000000b9, -CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT__SI__CI = 0x000000ba, -CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS__VI = 0x000000ba, -CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS__SI__CI = 0x000000bb, -CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT__VI = 0x000000bb, -CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS__SI__CI = 0x000000bc, -CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS__VI = 0x000000bc, -CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS__SI__CI = 0x000000bd, -CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS__VI = 0x000000bd, -CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS__SI__CI = 0x000000be, -CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS__VI = 0x000000be, -CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS__SI__CI = 0x000000bf, -CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS__VI = 0x000000bf, -CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS__SI__CI = 0x000000c0, -CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS__VI = 0x000000c0, -CB_PERF_SEL_QUAD_READS_FRAGMENT_0__SI__CI = 0x000000c1, -CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS__VI = 0x000000c1, -CB_PERF_SEL_QUAD_READS_FRAGMENT_1__SI__CI = 0x000000c2, -CB_PERF_SEL_QUAD_READS_FRAGMENT_0__VI = 0x000000c2, -CB_PERF_SEL_QUAD_READS_FRAGMENT_2__SI__CI = 0x000000c3, -CB_PERF_SEL_QUAD_READS_FRAGMENT_1__VI = 0x000000c3, -CB_PERF_SEL_QUAD_READS_FRAGMENT_3__SI__CI = 0x000000c4, -CB_PERF_SEL_QUAD_READS_FRAGMENT_2__VI = 0x000000c4, -CB_PERF_SEL_QUAD_READS_FRAGMENT_4__SI__CI = 0x000000c5, -CB_PERF_SEL_QUAD_READS_FRAGMENT_3__VI = 0x000000c5, -CB_PERF_SEL_QUAD_READS_FRAGMENT_5__SI__CI = 0x000000c6, -CB_PERF_SEL_QUAD_READS_FRAGMENT_4__VI = 0x000000c6, -CB_PERF_SEL_QUAD_READS_FRAGMENT_6__SI__CI = 0x000000c7, -CB_PERF_SEL_QUAD_READS_FRAGMENT_5__VI = 0x000000c7, -CB_PERF_SEL_QUAD_READS_FRAGMENT_7__SI__CI = 0x000000c8, -CB_PERF_SEL_QUAD_READS_FRAGMENT_6__VI = 0x000000c8, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0__SI__CI = 0x000000c9, -CB_PERF_SEL_QUAD_READS_FRAGMENT_7__VI = 0x000000c9, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1__SI__CI = 0x000000ca, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0__VI = 0x000000ca, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2__SI__CI = 0x000000cb, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1__VI = 0x000000cb, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3__SI__CI = 0x000000cc, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2__VI = 0x000000cc, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4__SI__CI = 0x000000cd, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3__VI = 0x000000cd, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5__SI__CI = 0x000000ce, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4__VI = 0x000000ce, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6__SI__CI = 0x000000cf, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5__VI = 0x000000cf, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7__SI__CI = 0x000000d0, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6__VI = 0x000000d0, -CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST__SI__CI = 0x000000d1, -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7__VI = 0x000000d1, -CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS__SI__CI = 0x000000d2, -CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST__VI = 0x000000d2, -CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS__SI__CI = 0x000000d3, -CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS__VI = 0x000000d3, -CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS__VI = 0x000000d4, -CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED__SI__CI = 0x000000d6, -CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST__CI = 0x000000d7, -CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED__VI = 0x000000d7, -CB_PERF_SEL_DRAWN_BUSY__CI = 0x000000d8, -CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST__VI = 0x000000d8, -CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY__CI = 0x000000d9, -CB_PERF_SEL_DRAWN_BUSY__VI = 0x000000d9, -CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY__CI = 0x000000da, -CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY__VI = 0x000000da, -CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY__CI = 0x000000db, -CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY__VI = 0x000000db, -CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY__CI = 0x000000dc, -CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY__VI = 0x000000dc, -CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY__VI = 0x000000dd, -CB_PERF_SEL_FC_SEQUENCER_CLEAR__CI = 0x000000de, -CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR__CI = 0x000000df, -CB_PERF_SEL_FC_SEQUENCER_CLEAR__VI = 0x000000df, -CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS__CI = 0x000000e0, -CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR__VI = 0x000000e0, -CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS__VI = 0x000000e1, -CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL__VI = 0x000000e3, -CB_PERF_SEL_FC_DOC_IS_STALLED__VI = 0x000000e4, -CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED__VI = 0x000000e5, -CB_PERF_SEL_FC_DOC_MRTS_COMBINED__VI = 0x000000e6, -CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS__VI = 0x000000e7, -CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT__VI = 0x000000e8, -CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS__VI = 0x000000e9, -CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT__VI = 0x000000ea, -CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL__VI = 0x000000eb, -CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR__VI = 0x000000ec, -CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS__VI = 0x000000ed, -CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS__VI = 0x000000ee, -CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS__VI = 0x000000ef, -CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS__VI = 0x000000f0, -CB_PERF_SEL_FC_DCC_CACHE_HIT__VI = 0x000000f1, -CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS__VI = 0x000000f2, -CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS__VI = 0x000000f3, -CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL__VI = 0x000000f4, -CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL__VI = 0x000000f8, -CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL__VI = 0x000000f9, -CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL__VI = 0x000000fa, -CB_PERF_SEL_FC_DCC_CACHE_STALL__VI = 0x000000fb, -CB_PERF_SEL_FC_DCC_CACHE_FLUSH__VI = 0x000000fc, -CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED__VI = 0x000000fd, -CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED__VI = 0x000000fe, -CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED__VI = 0x000000ff, -CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT__VI = 0x00000100, -CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST__VI = 0x00000101, -CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT__VI = 0x00000102, -CB_PERF_SEL_FC_MC_DCC_READ_REQUEST__VI = 0x00000103, -CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT__VI = 0x00000104, -CB_PERF_SEL_CC_DCC_RDREQ_STALL__VI = 0x00000105, -CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN__VI = 0x00000106, -CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT__VI = 0x00000107, -CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN__VI = 0x00000108, -CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT__VI = 0x00000109, -CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR__VI = 0x0000010a, -CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1__VI = 0x0000010b, -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1__VI = 0x0000011a, -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2__VI = 0x0000011f, -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3__VI = 0x00000124, -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0__VI = 0x0000015c, -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1__VI = 0x0000015d, -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0__VI = 0x00000163, -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1__VI = 0x00000164, -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1__VI = 0x0000016b, -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1__VI = 0x0000016c, -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2__VI = 0x00000172, -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2__VI = 0x00000173, -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1__VI = 0x00000174, -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2__VI = 0x00000175, -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3__VI = 0x00000176, -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4__VI = 0x00000177, -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5__VI = 0x00000178, -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6__VI = 0x00000179, -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7__VI = 0x0000017a, -CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED__VI = 0x0000017b, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1__VI = 0x0000017c, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1__VI = 0x0000017d, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2__VI = 0x0000017e, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3__VI = 0x0000017f, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1__VI = 0x00000180, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2__VI = 0x00000181, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3__VI = 0x00000182, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4__VI = 0x00000183, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5__VI = 0x00000184, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1__VI = 0x00000185, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2__VI = 0x00000186, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3__VI = 0x00000187, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4__VI = 0x00000188, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5__VI = 0x00000189, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6__VI = 0x0000018a, -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7__VI = 0x0000018b, -} CBPerfSel; - -typedef enum CHUB_TC_RET_CREDITS_ENUM { -CHUB_TC_RET_CREDITS = 0x00000020, -} CHUB_TC_RET_CREDITS_ENUM; - -typedef enum CLKGATE_BASE_MODE { -MULT_8 = 0x00000000, -MULT_16 = 0x00000001, -} CLKGATE_BASE_MODE; - -typedef enum CLKGATE_SM_MODE { -ON_SEQ = 0x00000000, -OFF_SEQ = 0x00000001, -PROG_SEQ = 0x00000002, -READ_SEQ = 0x00000003, -SM_MODE_RESERVED = 0x00000004, -} CLKGATE_SM_MODE; - -typedef enum CPC_PERFCOUNT_SEL { -CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000, -CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001, -CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002, -CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x00000003, -CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x00000004, -CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005, -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006, -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007, -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008, -CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x00000009, -CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0x0000000a, -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b, -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c, -CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d, -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e, -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f, -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010, -CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x00000011, -CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x00000012, -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013, -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014, -CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015, -CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE__VI = 0x00000016, -CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS__VI = 0x00000017, -CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION__VI = 0x00000018, -} CPC_PERFCOUNT_SEL; - -typedef enum CPF_PERFCOUNT_SEL { -CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000, -CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001, -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002, -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003, -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004, -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005, -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006, -CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007, -CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008, -CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x00000009, -CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a, -CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b, -CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c, -CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d, -CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e, -CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0x0000000f, -CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x00000010, -CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE__VI = 0x00000011, -CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS__VI = 0x00000012, -CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION__VI = 0x00000013, -} CPF_PERFCOUNT_SEL; - -typedef enum CPG_PERFCOUNT_SEL { -CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000, -CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001, -CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002, -CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000003, -CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004, -CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005, -CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006, -CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007, -CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x00000008, -CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009, -CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a, -CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b, -CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c, -CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d, -CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e, -CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f, -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010, -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011, -CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012, -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013, -CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014, -CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015, -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016, -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017, -CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018, -CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019, -CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a, -CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b, -CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c, -CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d, -CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e, -CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f, -CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020, -CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021, -CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x00000022, -CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x00000023, -CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024, -CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025, -CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026, -CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027, -CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x00000028, -CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029, -CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a, -CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b, -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c, -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d, -CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE__VI = 0x0000002e, -CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS__VI = 0x0000002f, -CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION__VI = 0x00000030, -} CPG_PERFCOUNT_SEL; - -typedef enum CP_ALPHA_TAG_RAM_SEL { -CPG_TAG_RAM = 0x00000000, -CPC_TAG_RAM = 0x00000001, -CPF_TAG_RAM = 0x00000002, -RSV_TAG_RAM = 0x00000003, -} CP_ALPHA_TAG_RAM_SEL; - -typedef enum CP_ME_ID { -ME_ID0 = 0x00000000, -ME_ID1 = 0x00000001, -ME_ID2 = 0x00000002, -ME_ID3 = 0x00000003, -} CP_ME_ID; - -typedef enum CP_PERFMON_ENABLE_MODE { -CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000, -CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001, -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002, -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003, -} CP_PERFMON_ENABLE_MODE; - -typedef enum CP_PERFMON_STATE { -CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, -CP_PERFMON_STATE_START_COUNTING = 0x00000001, -CP_PERFMON_STATE_STOP_COUNTING = 0x00000002, -CP_PERFMON_STATE_RESERVED_3 = 0x00000003, -CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, -CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, -} CP_PERFMON_STATE; - -typedef enum CP_PIPE_ID { -PIPE_ID0 = 0x00000000, -PIPE_ID1 = 0x00000001, -PIPE_ID2 = 0x00000002, -PIPE_ID3 = 0x00000003, -} CP_PIPE_ID; - -typedef enum CP_RING_ID { -RINGID0 = 0x00000000, -RINGID1 = 0x00000001, -RINGID2 = 0x00000002, -RINGID3__CI__VI = 0x00000003, -} CP_RING_ID; - -typedef enum CSDATA_TYPE { -CSDATA_TYPE_TG = 0x00000000, -CSDATA_TYPE_STATE = 0x00000001, -CSDATA_TYPE_EVENT = 0x00000002, -CSDATA_TYPE_PRIVATE = 0x00000003, -} CSDATA_TYPE; - -typedef enum CmaskCode { -CMASK_CLR00_F0 = 0x00000000, -CMASK_CLR00_F1 = 0x00000001, -CMASK_CLR00_F2 = 0x00000002, -CMASK_CLR00_FX = 0x00000003, -CMASK_CLR01_F0 = 0x00000004, -CMASK_CLR01_F1 = 0x00000005, -CMASK_CLR01_F2 = 0x00000006, -CMASK_CLR01_FX = 0x00000007, -CMASK_CLR10_F0 = 0x00000008, -CMASK_CLR10_F1 = 0x00000009, -CMASK_CLR10_F2 = 0x0000000a, -CMASK_CLR10_FX = 0x0000000b, -CMASK_CLR11_F0 = 0x0000000c, -CMASK_CLR11_F1 = 0x0000000d, -CMASK_CLR11_F2 = 0x0000000e, -CMASK_CLR11_FX = 0x0000000f, -} CmaskCode; - -typedef enum CmaskMode { -CMASK_CLEAR_NONE = 0x00000000, -CMASK_CLEAR_ONE = 0x00000001, -CMASK_CLEAR_ALL = 0x00000002, -CMASK_ANY_EXPANDED = 0x00000003, -CMASK_ALPHA0_FRAG1 = 0x00000004, -CMASK_ALPHA0_FRAG2 = 0x00000005, -CMASK_ALPHA0_FRAG4 = 0x00000006, -CMASK_ALPHA0_FRAGS = 0x00000007, -CMASK_ALPHA1_FRAG1 = 0x00000008, -CMASK_ALPHA1_FRAG2 = 0x00000009, -CMASK_ALPHA1_FRAG4 = 0x0000000a, -CMASK_ALPHA1_FRAGS = 0x0000000b, -CMASK_ALPHAX_FRAG1 = 0x0000000c, -CMASK_ALPHAX_FRAG2 = 0x0000000d, -CMASK_ALPHAX_FRAG4 = 0x0000000e, -CMASK_ALPHAX_FRAGS = 0x0000000f, -} CmaskMode; - -typedef enum ColorArray { -ARRAY_2D_ALT_COLOR = 0x00000000, -ARRAY_2D_COLOR = 0x00000001, -ARRAY_3D_SLICE_COLOR = 0x00000003, -} ColorArray; - -typedef enum ColorFormat { -COLOR_INVALID = 0x00000000, -COLOR_8 = 0x00000001, -COLOR_16 = 0x00000002, -COLOR_8_8 = 0x00000003, -COLOR_32 = 0x00000004, -COLOR_16_16 = 0x00000005, -COLOR_10_11_11 = 0x00000006, -COLOR_11_11_10 = 0x00000007, -COLOR_10_10_10_2 = 0x00000008, -COLOR_2_10_10_10 = 0x00000009, -COLOR_8_8_8_8 = 0x0000000a, -COLOR_32_32 = 0x0000000b, -COLOR_16_16_16_16 = 0x0000000c, -COLOR_RESERVED_13 = 0x0000000d, -COLOR_32_32_32_32 = 0x0000000e, -COLOR_RESERVED_15 = 0x0000000f, -COLOR_5_6_5 = 0x00000010, -COLOR_1_5_5_5 = 0x00000011, -COLOR_5_5_5_1 = 0x00000012, -COLOR_4_4_4_4 = 0x00000013, -COLOR_8_24 = 0x00000014, -COLOR_24_8 = 0x00000015, -COLOR_X24_8_32_FLOAT = 0x00000016, -COLOR_RESERVED_23 = 0x00000017, -} ColorFormat; - -typedef enum CombFunc { -COMB_DST_PLUS_SRC = 0x00000000, -COMB_SRC_MINUS_DST = 0x00000001, -COMB_MIN_DST_SRC = 0x00000002, -COMB_MAX_DST_SRC = 0x00000003, -COMB_DST_MINUS_SRC = 0x00000004, -} CombFunc; - -typedef enum CompareFrag { -FRAG_NEVER = 0x00000000, -FRAG_LESS = 0x00000001, -FRAG_EQUAL = 0x00000002, -FRAG_LEQUAL = 0x00000003, -FRAG_GREATER = 0x00000004, -FRAG_NOTEQUAL = 0x00000005, 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0x00000007, -DBG_BLOCK_ID_SPIM_BY2 = 0x00000009, -DBG_BLOCK_ID_SPIS_BY2 = 0x0000000a, -DBG_BLOCK_ID_PA0_BY2 = 0x0000000b, -DBG_BLOCK_ID_CP0_BY2 = 0x0000000c, -DBG_BLOCK_ID_CP2_BY2 = 0x0000000d, -DBG_BLOCK_ID_UVDU_BY2 = 0x0000000e, -DBG_BLOCK_ID_VCE_BY2 = 0x0000000f, -DBG_BLOCK_ID_VGT0_BY2 = 0x00000010, -DBG_BLOCK_ID_IA_BY2 = 0x00000011, -DBG_BLOCK_ID_SCT0_BY2 = 0x00000012, -DBG_BLOCK_ID_SPM0_BY2 = 0x00000013, -DBG_BLOCK_ID_TCAA_BY2 = 0x00000014, -DBG_BLOCK_ID_TCCA_BY2 = 0x00000015, -DBG_BLOCK_ID_MCC0_BY2 = 0x00000016, -DBG_BLOCK_ID_MCC2_BY2 = 0x00000017, -DBG_BLOCK_ID_SX0_BY2 = 0x00000018, -DBG_BLOCK_ID_SX2_BY2 = 0x00000019, -DBG_BLOCK_ID_UNUSED4_BY2 = 0x0000001a, -DBG_BLOCK_ID_UNUSED6_BY2 = 0x0000001b, -DBG_BLOCK_ID_PC0_BY2 = 0x0000001c, -DBG_BLOCK_ID_UNUSED8_BY2 = 0x0000001d, -DBG_BLOCK_ID_UNUSED10_BY2 = 0x0000001e, -DBG_BLOCK_ID_MCB_BY2 = 0x0000001f, -DBG_BLOCK_ID_SCB0_BY2 = 0x00000020, -DBG_BLOCK_ID_UNUSED13_BY2 = 0x00000021, -DBG_BLOCK_ID_SCF0_BY2 = 0x00000022, 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-DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x0000003d, -DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x0000003e, -DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x0000003f, -DBG_BLOCK_ID_DB00_BY2 = 0x00000040, -DBG_BLOCK_ID_DB02_BY2 = 0x00000041, -DBG_BLOCK_ID_DB04_BY2 = 0x00000042, -DBG_BLOCK_ID_UNUSED28_BY2 = 0x00000043, -DBG_BLOCK_ID_DB10_BY2 = 0x00000044, -DBG_BLOCK_ID_DB12_BY2 = 0x00000045, -DBG_BLOCK_ID_DB14_BY2 = 0x00000046, -DBG_BLOCK_ID_UNUSED31_BY2 = 0x00000047, -DBG_BLOCK_ID_TCC0_BY2 = 0x00000048, -DBG_BLOCK_ID_TCC2_BY2 = 0x00000049, -DBG_BLOCK_ID_TCC4_BY2 = 0x0000004a, -DBG_BLOCK_ID_TCC6_BY2 = 0x0000004b, -DBG_BLOCK_ID_SPS00_BY2 = 0x0000004c, -DBG_BLOCK_ID_SPS02_BY2 = 0x0000004d, -DBG_BLOCK_ID_SPS11_BY2 = 0x0000004e, -DBG_BLOCK_ID_UNUSED33_BY2 = 0x0000004f, -DBG_BLOCK_ID_TA00_BY2 = 0x00000050, -DBG_BLOCK_ID_TA02_BY2 = 0x00000051, -DBG_BLOCK_ID_TA04_BY2 = 0x00000052, -DBG_BLOCK_ID_TA06_BY2 = 0x00000053, -DBG_BLOCK_ID_TA08_BY2 = 0x00000054, -DBG_BLOCK_ID_TA0A_BY2 = 0x00000055, -DBG_BLOCK_ID_UNUSED35_BY2 = 0x00000056, -DBG_BLOCK_ID_UNUSED37_BY2 = 0x00000057, -DBG_BLOCK_ID_TA10_BY2 = 0x00000058, -DBG_BLOCK_ID_TA12_BY2 = 0x00000059, -DBG_BLOCK_ID_TA14_BY2 = 0x0000005a, -DBG_BLOCK_ID_TA16_BY2 = 0x0000005b, -DBG_BLOCK_ID_TA18_BY2 = 0x0000005c, -DBG_BLOCK_ID_TA1A_BY2 = 0x0000005d, -DBG_BLOCK_ID_UNUSED39_BY2 = 0x0000005e, -DBG_BLOCK_ID_UNUSED41_BY2 = 0x0000005f, -DBG_BLOCK_ID_TD00_BY2 = 0x00000060, -DBG_BLOCK_ID_TD02_BY2 = 0x00000061, -DBG_BLOCK_ID_TD04_BY2 = 0x00000062, -DBG_BLOCK_ID_TD06_BY2 = 0x00000063, -DBG_BLOCK_ID_TD08_BY2 = 0x00000064, -DBG_BLOCK_ID_TD0A_BY2 = 0x00000065, -DBG_BLOCK_ID_UNUSED43_BY2 = 0x00000066, -DBG_BLOCK_ID_UNUSED45_BY2 = 0x00000067, -DBG_BLOCK_ID_TD10_BY2 = 0x00000068, -DBG_BLOCK_ID_TD12_BY2 = 0x00000069, -DBG_BLOCK_ID_TD14_BY2 = 0x0000006a, -DBG_BLOCK_ID_TD16_BY2 = 0x0000006b, -DBG_BLOCK_ID_TD18_BY2 = 0x0000006c, -DBG_BLOCK_ID_TD1A_BY2 = 0x0000006d, -DBG_BLOCK_ID_UNUSED47_BY2 = 0x0000006e, -DBG_BLOCK_ID_UNUSED49_BY2 = 0x0000006f, -DBG_BLOCK_ID_MCD0_BY2 = 0x00000070, -DBG_BLOCK_ID_MCD2_BY2 = 0x00000071, -DBG_BLOCK_ID_MCD4_BY2 = 0x00000072, -DBG_BLOCK_ID_UNUSED51_BY2 = 0x00000073, -} DebugBlockId_BY2; - -typedef enum DebugBlockId_BY4 { -DBG_BLOCK_ID_RESERVED_BY4 = 0x00000000, -DBG_BLOCK_ID_CG_BY4 = 0x00000001, -DBG_BLOCK_ID_CSC_BY4 = 0x00000002, -DBG_BLOCK_ID_SQ_BY4 = 0x00000003, -DBG_BLOCK_ID_SPIS_BY4 = 0x00000005, -DBG_BLOCK_ID_CP0_BY4 = 0x00000006, -DBG_BLOCK_ID_UVDU_BY4 = 0x00000007, -DBG_BLOCK_ID_VGT0_BY4 = 0x00000008, -DBG_BLOCK_ID_SCT0_BY4 = 0x00000009, -DBG_BLOCK_ID_TCAA_BY4 = 0x0000000a, -DBG_BLOCK_ID_MCC0_BY4 = 0x0000000b, -DBG_BLOCK_ID_SX0_BY4 = 0x0000000c, -DBG_BLOCK_ID_UNUSED4_BY4 = 0x0000000d, -DBG_BLOCK_ID_PC0_BY4 = 0x0000000e, -DBG_BLOCK_ID_UNUSED10_BY4 = 0x0000000f, -DBG_BLOCK_ID_SCB0_BY4 = 0x00000010, -DBG_BLOCK_ID_SCF0_BY4 = 0x00000011, -DBG_BLOCK_ID_BCI0_BY4 = 0x00000012, -DBG_BLOCK_ID_UNUSED17_BY4 = 0x00000013, -DBG_BLOCK_ID_CB00_BY4 = 0x00000014, -DBG_BLOCK_ID_CB04_BY4 = 0x00000015, -DBG_BLOCK_ID_CB10_BY4 = 0x00000016, -DBG_BLOCK_ID_CB14_BY4 = 0x00000017, -DBG_BLOCK_ID_TCP0_BY4 = 0x00000018, -DBG_BLOCK_ID_TCP4_BY4 = 0x00000019, -DBG_BLOCK_ID_TCP8_BY4 = 0x0000001a, -DBG_BLOCK_ID_TCP12_BY4 = 0x0000001b, -DBG_BLOCK_ID_TCP16_BY4 = 0x0000001c, -DBG_BLOCK_ID_TCP20_BY4 = 0x0000001d, -DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x0000001e, -DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x0000001f, -DBG_BLOCK_ID_DB_BY4 = 0x00000020, -DBG_BLOCK_ID_DB04_BY4 = 0x00000021, -DBG_BLOCK_ID_DB10_BY4 = 0x00000022, -DBG_BLOCK_ID_DB14_BY4 = 0x00000023, -DBG_BLOCK_ID_TCC0_BY4 = 0x00000024, -DBG_BLOCK_ID_TCC4_BY4 = 0x00000025, -DBG_BLOCK_ID_SPS00_BY4 = 0x00000026, -DBG_BLOCK_ID_SPS11_BY4 = 0x00000027, -DBG_BLOCK_ID_TA00_BY4 = 0x00000028, -DBG_BLOCK_ID_TA04_BY4 = 0x00000029, -DBG_BLOCK_ID_TA08_BY4 = 0x0000002a, -DBG_BLOCK_ID_UNUSED35_BY4 = 0x0000002b, -DBG_BLOCK_ID_TA10_BY4 = 0x0000002c, -DBG_BLOCK_ID_TA14_BY4 = 0x0000002d, -DBG_BLOCK_ID_TA18_BY4 = 0x0000002e, -DBG_BLOCK_ID_UNUSED39_BY4 = 0x0000002f, -DBG_BLOCK_ID_TD00_BY4 = 0x00000030, -DBG_BLOCK_ID_TD04_BY4 = 0x00000031, -DBG_BLOCK_ID_TD08_BY4 = 0x00000032, -DBG_BLOCK_ID_UNUSED43_BY4 = 0x00000033, -DBG_BLOCK_ID_TD10_BY4 = 0x00000034, -DBG_BLOCK_ID_TD14_BY4 = 0x00000035, -DBG_BLOCK_ID_TD18_BY4 = 0x00000036, -DBG_BLOCK_ID_UNUSED47_BY4 = 0x00000037, -DBG_BLOCK_ID_MCD0_BY4 = 0x00000038, -DBG_BLOCK_ID_MCD4_BY4 = 0x00000039, -} DebugBlockId_BY4; - -typedef enum DebugBlockId_BY8 { -DBG_BLOCK_ID_RESERVED_BY8 = 0x00000000, -DBG_BLOCK_ID_CSC_BY8 = 0x00000001, -DBG_BLOCK_ID_CP0_BY8 = 0x00000003, -DBG_BLOCK_ID_VGT0_BY8 = 0x00000004, -DBG_BLOCK_ID_TCAA_BY8 = 0x00000005, -DBG_BLOCK_ID_SX0_BY8 = 0x00000006, -DBG_BLOCK_ID_PC0_BY8 = 0x00000007, -DBG_BLOCK_ID_SCB0_BY8 = 0x00000008, -DBG_BLOCK_ID_BCI0_BY8 = 0x00000009, -DBG_BLOCK_ID_CB00_BY8 = 0x0000000a, -DBG_BLOCK_ID_CB10_BY8 = 0x0000000b, -DBG_BLOCK_ID_TCP0_BY8 = 0x0000000c, -DBG_BLOCK_ID_TCP8_BY8 = 0x0000000d, -DBG_BLOCK_ID_TCP16_BY8 = 0x0000000e, -DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0x0000000f, -DBG_BLOCK_ID_DB00_BY8 = 0x00000010, -DBG_BLOCK_ID_DB10_BY8 = 0x00000011, -DBG_BLOCK_ID_TCC0_BY8 = 0x00000012, -DBG_BLOCK_ID_SPS00_BY8 = 0x00000013, -DBG_BLOCK_ID_TA00_BY8 = 0x00000014, -DBG_BLOCK_ID_TA08_BY8 = 0x00000015, -DBG_BLOCK_ID_TA10_BY8 = 0x00000016, -DBG_BLOCK_ID_TA18_BY8 = 0x00000017, -DBG_BLOCK_ID_TD00_BY8 = 0x00000018, -DBG_BLOCK_ID_TD08_BY8 = 0x00000019, -DBG_BLOCK_ID_TD10_BY8 = 0x0000001a, -DBG_BLOCK_ID_TD18_BY8 = 0x0000001b, -DBG_BLOCK_ID_MCD0_BY8 = 0x0000001c, -} DebugBlockId_BY8; - -typedef enum DepthArray { -ARRAY_2D_ALT_DEPTH = 0x00000000, -ARRAY_2D_DEPTH = 0x00000001, -} DepthArray; - -typedef enum DepthFormat { -DEPTH_INVALID = 0x00000000, -DEPTH_16 = 0x00000001, -DEPTH_X8_24 = 0x00000002, -DEPTH_8_24 = 0x00000003, -DEPTH_X8_24_FLOAT = 0x00000004, -DEPTH_8_24_FLOAT = 0x00000005, -DEPTH_32_FLOAT = 0x00000006, -DEPTH_X24_8_32_FLOAT = 0x00000007, -} DepthFormat; - -typedef enum ENUM_SQ_EXPORT_RAT_INST { -SQ_EXPORT_RAT_INST_NOP = 0x00000000, -SQ_EXPORT_RAT_INST_STORE_TYPED = 0x00000001, -SQ_EXPORT_RAT_INST_STORE_RAW = 0x00000002, -SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x00000003, -SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x00000004, -SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x00000005, -SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x00000006, -SQ_EXPORT_RAT_INST_ADD = 0x00000007, -SQ_EXPORT_RAT_INST_SUB = 0x00000008, -SQ_EXPORT_RAT_INST_RSUB = 0x00000009, -SQ_EXPORT_RAT_INST_MIN_INT = 0x0000000a, -SQ_EXPORT_RAT_INST_MIN_UINT = 0x0000000b, -SQ_EXPORT_RAT_INST_MAX_INT = 0x0000000c, -SQ_EXPORT_RAT_INST_MAX_UINT = 0x0000000d, -SQ_EXPORT_RAT_INST_AND = 0x0000000e, -SQ_EXPORT_RAT_INST_OR = 0x0000000f, -SQ_EXPORT_RAT_INST_XOR = 0x00000010, -SQ_EXPORT_RAT_INST_MSKOR = 0x00000011, -SQ_EXPORT_RAT_INST_INC_UINT = 0x00000012, -SQ_EXPORT_RAT_INST_DEC_UINT = 0x00000013, -SQ_EXPORT_RAT_INST_STORE_DWORD = 0x00000014, -SQ_EXPORT_RAT_INST_STORE_SHORT = 0x00000015, -SQ_EXPORT_RAT_INST_STORE_BYTE = 0x00000016, -SQ_EXPORT_RAT_INST_NOP_RTN = 0x00000020, -SQ_EXPORT_RAT_INST_XCHG_RTN = 0x00000022, -SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x00000023, -SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x00000024, -SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x00000025, -SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x00000026, -SQ_EXPORT_RAT_INST_ADD_RTN = 0x00000027, -SQ_EXPORT_RAT_INST_SUB_RTN = 0x00000028, -SQ_EXPORT_RAT_INST_RSUB_RTN = 0x00000029, -SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x0000002a, -SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x0000002b, -SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x0000002c, -SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x0000002d, -SQ_EXPORT_RAT_INST_AND_RTN = 0x0000002e, -SQ_EXPORT_RAT_INST_OR_RTN = 0x0000002f, -SQ_EXPORT_RAT_INST_XOR_RTN = 0x00000030, -SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x00000031, -SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x00000032, -SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x00000033, -} ENUM_SQ_EXPORT_RAT_INST; - -typedef enum ForceControl { -FORCE_OFF = 0x00000000, -FORCE_ENABLE = 0x00000001, -FORCE_DISABLE = 0x00000002, -FORCE_RESERVED = 0x00000003, -} ForceControl; - -typedef enum GB_EDC_DED_MODE { -GB_EDC_DED_MODE_LOG = 0x00000000, -GB_EDC_DED_MODE_HALT = 0x00000001, -GB_EDC_DED_MODE_INT_HALT = 0x00000002, -} GB_EDC_DED_MODE; - -typedef enum GRBM_PERF_SEL { -GRBM_PERF_SEL_COUNT = 0x00000000, -GRBM_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002, -GRBM_PERF_SEL_CP_BUSY = 0x00000003, -GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004, -GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005, -GRBM_PERF_SEL_CB_BUSY = 0x00000006, -GRBM_PERF_SEL_DB_BUSY = 0x00000007, -GRBM_PERF_SEL_PA_BUSY = 0x00000008, -GRBM_PERF_SEL_SC_BUSY = 0x00000009, -GRBM_PERF_SEL_RESERVED_2__SI = 0x0000000a, -GRBM_PERF_SEL_RESERVED_6__CI__VI = 0x0000000a, -GRBM_PERF_SEL_SPI_BUSY = 0x0000000b, -GRBM_PERF_SEL_SX_BUSY = 0x0000000c, -GRBM_PERF_SEL_TA_BUSY = 0x0000000d, -GRBM_PERF_SEL_CB_CLEAN = 0x0000000e, -GRBM_PERF_SEL_DB_CLEAN = 0x0000000f, -GRBM_PERF_SEL_RESERVED_1__SI = 0x00000010, -GRBM_PERF_SEL_RESERVED_5__CI__VI = 0x00000010, -GRBM_PERF_SEL_VGT_BUSY = 0x00000011, -GRBM_PERF_SEL_RESERVED_0__SI = 0x00000012, -GRBM_PERF_SEL_RESERVED_4__CI__VI = 0x00000012, -GRBM_PERF_SEL_RESERVED_3__CI__VI = 0x00000013, -GRBM_PERF_SEL_RESERVED_2__CI__VI = 0x00000014, -GRBM_PERF_SEL_RESERVED_1__CI__VI = 0x00000015, -GRBM_PERF_SEL_RESERVED_0__CI__VI = 0x00000016, -GRBM_PERF_SEL_IA_BUSY = 0x00000017, -GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x00000018, -GRBM_PERF_SEL_GDS_BUSY = 0x00000019, -GRBM_PERF_SEL_BCI_BUSY = 0x0000001a, -GRBM_PERF_SEL_RLC_BUSY = 0x0000001b, -GRBM_PERF_SEL_TC_BUSY = 0x0000001c, -GRBM_PERF_SEL_CPG_BUSY__CI__VI = 0x0000001d, -GRBM_PERF_SEL_CPC_BUSY__CI__VI = 0x0000001e, -GRBM_PERF_SEL_CPF_BUSY__CI__VI = 0x0000001f, -GRBM_PERF_SEL_WD_BUSY__CI__VI = 0x00000020, -GRBM_PERF_SEL_WD_NO_DMA_BUSY__CI__VI = 0x00000021, -} GRBM_PERF_SEL; - -typedef enum GRBM_SE0_PERF_SEL { -GRBM_SE0_PERF_SEL_COUNT = 0x00000000, -GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE0_PERF_SEL_RESERVED_1 = 0x00000005, -GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE0_PERF_SEL_RESERVED_0 = 0x0000000b, -GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE0_PERF_SEL_VGT_BUSY = 0x0000000d, -GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e, -} GRBM_SE0_PERF_SEL; - -typedef enum GRBM_SE1_PERF_SEL { -GRBM_SE1_PERF_SEL_COUNT = 0x00000000, -GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE1_PERF_SEL_RESERVED_1 = 0x00000005, -GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE1_PERF_SEL_RESERVED_0 = 0x0000000b, -GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE1_PERF_SEL_VGT_BUSY = 0x0000000d, -GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e, -} GRBM_SE1_PERF_SEL; - -typedef enum GRBM_SE2_PERF_SEL { -GRBM_SE2_PERF_SEL_COUNT = 0x00000000, -GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE2_PERF_SEL_RESERVED_1 = 0x00000005, -GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE2_PERF_SEL_RESERVED_0 = 0x0000000b, -GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE2_PERF_SEL_VGT_BUSY = 0x0000000d, -GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e, -} GRBM_SE2_PERF_SEL; - -typedef enum GRBM_SE3_PERF_SEL { -GRBM_SE3_PERF_SEL_COUNT = 0x00000000, -GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE3_PERF_SEL_RESERVED_1 = 0x00000005, -GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE3_PERF_SEL_RESERVED_0 = 0x0000000b, -GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE3_PERF_SEL_VGT_BUSY = 0x0000000d, -GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e, -} GRBM_SE3_PERF_SEL; - -typedef enum GroupInterleave { -CONFIG_256B_GROUP = 0x00000000, -CONFIG_512B_GROUP = 0x00000001, -} GroupInterleave; - -typedef enum IA_PERFCOUNT_SELECT { -ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE__CI__VI = 0x00000000, -ia_perf_MC_LAT_BIN_0__CI = 0x00000001, -ia_perf_dma_data_fifo_full__VI = 0x00000001, -ia_perf_MC_LAT_BIN_1__CI = 0x00000002, -ia_perf_RESERVED1__VI = 0x00000002, -ia_perf_MC_LAT_BIN_2__CI = 0x00000003, -ia_perf_RESERVED2__VI = 0x00000003, -ia_perf_MC_LAT_BIN_3__CI = 0x00000004, -ia_perf_RESERVED3__VI = 0x00000004, -ia_perf_MC_LAT_BIN_4__CI = 0x00000005, -ia_perf_RESERVED4__VI = 0x00000005, -ia_perf_MC_LAT_BIN_5__CI = 0x00000006, -ia_perf_RESERVED5__VI = 0x00000006, -ia_perf_MC_LAT_BIN_0__SI__VI = 0x00000007, -ia_perf_MC_LAT_BIN_6__CI = 0x00000007, -ia_perf_MC_LAT_BIN_1__SI__VI = 0x00000008, -ia_perf_MC_LAT_BIN_7__CI = 0x00000008, -ia_perf_MC_LAT_BIN_2__SI__VI = 0x00000009, -ia_perf_ia_busy__CI = 0x00000009, -ia_perf_MC_LAT_BIN_3__SI__VI = 0x0000000a, -ia_perf_ia_sclk_reg_vld_event__CI = 0x0000000a, -ia_perf_MC_LAT_BIN_4__SI__VI = 0x0000000b, -ia_perf_RESERVED0__CI = 0x0000000b, -ia_perf_MC_LAT_BIN_5__SI__VI = 0x0000000c, -ia_perf_ia_sclk_core_vld_event__CI = 0x0000000c, -ia_perf_MC_LAT_BIN_6__SI__VI = 0x0000000d, -ia_perf_RESERVED1__CI = 0x0000000d, -ia_perf_MC_LAT_BIN_7__SI__VI = 0x0000000e, -ia_perf_ia_dma_return__CI = 0x0000000e, -ia_perf_ia_busy__SI__VI = 0x0000000f, -ia_perf_shift_starved_pipe1_event__CI = 0x0000000f, -ia_perf_ia_sclk_reg_vld_event__SI__VI = 0x00000010, -ia_perf_shift_starved_pipe0_event__CI = 0x00000010, -ia_perf_ia_stalled__CI = 0x00000011, -ia_perf_RESERVED6__VI = 0x00000011, -ia_perf_ia_sclk_core_vld_event__SI__VI = 0x00000012, -ia_perf_RESERVED7__VI = 0x00000013, -ia_perf_ia_dma_return__SI__VI = 0x00000014, -ia_perf_ia_stalled__SI__VI = 0x00000015, -ia_perf_shift_starved_pipe0_event__VI = 0x00000016, -ia_perf_shift_starved_pipe1_event__VI = 0x00000017, -} IA_PERFCOUNT_SELECT; - -typedef enum IH_CLIENT_ID { -DC_IH_SRC_ID_START = 0x00000001, -DC_IH_SRC_ID_END = 0x0000001f, -VGA_IH_SRC_ID_START = 0x00000020, -VGA_IH_SRC_ID_END = 0x00000027, -CAP_IH_SRC_ID_START = 0x00000028, -CAP_IH_SRC_ID_END = 0x0000002f, -VIP_IH_SRC_ID_START = 0x00000030, -VIP_IH_SRC_ID_END = 0x0000003f, -ROM_IH_SRC_ID_START = 0x00000040, -ROM_IH_SRC_ID_END = 0x0000005d, -BIF_IH_SRC_ID_START = 0x0000005e, -SAM_IH_SRC_ID_START__CI__VI = 0x0000005f, -SRBM_IH_SRC_ID_START = 0x00000060, -SRBM_IH_SRC_ID_END = 0x00000067, -UVD_IH_SRC_ID_START = 0x00000072, -UVD_IH_SRC_ID_END = 0x00000085, -VMC_IH_SRC_ID_START = 0x00000086, -VMC_IH_SRC_ID_END = 0x0000008f, -RLC_IH_SRC_ID_START = 0x00000090, -RLC_IH_SRC_ID_END = 0x000000f3, -PDMA_IH_SRC_ID_START = 0x000000f4, -PDMA_IH_SRC_ID_END = 0x000000f7, -CG_IH_SRC_ID_START = 0x000000f8, -CG_IH_SRC_ID_END = 0x000000ff, -} IH_CLIENT_ID; - -typedef enum IH_PERF_SEL { -IH_PERF_SEL_CYCLE__CI__VI = 0x00000000, -IH_PERF_SEL_IDLE__CI__VI = 0x00000001, -IH_PERF_SEL_INPUT_IDLE__CI__VI = 0x00000002, -IH_PERF_SEL_CLIENT0_IH_STALL__CI__VI = 0x00000003, -IH_PERF_SEL_CLIENT1_IH_STALL__CI__VI = 0x00000004, -IH_PERF_SEL_CLIENT2_IH_STALL__CI__VI = 0x00000005, -IH_PERF_SEL_CLIENT3_IH_STALL__CI__VI = 0x00000006, -IH_PERF_SEL_CLIENT4_IH_STALL__CI__VI = 0x00000007, -IH_PERF_SEL_CLIENT5_IH_STALL__CI__VI = 0x00000008, -IH_PERF_SEL_CLIENT6_IH_STALL__CI__VI = 0x00000009, -IH_PERF_SEL_CLIENT7_IH_STALL__CI__VI = 0x0000000a, -IH_PERF_SEL_RB_IDLE__CI__VI = 0x0000000b, -IH_PERF_SEL_RB_FULL__CI__VI = 0x0000000c, -IH_PERF_SEL_RB_OVERFLOW__CI__VI = 0x0000000d, -IH_PERF_SEL_RB_WPTR_WRITEBACK__CI__VI = 0x0000000e, -IH_PERF_SEL_RB_WPTR_WRAP__CI__VI = 0x0000000f, -IH_PERF_SEL_RB_RPTR_WRAP__CI__VI = 0x00000010, -IH_PERF_SEL_MC_WR_IDLE__CI__VI = 0x00000011, -IH_PERF_SEL_MC_WR_COUNT__CI__VI = 0x00000012, -IH_PERF_SEL_MC_WR_STALL__CI__VI = 0x00000013, -IH_PERF_SEL_MC_WR_CLEAN_PENDING__CI__VI = 0x00000014, -IH_PERF_SEL_MC_WR_CLEAN_STALL__CI__VI = 0x00000015, -IH_PERF_SEL_BIF_RISING__CI__VI = 0x00000016, -IH_PERF_SEL_BIF_FALLING__CI__VI = 0x00000017, -IH_PERF_SEL_CLIENT8_IH_STALL__CI__VI = 0x00000018, -IH_PERF_SEL_CLIENT9_IH_STALL__CI__VI = 0x00000019, -IH_PERF_SEL_CLIENT10_IH_STALL__CI__VI = 0x0000001a, -IH_PERF_SEL_CLIENT11_IH_STALL__CI__VI = 0x0000001b, -IH_PERF_SEL_CLIENT12_IH_STALL__CI__VI = 0x0000001c, -IH_PERF_SEL_CLIENT13_IH_STALL__CI__VI = 0x0000001d, -IH_PERF_SEL_CLIENT14_IH_STALL__CI__VI = 0x0000001e, -IH_PERF_SEL_CLIENT15_IH_STALL__CI__VI = 0x0000001f, -IH_PERF_SEL_CLIENT16_IH_STALL__CI__VI = 0x00000020, -IH_PERF_SEL_CLIENT17_IH_STALL__CI__VI = 0x00000021, -IH_PERF_SEL_CLIENT18_IH_STALL__CI__VI = 0x00000022, -IH_PERF_SEL_CLIENT19_IH_STALL__CI__VI = 0x00000023, -IH_PERF_SEL_CLIENT20_IH_STALL__VI = 0x00000024, -IH_PERF_SEL_CLIENT21_IH_STALL__VI = 0x00000025, -IH_PERF_SEL_CLIENT22_IH_STALL__VI = 0x00000026, -IH_PERF_SEL_RB_FULL_VF0__VI = 0x00000027, -IH_PERF_SEL_RB_FULL_VF1__VI = 0x00000028, -IH_PERF_SEL_RB_FULL_VF2__VI = 0x00000029, -IH_PERF_SEL_RB_FULL_VF3__VI = 0x0000002a, -IH_PERF_SEL_RB_FULL_VF4__VI = 0x0000002b, -IH_PERF_SEL_RB_FULL_VF5__VI = 0x0000002c, -IH_PERF_SEL_RB_FULL_VF6__VI = 0x0000002d, -IH_PERF_SEL_RB_FULL_VF7__VI = 0x0000002e, -IH_PERF_SEL_RB_FULL_VF8__VI = 0x0000002f, -IH_PERF_SEL_RB_FULL_VF9__VI = 0x00000030, -IH_PERF_SEL_RB_FULL_VF10__VI = 0x00000031, -IH_PERF_SEL_RB_FULL_VF11__VI = 0x00000032, -IH_PERF_SEL_RB_FULL_VF12__VI = 0x00000033, -IH_PERF_SEL_RB_FULL_VF13__VI = 0x00000034, -IH_PERF_SEL_RB_FULL_VF14__VI = 0x00000035, -IH_PERF_SEL_RB_FULL_VF15__VI = 0x00000036, -IH_PERF_SEL_RB_OVERFLOW_VF0__VI = 0x00000037, -IH_PERF_SEL_RB_OVERFLOW_VF1__VI = 0x00000038, -IH_PERF_SEL_RB_OVERFLOW_VF2__VI = 0x00000039, -IH_PERF_SEL_RB_OVERFLOW_VF3__VI = 0x0000003a, -IH_PERF_SEL_RB_OVERFLOW_VF4__VI = 0x0000003b, -IH_PERF_SEL_RB_OVERFLOW_VF5__VI = 0x0000003c, -IH_PERF_SEL_RB_OVERFLOW_VF6__VI = 0x0000003d, -IH_PERF_SEL_RB_OVERFLOW_VF7__VI = 0x0000003e, -IH_PERF_SEL_RB_OVERFLOW_VF8__VI = 0x0000003f, -IH_PERF_SEL_RB_OVERFLOW_VF9__VI = 0x00000040, -IH_PERF_SEL_RB_OVERFLOW_VF10__VI = 0x00000041, -IH_PERF_SEL_RB_OVERFLOW_VF11__VI = 0x00000042, -IH_PERF_SEL_RB_OVERFLOW_VF12__VI = 0x00000043, -IH_PERF_SEL_RB_OVERFLOW_VF13__VI = 0x00000044, -IH_PERF_SEL_RB_OVERFLOW_VF14__VI = 0x00000045, -IH_PERF_SEL_RB_OVERFLOW_VF15__VI = 0x00000046, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF0__VI = 0x00000047, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF1__VI = 0x00000048, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF2__VI = 0x00000049, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF3__VI = 0x0000004a, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF4__VI = 0x0000004b, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF5__VI = 0x0000004c, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF6__VI = 0x0000004d, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF7__VI = 0x0000004e, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF8__VI = 0x0000004f, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF9__VI = 0x00000050, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF10__VI = 0x00000051, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF11__VI = 0x00000052, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF12__VI = 0x00000053, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF13__VI = 0x00000054, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF14__VI = 0x00000055, -IH_PERF_SEL_RB_WPTR_WRITEBACK_VF15__VI = 0x00000056, -IH_PERF_SEL_RB_WPTR_WRAP_VF0__VI = 0x00000057, -IH_PERF_SEL_RB_WPTR_WRAP_VF1__VI = 0x00000058, -IH_PERF_SEL_RB_WPTR_WRAP_VF2__VI = 0x00000059, -IH_PERF_SEL_RB_WPTR_WRAP_VF3__VI = 0x0000005a, -IH_PERF_SEL_RB_WPTR_WRAP_VF4__VI = 0x0000005b, -IH_PERF_SEL_RB_WPTR_WRAP_VF5__VI = 0x0000005c, -IH_PERF_SEL_RB_WPTR_WRAP_VF6__VI = 0x0000005d, -IH_PERF_SEL_RB_WPTR_WRAP_VF7__VI = 0x0000005e, -IH_PERF_SEL_RB_WPTR_WRAP_VF8__VI = 0x0000005f, -IH_PERF_SEL_RB_WPTR_WRAP_VF9__VI = 0x00000060, -IH_PERF_SEL_RB_WPTR_WRAP_VF10__VI = 0x00000061, -IH_PERF_SEL_RB_WPTR_WRAP_VF11__VI = 0x00000062, -IH_PERF_SEL_RB_WPTR_WRAP_VF12__VI = 0x00000063, -IH_PERF_SEL_RB_WPTR_WRAP_VF13__VI = 0x00000064, -IH_PERF_SEL_RB_WPTR_WRAP_VF14__VI = 0x00000065, -IH_PERF_SEL_RB_WPTR_WRAP_VF15__VI = 0x00000066, -IH_PERF_SEL_RB_RPTR_WRAP_VF0__VI = 0x00000067, -IH_PERF_SEL_RB_RPTR_WRAP_VF1__VI = 0x00000068, -IH_PERF_SEL_RB_RPTR_WRAP_VF2__VI = 0x00000069, -IH_PERF_SEL_RB_RPTR_WRAP_VF3__VI = 0x0000006a, -IH_PERF_SEL_RB_RPTR_WRAP_VF4__VI = 0x0000006b, -IH_PERF_SEL_RB_RPTR_WRAP_VF5__VI = 0x0000006c, -IH_PERF_SEL_RB_RPTR_WRAP_VF6__VI = 0x0000006d, -IH_PERF_SEL_RB_RPTR_WRAP_VF7__VI = 0x0000006e, -IH_PERF_SEL_RB_RPTR_WRAP_VF8__VI = 0x0000006f, -IH_PERF_SEL_RB_RPTR_WRAP_VF9__VI = 0x00000070, -IH_PERF_SEL_RB_RPTR_WRAP_VF10__VI = 0x00000071, -IH_PERF_SEL_RB_RPTR_WRAP_VF11__VI = 0x00000072, -IH_PERF_SEL_RB_RPTR_WRAP_VF12__VI = 0x00000073, -IH_PERF_SEL_RB_RPTR_WRAP_VF13__VI = 0x00000074, -IH_PERF_SEL_RB_RPTR_WRAP_VF14__VI = 0x00000075, -IH_PERF_SEL_RB_RPTR_WRAP_VF15__VI = 0x00000076, -IH_PERF_SEL_BIF_RISING_VF0__VI = 0x00000077, -IH_PERF_SEL_BIF_RISING_VF1__VI = 0x00000078, -IH_PERF_SEL_BIF_RISING_VF2__VI = 0x00000079, -IH_PERF_SEL_BIF_RISING_VF3__VI = 0x0000007a, -IH_PERF_SEL_BIF_RISING_VF4__VI = 0x0000007b, -IH_PERF_SEL_BIF_RISING_VF5__VI = 0x0000007c, -IH_PERF_SEL_BIF_RISING_VF6__VI = 0x0000007d, -IH_PERF_SEL_BIF_RISING_VF7__VI = 0x0000007e, -IH_PERF_SEL_BIF_RISING_VF8__VI = 0x0000007f, -IH_PERF_SEL_BIF_RISING_VF9__VI = 0x00000080, -IH_PERF_SEL_BIF_RISING_VF10__VI = 0x00000081, -IH_PERF_SEL_BIF_RISING_VF11__VI = 0x00000082, -IH_PERF_SEL_BIF_RISING_VF12__VI = 0x00000083, -IH_PERF_SEL_BIF_RISING_VF13__VI = 0x00000084, -IH_PERF_SEL_BIF_RISING_VF14__VI = 0x00000085, -IH_PERF_SEL_BIF_RISING_VF15__VI = 0x00000086, -IH_PERF_SEL_BIF_FALLING_VF0__VI = 0x00000087, -IH_PERF_SEL_BIF_FALLING_VF1__VI = 0x00000088, -IH_PERF_SEL_BIF_FALLING_VF2__VI = 0x00000089, -IH_PERF_SEL_BIF_FALLING_VF3__VI = 0x0000008a, -IH_PERF_SEL_BIF_FALLING_VF4__VI = 0x0000008b, -IH_PERF_SEL_BIF_FALLING_VF5__VI = 0x0000008c, -IH_PERF_SEL_BIF_FALLING_VF6__VI = 0x0000008d, -IH_PERF_SEL_BIF_FALLING_VF7__VI = 0x0000008e, -IH_PERF_SEL_BIF_FALLING_VF8__VI = 0x0000008f, -IH_PERF_SEL_BIF_FALLING_VF9__VI = 0x00000090, -IH_PERF_SEL_BIF_FALLING_VF10__VI = 0x00000091, -IH_PERF_SEL_BIF_FALLING_VF11__VI = 0x00000092, -IH_PERF_SEL_BIF_FALLING_VF12__VI = 0x00000093, -IH_PERF_SEL_BIF_FALLING_VF13__VI = 0x00000094, -IH_PERF_SEL_BIF_FALLING_VF14__VI = 0x00000095, -IH_PERF_SEL_BIF_FALLING_VF15__VI = 0x00000096, -} IH_PERF_SEL; - -typedef enum IMG_DATA_FORMAT { -IMG_DATA_FORMAT_INVALID = 0x00000000, -IMG_DATA_FORMAT_8 = 0x00000001, -IMG_DATA_FORMAT_16 = 0x00000002, -IMG_DATA_FORMAT_8_8 = 0x00000003, -IMG_DATA_FORMAT_32 = 0x00000004, -IMG_DATA_FORMAT_16_16 = 0x00000005, -IMG_DATA_FORMAT_10_11_11 = 0x00000006, -IMG_DATA_FORMAT_11_11_10 = 0x00000007, -IMG_DATA_FORMAT_10_10_10_2 = 0x00000008, -IMG_DATA_FORMAT_2_10_10_10 = 0x00000009, -IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a, -IMG_DATA_FORMAT_32_32 = 0x0000000b, -IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c, -IMG_DATA_FORMAT_32_32_32 = 0x0000000d, -IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e, -IMG_DATA_FORMAT_RESERVED_15 = 0x0000000f, -IMG_DATA_FORMAT_5_6_5 = 0x00000010, -IMG_DATA_FORMAT_1_5_5_5 = 0x00000011, -IMG_DATA_FORMAT_5_5_5_1 = 0x00000012, -IMG_DATA_FORMAT_4_4_4_4 = 0x00000013, -IMG_DATA_FORMAT_8_24 = 0x00000014, -IMG_DATA_FORMAT_24_8 = 0x00000015, -IMG_DATA_FORMAT_X24_8_32 = 0x00000016, -IMG_DATA_FORMAT_RESERVED_23 = 0x00000017, -IMG_DATA_FORMAT_RESERVED_24 = 0x00000018, -IMG_DATA_FORMAT_ETC2_RGB__VI = 0x00000018, -IMG_DATA_FORMAT_RESERVED_25 = 0x00000019, -IMG_DATA_FORMAT_ETC2_RGBA__VI = 0x00000019, -IMG_DATA_FORMAT_RESERVED_26 = 0x0000001a, -IMG_DATA_FORMAT_ETC2_R__VI = 0x0000001a, -IMG_DATA_FORMAT_RESERVED_27 = 0x0000001b, -IMG_DATA_FORMAT_ETC2_RG__VI = 0x0000001b, -IMG_DATA_FORMAT_RESERVED_28 = 0x0000001c, -IMG_DATA_FORMAT_ETC2_RGBA1__VI = 0x0000001c, -IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d, -IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e, -IMG_DATA_FORMAT_RESERVED_31 = 0x0000001f, -IMG_DATA_FORMAT_GB_GR = 0x00000020, -IMG_DATA_FORMAT_BG_RG = 0x00000021, -IMG_DATA_FORMAT_5_9_9_9 = 0x00000022, -IMG_DATA_FORMAT_BC1 = 0x00000023, -IMG_DATA_FORMAT_BC2 = 0x00000024, -IMG_DATA_FORMAT_BC3 = 0x00000025, -IMG_DATA_FORMAT_BC4 = 0x00000026, -IMG_DATA_FORMAT_BC5 = 0x00000027, -IMG_DATA_FORMAT_BC6 = 0x00000028, -IMG_DATA_FORMAT_BC7 = 0x00000029, -IMG_DATA_FORMAT_RESERVED_42 = 0x0000002a, -IMG_DATA_FORMAT_RESERVED_43 = 0x0000002b, -IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x0000002c, -IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x0000002d, -IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x0000002e, -IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x0000002f, -IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x00000030, -IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x00000031, -IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x00000032, -IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x00000033, -IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x00000034, -IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x00000035, -IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x00000036, -IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x00000037, -IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x00000038, -IMG_DATA_FORMAT_4_4 = 0x00000039, -IMG_DATA_FORMAT_6_5_5 = 0x0000003a, -IMG_DATA_FORMAT_1 = 0x0000003b, -IMG_DATA_FORMAT_1_REVERSED = 0x0000003c, -IMG_DATA_FORMAT_32_AS_8 = 0x0000003d, -IMG_DATA_FORMAT_32_AS_8_8 = 0x0000003e, -IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f, -} IMG_DATA_FORMAT; - -typedef enum IMG_NUM_FORMAT { -IMG_NUM_FORMAT_UNORM = 0x00000000, -IMG_NUM_FORMAT_SNORM = 0x00000001, -IMG_NUM_FORMAT_USCALED = 0x00000002, -IMG_NUM_FORMAT_SSCALED = 0x00000003, -IMG_NUM_FORMAT_UINT = 0x00000004, -IMG_NUM_FORMAT_SINT = 0x00000005, -IMG_NUM_FORMAT_SNORM_OGL__SI__CI = 0x00000006, -IMG_NUM_FORMAT_RESERVED_6__VI = 0x00000006, -IMG_NUM_FORMAT_FLOAT = 0x00000007, -IMG_NUM_FORMAT_RESERVED_8 = 0x00000008, -IMG_NUM_FORMAT_SRGB = 0x00000009, -IMG_NUM_FORMAT_UBNORM__SI__CI = 0x0000000a, -IMG_NUM_FORMAT_RESERVED_10__VI = 0x0000000a, -IMG_NUM_FORMAT_UBNORM_OGL__SI__CI = 0x0000000b, -IMG_NUM_FORMAT_RESERVED_11__VI = 0x0000000b, -IMG_NUM_FORMAT_UBINT__SI__CI = 0x0000000c, -IMG_NUM_FORMAT_RESERVED_12__VI = 0x0000000c, -IMG_NUM_FORMAT_UBSCALED__SI__CI = 0x0000000d, -IMG_NUM_FORMAT_RESERVED_13__VI = 0x0000000d, -IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e, -IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f, -} IMG_NUM_FORMAT; - -typedef enum MacroTileAspect { -ADDR_SURF_MACRO_ASPECT_1 = 0x00000000, -ADDR_SURF_MACRO_ASPECT_2 = 0x00000001, -ADDR_SURF_MACRO_ASPECT_4 = 0x00000002, -ADDR_SURF_MACRO_ASPECT_8 = 0x00000003, -} MacroTileAspect; - -typedef enum MicroTileMode { -ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000, -ADDR_SURF_THIN_MICRO_TILING = 0x00000001, -ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002, -ADDR_SURF_THICK_MICRO_TILING__SI = 0x00000003, -ADDR_SURF_ROTATED_MICRO_TILING__CI__VI = 0x00000003, -ADDR_SURF_THICK_MICRO_TILING__CI__VI = 0x00000004, -} MicroTileMode; - -typedef enum MultiGPUTileSize { -ADDR_CONFIG_GPU_TILE_16 = 0x00000000, -ADDR_CONFIG_GPU_TILE_32 = 0x00000001, -ADDR_CONFIG_GPU_TILE_64 = 0x00000002, -ADDR_CONFIG_GPU_TILE_128 = 0x00000003, -} MultiGPUTileSize; - -typedef enum NonDispTilingOrder { -ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000, -ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001, -} NonDispTilingOrder; - -typedef enum NumBanks { -ADDR_SURF_2_BANK = 0x00000000, -ADDR_SURF_4_BANK = 0x00000001, -ADDR_SURF_8_BANK = 0x00000002, -ADDR_SURF_16_BANK = 0x00000003, -} NumBanks; - -typedef enum NumGPUs { -ADDR_CONFIG_1_GPU = 0x00000000, -ADDR_CONFIG_2_GPU = 0x00000001, -ADDR_CONFIG_4_GPU = 0x00000002, -} NumGPUs; - -typedef enum NumLowerPipes { -ADDR_CONFIG_1_LOWER_PIPES = 0x00000000, -ADDR_CONFIG_2_LOWER_PIPES = 0x00000001, -} NumLowerPipes; - -typedef enum NumPipes { -ADDR_CONFIG_1_PIPE = 0x00000000, -ADDR_CONFIG_2_PIPE = 0x00000001, -ADDR_CONFIG_4_PIPE = 0x00000002, -ADDR_CONFIG_8_PIPE = 0x00000003, -} NumPipes; - -typedef enum NumShaderEngines { -ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, -ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, -} NumShaderEngines; - -typedef enum PERFMON_COUNTER_MODE { -PERFMON_COUNTER_MODE_ACCUM = 0x00000000, -PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001, -PERFMON_COUNTER_MODE_MAX = 0x00000002, -PERFMON_COUNTER_MODE_DIRTY = 0x00000003, -PERFMON_COUNTER_MODE_SAMPLE = 0x00000004, -PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005, -PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006, -PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007, -PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008, -PERFMON_COUNTER_MODE_INACTIVE_CYCLES__CI__VI = 0x00000009, -PERFMON_COUNTER_MODE_RESERVED = 0x0000000f, -} PERFMON_COUNTER_MODE; - -typedef enum PERFMON_SPM_MODE { -PERFMON_SPM_MODE_OFF = 0x00000000, -PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001, -PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002, -PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003, -PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004, -PERFMON_SPM_MODE_RESERVED_5 = 0x00000005, -PERFMON_SPM_MODE_RESERVED_6 = 0x00000006, -PERFMON_SPM_MODE_RESERVED_7 = 0x00000007, -PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008, -PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009, -PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a, -} PERFMON_SPM_MODE; - -typedef enum PerfCounter_Vals { -DB_PERF_SEL_SC_DB_tile_sends = 0x00000000, -DB_PERF_SEL_SC_DB_tile_busy = 0x00000001, -DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002, -DB_PERF_SEL_SC_DB_tile_events = 0x00000003, -DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004, -DB_PERF_SEL_SC_DB_tile_covered = 0x00000005, -DB_PERF_SEL_hiz_tc_read_starved = 0x00000006, -DB_PERF_SEL_hiz_tc_write_stall = 0x00000007, -DB_PERF_SEL_hiz_qtiles_culled = 0x00000008, -DB_PERF_SEL_his_qtiles_culled = 0x00000009, -DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a, -DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b, -DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c, -DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d, -DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e, -DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f, -DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010, -DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011, -DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012, -DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013, -DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014, -DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015, -DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016, -DB_PERF_SEL_SC_DB_quad_sends = 0x00000017, -DB_PERF_SEL_SC_DB_quad_busy = 0x00000018, -DB_PERF_SEL_SC_DB_quad_squads = 0x00000019, -DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a, -DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b, -DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c, -DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d, -DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e, -DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f, -DB_PERF_SEL_DB_SC_quad_tiles__CI__VI = 0x00000020, -DB_PERF_SEL_DB_SC_quad_tiles__SI = 0x00000021, -DB_PERF_SEL_DB_SC_quad_lit_quad__CI__VI = 0x00000021, -DB_PERF_SEL_DB_SC_quad_lit_quad__SI = 0x00000022, -DB_PERF_SEL_DB_CB_tile_sends__CI__VI = 0x00000022, -DB_PERF_SEL_DB_CB_tile_sends__SI = 0x00000023, -DB_PERF_SEL_DB_CB_tile_busy__CI__VI = 0x00000023, -DB_PERF_SEL_DB_CB_tile_busy__SI = 0x00000024, -DB_PERF_SEL_DB_CB_tile_stalls__CI__VI = 0x00000024, -DB_PERF_SEL_DB_CB_tile_stalls__SI = 0x00000025, -DB_PERF_SEL_SX_DB_quad_sends__CI__VI = 0x00000025, -DB_PERF_SEL_SX_DB_quad_sends__SI = 0x00000026, -DB_PERF_SEL_SX_DB_quad_busy__CI__VI = 0x00000026, -DB_PERF_SEL_SX_DB_quad_busy__SI = 0x00000027, -DB_PERF_SEL_SX_DB_quad_stalls__CI__VI = 0x00000027, -DB_PERF_SEL_SX_DB_quad_stalls__SI = 0x00000028, -DB_PERF_SEL_SX_DB_quad_quads__CI__VI = 0x00000028, -DB_PERF_SEL_SX_DB_quad_quads__SI = 0x00000029, -DB_PERF_SEL_SX_DB_quad_pixels__CI__VI = 0x00000029, -DB_PERF_SEL_SX_DB_quad_pixels__SI = 0x0000002a, -DB_PERF_SEL_SX_DB_quad_exports__CI__VI = 0x0000002a, -DB_PERF_SEL_SX_DB_quad_exports__SI = 0x0000002b, -DB_PERF_SEL_SH_quads_outstanding_sum__CI__VI = 0x0000002b, -DB_PERF_SEL_SH_quads_outstanding_sum__SI = 0x0000002c, -DB_PERF_SEL_DB_CB_lquad_sends__CI__VI = 0x0000002c, -DB_PERF_SEL_DB_CB_lquad_sends__SI = 0x0000002d, -DB_PERF_SEL_DB_CB_lquad_busy__CI__VI = 0x0000002d, -DB_PERF_SEL_DB_CB_lquad_busy__SI = 0x0000002e, -DB_PERF_SEL_DB_CB_lquad_stalls__CI__VI = 0x0000002e, -DB_PERF_SEL_DB_CB_lquad_stalls__SI = 0x0000002f, -DB_PERF_SEL_DB_CB_lquad_quads__CI__VI = 0x0000002f, -DB_PERF_SEL_DB_CB_lquad_quads__SI = 0x00000030, -DB_PERF_SEL_tile_rd_sends__CI__VI = 0x00000030, -DB_PERF_SEL_tile_rd_sends__SI = 0x00000031, -DB_PERF_SEL_mi_tile_rd_outstanding_sum__CI__VI = 0x00000031, -DB_PERF_SEL_mi_tile_rd_outstanding_sum__SI = 0x00000032, -DB_PERF_SEL_quad_rd_sends__CI__VI = 0x00000032, -DB_PERF_SEL_quad_rd_sends__SI = 0x00000033, -DB_PERF_SEL_quad_rd_busy__CI__VI = 0x00000033, -DB_PERF_SEL_quad_rd_busy__SI = 0x00000034, -DB_PERF_SEL_quad_rd_mi_stall__CI__VI = 0x00000034, -DB_PERF_SEL_quad_rd_mi_stall__SI = 0x00000035, -DB_PERF_SEL_quad_rd_rw_collision__CI__VI = 0x00000035, -DB_PERF_SEL_quad_rd_rw_collision__SI = 0x00000036, -DB_PERF_SEL_quad_rd_tag_stall__CI__VI = 0x00000036, -DB_PERF_SEL_quad_rd_tag_stall__SI = 0x00000037, -DB_PERF_SEL_quad_rd_32byte_reqs__CI__VI = 0x00000037, -DB_PERF_SEL_quad_rd_32byte_reqs__SI = 0x00000038, -DB_PERF_SEL_quad_rd_panic__CI__VI = 0x00000038, -DB_PERF_SEL_quad_rd_panic__SI = 0x00000039, -DB_PERF_SEL_mi_quad_rd_outstanding_sum__CI__VI = 0x00000039, -DB_PERF_SEL_mi_quad_rd_outstanding_sum__SI = 0x0000003a, -DB_PERF_SEL_quad_rdret_sends__CI__VI = 0x0000003a, -DB_PERF_SEL_quad_rdret_sends__SI = 0x0000003b, -DB_PERF_SEL_quad_rdret_busy__CI__VI = 0x0000003b, -DB_PERF_SEL_quad_rdret_busy__SI = 0x0000003c, -DB_PERF_SEL_tile_wr_sends__CI__VI = 0x0000003c, -DB_PERF_SEL_tile_wr_sends__SI = 0x0000003d, -DB_PERF_SEL_tile_wr_acks__CI__VI = 0x0000003d, -DB_PERF_SEL_tile_wr_acks__SI = 0x0000003e, -DB_PERF_SEL_mi_tile_wr_outstanding_sum__CI__VI = 0x0000003e, -DB_PERF_SEL_mi_tile_wr_outstanding_sum__SI = 0x0000003f, -DB_PERF_SEL_quad_wr_sends__CI__VI = 0x0000003f, -DB_PERF_SEL_quad_wr_sends__SI = 0x00000040, -DB_PERF_SEL_quad_wr_busy__CI__VI = 0x00000040, -DB_PERF_SEL_quad_wr_busy__SI = 0x00000041, -DB_PERF_SEL_quad_wr_mi_stall__CI__VI = 0x00000041, -DB_PERF_SEL_quad_wr_mi_stall__SI = 0x00000042, -DB_PERF_SEL_quad_wr_coherency_stall__CI__VI = 0x00000042, -DB_PERF_SEL_quad_wr_coherency_stall__SI = 0x00000043, -DB_PERF_SEL_quad_wr_acks__CI__VI = 0x00000043, -DB_PERF_SEL_quad_wr_acks__SI = 0x00000044, -DB_PERF_SEL_mi_quad_wr_outstanding_sum__CI__VI = 0x00000044, -DB_PERF_SEL_mi_quad_wr_outstanding_sum__SI = 0x00000045, -DB_PERF_SEL_Tile_Cache_misses__CI__VI = 0x00000045, -DB_PERF_SEL_Tile_Cache_misses__SI = 0x00000046, -DB_PERF_SEL_Tile_Cache_hits__CI__VI = 0x00000046, -DB_PERF_SEL_Tile_Cache_hits__SI = 0x00000047, -DB_PERF_SEL_Tile_Cache_flushes__CI__VI = 0x00000047, -DB_PERF_SEL_Tile_Cache_flushes__SI = 0x00000048, -DB_PERF_SEL_Tile_Cache_surface_stall__CI__VI = 0x00000048, -DB_PERF_SEL_Tile_Cache_surface_stall__SI = 0x00000049, -DB_PERF_SEL_Tile_Cache_starves__CI__VI = 0x00000049, -DB_PERF_SEL_Tile_Cache_starves__SI = 0x0000004a, -DB_PERF_SEL_Tile_Cache_mem_return_starve__CI__VI = 0x0000004a, -DB_PERF_SEL_Tile_Cache_mem_return_starve__SI = 0x0000004b, -DB_PERF_SEL_tcp_dispatcher_reads__CI__VI = 0x0000004b, -DB_PERF_SEL_tcp_dispatcher_reads__SI = 0x0000004c, -DB_PERF_SEL_tcp_prefetcher_reads__CI__VI = 0x0000004c, -DB_PERF_SEL_tcp_prefetcher_reads__SI = 0x0000004d, -DB_PERF_SEL_tcp_preloader_reads__CI__VI = 0x0000004d, -DB_PERF_SEL_tcp_preloader_reads__SI = 0x0000004e, -DB_PERF_SEL_tcp_dispatcher_flushes__CI__VI = 0x0000004e, -DB_PERF_SEL_tcp_dispatcher_flushes__SI = 0x0000004f, -DB_PERF_SEL_tcp_prefetcher_flushes__CI__VI = 0x0000004f, -DB_PERF_SEL_tcp_prefetcher_flushes__SI = 0x00000050, -DB_PERF_SEL_tcp_preloader_flushes__CI__VI = 0x00000050, -DB_PERF_SEL_tcp_preloader_flushes__SI = 0x00000051, -DB_PERF_SEL_Depth_Tile_Cache_sends__CI__VI = 0x00000051, -DB_PERF_SEL_Depth_Tile_Cache_sends__SI = 0x00000052, -DB_PERF_SEL_Depth_Tile_Cache_busy__CI__VI = 0x00000052, -DB_PERF_SEL_Depth_Tile_Cache_busy__SI = 0x00000053, -DB_PERF_SEL_Depth_Tile_Cache_starves__CI__VI = 0x00000053, -DB_PERF_SEL_Depth_Tile_Cache_starves__SI = 0x00000054, -DB_PERF_SEL_Depth_Tile_Cache_dtile_locked__CI__VI = 0x00000054, -DB_PERF_SEL_Depth_Tile_Cache_dtile_locked__SI = 0x00000055, -DB_PERF_SEL_Depth_Tile_Cache_alloc_stall__CI__VI = 0x00000055, -DB_PERF_SEL_Depth_Tile_Cache_alloc_stall__SI = 0x00000056, -DB_PERF_SEL_Depth_Tile_Cache_misses__CI__VI = 0x00000056, -DB_PERF_SEL_Depth_Tile_Cache_misses__SI = 0x00000057, -DB_PERF_SEL_Depth_Tile_Cache_hits__CI__VI = 0x00000057, -DB_PERF_SEL_Depth_Tile_Cache_hits__SI = 0x00000058, -DB_PERF_SEL_Depth_Tile_Cache_flushes__CI__VI = 0x00000058, -DB_PERF_SEL_Depth_Tile_Cache_flushes__SI = 0x00000059, -DB_PERF_SEL_Depth_Tile_Cache_noop_tile__CI__VI = 0x00000059, -DB_PERF_SEL_Depth_Tile_Cache_noop_tile__SI = 0x0000005a, -DB_PERF_SEL_Depth_Tile_Cache_detailed_noop__CI__VI = 0x0000005a, -DB_PERF_SEL_Depth_Tile_Cache_detailed_noop__SI = 0x0000005b, -DB_PERF_SEL_Depth_Tile_Cache_event__CI__VI = 0x0000005b, -DB_PERF_SEL_Depth_Tile_Cache_event__SI = 0x0000005c, -DB_PERF_SEL_Depth_Tile_Cache_tile_frees__CI__VI = 0x0000005c, -DB_PERF_SEL_Depth_Tile_Cache_tile_frees__SI = 0x0000005d, -DB_PERF_SEL_Depth_Tile_Cache_data_frees__CI__VI = 0x0000005d, -DB_PERF_SEL_Depth_Tile_Cache_data_frees__SI = 0x0000005e, -DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve__CI__VI = 0x0000005e, -DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve__SI = 0x0000005f, -DB_PERF_SEL_Stencil_Cache_misses__CI__VI = 0x0000005f, -DB_PERF_SEL_Stencil_Cache_misses__SI = 0x00000060, -DB_PERF_SEL_Stencil_Cache_hits__CI__VI = 0x00000060, -DB_PERF_SEL_Stencil_Cache_hits__SI = 0x00000061, -DB_PERF_SEL_Stencil_Cache_flushes__CI__VI = 0x00000061, -DB_PERF_SEL_Stencil_Cache_flushes__SI = 0x00000062, -DB_PERF_SEL_Stencil_Cache_starves__CI__VI = 0x00000062, -DB_PERF_SEL_Stencil_Cache_starves__SI = 0x00000063, -DB_PERF_SEL_Stencil_Cache_frees__CI__VI = 0x00000063, -DB_PERF_SEL_Stencil_Cache_frees__SI = 0x00000064, -DB_PERF_SEL_Z_Cache_separate_Z_misses__CI__VI = 0x00000064, -DB_PERF_SEL_Z_Cache_separate_Z_misses__SI = 0x00000065, -DB_PERF_SEL_Z_Cache_separate_Z_hits__CI__VI = 0x00000065, -DB_PERF_SEL_Z_Cache_separate_Z_hits__SI = 0x00000066, -DB_PERF_SEL_Z_Cache_separate_Z_flushes__CI__VI = 0x00000066, -DB_PERF_SEL_Z_Cache_separate_Z_flushes__SI = 0x00000067, -DB_PERF_SEL_Z_Cache_separate_Z_starves__CI__VI = 0x00000067, -DB_PERF_SEL_Z_Cache_separate_Z_starves__SI = 0x00000068, -DB_PERF_SEL_Z_Cache_pmask_misses__CI__VI = 0x00000068, -DB_PERF_SEL_Z_Cache_pmask_misses__SI = 0x00000069, -DB_PERF_SEL_Z_Cache_pmask_hits__CI__VI = 0x00000069, -DB_PERF_SEL_Z_Cache_pmask_hits__SI = 0x0000006a, -DB_PERF_SEL_Z_Cache_pmask_flushes__CI__VI = 0x0000006a, -DB_PERF_SEL_Z_Cache_pmask_flushes__SI = 0x0000006b, -DB_PERF_SEL_Z_Cache_pmask_starves__CI__VI = 0x0000006b, -DB_PERF_SEL_Z_Cache_pmask_starves__SI = 0x0000006c, -DB_PERF_SEL_Z_Cache_frees__CI__VI = 0x0000006c, -DB_PERF_SEL_Z_Cache_frees__SI = 0x0000006d, -DB_PERF_SEL_Plane_Cache_misses__CI__VI = 0x0000006d, -DB_PERF_SEL_Plane_Cache_misses__SI = 0x0000006e, -DB_PERF_SEL_Plane_Cache_hits__CI__VI = 0x0000006e, -DB_PERF_SEL_Plane_Cache_hits__SI = 0x0000006f, -DB_PERF_SEL_Plane_Cache_flushes__CI__VI = 0x0000006f, -DB_PERF_SEL_Plane_Cache_flushes__SI = 0x00000070, -DB_PERF_SEL_Plane_Cache_starves__CI__VI = 0x00000070, -DB_PERF_SEL_Plane_Cache_starves__SI = 0x00000071, -DB_PERF_SEL_Plane_Cache_frees__CI__VI = 0x00000071, -DB_PERF_SEL_Plane_Cache_frees__SI = 0x00000072, -DB_PERF_SEL_flush_expanded_stencil__CI__VI = 0x00000072, -DB_PERF_SEL_flush_expanded_stencil__SI = 0x00000073, -DB_PERF_SEL_flush_compressed_stencil__CI__VI = 0x00000073, -DB_PERF_SEL_flush_compressed_stencil__SI = 0x00000074, -DB_PERF_SEL_flush_single_stencil__CI__VI = 0x00000074, -DB_PERF_SEL_flush_single_stencil__SI = 0x00000075, -DB_PERF_SEL_planes_flushed__CI__VI = 0x00000075, -DB_PERF_SEL_planes_flushed__SI = 0x00000076, -DB_PERF_SEL_flush_1plane__CI__VI = 0x00000076, -DB_PERF_SEL_flush_1plane__SI = 0x00000077, -DB_PERF_SEL_flush_2plane__CI__VI = 0x00000077, -DB_PERF_SEL_flush_2plane__SI = 0x00000078, -DB_PERF_SEL_flush_3plane__CI__VI = 0x00000078, -DB_PERF_SEL_flush_3plane__SI = 0x00000079, -DB_PERF_SEL_flush_4plane__CI__VI = 0x00000079, -DB_PERF_SEL_flush_4plane__SI = 0x0000007a, -DB_PERF_SEL_flush_5plane__CI__VI = 0x0000007a, -DB_PERF_SEL_flush_5plane__SI = 0x0000007b, -DB_PERF_SEL_flush_6plane__CI__VI = 0x0000007b, -DB_PERF_SEL_flush_6plane__SI = 0x0000007c, -DB_PERF_SEL_flush_7plane__CI__VI = 0x0000007c, -DB_PERF_SEL_flush_7plane__SI = 0x0000007d, -DB_PERF_SEL_flush_8plane__CI__VI = 0x0000007d, -DB_PERF_SEL_flush_8plane__SI = 0x0000007e, -DB_PERF_SEL_flush_9plane__CI__VI = 0x0000007e, -DB_PERF_SEL_flush_9plane__SI = 0x0000007f, -DB_PERF_SEL_flush_10plane__CI__VI = 0x0000007f, -DB_PERF_SEL_flush_10plane__SI = 0x00000080, -DB_PERF_SEL_flush_11plane__CI__VI = 0x00000080, -DB_PERF_SEL_flush_11plane__SI = 0x00000081, -DB_PERF_SEL_flush_12plane__CI__VI = 0x00000081, -DB_PERF_SEL_flush_12plane__SI = 0x00000082, -DB_PERF_SEL_flush_13plane__CI__VI = 0x00000082, -DB_PERF_SEL_flush_13plane__SI = 0x00000083, -DB_PERF_SEL_flush_14plane__CI__VI = 0x00000083, -DB_PERF_SEL_flush_14plane__SI = 0x00000084, -DB_PERF_SEL_flush_15plane__CI__VI = 0x00000084, -DB_PERF_SEL_flush_15plane__SI = 0x00000085, -DB_PERF_SEL_flush_16plane__CI__VI = 0x00000085, -DB_PERF_SEL_flush_16plane__SI = 0x00000086, -DB_PERF_SEL_flush_expanded_z__CI__VI = 0x00000086, -DB_PERF_SEL_flush_expanded_z__SI = 0x00000087, -DB_PERF_SEL_earlyZ_waiting_for_postZ_done__CI__VI = 0x00000087, -DB_PERF_SEL_earlyZ_waiting_for_postZ_done__SI = 0x00000088, -DB_PERF_SEL_reZ_waiting_for_postZ_done__CI__VI = 0x00000088, -DB_PERF_SEL_reZ_waiting_for_postZ_done__SI = 0x00000089, -DB_PERF_SEL_dk_tile_sends__CI__VI = 0x00000089, -DB_PERF_SEL_dk_tile_sends__SI = 0x0000008a, -DB_PERF_SEL_dk_tile_busy__CI__VI = 0x0000008a, -DB_PERF_SEL_dk_tile_busy__SI = 0x0000008b, -DB_PERF_SEL_dk_tile_quad_starves__CI__VI = 0x0000008b, -DB_PERF_SEL_dk_tile_quad_starves__SI = 0x0000008c, -DB_PERF_SEL_dk_tile_stalls__CI__VI = 0x0000008c, -DB_PERF_SEL_dk_tile_stalls__SI = 0x0000008d, -DB_PERF_SEL_dk_squad_sends__CI__VI = 0x0000008d, -DB_PERF_SEL_dk_squad_sends__SI = 0x0000008e, -DB_PERF_SEL_dk_squad_busy__CI__VI = 0x0000008e, -DB_PERF_SEL_dk_squad_busy__SI = 0x0000008f, -DB_PERF_SEL_dk_squad_stalls__CI__VI = 0x0000008f, -DB_PERF_SEL_dk_squad_stalls__SI = 0x00000090, -DB_PERF_SEL_Op_Pipe_Busy__CI__VI = 0x00000090, -DB_PERF_SEL_Op_Pipe_Busy__SI = 0x00000091, -DB_PERF_SEL_Op_Pipe_MC_Read_stall__CI__VI = 0x00000091, -DB_PERF_SEL_Op_Pipe_MC_Read_stall__SI = 0x00000092, -DB_PERF_SEL_qc_busy__CI__VI = 0x00000092, -DB_PERF_SEL_qc_busy__SI = 0x00000093, -DB_PERF_SEL_qc_xfc__CI__VI = 0x00000093, -DB_PERF_SEL_qc_xfc__SI = 0x00000094, -DB_PERF_SEL_qc_conflicts__CI__VI = 0x00000094, -DB_PERF_SEL_qc_conflicts__SI = 0x00000095, -DB_PERF_SEL_qc_full_stall__CI__VI = 0x00000095, -DB_PERF_SEL_qc_full_stall__SI = 0x00000096, -DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ__CI__VI = 0x00000096, -DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ__SI = 0x00000097, -DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ__CI__VI = 0x00000097, -DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ__SI = 0x00000098, -DB_PERF_SEL_tsc_insert_summarize_stall__CI__VI = 0x00000098, -DB_PERF_SEL_tsc_insert_summarize_stall__SI = 0x00000099, -DB_PERF_SEL_tl_busy__CI__VI = 0x00000099, -DB_PERF_SEL_tl_busy__SI = 0x0000009a, -DB_PERF_SEL_tl_dtc_read_starved__CI__VI = 0x0000009a, -DB_PERF_SEL_tl_dtc_read_starved__SI = 0x0000009b, -DB_PERF_SEL_tl_z_fetch_stall__CI__VI = 0x0000009b, -DB_PERF_SEL_tl_z_fetch_stall__SI = 0x0000009c, -DB_PERF_SEL_tl_stencil_stall__CI__VI = 0x0000009c, -DB_PERF_SEL_tl_stencil_stall__SI = 0x0000009d, -DB_PERF_SEL_tl_z_decompress_stall__CI__VI = 0x0000009d, -DB_PERF_SEL_tl_z_decompress_stall__SI = 0x0000009e, -DB_PERF_SEL_tl_stencil_locked_stall__CI__VI = 0x0000009e, -DB_PERF_SEL_tl_stencil_locked_stall__SI = 0x0000009f, -DB_PERF_SEL_tl_events__CI__VI = 0x0000009f, -DB_PERF_SEL_tl_events__SI = 0x000000a0, -DB_PERF_SEL_tl_summarize_squads__CI__VI = 0x000000a0, -DB_PERF_SEL_tl_summarize_squads__SI = 0x000000a1, -DB_PERF_SEL_tl_flush_expand_squads__CI__VI = 0x000000a1, -DB_PERF_SEL_tl_flush_expand_squads__SI = 0x000000a2, -DB_PERF_SEL_tl_expand_squads__CI__VI = 0x000000a2, -DB_PERF_SEL_tl_expand_squads__SI = 0x000000a3, -DB_PERF_SEL_tl_preZ_squads__CI__VI = 0x000000a3, -DB_PERF_SEL_tl_preZ_squads__SI = 0x000000a4, -DB_PERF_SEL_tl_postZ_squads__CI__VI = 0x000000a4, -DB_PERF_SEL_tl_postZ_squads__SI = 0x000000a5, -DB_PERF_SEL_tl_preZ_noop_squads__CI__VI = 0x000000a5, -DB_PERF_SEL_tl_preZ_noop_squads__SI = 0x000000a6, -DB_PERF_SEL_tl_postZ_noop_squads__CI__VI = 0x000000a6, -DB_PERF_SEL_tl_postZ_noop_squads__SI = 0x000000a7, -DB_PERF_SEL_tl_tile_ops__CI__VI = 0x000000a7, -DB_PERF_SEL_tl_in_xfc__CI__VI = 0x000000a8, -DB_PERF_SEL_tl_tile_ops__SI = 0x000000a9, -DB_PERF_SEL_tl_in_single_stencil_expand_stall__CI__VI = 0x000000a9, -DB_PERF_SEL_tl_in_xfc__SI = 0x000000aa, -DB_PERF_SEL_tl_in_fast_z_stall__CI__VI = 0x000000aa, -DB_PERF_SEL_tl_in_single_stencil_expand_stall__SI = 0x000000ab, -DB_PERF_SEL_tl_out_xfc__CI__VI = 0x000000ab, -DB_PERF_SEL_tl_out_squads__CI__VI = 0x000000ac, -DB_PERF_SEL_tl_in_fast_z_stall__SI = 0x000000ad, -DB_PERF_SEL_zf_plane_multicycle__CI__VI = 0x000000ad, -DB_PERF_SEL_tl_out_xfc__SI = 0x000000ae, -DB_PERF_SEL_PostZ_Samples_passing_Z__CI__VI = 0x000000ae, -DB_PERF_SEL_tl_out_squads__SI = 0x000000af, -DB_PERF_SEL_PostZ_Samples_failing_Z__CI__VI = 0x000000af, -DB_PERF_SEL_zf_plane_multicycle__SI = 0x000000b0, -DB_PERF_SEL_PostZ_Samples_failing_S__CI__VI = 0x000000b0, -DB_PERF_SEL_PostZ_Samples_passing_Z__SI = 0x000000b1, -DB_PERF_SEL_PreZ_Samples_passing_Z__CI__VI = 0x000000b1, -DB_PERF_SEL_PostZ_Samples_failing_Z__SI = 0x000000b2, -DB_PERF_SEL_PreZ_Samples_failing_Z__CI__VI = 0x000000b2, -DB_PERF_SEL_PostZ_Samples_failing_S__SI = 0x000000b3, -DB_PERF_SEL_PreZ_Samples_failing_S__CI__VI = 0x000000b3, -DB_PERF_SEL_PreZ_Samples_passing_Z__SI = 0x000000b4, -DB_PERF_SEL_ts_tc_update_stall__CI__VI = 0x000000b4, -DB_PERF_SEL_PreZ_Samples_failing_Z__SI = 0x000000b5, -DB_PERF_SEL_sc_kick_start__CI__VI = 0x000000b5, -DB_PERF_SEL_PreZ_Samples_failing_S__SI = 0x000000b6, -DB_PERF_SEL_sc_kick_end__CI__VI = 0x000000b6, -DB_PERF_SEL_ts_tc_update_stall__SI = 0x000000b7, -DB_PERF_SEL_clock_reg_active__CI__VI = 0x000000b7, -DB_PERF_SEL_sc_kick_start__SI = 0x000000b8, -DB_PERF_SEL_clock_main_active__CI__VI = 0x000000b8, -DB_PERF_SEL_sc_kick_end__SI = 0x000000b9, -DB_PERF_SEL_clock_mem_export_active__CI__VI = 0x000000b9, -DB_PERF_SEL_clock_reg_active__SI = 0x000000ba, -DB_PERF_SEL_esr_ps_out_busy__CI__VI = 0x000000ba, -DB_PERF_SEL_clock_main_active__SI = 0x000000bb, -DB_PERF_SEL_esr_ps_lqf_busy__CI__VI = 0x000000bb, -DB_PERF_SEL_clock_mem_export_active__SI = 0x000000bc, -DB_PERF_SEL_esr_ps_lqf_stall__CI__VI = 0x000000bc, -DB_PERF_SEL_esr_ps_out_busy__SI = 0x000000bd, -DB_PERF_SEL_etr_out_send__CI__VI = 0x000000bd, -DB_PERF_SEL_esr_ps_lqf_busy__SI = 0x000000be, -DB_PERF_SEL_etr_out_busy__CI__VI = 0x000000be, -DB_PERF_SEL_esr_ps_lqf_stall__SI = 0x000000bf, -DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall__CI__VI = 0x000000bf, -DB_PERF_SEL_etr_out_send__SI = 0x000000c0, -DB_PERF_SEL_etr_out_cb_tile_stall__CI__VI = 0x000000c0, -DB_PERF_SEL_etr_out_busy__SI = 0x000000c1, -DB_PERF_SEL_etr_out_esr_stall__CI__VI = 0x000000c1, -DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall__SI = 0x000000c2, -DB_PERF_SEL_esr_ps_sqq_busy__CI__VI = 0x000000c2, -DB_PERF_SEL_etr_out_cb_tile_stall__SI = 0x000000c3, -DB_PERF_SEL_esr_ps_sqq_stall__CI__VI = 0x000000c3, -DB_PERF_SEL_etr_out_esr_stall__SI = 0x000000c4, -DB_PERF_SEL_esr_eot_fwd_busy__CI__VI = 0x000000c4, -DB_PERF_SEL_esr_ps_sqq_busy__SI = 0x000000c5, -DB_PERF_SEL_esr_eot_fwd_holding_squad__CI__VI = 0x000000c5, -DB_PERF_SEL_esr_ps_sqq_stall__SI = 0x000000c6, -DB_PERF_SEL_esr_eot_fwd_forward__CI__VI = 0x000000c6, -DB_PERF_SEL_esr_eot_fwd_busy__SI = 0x000000c7, -DB_PERF_SEL_esr_sqq_zi_busy__CI__VI = 0x000000c7, -DB_PERF_SEL_esr_eot_fwd_holding_squad__SI = 0x000000c8, -DB_PERF_SEL_esr_sqq_zi_stall__CI__VI = 0x000000c8, -DB_PERF_SEL_esr_eot_fwd_forward__SI = 0x000000c9, -DB_PERF_SEL_postzl_sq_pt_busy__CI__VI = 0x000000c9, -DB_PERF_SEL_esr_sqq_zi_busy__SI = 0x000000ca, -DB_PERF_SEL_postzl_sq_pt_stall__CI__VI = 0x000000ca, -DB_PERF_SEL_esr_sqq_zi_stall__SI = 0x000000cb, -DB_PERF_SEL_postzl_se_busy__CI__VI = 0x000000cb, -DB_PERF_SEL_postzl_sq_pt_busy__SI = 0x000000cc, -DB_PERF_SEL_postzl_se_stall__CI__VI = 0x000000cc, -DB_PERF_SEL_postzl_sq_pt_stall__SI = 0x000000cd, -DB_PERF_SEL_postzl_partial_launch__CI__VI = 0x000000cd, -DB_PERF_SEL_postzl_se_busy__SI = 0x000000ce, -DB_PERF_SEL_postzl_full_launch__CI__VI = 0x000000ce, -DB_PERF_SEL_postzl_se_stall__SI = 0x000000cf, -DB_PERF_SEL_postzl_partial_waiting__CI__VI = 0x000000cf, -DB_PERF_SEL_postzl_partial_launch__SI = 0x000000d0, -DB_PERF_SEL_postzl_tile_mem_stall__CI__VI = 0x000000d0, -DB_PERF_SEL_postzl_full_launch__SI = 0x000000d1, -DB_PERF_SEL_postzl_tile_init_stall__CI__VI = 0x000000d1, -DB_PERF_SEL_postzl_partial_waiting__SI = 0x000000d2, -DB_PEFF_SEL_prezl_tile_mem_stall__CI__VI = 0x000000d2, -DB_PERF_SEL_postzl_tile_mem_stall__SI = 0x000000d3, -DB_PERF_SEL_prezl_tile_init_stall__CI__VI = 0x000000d3, -DB_PERF_SEL_postzl_tile_init_stall__SI = 0x000000d4, -DB_PERF_SEL_dtt_sm_clash_stall__CI__VI = 0x000000d4, -DB_PEFF_SEL_prezl_tile_mem_stall__SI = 0x000000d5, -DB_PERF_SEL_dtt_sm_slot_stall__CI__VI = 0x000000d5, -DB_PERF_SEL_prezl_tile_init_stall__SI = 0x000000d6, -DB_PERF_SEL_dtt_sm_miss_stall__CI__VI = 0x000000d6, -DB_PERF_SEL_dtt_sm_clash_stall__SI = 0x000000d7, -DB_PERF_SEL_mi_rdreq_busy__CI__VI = 0x000000d7, -DB_PERF_SEL_dtt_sm_slot_stall__SI = 0x000000d8, -DB_PERF_SEL_mi_rdreq_stall__CI__VI = 0x000000d8, -DB_PERF_SEL_dtt_sm_miss_stall__SI = 0x000000d9, -DB_PERF_SEL_mi_wrreq_busy__CI__VI = 0x000000d9, -DB_PERF_SEL_mi_rdreq_busy__SI = 0x000000da, -DB_PERF_SEL_mi_wrreq_stall__CI__VI = 0x000000da, -DB_PERF_SEL_mi_rdreq_stall__SI = 0x000000db, -DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop__CI__VI = 0x000000db, -DB_PERF_SEL_mi_wrreq_busy__SI = 0x000000dc, -DB_PERF_SEL_dkg_tile_rate_tile__CI__VI = 0x000000dc, -DB_PERF_SEL_mi_wrreq_stall__SI = 0x000000dd, -DB_PERF_SEL_prezl_src_in_sends__CI__VI = 0x000000dd, -DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop__SI = 0x000000de, -DB_PERF_SEL_prezl_src_in_stall__CI__VI = 0x000000de, -DB_PERF_SEL_dkg_tile_rate_tile__SI = 0x000000df, -DB_PERF_SEL_prezl_src_in_squads__CI__VI = 0x000000df, -DB_PERF_SEL_prezl_src_in_sends__SI = 0x000000e0, -DB_PERF_SEL_prezl_src_in_squads_unrolled__CI__VI = 0x000000e0, -DB_PERF_SEL_prezl_src_in_stall__SI = 0x000000e1, -DB_PERF_SEL_prezl_src_in_tile_rate__CI__VI = 0x000000e1, -DB_PERF_SEL_prezl_src_in_squads__SI = 0x000000e2, -DB_PERF_SEL_prezl_src_in_tile_rate_unrolled__CI__VI = 0x000000e2, -DB_PERF_SEL_prezl_src_in_squads_unrolled__SI = 0x000000e3, -DB_PERF_SEL_prezl_src_out_stall__CI__VI = 0x000000e3, -DB_PERF_SEL_prezl_src_in_tile_rate__SI = 0x000000e4, -DB_PERF_SEL_postzl_src_in_sends__CI__VI = 0x000000e4, -DB_PERF_SEL_prezl_src_in_tile_rate_unrolled__SI = 0x000000e5, -DB_PERF_SEL_postzl_src_in_stall__CI__VI = 0x000000e5, -DB_PERF_SEL_prezl_src_out_stall__SI = 0x000000e6, -DB_PERF_SEL_postzl_src_in_squads__CI__VI = 0x000000e6, -DB_PERF_SEL_postzl_src_in_sends__SI = 0x000000e7, -DB_PERF_SEL_postzl_src_in_squads_unrolled__CI__VI = 0x000000e7, -DB_PERF_SEL_postzl_src_in_stall__SI = 0x000000e8, -DB_PERF_SEL_postzl_src_in_tile_rate__CI__VI = 0x000000e8, -DB_PERF_SEL_postzl_src_in_squads__SI = 0x000000e9, -DB_PERF_SEL_postzl_src_in_tile_rate_unrolled__CI__VI = 0x000000e9, -DB_PERF_SEL_postzl_src_in_squads_unrolled__SI = 0x000000ea, -DB_PERF_SEL_postzl_src_out_stall__CI__VI = 0x000000ea, -DB_PERF_SEL_postzl_src_in_tile_rate__SI = 0x000000eb, -DB_PERF_SEL_esr_ps_src_in_sends__CI__VI = 0x000000eb, -DB_PERF_SEL_postzl_src_in_tile_rate_unrolled__SI = 0x000000ec, -DB_PERF_SEL_esr_ps_src_in_stall__CI__VI = 0x000000ec, -DB_PERF_SEL_postzl_src_out_stall__SI = 0x000000ed, -DB_PERF_SEL_esr_ps_src_in_squads__CI__VI = 0x000000ed, -DB_PERF_SEL_esr_ps_src_in_sends__SI = 0x000000ee, -DB_PERF_SEL_esr_ps_src_in_squads_unrolled__CI__VI = 0x000000ee, -DB_PERF_SEL_esr_ps_src_in_stall__SI = 0x000000ef, -DB_PERF_SEL_esr_ps_src_in_tile_rate__CI__VI = 0x000000ef, -DB_PERF_SEL_esr_ps_src_in_squads__SI = 0x000000f0, -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled__CI__VI = 0x000000f0, -DB_PERF_SEL_esr_ps_src_in_squads_unrolled__SI = 0x000000f1, -DB_PERF_SEL_esr_ps_src_in_tile_rate__SI = 0x000000f2, -DB_PERF_SEL_esr_ps_src_out_stall__CI__VI = 0x000000f2, -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled__SI = 0x000000f3, -DB_PERF_SEL_depth_bounds_qtiles_culled__CI__VI = 0x000000f3, -DB_PERF_SEL_PreZ_Samples_failing_DB__CI__VI = 0x000000f4, -DB_PERF_SEL_esr_ps_src_out_stall__SI = 0x000000f5, -DB_PERF_SEL_PostZ_Samples_failing_DB__CI__VI = 0x000000f5, -DB_PERF_SEL_depth_bounds_qtiles_culled__SI = 0x000000f6, -DB_PERF_SEL_flush_compressed__CI__VI = 0x000000f6, -DB_PERF_SEL_PreZ_Samples_failing_DB__SI = 0x000000f7, -DB_PERF_SEL_flush_plane_le4__CI__VI = 0x000000f7, -DB_PERF_SEL_PostZ_Samples_failing_DB__SI = 0x000000f8, -DB_PERF_SEL_tiles_z_fully_summarized__CI__VI = 0x000000f8, -DB_PERF_SEL_tiles_stencil_fully_summarized__CI__VI = 0x000000f9, -DB_PERF_SEL_tiles_z_clear_on_expclear__CI__VI = 0x000000fa, -DB_PERF_SEL_tiles_s_clear_on_expclear__CI__VI = 0x000000fb, -DB_PERF_SEL_tiles_decomp_on_expclear__CI__VI = 0x000000fc, -DB_PERF_SEL_tiles_compressed_to_decompressed__CI__VI = 0x000000fd, -DB_PERF_SEL_Op_Pipe_Prez_Busy__CI__VI = 0x000000fe, -DB_PERF_SEL_Op_Pipe_Postz_Busy__CI__VI = 0x000000ff, -DB_PERF_SEL_di_dt_stall__CI__VI = 0x00000100, -} PerfCounter_Vals; - -typedef enum PipeConfig { -ADDR_SURF_P2 = 0x00000000, -ADDR_SURF_P2_RESERVED0 = 0x00000001, -ADDR_SURF_P2_RESERVED1 = 0x00000002, -ADDR_SURF_P2_RESERVED2 = 0x00000003, -ADDR_SURF_P4_8x16 = 0x00000004, -ADDR_SURF_P4_16x16 = 0x00000005, -ADDR_SURF_P4_16x32 = 0x00000006, -ADDR_SURF_P4_32x32 = 0x00000007, -ADDR_SURF_P8_16x16_8x16 = 0x00000008, -ADDR_SURF_P8_16x32_8x16 = 0x00000009, -ADDR_SURF_P8_32x32_8x16 = 0x0000000a, -ADDR_SURF_P8_16x32_16x16 = 0x0000000b, -ADDR_SURF_P8_32x32_16x16 = 0x0000000c, -ADDR_SURF_P8_32x32_16x32 = 0x0000000d, -ADDR_SURF_P8_32x64_32x32 = 0x0000000e, -ADDR_SURF_P8_RESERVED0__CI__VI = 0x0000000f, -ADDR_SURF_P16_32x32_8x16__CI__VI = 0x00000010, -ADDR_SURF_P16_32x32_16x16__CI__VI = 0x00000011, -} PipeConfig; - -typedef enum PipeInterleaveSize { -ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, -ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, -} PipeInterleaveSize; - -typedef enum PipeTiling { -CONFIG_1_PIPE = 0x00000000, -CONFIG_2_PIPE = 0x00000001, -CONFIG_4_PIPE = 0x00000002, -CONFIG_8_PIPE = 0x00000003, -} PipeTiling; - -typedef enum PixelPipeCounterId { -PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000, -PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001, -PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002, -PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003, -PIXEL_PIPE_SCREEN_MIN_EXTENTS_0__VI = 0x00000004, -PIXEL_PIPE_SCREEN_MAX_EXTENTS_0__VI = 0x00000005, -PIXEL_PIPE_SCREEN_MIN_EXTENTS_1__VI = 0x00000006, -PIXEL_PIPE_SCREEN_MAX_EXTENTS_1__VI = 0x00000007, -} PixelPipeCounterId; - -typedef enum PixelPipeStride { -PIXEL_PIPE_STRIDE_32_BITS = 0x00000000, -PIXEL_PIPE_STRIDE_64_BITS = 0x00000001, -PIXEL_PIPE_STRIDE_128_BITS = 0x00000002, -PIXEL_PIPE_STRIDE_256_BITS = 0x00000003, -} PixelPipeStride; - -typedef enum PkrMap { -RASTER_CONFIG_PKR_MAP_0 = 0x00000000, -RASTER_CONFIG_PKR_MAP_1 = 0x00000001, -RASTER_CONFIG_PKR_MAP_2 = 0x00000002, -RASTER_CONFIG_PKR_MAP_3 = 0x00000003, -} PkrMap; - -typedef enum PkrXsel { -RASTER_CONFIG_PKR_XSEL_0 = 0x00000000, -RASTER_CONFIG_PKR_XSEL_1 = 0x00000001, -RASTER_CONFIG_PKR_XSEL_2 = 0x00000002, -RASTER_CONFIG_PKR_XSEL_3 = 0x00000003, -} PkrXsel; - -typedef enum PkrXsel2 { -RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000, -RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001, -RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002, -RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003, -} PkrXsel2; - -typedef enum PkrYsel { -RASTER_CONFIG_PKR_YSEL_0 = 0x00000000, -RASTER_CONFIG_PKR_YSEL_1 = 0x00000001, -RASTER_CONFIG_PKR_YSEL_2 = 0x00000002, -RASTER_CONFIG_PKR_YSEL_3 = 0x00000003, -} PkrYsel; - -typedef enum QuadExportFormat { -EXPORT_UNUSED = 0x00000000, -EXPORT_32_R = 0x00000001, -EXPORT_32_GR = 0x00000002, -EXPORT_32_AR = 0x00000003, -EXPORT_FP16_ABGR = 0x00000004, -EXPORT_UNSIGNED16_ABGR = 0x00000005, -EXPORT_SIGNED16_ABGR = 0x00000006, -EXPORT_32_ABGR = 0x00000007, -} QuadExportFormat; - -typedef enum QuadExportFormatOld { -EXPORT_4P_32BPC_ABGR = 0x00000000, -EXPORT_4P_16BPC_ABGR = 0x00000001, -EXPORT_4P_32BPC_GR = 0x00000002, -EXPORT_4P_32BPC_AR = 0x00000003, -EXPORT_2P_32BPC_ABGR = 0x00000004, -EXPORT_8P_32BPC_R = 0x00000005, -} QuadExportFormatOld; - -typedef enum RbMap { -RASTER_CONFIG_RB_MAP_0 = 0x00000000, -RASTER_CONFIG_RB_MAP_1 = 0x00000001, -RASTER_CONFIG_RB_MAP_2 = 0x00000002, -RASTER_CONFIG_RB_MAP_3 = 0x00000003, -} RbMap; - -typedef enum RbXsel { -RASTER_CONFIG_RB_XSEL_0 = 0x00000000, -RASTER_CONFIG_RB_XSEL_1 = 0x00000001, -} RbXsel; - -typedef enum RbXsel2 { -RASTER_CONFIG_RB_XSEL2_0 = 0x00000000, -RASTER_CONFIG_RB_XSEL2_1 = 0x00000001, -RASTER_CONFIG_RB_XSEL2_2 = 0x00000002, -RASTER_CONFIG_RB_XSEL2_3 = 0x00000003, -} RbXsel2; - -typedef enum RbYsel { -RASTER_CONFIG_RB_YSEL_0 = 0x00000000, -RASTER_CONFIG_RB_YSEL_1 = 0x00000001, -} RbYsel; - -typedef enum ReadSize { -READ_256_BITS = 0x00000000, -READ_512_BITS = 0x00000001, -} ReadSize; - -typedef enum RingCounterControl { -COUNTER_RING_SPLIT = 0x00000000, -COUNTER_RING_0 = 0x00000001, -COUNTER_RING_1 = 0x00000002, -} RingCounterControl; - -typedef enum RoundMode { -ROUND_BY_HALF = 0x00000000, -ROUND_TRUNCATE = 0x00000001, -} RoundMode; - -typedef enum RowSize { -ADDR_CONFIG_1KB_ROW = 0x00000000, -ADDR_CONFIG_2KB_ROW = 0x00000001, -ADDR_CONFIG_4KB_ROW = 0x00000002, -} RowSize; - -typedef enum RowTiling { -CONFIG_1KB_ROW = 0x00000000, -CONFIG_2KB_ROW = 0x00000001, -CONFIG_4KB_ROW = 0x00000002, -CONFIG_8KB_ROW = 0x00000003, -CONFIG_1KB_ROW_OPT = 0x00000004, -CONFIG_2KB_ROW_OPT = 0x00000005, -CONFIG_4KB_ROW_OPT = 0x00000006, -CONFIG_8KB_ROW_OPT = 0x00000007, -} RowTiling; - -typedef enum SC_PERFCNT_SEL { -SC_SRPS_WINDOW_VALID = 0x00000000, -SC_PSSW_WINDOW_VALID = 0x00000001, -SC_TPQZ_WINDOW_VALID = 0x00000002, -SC_QZQP_WINDOW_VALID = 0x00000003, -SC_TRPK_WINDOW_VALID = 0x00000004, -SC_SRPS_WINDOW_VALID_BUSY = 0x00000005, -SC_PSSW_WINDOW_VALID_BUSY = 0x00000006, -SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007, -SC_QZQP_WINDOW_VALID_BUSY = 0x00000008, -SC_TRPK_WINDOW_VALID_BUSY = 0x00000009, -SC_STARVED_BY_PA = 0x0000000a, -SC_STALLED_BY_PRIMFIFO = 0x0000000b, -SC_STALLED_BY_DB_TILE = 0x0000000c, -SC_STARVED_BY_DB_TILE = 0x0000000d, -SC_STALLED_BY_TILEORDERFIFO = 0x0000000e, -SC_STALLED_BY_TILEFIFO = 0x0000000f, -SC_STALLED_BY_DB_QUAD = 0x00000010, -SC_STARVED_BY_DB_QUAD = 0x00000011, -SC_STALLED_BY_QUADFIFO = 0x00000012, -SC_STALLED_BY_BCI = 0x00000013, -SC_STALLED_BY_SPI = 0x00000014, -SC_SCISSOR_DISCARD = 0x00000015, -SC_BB_DISCARD = 0x00000016, -SC_SUPERTILE_COUNT = 0x00000017, -SC_SUPERTILE_PER_PRIM_H0 = 0x00000018, -SC_SUPERTILE_PER_PRIM_H1 = 0x00000019, -SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a, -SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b, -SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c, -SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d, -SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e, -SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f, -SC_SUPERTILE_PER_PRIM_H8 = 0x00000020, -SC_SUPERTILE_PER_PRIM_H9 = 0x00000021, -SC_SUPERTILE_PER_PRIM_H10 = 0x00000022, -SC_SUPERTILE_PER_PRIM_H11 = 0x00000023, -SC_SUPERTILE_PER_PRIM_H12 = 0x00000024, -SC_SUPERTILE_PER_PRIM_H13 = 0x00000025, -SC_SUPERTILE_PER_PRIM_H14 = 0x00000026, -SC_SUPERTILE_PER_PRIM_H15 = 0x00000027, -SC_SUPERTILE_PER_PRIM_H16 = 0x00000028, -SC_TILE_PER_PRIM_H0 = 0x00000029, -SC_TILE_PER_PRIM_H1 = 0x0000002a, -SC_TILE_PER_PRIM_H2 = 0x0000002b, -SC_TILE_PER_PRIM_H3 = 0x0000002c, -SC_TILE_PER_PRIM_H4 = 0x0000002d, -SC_TILE_PER_PRIM_H5 = 0x0000002e, -SC_TILE_PER_PRIM_H6 = 0x0000002f, -SC_TILE_PER_PRIM_H7 = 0x00000030, -SC_TILE_PER_PRIM_H8 = 0x00000031, -SC_TILE_PER_PRIM_H9 = 0x00000032, -SC_TILE_PER_PRIM_H10 = 0x00000033, -SC_TILE_PER_PRIM_H11 = 0x00000034, -SC_TILE_PER_PRIM_H12 = 0x00000035, -SC_TILE_PER_PRIM_H13 = 0x00000036, -SC_TILE_PER_PRIM_H14 = 0x00000037, -SC_TILE_PER_PRIM_H15 = 0x00000038, -SC_TILE_PER_PRIM_H16 = 0x00000039, -SC_TILE_PER_SUPERTILE_H0 = 0x0000003a, -SC_TILE_PER_SUPERTILE_H1 = 0x0000003b, -SC_TILE_PER_SUPERTILE_H2 = 0x0000003c, -SC_TILE_PER_SUPERTILE_H3 = 0x0000003d, -SC_TILE_PER_SUPERTILE_H4 = 0x0000003e, -SC_TILE_PER_SUPERTILE_H5 = 0x0000003f, -SC_TILE_PER_SUPERTILE_H6 = 0x00000040, -SC_TILE_PER_SUPERTILE_H7 = 0x00000041, -SC_TILE_PER_SUPERTILE_H8 = 0x00000042, -SC_TILE_PER_SUPERTILE_H9 = 0x00000043, -SC_TILE_PER_SUPERTILE_H10 = 0x00000044, -SC_TILE_PER_SUPERTILE_H11 = 0x00000045, -SC_TILE_PER_SUPERTILE_H12 = 0x00000046, -SC_TILE_PER_SUPERTILE_H13 = 0x00000047, -SC_TILE_PER_SUPERTILE_H14 = 0x00000048, -SC_TILE_PER_SUPERTILE_H15 = 0x00000049, -SC_TILE_PER_SUPERTILE_H16 = 0x0000004a, -SC_TILE_PICKED_H1 = 0x0000004b, -SC_TILE_PICKED_H2 = 0x0000004c, -SC_TILE_PICKED_H3 = 0x0000004d, -SC_TILE_PICKED_H4 = 0x0000004e, -SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x0000004f, -SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x00000050, -SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x00000051, -SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x00000052, -SC_QZ0_TILE_COUNT = 0x00000053, -SC_QZ1_TILE_COUNT = 0x00000054, -SC_QZ2_TILE_COUNT = 0x00000055, -SC_QZ3_TILE_COUNT = 0x00000056, -SC_QZ0_TILE_COVERED_COUNT = 0x00000057, -SC_QZ1_TILE_COVERED_COUNT = 0x00000058, -SC_QZ2_TILE_COVERED_COUNT = 0x00000059, -SC_QZ3_TILE_COVERED_COUNT = 0x0000005a, -SC_QZ0_TILE_NOT_COVERED_COUNT = 0x0000005b, -SC_QZ1_TILE_NOT_COVERED_COUNT = 0x0000005c, -SC_QZ2_TILE_NOT_COVERED_COUNT = 0x0000005d, -SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005e, -SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005f, -SC_QZ0_QUAD_PER_TILE_H1 = 0x00000060, -SC_QZ0_QUAD_PER_TILE_H2 = 0x00000061, -SC_QZ0_QUAD_PER_TILE_H3 = 0x00000062, -SC_QZ0_QUAD_PER_TILE_H4 = 0x00000063, -SC_QZ0_QUAD_PER_TILE_H5 = 0x00000064, -SC_QZ0_QUAD_PER_TILE_H6 = 0x00000065, -SC_QZ0_QUAD_PER_TILE_H7 = 0x00000066, -SC_QZ0_QUAD_PER_TILE_H8 = 0x00000067, -SC_QZ0_QUAD_PER_TILE_H9 = 0x00000068, -SC_QZ0_QUAD_PER_TILE_H10 = 0x00000069, -SC_QZ0_QUAD_PER_TILE_H11 = 0x0000006a, -SC_QZ0_QUAD_PER_TILE_H12 = 0x0000006b, -SC_QZ0_QUAD_PER_TILE_H13 = 0x0000006c, -SC_QZ0_QUAD_PER_TILE_H14 = 0x0000006d, -SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006e, -SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006f, -SC_QZ1_QUAD_PER_TILE_H0 = 0x00000070, -SC_QZ1_QUAD_PER_TILE_H1 = 0x00000071, -SC_QZ1_QUAD_PER_TILE_H2 = 0x00000072, -SC_QZ1_QUAD_PER_TILE_H3 = 0x00000073, -SC_QZ1_QUAD_PER_TILE_H4 = 0x00000074, -SC_QZ1_QUAD_PER_TILE_H5 = 0x00000075, -SC_QZ1_QUAD_PER_TILE_H6 = 0x00000076, -SC_QZ1_QUAD_PER_TILE_H7 = 0x00000077, -SC_QZ1_QUAD_PER_TILE_H8 = 0x00000078, -SC_QZ1_QUAD_PER_TILE_H9 = 0x00000079, -SC_QZ1_QUAD_PER_TILE_H10 = 0x0000007a, -SC_QZ1_QUAD_PER_TILE_H11 = 0x0000007b, -SC_QZ1_QUAD_PER_TILE_H12 = 0x0000007c, -SC_QZ1_QUAD_PER_TILE_H13 = 0x0000007d, -SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007e, -SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007f, -SC_QZ1_QUAD_PER_TILE_H16 = 0x00000080, -SC_QZ2_QUAD_PER_TILE_H0 = 0x00000081, -SC_QZ2_QUAD_PER_TILE_H1 = 0x00000082, -SC_QZ2_QUAD_PER_TILE_H2 = 0x00000083, -SC_QZ2_QUAD_PER_TILE_H3 = 0x00000084, -SC_QZ2_QUAD_PER_TILE_H4 = 0x00000085, -SC_QZ2_QUAD_PER_TILE_H5 = 0x00000086, -SC_QZ2_QUAD_PER_TILE_H6 = 0x00000087, -SC_QZ2_QUAD_PER_TILE_H7 = 0x00000088, -SC_QZ2_QUAD_PER_TILE_H8 = 0x00000089, -SC_QZ2_QUAD_PER_TILE_H9 = 0x0000008a, -SC_QZ2_QUAD_PER_TILE_H10 = 0x0000008b, -SC_QZ2_QUAD_PER_TILE_H11 = 0x0000008c, -SC_QZ2_QUAD_PER_TILE_H12 = 0x0000008d, -SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008e, -SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008f, -SC_QZ2_QUAD_PER_TILE_H15 = 0x00000090, -SC_QZ2_QUAD_PER_TILE_H16 = 0x00000091, -SC_QZ3_QUAD_PER_TILE_H0 = 0x00000092, -SC_QZ3_QUAD_PER_TILE_H1 = 0x00000093, -SC_QZ3_QUAD_PER_TILE_H2 = 0x00000094, -SC_QZ3_QUAD_PER_TILE_H3 = 0x00000095, -SC_QZ3_QUAD_PER_TILE_H4 = 0x00000096, -SC_QZ3_QUAD_PER_TILE_H5 = 0x00000097, -SC_QZ3_QUAD_PER_TILE_H6 = 0x00000098, -SC_QZ3_QUAD_PER_TILE_H7 = 0x00000099, -SC_QZ3_QUAD_PER_TILE_H8 = 0x0000009a, -SC_QZ3_QUAD_PER_TILE_H9 = 0x0000009b, -SC_QZ3_QUAD_PER_TILE_H10 = 0x0000009c, -SC_QZ3_QUAD_PER_TILE_H11 = 0x0000009d, -SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009e, -SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009f, -SC_QZ3_QUAD_PER_TILE_H14 = 0x000000a0, -SC_QZ3_QUAD_PER_TILE_H15 = 0x000000a1, -SC_QZ3_QUAD_PER_TILE_H16 = 0x000000a2, -SC_QZ0_QUAD_COUNT = 0x000000a3, -SC_QZ1_QUAD_COUNT = 0x000000a4, -SC_QZ2_QUAD_COUNT = 0x000000a5, -SC_QZ3_QUAD_COUNT = 0x000000a6, -SC_P0_HIZ_TILE_COUNT = 0x000000a7, -SC_P1_HIZ_TILE_COUNT = 0x000000a8, -SC_P2_HIZ_TILE_COUNT = 0x000000a9, -SC_P3_HIZ_TILE_COUNT = 0x000000aa, -SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000ab, -SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000ac, -SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000ad, -SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000ae, -SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000af, -SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000b0, -SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000b1, -SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000b2, -SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000b3, -SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b4, -SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b5, -SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b6, -SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b7, -SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b8, -SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b9, -SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000ba, -SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000bb, -SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000bc, -SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000bd, -SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000be, -SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bf, -SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000c0, -SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000c1, -SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000c2, -SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000c3, -SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c4, -SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c5, -SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c6, -SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c7, -SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c8, -SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c9, -SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000ca, -SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000cb, -SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000cc, -SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000cd, -SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ce, -SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cf, -SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000d0, -SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000d1, -SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000d2, -SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000d3, -SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d4, -SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d5, -SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d6, -SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d7, -SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d8, -SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d9, -SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000da, -SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000db, -SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000dc, -SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000dd, -SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000de, -SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000df, -SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000e0, -SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000e1, -SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000e2, -SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000e3, -SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e4, -SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e5, -SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e6, -SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e7, -SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e8, -SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e9, -SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000ea, -SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000eb, -SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000ec, -SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000ed, -SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ee, -SC_P0_HIZ_QUAD_COUNT = 0x000000ef, -SC_P1_HIZ_QUAD_COUNT = 0x000000f0, -SC_P2_HIZ_QUAD_COUNT = 0x000000f1, -SC_P3_HIZ_QUAD_COUNT = 0x000000f2, -SC_P0_DETAIL_QUAD_COUNT = 0x000000f3, -SC_P1_DETAIL_QUAD_COUNT = 0x000000f4, -SC_P2_DETAIL_QUAD_COUNT = 0x000000f5, -SC_P3_DETAIL_QUAD_COUNT = 0x000000f6, -SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f7, -SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f8, -SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f9, -SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000fa, -SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000fb, -SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000fc, -SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000fd, -SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fe, -SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000ff, -SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x00000100, -SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x00000101, -SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x00000102, -SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x00000103, -SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000104, -SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000105, -SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000106, -SC_EARLYZ_QUAD_COUNT = 0x00000107, -SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000108, -SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000109, -SC_EARLYZ_QUAD_WITH_3_PIX = 0x0000010a, -SC_EARLYZ_QUAD_WITH_4_PIX = 0x0000010b, -SC_PKR_QUAD_PER_ROW_H1 = 0x0000010c, -SC_PKR_QUAD_PER_ROW_H2 = 0x0000010d, -SC_PKR_QUAD_PER_ROW_H3 = 0x0000010e, -SC_PKR_QUAD_PER_ROW_H4 = 0x0000010f, -SC_PKR_END_OF_VECTOR = 0x00000110, -SC_PKR_CONTROL_XFER = 0x00000111, -SC_PKR_DBHANG_FORCE_EOV = 0x00000112, -SC_REG_SCLK_BUSY = 0x00000113, -SC_GRP0_DYN_SCLK_BUSY = 0x00000114, -SC_GRP1_DYN_SCLK_BUSY = 0x00000115, -SC_GRP2_DYN_SCLK_BUSY = 0x00000116, -SC_GRP3_DYN_SCLK_BUSY = 0x00000117, -SC_GRP4_DYN_SCLK_BUSY = 0x00000118, -SC_PA0_SC_DATA_FIFO_RD = 0x00000119, -SC_PA0_SC_DATA_FIFO_WE = 0x0000011a, -SC_PA1_SC_DATA_FIFO_RD = 0x0000011b, -SC_PA1_SC_DATA_FIFO_WE = 0x0000011c, -SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x0000011d, -SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011e, -SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011f, -SC_PS_ARB_STALLED_FROM_BELOW = 0x00000120, -SC_PS_ARB_STARVED_FROM_ABOVE = 0x00000121, -SC_PS_ARB_SC_BUSY = 0x00000122, -SC_PS_ARB_PA_SC_BUSY = 0x00000123, -SC_PA2_SC_DATA_FIFO_RD__CI__VI = 0x00000124, -SC_PA2_SC_DATA_FIFO_WE__CI__VI = 0x00000125, -SC_PA3_SC_DATA_FIFO_RD__CI__VI = 0x00000126, -SC_PA3_SC_DATA_FIFO_WE__CI__VI = 0x00000127, -SC_PA_SC_DEALLOC_0_0_WE__CI__VI = 0x00000128, -SC_PA_SC_DEALLOC_0_1_WE__CI__VI = 0x00000129, -SC_PA_SC_DEALLOC_1_0_WE__CI__VI = 0x0000012a, -SC_PA_SC_DEALLOC_1_1_WE__CI__VI = 0x0000012b, -SC_PA_SC_DEALLOC_2_0_WE__CI__VI = 0x0000012c, -SC_PA_SC_DEALLOC_2_1_WE__CI__VI = 0x0000012d, -SC_PA_SC_DEALLOC_3_0_WE__CI__VI = 0x0000012e, -SC_PA_SC_DEALLOC_3_1_WE__CI__VI = 0x0000012f, -SC_PA0_SC_EOP_WE__CI__VI = 0x00000130, -SC_PA0_SC_EOPG_WE__CI__VI = 0x00000131, -SC_PA0_SC_EVENT_WE__CI__VI = 0x00000132, -SC_PA1_SC_EOP_WE__CI__VI = 0x00000133, -SC_PA1_SC_EOPG_WE__CI__VI = 0x00000134, -SC_PA1_SC_EVENT_WE__CI__VI = 0x00000135, -SC_PA2_SC_EOP_WE__CI__VI = 0x00000136, -SC_PA2_SC_EOPG_WE__CI__VI = 0x00000137, -SC_PA2_SC_EVENT_WE__CI__VI = 0x00000138, -SC_PA3_SC_EOP_WE__CI__VI = 0x00000139, -SC_PA3_SC_EOPG_WE__CI__VI = 0x0000013a, -SC_PA3_SC_EVENT_WE__CI__VI = 0x0000013b, -SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO__CI__VI = 0x0000013c, -SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH__CI__VI = 0x0000013d, -SC_PS_ARB_NULL_PRIM_BUBBLE_POP__CI__VI = 0x0000013e, -SC_PS_ARB_EOP_POP_SYNC_POP__CI__VI = 0x0000013f, -SC_PS_ARB_EVENT_SYNC_POP__CI__VI = 0x00000140, -SC_SC_PS_ENG_MULTICYCLE_BUBBLE__CI__VI = 0x00000141, -SC_PA0_SC_FPOV_WE__CI__VI = 0x00000142, -SC_PA1_SC_FPOV_WE__CI__VI = 0x00000143, -SC_PA2_SC_FPOV_WE__CI__VI = 0x00000144, -SC_PA3_SC_FPOV_WE__CI__VI = 0x00000145, -SC_PA0_SC_LPOV_WE__CI__VI = 0x00000146, -SC_PA1_SC_LPOV_WE__CI__VI = 0x00000147, -SC_PA2_SC_LPOV_WE__CI__VI = 0x00000148, -SC_PA3_SC_LPOV_WE__CI__VI = 0x00000149, -SC_SC_SPI_DEALLOC_0_0__CI__VI = 0x0000014a, -SC_SC_SPI_DEALLOC_0_1__CI__VI = 0x0000014b, -SC_SC_SPI_DEALLOC_0_2__CI__VI = 0x0000014c, -SC_SC_SPI_DEALLOC_1_0__CI__VI = 0x0000014d, -SC_SC_SPI_DEALLOC_1_1__CI__VI = 0x0000014e, -SC_SC_SPI_DEALLOC_1_2__CI__VI = 0x0000014f, -SC_SC_SPI_DEALLOC_2_0__CI__VI = 0x00000150, -SC_SC_SPI_DEALLOC_2_1__CI__VI = 0x00000151, -SC_SC_SPI_DEALLOC_2_2__CI__VI = 0x00000152, -SC_SC_SPI_DEALLOC_3_0__CI__VI = 0x00000153, -SC_SC_SPI_DEALLOC_3_1__CI__VI = 0x00000154, -SC_SC_SPI_DEALLOC_3_2__CI__VI = 0x00000155, -SC_SC_SPI_FPOV_0__CI__VI = 0x00000156, -SC_SC_SPI_FPOV_1__CI__VI = 0x00000157, -SC_SC_SPI_FPOV_2__CI__VI = 0x00000158, -SC_SC_SPI_FPOV_3__CI__VI = 0x00000159, -SC_SC_SPI_EVENT__CI__VI = 0x0000015a, -SC_PS_TS_EVENT_FIFO_PUSH__CI__VI = 0x0000015b, -SC_PS_TS_EVENT_FIFO_POP__CI__VI = 0x0000015c, -SC_PS_CTX_DONE_FIFO_PUSH__CI__VI = 0x0000015d, -SC_PS_CTX_DONE_FIFO_POP__CI__VI = 0x0000015e, -SC_MULTICYCLE_BUBBLE_FREEZE__CI__VI = 0x0000015f, -SC_EOP_SYNC_WINDOW__CI__VI = 0x00000160, -SC_PA0_SC_NULL_WE__CI__VI = 0x00000161, -SC_PA0_SC_NULL_DEALLOC_WE__CI__VI = 0x00000162, -SC_PA0_SC_DATA_FIFO_EOPG_RD__CI__VI = 0x00000163, -SC_PA0_SC_DATA_FIFO_EOP_RD__CI__VI = 0x00000164, -SC_PA0_SC_DEALLOC_0_RD__CI__VI = 0x00000165, -SC_PA0_SC_DEALLOC_1_RD__CI__VI = 0x00000166, -SC_PA1_SC_DATA_FIFO_EOPG_RD__CI__VI = 0x00000167, -SC_PA1_SC_DATA_FIFO_EOP_RD__CI__VI = 0x00000168, -SC_PA1_SC_DEALLOC_0_RD__CI__VI = 0x00000169, -SC_PA1_SC_DEALLOC_1_RD__CI__VI = 0x0000016a, -SC_PA1_SC_NULL_WE__CI__VI = 0x0000016b, -SC_PA1_SC_NULL_DEALLOC_WE__CI__VI = 0x0000016c, -SC_PA2_SC_DATA_FIFO_EOPG_RD__CI__VI = 0x0000016d, -SC_PA2_SC_DATA_FIFO_EOP_RD__CI__VI = 0x0000016e, -SC_PA2_SC_DEALLOC_0_RD__CI__VI = 0x0000016f, -SC_PA2_SC_DEALLOC_1_RD__CI__VI = 0x00000170, -SC_PA2_SC_NULL_WE__CI__VI = 0x00000171, -SC_PA2_SC_NULL_DEALLOC_WE__CI__VI = 0x00000172, -SC_PA3_SC_DATA_FIFO_EOPG_RD__CI__VI = 0x00000173, -SC_PA3_SC_DATA_FIFO_EOP_RD__CI__VI = 0x00000174, -SC_PA3_SC_DEALLOC_0_RD__CI__VI = 0x00000175, -SC_PA3_SC_DEALLOC_1_RD__CI__VI = 0x00000176, -SC_PA3_SC_NULL_WE__CI__VI = 0x00000177, -SC_PA3_SC_NULL_DEALLOC_WE__CI__VI = 0x00000178, -SC_PS_PA0_SC_FIFO_EMPTY__CI__VI = 0x00000179, -SC_PS_PA0_SC_FIFO_FULL__CI__VI = 0x0000017a, -SC_PA0_PS_DATA_SEND__CI__VI = 0x0000017b, -SC_PS_PA1_SC_FIFO_EMPTY__CI__VI = 0x0000017c, -SC_PS_PA1_SC_FIFO_FULL__CI__VI = 0x0000017d, -SC_PA1_PS_DATA_SEND__CI__VI = 0x0000017e, -SC_PS_PA2_SC_FIFO_EMPTY__CI__VI = 0x0000017f, -SC_PS_PA2_SC_FIFO_FULL__CI__VI = 0x00000180, -SC_PA2_PS_DATA_SEND__CI__VI = 0x00000181, -SC_PS_PA3_SC_FIFO_EMPTY__CI__VI = 0x00000182, -SC_PS_PA3_SC_FIFO_FULL__CI__VI = 0x00000183, -SC_PA3_PS_DATA_SEND__CI__VI = 0x00000184, -SC_BUSY_PROCESSING_MULTICYCLE_PRIM__CI__VI = 0x00000185, -SC_BUSY_CNT_NOT_ZERO__CI__VI = 0x00000186, -SC_BM_BUSY__CI__VI = 0x00000187, -SC_BACKEND_BUSY__CI__VI = 0x00000188, -SC_SCF_SCB_INTERFACE_BUSY__CI__VI = 0x00000189, -SC_SCB_BUSY__CI__VI = 0x0000018a, -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY__VI = 0x0000018b, -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL__VI = 0x0000018c, -} SC_PERFCNT_SEL; - -typedef enum SDMA_PERF_SEL { -SDMA_PERF_SEL_CYCLE = 0x00000000, -SDMA_PERF_SEL_IDLE = 0x00000001, -SDMA_PERF_SEL_REG_IDLE = 0x00000002, -SDMA_PERF_SEL_RB_EMPTY = 0x00000003, -SDMA_PERF_SEL_RB_FULL = 0x00000004, -SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, -SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, -SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, -SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, -SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, -SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, -SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, -SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, -SDMA_PERF_SEL_EX_IDLE = 0x0000000d, -SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, -SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, -SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, -SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, -SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, -SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, -SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, -SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, -SDMA_PERF_SEL_SEM_IDLE = 0x00000018, -SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, -SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, -SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, -SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, -SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, -SDMA_PERF_SEL_INT_IDLE = 0x0000001e, -SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, -SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, -SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, -SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, -SDMA_PERF_SEL_NUM_PACKET = 0x00000023, -SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, -SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, -SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, -SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, -SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, -SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, -SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, -SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, -SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, -SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, -SDMA_PERF_SEL_CE_RD_STALL = 0x00000033, -SDMA_PERF_SEL_CE_WR_STALL = 0x00000034, -SDMA_PERF_SEL_GFX_SELECT__VI = 0x00000035, -SDMA_PERF_SEL_RLC0_SELECT__VI = 0x00000036, -SDMA_PERF_SEL_RLC1_SELECT__VI = 0x00000037, -SDMA_PERF_SEL_CTX_CHANGE__VI = 0x00000038, -SDMA_PERF_SEL_CTX_CHANGE_EXPIRED__VI = 0x00000039, -SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION__VI = 0x0000003a, -SDMA_PERF_SEL_DOORBELL__VI = 0x0000003b, -SDMA_PERF_SEL_RD_BA_RTR__VI = 0x0000003c, -SDMA_PERF_SEL_WR_BA_RTR__VI = 0x0000003d, -} SDMA_PERF_SEL; - -typedef enum SH_MEM_ALIGNMENT_MODE { -SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, -SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001, -SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002, -SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003, -} SH_MEM_ALIGNMENT_MODE; - -typedef enum SPI_FOG_MODE { -SPI_FOG_NONE = 0x00000000, -SPI_FOG_EXP = 0x00000001, -SPI_FOG_EXP2 = 0x00000002, -SPI_FOG_LINEAR = 0x00000003, -} SPI_FOG_MODE; - -typedef enum SPI_PERFCNT_SEL { -SPI_PERF_VS_WINDOW_VALID = 0x00000000, -SPI_PERF_VS_BUSY = 0x00000001, -SPI_PERF_VS_FIRST_WAVE = 0x00000002, -SPI_PERF_VS_LAST_WAVE = 0x00000003, -SPI_PERF_VS_LSHS_DEALLOC = 0x00000004, -SPI_PERF_VS_PC_STALL = 0x00000005, -SPI_PERF_VS_POS0_STALL = 0x00000006, -SPI_PERF_VS_POS1_STALL = 0x00000007, -SPI_PERF_VS_CRAWLER_STALL = 0x00000008, -SPI_PERF_VS_EVENT_WAVE = 0x00000009, -SPI_PERF_VS_WAVE = 0x0000000a, -SPI_PERF_VS_PERS_UPD_FULL0__CI__VI = 0x0000000b, -SPI_PERF_GS_WINDOW_VALID__SI = 0x0000000c, -SPI_PERF_VS_PERS_UPD_FULL1__CI__VI = 0x0000000c, -SPI_PERF_GS_BUSY__SI = 0x0000000d, -SPI_PERF_VS_LATE_ALLOC_FULL__CI__VI = 0x0000000d, -SPI_PERF_GS_CRAWLER_STALL__SI = 0x0000000e, -SPI_PERF_VS_FIRST_SUBGRP__CI__VI = 0x0000000e, -SPI_PERF_GS_EVENT_WAVE__SI = 0x0000000f, -SPI_PERF_VS_LAST_SUBGRP__CI__VI = 0x0000000f, -SPI_PERF_GS_WAVE__SI = 0x00000010, -SPI_PERF_GS_WINDOW_VALID__CI__VI = 0x00000010, -SPI_PERF_GS_BUSY__CI__VI = 0x00000011, -SPI_PERF_ES_WINDOW_VALID__SI = 0x00000012, -SPI_PERF_GS_CRAWLER_STALL__CI__VI = 0x00000012, -SPI_PERF_ES_BUSY__SI = 0x00000013, -SPI_PERF_GS_EVENT_WAVE__CI__VI = 0x00000013, -SPI_PERF_ES_CRAWLER_STALL__SI = 0x00000014, -SPI_PERF_GS_WAVE__CI__VI = 0x00000014, -SPI_PERF_ES_FIRST_WAVE__SI = 0x00000015, -SPI_PERF_GS_PERS_UPD_FULL0__CI__VI = 0x00000015, -SPI_PERF_ES_LAST_WAVE__SI = 0x00000016, -SPI_PERF_GS_PERS_UPD_FULL1__CI__VI = 0x00000016, -SPI_PERF_ES_LSHS_DEALLOC__SI = 0x00000017, -SPI_PERF_GS_FIRST_SUBGRP__CI__VI = 0x00000017, -SPI_PERF_ES_EVENT_WAVE__SI = 0x00000018, -SPI_PERF_GS_LAST_SUBGRP__CI__VI = 0x00000018, -SPI_PERF_ES_WAVE__SI = 0x00000019, -SPI_PERF_ES_WINDOW_VALID__CI__VI = 0x00000019, -SPI_PERF_ES_BUSY__CI__VI = 0x0000001a, -SPI_PERF_HS_WINDOW_VALID__SI = 0x0000001b, -SPI_PERF_ES_CRAWLER_STALL__CI__VI = 0x0000001b, -SPI_PERF_HS_BUSY__SI = 0x0000001c, -SPI_PERF_ES_FIRST_WAVE__CI__VI = 0x0000001c, -SPI_PERF_HS_CRAWLER_STALL__SI = 0x0000001d, -SPI_PERF_ES_LAST_WAVE__CI__VI = 0x0000001d, -SPI_PERF_HS_FIRST_WAVE__SI = 0x0000001e, -SPI_PERF_ES_LSHS_DEALLOC__CI__VI = 0x0000001e, -SPI_PERF_HS_LAST_WAVE__SI = 0x0000001f, -SPI_PERF_ES_EVENT_WAVE__CI__VI = 0x0000001f, -SPI_PERF_HS_LSHS_DEALLOC__SI = 0x00000020, -SPI_PERF_ES_WAVE__CI__VI = 0x00000020, -SPI_PERF_HS_EVENT_WAVE__SI = 0x00000021, -SPI_PERF_ES_PERS_UPD_FULL0__CI__VI = 0x00000021, -SPI_PERF_HS_WAVE__SI = 0x00000022, -SPI_PERF_ES_PERS_UPD_FULL1__CI__VI = 0x00000022, -SPI_PERF_ES_FIRST_SUBGRP__CI__VI = 0x00000023, -SPI_PERF_LS_WINDOW_VALID__SI = 0x00000024, -SPI_PERF_ES_LAST_SUBGRP__CI__VI = 0x00000024, -SPI_PERF_LS_BUSY__SI = 0x00000025, -SPI_PERF_HS_WINDOW_VALID__CI__VI = 0x00000025, -SPI_PERF_LS_CRAWLER_STALL__SI = 0x00000026, -SPI_PERF_HS_BUSY__CI__VI = 0x00000026, -SPI_PERF_LS_FIRST_WAVE__SI = 0x00000027, -SPI_PERF_HS_CRAWLER_STALL__CI__VI = 0x00000027, -SPI_PERF_LS_LAST_WAVE__SI = 0x00000028, -SPI_PERF_HS_FIRST_WAVE__CI__VI = 0x00000028, -SPI_PERF_OFFCHIP_LDS_STALL_LS__SI = 0x00000029, -SPI_PERF_HS_LAST_WAVE__CI__VI = 0x00000029, -SPI_PERF_LS_EVENT_WAVE__SI = 0x0000002a, -SPI_PERF_HS_LSHS_DEALLOC__CI__VI = 0x0000002a, -SPI_PERF_LS_WAVE__SI = 0x0000002b, -SPI_PERF_HS_EVENT_WAVE__CI__VI = 0x0000002b, -SPI_PERF_HS_WAVE__CI__VI = 0x0000002c, -SPI_PERF_HS_PERS_UPD_FULL0__CI__VI = 0x0000002d, -SPI_PERF_HS_PERS_UPD_FULL1__CI__VI = 0x0000002e, -SPI_PERF_LS_WINDOW_VALID__CI__VI = 0x0000002f, -SPI_PERF_LS_BUSY__CI__VI = 0x00000030, -SPI_PERF_LS_CRAWLER_STALL__CI__VI = 0x00000031, -SPI_PERF_LS_FIRST_WAVE__CI__VI = 0x00000032, -SPI_PERF_LS_LAST_WAVE__CI__VI = 0x00000033, -SPI_PERF_OFFCHIP_LDS_STALL_LS__CI__VI = 0x00000034, -SPI_PERF_LS_EVENT_WAVE__CI__VI = 0x00000035, -SPI_PERF_LS_WAVE__CI__VI = 0x00000036, -SPI_PERF_LS_PERS_UPD_FULL0__CI__VI = 0x00000037, -SPI_PERF_LS_PERS_UPD_FULL1__CI__VI = 0x00000038, -SPI_PERF_CSG_WINDOW_VALID__CI__VI = 0x00000039, -SPI_PERF_CSG_BUSY__CI__VI = 0x0000003a, -SPI_PERF_CSG_NUM_THREADGROUPS__CI__VI = 0x0000003b, -SPI_PERF_CSG_CRAWLER_STALL__CI__VI = 0x0000003c, -SPI_PERF_CSG_EVENT_WAVE__CI__VI = 0x0000003d, -SPI_PERF_CSG_WAVE__CI__VI = 0x0000003e, -SPI_PERF_CSN_WINDOW_VALID__CI__VI = 0x0000003f, -SPI_PERF_CSN_BUSY__CI__VI = 0x00000040, -SPI_PERF_CSN_NUM_THREADGROUPS__CI__VI = 0x00000041, -SPI_PERF_PS_CTL_WINDOW_VALID__SI = 0x00000042, -SPI_PERF_CSN_CRAWLER_STALL__CI__VI = 0x00000042, -SPI_PERF_PS_CTL_BUSY__SI = 0x00000043, -SPI_PERF_CSN_EVENT_WAVE__CI__VI = 0x00000043, -SPI_PERF_PS_CTL_ACTIVE__SI = 0x00000044, -SPI_PERF_CSN_WAVE__CI__VI = 0x00000044, -SPI_PERF_PS_CTL_WINDOW_VALID__CI__VI = 0x00000045, -SPI_PERF_PS_CTL_BUSY__CI__VI = 0x00000046, -SPI_PERF_PS_CTL_ACTIVE__CI__VI = 0x00000047, -SPI_PERF_PS_CTL_DEALLOC_BIN0__CI__VI = 0x00000048, -SPI_PERF_PS_CTL_EVENT_WAVE__SI = 0x00000049, -SPI_PERF_PS_CTL_FPOS_BIN1_STALL__CI__VI = 0x00000049, -SPI_PERF_PS_CTL_WAVE__SI = 0x0000004a, -SPI_PERF_PS_CTL_EVENT_WAVE__CI__VI = 0x0000004a, -SPI_PERF_PS_CTL_OPT_WAVE__SI = 0x0000004b, -SPI_PERF_PS_CTL_WAVE__CI__VI = 0x0000004b, -SPI_PERF_PS_CTL_PASS_BIN0__SI = 0x0000004c, -SPI_PERF_PS_CTL_OPT_WAVE__CI__VI = 0x0000004c, -SPI_PERF_PS_CTL_PASS_BIN1__SI = 0x0000004d, -SPI_PERF_PS_CTL_PASS_BIN0__CI__VI = 0x0000004d, -SPI_PERF_PS_CTL_PASS_BIN1__CI__VI = 0x0000004e, -SPI_PERF_PS_CTL_FPOS_BIN2__CI__VI = 0x0000004f, -SPI_PERF_PS_CTL_PRIM_BIN0 = 0x00000050, -SPI_PERF_PS_CTL_PRIM_BIN1 = 0x00000051, -SPI_PERF_PS_CTL_CNF_BIN2 = 0x00000052, -SPI_PERF_PS_CTL_CNF_BIN3 = 0x00000053, -SPI_PERF_PS_CTL_CRAWLER_STALL = 0x00000054, -SPI_PERF_PS_CTL_LDS_RES_FULL = 0x00000055, -SPI_PERF_PS_PERS_UPD_FULL0__CI__VI = 0x00000056, -SPI_PERF_PIX_ALLOC_PEND_CNT__SI = 0x00000057, -SPI_PERF_PS_PERS_UPD_FULL1__CI__VI = 0x00000057, -SPI_PERF_PIX_ALLOC_SCB_STALL__SI = 0x00000058, -SPI_PERF_PIX_ALLOC_PEND_CNT__CI__VI = 0x00000058, -SPI_PERF_PIX_ALLOC_DB0_STALL__SI = 0x00000059, -SPI_PERF_PIX_ALLOC_SCB_STALL__CI__VI = 0x00000059, -SPI_PERF_PIX_ALLOC_DB1_STALL__SI = 0x0000005a, -SPI_PERF_PIX_ALLOC_DB0_STALL__CI__VI = 0x0000005a, -SPI_PERF_PIX_ALLOC_DB1_STALL__CI__VI = 0x0000005b, -SPI_PERF_PIX_ALLOC_DB2_STALL__CI__VI = 0x0000005c, -SPI_PERF_PIX_ALLOC_DB3_STALL__CI__VI = 0x0000005d, -SPI_PERF_RA_TASK_REQ_BIN3__SI = 0x0000005e, -SPI_PERF_LDS0_PC_VALID__CI__VI = 0x0000005e, -SPI_PERF_RA_WR_CTL_FULL__SI = 0x0000005f, -SPI_PERF_LDS1_PC_VALID__CI__VI = 0x0000005f, -SPI_PERF_RA_REQ_NO_ALLOC__SI = 0x00000060, -SPI_PERF_RA_PIPE_REQ_BIN2__CI__VI = 0x00000060, -SPI_PERF_RA_REQ_NO_ALLOC_PS__SI = 0x00000061, -SPI_PERF_RA_TASK_REQ_BIN3__CI__VI = 0x00000061, -SPI_PERF_RA_REQ_NO_ALLOC_VS__SI = 0x00000062, -SPI_PERF_RA_WR_CTL_FULL__CI__VI = 0x00000062, -SPI_PERF_RA_REQ_NO_ALLOC_GS__SI = 0x00000063, -SPI_PERF_RA_REQ_NO_ALLOC__CI__VI = 0x00000063, -SPI_PERF_RA_REQ_NO_ALLOC_ES__SI = 0x00000064, -SPI_PERF_RA_REQ_NO_ALLOC_PS__CI__VI = 0x00000064, -SPI_PERF_RA_REQ_NO_ALLOC_HS__SI = 0x00000065, -SPI_PERF_RA_REQ_NO_ALLOC_VS__CI__VI = 0x00000065, -SPI_PERF_RA_REQ_NO_ALLOC_LS__SI = 0x00000066, -SPI_PERF_RA_REQ_NO_ALLOC_GS__CI__VI = 0x00000066, -SPI_PERF_RA_REQ_NO_ALLOC_ES__CI__VI = 0x00000067, -SPI_PERF_RA_REQ_NO_ALLOC_HS__CI__VI = 0x00000068, -SPI_PERF_RA_REQ_NO_ALLOC_LS__CI__VI = 0x00000069, -SPI_PERF_RA_RES_STALL_PS__SI = 0x0000006a, -SPI_PERF_RA_REQ_NO_ALLOC_CSG__CI__VI = 0x0000006a, -SPI_PERF_RA_RES_STALL_VS__SI = 0x0000006b, -SPI_PERF_RA_REQ_NO_ALLOC_CSN__CI__VI = 0x0000006b, -SPI_PERF_RA_RES_STALL_GS__SI = 0x0000006c, -SPI_PERF_RA_RES_STALL_PS__CI__VI = 0x0000006c, -SPI_PERF_RA_RES_STALL_ES__SI = 0x0000006d, -SPI_PERF_RA_RES_STALL_VS__CI__VI = 0x0000006d, -SPI_PERF_RA_RES_STALL_HS__SI = 0x0000006e, -SPI_PERF_RA_RES_STALL_GS__CI__VI = 0x0000006e, -SPI_PERF_RA_RES_STALL_LS__SI = 0x0000006f, -SPI_PERF_RA_RES_STALL_ES__CI__VI = 0x0000006f, -SPI_PERF_RA_RES_STALL_HS__CI__VI = 0x00000070, -SPI_PERF_RA_RES_STALL_LS__CI__VI = 0x00000071, -SPI_PERF_RA_RES_STALL_CSG__CI__VI = 0x00000072, -SPI_PERF_RA_TMP_STALL_PS__SI = 0x00000073, -SPI_PERF_RA_RES_STALL_CSN__CI__VI = 0x00000073, -SPI_PERF_RA_TMP_STALL_VS__SI = 0x00000074, -SPI_PERF_RA_TMP_STALL_PS__CI__VI = 0x00000074, -SPI_PERF_RA_TMP_STALL_GS__SI = 0x00000075, -SPI_PERF_RA_TMP_STALL_VS__CI__VI = 0x00000075, -SPI_PERF_RA_TMP_STALL_ES__SI = 0x00000076, -SPI_PERF_RA_TMP_STALL_GS__CI__VI = 0x00000076, -SPI_PERF_RA_TMP_STALL_HS__SI = 0x00000077, -SPI_PERF_RA_TMP_STALL_ES__CI__VI = 0x00000077, -SPI_PERF_RA_TMP_STALL_LS__SI = 0x00000078, -SPI_PERF_RA_TMP_STALL_HS__CI__VI = 0x00000078, -SPI_PERF_RA_TMP_STALL_LS__CI__VI = 0x00000079, -SPI_PERF_RA_TMP_STALL_CSG__CI__VI = 0x0000007a, -SPI_PERF_RA_TMP_STALL_CSN__CI__VI = 0x0000007b, -SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x0000007c, -SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x0000007d, -SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x0000007e, -SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x0000007f, -SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x00000080, -SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x00000081, -SPI_PERF_RA_WAVE_SIMD_FULL_CSG__CI__VI = 0x00000082, -SPI_PERF_RA_WAVE_SIMD_FULL_CSN__CI__VI = 0x00000083, -SPI_PERF_RA_VGPR_SIMD_FULL_PS__CI__VI = 0x00000084, -SPI_PERF_RA_VGPR_SIMD_FULL_PS__SI = 0x00000085, -SPI_PERF_RA_VGPR_SIMD_FULL_VS__CI__VI = 0x00000085, -SPI_PERF_RA_VGPR_SIMD_FULL_VS__SI = 0x00000086, -SPI_PERF_RA_VGPR_SIMD_FULL_GS__CI__VI = 0x00000086, -SPI_PERF_RA_VGPR_SIMD_FULL_GS__SI = 0x00000087, -SPI_PERF_RA_VGPR_SIMD_FULL_ES__CI__VI = 0x00000087, -SPI_PERF_RA_VGPR_SIMD_FULL_ES__SI = 0x00000088, -SPI_PERF_RA_VGPR_SIMD_FULL_HS__CI__VI = 0x00000088, -SPI_PERF_RA_VGPR_SIMD_FULL_HS__SI = 0x00000089, -SPI_PERF_RA_VGPR_SIMD_FULL_LS__CI__VI = 0x00000089, -SPI_PERF_RA_VGPR_SIMD_FULL_LS__SI = 0x0000008a, -SPI_PERF_RA_VGPR_SIMD_FULL_CSG__CI__VI = 0x0000008a, -SPI_PERF_RA_VGPR_SIMD_FULL_CSN__CI__VI = 0x0000008b, -SPI_PERF_RA_SGPR_SIMD_FULL_PS__CI__VI = 0x0000008c, -SPI_PERF_RA_SGPR_SIMD_FULL_VS__CI__VI = 0x0000008d, -SPI_PERF_RA_SGPR_SIMD_FULL_PS__SI = 0x0000008e, -SPI_PERF_RA_SGPR_SIMD_FULL_GS__CI__VI = 0x0000008e, -SPI_PERF_RA_SGPR_SIMD_FULL_VS__SI = 0x0000008f, -SPI_PERF_RA_SGPR_SIMD_FULL_ES__CI__VI = 0x0000008f, -SPI_PERF_RA_SGPR_SIMD_FULL_GS__SI = 0x00000090, -SPI_PERF_RA_SGPR_SIMD_FULL_HS__CI__VI = 0x00000090, -SPI_PERF_RA_SGPR_SIMD_FULL_ES__SI = 0x00000091, -SPI_PERF_RA_SGPR_SIMD_FULL_LS__CI__VI = 0x00000091, -SPI_PERF_RA_SGPR_SIMD_FULL_HS__SI = 0x00000092, -SPI_PERF_RA_SGPR_SIMD_FULL_CSG__CI__VI = 0x00000092, -SPI_PERF_RA_SGPR_SIMD_FULL_LS__SI = 0x00000093, -SPI_PERF_RA_SGPR_SIMD_FULL_CSN__CI__VI = 0x00000093, -SPI_PERF_RA_LDS_CU_FULL_PS__CI__VI = 0x00000094, -SPI_PERF_RA_LDS_CU_FULL_LS__CI__VI = 0x00000095, -SPI_PERF_RA_LDS_CU_FULL_ES__CI__VI = 0x00000096, -SPI_PERF_RA_LDS_CU_FULL_PS__SI = 0x00000097, -SPI_PERF_RA_LDS_CU_FULL_CSG__CI__VI = 0x00000097, -SPI_PERF_RA_LDS_CU_FULL_LS__SI = 0x00000098, -SPI_PERF_RA_LDS_CU_FULL_CSN__CI__VI = 0x00000098, -SPI_PERF_RA_BAR_CU_FULL_HS__CI__VI = 0x00000099, -SPI_PERF_RA_BAR_CU_FULL_CSG__CI__VI = 0x0000009a, -SPI_PERF_RA_BAR_CU_FULL_CSN__CI__VI = 0x0000009b, -SPI_PERF_RA_BAR_CU_FULL_HS__SI = 0x0000009c, -SPI_PERF_RA_BULKY_CU_FULL_CSG__CI__VI = 0x0000009c, -SPI_PERF_RA_BULKY_CU_FULL_CSN__CI__VI = 0x0000009d, -SPI_PERF_RA_TGLIM_CU_FULL_CSG__CI__VI = 0x0000009e, -SPI_PERF_RA_TGLIM_CU_FULL_CSN__CI__VI = 0x0000009f, -SPI_PERF_RA_WVLIM_STALL_PS__CI__VI = 0x000000a0, -SPI_PERF_RA_WVLIM_STALL_VS__CI__VI = 0x000000a1, -SPI_PERF_RA_WVLIM_STALL_GS__CI__VI = 0x000000a2, -SPI_PERF_RA_WVLIM_STALL_PS__SI = 0x000000a3, -SPI_PERF_RA_WVLIM_STALL_ES__CI__VI = 0x000000a3, -SPI_PERF_RA_WVLIM_STALL_VS__SI = 0x000000a4, -SPI_PERF_RA_WVLIM_STALL_HS__CI__VI = 0x000000a4, -SPI_PERF_RA_WVLIM_STALL_GS__SI = 0x000000a5, -SPI_PERF_RA_WVLIM_STALL_LS__CI__VI = 0x000000a5, -SPI_PERF_RA_WVLIM_STALL_ES__SI = 0x000000a6, -SPI_PERF_RA_WVLIM_STALL_CSG__CI__VI = 0x000000a6, -SPI_PERF_RA_WVLIM_STALL_HS__SI = 0x000000a7, -SPI_PERF_RA_WVLIM_STALL_CSN__CI__VI = 0x000000a7, -SPI_PERF_RA_WVLIM_STALL_LS__SI = 0x000000a8, -SPI_PERF_RA_PS_LOCK__CI = 0x000000a8, -SPI_PERF_RA_PS_LOCK_NA__VI = 0x000000a8, -SPI_PERF_RA_VS_LOCK__CI__VI = 0x000000a9, -SPI_PERF_RA_GS_LOCK__CI__VI = 0x000000aa, -SPI_PERF_RA_ES_LOCK__CI__VI = 0x000000ab, -SPI_PERF_RA_VS_LOCK__SI = 0x000000ac, -SPI_PERF_RA_HS_LOCK__CI__VI = 0x000000ac, -SPI_PERF_RA_GS_LOCK__SI = 0x000000ad, -SPI_PERF_RA_LS_LOCK__CI__VI = 0x000000ad, -SPI_PERF_RA_ES_LOCK__SI = 0x000000ae, -SPI_PERF_RA_CSG_LOCK__CI__VI = 0x000000ae, -SPI_PERF_RA_HS_LOCK__SI = 0x000000af, -SPI_PERF_RA_CSN_LOCK__CI__VI = 0x000000af, -SPI_PERF_RA_LS_LOCK__SI = 0x000000b0, -SPI_PERF_RA_RSV_UPD__CI__VI = 0x000000b0, -SPI_PERF_EXP_ARB_COL_CNT__CI__VI = 0x000000b1, -SPI_PERF_EXP_ARB_PAR_CNT__CI__VI = 0x000000b2, -SPI_PERF_EXP_ARB_POS_CNT__CI__VI = 0x000000b3, -SPI_PERF_EXP_ARB_COL_CNT__SI = 0x000000b4, -SPI_PERF_EXP_ARB_GDS_CNT__CI__VI = 0x000000b4, -SPI_PERF_EXP_ARB_PAR_CNT__SI = 0x000000b5, -SPI_PERF_CLKGATE_BUSY_STALL__CI__VI = 0x000000b5, -SPI_PERF_EXP_ARB_POS_CNT__SI = 0x000000b6, -SPI_PERF_CLKGATE_ACTIVE_STALL__CI__VI = 0x000000b6, -SPI_PERF_EXP_ARB_GDS_CNT__SI = 0x000000b7, -SPI_PERF_CLKGATE_ALL_CLOCKS_ON__CI__VI = 0x000000b7, -SPI_PERF_CLKGATE_BUSY_STALL__SI = 0x000000b8, -SPI_PERF_CLKGATE_CGTT_DYN_ON__CI__VI = 0x000000b8, -SPI_PERF_CLKGATE_ACTIVE_STALL__SI = 0x000000b9, -SPI_PERF_CLKGATE_CGTT_REG_ON__CI__VI = 0x000000b9, -SPI_PERF_CLKGATE_ALL_CLOCKS_ON__SI = 0x000000ba, -SPI_PERF_NUM_VS_POS_EXPORTS__VI = 0x000000ba, -SPI_PERF_CLKGATE_CGTT_DYN_ON__SI = 0x000000bb, -SPI_PERF_NUM_VS_PARAM_EXPORTS__VI = 0x000000bb, -SPI_PERF_CLKGATE_CGTT_REG_ON__SI = 0x000000bc, -SPI_PERF_NUM_PS_COL_EXPORTS__VI = 0x000000bc, -SPI_PERF_ES_GRP_FIFO_FULL__VI = 0x000000bd, -SPI_PERF_GS_GRP_FIFO_FULL__VI = 0x000000be, -SPI_PERF_HS_GRP_FIFO_FULL__VI = 0x000000bf, -SPI_PERF_LS_GRP_FIFO_FULL__VI = 0x000000c0, -SPI_PERF_VS_ALLOC_CNT__VI = 0x000000c1, -SPI_PERF_VS_LATE_ALLOC_ACCUM__VI = 0x000000c2, -SPI_PERF_PC_ALLOC_CNT__VI = 0x000000c3, -SPI_PERF_PC_ALLOC_ACCUM__VI = 0x000000c4, -} SPI_PERFCNT_SEL; - -typedef enum SPI_PNT_SPRITE_OVERRIDE { -SPI_PNT_SPRITE_SEL_0 = 0x00000000, -SPI_PNT_SPRITE_SEL_1 = 0x00000001, -SPI_PNT_SPRITE_SEL_S = 0x00000002, -SPI_PNT_SPRITE_SEL_T = 0x00000003, -SPI_PNT_SPRITE_SEL_NONE = 0x00000004, -} SPI_PNT_SPRITE_OVERRIDE; - -typedef enum SPI_SAMPLE_CNTL { -CENTROIDS_ONLY = 0x00000000, -CENTERS_ONLY = 0x00000001, -CENTROIDS_AND_CENTERS = 0x00000002, -UNDEF = 0x00000003, -} SPI_SAMPLE_CNTL; - -typedef enum SPI_SHADER_EX_FORMAT { -SPI_SHADER_ZERO = 0x00000000, -SPI_SHADER_32_R = 0x00000001, -SPI_SHADER_32_GR = 0x00000002, -SPI_SHADER_32_AR = 0x00000003, -SPI_SHADER_FP16_ABGR = 0x00000004, -SPI_SHADER_UNORM16_ABGR = 0x00000005, -SPI_SHADER_SNORM16_ABGR = 0x00000006, -SPI_SHADER_UINT16_ABGR = 0x00000007, -SPI_SHADER_SINT16_ABGR = 0x00000008, -SPI_SHADER_32_ABGR = 0x00000009, -} SPI_SHADER_EX_FORMAT; - -typedef enum SPI_SHADER_FORMAT { -SPI_SHADER_NONE = 0x00000000, -SPI_SHADER_1COMP = 0x00000001, -SPI_SHADER_2COMP = 0x00000002, -SPI_SHADER_4COMPRESS = 0x00000003, -SPI_SHADER_4COMP = 0x00000004, -} SPI_SHADER_FORMAT; - -typedef enum SPM_PERFMON_STATE { -STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, -STRM_PERFMON_STATE_START_COUNTING = 0x00000001, -STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002, -STRM_PERFMON_STATE_RESERVED_3 = 0x00000003, -STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, -STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, -} SPM_PERFMON_STATE; - -typedef enum SQC_DATA_CACHE_POLICIES { -SQC_DATA_CACHE_POLICY_HIT_LRU = 0x00000000, -SQC_DATA_CACHE_POLICY_MISS_EVICT = 0x00000001, -} SQC_DATA_CACHE_POLICIES; - -typedef enum SQ_CAC_POWER_SEL { -SQ_CAC_POWER_VALU = 0x00000000, -SQ_CAC_POWER_VALU0 = 0x00000001, -SQ_CAC_POWER_VALU1 = 0x00000002, -SQ_CAC_POWER_VALU2 = 0x00000003, -SQ_CAC_POWER_GPR_RD = 0x00000004, -SQ_CAC_POWER_GPR_WR = 0x00000005, -SQ_CAC_POWER_LDS_BUSY = 0x00000006, -SQ_CAC_POWER_ALU_BUSY = 0x00000007, -SQ_CAC_POWER_TEX_BUSY = 0x00000008, -} SQ_CAC_POWER_SEL; - -typedef enum SQ_DED_INFO_SOURCE { -SQ_DED_INFO_SOURCE_INVALID = 0x00000000, -SQ_DED_INFO_SOURCE_INST = 0x00000001, -SQ_DED_INFO_SOURCE_SGPR = 0x00000002, -SQ_DED_INFO_SOURCE_VGPR = 0x00000003, -SQ_DED_INFO_SOURCE_LDS = 0x00000004, -SQ_DED_INFO_SOURCE_GDS = 0x00000005, -SQ_DED_INFO_SOURCE_TA = 0x00000006, -} SQ_DED_INFO_SOURCE; - -typedef enum SQ_IBUF_ST { -SQ_IBUF_IB_IDLE = 0x00000000, -SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001, -SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002, -SQ_IBUF_IB_LE_4DW = 0x00000003, -SQ_IBUF_IB_WAIT_DRET = 0x00000004, -SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005, -SQ_IBUF_IB_DRET = 0x00000006, -SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007, -} SQ_IBUF_ST; - -typedef enum SQ_IMG_FILTER_TYPE { -SQ_IMG_FILTER_MODE_BLEND = 0x00000000, -SQ_IMG_FILTER_MODE_MIN = 0x00000001, -SQ_IMG_FILTER_MODE_MAX = 0x00000002, -} SQ_IMG_FILTER_TYPE; - -typedef enum SQ_IND_CMD_CMD { -SQ_IND_CMD_CMD_NULL = 0x00000000, -SQ_IND_CMD_CMD_HALT__SI__CI = 0x00000001, -SQ_IND_CMD_CMD_SETHALT__VI = 0x00000001, -SQ_IND_CMD_CMD_RESUME__SI__CI = 0x00000002, -SQ_IND_CMD_CMD_SAVECTX__VI = 0x00000002, -SQ_IND_CMD_CMD_KILL = 0x00000003, -SQ_IND_CMD_CMD_DEBUG = 0x00000004, -SQ_IND_CMD_CMD_TRAP = 0x00000005, -SQ_IND_CMD_CMD_SET_SPI_PRIO__VI = 0x00000006, -} SQ_IND_CMD_CMD; - -typedef enum SQ_IND_CMD_MODE { -SQ_IND_CMD_MODE_SINGLE = 0x00000000, -SQ_IND_CMD_MODE_BROADCAST = 0x00000001, -SQ_IND_CMD_MODE_BROADCAST_QUEUE__CI__VI = 0x00000002, -SQ_IND_CMD_MODE_BROADCAST_PIPE__CI__VI = 0x00000003, -SQ_IND_CMD_MODE_BROADCAST_ME__CI__VI = 0x00000004, -} SQ_IND_CMD_MODE; - -typedef enum SQ_INST_STR_ST { -SQ_INST_STR_IB_WAVE_NORML = 0x00000000, -SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001, -SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002, -SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003, -SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x00000004, -SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x00000005, -SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000006, -SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007, -} SQ_INST_STR_ST; - -typedef enum SQ_INTERRUPT_WORD_ENCODING { -SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x00000000, -SQ_INTERRUPT_WORD_ENCODING_INST = 0x00000001, -SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x00000002, -} SQ_INTERRUPT_WORD_ENCODING; - -typedef enum SQ_PERF_SEL { -SQ_PERF_SEL_NONE = 0x00000000, -SQ_PERF_SEL_ACCUM_PREV = 0x00000001, -SQ_PERF_SEL_CYCLES = 0x00000002, -SQ_PERF_SEL_BUSY_CYCLES = 0x00000003, -SQ_PERF_SEL_WAVES = 0x00000004, -SQ_PERF_SEL_LEVEL_WAVES = 0x00000005, -SQ_PERF_SEL_WAVES_CU__SI = 0x00000006, -SQ_PERF_SEL_WAVES_EQ_64__CI__VI = 0x00000006, -SQ_PERF_SEL_LEVEL_WAVES_CU__SI = 0x00000007, -SQ_PERF_SEL_WAVES_LT_64__CI__VI = 0x00000007, -SQ_PERF_SEL_BUSY_CU_CYCLES__SI = 0x00000008, -SQ_PERF_SEL_WAVES_LT_48__CI__VI = 0x00000008, -SQ_PERF_SEL_ITEMS__SI = 0x00000009, -SQ_PERF_SEL_WAVES_LT_32__CI__VI = 0x00000009, -SQ_PERF_SEL_QUADS__SI = 0x0000000a, -SQ_PERF_SEL_WAVES_LT_16__CI__VI = 0x0000000a, -SQ_PERF_SEL_EVENTS__SI = 0x0000000b, -SQ_PERF_SEL_WAVES_CU__CI__VI = 0x0000000b, -SQ_PERF_SEL_SURF_SYNCS__SI = 0x0000000c, -SQ_PERF_SEL_LEVEL_WAVES_CU__CI__VI = 0x0000000c, -SQ_PERF_SEL_INSTS__SI = 0x0000000d, -SQ_PERF_SEL_BUSY_CU_CYCLES__CI__VI = 0x0000000d, -SQ_PERF_SEL_INSTS_VALU__SI = 0x0000000e, -SQ_PERF_SEL_ITEMS__CI__VI = 0x0000000e, -SQ_PERF_SEL_INSTS_VMEM_WR__SI = 0x0000000f, -SQ_PERF_SEL_QUADS__CI__VI = 0x0000000f, -SQ_PERF_SEL_INSTS_VMEM_RD__SI = 0x00000010, -SQ_PERF_SEL_EVENTS__CI__VI = 0x00000010, -SQ_PERF_SEL_INSTS_VMEM__SI = 0x00000011, -SQ_PERF_SEL_SURF_SYNCS__CI__VI = 0x00000011, -SQ_PERF_SEL_INSTS_SALU__SI = 0x00000012, -SQ_PERF_SEL_TTRACE_REQS__CI__VI = 0x00000012, -SQ_PERF_SEL_INSTS_SMEM__SI = 0x00000013, -SQ_PERF_SEL_TTRACE_INFLIGHT_REQS__CI__VI = 0x00000013, -SQ_PERF_SEL_INSTS_LDS__SI = 0x00000014, -SQ_PERF_SEL_TTRACE_STALL__CI__VI = 0x00000014, -SQ_PERF_SEL_INSTS_GDS__SI = 0x00000015, -SQ_PERF_SEL_MSG_CNTR__CI__VI = 0x00000015, -SQ_PERF_SEL_INSTS_EXP__SI = 0x00000016, -SQ_PERF_SEL_MSG_PERF__CI__VI = 0x00000016, -SQ_PERF_SEL_INSTS_BRANCH__SI = 0x00000017, -SQ_PERF_SEL_MSG_GSCNT__CI__VI = 0x00000017, -SQ_PERF_SEL_INSTS_SENDMSG__SI = 0x00000018, -SQ_PERF_SEL_MSG_INTERRUPT__CI__VI = 0x00000018, -SQ_PERF_SEL_INST_LEVEL_VMEM__SI = 0x00000019, -SQ_PERF_SEL_INSTS__CI__VI = 0x00000019, -SQ_PERF_SEL_INST_LEVEL_SMEM__SI = 0x0000001a, -SQ_PERF_SEL_INSTS_VALU__CI__VI = 0x0000001a, -SQ_PERF_SEL_INST_LEVEL_LDS__SI = 0x0000001b, -SQ_PERF_SEL_INSTS_VMEM_WR__CI__VI = 0x0000001b, -SQ_PERF_SEL_INST_LEVEL_GDS__SI = 0x0000001c, -SQ_PERF_SEL_INSTS_VMEM_RD__CI__VI = 0x0000001c, -SQ_PERF_SEL_INST_LEVEL_EXP__SI = 0x0000001d, -SQ_PERF_SEL_INSTS_VMEM__CI__VI = 0x0000001d, -SQ_PERF_SEL_WAIT_CNT_VM__SI = 0x0000001e, -SQ_PERF_SEL_INSTS_SALU__CI__VI = 0x0000001e, -SQ_PERF_SEL_WAIT_CNT_LGKM__SI = 0x0000001f, -SQ_PERF_SEL_INSTS_SMEM__CI__VI = 0x0000001f, -SQ_PERF_SEL_WAIT_CNT_EXP__SI = 0x00000020, -SQ_PERF_SEL_INSTS_FLAT__CI__VI = 0x00000020, -SQ_PERF_SEL_WAIT_CNT_ANY__SI = 0x00000021, -SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY__CI__VI = 0x00000021, -SQ_PERF_SEL_WAIT_BARRIER__SI = 0x00000022, -SQ_PERF_SEL_INSTS_LDS__CI__VI = 0x00000022, -SQ_PERF_SEL_WAIT_EXP_ALLOC__SI = 0x00000023, -SQ_PERF_SEL_INSTS_GDS__CI__VI = 0x00000023, -SQ_PERF_SEL_WAIT_SLEEP__SI = 0x00000024, -SQ_PERF_SEL_INSTS_EXP__CI__VI = 0x00000024, -SQ_PERF_SEL_WAIT_INST_VMEM__SI = 0x00000025, -SQ_PERF_SEL_INSTS_EXP_GDS__CI__VI = 0x00000025, -SQ_PERF_SEL_WAIT_INST_SCA__SI = 0x00000026, -SQ_PERF_SEL_INSTS_BRANCH__CI__VI = 0x00000026, -SQ_PERF_SEL_WAIT_INST_LDS__SI = 0x00000027, -SQ_PERF_SEL_INSTS_SENDMSG__CI__VI = 0x00000027, -SQ_PERF_SEL_WAIT_INST_VALU__SI = 0x00000028, -SQ_PERF_SEL_INSTS_VSKIPPED__CI__VI = 0x00000028, -SQ_PERF_SEL_WAIT_INST_EXP_GDS__SI = 0x00000029, -SQ_PERF_SEL_INST_LEVEL_VMEM__CI__VI = 0x00000029, -SQ_PERF_SEL_WAIT_INST_MISC__SI = 0x0000002a, -SQ_PERF_SEL_INST_LEVEL_SMEM__CI__VI = 0x0000002a, -SQ_PERF_SEL_INST_CYCLES_VMEM_WR__SI = 0x0000002b, -SQ_PERF_SEL_INST_LEVEL_LDS__CI__VI = 0x0000002b, -SQ_PERF_SEL_INST_CYCLES_VMEM_RD__SI = 0x0000002c, -SQ_PERF_SEL_INST_LEVEL_GDS__CI__VI = 0x0000002c, -SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR__SI = 0x0000002d, -SQ_PERF_SEL_INST_LEVEL_EXP__CI__VI = 0x0000002d, -SQ_PERF_SEL_INST_CYCLES_VMEM_DATA__SI = 0x0000002e, -SQ_PERF_SEL_WAVE_CYCLES__CI__VI = 0x0000002e, -SQ_PERF_SEL_INST_CYCLES_VMEM_CMD__SI = 0x0000002f, -SQ_PERF_SEL_WAVE_READY__CI__VI = 0x0000002f, -SQ_PERF_SEL_INST_CYCLES_VMEM__SI = 0x00000030, -SQ_PERF_SEL_WAIT_CNT_VM__CI__VI = 0x00000030, -SQ_PERF_SEL_INST_CYCLES_LDS__SI = 0x00000031, -SQ_PERF_SEL_WAIT_CNT_LGKM__CI__VI = 0x00000031, -SQ_PERF_SEL_INST_CYCLES_VALU__SI = 0x00000032, -SQ_PERF_SEL_WAIT_CNT_EXP__CI__VI = 0x00000032, -SQ_PERF_SEL_INST_CYCLES_EXP__SI = 0x00000033, -SQ_PERF_SEL_WAIT_CNT_ANY__CI__VI = 0x00000033, -SQ_PERF_SEL_INST_CYCLES_GDS__SI = 0x00000034, -SQ_PERF_SEL_WAIT_BARRIER__CI__VI = 0x00000034, -SQ_PERF_SEL_INST_CYCLES_SCA__SI = 0x00000035, -SQ_PERF_SEL_WAIT_EXP_ALLOC__CI__VI = 0x00000035, -SQ_PERF_SEL_INST_CYCLES_SMEM__SI = 0x00000036, -SQ_PERF_SEL_WAIT_SLEEP__CI__VI = 0x00000036, -SQ_PERF_SEL_INST_CYCLES_SALU__SI = 0x00000037, -SQ_PERF_SEL_WAIT_OTHER__CI__VI = 0x00000037, -SQ_PERF_SEL_INST_CYCLES_EXP_GDS__SI = 0x00000038, -SQ_PERF_SEL_WAIT_ANY__CI__VI = 0x00000038, -SQ_PERF_SEL_INST_CYCLES_MISC__SI = 0x00000039, -SQ_PERF_SEL_WAIT_TTRACE__CI__VI = 0x00000039, -SQ_PERF_SEL_THREAD_CYCLES_VALU__SI = 0x0000003a, -SQ_PERF_SEL_WAIT_IFETCH__CI__VI = 0x0000003a, -SQ_PERF_SEL_WAIT_INST_VMEM__CI__VI = 0x0000003b, -SQ_PERF_SEL_VALU_LDS_DIRECT_RD__SI = 0x0000003c, -SQ_PERF_SEL_WAIT_INST_SCA__CI__VI = 0x0000003c, -SQ_PERF_SEL_VALU_LDS_INTERP_OP__SI = 0x0000003d, -SQ_PERF_SEL_WAIT_INST_LDS__CI__VI = 0x0000003d, -SQ_PERF_SEL_LDS_BANK_CONFLICT__SI = 0x0000003e, -SQ_PERF_SEL_WAIT_INST_VALU__CI__VI = 0x0000003e, -SQ_PERF_SEL_LDS_ADDR_CONFLICT__SI = 0x0000003f, -SQ_PERF_SEL_WAIT_INST_EXP_GDS__CI__VI = 0x0000003f, -SQ_PERF_SEL_VALU_DEP_STALL__SI = 0x00000040, -SQ_PERF_SEL_WAIT_INST_MISC__CI__VI = 0x00000040, -SQ_PERF_SEL_EXP_REQ_FIFO_FULL__SI = 0x00000041, -SQ_PERF_SEL_WAIT_INST_FLAT__CI__VI = 0x00000041, -SQ_PERF_SEL_LDS_BACK2BACK_STALL__SI = 0x00000042, -SQ_PERF_SEL_ACTIVE_INST_ANY__CI__VI = 0x00000042, -SQ_PERF_SEL_LDS_DATA_FIFO_FULL__SI = 0x00000043, -SQ_PERF_SEL_ACTIVE_INST_VMEM__CI__VI = 0x00000043, -SQ_PERF_SEL_LDS_CMD_FIFO_FULL__SI = 0x00000044, -SQ_PERF_SEL_ACTIVE_INST_LDS__CI__VI = 0x00000044, -SQ_PERF_SEL_VMEM_BACK2BACK_STALL__SI = 0x00000045, -SQ_PERF_SEL_ACTIVE_INST_VALU__CI__VI = 0x00000045, -SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL__SI = 0x00000046, -SQ_PERF_SEL_ACTIVE_INST_SCA__CI__VI = 0x00000046, -SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL__SI = 0x00000047, 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-SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB__CI__VI = 0x000000a9, -SQC_PERF_SEL_ICACHE_INPUT_VALIDB__CI__VI = 0x000000aa, -SQC_PERF_SEL_DCACHE_INPUT_VALID_READY__CI__VI = 0x000000ab, -SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB__CI__VI = 0x000000ac, -SQC_PERF_SEL_DCACHE_INPUT_VALIDB__CI__VI = 0x000000ad, -SQC_PERF_SEL_TC_REQ__CI__VI = 0x000000ae, -SQC_PERF_SEL_TC_INST_REQ__CI__VI = 0x000000af, -SQC_PERF_SEL_TC_DATA_REQ__CI = 0x000000b0, -SQC_PERF_SEL_TC_DATA_READ_REQ__VI = 0x000000b0, -SQC_PERF_SEL_TC_STALL__CI = 0x000000b1, -SQC_PERF_SEL_TC_DATA_WRITE_REQ__VI = 0x000000b1, -SQC_PERF_SEL_TC_STARVE__CI = 0x000000b2, -SQC_PERF_SEL_TC_DATA_ATOMIC_REQ__VI = 0x000000b2, -SQC_PERF_SEL_ICACHE_BUSY_CYCLES__CI = 0x000000b3, -SQC_PERF_SEL_TC_STALL__VI = 0x000000b3, -SQC_PERF_SEL_ICACHE_REQ__CI = 0x000000b4, -SQC_PERF_SEL_TC_STARVE__VI = 0x000000b4, -SQC_PERF_SEL_ICACHE_HITS__CI = 0x000000b5, -SQC_PERF_SEL_ICACHE_BUSY_CYCLES__VI = 0x000000b5, -SQC_PERF_SEL_ICACHE_HITS__SI = 0x000000b6, -SQC_PERF_SEL_ICACHE_MISSES__CI = 0x000000b6, -SQC_PERF_SEL_ICACHE_REQ__VI = 0x000000b6, -SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE__CI = 0x000000b7, -SQC_PERF_SEL_ICACHE_HITS__VI = 0x000000b7, -SQC_PERF_SEL_ICACHE_UNCACHED__CI = 0x000000b8, -SQC_PERF_SEL_ICACHE_MISSES__VI = 0x000000b8, -SQC_PERF_SEL_ICACHE_VOLATILE__CI = 0x000000b9, -SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE__VI = 0x000000b9, -SQC_PERF_SEL_ICACHE_INVAL_INST__CI__VI = 0x000000ba, -SQC_PERF_SEL_ICACHE_INVAL_ASYNC__CI__VI = 0x000000bb, -SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_INST__CI = 0x000000bc, -SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT__VI = 0x000000bc, -SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_ASYNC__CI = 0x000000bd, -SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB__VI = 0x000000bd, -SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT__CI = 0x000000be, -SQC_PERF_SEL_ICACHE_CACHE_STALLED__VI = 0x000000be, -SQC_PERF_SEL_ICACHE_MISSES__SI = 0x000000bf, -SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB__CI = 0x000000bf, -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO__VI = 0x000000bf, -SQC_PERF_SEL_ICACHE_CACHE_STALLED__CI = 0x000000c0, -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX__VI = 0x000000c0, -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO__CI = 0x000000c1, -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT__VI = 0x000000c1, -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX__CI = 0x000000c2, -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO__VI = 0x000000c2, -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO__VI = 0x000000c3, -SQC_PERF_SEL_ICACHE_CACHE_STALL_UNCACHED_HIT__CI = 0x000000c4, -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF__VI = 0x000000c4, -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT__CI = 0x000000c5, -SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT__VI = 0x000000c5, -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO__CI = 0x000000c6, -SQC_PERF_SEL_DCACHE_BUSY_CYCLES__VI = 0x000000c6, -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO__CI = 0x000000c7, -SQC_PERF_SEL_DCACHE_REQ__VI = 0x000000c7, -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF__CI = 0x000000c8, -SQC_PERF_SEL_DCACHE_HITS__VI = 0x000000c8, -SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT__CI = 0x000000c9, -SQC_PERF_SEL_DCACHE_MISSES__VI = 0x000000c9, -SQC_PERF_SEL_DCACHE_BUSY_CYCLES__CI = 0x000000ca, -SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE__VI = 0x000000ca, -SQC_PERF_SEL_DCACHE_REQ__CI = 0x000000cb, -SQC_PERF_SEL_DCACHE_HIT_LRU_READ__VI = 0x000000cb, -SQC_PERF_SEL_DCACHE_HITS__CI = 0x000000cc, -SQC_PERF_SEL_DCACHE_MISS_EVICT_READ__VI = 0x000000cc, -SQC_PERF_SEL_DCACHE_MISSES__CI = 0x000000cd, -SQC_PERF_SEL_DCACHE_WC_LRU_WRITE__VI = 0x000000cd, -SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE__CI = 0x000000ce, -SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE__VI = 0x000000ce, -SQC_PERF_SEL_DCACHE_UNCACHED__CI = 0x000000cf, -SQC_PERF_SEL_DCACHE_ATOMIC__VI = 0x000000cf, -SQC_PERF_SEL_DCACHE_VOLATILE__CI__VI = 0x000000d0, -SQC_PERF_SEL_DCACHE_INVAL_INST__CI__VI = 0x000000d1, -SQC_PERF_SEL_DCACHE_INVAL_ASYNC__CI__VI = 0x000000d2, -SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST__CI__VI = 0x000000d3, -SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC__CI__VI = 0x000000d4, -SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT__CI = 0x000000d5, -SQC_PERF_SEL_DCACHE_WB_INST__VI = 0x000000d5, -SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB__CI = 0x000000d6, -SQC_PERF_SEL_DCACHE_WB_ASYNC__VI = 0x000000d6, -SQC_PERF_SEL_DCACHE_CACHE_STALLED__CI = 0x000000d7, -SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST__VI = 0x000000d7, -SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO__CI = 0x000000d8, -SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC__VI = 0x000000d8, -SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX__CI = 0x000000d9, -SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT__VI = 0x000000d9, -SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB__VI = 0x000000da, -SQC_PERF_SEL_DCACHE_CACHE_STALL_UNCACHED_HIT__CI = 0x000000db, -SQC_PERF_SEL_DCACHE_CACHE_STALLED__VI = 0x000000db, -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT__CI = 0x000000dc, -SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX__VI = 0x000000dc, -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO__CI = 0x000000dd, -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT__VI = 0x000000dd, -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO__CI = 0x000000de, -SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT__VI = 0x000000de, -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF__CI = 0x000000df, -SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED__VI = 0x000000df, -SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT__CI = 0x000000e0, -SQC_PERF_SEL_DCACHE_REQ_1__CI = 0x000000e1, -SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT__VI = 0x000000e1, -SQC_PERF_SEL_DCACHE_REQ_2__CI = 0x000000e2, -SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH__VI = 0x000000e2, -SQC_PERF_SEL_DCACHE_REQ_4__CI = 0x000000e3, -SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE__VI = 0x000000e3, -SQC_PERF_SEL_DCACHE_REQ_8__CI = 0x000000e4, -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO__VI = 0x000000e4, -SQC_PERF_SEL_DCACHE_REQ_16__CI = 0x000000e5, -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO__VI = 0x000000e5, -SQC_PERF_SEL_DCACHE_REQ_TIME__CI = 0x000000e6, -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF__VI = 0x000000e6, -SQC_PERF_SEL_SQ_DCACHE_REQS__CI = 0x000000e7, -SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT__VI = 0x000000e7, -SQC_PERF_SEL_DCACHE_FLAT_REQ__CI = 0x000000e8, -SQC_PERF_SEL_DCACHE_REQ_READ_1__VI = 0x000000e8, -SQC_PERF_SEL_DCACHE_NONFLAT_REQ__CI = 0x000000e9, -SQC_PERF_SEL_DCACHE_REQ_READ_2__VI = 0x000000e9, -SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL__CI = 0x000000ea, -SQC_PERF_SEL_DCACHE_REQ_READ_4__VI = 0x000000ea, -SQC_PERF_SEL_ICACHE_PRE_CC_LEVEL__CI = 0x000000eb, -SQC_PERF_SEL_DCACHE_REQ_READ_8__VI = 0x000000eb, -SQC_PERF_SEL_ICACHE_POST_CC_LEVEL__CI = 0x000000ec, -SQC_PERF_SEL_DCACHE_REQ_READ_16__VI = 0x000000ec, -SQC_PERF_SEL_ICACHE_POST_CC_HIT_LEVEL__CI = 0x000000ed, -SQC_PERF_SEL_DCACHE_REQ_TIME__VI = 0x000000ed, -SQC_PERF_SEL_ICACHE_POST_CC_MISS_LEVEL__CI = 0x000000ee, -SQC_PERF_SEL_DCACHE_REQ_WRITE_1__VI = 0x000000ee, -SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL__CI = 0x000000ef, -SQC_PERF_SEL_DCACHE_REQ_WRITE_2__VI = 0x000000ef, -SQC_PERF_SEL_DCACHE_PRE_CC_LEVEL__CI = 0x000000f0, -SQC_PERF_SEL_DCACHE_REQ_WRITE_4__VI = 0x000000f0, -SQC_PERF_SEL_DCACHE_POST_CC_LEVEL__CI = 0x000000f1, -SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE__VI = 0x000000f1, -SQC_PERF_SEL_DCACHE_POST_CC_HIT_LEVEL__CI = 0x000000f2, -SQC_PERF_SEL_SQ_DCACHE_REQS__VI = 0x000000f2, -SQC_PERF_SEL_DCACHE_POST_CC_MISS_LEVEL__CI = 0x000000f3, -SQC_PERF_SEL_DCACHE_FLAT_REQ__VI = 0x000000f3, -SQC_PERF_SEL_TC_INFLIGHT_LEVEL__CI = 0x000000f4, -SQC_PERF_SEL_DCACHE_NONFLAT_REQ__VI = 0x000000f4, -SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL__CI = 0x000000f5, -SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL__VI = 0x000000f5, -SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL__CI = 0x000000f6, -SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL__VI = 0x000000f6, -SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED__CI = 0x000000f7, -SQC_PERF_SEL_TC_INFLIGHT_LEVEL__VI = 0x000000f7, -SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED__CI = 0x000000f8, -SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL__VI = 0x000000f8, -SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED__CI = 0x000000f9, -SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL__VI = 0x000000f9, -SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS__VI = 0x000000fa, -SQC_PERF_SEL_DUMMY_LAST__CI = 0x000000fb, -SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS__VI = 0x000000fb, -SQC_PERF_SEL_ICACHE_GATCL1_REQUEST__VI = 0x000000fc, -SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX__VI = 0x000000fd, -SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT__VI = 0x000000fe, -SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL__VI = 0x000000ff, -SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES__VI = 0x00000100, -SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT__VI = 0x00000102, -SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL__VI = 0x00000103, -SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS__VI = 0x00000104, -SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS__VI = 0x00000105, -SQC_PERF_SEL_DCACHE_GATCL1_REQUEST__VI = 0x00000106, -SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX__VI = 0x00000107, -SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT__VI = 0x00000108, -SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL__VI = 0x00000109, -SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES__VI = 0x0000010a, -SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT__VI = 0x0000010c, -SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL__VI = 0x0000010d, -SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS__VI = 0x0000010e, -SQC_PERF_SEL_DCACHE_BUSY_CYCLES__SI = 0x0000010f, -SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL__VI = 0x0000010f, -SQC_PERF_SEL_DUMMY_LAST__VI = 0x00000110, -SQC_PERF_SEL_DCACHE_REQ__SI = 0x00000111, -SQ_PERF_SEL_INSTS_SMEM_NORM__VI = 0x00000111, -SQ_PERF_SEL_ATC_INSTS_VMEM__VI = 0x00000112, -SQ_PERF_SEL_ATC_INST_LEVEL_VMEM__VI = 0x00000113, -SQ_PERF_SEL_ATC_XNACK_FIRST__VI = 0x00000114, -SQ_PERF_SEL_ATC_XNACK_ALL__VI = 0x00000115, -SQ_PERF_SEL_ATC_XNACK_FIFO_FULL__VI = 0x00000116, -SQ_PERF_SEL_ATC_INSTS_SMEM__VI = 0x00000117, -SQ_PERF_SEL_ATC_INST_LEVEL_SMEM__VI = 0x00000118, -SQ_PERF_SEL_IFETCH_XNACK__VI = 0x00000119, -SQ_PERF_SEL_TLB_SHOOTDOWN__VI = 0x0000011a, -SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES__VI = 0x0000011b, -SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY__VI = 0x0000011c, -SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY__VI = 0x0000011d, -SQ_PERF_SEL_INSTS_VMEM_REPLAY__VI = 0x0000011e, -SQ_PERF_SEL_INSTS_SMEM_REPLAY__VI = 0x0000011f, -SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY__VI = 0x00000120, -SQ_PERF_SEL_INSTS_FLAT_REPLAY__VI = 0x00000121, -SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY__VI = 0x00000122, -SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY__VI = 0x00000123, -SQC_PERF_SEL_DCACHE_REQ_1__SI = 0x0000012a, -SQ_PERF_SEL_DUMMY_LAST1__VI = 0x0000012a, -SQC_PERF_SEL_DCACHE_REQ_2__SI = 0x0000012b, -SQC_PERF_SEL_DCACHE_REQ_4__SI = 0x0000012c, -SQC_PERF_SEL_DCACHE_REQ_8__SI = 0x0000012d, -SQC_PERF_SEL_DCACHE_REQ_16__SI = 0x0000012e, -SQC_PERF_SEL_DCACHE_REQ_TIME__SI = 0x0000012f, -SQC_PERF_SEL_DCACHE_HITS__SI = 0x00000130, -SQC_PERF_SEL_DCACHE_MISSES__SI = 0x00000139, -SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED__SI = 0x00000189, -SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED__SI = 0x0000018a, -SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED__SI = 0x0000018b, -} SQ_PERF_SEL; - -typedef enum SQ_ROUND_MODE { -SQ_ROUND_NEAREST_EVEN = 0x00000000, -SQ_ROUND_PLUS_INFINITY = 0x00000001, -SQ_ROUND_MINUS_INFINITY = 0x00000002, -SQ_ROUND_TO_ZERO = 0x00000003, -} SQ_ROUND_MODE; - -typedef enum SQ_RSRC_BUF_TYPE { -SQ_RSRC_BUF = 0x00000000, -SQ_RSRC_BUF_RSVD_1 = 0x00000001, -SQ_RSRC_BUF_RSVD_2 = 0x00000002, -SQ_RSRC_BUF_RSVD_3 = 0x00000003, -} SQ_RSRC_BUF_TYPE; - -typedef enum SQ_RSRC_FLAT_TYPE { -SQ_RSRC_FLAT_RSVD_0 = 0x00000000, -SQ_RSRC_FLAT = 0x00000001, -SQ_RSRC_FLAT_RSVD_2 = 0x00000002, -SQ_RSRC_FLAT_RSVD_3 = 0x00000003, -} SQ_RSRC_FLAT_TYPE; - -typedef enum SQ_RSRC_IMG_TYPE { -SQ_RSRC_IMG_RSVD_0 = 0x00000000, -SQ_RSRC_IMG_RSVD_1 = 0x00000001, -SQ_RSRC_IMG_RSVD_2 = 0x00000002, -SQ_RSRC_IMG_RSVD_3 = 0x00000003, -SQ_RSRC_IMG_RSVD_4 = 0x00000004, -SQ_RSRC_IMG_RSVD_5 = 0x00000005, -SQ_RSRC_IMG_RSVD_6 = 0x00000006, -SQ_RSRC_IMG_RSVD_7 = 0x00000007, -SQ_RSRC_IMG_1D = 0x00000008, -SQ_RSRC_IMG_2D = 0x00000009, -SQ_RSRC_IMG_3D = 0x0000000a, -SQ_RSRC_IMG_CUBE = 0x0000000b, -SQ_RSRC_IMG_1D_ARRAY = 0x0000000c, -SQ_RSRC_IMG_2D_ARRAY = 0x0000000d, -SQ_RSRC_IMG_2D_MSAA = 0x0000000e, -SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f, -} SQ_RSRC_IMG_TYPE; - -typedef enum SQ_SEL_XYZW01 { -SQ_SEL_0 = 0x00000000, -SQ_SEL_1 = 0x00000001, -SQ_SEL_RESERVED_0 = 0x00000002, -SQ_SEL_RESERVED_1 = 0x00000003, -SQ_SEL_X = 0x00000004, -SQ_SEL_Y = 0x00000005, -SQ_SEL_Z = 0x00000006, -SQ_SEL_W = 0x00000007, -} SQ_SEL_XYZW01; - -typedef enum SQ_TEX_ANISO_RATIO { -SQ_TEX_ANISO_RATIO_1 = 0x00000000, -SQ_TEX_ANISO_RATIO_2 = 0x00000001, -SQ_TEX_ANISO_RATIO_4 = 0x00000002, -SQ_TEX_ANISO_RATIO_8 = 0x00000003, -SQ_TEX_ANISO_RATIO_16 = 0x00000004, -} SQ_TEX_ANISO_RATIO; - -typedef enum SQ_TEX_BORDER_COLOR { -SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000, -SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001, -SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002, -SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003, -} SQ_TEX_BORDER_COLOR; - -typedef enum SQ_TEX_CLAMP { -SQ_TEX_WRAP = 0x00000000, -SQ_TEX_MIRROR = 0x00000001, -SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002, -SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003, -SQ_TEX_CLAMP_HALF_BORDER = 0x00000004, -SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005, -SQ_TEX_CLAMP_BORDER = 0x00000006, -SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007, -} SQ_TEX_CLAMP; - -typedef enum SQ_TEX_DEPTH_COMPARE { -SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000, -SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001, -SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002, -SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003, -SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004, -SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005, -SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006, -SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007, -} SQ_TEX_DEPTH_COMPARE; - -typedef enum SQ_TEX_MIP_FILTER { -SQ_TEX_MIP_FILTER_NONE = 0x00000000, -SQ_TEX_MIP_FILTER_POINT = 0x00000001, -SQ_TEX_MIP_FILTER_LINEAR = 0x00000002, -SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ__VI = 0x00000003, -} SQ_TEX_MIP_FILTER; - -typedef enum SQ_TEX_XY_FILTER { -SQ_TEX_XY_FILTER_POINT = 0x00000000, -SQ_TEX_XY_FILTER_BILINEAR = 0x00000001, -SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002, -SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003, -} SQ_TEX_XY_FILTER; - -typedef enum SQ_TEX_Z_FILTER { -SQ_TEX_Z_FILTER_NONE = 0x00000000, -SQ_TEX_Z_FILTER_POINT = 0x00000001, -SQ_TEX_Z_FILTER_LINEAR = 0x00000002, -} SQ_TEX_Z_FILTER; - -typedef enum SQ_THREAD_TRACE_CAPTURE_MODE { -SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x00000000, -SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x00000001, -SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x00000002, -} SQ_THREAD_TRACE_CAPTURE_MODE; - -typedef enum SQ_THREAD_TRACE_INST_TYPE { -SQ_THREAD_TRACE_INST_TYPE_SMEM__SI__CI = 0x00000000, -SQ_THREAD_TRACE_INST_TYPE_SMEM_RD__VI = 0x00000000, -SQ_THREAD_TRACE_INST_TYPE_SALU__SI__CI = 0x00000001, -SQ_THREAD_TRACE_INST_TYPE_SALU_32__VI = 0x00000001, -SQ_THREAD_TRACE_INST_TYPE_VMEM_RD__CI__VI = 0x00000002, -SQ_THREAD_TRACE_INST_TYPE_VMEM_WR__CI__VI = 0x00000003, -SQ_THREAD_TRACE_INST_TYPE_FLAT_WR__CI__VI = 0x00000004, -SQ_THREAD_TRACE_INST_TYPE_VALU__SI__CI = 0x00000005, -SQ_THREAD_TRACE_INST_TYPE_VALU_32__VI = 0x00000005, -SQ_THREAD_TRACE_INST_TYPE_LDS = 0x00000006, -SQ_THREAD_TRACE_INST_TYPE_PC = 0x00000007, -SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x00000008, -SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x00000009, -SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0x0000000a, -SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0x0000000b, -SQ_THREAD_TRACE_INST_TYPE_JUMP = 0x0000000c, -SQ_THREAD_TRACE_INST_TYPE_NEXT = 0x0000000d, -SQ_THREAD_TRACE_INST_TYPE_FLAT_RD__CI__VI = 0x0000000e, -SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0x0000000f, -SQ_THREAD_TRACE_INST_TYPE_SMEM_WR__VI = 0x00000010, -SQ_THREAD_TRACE_INST_TYPE_SALU_64__VI = 0x00000011, -SQ_THREAD_TRACE_INST_TYPE_VALU_64__VI = 0x00000012, -SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY__VI = 0x00000013, -SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY__VI = 0x00000014, -SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY__VI = 0x00000015, -SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY__VI = 0x00000016, -SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY__VI = 0x00000017, -SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY__VI = 0x00000018, -} SQ_THREAD_TRACE_INST_TYPE; - -typedef enum SQ_THREAD_TRACE_ISSUE { -SQ_THREAD_TRACE_ISSUE_NULL = 0x00000000, -SQ_THREAD_TRACE_ISSUE_STALL = 0x00000001, -SQ_THREAD_TRACE_ISSUE_INST = 0x00000002, -SQ_THREAD_TRACE_ISSUE_IMMED = 0x00000003, -} SQ_THREAD_TRACE_ISSUE; - -typedef enum SQ_THREAD_TRACE_ISSUE_MASK { -SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x00000000, -SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x00000001, -SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x00000002, -SQ_THREAD_TRACE_ISSUE_MASK_IMMED__CI__VI = 0x00000003, -} SQ_THREAD_TRACE_ISSUE_MASK; - -typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE { -SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC__SI = 0x00000000, -SQ_THREAD_TRACE_MISC_TOKEN_TIME__CI__VI = 0x00000000, -SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN__SI = 0x00000001, -SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET__CI__VI = 0x00000001, -SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END__SI = 0x00000002, -SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST__CI__VI = 0x00000002, -SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC__CI__VI = 0x00000003, -SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN__CI__VI = 0x00000004, -SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END__CI__VI = 0x00000005, -SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX__VI = 0x00000006, -SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN__VI = 0x00000007, -} SQ_THREAD_TRACE_MISC_TOKEN_TYPE; - -typedef enum SQ_THREAD_TRACE_MODE_SEL { -SQ_THREAD_TRACE_MODE_OFF = 0x00000000, -SQ_THREAD_TRACE_MODE_ON = 0x00000001, -SQ_THREAD_TRACE_MODE_RANDOM__SI__CI = 0x00000002, -} SQ_THREAD_TRACE_MODE_SEL; - -typedef enum SQ_THREAD_TRACE_REG_OP { -SQ_THREAD_TRACE_REG_OP_READ = 0x00000000, -SQ_THREAD_TRACE_REG_OP_WRITE = 0x00000001, -} SQ_THREAD_TRACE_REG_OP; - -typedef enum SQ_THREAD_TRACE_REG_TYPE { -SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x00000000, -SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x00000001, -SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x00000002, -SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x00000003, -SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x00000004, -SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x00000005, -SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x00000006, -SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x00000007, -} SQ_THREAD_TRACE_REG_TYPE; - -typedef enum SQ_THREAD_TRACE_TOKEN_TYPE { -SQ_THREAD_TRACE_TOKEN_MISC__CI__VI = 0x00000000, -SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x00000001, -SQ_THREAD_TRACE_TOKEN_REG = 0x00000002, -SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x00000003, -SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC__CI__VI = 0x00000004, -SQ_THREAD_TRACE_TOKEN_REG_CSPRIV__CI__VI = 0x00000005, -SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x00000006, -SQ_THREAD_TRACE_TOKEN_EVENT = 0x00000007, -SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x00000008, -SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x00000009, -SQ_THREAD_TRACE_TOKEN_INST = 0x0000000a, -SQ_THREAD_TRACE_TOKEN_INST_PC = 0x0000000b, -SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0x0000000c, -SQ_THREAD_TRACE_TOKEN_ISSUE = 0x0000000d, -SQ_THREAD_TRACE_TOKEN_PERF = 0x0000000e, -SQ_THREAD_TRACE_TOKEN_MISC__SI = 0x0000000f, -SQ_THREAD_TRACE_TOKEN_REG_CS__CI__VI = 0x0000000f, -} SQ_THREAD_TRACE_TOKEN_TYPE; - -typedef enum SQ_THREAD_TRACE_VM_ID_MASK { -SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x00000000, -SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x00000001, -SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x00000002, -} SQ_THREAD_TRACE_VM_ID_MASK; - -typedef enum SQ_THREAD_TRACE_WAVE_MASK { -SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x00000000, -SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x00000001, -SQ_THREAD_TRACE_WAVE_MASK_1_2__SI__CI = 0x00000002, -SQ_THREAD_TRACE_WAVE_MASK_1_4__SI__CI = 0x00000003, -SQ_THREAD_TRACE_WAVE_MASK_1_8__SI__CI = 0x00000004, -SQ_THREAD_TRACE_WAVE_MASK_1_16__SI__CI = 0x00000005, -SQ_THREAD_TRACE_WAVE_MASK_1_32__SI__CI = 0x00000006, -SQ_THREAD_TRACE_WAVE_MASK_1_64__SI__CI = 0x00000007, -} SQ_THREAD_TRACE_WAVE_MASK; - -typedef enum SQ_WAVE_IB_ECC_ST { -SQ_WAVE_IB_ECC_CLEAN = 0x00000000, -SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001, -SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002, -SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003, -} SQ_WAVE_IB_ECC_ST; - -typedef enum SQ_WAVE_TYPE { -SQ_WAVE_TYPE_PS = 0x00000000, -SQ_WAVE_TYPE_VS = 0x00000001, -SQ_WAVE_TYPE_GS = 0x00000002, -SQ_WAVE_TYPE_ES = 0x00000003, -SQ_WAVE_TYPE_HS = 0x00000004, -SQ_WAVE_TYPE_LS = 0x00000005, -SQ_WAVE_TYPE_CS = 0x00000006, -SQ_WAVE_TYPE_PS1 = 0x00000007, -} SQ_WAVE_TYPE; - -typedef enum SRBM_PERFCOUNT1_SEL { -SRBM_PERF_SEL_COUNT = 0x00000000, -SRBM_PERF_SEL_BIF_BUSY = 0x00000001, -SRBM_PERF_SEL_SDMA0_BUSY__CI__VI = 0x00000003, -SRBM_PERF_SEL_IH_BUSY = 0x00000004, -SRBM_PERF_SEL_MCB_BUSY = 0x00000005, -SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x00000006, -SRBM_PERF_SEL_MCC_BUSY = 0x00000007, -SRBM_PERF_SEL_MCD_BUSY = 0x00000008, -SRBM_PERF_SEL_CHUB_BUSY__CI__VI = 0x00000009, -SRBM_PERF_SEL_SEM_BUSY = 0x0000000a, -SRBM_PERF_SEL_UVD_BUSY = 0x0000000b, -SRBM_PERF_SEL_VMC_BUSY = 0x0000000c, -SRBM_PERF_SEL_XSP_BUSY__SI__CI = 0x0000000d, -SRBM_PERF_SEL_ODE_BUSY__VI = 0x0000000d, -SRBM_PERF_SEL_SDMA1_BUSY__CI__VI = 0x0000000e, -SRBM_PERF_SEL_SAMMSP_BUSY__VI = 0x0000000f, -SRBM_PERF_SEL_VCE0_BUSY__VI = 0x00000010, -SRBM_PERF_SEL_XDMA_BUSY = 0x00000011, -SRBM_PERF_SEL_ACP_BUSY__CI__VI = 0x00000012, -SRBM_PERF_SEL_SDMA2_BUSY__VI = 0x00000013, -SRBM_PERF_SEL_SDMA3_BUSY__VI = 0x00000014, -SRBM_PERF_SEL_SAMSCP_BUSY__VI = 0x00000015, -SRBM_PERF_SEL_VMC1_BUSY__VI = 0x00000016, -SRBM_PERF_SEL_ISP_BUSY__VI = 0x00000017, -SRBM_PERF_SEL_VCE1_BUSY__VI = 0x00000018, -SRBM_PERF_SEL_GCATCL2_BUSY__VI = 0x00000019, -SRBM_PERF_SEL_OSATCL2_BUSY__VI = 0x0000001a, -SRBM_PERF_SEL_VP8_BUSY__VI = 0x0000001b, -} SRBM_PERFCOUNT1_SEL; - -typedef enum SU_PERFCNT_SEL { -PERF_PAPC_PASX_REQ = 0x00000000, -PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001, -PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002, -PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003, -PERF_PAPC_PASX_FIRST_DEAD = 0x00000004, -PERF_PAPC_PASX_SECOND_DEAD = 0x00000005, -PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006, -PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007, -PERF_PAPC_PA_INPUT_PRIM = 0x00000008, -PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009, -PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a, -PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b, -PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c, -PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d, -PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e, -PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f, -PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010, -PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011, -PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012, -PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013, -PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014, -PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015, -PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016, -PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017, -PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e, -PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f, -PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020, -PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021, -PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022, -PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023, -PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024, -PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025, -PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026, -PERF_PAPC_CLSM_NULL_PRIM = 0x00000027, -PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028, -PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029, -PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a, -PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b, -PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c, -PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d, -PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e, -PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f, -PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030, -PERF_PAPC_SU_INPUT_PRIM = 0x00000031, -PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032, -PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033, -PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034, -PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035, -PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036, -PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037, -PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038, -PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039, -PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a, -PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b, -PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c, -PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d, -PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e, -PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f, -PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040, -PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041, -PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042, -PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043, -PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044, -PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045, -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046, -PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047, -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048, -PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049, -PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a, -PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b, -PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c, -PERF_PAPC_PASX_REQ_IDLE = 0x0000004d, -PERF_PAPC_PASX_REQ_BUSY = 0x0000004e, -PERF_PAPC_PASX_REQ_STALLED = 0x0000004f, -PERF_PAPC_PASX_REC_IDLE = 0x00000050, -PERF_PAPC_PASX_REC_BUSY = 0x00000051, -PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052, -PERF_PAPC_PASX_REC_STALLED = 0x00000053, -PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054, -PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055, -PERF_PAPC_CCGSM_IDLE = 0x00000056, -PERF_PAPC_CCGSM_BUSY = 0x00000057, -PERF_PAPC_CCGSM_STALLED = 0x00000058, -PERF_PAPC_CLPRIM_IDLE = 0x00000059, -PERF_PAPC_CLPRIM_BUSY = 0x0000005a, -PERF_PAPC_CLPRIM_STALLED = 0x0000005b, -PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c, -PERF_PAPC_CLIPSM_IDLE = 0x0000005d, -PERF_PAPC_CLIPSM_BUSY = 0x0000005e, -PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f, -PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060, -PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061, -PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062, -PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063, -PERF_PAPC_CLIPGA_IDLE = 0x00000064, -PERF_PAPC_CLIPGA_BUSY = 0x00000065, -PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066, -PERF_PAPC_CLIPGA_STALLED = 0x00000067, -PERF_PAPC_CLIP_IDLE = 0x00000068, -PERF_PAPC_CLIP_BUSY = 0x00000069, -PERF_PAPC_SU_IDLE = 0x0000006a, -PERF_PAPC_SU_BUSY = 0x0000006b, -PERF_PAPC_SU_STARVED_CLIP = 0x0000006c, -PERF_PAPC_SU_STALLED_SC = 0x0000006d, -PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e, -PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f, -PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070, -PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071, -PERF_PAPC_PASX_SE0_REQ = 0x00000072, -PERF_PAPC_PASX_SE1_REQ = 0x00000073, -PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074, -PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075, -PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076, -PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077, -PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078, -PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079, -PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a, -PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b, -PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c, -PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d, -PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e, -PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f, -PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080, -PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081, -PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082, -PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083, -PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084, -PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085, -PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086, -PERF_PAPC_SU_CULLED_PRIM = 0x00000087, -PERF_PAPC_SU_OUTPUT_EOPG__CI__VI = 0x00000088, -PERF_PAPC_SU_SE2_PRIM_FILTER_CULL__CI__VI = 0x00000089, -PERF_PAPC_SU_SE3_PRIM_FILTER_CULL__CI__VI = 0x0000008a, -PERF_PAPC_SU_SE2_OUTPUT_PRIM__CI__VI = 0x0000008b, -PERF_PAPC_SU_SE3_OUTPUT_PRIM__CI__VI = 0x0000008c, -PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM__CI__VI = 0x0000008d, -PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM__CI__VI = 0x0000008e, -PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET__CI__VI = 0x0000008f, -PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET__CI__VI = 0x00000090, -PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET__CI__VI = 0x00000091, -PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET__CI__VI = 0x00000092, -PERF_PAPC_SU_SE0_OUTPUT_EOPG__CI__VI = 0x00000093, -PERF_PAPC_SU_SE1_OUTPUT_EOPG__CI__VI = 0x00000094, -PERF_PAPC_SU_SE2_OUTPUT_EOPG__CI__VI = 0x00000095, -PERF_PAPC_SU_SE3_OUTPUT_EOPG__CI__VI = 0x00000096, -PERF_PAPC_SU_SE2_STALLED_SC__CI__VI = 0x00000097, -PERF_PAPC_SU_SE3_STALLED_SC__CI__VI = 0x00000098, -} SU_PERFCNT_SEL; - -typedef enum SampleSplit { -ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000, -ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001, -ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002, -ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003, -} SampleSplit; - -typedef enum SampleSplitBytes { -CONFIG_1KB_SPLIT = 0x00000000, -CONFIG_2KB_SPLIT = 0x00000001, -CONFIG_4KB_SPLIT = 0x00000002, -CONFIG_8KB_SPLIT = 0x00000003, -} SampleSplitBytes; - -typedef enum ScMap { -RASTER_CONFIG_SC_MAP_0 = 0x00000000, -RASTER_CONFIG_SC_MAP_1 = 0x00000001, -RASTER_CONFIG_SC_MAP_2 = 0x00000002, -RASTER_CONFIG_SC_MAP_3 = 0x00000003, -} ScMap; - -typedef enum ScXsel { -RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003, -} ScXsel; - -typedef enum ScYsel { -RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003, -} ScYsel; - -typedef enum SeMap { -RASTER_CONFIG_SE_MAP_0 = 0x00000000, -RASTER_CONFIG_SE_MAP_1 = 0x00000001, -RASTER_CONFIG_SE_MAP_2 = 0x00000002, -RASTER_CONFIG_SE_MAP_3 = 0x00000003, -} SeMap; - -typedef enum SePairMap { -RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000, -RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001, -RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002, -RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003, -} SePairMap; - -typedef enum SePairXsel { -RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003, -} SePairXsel; - -typedef enum SePairYsel { -RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003, -} SePairYsel; - -typedef enum SeXsel { -RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003, -} SeXsel; - -typedef enum SeYsel { -RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003, -} SeYsel; - -typedef enum ShaderEngineTileSize { -ADDR_CONFIG_SE_TILE_16 = 0x00000000, -ADDR_CONFIG_SE_TILE_32 = 0x00000001, -} ShaderEngineTileSize; - -typedef enum SourceFormat { -EXPORT_4C_32BPC = 0x00000000, -EXPORT_4C_16BPC = 0x00000001, -EXPORT_2C_32BPC_GR = 0x00000002, -EXPORT_2C_32BPC_AR = 0x00000003, -} SourceFormat; - -typedef enum StencilFormat { -STENCIL_INVALID = 0x00000000, -STENCIL_8 = 0x00000001, -} StencilFormat; - -typedef enum StencilOp { -STENCIL_KEEP = 0x00000000, -STENCIL_ZERO = 0x00000001, -STENCIL_ONES = 0x00000002, -STENCIL_REPLACE_TEST = 0x00000003, -STENCIL_REPLACE_OP = 0x00000004, -STENCIL_ADD_CLAMP = 0x00000005, -STENCIL_SUB_CLAMP = 0x00000006, -STENCIL_INVERT = 0x00000007, -STENCIL_ADD_WRAP = 0x00000008, -STENCIL_SUB_WRAP = 0x00000009, -STENCIL_AND = 0x0000000a, -STENCIL_OR = 0x0000000b, -STENCIL_XOR = 0x0000000c, -STENCIL_NAND = 0x0000000d, -STENCIL_NOR = 0x0000000e, -STENCIL_XNOR = 0x0000000f, -} StencilOp; - -typedef enum SurfaceArray { -ARRAY_1D = 0x00000000, -ARRAY_2D = 0x00000001, -ARRAY_3D = 0x00000002, -ARRAY_3D_SLICE = 0x00000003, -} SurfaceArray; - -typedef enum SurfaceEndian { -ENDIAN_NONE = 0x00000000, -ENDIAN_8IN16 = 0x00000001, -ENDIAN_8IN32 = 0x00000002, -ENDIAN_8IN64 = 0x00000003, -} SurfaceEndian; - -typedef enum SurfaceFormat { -FMT_INVALID = 0x00000000, -FMT_8 = 0x00000001, -FMT_16 = 0x00000002, -FMT_8_8 = 0x00000003, -FMT_32 = 0x00000004, -FMT_16_16 = 0x00000005, -FMT_10_11_11 = 0x00000006, -FMT_11_11_10 = 0x00000007, -FMT_10_10_10_2 = 0x00000008, -FMT_2_10_10_10 = 0x00000009, -FMT_8_8_8_8 = 0x0000000a, -FMT_32_32 = 0x0000000b, -FMT_16_16_16_16 = 0x0000000c, -FMT_32_32_32 = 0x0000000d, -FMT_32_32_32_32 = 0x0000000e, -FMT_RESERVED_4 = 0x0000000f, -FMT_5_6_5 = 0x00000010, -FMT_1_5_5_5 = 0x00000011, -FMT_5_5_5_1 = 0x00000012, -FMT_4_4_4_4 = 0x00000013, -FMT_8_24 = 0x00000014, -FMT_24_8 = 0x00000015, -FMT_X24_8_32_FLOAT = 0x00000016, -FMT_RESERVED_33 = 0x00000017, -FMT_11_11_10_FLOAT = 0x00000018, -FMT_16_FLOAT = 0x00000019, -FMT_32_FLOAT = 0x0000001a, -FMT_16_16_FLOAT = 0x0000001b, -FMT_8_24_FLOAT = 0x0000001c, -FMT_24_8_FLOAT = 0x0000001d, -FMT_32_32_FLOAT = 0x0000001e, -FMT_10_11_11_FLOAT = 0x0000001f, -FMT_16_16_16_16_FLOAT = 0x00000020, -FMT_3_3_2 = 0x00000021, -FMT_6_5_5 = 0x00000022, -FMT_32_32_32_32_FLOAT = 0x00000023, -FMT_RESERVED_36 = 0x00000024, -FMT_1 = 0x00000025, -FMT_1_REVERSED = 0x00000026, -FMT_GB_GR = 0x00000027, -FMT_BG_RG = 0x00000028, -FMT_32_AS_8 = 0x00000029, -FMT_32_AS_8_8 = 0x0000002a, -FMT_5_9_9_9_SHAREDEXP = 0x0000002b, -FMT_8_8_8 = 0x0000002c, -FMT_16_16_16 = 0x0000002d, -FMT_16_16_16_FLOAT = 0x0000002e, -FMT_4_4 = 0x0000002f, -FMT_32_32_32_FLOAT = 0x00000030, -FMT_BC1 = 0x00000031, -FMT_BC2 = 0x00000032, -FMT_BC3 = 0x00000033, -FMT_BC4 = 0x00000034, -FMT_BC5 = 0x00000035, -FMT_BC6 = 0x00000036, -FMT_BC7 = 0x00000037, -FMT_32_AS_32_32_32_32 = 0x00000038, -FMT_APC3 = 0x00000039, -FMT_APC4 = 0x0000003a, -FMT_APC5 = 0x0000003b, -FMT_APC6 = 0x0000003c, -FMT_APC7 = 0x0000003d, -FMT_CTX1 = 0x0000003e, -FMT_RESERVED_63 = 0x0000003f, -} SurfaceFormat; - -typedef enum SurfaceNumber { -NUMBER_UNORM = 0x00000000, -NUMBER_SNORM = 0x00000001, -NUMBER_USCALED = 0x00000002, -NUMBER_SSCALED = 0x00000003, -NUMBER_UINT = 0x00000004, -NUMBER_SINT = 0x00000005, -NUMBER_SRGB = 0x00000006, -NUMBER_FLOAT = 0x00000007, -} SurfaceNumber; - -typedef enum SurfaceSwap { -SWAP_STD = 0x00000000, -SWAP_ALT = 0x00000001, -SWAP_STD_REV = 0x00000002, -SWAP_ALT_REV = 0x00000003, -} SurfaceSwap; - -typedef enum SurfaceTiling { -ARRAY_LINEAR = 0x00000000, -ARRAY_TILED = 0x00000001, -} SurfaceTiling; - -typedef enum TA_PERFCOUNT_SEL { -TA_PERF_SEL_ta_busy__SI__CI = 0x00000000, -TA_PERF_SEL_NULL__VI = 0x00000000, -TA_PERF_SEL_sh_fifo_busy = 0x00000001, -TA_PERF_SEL_sh_fifo_cmd_busy = 0x00000002, -TA_PERF_SEL_sh_fifo_addr_busy = 0x00000003, -TA_PERF_SEL_sh_fifo_data_busy = 0x00000004, -TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x00000005, -TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x00000006, -TA_PERF_SEL_gradient_busy = 0x00000007, -TA_PERF_SEL_gradient_fifo_busy = 0x00000008, -TA_PERF_SEL_lod_busy = 0x00000009, -TA_PERF_SEL_lod_fifo_busy = 0x0000000a, -TA_PERF_SEL_addresser_busy = 0x0000000b, -TA_PERF_SEL_addresser_fifo_busy = 0x0000000c, -TA_PERF_SEL_aligner_busy = 0x0000000d, -TA_PERF_SEL_write_path_busy = 0x0000000e, -TA_PERF_SEL_RESERVED_15__SI__CI = 0x0000000f, -TA_PERF_SEL_ta_busy__VI = 0x0000000f, -TA_PERF_SEL_sq_ta_cmd_cycles = 0x00000010, -TA_PERF_SEL_sp_ta_addr_cycles = 0x00000011, -TA_PERF_SEL_sp_ta_data_cycles = 0x00000012, -TA_PERF_SEL_ta_fa_data_state_cycles = 0x00000013, -TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x00000014, -TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x00000015, -TA_PERF_SEL_RESERVED_28 = 0x0000001c, -TA_PERF_SEL_RESERVED_29 = 0x0000001d, -TA_PERF_SEL_sh_fifo_addr_cycles = 0x0000001e, -TA_PERF_SEL_sh_fifo_data_cycles = 0x0000001f, -TA_PERF_SEL_total_wavefronts = 0x00000020, -TA_PERF_SEL_gradient_cycles = 0x00000021, -TA_PERF_SEL_walker_cycles = 0x00000022, -TA_PERF_SEL_aligner_cycles = 0x00000023, -TA_PERF_SEL_image_wavefronts = 0x00000024, -TA_PERF_SEL_image_read_wavefronts = 0x00000025, -TA_PERF_SEL_image_write_wavefronts = 0x00000026, -TA_PERF_SEL_image_atomic_wavefronts = 0x00000027, -TA_PERF_SEL_image_total_cycles = 0x00000028, -TA_PERF_SEL_RESERVED_41 = 0x00000029, -TA_PERF_SEL_RESERVED_42 = 0x0000002a, -TA_PERF_SEL_RESERVED_43 = 0x0000002b, -TA_PERF_SEL_buffer_wavefronts = 0x0000002c, -TA_PERF_SEL_buffer_read_wavefronts = 0x0000002d, -TA_PERF_SEL_buffer_write_wavefronts = 0x0000002e, -TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f, -TA_PERF_SEL_buffer_coalescable_wavefronts = 0x00000030, -TA_PERF_SEL_buffer_total_cycles = 0x00000031, -TA_PERF_SEL_buffer_coalesced_read_cycles = 0x00000034, -TA_PERF_SEL_buffer_coalesced_write_cycles = 0x00000035, -TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036, -TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037, -TA_PERF_SEL_data_stalled_by_tc_cycles = 0x00000038, -TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a, -TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c, -TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d, -TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e, -TA_PERF_SEL_aniso_gt1_cycle_quads__CI__VI = 0x0000003f, -TA_PERF_SEL_color_1_cycle_pixels = 0x00000040, -TA_PERF_SEL_color_2_cycle_pixels = 0x00000041, -TA_PERF_SEL_color_3_cycle_pixels = 0x00000042, -TA_PERF_SEL_color_4_cycle_pixels = 0x00000043, -TA_PERF_SEL_mip_1_cycle_pixels = 0x00000044, -TA_PERF_SEL_mip_2_cycle_pixels = 0x00000045, -TA_PERF_SEL_vol_1_cycle_pixels = 0x00000046, -TA_PERF_SEL_vol_2_cycle_pixels = 0x00000047, -TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x00000048, -TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049, -TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a, -TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b, -TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c, -TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d, -TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e, -TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f, -TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050, -TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051, -TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052, -TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053, -TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054, -TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055, -TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056, -TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057, -TA_PERF_SEL_mipmap_invalid_samples = 0x00000058, -TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059, -TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a, -TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b, -TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c, -TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d, -TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e, -TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f, -TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060, -TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061, -TA_PERF_SEL_write_path_input_cycles = 0x00000062, -TA_PERF_SEL_write_path_output_cycles = 0x00000063, -TA_PERF_SEL_reg_sclk_vld__SI = 0x00000064, -TA_PERF_SEL_flat_wavefronts__CI__VI = 0x00000064, -TA_PERF_SEL_local_cg_dyn_sclk_grp0_en__SI = 0x00000065, -TA_PERF_SEL_flat_read_wavefronts__CI__VI = 0x00000065, -TA_PERF_SEL_local_cg_dyn_sclk_grp1_en__SI = 0x00000066, -TA_PERF_SEL_flat_write_wavefronts__CI__VI = 0x00000066, -TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en__SI = 0x00000067, -TA_PERF_SEL_flat_atomic_wavefronts__CI__VI = 0x00000067, -TA_PERF_SEL_local_cg_dyn_sclk_grp4_en__SI = 0x00000068, -TA_PERF_SEL_flat_coalesceable_wavefronts__CI__VI = 0x00000068, -TA_PERF_SEL_local_cg_dyn_sclk_grp5_en__SI = 0x00000069, -TA_PERF_SEL_reg_sclk_vld__CI__VI = 0x00000069, -TA_PERF_SEL_local_cg_dyn_sclk_grp0_en__CI__VI = 0x0000006a, -TA_PERF_SEL_local_cg_dyn_sclk_grp1_en__CI__VI = 0x0000006b, -TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en__CI__VI = 0x0000006c, -TA_PERF_SEL_local_cg_dyn_sclk_grp4_en__CI__VI = 0x0000006d, -TA_PERF_SEL_local_cg_dyn_sclk_grp5_en__CI__VI = 0x0000006e, -TA_PERF_SEL_xnack_on_phase0__VI = 0x0000006f, -TA_PERF_SEL_xnack_on_phase1__VI = 0x00000070, -TA_PERF_SEL_xnack_on_phase2__VI = 0x00000071, -TA_PERF_SEL_xnack_on_phase3__VI = 0x00000072, -TA_PERF_SEL_first_xnack_on_phase0__VI = 0x00000073, -TA_PERF_SEL_first_xnack_on_phase1__VI = 0x00000074, -TA_PERF_SEL_first_xnack_on_phase2__VI = 0x00000075, -TA_PERF_SEL_first_xnack_on_phase3__VI = 0x00000076, -} TA_PERFCOUNT_SEL; - -typedef enum TA_TC_ADDR_MODES { -TA_TC_ADDR_MODE_DEFAULT = 0x00000000, -TA_TC_ADDR_MODE_COMP0 = 0x00000001, -TA_TC_ADDR_MODE_COMP1 = 0x00000002, -TA_TC_ADDR_MODE_COMP2 = 0x00000003, -TA_TC_ADDR_MODE_COMP3 = 0x00000004, -TA_TC_ADDR_MODE_UNALIGNED = 0x00000005, -TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006, -} TA_TC_ADDR_MODES; - -typedef enum TCA_PERF_SEL { -TCA_PERF_SEL_NONE = 0x00000000, -TCA_PERF_SEL_CYCLE = 0x00000001, -TCA_PERF_SEL_BUSY = 0x00000002, -TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x00000003, -TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x00000004, -TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x00000005, -TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x00000006, -TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x00000007, -TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x00000008, -TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x00000009, -TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0x0000000a, -TCA_PERF_SEL_REQ_TCC0 = 0x0000000b, -TCA_PERF_SEL_REQ_TCC1 = 0x0000000c, -TCA_PERF_SEL_REQ_TCC2 = 0x0000000d, -TCA_PERF_SEL_REQ_TCC3 = 0x0000000e, -TCA_PERF_SEL_REQ_TCC4 = 0x0000000f, -TCA_PERF_SEL_REQ_TCC5 = 0x00000010, -TCA_PERF_SEL_REQ_TCC6 = 0x00000011, -TCA_PERF_SEL_REQ_TCC7 = 0x00000012, -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x00000013, -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x00000014, -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x00000015, -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x00000016, -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x00000017, -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x00000018, -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x00000019, -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x0000001a, -TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x0000001b, -TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x0000001c, -TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x0000001d, -TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x0000001e, -TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x0000001f, -TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x00000020, -TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x00000021, -TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x00000022, -TCA_PERF_SEL_FORCED_HOLE_TCS__CI = 0x00000023, -TCA_PERF_SEL_REQ_TCS__CI = 0x00000024, -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCS__CI = 0x00000025, -TCA_PERF_SEL_CROSSBAR_STALL_TCS__CI = 0x00000026, -} TCA_PERF_SEL; - -typedef enum TCC_CACHE_POLICIES { -TCC_CACHE_POLICY_LRU = 0x00000000, -TCC_CACHE_POLICY_STREAM = 0x00000001, -TCC_CACHE_POLICY_BYPASS__SI__CI = 0x00000002, -} TCC_CACHE_POLICIES; - -typedef enum TCC_PERF_SEL { -TCC_PERF_SEL_NONE = 0x00000000, -TCC_PERF_SEL_CYCLE = 0x00000001, -TCC_PERF_SEL_BUSY = 0x00000002, -TCC_PERF_SEL_REQ = 0x00000003, -TCC_PERF_SEL_STREAMING_REQ = 0x00000004, -TCC_PERF_SEL_READ__SI__CI = 0x00000005, -TCC_PERF_SEL_EXE_REQ__VI = 0x00000005, -TCC_PERF_SEL_WRITE__SI__CI = 0x00000006, -TCC_PERF_SEL_COMPRESSED_REQ__VI = 0x00000006, -TCC_PERF_SEL_ATOMIC__SI__CI = 0x00000007, -TCC_PERF_SEL_COMPRESSED_0_REQ__VI = 0x00000007, -TCC_PERF_SEL_WBINVL2__SI__CI = 0x00000008, -TCC_PERF_SEL_METADATA_REQ__VI = 0x00000008, -TCC_PERF_SEL_WBINVL2_CYCLE__SI__CI = 0x00000009, -TCC_PERF_SEL_NC_VIRTUAL_REQ__VI = 0x00000009, -TCC_PERF_SEL_HIT__SI__CI = 0x0000000a, -TCC_PERF_SEL_NC_PHYSICAL_REQ__VI = 0x0000000a, -TCC_PERF_SEL_MISS__SI__CI = 0x0000000b, -TCC_PERF_SEL_UC_VIRTUAL_REQ__VI = 0x0000000b, -TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT__SI__CI = 0x0000000c, -TCC_PERF_SEL_UC_PHYSICAL_REQ__VI = 0x0000000c, -TCC_PERF_SEL_FULLY_WRITTEN_HIT__SI__CI = 0x0000000d, -TCC_PERF_SEL_CC_PHYSICAL_REQ__VI = 0x0000000d, -TCC_PERF_SEL_WRITEBACK__SI__CI = 0x0000000e, -TCC_PERF_SEL_PROBE__VI = 0x0000000e, -TCC_PERF_SEL_LATENCY_FIFO_FULL__SI__CI = 0x0000000f, -TCC_PERF_SEL_READ__VI = 0x0000000f, -TCC_PERF_SEL_SRC_FIFO_FULL__SI__CI = 0x00000010, -TCC_PERF_SEL_WRITE__VI = 0x00000010, -TCC_PERF_SEL_HOLE_FIFO_FULL__SI__CI = 0x00000011, -TCC_PERF_SEL_ATOMIC__VI = 0x00000011, -TCC_PERF_SEL_MC_WRREQ__SI__CI = 0x00000012, -TCC_PERF_SEL_HIT__VI = 0x00000012, -TCC_PERF_SEL_MC_WRREQ_STALL__SI__CI = 0x00000013, -TCC_PERF_SEL_MISS__VI = 0x00000013, -TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL__SI__CI = 0x00000014, -TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT__VI = 0x00000014, -TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL__SI__CI = 0x00000015, -TCC_PERF_SEL_FULLY_WRITTEN_HIT__VI = 0x00000015, -TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL__SI__CI = 0x00000016, -TCC_PERF_SEL_WRITEBACK__VI = 0x00000016, -TCC_PERF_SEL_MC_WRREQ_LEVEL__SI__CI = 0x00000017, -TCC_PERF_SEL_LATENCY_FIFO_FULL__VI = 0x00000017, -TCC_PERF_SEL_MC_RDREQ__SI__CI = 0x00000018, -TCC_PERF_SEL_SRC_FIFO_FULL__VI = 0x00000018, -TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL__SI__CI = 0x00000019, -TCC_PERF_SEL_HOLE_FIFO_FULL__VI = 0x00000019, -TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL__SI__CI = 0x0000001a, -TCC_PERF_SEL_MC_WRREQ__VI = 0x0000001a, -TCC_PERF_SEL_MC_RDREQ_LEVEL__SI__CI = 0x0000001b, -TCC_PERF_SEL_MC_WRREQ_UNCACHED__VI = 0x0000001b, -TCC_PERF_SEL_TAG_STALL__SI__CI = 0x0000001c, -TCC_PERF_SEL_MC_WRREQ_STALL__VI = 0x0000001c, -TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL__SI__CI = 0x0000001d, -TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL__VI = 0x0000001d, -TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL__SI__CI = 0x0000001e, -TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL__VI = 0x0000001e, -TCC_PERF_SEL_READ_RETURN_TIMEOUT__SI__CI = 0x0000001f, -TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL__VI = 0x0000001f, -TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT__SI__CI = 0x00000020, -TCC_PERF_SEL_MC_WRREQ_LEVEL__VI = 0x00000020, -TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE__SI__CI = 0x00000021, -TCC_PERF_SEL_MC_ATOMIC__VI = 0x00000021, -TCC_PERF_SEL_BUBBLE__SI__CI = 0x00000022, -TCC_PERF_SEL_MC_ATOMIC_LEVEL__VI = 0x00000022, -TCC_PERF_SEL_RETURN_ACK__SI__CI = 0x00000023, -TCC_PERF_SEL_MC_RDREQ__VI = 0x00000023, -TCC_PERF_SEL_RETURN_DATA__SI__CI = 0x00000024, -TCC_PERF_SEL_MC_RDREQ_UNCACHED__VI = 0x00000024, -TCC_PERF_SEL_RETURN_HOLE__SI__CI = 0x00000025, -TCC_PERF_SEL_MC_RDREQ_MDC__VI = 0x00000025, -TCC_PERF_SEL_RETURN_ACK_HOLE__SI__CI = 0x00000026, -TCC_PERF_SEL_MC_RDREQ_COMPRESSED__VI = 0x00000026, -TCC_PERF_SEL_IB_STALL__SI__CI = 0x00000027, -TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL__VI = 0x00000027, -TCC_PERF_SEL_TCA_LEVEL__SI__CI = 0x00000028, -TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL__VI = 0x00000028, -TCC_PERF_SEL_HOLE_LEVEL__SI__CI = 0x00000029, -TCC_PERF_SEL_MC_RDREQ_LEVEL__VI = 0x00000029, -TCC_PERF_SEL_MC_RDRET_NACK__CI = 0x0000002a, -TCC_PERF_SEL_TAG_STALL__VI = 0x0000002a, -TCC_PERF_SEL_MC_WRRET_NACK__CI = 0x0000002b, -TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL__VI = 0x0000002b, -TCC_PERF_SEL_EXE_REQ__CI = 0x0000002c, -TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL__VI = 0x0000002c, -TCC_PERF_SEL_TAG_PROBE_STALL__VI = 0x0000002f, -TCC_PERF_SEL_TAG_PROBE_FILTER_STALL__VI = 0x00000030, -TCC_PERF_SEL_READ_RETURN_TIMEOUT__VI = 0x00000031, -TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT__VI = 0x00000032, -TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE__VI = 0x00000033, -TCC_PERF_SEL_BUBBLE__VI = 0x00000034, -TCC_PERF_SEL_RETURN_ACK__VI = 0x00000035, -TCC_PERF_SEL_RETURN_DATA__VI = 0x00000036, -TCC_PERF_SEL_RETURN_HOLE__VI = 0x00000037, -TCC_PERF_SEL_RETURN_ACK_HOLE__VI = 0x00000038, -TCC_PERF_SEL_IB_REQ__VI = 0x00000039, -TCC_PERF_SEL_IB_STALL__VI = 0x0000003a, -TCC_PERF_SEL_IB_TAG_STALL__VI = 0x0000003b, -TCC_PERF_SEL_IB_MDC_STALL__VI = 0x0000003c, -TCC_PERF_SEL_TCA_LEVEL__VI = 0x0000003d, -TCC_PERF_SEL_HOLE_LEVEL__VI = 0x0000003e, -TCC_PERF_SEL_MC_RDRET_NACK__VI = 0x0000003f, -TCC_PERF_SEL_CLIENT0_REQ__SI__CI = 0x00000040, -TCC_PERF_SEL_MC_WRRET_NACK__VI = 0x00000040, -TCC_PERF_SEL_CLIENT1_REQ__SI__CI = 0x00000041, -TCC_PERF_SEL_NORMAL_WRITEBACK__VI = 0x00000041, -TCC_PERF_SEL_CLIENT2_REQ__SI__CI = 0x00000042, -TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK__VI = 0x00000042, -TCC_PERF_SEL_CLIENT3_REQ__SI__CI = 0x00000043, -TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK__VI = 0x00000043, -TCC_PERF_SEL_CLIENT4_REQ__SI__CI = 0x00000044, -TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK__VI = 0x00000044, -TCC_PERF_SEL_CLIENT5_REQ__SI__CI = 0x00000045, -TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK__VI = 0x00000045, -TCC_PERF_SEL_CLIENT6_REQ__SI__CI = 0x00000046, -TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK__VI = 0x00000046, -TCC_PERF_SEL_CLIENT7_REQ__SI__CI = 0x00000047, -TCC_PERF_SEL_NORMAL_EVICT__VI = 0x00000047, -TCC_PERF_SEL_CLIENT8_REQ__SI__CI = 0x00000048, -TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT__VI = 0x00000048, -TCC_PERF_SEL_CLIENT9_REQ__SI__CI = 0x00000049, -TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT__VI = 0x00000049, -TCC_PERF_SEL_CLIENT10_REQ__SI__CI = 0x0000004a, -TCC_PERF_SEL_TC_OP_WBINVL2_EVICT__VI = 0x0000004a, -TCC_PERF_SEL_CLIENT11_REQ__SI__CI = 0x0000004b, -TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT__VI = 0x0000004b, -TCC_PERF_SEL_CLIENT12_REQ__SI__CI = 0x0000004c, -TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT__VI = 0x0000004c, -TCC_PERF_SEL_CLIENT13_REQ__SI__CI = 0x0000004d, -TCC_PERF_SEL_ALL_TC_OP_INV_EVICT__VI = 0x0000004d, -TCC_PERF_SEL_CLIENT14_REQ__SI__CI = 0x0000004e, -TCC_PERF_SEL_PROBE_EVICT__VI = 0x0000004e, -TCC_PERF_SEL_CLIENT15_REQ__SI__CI = 0x0000004f, -TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE__VI = 0x0000004f, -TCC_PERF_SEL_CLIENT16_REQ__SI__CI = 0x00000050, -TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE__VI = 0x00000050, -TCC_PERF_SEL_CLIENT17_REQ__SI__CI = 0x00000051, -TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE__VI = 0x00000051, -TCC_PERF_SEL_CLIENT18_REQ__SI__CI = 0x00000052, -TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE__VI = 0x00000052, -TCC_PERF_SEL_CLIENT19_REQ__SI__CI = 0x00000053, -TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE__VI = 0x00000053, -TCC_PERF_SEL_CLIENT20_REQ__SI__CI = 0x00000054, -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE__VI = 0x00000054, -TCC_PERF_SEL_CLIENT21_REQ__SI__CI = 0x00000055, -TCC_PERF_SEL_TC_OP_WBL2_NC_START__VI = 0x00000055, -TCC_PERF_SEL_CLIENT22_REQ__SI__CI = 0x00000056, -TCC_PERF_SEL_TC_OP_INVL2_NC_START__VI = 0x00000056, -TCC_PERF_SEL_CLIENT23_REQ__SI__CI = 0x00000057, -TCC_PERF_SEL_TC_OP_WBINVL2_START__VI = 0x00000057, -TCC_PERF_SEL_CLIENT24_REQ__SI__CI = 0x00000058, -TCC_PERF_SEL_TC_OP_WBINVL2_NC_START__VI = 0x00000058, -TCC_PERF_SEL_CLIENT25_REQ__SI__CI = 0x00000059, -TCC_PERF_SEL_TC_OP_WBINVL2_SD_START__VI = 0x00000059, -TCC_PERF_SEL_CLIENT26_REQ__SI__CI = 0x0000005a, -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START__VI = 0x0000005a, -TCC_PERF_SEL_CLIENT27_REQ__SI__CI = 0x0000005b, -TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH__VI = 0x0000005b, -TCC_PERF_SEL_CLIENT28_REQ__SI__CI = 0x0000005c, -TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH__VI = 0x0000005c, -TCC_PERF_SEL_CLIENT29_REQ__SI__CI = 0x0000005d, -TCC_PERF_SEL_TC_OP_WBINVL2_FINISH__VI = 0x0000005d, -TCC_PERF_SEL_CLIENT30_REQ__SI__CI = 0x0000005e, -TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH__VI = 0x0000005e, -TCC_PERF_SEL_CLIENT31_REQ__SI__CI = 0x0000005f, -TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH__VI = 0x0000005f, -TCC_PERF_SEL_CLIENT32_REQ__SI__CI = 0x00000060, -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH__VI = 0x00000060, -TCC_PERF_SEL_CLIENT33_REQ__SI__CI = 0x00000061, -TCC_PERF_SEL_MDC_REQ__VI = 0x00000061, -TCC_PERF_SEL_CLIENT34_REQ__SI__CI = 0x00000062, -TCC_PERF_SEL_MDC_LEVEL__VI = 0x00000062, -TCC_PERF_SEL_CLIENT35_REQ__SI__CI = 0x00000063, -TCC_PERF_SEL_MDC_TAG_HIT__VI = 0x00000063, -TCC_PERF_SEL_CLIENT36_REQ__SI__CI = 0x00000064, -TCC_PERF_SEL_MDC_SECTOR_HIT__VI = 0x00000064, -TCC_PERF_SEL_CLIENT37_REQ__SI__CI = 0x00000065, -TCC_PERF_SEL_MDC_SECTOR_MISS__VI = 0x00000065, -TCC_PERF_SEL_CLIENT38_REQ__SI__CI = 0x00000066, -TCC_PERF_SEL_MDC_TAG_STALL__VI = 0x00000066, -TCC_PERF_SEL_CLIENT39_REQ__SI__CI = 0x00000067, -TCC_PERF_SEL_CLIENT40_REQ__SI__CI = 0x00000068, -TCC_PERF_SEL_CLIENT41_REQ__SI__CI = 0x00000069, -TCC_PERF_SEL_CLIENT42_REQ__SI__CI = 0x0000006a, -TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION__VI = 0x0000006a, -TCC_PERF_SEL_CLIENT43_REQ__SI__CI = 0x0000006b, -TCC_PERF_SEL_PROBE_FILTER_DISABLED__VI = 0x0000006b, -TCC_PERF_SEL_CLIENT44_REQ__SI__CI = 0x0000006c, -TCC_PERF_SEL_CLIENT45_REQ__SI__CI = 0x0000006d, -TCC_PERF_SEL_CLIENT46_REQ__SI__CI = 0x0000006e, -TCC_PERF_SEL_CLIENT47_REQ__SI__CI = 0x0000006f, -TCC_PERF_SEL_CLIENT48_REQ__SI__CI = 0x00000070, -TCC_PERF_SEL_CLIENT49_REQ__SI__CI = 0x00000071, -TCC_PERF_SEL_CLIENT50_REQ__SI__CI = 0x00000072, -TCC_PERF_SEL_CLIENT51_REQ__SI__CI = 0x00000073, -TCC_PERF_SEL_CLIENT52_REQ__SI__CI = 0x00000074, -TCC_PERF_SEL_CLIENT53_REQ__SI__CI = 0x00000075, -TCC_PERF_SEL_CLIENT54_REQ__SI__CI = 0x00000076, -TCC_PERF_SEL_CLIENT55_REQ__SI__CI = 0x00000077, -TCC_PERF_SEL_CLIENT56_REQ__SI__CI = 0x00000078, -TCC_PERF_SEL_CLIENT57_REQ__SI__CI = 0x00000079, -TCC_PERF_SEL_CLIENT58_REQ__SI__CI = 0x0000007a, -TCC_PERF_SEL_CLIENT59_REQ__SI__CI = 0x0000007b, -TCC_PERF_SEL_CLIENT60_REQ__SI__CI = 0x0000007c, -TCC_PERF_SEL_CLIENT61_REQ__SI__CI = 0x0000007d, -TCC_PERF_SEL_CLIENT62_REQ__SI__CI = 0x0000007e, -TCC_PERF_SEL_CLIENT63_REQ__SI__CI = 0x0000007f, -TCC_PERF_SEL_NORMAL_WRITEBACK__CI = 0x00000080, -TCC_PERF_SEL_CLIENT0_REQ__VI = 0x00000080, -TCC_PERF_SEL_TC_OP_WBL2_VOL_WRITEBACK__CI = 0x00000081, -TCC_PERF_SEL_CLIENT1_REQ__VI = 0x00000081, -TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK__CI = 0x00000082, -TCC_PERF_SEL_CLIENT2_REQ__VI = 0x00000082, -TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK__CI = 0x00000083, -TCC_PERF_SEL_CLIENT3_REQ__VI = 0x00000083, -TCC_PERF_SEL_NORMAL_EVICT__CI = 0x00000084, -TCC_PERF_SEL_CLIENT4_REQ__VI = 0x00000084, -TCC_PERF_SEL_TC_OP_INVL2_VOL_EVICT__CI = 0x00000085, -TCC_PERF_SEL_CLIENT5_REQ__VI = 0x00000085, -TCC_PERF_SEL_TC_OP_INVL1L2_VOL_EVICT__CI = 0x00000086, -TCC_PERF_SEL_CLIENT6_REQ__VI = 0x00000086, -TCC_PERF_SEL_TC_OP_WBL2_VOL_EVICT__CI = 0x00000087, -TCC_PERF_SEL_CLIENT7_REQ__VI = 0x00000087, -TCC_PERF_SEL_TC_OP_WBINVL2_EVICT__CI = 0x00000088, -TCC_PERF_SEL_CLIENT8_REQ__VI = 0x00000088, -TCC_PERF_SEL_ALL_TC_OP_INV_EVICT__CI = 0x00000089, -TCC_PERF_SEL_CLIENT9_REQ__VI = 0x00000089, -TCC_PERF_SEL_ALL_TC_OP_INV_VOL_EVICT__CI = 0x0000008a, -TCC_PERF_SEL_CLIENT10_REQ__VI = 0x0000008a, -TCC_PERF_SEL_TC_OP_WBL2_VOL_CYCLE__CI = 0x0000008b, -TCC_PERF_SEL_CLIENT11_REQ__VI = 0x0000008b, -TCC_PERF_SEL_TC_OP_INVL2_VOL_CYCLE__CI = 0x0000008c, -TCC_PERF_SEL_CLIENT12_REQ__VI = 0x0000008c, -TCC_PERF_SEL_TC_OP_INVL1L2_VOL_CYCLE__CI = 0x0000008d, -TCC_PERF_SEL_CLIENT13_REQ__VI = 0x0000008d, -TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE__CI = 0x0000008e, -TCC_PERF_SEL_CLIENT14_REQ__VI = 0x0000008e, -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE__CI = 0x0000008f, -TCC_PERF_SEL_CLIENT15_REQ__VI = 0x0000008f, -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_CYCLE__CI = 0x00000090, -TCC_PERF_SEL_CLIENT16_REQ__VI = 0x00000090, -TCC_PERF_SEL_TC_OP_WBL2_VOL_START__CI = 0x00000091, -TCC_PERF_SEL_CLIENT17_REQ__VI = 0x00000091, -TCC_PERF_SEL_TC_OP_INVL2_VOL_START__CI = 0x00000092, -TCC_PERF_SEL_CLIENT18_REQ__VI = 0x00000092, -TCC_PERF_SEL_TC_OP_INVL1L2_VOL_START__CI = 0x00000093, -TCC_PERF_SEL_CLIENT19_REQ__VI = 0x00000093, -TCC_PERF_SEL_TC_OP_WBINVL2_START__CI = 0x00000094, -TCC_PERF_SEL_CLIENT20_REQ__VI = 0x00000094, -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START__CI = 0x00000095, -TCC_PERF_SEL_CLIENT21_REQ__VI = 0x00000095, -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START__CI = 0x00000096, -TCC_PERF_SEL_CLIENT22_REQ__VI = 0x00000096, -TCC_PERF_SEL_TC_OP_WBL2_VOL_FINISH__CI = 0x00000097, -TCC_PERF_SEL_CLIENT23_REQ__VI = 0x00000097, -TCC_PERF_SEL_TC_OP_INVL2_VOL_FINISH__CI = 0x00000098, -TCC_PERF_SEL_CLIENT24_REQ__VI = 0x00000098, -TCC_PERF_SEL_TC_OP_INVL1L2_VOL_FINISH__CI = 0x00000099, -TCC_PERF_SEL_CLIENT25_REQ__VI = 0x00000099, -TCC_PERF_SEL_TC_OP_WBINVL2_FINISH__CI = 0x0000009a, -TCC_PERF_SEL_CLIENT26_REQ__VI = 0x0000009a, -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH__CI = 0x0000009b, -TCC_PERF_SEL_CLIENT27_REQ__VI = 0x0000009b, -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_FINISH__CI = 0x0000009c, -TCC_PERF_SEL_CLIENT28_REQ__VI = 0x0000009c, -TCC_PERF_SEL_VOL_MC_WRREQ__CI = 0x0000009d, -TCC_PERF_SEL_CLIENT29_REQ__VI = 0x0000009d, -TCC_PERF_SEL_VOL_MC_RDREQ__CI = 0x0000009e, -TCC_PERF_SEL_CLIENT30_REQ__VI = 0x0000009e, -TCC_PERF_SEL_VOL_REQ__CI = 0x0000009f, -TCC_PERF_SEL_CLIENT31_REQ__VI = 0x0000009f, -TCC_PERF_SEL_CLIENT32_REQ__VI = 0x000000a0, -TCC_PERF_SEL_CLIENT33_REQ__VI = 0x000000a1, -TCC_PERF_SEL_CLIENT34_REQ__VI = 0x000000a2, -TCC_PERF_SEL_CLIENT35_REQ__VI = 0x000000a3, -TCC_PERF_SEL_CLIENT36_REQ__VI = 0x000000a4, -TCC_PERF_SEL_CLIENT37_REQ__VI = 0x000000a5, -TCC_PERF_SEL_CLIENT38_REQ__VI = 0x000000a6, -TCC_PERF_SEL_CLIENT39_REQ__VI = 0x000000a7, -TCC_PERF_SEL_CLIENT40_REQ__VI = 0x000000a8, -TCC_PERF_SEL_CLIENT41_REQ__VI = 0x000000a9, -TCC_PERF_SEL_CLIENT42_REQ__VI = 0x000000aa, -TCC_PERF_SEL_CLIENT43_REQ__VI = 0x000000ab, -TCC_PERF_SEL_CLIENT44_REQ__VI = 0x000000ac, -TCC_PERF_SEL_CLIENT45_REQ__VI = 0x000000ad, -TCC_PERF_SEL_CLIENT46_REQ__VI = 0x000000ae, -TCC_PERF_SEL_CLIENT47_REQ__VI = 0x000000af, -TCC_PERF_SEL_CLIENT48_REQ__VI = 0x000000b0, -TCC_PERF_SEL_CLIENT49_REQ__VI = 0x000000b1, -TCC_PERF_SEL_CLIENT50_REQ__VI = 0x000000b2, -TCC_PERF_SEL_CLIENT51_REQ__VI = 0x000000b3, -TCC_PERF_SEL_CLIENT52_REQ__VI = 0x000000b4, -TCC_PERF_SEL_CLIENT53_REQ__VI = 0x000000b5, -TCC_PERF_SEL_CLIENT54_REQ__VI = 0x000000b6, -TCC_PERF_SEL_CLIENT55_REQ__VI = 0x000000b7, -TCC_PERF_SEL_CLIENT56_REQ__VI = 0x000000b8, -TCC_PERF_SEL_CLIENT57_REQ__VI = 0x000000b9, -TCC_PERF_SEL_CLIENT58_REQ__VI = 0x000000ba, -TCC_PERF_SEL_CLIENT59_REQ__VI = 0x000000bb, -TCC_PERF_SEL_CLIENT60_REQ__VI = 0x000000bc, -TCC_PERF_SEL_CLIENT61_REQ__VI = 0x000000bd, -TCC_PERF_SEL_CLIENT62_REQ__VI = 0x000000be, -TCC_PERF_SEL_CLIENT63_REQ__VI = 0x000000bf, -TCC_PERF_SEL_CLIENT64_REQ__VI = 0x000000c0, -TCC_PERF_SEL_CLIENT65_REQ__VI = 0x000000c1, -TCC_PERF_SEL_CLIENT66_REQ__VI = 0x000000c2, -TCC_PERF_SEL_CLIENT67_REQ__VI = 0x000000c3, -TCC_PERF_SEL_CLIENT68_REQ__VI = 0x000000c4, -TCC_PERF_SEL_CLIENT69_REQ__VI = 0x000000c5, -TCC_PERF_SEL_CLIENT70_REQ__VI = 0x000000c6, -TCC_PERF_SEL_CLIENT71_REQ__VI = 0x000000c7, -TCC_PERF_SEL_CLIENT72_REQ__VI = 0x000000c8, -TCC_PERF_SEL_CLIENT73_REQ__VI = 0x000000c9, -TCC_PERF_SEL_CLIENT74_REQ__VI = 0x000000ca, -TCC_PERF_SEL_CLIENT75_REQ__VI = 0x000000cb, -TCC_PERF_SEL_CLIENT76_REQ__VI = 0x000000cc, -TCC_PERF_SEL_CLIENT77_REQ__VI = 0x000000cd, -TCC_PERF_SEL_CLIENT78_REQ__VI = 0x000000ce, -TCC_PERF_SEL_CLIENT79_REQ__VI = 0x000000cf, -TCC_PERF_SEL_CLIENT80_REQ__VI = 0x000000d0, -TCC_PERF_SEL_CLIENT81_REQ__VI = 0x000000d1, -TCC_PERF_SEL_CLIENT82_REQ__VI = 0x000000d2, -TCC_PERF_SEL_CLIENT83_REQ__VI = 0x000000d3, -TCC_PERF_SEL_CLIENT84_REQ__VI = 0x000000d4, -TCC_PERF_SEL_CLIENT85_REQ__VI = 0x000000d5, -TCC_PERF_SEL_CLIENT86_REQ__VI = 0x000000d6, -TCC_PERF_SEL_CLIENT87_REQ__VI = 0x000000d7, -TCC_PERF_SEL_CLIENT88_REQ__VI = 0x000000d8, -TCC_PERF_SEL_CLIENT89_REQ__VI = 0x000000d9, -TCC_PERF_SEL_CLIENT90_REQ__VI = 0x000000da, -TCC_PERF_SEL_CLIENT91_REQ__VI = 0x000000db, -TCC_PERF_SEL_CLIENT92_REQ__VI = 0x000000dc, -TCC_PERF_SEL_CLIENT93_REQ__VI = 0x000000dd, -TCC_PERF_SEL_CLIENT94_REQ__VI = 0x000000de, -TCC_PERF_SEL_CLIENT95_REQ__VI = 0x000000df, -TCC_PERF_SEL_CLIENT96_REQ__VI = 0x000000e0, -TCC_PERF_SEL_CLIENT97_REQ__VI = 0x000000e1, -TCC_PERF_SEL_CLIENT98_REQ__VI = 0x000000e2, -TCC_PERF_SEL_CLIENT99_REQ__VI = 0x000000e3, -TCC_PERF_SEL_CLIENT100_REQ__VI = 0x000000e4, -TCC_PERF_SEL_CLIENT101_REQ__VI = 0x000000e5, -TCC_PERF_SEL_CLIENT102_REQ__VI = 0x000000e6, -TCC_PERF_SEL_CLIENT103_REQ__VI = 0x000000e7, -TCC_PERF_SEL_CLIENT104_REQ__VI = 0x000000e8, -TCC_PERF_SEL_CLIENT105_REQ__VI = 0x000000e9, -TCC_PERF_SEL_CLIENT106_REQ__VI = 0x000000ea, -TCC_PERF_SEL_CLIENT107_REQ__VI = 0x000000eb, -TCC_PERF_SEL_CLIENT108_REQ__VI = 0x000000ec, -TCC_PERF_SEL_CLIENT109_REQ__VI = 0x000000ed, -TCC_PERF_SEL_CLIENT110_REQ__VI = 0x000000ee, -TCC_PERF_SEL_CLIENT111_REQ__VI = 0x000000ef, -TCC_PERF_SEL_CLIENT112_REQ__VI = 0x000000f0, -TCC_PERF_SEL_CLIENT113_REQ__VI = 0x000000f1, -TCC_PERF_SEL_CLIENT114_REQ__VI = 0x000000f2, -TCC_PERF_SEL_CLIENT115_REQ__VI = 0x000000f3, -TCC_PERF_SEL_CLIENT116_REQ__VI = 0x000000f4, -TCC_PERF_SEL_CLIENT117_REQ__VI = 0x000000f5, -TCC_PERF_SEL_CLIENT118_REQ__VI = 0x000000f6, -TCC_PERF_SEL_CLIENT119_REQ__VI = 0x000000f7, -TCC_PERF_SEL_CLIENT120_REQ__VI = 0x000000f8, -TCC_PERF_SEL_CLIENT121_REQ__VI = 0x000000f9, -TCC_PERF_SEL_CLIENT122_REQ__VI = 0x000000fa, -TCC_PERF_SEL_CLIENT123_REQ__VI = 0x000000fb, -TCC_PERF_SEL_CLIENT124_REQ__VI = 0x000000fc, -TCC_PERF_SEL_CLIENT125_REQ__VI = 0x000000fd, -TCC_PERF_SEL_CLIENT126_REQ__VI = 0x000000fe, -TCC_PERF_SEL_CLIENT127_REQ__VI = 0x000000ff, -} TCC_PERF_SEL; - -typedef enum TCP_CACHE_POLICIES { -TCP_CACHE_POLICY_MISS_LRU = 0x00000000, -TCP_CACHE_POLICY_MISS_EVICT = 0x00000001, -TCP_CACHE_POLICY_HIT_LRU = 0x00000002, -TCP_CACHE_POLICY_HIT_EVICT = 0x00000003, -} TCP_CACHE_POLICIES; - -typedef enum TCP_CACHE_STORE_POLICIES { -TCP_CACHE_STORE_POLICY_MISS_LRU__SI__CI = 0x00000000, -TCP_CACHE_STORE_POLICY_WT_LRU__VI = 0x00000000, -TCP_CACHE_STORE_POLICY_MISS_EVICT__SI__CI = 0x00000001, -TCP_CACHE_STORE_POLICY_WT_EVICT__VI = 0x00000001, -} TCP_CACHE_STORE_POLICIES; - -typedef enum TCP_PERFCOUNT_SELECT { -TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES__SI = 0, -TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES__CI__VI = 0x00000000, -TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES__CI__VI = 0x00000001, -TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES__CI__VI = 0x00000002, -TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES__CI__VI = 0x00000003, -TCP_PERF_SEL_TD_TCP_STALL_CYCLES__CI__VI = 0x00000004, -TCP_PERF_SEL_TCR_TCP_STALL_CYCLES__CI__VI = 0x00000005, -TCP_PERF_SEL_LOD_STALL_CYCLES__CI__VI = 0x00000006, -TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES__CI__VI = 0x00000007, -TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES__CI__VI = 0x00000008, -TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES__CI__VI = 0x00000009, -TCP_PERF_SEL_ALLOC_STALL_CYCLES__CI__VI = 0x0000000a, -TCP_PERF_SEL_LFIFO_STALL_CYCLES__CI__VI = 0x0000000b, -TCP_PERF_SEL_RFIFO_STALL_CYCLES__CI__VI = 0x0000000c, -TCP_PERF_SEL_TCR_RDRET_STALL__CI__VI = 0x0000000d, -TCP_PERF_SEL_WRITE_CONFLICT_STALL__CI__VI = 0x0000000e, -TCP_PERF_SEL_HOLE_READ_STALL__CI__VI = 0x0000000f, -TCP_PERF_SEL_READCONFLICT_STALL_CYCLES__CI__VI = 0x00000010, -TCP_PERF_SEL_PENDING_STALL_CYCLES__CI__VI = 0x00000011, -TCP_PERF_SEL_READFIFO_STALL_CYCLES__CI__VI = 0x00000012, -TCP_PERF_SEL_TCP_LATENCY__CI__VI = 0x00000013, -TCP_PERF_SEL_TCC_READ_REQ_LATENCY__CI__VI = 0x00000014, -TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY__CI__VI = 0x00000015, -TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY__CI__VI = 0x00000016, -TCP_PERF_SEL_TCC_READ_REQ__CI__VI = 0x00000017, -TCP_PERF_SEL_TCC_WRITE_REQ__CI__VI = 0x00000018, -TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ__CI__VI = 0x00000019, -TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ__CI__VI = 0x0000001a, -TCP_PERF_SEL_TOTAL_LOCAL_READ__CI__VI = 0x0000001b, -TCP_PERF_SEL_TOTAL_GLOBAL_READ__CI__VI = 0x0000001c, -TCP_PERF_SEL_TOTAL_LOCAL_WRITE__CI__VI = 0x0000001d, -TCP_PERF_SEL_TOTAL_GLOBAL_WRITE__CI__VI = 0x0000001e, -TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET__CI__VI = 0x0000001f, -TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET__CI__VI = 0x00000020, -TCP_PERF_SEL_TOTAL_WBINVL1__CI__VI = 0x00000021, -TCP_PERF_SEL_IMG_READ_FMT_1__CI__VI = 0x00000022, -TCP_PERF_SEL_IMG_READ_FMT_8__CI__VI = 0x00000023, -TCP_PERF_SEL_IMG_READ_FMT_16__CI__VI = 0x00000024, -TCP_PERF_SEL_IMG_READ_FMT_32__CI__VI = 0x00000025, -TCP_PERF_SEL_IMG_READ_FMT_32_AS_8__CI__VI = 0x00000026, -TCP_PERF_SEL_IMG_READ_FMT_32_AS_16__CI__VI = 0x00000027, -TCP_PERF_SEL_IMG_READ_FMT_32_AS_128__CI__VI = 0x00000028, -TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE__CI__VI = 0x00000029, -TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE__CI__VI = 0x0000002a, -TCP_PERF_SEL_IMG_READ_FMT_96__CI__VI = 0x0000002b, -TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE__CI__VI = 0x0000002c, -TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE__CI__VI = 0x0000002d, -TCP_PERF_SEL_IMG_READ_FMT_BC1__CI__VI = 0x0000002e, -TCP_PERF_SEL_IMG_READ_FMT_BC2__CI__VI = 0x0000002f, -TCP_PERF_SEL_IMG_READ_FMT_BC3__CI__VI = 0x00000030, -TCP_PERF_SEL_IMG_READ_FMT_BC4__CI__VI = 0x00000031, -TCP_PERF_SEL_IMG_READ_FMT_BC5__CI__VI = 0x00000032, -TCP_PERF_SEL_IMG_READ_FMT_BC6__CI__VI = 0x00000033, -TCP_PERF_SEL_IMG_READ_FMT_BC7__CI__VI = 0x00000034, -TCP_PERF_SEL_IMG_READ_FMT_I8__CI__VI = 0x00000035, -TCP_PERF_SEL_IMG_READ_FMT_I16__CI__VI = 0x00000036, -TCP_PERF_SEL_IMG_READ_FMT_I32__CI__VI = 0x00000037, -TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8__CI__VI = 0x00000038, -TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16__CI__VI = 0x00000039, -TCP_PERF_SEL_IMG_READ_FMT_D8__CI__VI = 0x0000003a, -TCP_PERF_SEL_IMG_READ_FMT_D16__CI__VI = 0x0000003b, -TCP_PERF_SEL_IMG_READ_FMT_D32__CI__VI = 0x0000003c, -TCP_PERF_SEL_IMG_WRITE_FMT_8__CI__VI = 0x0000003d, -TCP_PERF_SEL_IMG_WRITE_FMT_16__CI__VI = 0x0000003e, -TCP_PERF_SEL_IMG_WRITE_FMT_32__CI__VI = 0x0000003f, -TCP_PERF_SEL_IMG_WRITE_FMT_64__CI__VI = 0x00000040, -TCP_PERF_SEL_IMG_WRITE_FMT_128__CI__VI = 0x00000041, -TCP_PERF_SEL_IMG_WRITE_FMT_D8__CI__VI = 0x00000042, -TCP_PERF_SEL_IMG_WRITE_FMT_D16__CI__VI = 0x00000043, -TCP_PERF_SEL_IMG_WRITE_FMT_D32__CI__VI = 0x00000044, -TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32__CI__VI = 0x00000045, -TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32__CI__VI = 0x00000046, -TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64__CI__VI = 0x00000047, -TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64__CI__VI = 0x00000048, -TCP_PERF_SEL_BUF_READ_FMT_8__CI__VI = 0x00000049, -TCP_PERF_SEL_BUF_READ_FMT_16__CI__VI = 0x0000004a, -TCP_PERF_SEL_BUF_READ_FMT_32__CI__VI = 0x0000004b, -TCP_PERF_SEL_BUF_WRITE_FMT_8__CI__VI = 0x0000004c, -TCP_PERF_SEL_BUF_WRITE_FMT_16__CI__VI = 0x0000004d, -TCP_PERF_SEL_BUF_WRITE_FMT_32__CI__VI = 0x0000004e, -TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32__CI__VI = 0x0000004f, -TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32__CI__VI = 0x00000050, -TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64__CI__VI = 0x00000051, -TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64__CI__VI = 0x00000052, -TCP_PERF_SEL_ARR_LINEAR_GENERAL__CI__VI = 0x00000053, -TCP_PERF_SEL_ARR_LINEAR_ALIGNED__CI__VI = 0x00000054, -TCP_PERF_SEL_ARR_1D_THIN1__CI__VI = 0x00000055, -TCP_PERF_SEL_ARR_1D_THICK__CI__VI = 0x00000056, -TCP_PERF_SEL_ARR_2D_THIN1__CI__VI = 0x00000057, -TCP_PERF_SEL_ARR_2D_THICK__CI__VI = 0x00000058, -TCP_PERF_SEL_ARR_2D_XTHICK__CI__VI = 0x00000059, -TCP_PERF_SEL_ARR_3D_THIN1__CI__VI = 0x0000005a, -TCP_PERF_SEL_ARR_3D_THICK__CI__VI = 0x0000005b, -TCP_PERF_SEL_ARR_3D_XTHICK__CI__VI = 0x0000005c, -TCP_PERF_SEL_DIM_1D__CI__VI = 0x0000005d, -TCP_PERF_SEL_DIM_2D__CI__VI = 0x0000005e, -TCP_PERF_SEL_DIM_3D__CI__VI = 0x0000005f, -TCP_PERF_SEL_DIM_1D_ARRAY__CI__VI = 0x00000060, -TCP_PERF_SEL_DIM_2D_ARRAY__CI__VI = 0x00000061, -TCP_PERF_SEL_DIM_2D_MSAA__CI__VI = 0x00000062, -TCP_PERF_SEL_DIM_2D_ARRAY_MSAA__CI__VI = 0x00000063, -TCP_PERF_SEL_DIM_CUBE_ARRAY__CI__VI = 0x00000064, -TCP_PERF_SEL_CP_TCP_INVALIDATE__CI__VI = 0x00000065, -TCP_PERF_SEL_TA_TCP_STATE_READ__CI__VI = 0x00000066, -TCP_PERF_SEL_TAGRAM0_REQ__CI__VI = 0x00000067, -TCP_PERF_SEL_TAGRAM1_REQ__CI__VI = 0x00000068, -TCP_PERF_SEL_TAGRAM2_REQ__CI__VI = 0x00000069, -TCP_PERF_SEL_TAGRAM3_REQ__CI__VI = 0x0000006a, -TCP_PERF_SEL_GATE_EN1__CI__VI = 0x0000006b, -TCP_PERF_SEL_GATE_EN2__CI__VI = 0x0000006c, -TCP_PERF_SEL_CORE_REG_SCLK_VLD__CI__VI = 0x0000006d, -TCP_PERF_SEL_TCC_REQ__CI__VI = 0x0000006e, -TCP_PERF_SEL_TCC_NON_READ_REQ__CI__VI = 0x0000006f, -TCP_PERF_SEL_TCC_BYPASS_READ_REQ__CI__VI = 0x00000070, -TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ__CI__VI = 0x00000071, -TCP_PERF_SEL_TCC_VOLATILE_READ_REQ__CI__VI = 0x00000072, -TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ__CI__VI = 0x00000073, -TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ__CI__VI = 0x00000074, -TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ__CI__VI = 0x00000075, -TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ__CI__VI = 0x00000076, -TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ__CI__VI = 0x00000077, -TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ__CI__VI = 0x00000078, -TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ__CI__VI = 0x00000079, -TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ__CI__VI = 0x0000007a, -TCP_PERF_SEL_TCC_ATOMIC_REQ__CI__VI = 0x0000007b, -TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ__CI__VI = 0x0000007c, -TCP_PERF_SEL_TCC_DATA_BUS_BUSY__CI__VI = 0x0000007d, -TCP_PERF_SEL_TOTAL_ACCESSES__CI__VI = 0x0000007e, -TCP_PERF_SEL_TOTAL_READ__CI__VI = 0x0000007f, -TCP_PERF_SEL_TOTAL_HIT_LRU_READ__CI__VI = 0x00000080, -TCP_PERF_SEL_TOTAL_HIT_EVICT_READ__CI__VI = 0x00000081, -TCP_PERF_SEL_TOTAL_MISS_LRU_READ__CI__VI = 0x00000082, -TCP_PERF_SEL_TOTAL_MISS_EVICT_READ__CI__VI = 0x00000083, -TCP_PERF_SEL_TOTAL_NON_READ__CI__VI = 0x00000084, -TCP_PERF_SEL_TOTAL_WRITE__CI__VI = 0x00000085, -TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE__CI__VI = 0x00000086, -TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE__CI__VI = 0x00000087, -TCP_PERF_SEL_TOTAL_WBINVL1_VOL__CI__VI = 0x00000088, -TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES__CI__VI = 0x00000089, -TCP_PERF_SEL_DISPLAY_MICROTILING__CI__VI = 0x0000008a, -TCP_PERF_SEL_THIN_MICROTILING__CI__VI = 0x0000008b, -TCP_PERF_SEL_DEPTH_MICROTILING__CI__VI = 0x0000008c, -TCP_PERF_SEL_ARR_PRT_THIN1__CI__VI = 0x0000008d, -TCP_PERF_SEL_ARR_PRT_2D_THIN1__CI__VI = 0x0000008e, -TCP_PERF_SEL_ARR_PRT_3D_THIN1__CI__VI = 0x0000008f, -TCP_PERF_SEL_ARR_PRT_THICK__CI__VI = 0x00000090, -TCP_PERF_SEL_ARR_PRT_2D_THICK__CI__VI = 0x00000091, -TCP_PERF_SEL_ARR_PRT_3D_THICK__CI__VI = 0x00000092, -TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL__CI__VI = 0x00000093, -TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL__CI__VI = 0x00000094, -TCP_PERF_SEL_UNALIGNED__CI__VI = 0x00000095, -TCP_PERF_SEL_ROTATED_MICROTILING__CI__VI = 0x00000096, -TCP_PERF_SEL_THICK_MICROTILING__CI__VI = 0x00000097, -TCP_PERF_SEL_ATC__CI__VI = 0x00000098, -TCP_PERF_SEL_POWER_STALL__CI__VI = 0x00000099, -TCP_PERF_SEL_RESERVED_154__VI = 0x0000009a, -TCP_PERF_SEL_TCC_LRU_REQ__VI = 0x0000009b, -TCP_PERF_SEL_TCC_STREAM_REQ__VI = 0x0000009c, -TCP_PERF_SEL_TCC_NC_READ_REQ__VI = 0x0000009d, -TCP_PERF_SEL_TCC_NC_WRITE_REQ__VI = 0x0000009e, -TCP_PERF_SEL_TCC_NC_ATOMIC_REQ__VI = 0x0000009f, -TCP_PERF_SEL_TCC_UC_READ_REQ__VI = 0x000000a0, -TCP_PERF_SEL_TCC_UC_WRITE_REQ__VI = 0x000000a1, -TCP_PERF_SEL_TCC_UC_ATOMIC_REQ__VI = 0x000000a2, -TCP_PERF_SEL_TCC_CC_READ_REQ__VI = 0x000000a3, -TCP_PERF_SEL_TCC_CC_WRITE_REQ__VI = 0x000000a4, -TCP_PERF_SEL_TCC_CC_ATOMIC_REQ__VI = 0x000000a5, -TCP_PERF_SEL_TCC_DCC_REQ__VI = 0x000000a6, -TCP_PERF_SEL_TCC_PHYSICAL_REQ__VI = 0x000000a7, -TCP_PERF_SEL_UNORDERED_MTYPE_STALL__VI = 0x000000a8, -TCP_PERF_SEL_VOLATILE__VI = 0x000000a9, -TCP_PERF_SEL_TC_TA_XNACK_STALL__VI = 0x000000aa, -TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL__VI = 0x000000ab, -TCP_PERF_SEL_SHOOTDOWN__VI = 0x000000ac, -TCP_PERF_SEL_GATCL1_TRANSLATION_MISS__VI = 0x000000ad, -TCP_PERF_SEL_GATCL1_PERMISSION_MISS__VI = 0x000000ae, -TCP_PERF_SEL_GATCL1_REQUEST__VI = 0x000000af, -TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX__VI = 0x000000b0, -TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT__VI = 0x000000b1, -TCP_PERF_SEL_GATCL1_LFIFO_FULL__VI = 0x000000b2, -TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES__VI = 0x000000b3, -TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT__VI = 0x000000b5, -TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL__VI = 0x000000b6, -TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES__SI = 1, -TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES__SI = 2, -TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES__SI = 3, -TCP_PERF_SEL_TD_TCP_STALL_CYCLES__SI = 4, -TCP_PERF_SEL_TCR_TCP_STALL_CYCLES__SI = 5, -TCP_PERF_SEL_LOD_STALL_CYCLES__SI = 6, -TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES__SI = 7, -TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES__SI = 8, -TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES__SI = 9, -TCP_PERF_SEL_ALLOC_STALL_CYCLES__SI = 10, -TCP_PERF_SEL_LFIFO_STALL_CYCLES__SI = 11, -TCP_PERF_SEL_RFIFO_STALL_CYCLES__SI = 12, -TCP_PERF_SEL_TCR_RDRET_STALL__SI = 13, -TCP_PERF_SEL_WRITE_CONFLICT_STALL__SI = 14, -TCP_PERF_SEL_HOLE_READ_STALL__SI = 15, -TCP_PERF_SEL_READCONFLICT_STALL_CYCLES__SI = 16, -TCP_PERF_SEL_PENDING_STALL_CYCLES__SI = 17, -TCP_PERF_SEL_READFIFO_STALL_CYCLES__SI = 18, -TCP_PERF_SEL_TCP_LATENCY__SI = 19, -TCP_PERF_SEL_TCC_READ_REQ_LATENCY__SI = 20, -TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY__SI = 21, -TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY__SI = 22, -TCP_PERF_SEL_TCC_READ_REQ__SI = 23, -TCP_PERF_SEL_TCC_WRITE_REQ__SI = 24, -TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ__SI = 25, -TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ__SI = 26, -TCP_PERF_SEL_TOTAL_LOCAL_READ__SI = 27, -TCP_PERF_SEL_TOTAL_GLOBAL_READ__SI = 28, -TCP_PERF_SEL_TOTAL_LOCAL_WRITE__SI = 29, -TCP_PERF_SEL_TOTAL_GLOBAL_WRITE__SI = 30, -TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET__SI = 31, -TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET__SI = 32, -TCP_PERF_SEL_TOTAL_WBINVL1__SI = 33, -TCP_PERF_SEL_IMG_READ_FMT_1__SI = 34, -TCP_PERF_SEL_IMG_READ_FMT_8__SI = 35, -TCP_PERF_SEL_IMG_READ_FMT_16__SI = 36, -TCP_PERF_SEL_IMG_READ_FMT_32__SI = 37, -TCP_PERF_SEL_IMG_READ_FMT_32_AS_8__SI = 38, -TCP_PERF_SEL_IMG_READ_FMT_32_AS_16__SI = 39, -TCP_PERF_SEL_IMG_READ_FMT_32_AS_128__SI = 40, -TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE__SI = 41, -TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE__SI = 42, -TCP_PERF_SEL_IMG_READ_FMT_96__SI = 43, -TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE__SI = 44, -TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE__SI = 45, -TCP_PERF_SEL_IMG_READ_FMT_BC1__SI = 46, -TCP_PERF_SEL_IMG_READ_FMT_BC2__SI = 47, -TCP_PERF_SEL_IMG_READ_FMT_BC3__SI = 48, -TCP_PERF_SEL_IMG_READ_FMT_BC4__SI = 49, -TCP_PERF_SEL_IMG_READ_FMT_BC5__SI = 50, -TCP_PERF_SEL_IMG_READ_FMT_BC6__SI = 51, -TCP_PERF_SEL_IMG_READ_FMT_BC7__SI = 52, -TCP_PERF_SEL_IMG_READ_FMT_I8__SI = 53, -TCP_PERF_SEL_IMG_READ_FMT_I16__SI = 54, -TCP_PERF_SEL_IMG_READ_FMT_I32__SI = 55, -TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8__SI = 56, -TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16__SI = 57, -TCP_PERF_SEL_IMG_READ_FMT_D8__SI = 58, -TCP_PERF_SEL_IMG_READ_FMT_D16__SI = 59, -TCP_PERF_SEL_IMG_READ_FMT_D32__SI = 60, -TCP_PERF_SEL_IMG_WRITE_FMT_8__SI = 61, -TCP_PERF_SEL_IMG_WRITE_FMT_16__SI = 62, -TCP_PERF_SEL_IMG_WRITE_FMT_32__SI = 63, -TCP_PERF_SEL_IMG_WRITE_FMT_64__SI = 64, -TCP_PERF_SEL_IMG_WRITE_FMT_128__SI = 65, -TCP_PERF_SEL_IMG_WRITE_FMT_D8__SI = 66, -TCP_PERF_SEL_IMG_WRITE_FMT_D16__SI = 67, -TCP_PERF_SEL_IMG_WRITE_FMT_D32__SI = 68, -TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32__SI = 69, -TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32__SI = 70, -TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64__SI = 71, -TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64__SI = 72, -TCP_PERF_SEL_BUF_READ_FMT_8__SI = 73, -TCP_PERF_SEL_BUF_READ_FMT_16__SI = 74, -TCP_PERF_SEL_BUF_READ_FMT_32__SI = 75, -TCP_PERF_SEL_BUF_WRITE_FMT_8__SI = 76, -TCP_PERF_SEL_BUF_WRITE_FMT_16__SI = 77, -TCP_PERF_SEL_BUF_WRITE_FMT_32__SI = 78, -TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32__SI = 79, -TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32__SI = 80, -TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64__SI = 81, -TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64__SI = 82, -TCP_PERF_SEL_ARR_LINEAR_GENERAL__SI = 83, -TCP_PERF_SEL_ARR_LINEAR_ALIGNED__SI = 84, -TCP_PERF_SEL_ARR_1D_THIN1__SI = 85, -TCP_PERF_SEL_ARR_1D_THICK__SI = 86, -TCP_PERF_SEL_ARR_2D_THIN1__SI = 87, -TCP_PERF_SEL_ARR_2D_THICK__SI = 88, -TCP_PERF_SEL_ARR_2D_XTHICK__SI = 89, -TCP_PERF_SEL_ARR_3D_THIN1__SI = 90, -TCP_PERF_SEL_ARR_3D_THICK__SI = 91, -TCP_PERF_SEL_ARR_3D_XTHICK__SI = 92, -TCP_PERF_SEL_DIM_1D__SI = 93, -TCP_PERF_SEL_DIM_2D__SI = 94, -TCP_PERF_SEL_DIM_3D__SI = 95, -TCP_PERF_SEL_DIM_1D_ARRAY__SI = 96, -TCP_PERF_SEL_DIM_2D_ARRAY__SI = 97, -TCP_PERF_SEL_DIM_2D_MSAA__SI = 98, -TCP_PERF_SEL_DIM_2D_ARRAY_MSAA__SI = 99, -TCP_PERF_SEL_DIM_CUBE_ARRAY__SI = 100, -TCP_PERF_SEL_CP_TCP_INVALIDATE__SI = 101, -TCP_PERF_SEL_TA_TCP_STATE_READ__SI = 102, -TCP_PERF_SEL_TAGRAM0_REQ__SI = 103, -TCP_PERF_SEL_TAGRAM1_REQ__SI = 104, -TCP_PERF_SEL_TAGRAM2_REQ__SI = 105, -TCP_PERF_SEL_TAGRAM3_REQ__SI = 106, -TCP_PERF_SEL_GATE_EN1__SI = 107, -TCP_PERF_SEL_GATE_EN2__SI = 108, -TCP_PERF_SEL_CORE_REG_SCLK_VLD__SI = 109, -} TCP_PERFCOUNT_SELECT; - -typedef enum TCP_WATCH_MODES { -TCP_WATCH_MODE_READ = 0x00000000, -TCP_WATCH_MODE_NONREAD = 0x00000001, -TCP_WATCH_MODE_ATOMIC = 0x00000002, -TCP_WATCH_MODE_ALL = 0x00000003, -} TCP_WATCH_MODES; - -typedef enum TCS_PERF_SEL { -TCS_PERF_SEL_NONE = 0x00000000, -TCS_PERF_SEL_CYCLE = 0x00000001, -TCS_PERF_SEL_BUSY = 0x00000002, -TCS_PERF_SEL_REQ = 0x00000003, -TCS_PERF_SEL_READ = 0x00000004, -TCS_PERF_SEL_WRITE = 0x00000005, -TCS_PERF_SEL_ATOMIC = 0x00000006, -TCS_PERF_SEL_HOLE_FIFO_FULL = 0x00000007, -TCS_PERF_SEL_REQ_FIFO_FULL = 0x00000008, -TCS_PERF_SEL_REQ_CREDIT_STALL = 0x00000009, -TCS_PERF_SEL_REQ_NO_SRC_DATA_STALL = 0x0000000a, -TCS_PERF_SEL_REQ_STALL = 0x0000000b, -TCS_PERF_SEL_TCS_CHUB_REQ_SEND = 0x0000000c, -TCS_PERF_SEL_CHUB_TCS_RET_SEND = 0x0000000d, -TCS_PERF_SEL_RETURN_ACK = 0x0000000e, -TCS_PERF_SEL_RETURN_DATA = 0x0000000f, -TCS_PERF_SEL_IB_TOTAL_REQUESTS_STALL = 0x00000010, -TCS_PERF_SEL_IB_STALL = 0x00000011, -TCS_PERF_SEL_TCA_LEVEL = 0x00000012, -TCS_PERF_SEL_HOLE_LEVEL = 0x00000013, -TCS_PERF_SEL_CHUB_LEVEL = 0x00000014, -TCS_PERF_SEL_CLIENT0_REQ = 0x00000040, -TCS_PERF_SEL_CLIENT1_REQ = 0x00000041, -TCS_PERF_SEL_CLIENT2_REQ = 0x00000042, -TCS_PERF_SEL_CLIENT3_REQ = 0x00000043, -TCS_PERF_SEL_CLIENT4_REQ = 0x00000044, -TCS_PERF_SEL_CLIENT5_REQ = 0x00000045, -TCS_PERF_SEL_CLIENT6_REQ = 0x00000046, -TCS_PERF_SEL_CLIENT7_REQ = 0x00000047, -TCS_PERF_SEL_CLIENT8_REQ = 0x00000048, -TCS_PERF_SEL_CLIENT9_REQ = 0x00000049, -TCS_PERF_SEL_CLIENT10_REQ = 0x0000004a, -TCS_PERF_SEL_CLIENT11_REQ = 0x0000004b, -TCS_PERF_SEL_CLIENT12_REQ = 0x0000004c, -TCS_PERF_SEL_CLIENT13_REQ = 0x0000004d, -TCS_PERF_SEL_CLIENT14_REQ = 0x0000004e, -TCS_PERF_SEL_CLIENT15_REQ = 0x0000004f, -TCS_PERF_SEL_CLIENT16_REQ = 0x00000050, -TCS_PERF_SEL_CLIENT17_REQ = 0x00000051, -TCS_PERF_SEL_CLIENT18_REQ = 0x00000052, -TCS_PERF_SEL_CLIENT19_REQ = 0x00000053, -TCS_PERF_SEL_CLIENT20_REQ = 0x00000054, -TCS_PERF_SEL_CLIENT21_REQ = 0x00000055, -TCS_PERF_SEL_CLIENT22_REQ = 0x00000056, -TCS_PERF_SEL_CLIENT23_REQ = 0x00000057, -TCS_PERF_SEL_CLIENT24_REQ = 0x00000058, -TCS_PERF_SEL_CLIENT25_REQ = 0x00000059, -TCS_PERF_SEL_CLIENT26_REQ = 0x0000005a, -TCS_PERF_SEL_CLIENT27_REQ = 0x0000005b, -TCS_PERF_SEL_CLIENT28_REQ = 0x0000005c, -TCS_PERF_SEL_CLIENT29_REQ = 0x0000005d, -TCS_PERF_SEL_CLIENT30_REQ = 0x0000005e, -TCS_PERF_SEL_CLIENT31_REQ = 0x0000005f, -TCS_PERF_SEL_CLIENT32_REQ = 0x00000060, -TCS_PERF_SEL_CLIENT33_REQ = 0x00000061, -TCS_PERF_SEL_CLIENT34_REQ = 0x00000062, -TCS_PERF_SEL_CLIENT35_REQ = 0x00000063, -TCS_PERF_SEL_CLIENT36_REQ = 0x00000064, -TCS_PERF_SEL_CLIENT37_REQ = 0x00000065, -TCS_PERF_SEL_CLIENT38_REQ = 0x00000066, -TCS_PERF_SEL_CLIENT39_REQ = 0x00000067, -TCS_PERF_SEL_CLIENT40_REQ = 0x00000068, -TCS_PERF_SEL_CLIENT41_REQ = 0x00000069, -TCS_PERF_SEL_CLIENT42_REQ = 0x0000006a, -TCS_PERF_SEL_CLIENT43_REQ = 0x0000006b, -TCS_PERF_SEL_CLIENT44_REQ = 0x0000006c, -TCS_PERF_SEL_CLIENT45_REQ = 0x0000006d, -TCS_PERF_SEL_CLIENT46_REQ = 0x0000006e, -TCS_PERF_SEL_CLIENT47_REQ = 0x0000006f, -TCS_PERF_SEL_CLIENT48_REQ = 0x00000070, -TCS_PERF_SEL_CLIENT49_REQ = 0x00000071, -TCS_PERF_SEL_CLIENT50_REQ = 0x00000072, -TCS_PERF_SEL_CLIENT51_REQ = 0x00000073, -TCS_PERF_SEL_CLIENT52_REQ = 0x00000074, -TCS_PERF_SEL_CLIENT53_REQ = 0x00000075, -TCS_PERF_SEL_CLIENT54_REQ = 0x00000076, -TCS_PERF_SEL_CLIENT55_REQ = 0x00000077, -TCS_PERF_SEL_CLIENT56_REQ = 0x00000078, -TCS_PERF_SEL_CLIENT57_REQ = 0x00000079, -TCS_PERF_SEL_CLIENT58_REQ = 0x0000007a, -TCS_PERF_SEL_CLIENT59_REQ = 0x0000007b, -TCS_PERF_SEL_CLIENT60_REQ = 0x0000007c, -TCS_PERF_SEL_CLIENT61_REQ = 0x0000007d, -TCS_PERF_SEL_CLIENT62_REQ = 0x0000007e, -TCS_PERF_SEL_CLIENT63_REQ = 0x0000007f, -} TCS_PERF_SEL; - -typedef enum TC_CHUB_REQ_CREDITS_ENUM { -TC_CHUB_REQ_CREDITS = 0x00000010, -} TC_CHUB_REQ_CREDITS_ENUM; - -typedef enum TC_NACKS { -TC_NACK_NO_FAULT = 0x00000000, -TC_NACK_PAGE_FAULT = 0x00000001, -TC_NACK_PROTECTION_FAULT = 0x00000002, -TC_NACK_DATA_ERROR = 0x00000003, -} TC_NACKS; - -typedef enum TC_OP { -TC_OP_READ = 0x00000000, -TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, -TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, -TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, -TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004, -TC_OP_RESERVED_FOP_RTN_32_1 = 0x00000005, -TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006, -TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, -TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0x0000000c, -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d, -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, -TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, -TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010, -TC_OP_ATOMIC_SMIN_RTN_32__CI__VI = 0x00000011, -TC_OP_ATOMIC_SMIN_RTN_32__SI = 0x00000012, -TC_OP_ATOMIC_UMIN_RTN_32__CI__VI = 0x00000012, -TC_OP_ATOMIC_UMIN_RTN_32__SI = 0x00000013, -TC_OP_ATOMIC_SMAX_RTN_32__CI__VI = 0x00000013, -TC_OP_ATOMIC_SMAX_RTN_32__SI = 0x00000014, -TC_OP_ATOMIC_UMAX_RTN_32__CI__VI = 0x00000014, -TC_OP_ATOMIC_UMAX_RTN_32__SI = 0x00000015, -TC_OP_ATOMIC_AND_RTN_32__CI__VI = 0x00000015, -TC_OP_ATOMIC_AND_RTN_32__SI = 0x00000016, -TC_OP_ATOMIC_OR_RTN_32__CI__VI = 0x00000016, -TC_OP_ATOMIC_OR_RTN_32__SI = 0x00000017, -TC_OP_ATOMIC_XOR_RTN_32__CI__VI = 0x00000017, -TC_OP_ATOMIC_XOR_RTN_32__SI = 0x00000018, -TC_OP_ATOMIC_INC_RTN_32__CI__VI = 0x00000018, -TC_OP_ATOMIC_INC_RTN_32__SI = 0x00000019, -TC_OP_ATOMIC_DEC_RTN_32__CI__VI = 0x00000019, -TC_OP_ATOMIC_DEC_RTN_32__SI = 0x0000001a, -TC_OP_WBINVL1_VOL__CI__VI = 0x0000001a, -TC_OP_RESERVED_NON_FLOAT_RTN_32_0__SI__CI = 0x0000001b, -TC_OP_WBINVL1_SD__VI = 0x0000001b, -TC_OP_RESERVED_NON_FLOAT_RTN_32_1__SI__CI = 0x0000001c, -TC_OP_RESERVED_NON_FLOAT_RTN_32_0__VI = 0x0000001c, -TC_OP_RESERVED_NON_FLOAT_RTN_32_2__SI__CI = 0x0000001d, -TC_OP_RESERVED_NON_FLOAT_RTN_32_1__VI = 0x0000001d, -TC_OP_RESERVED_NON_FLOAT_RTN_32_3__SI__CI = 0x0000001e, -TC_OP_RESERVED_NON_FLOAT_RTN_32_2__VI = 0x0000001e, -TC_OP_RESERVED_NON_FLOAT_RTN_32_4__SI__CI = 0x0000001f, -TC_OP_RESERVED_NON_FLOAT_RTN_32_3__VI = 0x0000001f, -TC_OP_WRITE = 0x00000020, -TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, -TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, -TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, -TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024, -TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025, -TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026, -TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, -TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0__SI__CI = 0x0000002c, -TC_OP_WBINVL2_SD__VI = 0x0000002c, -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1__SI__CI = 0x0000002d, -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0__VI = 0x0000002d, -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_2__SI__CI = 0x0000002e, -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1__VI = 0x0000002e, -TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, -TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030, -TC_OP_ATOMIC_SMIN_RTN_64__CI__VI = 0x00000031, -TC_OP_ATOMIC_SMIN_RTN_64__SI = 0x00000032, -TC_OP_ATOMIC_UMIN_RTN_64__CI__VI = 0x00000032, -TC_OP_ATOMIC_UMIN_RTN_64__SI = 0x00000033, -TC_OP_ATOMIC_SMAX_RTN_64__CI__VI = 0x00000033, -TC_OP_ATOMIC_SMAX_RTN_64__SI = 0x00000034, -TC_OP_ATOMIC_UMAX_RTN_64__CI__VI = 0x00000034, -TC_OP_ATOMIC_UMAX_RTN_64__SI = 0x00000035, -TC_OP_ATOMIC_AND_RTN_64__CI__VI = 0x00000035, -TC_OP_ATOMIC_AND_RTN_64__SI = 0x00000036, -TC_OP_ATOMIC_OR_RTN_64__CI__VI = 0x00000036, -TC_OP_ATOMIC_OR_RTN_64__SI = 0x00000037, -TC_OP_ATOMIC_XOR_RTN_64__CI__VI = 0x00000037, -TC_OP_ATOMIC_XOR_RTN_64__SI = 0x00000038, -TC_OP_ATOMIC_INC_RTN_64__CI__VI = 0x00000038, -TC_OP_ATOMIC_INC_RTN_64__SI = 0x00000039, -TC_OP_ATOMIC_DEC_RTN_64__CI__VI = 0x00000039, -TC_OP_ATOMIC_DEC_RTN_64__SI = 0x0000003a, -TC_OP_WBL2_VOL__CI = 0x0000003a, -TC_OP_WBL2_NC__VI = 0x0000003a, -TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x0000003b, -TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c, -TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d, -TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e, -TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f, -TC_OP_WBINVL1 = 0x00000040, -TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, -TC_OP_ATOMIC_FMIN_32 = 0x00000042, -TC_OP_ATOMIC_FMAX_32 = 0x00000043, -TC_OP_RESERVED_FOP_32_0 = 0x00000044, -TC_OP_RESERVED_FOP_32_1 = 0x00000045, -TC_OP_RESERVED_FOP_32_2 = 0x00000046, -TC_OP_ATOMIC_SWAP_32 = 0x00000047, -TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048, -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, -TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x0000004c, -TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x0000004d, -TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e, -TC_OP_ATOMIC_ADD_32 = 0x0000004f, -TC_OP_ATOMIC_SUB_32 = 0x00000050, -TC_OP_ATOMIC_SMIN_32__CI__VI = 0x00000051, -TC_OP_ATOMIC_SMIN_32__SI = 0x00000052, -TC_OP_ATOMIC_UMIN_32__CI__VI = 0x00000052, -TC_OP_ATOMIC_UMIN_32__SI = 0x00000053, -TC_OP_ATOMIC_SMAX_32__CI__VI = 0x00000053, -TC_OP_ATOMIC_SMAX_32__SI = 0x00000054, -TC_OP_ATOMIC_UMAX_32__CI__VI = 0x00000054, -TC_OP_ATOMIC_UMAX_32__SI = 0x00000055, -TC_OP_ATOMIC_AND_32__CI__VI = 0x00000055, -TC_OP_ATOMIC_AND_32__SI = 0x00000056, -TC_OP_ATOMIC_OR_32__CI__VI = 0x00000056, -TC_OP_ATOMIC_OR_32__SI = 0x00000057, -TC_OP_ATOMIC_XOR_32__CI__VI = 0x00000057, -TC_OP_ATOMIC_XOR_32__SI = 0x00000058, -TC_OP_ATOMIC_INC_32__CI__VI = 0x00000058, -TC_OP_ATOMIC_INC_32__SI = 0x00000059, -TC_OP_ATOMIC_DEC_32__CI__VI = 0x00000059, -TC_OP_ATOMIC_DEC_32__SI = 0x0000005a, -TC_OP_INVL2_VOL__CI = 0x0000005a, -TC_OP_INVL2_NC__VI = 0x0000005a, -TC_OP_RESERVED_NON_FLOAT_32_0 = 0x0000005b, -TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c, -TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d, -TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e, -TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f, -TC_OP_WBINVL2 = 0x00000060, -TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, -TC_OP_ATOMIC_FMIN_64 = 0x00000062, -TC_OP_ATOMIC_FMAX_64 = 0x00000063, -TC_OP_RESERVED_FOP_64_0 = 0x00000064, -TC_OP_RESERVED_FOP_64_1 = 0x00000065, -TC_OP_RESERVED_FOP_64_2 = 0x00000066, -TC_OP_ATOMIC_SWAP_64 = 0x00000067, -TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068, -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c, -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d, -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e, -TC_OP_ATOMIC_ADD_64 = 0x0000006f, -TC_OP_ATOMIC_SUB_64 = 0x00000070, -TC_OP_ATOMIC_SMIN_64__CI__VI = 0x00000071, -TC_OP_ATOMIC_SMIN_64__SI = 0x00000072, -TC_OP_ATOMIC_UMIN_64__CI__VI = 0x00000072, -TC_OP_ATOMIC_UMIN_64__SI = 0x00000073, -TC_OP_ATOMIC_SMAX_64__CI__VI = 0x00000073, -TC_OP_ATOMIC_SMAX_64__SI = 0x00000074, -TC_OP_ATOMIC_UMAX_64__CI__VI = 0x00000074, -TC_OP_ATOMIC_UMAX_64__SI = 0x00000075, -TC_OP_ATOMIC_AND_64__CI__VI = 0x00000075, -TC_OP_ATOMIC_AND_64__SI = 0x00000076, -TC_OP_ATOMIC_OR_64__CI__VI = 0x00000076, -TC_OP_ATOMIC_OR_64__SI = 0x00000077, -TC_OP_ATOMIC_XOR_64__CI__VI = 0x00000077, -TC_OP_ATOMIC_XOR_64__SI = 0x00000078, -TC_OP_ATOMIC_INC_64__CI__VI = 0x00000078, -TC_OP_ATOMIC_INC_64__SI = 0x00000079, -TC_OP_ATOMIC_DEC_64__CI__VI = 0x00000079, -TC_OP_ATOMIC_DEC_64__SI = 0x0000007a, -TC_OP_INVL1L2_VOL__CI = 0x0000007a, -TC_OP_WBINVL2_NC__VI = 0x0000007a, -TC_OP_RESERVED_NON_FLOAT_64_0 = 0x0000007b, -TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c, -TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d, -TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e, -TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f, -} TC_OP; - -typedef enum TC_OP_MASKS { -TC_OP_MASK_FLUSH_DENROM = 0x00000008, -TC_OP_MASK_64 = 0x00000020, -TC_OP_MASK_NO_RTN = 0x00000040, -} TC_OP_MASKS; - -typedef enum TD_PERFCOUNT_SEL { -TD_PERF_SEL_td_busy__SI__CI = 0x00000000, -TD_PERF_SEL_none__VI = 0x00000000, -TD_PERF_SEL_input_busy__SI__CI = 0x00000001, -TD_PERF_SEL_td_busy__VI = 0x00000001, -TD_PERF_SEL_output_busy__SI__CI = 0x00000002, -TD_PERF_SEL_input_busy__VI = 0x00000002, -TD_PERF_SEL_lerp_busy__SI__CI = 0x00000003, -TD_PERF_SEL_output_busy__VI = 0x00000003, -TD_PERF_SEL_RESERVED_4__SI__CI = 0x00000004, -TD_PERF_SEL_lerp_busy__VI = 0x00000004, -TD_PERF_SEL_reg_sclk_vld = 0x00000005, -TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x00000006, -TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x00000007, -TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x00000008, -TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x00000009, -TD_PERF_SEL_tc_td_fifo_full = 0x0000000a, -TD_PERF_SEL_constant_state_full = 0x0000000b, -TD_PERF_SEL_sample_state_full = 0x0000000c, -TD_PERF_SEL_output_fifo_full = 0x0000000d, -TD_PERF_SEL_RESERVED_14 = 0x0000000e, -TD_PERF_SEL_tc_stall = 0x0000000f, -TD_PERF_SEL_pc_stall = 0x00000010, -TD_PERF_SEL_gds_stall = 0x00000011, -TD_PERF_SEL_RESERVED_18 = 0x00000012, -TD_PERF_SEL_RESERVED_19 = 0x00000013, -TD_PERF_SEL_gather4_wavefront = 0x00000014, -TD_PERF_SEL_sample_c_wavefront = 0x00000015, -TD_PERF_SEL_load_wavefront = 0x00000016, -TD_PERF_SEL_atomic_wavefront = 0x00000017, -TD_PERF_SEL_store_wavefront = 0x00000018, -TD_PERF_SEL_ldfptr_wavefront = 0x00000019, -TD_PERF_SEL_RESERVED_26 = 0x0000001a, -TD_PERF_SEL_RESERVED_27 = 0x0000001b, -TD_PERF_SEL_RESERVED_28__SI__CI = 0x0000001c, -TD_PERF_SEL_d16_en_wavefront__VI = 0x0000001c, -TD_PERF_SEL_RESERVED_29__SI__CI = 0x0000001d, -TD_PERF_SEL_bicubic_filter_wavefront__VI = 0x0000001d, -TD_PERF_SEL_bypass_filter_wavefront = 0x0000001e, -TD_PERF_SEL_min_max_filter_wavefront = 0x0000001f, -TD_PERF_SEL_coalescable_wavefront = 0x00000020, -TD_PERF_SEL_coalesced_phase = 0x00000021, -TD_PERF_SEL_four_phase_wavefront = 0x00000022, -TD_PERF_SEL_eight_phase_wavefront = 0x00000023, -TD_PERF_SEL_sixteen_phase_wavefront = 0x00000024, -TD_PERF_SEL_four_phase_forward_wavefront = 0x00000025, -TD_PERF_SEL_write_ack_wavefront = 0x00000026, -TD_PERF_SEL_RESERVED_39 = 0x00000027, -TD_PERF_SEL_user_defined_border = 0x00000028, -TD_PERF_SEL_white_border = 0x00000029, -TD_PERF_SEL_opaque_black_border = 0x0000002a, -TD_PERF_SEL_RESERVED_43 = 0x0000002b, -TD_PERF_SEL_RESERVED_44 = 0x0000002c, -TD_PERF_SEL_nack = 0x0000002d, -TD_PERF_SEL_consume_gds_traffic__SI = 0x0000002e, -TD_PERF_SEL_td_sp_traffic__CI__VI = 0x0000002e, -TD_PERF_SEL_addresscmd_poison__SI = 0x0000002f, -TD_PERF_SEL_consume_gds_traffic__CI__VI = 0x0000002f, -TD_PERF_SEL_data_poison__SI = 0x00000030, -TD_PERF_SEL_addresscmd_poison__CI__VI = 0x00000030, -TD_PERF_SEL_data_poison__CI__VI = 0x00000031, -TD_PERF_SEL_start_cycle_0__CI__VI = 0x00000032, -TD_PERF_SEL_start_cycle_1__CI__VI = 0x00000033, -TD_PERF_SEL_start_cycle_2__CI__VI = 0x00000034, -TD_PERF_SEL_start_cycle_3__CI__VI = 0x00000035, -TD_PERF_SEL_null_cycle_output__CI__VI = 0x00000036, -} TD_PERFCOUNT_SEL; - -typedef enum TEX_BORDER_COLOR_TYPE { -TEX_BorderColor_TransparentBlack = 0x00000000, -TEX_BorderColor_OpaqueBlack = 0x00000001, -TEX_BorderColor_OpaqueWhite = 0x00000002, -TEX_BorderColor_Register = 0x00000003, -} TEX_BORDER_COLOR_TYPE; - -typedef enum TEX_CHROMA_KEY { -TEX_ChromaKey_Disabled = 0x00000000, -TEX_ChromaKey_Kill = 0x00000001, -TEX_ChromaKey_Blend = 0x00000002, -TEX_ChromaKey_RESERVED_3 = 0x00000003, -} TEX_CHROMA_KEY; - -typedef enum TEX_CLAMP { -TEX_Clamp_Repeat = 0x00000000, -TEX_Clamp_Mirror = 0x00000001, -TEX_Clamp_ClampToLast = 0x00000002, -TEX_Clamp_MirrorOnceToLast = 0x00000003, -TEX_Clamp_ClampHalfToBorder = 0x00000004, -TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005, -TEX_Clamp_ClampToBorder = 0x00000006, -TEX_Clamp_MirrorOnceToBorder = 0x00000007, -} TEX_CLAMP; - -typedef enum TEX_COORD_TYPE { -TEX_CoordType_Unnormalized = 0x00000000, -TEX_CoordType_Normalized = 0x00000001, -} TEX_COORD_TYPE; - -typedef enum TEX_DEPTH_COMPARE_FUNCTION { -TEX_DepthCompareFunction_Never = 0x00000000, -TEX_DepthCompareFunction_Less = 0x00000001, -TEX_DepthCompareFunction_Equal = 0x00000002, -TEX_DepthCompareFunction_LessEqual = 0x00000003, -TEX_DepthCompareFunction_Greater = 0x00000004, -TEX_DepthCompareFunction_NotEqual = 0x00000005, -TEX_DepthCompareFunction_GreaterEqual = 0x00000006, -TEX_DepthCompareFunction_Always = 0x00000007, -} TEX_DEPTH_COMPARE_FUNCTION; - -typedef enum TEX_DIM { -TEX_Dim_1D = 0x00000000, -TEX_Dim_2D = 0x00000001, -TEX_Dim_3D = 0x00000002, -TEX_Dim_CubeMap = 0x00000003, -TEX_Dim_1DArray = 0x00000004, -TEX_Dim_2DArray = 0x00000005, -TEX_Dim_2D_MSAA = 0x00000006, -TEX_Dim_2DArray_MSAA = 0x00000007, -} TEX_DIM; - -typedef enum TEX_FORMAT_COMP { -TEX_FormatComp_Unsigned = 0x00000000, -TEX_FormatComp_Signed = 0x00000001, -TEX_FormatComp_UnsignedBiased = 0x00000002, -TEX_FormatComp_RESERVED_3 = 0x00000003, -} TEX_FORMAT_COMP; - -typedef enum TEX_MAX_ANISO_RATIO { -TEX_MaxAnisoRatio_1to1 = 0x00000000, -TEX_MaxAnisoRatio_2to1 = 0x00000001, -TEX_MaxAnisoRatio_4to1 = 0x00000002, -TEX_MaxAnisoRatio_8to1 = 0x00000003, -TEX_MaxAnisoRatio_16to1 = 0x00000004, -TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005, -TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006, -TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007, -} TEX_MAX_ANISO_RATIO; - -typedef enum TEX_MIP_FILTER { -TEX_MipFilter_None = 0x00000000, -TEX_MipFilter_Point = 0x00000001, -TEX_MipFilter_Linear = 0x00000002, -TEX_MipFilter_RESERVED_3__SI__CI = 0x00000003, -TEX_MipFilter_Point_Aniso_Adj__VI = 0x00000003, -} TEX_MIP_FILTER; - -typedef enum TEX_REQUEST_SIZE { -TEX_RequestSize_32B = 0x00000000, -TEX_RequestSize_64B = 0x00000001, -TEX_RequestSize_128B = 0x00000002, -TEX_RequestSize_2X64B = 0x00000003, -} TEX_REQUEST_SIZE; - -typedef enum TEX_SAMPLER_TYPE { -TEX_SamplerType_Invalid = 0x00000000, -TEX_SamplerType_Valid = 0x00000001, -} TEX_SAMPLER_TYPE; - -typedef enum TEX_XY_FILTER { -TEX_XYFilter_Point = 0x00000000, -TEX_XYFilter_Linear = 0x00000001, -TEX_XYFilter_AnisoPoint = 0x00000002, -TEX_XYFilter_AnisoLinear = 0x00000003, -} TEX_XY_FILTER; - -typedef enum TEX_Z_FILTER { -TEX_ZFilter_None = 0x00000000, -TEX_ZFilter_Point = 0x00000001, -TEX_ZFilter_Linear = 0x00000002, -TEX_ZFilter_RESERVED_3 = 0x00000003, -} TEX_Z_FILTER; - -typedef enum TVX_DATA_FORMAT { -TVX_FMT_INVALID = 0x00000000, -TVX_FMT_8 = 0x00000001, -TVX_FMT_4_4 = 0x00000002, -TVX_FMT_3_3_2 = 0x00000003, -TVX_FMT_RESERVED_4 = 0x00000004, -TVX_FMT_16 = 0x00000005, -TVX_FMT_16_FLOAT = 0x00000006, -TVX_FMT_8_8 = 0x00000007, -TVX_FMT_5_6_5 = 0x00000008, -TVX_FMT_6_5_5 = 0x00000009, -TVX_FMT_1_5_5_5 = 0x0000000a, -TVX_FMT_4_4_4_4 = 0x0000000b, -TVX_FMT_5_5_5_1 = 0x0000000c, -TVX_FMT_32 = 0x0000000d, -TVX_FMT_32_FLOAT = 0x0000000e, -TVX_FMT_16_16 = 0x0000000f, -TVX_FMT_16_16_FLOAT = 0x00000010, -TVX_FMT_8_24 = 0x00000011, -TVX_FMT_8_24_FLOAT = 0x00000012, -TVX_FMT_24_8 = 0x00000013, -TVX_FMT_24_8_FLOAT = 0x00000014, -TVX_FMT_10_11_11 = 0x00000015, -TVX_FMT_10_11_11_FLOAT = 0x00000016, -TVX_FMT_11_11_10 = 0x00000017, -TVX_FMT_11_11_10_FLOAT = 0x00000018, -TVX_FMT_2_10_10_10 = 0x00000019, -TVX_FMT_8_8_8_8 = 0x0000001a, -TVX_FMT_10_10_10_2 = 0x0000001b, -TVX_FMT_X24_8_32_FLOAT = 0x0000001c, -TVX_FMT_32_32 = 0x0000001d, -TVX_FMT_32_32_FLOAT = 0x0000001e, -TVX_FMT_16_16_16_16 = 0x0000001f, -TVX_FMT_16_16_16_16_FLOAT = 0x00000020, -TVX_FMT_RESERVED_33 = 0x00000021, -TVX_FMT_32_32_32_32 = 0x00000022, -TVX_FMT_32_32_32_32_FLOAT = 0x00000023, -TVX_FMT_RESERVED_36 = 0x00000024, -TVX_FMT_1 = 0x00000025, -TVX_FMT_1_REVERSED = 0x00000026, -TVX_FMT_GB_GR = 0x00000027, -TVX_FMT_BG_RG = 0x00000028, -TVX_FMT_32_AS_8 = 0x00000029, -TVX_FMT_32_AS_8_8 = 0x0000002a, -TVX_FMT_5_9_9_9_SHAREDEXP = 0x0000002b, -TVX_FMT_8_8_8 = 0x0000002c, -TVX_FMT_16_16_16 = 0x0000002d, -TVX_FMT_16_16_16_FLOAT = 0x0000002e, -TVX_FMT_32_32_32 = 0x0000002f, -TVX_FMT_32_32_32_FLOAT = 0x00000030, -TVX_FMT_BC1 = 0x00000031, -TVX_FMT_BC2 = 0x00000032, -TVX_FMT_BC3 = 0x00000033, -TVX_FMT_BC4 = 0x00000034, -TVX_FMT_BC5 = 0x00000035, -TVX_FMT_APC0 = 0x00000036, -TVX_FMT_APC1 = 0x00000037, -TVX_FMT_APC2 = 0x00000038, -TVX_FMT_APC3 = 0x00000039, -TVX_FMT_APC4 = 0x0000003a, -TVX_FMT_APC5 = 0x0000003b, -TVX_FMT_APC6 = 0x0000003c, -TVX_FMT_APC7 = 0x0000003d, -TVX_FMT_CTX1 = 0x0000003e, -TVX_FMT_RESERVED_63 = 0x0000003f, -} TVX_DATA_FORMAT; - -typedef enum TVX_DST_SEL { -TVX_DstSel_X = 0x00000000, -TVX_DstSel_Y = 0x00000001, -TVX_DstSel_Z = 0x00000002, -TVX_DstSel_W = 0x00000003, -TVX_DstSel_0f = 0x00000004, -TVX_DstSel_1f = 0x00000005, -TVX_DstSel_RESERVED_6 = 0x00000006, -TVX_DstSel_Mask = 0x00000007, -} TVX_DST_SEL; - -typedef enum TVX_ENDIAN_SWAP { -TVX_EndianSwap_None = 0x00000000, -TVX_EndianSwap_8in16 = 0x00000001, -TVX_EndianSwap_8in32 = 0x00000002, -TVX_EndianSwap_8in64 = 0x00000003, -} TVX_ENDIAN_SWAP; - -typedef enum TVX_INST { -TVX_Inst_NormalVertexFetch = 0x00000000, -TVX_Inst_SemanticVertexFetch = 0x00000001, -TVX_Inst_RESERVED_2 = 0x00000002, -TVX_Inst_LD = 0x00000003, -TVX_Inst_GetTextureResInfo = 0x00000004, -TVX_Inst_GetNumberOfSamples = 0x00000005, -TVX_Inst_GetLOD = 0x00000006, -TVX_Inst_GetGradientsH = 0x00000007, -TVX_Inst_GetGradientsV = 0x00000008, -TVX_Inst_SetTextureOffsets = 0x00000009, -TVX_Inst_KeepGradients = 0x0000000a, -TVX_Inst_SetGradientsH = 0x0000000b, -TVX_Inst_SetGradientsV = 0x0000000c, -TVX_Inst_Pass = 0x0000000d, -TVX_Inst_GetBufferResInfo = 0x0000000e, -TVX_Inst_RESERVED_15 = 0x0000000f, -TVX_Inst_Sample = 0x00000010, -TVX_Inst_Sample_L = 0x00000011, -TVX_Inst_Sample_LB = 0x00000012, -TVX_Inst_Sample_LZ = 0x00000013, -TVX_Inst_Sample_G = 0x00000014, -TVX_Inst_Gather4 = 0x00000015, -TVX_Inst_Sample_G_LB = 0x00000016, -TVX_Inst_Gather4_O = 0x00000017, -TVX_Inst_Sample_C = 0x00000018, -TVX_Inst_Sample_C_L = 0x00000019, -TVX_Inst_Sample_C_LB = 0x0000001a, -TVX_Inst_Sample_C_LZ = 0x0000001b, -TVX_Inst_Sample_C_G = 0x0000001c, -TVX_Inst_Gather4_C = 0x0000001d, -TVX_Inst_Sample_C_G_LB = 0x0000001e, -TVX_Inst_Gather4_C_O = 0x0000001f, -} TVX_INST; - -typedef enum TVX_NUM_FORMAT_ALL { -TVX_NumFormatAll_Norm = 0x00000000, -TVX_NumFormatAll_Int = 0x00000001, -TVX_NumFormatAll_Scaled = 0x00000002, -TVX_NumFormatAll_RESERVED_3 = 0x00000003, -} TVX_NUM_FORMAT_ALL; - -typedef enum TVX_SRC_SEL { -TVX_SrcSel_X = 0x00000000, -TVX_SrcSel_Y = 0x00000001, -TVX_SrcSel_Z = 0x00000002, -TVX_SrcSel_W = 0x00000003, -TVX_SrcSel_0f = 0x00000004, -TVX_SrcSel_1f = 0x00000005, -} TVX_SRC_SEL; - -typedef enum TVX_SRF_MODE_ALL { -TVX_SRFModeAll_ZCMO = 0x00000000, -TVX_SRFModeAll_NZ = 0x00000001, -} TVX_SRF_MODE_ALL; - -typedef enum TVX_TYPE { -TVX_Type_InvalidTextureResource = 0x00000000, -TVX_Type_InvalidVertexBuffer = 0x00000001, -TVX_Type_ValidTextureResource = 0x00000002, -TVX_Type_ValidVertexBuffer = 0x00000003, -} TVX_TYPE; - -typedef enum TileSplit { -ADDR_SURF_TILE_SPLIT_64B = 0x00000000, -ADDR_SURF_TILE_SPLIT_128B = 0x00000001, -ADDR_SURF_TILE_SPLIT_256B = 0x00000002, -ADDR_SURF_TILE_SPLIT_512B = 0x00000003, -ADDR_SURF_TILE_SPLIT_1KB = 0x00000004, -ADDR_SURF_TILE_SPLIT_2KB = 0x00000005, -ADDR_SURF_TILE_SPLIT_4KB = 0x00000006, -} TileSplit; - -typedef enum TileType { -ARRAY_COLOR_TILE = 0x00000000, -ARRAY_DEPTH_TILE = 0x00000001, -} TileType; - -typedef enum UVDFirmwareCommand { -UVDFC_FENCE = 0x00000000, -UVDFC_TRAP = 0x00000001, -UVDFC_DECODED_ADDR = 0x00000002, -UVDFC_MBLOCK_ADDR = 0x00000003, -UVDFC_ITBUF_ADDR = 0x00000004, -UVDFC_DISPLAY_ADDR = 0x00000005, -UVDFC_EOD = 0x00000006, -UVDFC_DISPLAY_PITCH = 0x00000007, -UVDFC_DISPLAY_TILING = 0x00000008, -UVDFC_BITSTREAM_ADDR = 0x00000009, -UVDFC_BITSTREAM_SIZE = 0x0000000a, -} UVDFirmwareCommand; - -typedef enum VGT_CACHE_INVALID_MODE { -VC_ONLY = 0x00000000, -TC_ONLY = 0x00000001, -VC_AND_TC = 0x00000002, -} VGT_CACHE_INVALID_MODE; - -typedef enum VGT_DI_INDEX_SIZE { -DI_INDEX_SIZE_16_BIT = 0x00000000, -DI_INDEX_SIZE_32_BIT = 0x00000001, -DI_INDEX_SIZE_8_BIT__VI = 0x00000002, -} VGT_DI_INDEX_SIZE; - -typedef enum VGT_DI_MAJOR_MODE_SELECT { -DI_MAJOR_MODE_0 = 0x00000000, -DI_MAJOR_MODE_1 = 0x00000001, -} VGT_DI_MAJOR_MODE_SELECT; - -typedef enum VGT_DI_PRIM_TYPE { -DI_PT_NONE = 0x00000000, -DI_PT_POINTLIST = 0x00000001, -DI_PT_LINELIST = 0x00000002, -DI_PT_LINESTRIP = 0x00000003, -DI_PT_TRILIST = 0x00000004, -DI_PT_TRIFAN = 0x00000005, -DI_PT_TRISTRIP = 0x00000006, -DI_PT_UNUSED_0 = 0x00000007, -DI_PT_UNUSED_1 = 0x00000008, -DI_PT_PATCH = 0x00000009, -DI_PT_LINELIST_ADJ = 0x0000000a, -DI_PT_LINESTRIP_ADJ = 0x0000000b, -DI_PT_TRILIST_ADJ = 0x0000000c, -DI_PT_TRISTRIP_ADJ = 0x0000000d, -DI_PT_UNUSED_3 = 0x0000000e, -DI_PT_UNUSED_4 = 0x0000000f, -DI_PT_TRI_WITH_WFLAGS = 0x00000010, -DI_PT_RECTLIST = 0x00000011, -DI_PT_LINELOOP = 0x00000012, -DI_PT_QUADLIST = 0x00000013, -DI_PT_QUADSTRIP = 0x00000014, -DI_PT_POLYGON = 0x00000015, -DI_PT_2D_COPY_RECT_LIST_V0 = 0x00000016, -DI_PT_2D_COPY_RECT_LIST_V1 = 0x00000017, -DI_PT_2D_COPY_RECT_LIST_V2 = 0x00000018, -DI_PT_2D_COPY_RECT_LIST_V3 = 0x00000019, -DI_PT_2D_FILL_RECT_LIST = 0x0000001a, -DI_PT_2D_LINE_STRIP = 0x0000001b, -DI_PT_2D_TRI_STRIP = 0x0000001c, -} VGT_DI_PRIM_TYPE; - -typedef enum VGT_DI_SOURCE_SELECT { -DI_SRC_SEL_DMA = 0x00000000, -DI_SRC_SEL_IMMEDIATE = 0x00000001, -DI_SRC_SEL_AUTO_INDEX = 0x00000002, -DI_SRC_SEL_RESERVED = 0x00000003, -} VGT_DI_SOURCE_SELECT; - -typedef enum VGT_DMA_BUF_TYPE { -VGT_DMA_BUF_MEM = 0x00000000, -VGT_DMA_BUF_RING = 0x00000001, -VGT_DMA_BUF_SETUP = 0x00000002, -VGT_DMA_PTR_UPDATE__VI = 0x00000003, -} VGT_DMA_BUF_TYPE; - -typedef enum VGT_DMA_SWAP_MODE { -VGT_DMA_SWAP_NONE = 0x00000000, -VGT_DMA_SWAP_16_BIT = 0x00000001, -VGT_DMA_SWAP_32_BIT = 0x00000002, -VGT_DMA_SWAP_WORD = 0x00000003, -} VGT_DMA_SWAP_MODE; - -typedef enum VGT_EVENT_TYPE { -Reserved_0x00 = 0x00000000, -SAMPLE_STREAMOUTSTATS1 = 0x00000001, -SAMPLE_STREAMOUTSTATS2 = 0x00000002, -SAMPLE_STREAMOUTSTATS3 = 0x00000003, -CACHE_FLUSH_TS = 0x00000004, -CONTEXT_DONE = 0x00000005, -CACHE_FLUSH = 0x00000006, -CS_PARTIAL_FLUSH = 0x00000007, -VGT_STREAMOUT_SYNC = 0x00000008, -Reserved_0x09 = 0x00000009, -VGT_STREAMOUT_RESET = 0x0000000a, -END_OF_PIPE_INCR_DE = 0x0000000b, -END_OF_PIPE_IB_END = 0x0000000c, -RST_PIX_CNT = 0x0000000d, -Reserved_0x0E = 0x0000000e, -VS_PARTIAL_FLUSH = 0x0000000f, -PS_PARTIAL_FLUSH = 0x00000010, -FLUSH_HS_OUTPUT = 0x00000011, -FLUSH_LS_OUTPUT = 0x00000012, -Reserved_0x13 = 0x00000013, -CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014, -ZPASS_DONE = 0x00000015, -CACHE_FLUSH_AND_INV_EVENT = 0x00000016, -PERFCOUNTER_START = 0x00000017, -PERFCOUNTER_STOP = 0x00000018, -PIPELINESTAT_START = 0x00000019, -PIPELINESTAT_STOP = 0x0000001a, -PERFCOUNTER_SAMPLE = 0x0000001b, -FLUSH_ES_OUTPUT = 0x0000001c, -FLUSH_GS_OUTPUT = 0x0000001d, -SAMPLE_PIPELINESTAT = 0x0000001e, -SO_VGTSTREAMOUT_FLUSH = 0x0000001f, -SAMPLE_STREAMOUTSTATS = 0x00000020, -RESET_VTX_CNT = 0x00000021, -BLOCK_CONTEXT_DONE = 0x00000022, -CS_CONTEXT_DONE = 0x00000023, -VGT_FLUSH = 0x00000024, -Reserved_0x25__SI__CI = 0x00000025, -TGID_ROLLOVER__VI = 0x00000025, -SQ_NON_EVENT = 0x00000026, -SC_SEND_DB_VPZ = 0x00000027, -BOTTOM_OF_PIPE_TS = 0x00000028, -FLUSH_SX_TS = 0x00000029, -DB_CACHE_FLUSH_AND_INV = 0x0000002a, -FLUSH_AND_INV_DB_DATA_TS = 0x0000002b, -FLUSH_AND_INV_DB_META = 0x0000002c, -FLUSH_AND_INV_CB_DATA_TS = 0x0000002d, -FLUSH_AND_INV_CB_META = 0x0000002e, -CS_DONE = 0x0000002f, -PS_DONE = 0x00000030, -FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031, -SX_CB_RAT_ACK_REQUEST = 0x00000032, -THREAD_TRACE_START = 0x00000033, -THREAD_TRACE_STOP = 0x00000034, -THREAD_TRACE_MARKER = 0x00000035, -THREAD_TRACE_FLUSH = 0x00000036, -THREAD_TRACE_FINISH = 0x00000037, -PIXEL_PIPE_STAT_CONTROL__CI__VI = 0x00000038, -PIXEL_PIPE_STAT_DUMP__CI__VI = 0x00000039, -PIXEL_PIPE_STAT_RESET__CI__VI = 0x0000003a, -CONTEXT_SUSPEND__CI__VI = 0x0000003b, -OFFCHIP_HS_DEALLOC__VI = 0x0000003c, -} VGT_EVENT_TYPE; - -typedef enum VGT_GROUP_CONV_SEL { -VGT_GRP_INDEX_16 = 0x00000000, -VGT_GRP_INDEX_32 = 0x00000001, -VGT_GRP_UINT_16 = 0x00000002, -VGT_GRP_UINT_32 = 0x00000003, -VGT_GRP_SINT_16 = 0x00000004, -VGT_GRP_SINT_32 = 0x00000005, -VGT_GRP_FLOAT_32 = 0x00000006, -VGT_GRP_AUTO_PRIM = 0x00000007, -VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008, -} VGT_GROUP_CONV_SEL; - -typedef enum VGT_GRP_PRIM_ORDER { -VGT_GRP_LIST = 0x00000000, -VGT_GRP_STRIP = 0x00000001, -VGT_GRP_FAN = 0x00000002, -VGT_GRP_LOOP = 0x00000003, -VGT_GRP_POLYGON = 0x00000004, -} VGT_GRP_PRIM_ORDER; - -typedef enum VGT_GRP_PRIM_TYPE { -VGT_GRP_3D_POINT = 0x00000000, -VGT_GRP_3D_LINE = 0x00000001, -VGT_GRP_3D_TRI = 0x00000002, -VGT_GRP_3D_RECT = 0x00000003, -VGT_GRP_3D_QUAD = 0x00000004, -VGT_GRP_2D_COPY_RECT_V0 = 0x00000005, -VGT_GRP_2D_COPY_RECT_V1 = 0x00000006, -VGT_GRP_2D_COPY_RECT_V2 = 0x00000007, -VGT_GRP_2D_COPY_RECT_V3 = 0x00000008, -VGT_GRP_2D_FILL_RECT = 0x00000009, -VGT_GRP_2D_LINE = 0x0000000a, -VGT_GRP_2D_TRI = 0x0000000b, -VGT_GRP_PRIM_INDEX_LINE = 0x0000000c, -VGT_GRP_PRIM_INDEX_TRI = 0x0000000d, -VGT_GRP_PRIM_INDEX_QUAD = 0x0000000e, -VGT_GRP_3D_LINE_ADJ = 0x0000000f, -VGT_GRP_3D_TRI_ADJ = 0x00000010, -VGT_GRP_3D_PATCH = 0x00000011, -} VGT_GRP_PRIM_TYPE; - -typedef enum VGT_GS_CUT_MODE { -GS_CUT_1024 = 0x00000000, -GS_CUT_512 = 0x00000001, -GS_CUT_256 = 0x00000002, -GS_CUT_128 = 0x00000003, -} VGT_GS_CUT_MODE; - -typedef enum VGT_GS_MODE_TYPE { -GS_OFF = 0x00000000, -GS_SCENARIO_A = 0x00000001, -GS_SCENARIO_B = 0x00000002, -GS_SCENARIO_G = 0x00000003, -GS_SCENARIO_C = 0x00000004, -SPRITE_EN = 0x00000005, -} VGT_GS_MODE_TYPE; - -typedef enum VGT_GS_OUTPRIM_TYPE { -POINTLIST = 0x00000000, -LINESTRIP = 0x00000001, -TRISTRIP = 0x00000002, -} VGT_GS_OUTPRIM_TYPE; - -typedef enum VGT_INDEX_TYPE_MODE { -VGT_INDEX_16 = 0x00000000, -VGT_INDEX_32 = 0x00000001, -VGT_INDEX_8__VI = 0x00000002, -} VGT_INDEX_TYPE_MODE; - -typedef enum VGT_OUTPATH_SELECT { -VGT_OUTPATH_VTX_REUSE = 0x00000000, -VGT_OUTPATH_TESS_EN = 0x00000001, -VGT_OUTPATH_PASSTHRU = 0x00000002, -VGT_OUTPATH_GS_BLOCK = 0x00000003, -VGT_OUTPATH_HS_BLOCK = 0x00000004, -} VGT_OUTPATH_SELECT; - -typedef enum VGT_OUT_PRIM_TYPE { -VGT_OUT_POINT = 0x00000000, -VGT_OUT_LINE = 0x00000001, -VGT_OUT_TRI = 0x00000002, -VGT_OUT_RECT_V0 = 0x00000003, -VGT_OUT_RECT_V1 = 0x00000004, -VGT_OUT_RECT_V2 = 0x00000005, -VGT_OUT_RECT_V3 = 0x00000006, -VGT_OUT_RESERVED = 0x00000007, -VGT_TE_QUAD = 0x00000008, -VGT_TE_PRIM_INDEX_LINE = 0x00000009, -VGT_TE_PRIM_INDEX_TRI = 0x0000000a, -VGT_TE_PRIM_INDEX_QUAD = 0x0000000b, -VGT_OUT_LINE_ADJ = 0x0000000c, -VGT_OUT_TRI_ADJ = 0x0000000d, -VGT_OUT_PATCH = 0x0000000e, -} VGT_OUT_PRIM_TYPE; - -typedef enum VGT_PERFCOUNT_SELECT { -vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x00000000, -vgt_perf_VGT_SPI_ESVERT_VALID = 0x00000001, -vgt_perf_VGT_SPI_ESVERT_EOV = 0x00000002, -vgt_perf_VGT_SPI_ESVERT_STALLED = 0x00000003, -vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x00000004, -vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x00000005, -vgt_perf_VGT_SPI_ESVERT_STATIC = 0x00000006, -vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x00000007, -vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x00000008, -vgt_perf_VGT_SPI_GSPRIM_VALID = 0x00000009, -vgt_perf_VGT_SPI_GSPRIM_EOV = 0x0000000a, -vgt_perf_VGT_SPI_GSPRIM_CONT = 0x0000000b, -vgt_perf_VGT_SPI_GSPRIM_STALLED = 0x0000000c, -vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0x0000000d, -vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0x0000000e, -vgt_perf_VGT_SPI_GSPRIM_STATIC = 0x0000000f, -vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000010, -vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x00000011, -vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x00000012, -vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000013, -vgt_perf_VGT_SPI_VSVERT_SEND = 0x00000014, -vgt_perf_VGT_SPI_VSVERT_EOV = 0x00000015, -vgt_perf_VGT_SPI_VSVERT_STALLED = 0x00000016, -vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x00000017, -vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x00000018, -vgt_perf_VGT_SPI_VSVERT_STATIC = 0x00000019, -vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x0000001a, -vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x0000001b, -vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x0000001c, -vgt_perf_VGT_PA_CLIPV_SEND = 0x0000001d, -vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x0000001e, -vgt_perf_VGT_PA_CLIPV_STALLED = 0x0000001f, -vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x00000020, -vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x00000021, -vgt_perf_VGT_PA_CLIPV_STATIC = 0x00000022, -vgt_perf_VGT_PA_CLIPP_SEND = 0x00000023, -vgt_perf_VGT_PA_CLIPP_EOP = 0x00000024, -vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x00000025, -vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x00000026, -vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x00000027, -vgt_perf_VGT_PA_CLIPP_STALLED = 0x00000028, -vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x00000029, -vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x0000002a, -vgt_perf_VGT_PA_CLIPP_STATIC = 0x0000002b, -vgt_perf_VGT_PA_CLIPS_SEND = 0x0000002c, -vgt_perf_VGT_PA_CLIPS_STALLED = 0x0000002d, -vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x0000002e, -vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x0000002f, -vgt_perf_VGT_PA_CLIPS_STATIC = 0x00000030, -vgt_perf_vsvert_ds_send = 0x00000031, -vgt_perf_vsvert_api_send = 0x00000032, -vgt_perf_hs_tif_stall = 0x00000033, -vgt_perf_hs_input_stall = 0x00000034, -vgt_perf_hs_interface_stall = 0x00000035, -vgt_perf_hs_tfm_stall = 0x00000036, -vgt_perf_te11_starved = 0x00000037, -vgt_perf_gs_event_stall = 0x00000038, -vgt_perf_RESERVED0__SI = 0x00000039, -vgt_perf_vgt_pa_clipp_send_not_event__CI__VI = 0x00000039, -vgt_perf_RESERVED1__SI = 0x0000003a, -vgt_perf_vgt_pa_clipp_valid_prim__CI__VI = 0x0000003a, -vgt_perf_RESERVED2__SI = 0x0000003b, -vgt_perf_reused_es_indices__CI__VI = 0x0000003b, -vgt_perf_vs_cache_hits__CI__VI = 0x0000003c, -vgt_perf_gs_cache_hits__CI__VI = 0x0000003d, -vgt_perf_ds_cache_hits__CI__VI = 0x0000003e, -vgt_perf_total_cache_hits__CI__VI = 0x0000003f, -vgt_perf_vgt_busy = 0x00000040, -vgt_perf_vgt_gs_busy = 0x00000041, -vgt_perf_esvert_stalled_es_tbl = 0x00000042, -vgt_perf_esvert_stalled_gs_tbl = 0x00000043, -vgt_perf_esvert_stalled_gs_event = 0x00000044, -vgt_perf_esvert_stalled_gsprim = 0x00000045, -vgt_perf_gsprim_stalled_es_tbl = 0x00000046, -vgt_perf_gsprim_stalled_gs_tbl = 0x00000047, -vgt_perf_gsprim_stalled_gs_event = 0x00000048, -vgt_perf_gsprim_stalled_esvert = 0x00000049, -vgt_perf_esthread_stalled_es_rb_full = 0x0000004a, -vgt_perf_esthread_stalled_spi_bp = 0x0000004b, -vgt_perf_counters_avail_stalled = 0x0000004c, -vgt_perf_gs_rb_space_avail_stalled = 0x0000004d, -vgt_perf_gs_issue_rtr_stalled = 0x0000004e, -vgt_perf_gsthread_stalled = 0x0000004f, -vgt_perf_strmout_stalled__CI__VI = 0x00000050, -vgt_perf_wait_for_es_done_stalled = 0x00000051, -vgt_perf_cm_stalled_by_gog = 0x00000052, -vgt_perf_cm_reading_stalled = 0x00000053, -vgt_perf_cm_stalled_by_gsfetch_done = 0x00000054, -vgt_perf_gog_vs_tbl_stalled = 0x00000055, -vgt_perf_gog_out_indx_stalled = 0x00000056, -vgt_perf_gog_out_prim_stalled = 0x00000057, -vgt_perf_waveid_stalled__CI__VI = 0x00000058, -vgt_perf_gog_busy = 0x00000059, -vgt_perf_reused_vs_indices = 0x0000005a, -vgt_perf_sclk_reg_vld_event = 0x0000005b, -vgt_perf_RESERVED0__CI = 0x0000005c, -vgt_perf_vs_conflicting_indices__VI = 0x0000005c, -vgt_perf_sclk_core_vld_event = 0x0000005d, -vgt_perf_RESERVED1__CI = 0x0000005e, -vgt_perf_hswave_stalled__VI = 0x0000005e, -vgt_perf_sclk_gs_vld_event = 0x0000005f, -vgt_perf_VGT_SPI_LSVERT_VALID = 0x00000060, -vgt_perf_VGT_SPI_LSVERT_EOV = 0x00000061, -vgt_perf_VGT_SPI_LSVERT_STALLED = 0x00000062, -vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x00000063, -vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x00000064, -vgt_perf_VGT_SPI_LSVERT_STATIC = 0x00000065, -vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x00000066, -vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x00000067, -vgt_perf_VGT_SPI_LSWAVE_SEND = 0x00000068, -vgt_perf_VGT_SPI_HSVERT_VALID = 0x00000069, -vgt_perf_VGT_SPI_HSVERT_EOV = 0x0000006a, -vgt_perf_VGT_SPI_HSVERT_STALLED = 0x0000006b, -vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x0000006c, -vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x0000006d, -vgt_perf_VGT_SPI_HSVERT_STATIC = 0x0000006e, -vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x0000006f, -vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x00000070, -vgt_perf_VGT_SPI_HSWAVE_SEND = 0x00000071, -vgt_perf_ds_prims__CI__VI = 0x00000072, -vgt_perf_null_tess_patches__SI__CI = 0x00000073, -vgt_perf_ls_thread_groups__VI = 0x00000073, -vgt_perf_ls_thread_groups__SI__CI = 0x00000074, -vgt_perf_hs_thread_groups__VI = 0x00000074, -vgt_perf_hs_thread_groups__SI__CI = 0x00000075, -vgt_perf_es_thread_groups__VI = 0x00000075, -vgt_perf_es_thread_groups__SI__CI = 0x00000076, -vgt_perf_vs_thread_groups__VI = 0x00000076, -vgt_perf_vs_thread_groups__SI__CI = 0x00000077, -vgt_perf_ls_done_latency__VI = 0x00000077, -vgt_perf_ls_done_latency__SI__CI = 0x00000078, -vgt_perf_hs_done_latency__VI = 0x00000078, -vgt_perf_hs_done_latency__SI__CI = 0x00000079, -vgt_perf_es_done_latency__VI = 0x00000079, -vgt_perf_es_done_latency__SI__CI = 0x0000007a, -vgt_perf_gs_done_latency__VI = 0x0000007a, -vgt_perf_gs_done_latency__SI__CI = 0x0000007b, -vgt_perf_vgt_hs_busy__VI = 0x0000007b, -vgt_perf_vgt_hs_busy__SI__CI = 0x0000007c, -vgt_perf_vgt_te11_busy__VI = 0x0000007c, -vgt_perf_vgt_te11_busy__SI__CI = 0x0000007d, -vgt_perf_ls_flush__VI = 0x0000007d, -vgt_perf_ls_flush__SI__CI = 0x0000007e, -vgt_perf_hs_flush__VI = 0x0000007e, -vgt_perf_hs_flush__SI__CI = 0x0000007f, -vgt_perf_es_flush__VI = 0x0000007f, -vgt_perf_es_flush__SI__CI = 0x00000080, -vgt_perf_vgt_pa_clipp_eopg__VI = 0x00000080, -vgt_perf_gs_flush__SI__CI = 0x00000081, -vgt_perf_ls_done__VI = 0x00000081, -vgt_perf_ls_done__SI__CI = 0x00000082, -vgt_perf_hs_done__VI = 0x00000082, -vgt_perf_hs_done__SI__CI = 0x00000083, -vgt_perf_es_done__VI = 0x00000083, -vgt_perf_es_done__SI__CI = 0x00000084, -vgt_perf_gs_done__VI = 0x00000084, -vgt_perf_gs_done__SI__CI = 0x00000085, -vgt_perf_vsfetch_done__VI = 0x00000085, -vgt_perf_vsfetch_done__SI__CI = 0x00000086, -vgt_perf_gs_done_received__VI = 0x00000086, -vgt_perf_RESERVED2__CI = 0x00000087, -vgt_perf_es_ring_high_water_mark__VI = 0x00000087, -vgt_perf_es_ring_high_water_mark__SI__CI = 0x00000088, -vgt_perf_gs_ring_high_water_mark__VI = 0x00000088, -vgt_perf_gs_ring_high_water_mark__SI__CI = 0x00000089, -vgt_perf_vs_table_high_water_mark__VI = 0x00000089, -vgt_perf_vs_table_high_water_mark__SI__CI = 0x0000008a, -vgt_perf_hs_tgs_active_high_water_mark__VI = 0x0000008a, -vgt_perf_hs_tgs_active_high_water_mark__SI__CI = 0x0000008b, -vgt_perf_pa_clipp_dealloc__VI = 0x0000008b, -vgt_perf_cut_mem_flush_stalled__VI = 0x0000008c, -vgt_perf_vsvert_work_received__VI = 0x0000008d, -vgt_perf_vgt_pa_clipp_starved_after_work__VI = 0x0000008e, -vgt_perf_te11_con_starved_after_work__VI = 0x0000008f, -vgt_perf_hs_waiting_on_ls_done_stall__VI = 0x00000090, -vgt_spi_vsvert_valid__VI = 0x00000091, -} VGT_PERFCOUNT_SELECT; - -typedef enum VGT_RDREQ_POLICY { -VGT_POLICY_LRU = 0x00000000, -VGT_POLICY_STREAM = 0x00000001, -VGT_POLICY_BYPASS__SI__CI = 0x00000002, -VGT_POLICY_RESERVED__SI__CI = 0x00000003, -} VGT_RDREQ_POLICY; - -typedef enum VGT_STAGES_ES_EN { -ES_STAGE_OFF = 0x00000000, -ES_STAGE_DS = 0x00000001, -ES_STAGE_REAL = 0x00000002, -RESERVED_ES = 0x00000003, -} VGT_STAGES_ES_EN; - -typedef enum VGT_STAGES_GS_EN { -GS_STAGE_OFF = 0x00000000, -GS_STAGE_ON = 0x00000001, -} VGT_STAGES_GS_EN; - -typedef enum VGT_STAGES_HS_EN { -HS_STAGE_OFF = 0x00000000, -HS_STAGE_ON = 0x00000001, -} VGT_STAGES_HS_EN; - -typedef enum VGT_STAGES_LS_EN { -LS_STAGE_OFF = 0x00000000, -LS_STAGE_ON = 0x00000001, -CS_STAGE_ON = 0x00000002, -RESERVED_LS = 0x00000003, -} VGT_STAGES_LS_EN; - -typedef enum VGT_STAGES_VS_EN { -VS_STAGE_REAL = 0x00000000, -VS_STAGE_DS = 0x00000001, -VS_STAGE_COPY_SHADER = 0x00000002, -RESERVED_VS = 0x00000003, -} VGT_STAGES_VS_EN; - -typedef enum VGT_TESS_PARTITION { -PART_INTEGER = 0x00000000, -PART_POW2 = 0x00000001, -PART_FRAC_ODD = 0x00000002, -PART_FRAC_EVEN = 0x00000003, -} VGT_TESS_PARTITION; - -typedef enum VGT_TESS_TOPOLOGY { -OUTPUT_POINT = 0x00000000, -OUTPUT_LINE = 0x00000001, -OUTPUT_TRIANGLE_CW = 0x00000002, -OUTPUT_TRIANGLE_CCW = 0x00000003, -} VGT_TESS_TOPOLOGY; - -typedef enum VGT_TESS_TYPE { -TESS_ISOLINE = 0x00000000, -TESS_TRIANGLE = 0x00000001, -TESS_QUAD = 0x00000002, -} VGT_TESS_TYPE; - -typedef enum VTX_CLAMP { -VTX_Clamp_ClampToZero = 0x00000000, -VTX_Clamp_ClampToNAN = 0x00000001, -} VTX_CLAMP; - -typedef enum VTX_FETCH_TYPE { -VTX_FetchType_VertexData = 0x00000000, -VTX_FetchType_InstanceData = 0x00000001, -VTX_FetchType_NoIndexOffset = 0x00000002, -VTX_FetchType_RESERVED_3 = 0x00000003, -} VTX_FETCH_TYPE; - -typedef enum VTX_FORMAT_COMP_ALL { -VTX_FormatCompAll_Unsigned = 0x00000000, -VTX_FormatCompAll_Signed = 0x00000001, -} VTX_FORMAT_COMP_ALL; - -typedef enum VTX_MEM_REQUEST_SIZE { -VTX_MemRequestSize_32B = 0x00000000, -VTX_MemRequestSize_64B = 0x00000001, -} VTX_MEM_REQUEST_SIZE; - -typedef enum WD_IA_DRAW_TYPE { -WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000, -WD_IA_DRAW_TYPE_DI_MM1 = 0x00000001, -WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002, -WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003, -WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004, -WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005, -WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006, -WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007, -} WD_IA_DRAW_TYPE; - -typedef enum WD_PERFCOUNT_SELECT { -wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x00000000, -wd_perf_RBIU_DR_FIFO_STARVED = 0x00000001, -wd_perf_RBIU_DR_FIFO_STALLED = 0x00000002, -wd_perf_RBIU_DI_FIFO_STARVED = 0x00000003, -wd_perf_RBIU_DI_FIFO_STALLED = 0x00000004, -wd_perf_wd_busy = 0x00000005, -wd_perf_wd_sclk_reg_vld_event = 0x00000006, -wd_perf_wd_sclk_input_vld_event = 0x00000007, -wd_perf_wd_sclk_core_vld_event = 0x00000008, -wd_perf_wd_stalled = 0x00000009, -wd_perf_inside_tf_bin_0__VI = 0x0000000a, -wd_perf_inside_tf_bin_1__VI = 0x0000000b, -wd_perf_inside_tf_bin_2__VI = 0x0000000c, -wd_perf_inside_tf_bin_3__VI = 0x0000000d, -wd_perf_inside_tf_bin_4__VI = 0x0000000e, -wd_perf_inside_tf_bin_5__VI = 0x0000000f, -wd_perf_inside_tf_bin_6__VI = 0x00000010, -wd_perf_inside_tf_bin_7__VI = 0x00000011, -wd_perf_inside_tf_bin_8__VI = 0x00000012, -wd_perf_tfreq_lat_bin_0__VI = 0x00000013, -wd_perf_tfreq_lat_bin_1__VI = 0x00000014, -wd_perf_tfreq_lat_bin_2__VI = 0x00000015, -wd_perf_tfreq_lat_bin_3__VI = 0x00000016, -wd_perf_tfreq_lat_bin_4__VI = 0x00000017, -wd_perf_tfreq_lat_bin_5__VI = 0x00000018, -wd_perf_tfreq_lat_bin_6__VI = 0x00000019, -wd_perf_tfreq_lat_bin_7__VI = 0x0000001a, -wd_starved_on_hs_done__VI = 0x0000001b, -wd_perf_se0_hs_done_latency__VI = 0x0000001c, -wd_perf_se1_hs_done_latency__VI = 0x0000001d, -wd_perf_se2_hs_done_latency__VI = 0x0000001e, -wd_perf_se3_hs_done_latency__VI = 0x0000001f, -wd_perf_hs_done_se0__VI = 0x00000020, -wd_perf_hs_done_se1__VI = 0x00000021, -wd_perf_hs_done_se2__VI = 0x00000022, -wd_perf_hs_done_se3__VI = 0x00000023, -wd_perf_null_patches__VI = 0x00000024, -} WD_PERFCOUNT_SELECT; - -typedef enum ZFormat { -Z_INVALID = 0x00000000, -Z_16 = 0x00000001, -Z_24 = 0x00000002, -Z_32_FLOAT = 0x00000003, -} ZFormat; - -typedef enum ZLimitSumm { -FORCE_SUMM_OFF = 0x00000000, -FORCE_SUMM_MINZ = 0x00000001, -FORCE_SUMM_MAXZ = 0x00000002, -FORCE_SUMM_BOTH = 0x00000003, -} ZLimitSumm; - -typedef enum ZModeForce { -NO_FORCE = 0x00000000, -FORCE_EARLY_Z = 0x00000001, -FORCE_LATE_Z = 0x00000002, -FORCE_RE_Z = 0x00000003, -} ZModeForce; - -typedef enum ZOrder { -LATE_Z = 0x00000000, -EARLY_Z_THEN_LATE_Z = 0x00000001, -RE_Z = 0x00000002, -EARLY_Z_THEN_RE_Z = 0x00000003, -} ZOrder; - -typedef enum ZSamplePosition { -Z_SAMPLE_CENTER = 0x00000000, -Z_SAMPLE_CENTROID = 0x00000001, -} ZSamplePosition; - -typedef enum ZpassControl { -ZPASS_DISABLE = 0x00000000, -ZPASS_SAMPLES = 0x00000001, -ZPASS_PIXELS = 0x00000002, -} ZpassControl; - -//Merged Enumerations -typedef enum COL_MAN_DENORM_CLAMP_CONTROL { -DENORM_CLAMP_CONTROL_UNITY = 0x00000000, -DENORM_CLAMP_CONTROL_8 = 0x00000001, -DENORM_CLAMP_CONTROL_10 = 0x00000002, -DENORM_CLAMP_CONTROL_12 = 0x00000003, -} COL_MAN_DENORM_CLAMP_CONTROL; - -typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE { -COL_MAN_MULTIPLE_UPDATE = 0x00000000, -COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x00000001, -} COL_MAN_DISABLE_MULTIPLE_UPDATE; - -typedef enum COL_MAN_GAMMA_CORR_CONTROL { -GAMMA_CORR_CONTROL_BYPASS = 0x00000000, -GAMMA_CORR_CONTROL_A = 0x00000001, -GAMMA_CORR_CONTROL_B = 0x00000002, -} COL_MAN_GAMMA_CORR_CONTROL; - -typedef enum COL_MAN_INPUTCSC_CONVERT { -INPUTCSC_ROUND = 0x00000000, -INPUTCSC_TRUNCATE = 0x00000001, -} COL_MAN_INPUTCSC_CONVERT; - -typedef enum COL_MAN_INPUTCSC_MODE { -INPUTCSC_MODE_BYPASS = 0x00000000, -INPUTCSC_MODE_A = 0x00000001, -INPUTCSC_MODE_B = 0x00000002, -INPUTCSC_MODE_UNITY = 0x00000003, -} COL_MAN_INPUTCSC_MODE; - -typedef enum COL_MAN_INPUTCSC_TYPE { -INPUTCSC_TYPE_12_0 = 0x00000000, -INPUTCSC_TYPE_10_2 = 0x00000001, -INPUTCSC_TYPE_8_4 = 0x00000002, -} COL_MAN_INPUTCSC_TYPE; - -typedef enum COL_MAN_OUTPUT_CSC_MODE { -COL_MAN_OUTPUT_CSC_BYPASS = 0x00000000, -COL_MAN_OUTPUT_CSC_RGB = 0x00000001, -COL_MAN_OUTPUT_CSC_YCrCb601 = 0x00000002, -COL_MAN_OUTPUT_CSC_YCrCb709 = 0x00000003, -COL_MAN_OUTPUT_CSC_A = 0x00000004, -COL_MAN_OUTPUT_CSC_B = 0x00000005, -} COL_MAN_OUTPUT_CSC_MODE; - -typedef enum COL_MAN_PRESCALE_MODE { -PRESCALE_MODE_BYPASS = 0x00000000, -PRESCALE_MODE_PROGRAM = 0x00000001, -PRESCALE_MODE_UNITY = 0x00000002, -} COL_MAN_PRESCALE_MODE; - -typedef enum COL_MAN_UPDATE_LOCK { -COL_MAN_UPDATE_UNLOCKED = 0x00000000, -COL_MAN_UPDATE_LOCKED = 0x00000001, -} COL_MAN_UPDATE_LOCK; - -typedef enum CmaskAddr { -CMASK_ADDR_TILED = 0x00000000, -CMASK_ADDR_LINEAR = 0x00000001, -CMASK_ADDR_COMPATIBLE = 0x00000002, -} CmaskAddr; - -typedef enum ColorTransform { -DCC_CT_AUTO = 0x00000000, -DCC_CT_NONE = 0x00000001, -ABGR_TO_A_BG_G_RB = 0x00000002, -BGRA_TO_BG_G_RB_A = 0x00000003, -} ColorTransform; - -typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE { -DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x00000000, -DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x00000001, -} DCIOCHIP_AUXSLAVE_PAD_MODE; - -typedef enum DCIOCHIP_DVO_VREFPON { -DCIOCHIP_DVO_VREFPON_DISABLE = 0x00000000, -DCIOCHIP_DVO_VREFPON_ENABLE = 0x00000001, -} DCIOCHIP_DVO_VREFPON; - -typedef enum DCIOCHIP_DVO_VREFSEL { -DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x00000000, -DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x00000001, -} DCIOCHIP_DVO_VREFSEL; - -typedef enum DCIOCHIP_ENABLE_2BIT { -DCIOCHIP_2BIT_DISABLE = 0x00000000, -DCIOCHIP_2BIT_ENABLE = 0x00000003, -} DCIOCHIP_ENABLE_2BIT; - -typedef enum DCIOCHIP_ENABLE_4BIT { -DCIOCHIP_4BIT_DISABLE = 0x00000000, -DCIOCHIP_4BIT_ENABLE = 0x0000000f, -} DCIOCHIP_ENABLE_4BIT; - -typedef enum DCIOCHIP_ENABLE_5BIT { -DCIOCHIP_5BIT_DISABLE = 0x00000000, -DCIOCHIP_5BIT_ENABLE = 0x0000001f, -} DCIOCHIP_ENABLE_5BIT; - -typedef enum DCIOCHIP_GPIO_I2C_DRIVE { -DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x00000000, -DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x00000001, -} DCIOCHIP_GPIO_I2C_DRIVE; - -typedef enum DCIOCHIP_GPIO_I2C_EN { -DCIOCHIP_GPIO_I2C_DISABLE = 0x00000000, -DCIOCHIP_GPIO_I2C_ENABLE = 0x00000001, -} DCIOCHIP_GPIO_I2C_EN; - -typedef enum DCIOCHIP_GPIO_I2C_MASK { -DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x00000000, -DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x00000001, -} DCIOCHIP_GPIO_I2C_MASK; - -typedef enum DCIOCHIP_GPIO_MASK_EN { -DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000, -DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001, -} DCIOCHIP_GPIO_MASK_EN; - -typedef enum DCIOCHIP_HPD_SEL { -DCIOCHIP_HPD_SEL_ASYNC = 0x00000000, -DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001, -} DCIOCHIP_HPD_SEL; - -typedef enum DCIOCHIP_INVERT { -DCIOCHIP_POL_NON_INVERT = 0x00000000, -DCIOCHIP_POL_INVERT = 0x00000001, -} DCIOCHIP_INVERT; - -typedef enum DCIOCHIP_MASK { -DCIOCHIP_MASK_DISABLE = 0x00000000, -DCIOCHIP_MASK_ENABLE = 0x00000001, -} DCIOCHIP_MASK; - -typedef enum DCIOCHIP_MASK_2BIT { -DCIOCHIP_MASK_2BIT_DISABLE = 0x00000000, -DCIOCHIP_MASK_2BIT_ENABLE = 0x00000003, -} DCIOCHIP_MASK_2BIT; - -typedef enum DCIOCHIP_MASK_4BIT { -DCIOCHIP_MASK_4BIT_DISABLE = 0x00000000, -DCIOCHIP_MASK_4BIT_ENABLE = 0x0000000f, -} DCIOCHIP_MASK_4BIT; - -typedef enum DCIOCHIP_MASK_5BIT { -DCIOCHIP_MASIK_5BIT_DISABLE = 0x00000000, -DCIOCHIP_MASIK_5BIT_ENABLE = 0x0000001f, -} DCIOCHIP_MASK_5BIT; - -typedef enum DCIOCHIP_PAD_MODE { -DCIOCHIP_PAD_MODE_DDC = 0x00000000, -DCIOCHIP_PAD_MODE_DP = 0x00000001, -} DCIOCHIP_PAD_MODE; - -typedef enum DCIOCHIP_PD_EN { -DCIOCHIP_PD_EN_NOTALLOW = 0x00000000, -DCIOCHIP_PD_EN_ALLOW = 0x00000001, -} DCIOCHIP_PD_EN; - -typedef enum DCIOCHIP_REF_27_SRC_SEL { -DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000, -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001, -DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002, -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003, -} DCIOCHIP_REF_27_SRC_SEL; - -typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { -DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000, -DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001, -} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; - -typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN { -DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x00000000, -DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x00000001, -} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN; - -typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT { -DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000, -DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001, -DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002, -DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003, -} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; - -typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN { -DCIO_BL_PWM_DISABLE = 0x00000000, -DCIO_BL_PWM_ENABLE = 0x00000001, -} DCIO_BL_PWM_CNTL_BL_PWM_EN; - -typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { -DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x00000000, -DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x00000001, -} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; - -typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { -} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; - -typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { -DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000, -DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001, -} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; - -typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { -DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000, -} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; - -typedef enum DCIO_BL_PWM_GRP1_REG_LOCK { -DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000, -DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001, -} DCIO_BL_PWM_GRP1_REG_LOCK; - -typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START { -DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000, -DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001, -} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START; - -typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { -DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000, -DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001, -DCIO_TEST_CLK_SEL_SCLK = 0x00000002, -} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; - -typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { -DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000, -DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001, -} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; - -typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS { -DCIO_DISPCLK_R_DCIO_RAMP_DISABLE = 0x00000000, -DCIO_DISPCLK_R_DCIO_RAMP_ENABLE = 0x00000001, -} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS; - -typedef enum DCIO_DACA_SOFT_RESET { -DCIO_DACA_SOFT_RESET_DEASSERT = 0x00000000, -DCIO_DACA_SOFT_RESET_ASSERT = 0x00000001, -} DCIO_DACA_SOFT_RESET; - -typedef enum DCIO_DBG_OUT_12BIT_SEL { -DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x00000000, -DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x00000001, -DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x00000002, -DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x00000003, -} DCIO_DBG_OUT_12BIT_SEL; - -typedef enum DCIO_DBG_OUT_PIN_SEL { -DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x00000000, -DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x00000001, -} DCIO_DBG_OUT_PIN_SEL; - -typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX { -DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000, -DCIO_EXT_VSYNC_MUX_CRTC0 = 0x00000001, -DCIO_EXT_VSYNC_MUX_CRTC1 = 0x00000002, -DCIO_EXT_VSYNC_MUX_CRTC2 = 0x00000003, -DCIO_EXT_VSYNC_MUX_CRTC3 = 0x00000004, -DCIO_EXT_VSYNC_MUX_CRTC4 = 0x00000005, -DCIO_EXT_VSYNC_MUX_CRTC5 = 0x00000006, -DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007, -} DCIO_DCO_DCFE_EXT_VSYNC_MUX; - -typedef enum DCIO_DCO_EXT_VSYNC_MASK { -DCIO_EXT_VSYNC_MASK_NONE = 0x00000000, -DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001, -DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002, -DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003, -DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004, -DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005, -DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006, -DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007, -} DCIO_DCO_EXT_VSYNC_MASK; - -typedef enum DCIO_DCRXPHY_SOFT_RESET { -DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000, -DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001, -} DCIO_DCRXPHY_SOFT_RESET; - -typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN { -DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x00000000, -DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001, -} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN; - -typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN { -DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x00000000, -DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001, -} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN; - -typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN { -DCIO_VIP_MUX_EN_DVO = 0x00000000, -DCIO_VIP_MUX_EN_VIP = 0x00000001, -} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN; - -typedef enum DCIO_DC_GENERICA_SEL { -DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x00000000, -DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001, -DCIO_GENERICA_SEL_DACA_PIXCLK = 0x00000002, -DCIO_GENERICA_SEL_DACB_PIXCLK = 0x00000003, -DCIO_GENERICA_SEL_DVOA_CTL3 = 0x00000004, -DCIO_GENERICA_SEL_P1_PLLCLK = 0x00000005, -DCIO_GENERICA_SEL_P2_PLLCLK = 0x00000006, -DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x00000007, -DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x00000008, -DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x00000009, -DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a, -DCIO_GENERICA_SEL_SYNCEN = 0x0000000b, -DCIO_GENERICA_SEL_GENERICA_SCG = 0x0000000c, -DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0x0000000d, -DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0x0000000e, -DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0x0000000f, -DCIO_GENERICA_SEL_GENERICA_DPRX = 0x00000010, -DCIO_GENERICA_SEL_GENERICB_DPRX = 0x00000011, -} DCIO_DC_GENERICA_SEL; - -typedef enum DCIO_DC_GENERICB_SEL { -DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x00000000, -DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001, -DCIO_GENERICB_SEL_DACA_PIXCLK = 0x00000002, -DCIO_GENERICB_SEL_DACB_PIXCLK = 0x00000003, -DCIO_GENERICB_SEL_DVOA_CTL3 = 0x00000004, -DCIO_GENERICB_SEL_P1_PLLCLK = 0x00000005, -DCIO_GENERICB_SEL_P2_PLLCLK = 0x00000006, -DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x00000007, -DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x00000008, -DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x00000009, -DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a, -DCIO_GENERICB_SEL_SYNCEN = 0x0000000b, -DCIO_GENERICB_SEL_GENERICA_SCG = 0x0000000c, -DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0x0000000d, -DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0x0000000e, -DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0x0000000f, -} DCIO_DC_GENERICB_SEL; - -typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { -DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000, -DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001, -DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002, -DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003, -DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004, -DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005, -} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; - -typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { -DCIO_UNIPHYA_FBDIV_CLK = 0x00000000, -DCIO_UNIPHYB_FBDIV_CLK = 0x00000001, -DCIO_UNIPHYC_FBDIV_CLK = 0x00000002, -DCIO_UNIPHYD_FBDIV_CLK = 0x00000003, -DCIO_UNIPHYE_FBDIV_CLK = 0x00000004, -DCIO_UNIPHYF_FBDIV_CLK = 0x00000005, -} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; - -typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { -DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000, -DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001, -DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002, -DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003, -DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004, -DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005, -} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; - -typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { -DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000, -DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001, -DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002, -DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003, -DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004, -DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005, -} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; - -typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL { -DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x00000000, -DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x00000001, -} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL; - -typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN { -DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x00000000, -DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x00000001, -} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN; - -typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE { -DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x00000000, -DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x00000001, -} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; - -typedef enum DCIO_DC_GPIO_MACRO_DEBUG { -DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x00000000, -DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x00000001, -DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x00000002, -DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x00000003, -} DCIO_DC_GPIO_MACRO_DEBUG; - -typedef enum DCIO_DC_GPIO_VIP_DEBUG { -DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x00000000, -DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x00000001, -} DCIO_DC_GPIO_VIP_DEBUG; - -typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x00000002, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x00000003, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x00000004, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x00000005, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x00000006, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x00000007, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x00000008, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x00000009, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0x0000000a, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0x0000000b, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x0000000c, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x0000000d, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0x0000000e, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0x0000000f, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x00000010, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x00000011, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x00000012, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x00000013, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x00000014, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x00000015, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x00000016, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x00000017, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000018, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000019, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x0000001a, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x0000001b, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x0000001c, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x0000001d, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x0000001e, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x0000001f, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x00000020, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x00000021, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x00000022, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x00000023, -} DCIO_DC_GPU_TIMER_READ_SELECT; - -typedef enum DCIO_DC_GPU_TIMER_START_POSITION { -DCIO_GPU_TIMER_START_0_END_27 = 0x00000000, -DCIO_GPU_TIMER_START_1_END_28 = 0x00000001, -DCIO_GPU_TIMER_START_2_END_29 = 0x00000002, -DCIO_GPU_TIMER_START_3_END_30 = 0x00000003, -DCIO_GPU_TIMER_START_4_END_31 = 0x00000004, -DCIO_GPU_TIMER_START_6_END_33 = 0x00000005, -DCIO_GPU_TIMER_START_8_END_35 = 0x00000006, -DCIO_GPU_TIMER_START_10_END_37 = 0x00000007, -} DCIO_DC_GPU_TIMER_START_POSITION; - -typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS { -DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x00000000, -DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x00000001, -DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x00000002, -DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x00000003, -} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS; - -typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL { -DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x00000000, -DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x00000001, -DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x00000002, -DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x00000003, -DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x00000004, -DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x00000005, -DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x00000006, -DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x00000007, -DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x00000008, -DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x00000009, -DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0x0000000a, -DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0x0000000b, -DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0x0000000c, -DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0x0000000d, -DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0x0000000e, -DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0x0000000f, -} DCIO_DC_PAD_EXTERN_SIG_SEL; - -typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { -DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000, -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001, -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002, -DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003, -} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; - -typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL { -DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x00000000, -DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x00000001, -DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x00000002, -DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x00000003, -} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; - -typedef enum DCIO_DPHY_LANE_SEL { -DCIO_DPHY_LANE_SEL_LANE0 = 0x00000000, -DCIO_DPHY_LANE_SEL_LANE1 = 0x00000001, -DCIO_DPHY_LANE_SEL_LANE2 = 0x00000002, -DCIO_DPHY_LANE_SEL_LANE3 = 0x00000003, -} DCIO_DPHY_LANE_SEL; - -typedef enum DCIO_DSYNC_SOFT_RESET { -DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x00000000, -DCIO_DSYNC_SOFT_RESET_ASSERT = 0x00000001, -} DCIO_DSYNC_SOFT_RESET; - -typedef enum DCIO_GENLK_CLK_GSL_MASK { -DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000, -DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001, -DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002, -} DCIO_GENLK_CLK_GSL_MASK; - -typedef enum DCIO_GENLK_VSYNC_GSL_MASK { -DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000, -DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001, -DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002, -} DCIO_GENLK_VSYNC_GSL_MASK; - -typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL { -DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000, -DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001, -DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002, -DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003, -DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004, -} DCIO_GSL0_GLOBAL_UNLOCK_SEL; - -typedef enum DCIO_GSL0_TIMING_SYNC_SEL { -DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x00000000, -DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001, -DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002, -DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003, -DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004, -} DCIO_GSL0_TIMING_SYNC_SEL; - -typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL { -DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000, -DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001, -DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002, -DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003, -DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004, -} DCIO_GSL1_GLOBAL_UNLOCK_SEL; - -typedef enum DCIO_GSL1_TIMING_SYNC_SEL { -DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x00000000, -DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001, -DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002, -DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003, -DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004, -} DCIO_GSL1_TIMING_SYNC_SEL; - -typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL { -DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000, -DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001, -DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002, -DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003, -DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004, -} DCIO_GSL2_GLOBAL_UNLOCK_SEL; - -typedef enum DCIO_GSL2_TIMING_SYNC_SEL { -DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x00000000, -DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001, -DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002, -DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003, -DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004, -} DCIO_GSL2_TIMING_SYNC_SEL; - -typedef enum DCIO_GSL_SEL { -DCIO_GSL_SEL_GROUP_0 = 0x00000000, -DCIO_GSL_SEL_GROUP_1 = 0x00000001, -DCIO_GSL_SEL_GROUP_2 = 0x00000002, -} DCIO_GSL_SEL; - -typedef enum DCIO_GSL_VSYNC_SEL { -DCIO_GSL_VSYNC_SEL_PIPE0 = 0x00000000, -DCIO_GSL_VSYNC_SEL_PIPE1 = 0x00000001, -DCIO_GSL_VSYNC_SEL_PIPE2 = 0x00000002, -DCIO_GSL_VSYNC_SEL_PIPE3 = 0x00000003, -DCIO_GSL_VSYNC_SEL_PIPE4 = 0x00000004, -DCIO_GSL_VSYNC_SEL_PIPE5 = 0x00000005, -} DCIO_GSL_VSYNC_SEL; - -typedef enum DCIO_IMPCAL_STEP_DELAY { -DCIO_IMPCAL_STEP_DELAY_1us = 0x00000000, -DCIO_IMPCAL_STEP_DELAY_2us = 0x00000001, -DCIO_IMPCAL_STEP_DELAY_3us = 0x00000002, -DCIO_IMPCAL_STEP_DELAY_4us = 0x00000003, -DCIO_IMPCAL_STEP_DELAY_5us = 0x00000004, -DCIO_IMPCAL_STEP_DELAY_6us = 0x00000005, -DCIO_IMPCAL_STEP_DELAY_7us = 0x00000006, -DCIO_IMPCAL_STEP_DELAY_8us = 0x00000007, -DCIO_IMPCAL_STEP_DELAY_9us = 0x00000008, -DCIO_IMPCAL_STEP_DELAY_10us = 0x00000009, -DCIO_IMPCAL_STEP_DELAY_11us = 0x0000000a, -DCIO_IMPCAL_STEP_DELAY_12us = 0x0000000b, -DCIO_IMPCAL_STEP_DELAY_13us = 0x0000000c, -DCIO_IMPCAL_STEP_DELAY_14us = 0x0000000d, -DCIO_IMPCAL_STEP_DELAY_15us = 0x0000000e, -DCIO_IMPCAL_STEP_DELAY_16us = 0x0000000f, -} DCIO_IMPCAL_STEP_DELAY; - -typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN { -} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN; - -typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON { -DCIO_LVTMA_BLON_OFF = 0x00000000, -DCIO_LVTMA_BLON_ON = 0x00000001, -} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON; - -typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL { -DCIO_LVTMA_BLON_POL_NON_INVERT = 0x00000000, -DCIO_LVTMA_BLON_POL_INVERT = 0x00000001, -} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL; - -typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON { -DCIO_LVTMA_DIGON_OFF = 0x00000000, -DCIO_LVTMA_DIGON_ON = 0x00000001, -} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON; - -typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL { -DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x00000000, -DCIO_LVTMA_DIGON_POL_INVERT = 0x00000001, -} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL; - -typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL { -DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x00000000, -DCIO_LVTMA_SYNCEN_POL_INVERT = 0x00000001, -} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL; - -typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE { -DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000, -DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001, -} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE; - -typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN { -DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x00000000, -DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001, -} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN; - -typedef enum DCIO_SWAPLOCK_A_GSL_MASK { -DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000, -DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001, -DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002, -} DCIO_SWAPLOCK_A_GSL_MASK; - -typedef enum DCIO_SWAPLOCK_B_GSL_MASK { -DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000, -DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001, -DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002, -} DCIO_SWAPLOCK_B_GSL_MASK; - -typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000, -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001, -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002, -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003, -} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; - -typedef enum DCIO_UNIPHY_IMPCAL_SEL { -DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000, -DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001, -} DCIO_UNIPHY_IMPCAL_SEL; - -typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { -DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000, -DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001, -} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; - -typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000, -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001, -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002, -} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; - -typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION { -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000, -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001, -} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION; - -typedef enum ENUM_NUM_SIMD_PER_CU { -NUM_SIMD_PER_CU = 0x00000004, -} ENUM_NUM_SIMD_PER_CU; - -typedef enum GATCL1RequestType { -GATCL1_TYPE_NORMAL = 0x00000000, -GATCL1_TYPE_SHOOTDOWN = 0x00000001, -GATCL1_TYPE_BYPASS = 0x00000002, -} GATCL1RequestType; - -typedef enum MEM_PWR_DIS_CTRL { -ENABLE_MEM_PWR_CTRL = 0x00000000, -DISABLE_MEM_PWR_CTRL = 0x00000001, -} MEM_PWR_DIS_CTRL; - -typedef enum MEM_PWR_FORCE_CTRL { -NO_FORCE_REQUEST = 0x00000000, -FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, -FORCE_DEEP_SLEEP_REQUEST = 0x00000002, -FORCE_SHUT_DOWN_REQUEST = 0x00000003, -} MEM_PWR_FORCE_CTRL; - -typedef enum MEM_PWR_FORCE_CTRL2 { -NO_FORCE_REQ = 0x00000000, -FORCE_LIGHT_SLEEP_REQ = 0x00000001, -} MEM_PWR_FORCE_CTRL2; - -typedef enum MEM_PWR_SEL_CTRL { -DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, -DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001, -DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002, -} MEM_PWR_SEL_CTRL; - -typedef enum MEM_PWR_SEL_CTRL2 { -DYNAMIC_DEEP_SLEEP_EN = 0x00000000, -DYNAMIC_LIGHT_SLEEP_EN = 0x00000001, -} MEM_PWR_SEL_CTRL2; - -typedef enum MTYPE { -MTYPE_NC_NV = 0x00000000, -MTYPE_NC = 0x00000001, -MTYPE_CC = 0x00000002, -MTYPE_UC = 0x00000003, -} MTYPE; - -typedef enum SEM_PERF_SEL { -SEM_PERF_SEL_CYCLE = 0x00000000, -SEM_PERF_SEL_IDLE = 0x00000001, -SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002, -SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003, -SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000004, -SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000005, -SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000006, -SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x00000007, -SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x00000008, -SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x00000009, -SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000a, -SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000b, -SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000c, -SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x0000000d, -SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x0000000e, -SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x0000000f, -SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000010, -SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000011, -SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000012, -SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000013, -SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000014, -SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000015, -SEM_PERF_SEL_UVD_REQ_WAIT = 0x00000016, -SEM_PERF_SEL_VCE0_REQ_WAIT = 0x00000017, -SEM_PERF_SEL_ACP_REQ_WAIT = 0x00000018, -SEM_PERF_SEL_ISP_REQ_WAIT = 0x00000019, -SEM_PERF_SEL_VCE1_REQ_WAIT = 0x0000001a, -SEM_PERF_SEL_VP8_REQ_WAIT = 0x0000001b, -SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x0000001c, -SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x0000001d, -SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x0000001e, -SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x0000001f, -SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000020, -SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000021, -SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000022, -SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000023, -SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x00000024, -SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x00000025, -SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x00000026, -SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x00000027, -SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x00000028, -SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x00000029, -SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x0000002a, -SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x0000002b, -SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x0000002c, -SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x0000002d, -SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x0000002e, -SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x0000002f, -SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000030, -SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000031, -SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000032, -SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000033, -SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x00000034, -SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x00000035, -SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x00000036, -SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x00000037, -SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x00000038, -SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x00000039, -SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x0000003a, -SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x0000003b, -SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x0000003c, -SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x0000003d, -SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x0000003e, -SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x0000003f, -SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000040, -SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000041, -SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000042, -SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000043, -SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x00000044, -SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x00000045, -SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x00000046, -SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x00000047, -SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x00000048, -SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x00000049, -SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x0000004a, -SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x0000004b, -SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x0000004c, -SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x0000004d, -SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x0000004e, -SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x0000004f, -SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000050, -SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000051, -SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000052, -SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000053, -SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x00000054, -SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x00000055, -SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x00000056, -SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x00000057, -SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x00000058, -SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x00000059, -SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x0000005a, -SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x0000005b, -SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x0000005c, -SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x0000005d, -SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x0000005e, -SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x0000005f, -SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000060, -SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000061, -SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000062, -SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000063, -SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x00000064, -SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x00000065, -SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x00000066, -SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x00000067, -SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x00000068, -SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x00000069, -SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x0000006a, -SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x0000006b, -SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x0000006c, -SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x0000006d, -SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x0000006e, -SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x0000006f, -SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000070, -SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000071, -SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000072, -SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000073, -SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x00000074, -SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x00000075, -SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x00000076, -SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x00000077, -SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x00000078, -SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x00000079, -SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x0000007a, -SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x0000007b, -SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x0000007c, -SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x0000007d, -SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x0000007e, -SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x0000007f, -SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000080, -SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000081, -SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000082, -SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000083, -SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x00000084, -SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x00000085, -SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x00000086, -SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x00000087, -SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x00000088, -SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x00000089, -SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x0000008a, -SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x0000008b, -SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x0000008c, -SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x0000008d, -SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x0000008e, -SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x0000008f, -SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000090, -SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000091, -SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000092, -SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000093, -SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x00000094, -SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x00000095, -SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x00000096, -SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x00000097, -SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x00000098, -SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x00000099, -SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x0000009a, -SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x0000009b, -SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x0000009c, -SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x0000009d, -SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x0000009e, -SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x0000009f, -SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a0, -SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a1, -SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a2, -SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a3, -SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000a4, -SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000a5, -SEM_PERF_SEL_MC_RD_REQ = 0x000000a6, -SEM_PERF_SEL_MC_RD_RET = 0x000000a7, -SEM_PERF_SEL_MC_WR_REQ = 0x000000a8, -SEM_PERF_SEL_MC_WR_RET = 0x000000a9, -SEM_PERF_SEL_ATC_REQ = 0x000000aa, -SEM_PERF_SEL_ATC_RET = 0x000000ab, -SEM_PERF_SEL_ATC_XNACK = 0x000000ac, -SEM_PERF_SEL_ATC_INVALIDATION = 0x000000ad, -} SEM_PERF_SEL; - -typedef enum SH_MEM_ADDRESS_MODE { -SH_MEM_ADDRESS_MODE_GPUVM64 = 0x00000000, -SH_MEM_ADDRESS_MODE_GPUVM32 = 0x00000001, -SH_MEM_ADDRESS_MODE_HSA64 = 0x00000002, -SH_MEM_ADDRESS_MODE_HSA32 = 0x00000003, -} SH_MEM_ADDRESS_MODE; - -typedef enum SQ_EDC_INFO_SOURCE { -SQ_EDC_INFO_SOURCE_INVALID = 0x00000000, -SQ_EDC_INFO_SOURCE_INST = 0x00000001, -SQ_EDC_INFO_SOURCE_SGPR = 0x00000002, -SQ_EDC_INFO_SOURCE_VGPR = 0x00000003, -SQ_EDC_INFO_SOURCE_LDS = 0x00000004, -SQ_EDC_INFO_SOURCE_GDS = 0x00000005, -SQ_EDC_INFO_SOURCE_TA = 0x00000006, -} SQ_EDC_INFO_SOURCE; - -typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX { -SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x00000018, -SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x00000019, -} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX; - -typedef enum SRBM_GFX_CNTL_SEL { -SRBM_GFX_CNTL_BIF = 0x00000000, -SRBM_GFX_CNTL_SDMA0 = 0x00000001, -SRBM_GFX_CNTL_SDMA1 = 0x00000002, -SRBM_GFX_CNTL_GRBM = 0x00000003, -SRBM_GFX_CNTL_UVD = 0x00000004, -SRBM_GFX_CNTL_VCE0 = 0x00000005, -SRBM_GFX_CNTL_VCE1 = 0x00000006, -SRBM_GFX_CNTL_ACP = 0x00000007, -SRBM_GFX_CNTL_SMU = 0x00000008, -SRBM_GFX_CNTL_SAMMSP = 0x00000009, -SRBM_GFX_CNTL_SAMSCP = 0x0000000a, -SRBM_GFX_CNTL_ISP = 0x0000000b, -SRBM_GFX_CNTL_TST = 0x0000000c, -SRBM_GFX_CNTL_SDMA2 = 0x0000000d, -SRBM_GFX_CNTL_SDMA3 = 0x0000000e, -} SRBM_GFX_CNTL_SEL; - -typedef enum SX_BLEND_OPT { -BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000, -BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001, -BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002, -BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003, -BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004, -BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005, -BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006, -BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007, -} SX_BLEND_OPT; - -typedef enum SX_DOWNCONVERT_FORMAT { -SX_RT_EXPORT_NO_CONVERSION = 0x00000000, -SX_RT_EXPORT_32_R = 0x00000001, -SX_RT_EXPORT_32_A = 0x00000002, -SX_RT_EXPORT_10_11_11 = 0x00000003, -SX_RT_EXPORT_2_10_10_10 = 0x00000004, -SX_RT_EXPORT_8_8_8_8 = 0x00000005, -SX_RT_EXPORT_5_6_5 = 0x00000006, -SX_RT_EXPORT_1_5_5_5 = 0x00000007, -SX_RT_EXPORT_4_4_4_4 = 0x00000008, -SX_RT_EXPORT_16_16_GR = 0x00000009, -SX_RT_EXPORT_16_16_AR = 0x0000000a, -} SX_DOWNCONVERT_FORMAT; - -typedef enum SX_OPT_COMB_FCN { -OPT_COMB_NONE = 0x00000000, -OPT_COMB_ADD = 0x00000001, -OPT_COMB_SUBTRACT = 0x00000002, -OPT_COMB_MIN = 0x00000003, -OPT_COMB_MAX = 0x00000004, -OPT_COMB_REVSUBTRACT = 0x00000005, -OPT_COMB_BLEND_DISABLED = 0x00000006, -OPT_COMB_SAFE_ADD = 0x00000007, -} SX_OPT_COMB_FCN; - -typedef enum SYS_GRBM_GFX_INDEX_SEL { -GRBM_GFX_INDEX_BIF = 0x00000000, -GRBM_GFX_INDEX_SDMA0 = 0x00000001, -GRBM_GFX_INDEX_SDMA1 = 0x00000002, -RESEVERED0 = 0x00000003, -GRBM_GFX_INDEX_UVD = 0x00000004, -GRBM_GFX_INDEX_VCE0 = 0x00000005, -GRBM_GFX_INDEX_VCE1 = 0x00000006, -GRBM_GFX_INDEX_ACP = 0x00000007, -GRBM_GFX_INDEX_SMU = 0x00000008, -GRBM_GFX_INDEX_SAMMSP = 0x00000009, -GRBM_GFX_INDEX_SAMSCP = 0x0000000a, -GRBM_GFX_INDEX_ISP = 0x0000000b, -GRBM_GFX_INDEX_TST = 0x0000000c, -GRBM_GFX_INDEX_SDMA2 = 0x0000000d, -GRBM_GFX_INDEX_SDMA3 = 0x0000000e, -} SYS_GRBM_GFX_INDEX_SEL; - -typedef enum TCP_DSM_DATA_SEL { -TCP_DSM_DISABLE = 0x00000000, -TCP_DSM_SEL0 = 0x00000001, -TCP_DSM_SEL1 = 0x00000002, -TCP_DSM_SEL_BOTH = 0x00000003, -} TCP_DSM_DATA_SEL; - -typedef enum TCP_DSM_SINGLE_WRITE { -TCP_DSM_SINGLE_WRITE_EN = 0x00000001, -} TCP_DSM_SINGLE_WRITE; - -typedef enum VGT_DIST_MODE { -NO_DIST = 0x00000000, -PATCHES = 0x00000001, -DONUTS = 0x00000002, -TRAPEZOIDS = 0x00000003, -} VGT_DIST_MODE; - -typedef enum WD_IA_DRAW_SOURCE { -WD_IA_DRAW_SOURCE_DMA = 0x00000000, -WD_IA_DRAW_SOURCE_IMMD = 0x00000001, -WD_IA_DRAW_SOURCE_AUTO = 0x00000002, -WD_IA_DRAW_SOURCE_OPAQ = 0x00000003, -} WD_IA_DRAW_SOURCE; - -//Merged Defines -#define CG_SRBM_END_ADDR__CI__VI 0x000008ff -#define CG_SRBM_END_ADDR__SI 0x00000900 -#define CG_SRBM_START_ADDR 0x00000600 -#define CONFIG_SPACE1_END__CI__VI 0x00002bff -#define CONFIG_SPACE1_START__CI__VI 0x00002000 -#define CONFIG_SPACE2_END__CI__VI 0x00009fff -#define CONFIG_SPACE2_START__CI__VI 0x00003000 -#define CONFIG_SPACE_END__CI__VI 0x00009fff -#define CONFIG_SPACE_END__SI 0x000033ff -#define CONFIG_SPACE_START 0x00002000 -#define CONTEXT_SPACE_END__CI__VI 0x0000bfff -#define CONTEXT_SPACE_END__SI 0x0000afff -#define CONTEXT_SPACE_START 0x0000a000 -#define CSDATA_ADDR_WIDTH__CI__VI 0x00000007 -#define CSDATA_DATA_WIDTH__CI__VI 0x00000020 -#define CSDATA_TYPE_WIDTH__CI__VI 0x00000002 -#define GB_TILING_CONFIG_MACROTABLE_SIZE__CI__VI 0x00000010 -#define GB_TILING_CONFIG_TABLE_SIZE 0x00000020 -#define GSTHREADID_SIZE 0x00000002 -#define INST_ID_ECC_INTERRUPT_MSG__CI__VI 0xfffffff0 -#define INST_ID_HOST_REG_TRAP_MSG__CI__VI 0xfffffffe -#define INST_ID_HW_TRAP__CI__VI 0xfffffff2 -#define INST_ID_KILL_SEQ__CI__VI 0xfffffff3 -#define INST_ID_TTRACE_NEW_PC_MSG__CI__VI 0xfffffff1 -#define IQ_DEQUEUE_RETRY__CI__VI 0x00000004 -#define IQ_INTR_TYPE_IB__CI__VI 0x00000001 -#define IQ_INTR_TYPE_MQD__CI__VI 0x00000002 -#define IQ_INTR_TYPE_PQ__CI__VI 0x00000000 -#define IQ_OFFLOAD_RETRY__CI__VI 0x00000001 -#define IQ_QUEUE_SLEEP__CI__VI 0x00000000 -#define IQ_SCH_WAVE_MSG__CI__VI 0x00000002 -#define IQ_SEM_REARM__CI__VI 0x00000003 -#define KEYS_CHAIN_ADR__CI 0x00000000 -#define PERSISTENT_SPACE_END 0x00002fff -#define PERSISTENT_SPACE_START 0x00002c00 -#define RCU_CCF_BITS0__CI 0x00000500 -#define RCU_CCF_BITS1__CI 0x00001000 -#define RCU_CCF_BITS__SI 0x00000508 -#define RCU_CCF_DWORDS0__CI 0x00000028 -#define RCU_CCF_DWORDS1__CI 0x0000007f -#define RCU_SAM_BYTES__CI 0x00000040 -#define RCU_SAM_RTL_BYTES__CI 0x00000040 -#define RCU_SMU_BYTES__CI__VI 0x00000011 -#define RCU_SMU_RTL_BYTES__CI__VI 0x00000011 -#define ROM_SIGNATURE 0x0000aa55 -#define SAMU_KEY_EADR__CI 0x000000e0 -#define SAMU_KEY_SADR__CI 0x000000a1 -#define SEM_ECC_ERROR__CI__VI 0x00000000 -#define SEM_FAILED__CI__VI 0x00000002 -#define SEM_PASSED__CI__VI 0x00000003 -#define SEM_RESERVED__CI__VI 0x00000001 -#define SMC_HEADER_SIZE__CI__VI 0x00000040 -#define SMC_MSG_ADJUST_LOADLINE__CI__VI 0x00000018 -#define SMC_MSG_CASCADE_PLL_OFF__CI__VI 0x00000006 -#define SMC_MSG_CASCADE_PLL_ON__CI__VI 0x00000007 -#define SMC_MSG_CONFIG_BAPM__CI__VI 0x0000000d -#define SMC_MSG_CONFIG_HTC_LIMIT__CI__VI 0x00000010 -#define SMC_MSG_CONFIG_LCLK_DPM__CI__VI 0x00000009 -#define SMC_MSG_CONFIG_LOADLINE__CI__VI 0x00000017 -#define SMC_MSG_CONFIG_LPMx__CI__VI 0x0000000f -#define SMC_MSG_CONFIG_NBDPM__CI__VI 0x00000016 -#define SMC_MSG_CONFIG_TDC_LIMIT__CI__VI 0x0000000e -#define SMC_MSG_CONFIG_TDP_CNTL__CI__VI 0x00000013 -#define SMC_MSG_CONFIG_THERMAL_CNTL__CI__VI 0x00000011 -#define SMC_MSG_CONFIG_VOLTAGE_CNTL__CI__VI 0x00000012 -#define SMC_MSG_CONFIG_VPC_ACCUMULATOR__CI__VI 0x0000000c -#define SMC_MSG_DDI_PHY_OFF__CI__VI 0x00000004 -#define SMC_MSG_DDI_PHY_ON__CI__VI 0x00000005 -#define SMC_MSG_DIS_PM_CNTL__CI__VI 0x00000015 -#define SMC_MSG_EN_PM_CNTL__CI__VI 0x00000014 -#define SMC_MSG_FLUSH_DATA_CACHE__CI__VI 0x0000000a -#define SMC_MSG_FLUSH_INSTRUCTION_CACHE__CI__VI 0x0000000b -#define SMC_MSG_PHY_LN_OFF__CI__VI 0x00000002 -#define SMC_MSG_PHY_LN_ON__CI__VI 0x00000003 -#define SMC_MSG_PWR_OFF_x16__CI__VI 0x00000008 -#define SMC_MSG_RESET__CI__VI 0x00000020 -#define SMC_MSG_TEST__CI__VI 0x00000001 -#define SMC_MSG_VOLTAGE__CI__VI 0x00000025 -#define SMC_VERSION_MAJOR__CI__VI 0x00000007 -#define SMC_VERSION_MINOR__CI__VI 0x00000000 -#define SQDEC_BEGIN 0x00002300 -#define SQDEC_END 0x000023ff -#define SQGFXUDEC_BEGIN__CI 0x0000c340 -#define SQGFXUDEC_END__CI__VI 0x0000c380 -#define SQIND_GLOBAL_REGS_OFFSET 0x00000000 -#define SQIND_GLOBAL_REGS_SIZE 0x00000008 -#define SQIND_LOCAL_REGS_OFFSET 0x00000008 -#define SQIND_LOCAL_REGS_SIZE 0x00000008 -#define SQIND_WAVE_HWREGS_OFFSET 0x00000010 -#define SQIND_WAVE_HWREGS_SIZE 0x000001f0 -#define SQIND_WAVE_SGPRS_OFFSET 0x00000200 -#define SQIND_WAVE_SGPRS_SIZE 0x00000200 -#define SQPERFDDEC_BEGIN__CI__VI 0x0000d1c0 -#define SQPERFDDEC_END__CI__VI 0x0000d240 -#define SQPERFSDEC_BEGIN__CI__VI 0x0000d9c0 -#define SQPERFSDEC_END__CI__VI 0x0000da40 -#define SQPWRDEC_BEGIN__CI__VI 0x0000f08c -#define SQPWRDEC_END__CI__VI 0x0000f094 -#define SQ_ATTR0 0x00000000 -#define SQ_BUFFER_ATOMIC_FCMPSWAP__SI__CI 0x0000003e -#define SQ_BUFFER_ATOMIC_FCMPSWAP_X2__SI__CI 0x0000005e -#define SQ_BUFFER_ATOMIC_FMAX__SI__CI 0x00000040 -#define SQ_BUFFER_ATOMIC_FMAX_X2__SI__CI 0x00000060 -#define SQ_BUFFER_ATOMIC_FMIN__SI__CI 0x0000003f -#define SQ_BUFFER_ATOMIC_FMIN_X2__SI__CI 0x0000005f -#define SQ_BUFFER_LOAD_DWORDX3__CI 0x0000000f -#define SQ_BUFFER_LOAD_FORMAT_X 0x00000000 -#define SQ_BUFFER_LOAD_FORMAT_XY 0x00000001 -#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x00000002 -#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x00000003 -#define SQ_BUFFER_STORE_BYTE 0x00000018 -#define SQ_BUFFER_STORE_DWORD 0x0000001c -#define SQ_BUFFER_STORE_DWORDX2 0x0000001d -#define SQ_BUFFER_STORE_DWORDX3__CI 0x0000001f -#define SQ_BUFFER_STORE_FORMAT_X 0x00000004 -#define SQ_BUFFER_STORE_FORMAT_XY 0x00000005 -#define SQ_BUFFER_STORE_FORMAT_XYZ 0x00000006 -#define SQ_BUFFER_STORE_FORMAT_XYZW 0x00000007 -#define SQ_BUFFER_STORE_SHORT 0x0000001a -#define SQ_BUFFER_WBINVL1_VOL__CI 0x00000070 -#define SQ_CHAN_W 0x00000003 -#define SQ_CHAN_X 0x00000000 -#define SQ_CHAN_Y 0x00000001 -#define SQ_CHAN_Z 0x00000002 -#define SQ_CNT1 0x00000000 -#define SQ_CNT2 0x00000001 -#define SQ_CNT3 0x00000002 -#define SQ_CNT4 0x00000003 -#define SQ_DFMT_10_10_10_2__SI__CI 0x00000008 -#define SQ_DFMT_10_11_11__SI__CI 0x00000006 -#define SQ_DFMT_11_11_10__SI__CI 0x00000007 -#define SQ_DFMT_16__SI__CI 0x00000002 -#define SQ_DFMT_16_16__SI__CI 0x00000005 -#define SQ_DFMT_16_16_16_16__SI__CI 0x0000000c -#define SQ_DFMT_2_10_10_10__SI__CI 0x00000009 -#define SQ_DFMT_32__SI__CI 0x00000004 -#define SQ_DFMT_32_32__SI__CI 0x0000000b -#define SQ_DFMT_32_32_32__SI__CI 0x0000000d -#define SQ_DFMT_32_32_32_32__SI__CI 0x0000000e -#define SQ_DFMT_8__SI__CI 0x00000001 -#define SQ_DFMT_8_8__SI__CI 0x00000003 -#define SQ_DFMT_8_8_8_8__SI__CI 0x0000000a -#define SQ_DFMT_INVALID__SI__CI 0x00000000 -#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008 -#define SQ_DISPATCHER_GFX_MIN 0x00000010 -#define SQ_DS_ADD_RTN_U32 0x00000020 -#define SQ_DS_ADD_RTN_U64 0x00000060 -#define SQ_DS_ADD_SRC2_U32 0x00000080 -#define SQ_DS_ADD_SRC2_U64 0x000000c0 -#define SQ_DS_ADD_U32 0x00000000 -#define SQ_DS_ADD_U64 0x00000040 -#define SQ_DS_AND_B32 0x00000009 -#define SQ_DS_AND_B64 0x00000049 -#define SQ_DS_AND_RTN_B32 0x00000029 -#define SQ_DS_AND_RTN_B64 0x00000069 -#define SQ_DS_AND_SRC2_B32 0x00000089 -#define SQ_DS_AND_SRC2_B64 0x000000c9 -#define SQ_DS_CMPST_B32 0x00000010 -#define SQ_DS_CMPST_B64 0x00000050 -#define SQ_DS_CMPST_F32 0x00000011 -#define SQ_DS_CMPST_F64 0x00000051 -#define SQ_DS_CMPST_RTN_B32 0x00000030 -#define SQ_DS_CMPST_RTN_B64 0x00000070 -#define SQ_DS_CMPST_RTN_F32 0x00000031 -#define SQ_DS_CMPST_RTN_F64 0x00000071 -#define SQ_DS_CONDXCHG32_RTN_B128__CI__VI 0x000000fd -#define SQ_DS_CONDXCHG32_RTN_B64__CI__VI 0x0000007e -#define SQ_DS_DEC_RTN_U32 0x00000024 -#define SQ_DS_DEC_RTN_U64 0x00000064 -#define SQ_DS_DEC_SRC2_U32 0x00000084 -#define SQ_DS_DEC_SRC2_U64 0x000000c4 -#define SQ_DS_DEC_U32 0x00000004 -#define SQ_DS_DEC_U64 0x00000044 -#define SQ_DS_GWS_SEMA_RELEASE_ALL__CI 0x00000018 -#define SQ_DS_INC_RTN_U32 0x00000023 -#define SQ_DS_INC_RTN_U64 0x00000063 -#define SQ_DS_INC_SRC2_U32 0x00000083 -#define SQ_DS_INC_SRC2_U64 0x000000c3 -#define SQ_DS_INC_U32 0x00000003 -#define SQ_DS_INC_U64 0x00000043 -#define SQ_DS_MAX_F32 0x00000013 -#define SQ_DS_MAX_F64 0x00000053 -#define SQ_DS_MAX_I32 0x00000006 -#define SQ_DS_MAX_I64 0x00000046 -#define SQ_DS_MAX_RTN_F32 0x00000033 -#define SQ_DS_MAX_RTN_F64 0x00000073 -#define SQ_DS_MAX_RTN_I32 0x00000026 -#define SQ_DS_MAX_RTN_I64 0x00000066 -#define SQ_DS_MAX_RTN_U32 0x00000028 -#define SQ_DS_MAX_RTN_U64 0x00000068 -#define SQ_DS_MAX_SRC2_F32 0x00000093 -#define SQ_DS_MAX_SRC2_F64 0x000000d3 -#define SQ_DS_MAX_SRC2_I32 0x00000086 -#define SQ_DS_MAX_SRC2_I64 0x000000c6 -#define SQ_DS_MAX_SRC2_U32 0x00000088 -#define SQ_DS_MAX_SRC2_U64 0x000000c8 -#define SQ_DS_MAX_U32 0x00000008 -#define SQ_DS_MAX_U64 0x00000048 -#define SQ_DS_MIN_F32 0x00000012 -#define SQ_DS_MIN_F64 0x00000052 -#define SQ_DS_MIN_I32 0x00000005 -#define SQ_DS_MIN_I64 0x00000045 -#define SQ_DS_MIN_RTN_F32 0x00000032 -#define SQ_DS_MIN_RTN_F64 0x00000072 -#define SQ_DS_MIN_RTN_I32 0x00000025 -#define SQ_DS_MIN_RTN_I64 0x00000065 -#define SQ_DS_MIN_RTN_U32 0x00000027 -#define SQ_DS_MIN_RTN_U64 0x00000067 -#define SQ_DS_MIN_SRC2_F32 0x00000092 -#define SQ_DS_MIN_SRC2_F64 0x000000d2 -#define SQ_DS_MIN_SRC2_I32 0x00000085 -#define SQ_DS_MIN_SRC2_I64 0x000000c5 -#define SQ_DS_MIN_SRC2_U32 0x00000087 -#define SQ_DS_MIN_SRC2_U64 0x000000c7 -#define SQ_DS_MIN_U32 0x00000007 -#define SQ_DS_MIN_U64 0x00000047 -#define SQ_DS_MSKOR_B32 0x0000000c -#define SQ_DS_MSKOR_B64 0x0000004c -#define SQ_DS_MSKOR_RTN_B32 0x0000002c -#define SQ_DS_MSKOR_RTN_B64 0x0000006c -#define SQ_DS_NOP__CI__VI 0x00000014 -#define SQ_DS_OR_B32 0x0000000a -#define SQ_DS_OR_B64 0x0000004a -#define SQ_DS_OR_RTN_B32 0x0000002a -#define SQ_DS_OR_RTN_B64 0x0000006a -#define SQ_DS_OR_SRC2_B32 0x0000008a -#define SQ_DS_OR_SRC2_B64 0x000000ca -#define SQ_DS_READ2ST64_B32 0x00000038 -#define SQ_DS_READ2ST64_B64 0x00000078 -#define SQ_DS_READ2_B32 0x00000037 -#define SQ_DS_READ2_B64 0x00000077 -#define SQ_DS_READ_B128__CI__VI 0x000000ff -#define SQ_DS_READ_B32 0x00000036 -#define SQ_DS_READ_B64 0x00000076 -#define SQ_DS_READ_B96__CI__VI 0x000000fe -#define SQ_DS_READ_I16 0x0000003b -#define SQ_DS_READ_I8 0x00000039 -#define SQ_DS_READ_U16 0x0000003c -#define SQ_DS_READ_U8 0x0000003a -#define SQ_DS_RSUB_RTN_U32 0x00000022 -#define SQ_DS_RSUB_RTN_U64 0x00000062 -#define SQ_DS_RSUB_SRC2_U32 0x00000082 -#define SQ_DS_RSUB_SRC2_U64 0x000000c2 -#define SQ_DS_RSUB_U32 0x00000002 -#define SQ_DS_RSUB_U64 0x00000042 -#define SQ_DS_SUB_RTN_U32 0x00000021 -#define SQ_DS_SUB_RTN_U64 0x00000061 -#define SQ_DS_SUB_SRC2_U32 0x00000081 -#define SQ_DS_SUB_SRC2_U64 0x000000c1 -#define SQ_DS_SUB_U32 0x00000001 -#define SQ_DS_SUB_U64 0x00000041 -#define SQ_DS_WRAP_RTN_B32__CI__VI 0x00000034 -#define SQ_DS_WRITE2ST64_B32 0x0000000f -#define SQ_DS_WRITE2ST64_B64 0x0000004f -#define SQ_DS_WRITE2_B32 0x0000000e -#define SQ_DS_WRITE2_B64 0x0000004e -#define SQ_DS_WRITE_B128__CI__VI 0x000000df -#define SQ_DS_WRITE_B16 0x0000001f -#define SQ_DS_WRITE_B32 0x0000000d -#define SQ_DS_WRITE_B64 0x0000004d -#define SQ_DS_WRITE_B8 0x0000001e -#define SQ_DS_WRITE_B96__CI__VI 0x000000de -#define SQ_DS_WRITE_SRC2_B32 0x0000008d -#define SQ_DS_WRITE_SRC2_B64 0x000000cd -#define SQ_DS_WRXCHG2ST64_RTN_B32 0x0000002f -#define SQ_DS_WRXCHG2ST64_RTN_B64 0x0000006f -#define SQ_DS_WRXCHG2_RTN_B32 0x0000002e -#define SQ_DS_WRXCHG2_RTN_B64 0x0000006e -#define SQ_DS_WRXCHG_RTN_B32 0x0000002d -#define SQ_DS_WRXCHG_RTN_B64 0x0000006d -#define SQ_DS_XOR_B32 0x0000000b -#define SQ_DS_XOR_B64 0x0000004b -#define SQ_DS_XOR_RTN_B32 0x0000002b -#define SQ_DS_XOR_RTN_B64 0x0000006b -#define SQ_DS_XOR_SRC2_B32 0x0000008b -#define SQ_DS_XOR_SRC2_B64 0x000000cb -#define SQ_ENC_DS_BITS 0xd8000000 -#define SQ_ENC_DS_FIELD 0x00000036 -#define SQ_ENC_DS_MASK 0xfc000000 -#define SQ_ENC_EXP_MASK 0xfc000000 -#define SQ_ENC_FLAT_BITS__CI__VI 0xdc000000 -#define SQ_ENC_FLAT_FIELD__CI__VI 0x00000037 -#define SQ_ENC_FLAT_MASK__CI__VI 0xfc000000 -#define SQ_ENC_MIMG_BITS 0xf0000000 -#define SQ_ENC_MIMG_FIELD 0x0000003c -#define SQ_ENC_MIMG_MASK 0xfc000000 -#define SQ_ENC_MTBUF_BITS 0xe8000000 -#define SQ_ENC_MTBUF_FIELD 0x0000003a -#define SQ_ENC_MTBUF_MASK 0xfc000000 -#define SQ_ENC_MUBUF_BITS 0xe0000000 -#define SQ_ENC_MUBUF_FIELD 0x00000038 -#define SQ_ENC_MUBUF_MASK 0xfc000000 -#define SQ_ENC_SMRD_BITS__SI__CI 0xc0000000 -#define SQ_ENC_SMRD_FIELD__SI__CI 0x00000018 -#define SQ_ENC_SMRD_MASK__SI__CI 0xf8000000 -#define SQ_ENC_SOP1_BITS 0xbe800000 -#define SQ_ENC_SOP1_FIELD 0x0000017d -#define SQ_ENC_SOP1_MASK 0xff800000 -#define SQ_ENC_SOP2_BITS 0x80000000 -#define SQ_ENC_SOP2_FIELD 0x00000002 -#define SQ_ENC_SOP2_MASK 0xc0000000 -#define SQ_ENC_SOPC_BITS 0xbf000000 -#define SQ_ENC_SOPC_FIELD 0x0000017e -#define SQ_ENC_SOPC_MASK 0xff800000 -#define SQ_ENC_SOPK_BITS 0xb0000000 -#define SQ_ENC_SOPK_FIELD 0x0000000b -#define SQ_ENC_SOPK_MASK 0xf0000000 -#define SQ_ENC_SOPP_BITS 0xbf800000 -#define SQ_ENC_SOPP_FIELD 0x0000017f -#define SQ_ENC_SOPP_MASK 0xff800000 -#define SQ_ENC_VINTRP_MASK 0xfc000000 -#define SQ_ENC_VOP1_BITS 0x7e000000 -#define SQ_ENC_VOP1_FIELD 0x0000003f -#define SQ_ENC_VOP1_MASK 0xfe000000 -#define SQ_ENC_VOP2_BITS 0x00000000 -#define SQ_ENC_VOP2_FIELD 0x00000000 -#define SQ_ENC_VOP2_MASK 0x80000000 -#define SQ_ENC_VOP3_BITS 0xd0000000 -#define SQ_ENC_VOP3_FIELD 0x00000034 -#define SQ_ENC_VOP3_MASK 0xfc000000 -#define SQ_ENC_VOPC_BITS 0x7c000000 -#define SQ_ENC_VOPC_FIELD 0x0000003e -#define SQ_ENC_VOPC_MASK 0xfe000000 -#define SQ_EQ 0x00000002 -#define SQ_EXEC_HI 0x0000007f -#define SQ_EXEC_LO 0x0000007e -#define SQ_EXP 0x00000000 -#define SQ_EXP_GDS0 0x00000018 -#define SQ_EXP_MRT0 0x00000000 -#define SQ_EXP_MRTZ 0x00000008 -#define SQ_EXP_NULL 0x00000009 -#define SQ_EXP_NUM_GDS 0x00000005 -#define SQ_EXP_NUM_MRT 0x00000008 -#define SQ_EXP_NUM_PARAM 0x00000020 -#define SQ_EXP_NUM_POS 0x00000004 -#define SQ_EXP_PARAM0 0x00000020 -#define SQ_EXP_POS0 0x0000000c -#define SQ_EX_MODE_EXCP_ADDR_WATCH__CI__VI 0x00000007 -#define SQ_EX_MODE_EXCP_DIV0__CI__VI 0x00000002 -#define SQ_EX_MODE_EXCP_INEXACT__CI__VI 0x00000005 -#define SQ_EX_MODE_EXCP_INPUT_DENORM__CI__VI 0x00000001 -#define SQ_EX_MODE_EXCP_INT_DIV0__CI__VI 0x00000006 -#define SQ_EX_MODE_EXCP_INVALID__CI__VI 0x00000000 -#define SQ_EX_MODE_EXCP_MEM_VIOL__CI__VI 0x00000008 -#define SQ_EX_MODE_EXCP_OVERFLOW__CI__VI 0x00000003 -#define SQ_EX_MODE_EXCP_UNDERFLOW__CI__VI 0x00000004 -#define SQ_EX_MODE_EXCP_VALU_BASE__CI__VI 0x00000000 -#define SQ_EX_MODE_EXCP_VALU_SIZE__CI__VI 0x00000007 -#define SQ_F 0x00000000 -#define SQ_FLAT_ATOMIC_ADD_X2__CI 0x00000052 -#define SQ_FLAT_ATOMIC_ADD__CI 0x00000032 -#define SQ_FLAT_ATOMIC_AND_X2__CI 0x00000059 -#define SQ_FLAT_ATOMIC_AND__CI 0x00000039 -#define SQ_FLAT_ATOMIC_CMPSWAP_X2__CI 0x00000051 -#define SQ_FLAT_ATOMIC_CMPSWAP__CI 0x00000031 -#define SQ_FLAT_ATOMIC_DEC_X2__CI 0x0000005d -#define SQ_FLAT_ATOMIC_DEC__CI 0x0000003d -#define SQ_FLAT_ATOMIC_FCMPSWAP_X2__CI 0x0000005e -#define SQ_FLAT_ATOMIC_FCMPSWAP__CI 0x0000003e -#define SQ_FLAT_ATOMIC_FMAX_X2__CI 0x00000060 -#define SQ_FLAT_ATOMIC_FMAX__CI 0x00000040 -#define SQ_FLAT_ATOMIC_FMIN_X2__CI 0x0000005f -#define SQ_FLAT_ATOMIC_FMIN__CI 0x0000003f -#define SQ_FLAT_ATOMIC_INC_X2__CI 0x0000005c -#define SQ_FLAT_ATOMIC_INC__CI 0x0000003c -#define SQ_FLAT_ATOMIC_OR_X2__CI 0x0000005a -#define SQ_FLAT_ATOMIC_OR__CI 0x0000003a -#define SQ_FLAT_ATOMIC_SMAX_X2__CI 0x00000057 -#define SQ_FLAT_ATOMIC_SMAX__CI 0x00000037 -#define SQ_FLAT_ATOMIC_SMIN_X2__CI 0x00000055 -#define SQ_FLAT_ATOMIC_SMIN__CI 0x00000035 -#define SQ_FLAT_ATOMIC_SUB_X2__CI 0x00000053 -#define SQ_FLAT_ATOMIC_SUB__CI 0x00000033 -#define SQ_FLAT_ATOMIC_SWAP_X2__CI 0x00000050 -#define SQ_FLAT_ATOMIC_SWAP__CI 0x00000030 -#define SQ_FLAT_ATOMIC_UMAX_X2__CI 0x00000058 -#define SQ_FLAT_ATOMIC_UMAX__CI 0x00000038 -#define SQ_FLAT_ATOMIC_UMIN_X2__CI 0x00000056 -#define SQ_FLAT_ATOMIC_UMIN__CI 0x00000036 -#define SQ_FLAT_ATOMIC_XOR_X2__CI 0x0000005b -#define SQ_FLAT_ATOMIC_XOR__CI 0x0000003b -#define SQ_FLAT_LOAD_DWORDX2__CI 0x0000000d -#define SQ_FLAT_LOAD_DWORDX3__CI 0x0000000f -#define SQ_FLAT_LOAD_DWORDX4__CI 0x0000000e -#define SQ_FLAT_LOAD_DWORD__CI 0x0000000c -#define SQ_FLAT_LOAD_SBYTE__CI 0x00000009 -#define SQ_FLAT_LOAD_SSHORT__CI 0x0000000b -#define SQ_FLAT_LOAD_UBYTE__CI 0x00000008 -#define SQ_FLAT_LOAD_USHORT__CI 0x0000000a -#define SQ_FLAT_SCRATCH_HI__CI 0x00000069 -#define SQ_FLAT_SCRATCH_LO__CI 0x00000068 -#define SQ_FLAT_STORE_BYTE__CI__VI 0x00000018 -#define SQ_FLAT_STORE_DWORDX2__CI__VI 0x0000001d -#define SQ_FLAT_STORE_DWORDX3__CI 0x0000001f -#define SQ_FLAT_STORE_DWORDX4__CI 0x0000001e -#define SQ_FLAT_STORE_DWORD__CI__VI 0x0000001c -#define SQ_FLAT_STORE_SHORT__CI__VI 0x0000001a -#define SQ_GE 0x00000006 -#define SQ_GFXDEC_BEGIN 0x0000a000 -#define SQ_GFXDEC_END 0x0000c000 -#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a -#define SQ_GS_OP_CUT 0x00000001 -#define SQ_GS_OP_EMIT 0x00000002 -#define SQ_GS_OP_EMIT_CUT 0x00000003 -#define SQ_GS_OP_NOP 0x00000000 -#define SQ_GT 0x00000004 -#define SQ_HWREG_ID_SHIFT 0x00000000 -#define SQ_HWREG_ID_SIZE 0x00000006 -#define SQ_HWREG_OFFSET_SHIFT 0x00000006 -#define SQ_HWREG_OFFSET_SIZE 0x00000005 -#define SQ_HWREG_SIZE_SHIFT 0x0000000b -#define SQ_HWREG_SIZE_SIZE 0x00000005 -#define SQ_HW_REG_GPR_ALLOC 0x00000005 -#define SQ_HW_REG_HW_ID 0x00000004 -#define SQ_HW_REG_IB_DBG0 0x0000000c -#define SQ_HW_REG_IB_STS 0x00000007 -#define SQ_HW_REG_INST_DW0 0x0000000a -#define SQ_HW_REG_INST_DW1 0x0000000b -#define SQ_HW_REG_LDS_ALLOC 0x00000006 -#define SQ_HW_REG_MODE 0x00000001 -#define SQ_HW_REG_PC_HI 0x00000009 -#define SQ_HW_REG_PC_LO 0x00000008 -#define SQ_HW_REG_STATUS 0x00000002 -#define SQ_HW_REG_TRAPSTS 0x00000003 -#define SQ_IMAGE_ATOMIC_AND 0x00000018 -#define SQ_IMAGE_ATOMIC_DEC 0x0000001c -#define SQ_IMAGE_ATOMIC_FCMPSWAP__SI__CI 0x0000001d -#define SQ_IMAGE_ATOMIC_FMAX__SI__CI 0x0000001f -#define SQ_IMAGE_ATOMIC_FMIN__SI__CI 0x0000001e -#define SQ_IMAGE_ATOMIC_INC 0x0000001b -#define SQ_IMAGE_ATOMIC_OR 0x00000019 -#define SQ_IMAGE_ATOMIC_SMAX 0x00000016 -#define SQ_IMAGE_ATOMIC_SMIN 0x00000014 -#define SQ_IMAGE_ATOMIC_UMAX 0x00000017 -#define SQ_IMAGE_ATOMIC_UMIN 0x00000015 -#define SQ_IMAGE_ATOMIC_XOR 0x0000001a -#define SQ_IMAGE_GATHER4 0x00000040 -#define SQ_IMAGE_GATHER4_B 0x00000045 -#define SQ_IMAGE_GATHER4_B_CL 0x00000046 -#define SQ_IMAGE_GATHER4_B_CL_O 0x00000056 -#define SQ_IMAGE_GATHER4_B_O 0x00000055 -#define SQ_IMAGE_GATHER4_C 0x00000048 -#define SQ_IMAGE_GATHER4_CL 0x00000041 -#define SQ_IMAGE_GATHER4_CL_O 0x00000051 -#define SQ_IMAGE_GATHER4_C_B 0x0000004d -#define SQ_IMAGE_GATHER4_C_B_CL 0x0000004e -#define SQ_IMAGE_GATHER4_C_B_CL_O 0x0000005e -#define SQ_IMAGE_GATHER4_C_B_O 0x0000005d -#define SQ_IMAGE_GATHER4_C_CL 0x00000049 -#define SQ_IMAGE_GATHER4_C_CL_O 0x00000059 -#define SQ_IMAGE_GATHER4_C_L 0x0000004c -#define SQ_IMAGE_GATHER4_C_LZ 0x0000004f -#define SQ_IMAGE_GATHER4_C_LZ_O 0x0000005f -#define SQ_IMAGE_GATHER4_C_L_O 0x0000005c -#define SQ_IMAGE_GATHER4_C_O 0x00000058 -#define SQ_IMAGE_GATHER4_L 0x00000044 -#define SQ_IMAGE_GATHER4_LZ 0x00000047 -#define SQ_IMAGE_GATHER4_LZ_O 0x00000057 -#define SQ_IMAGE_GATHER4_L_O 0x00000054 -#define SQ_IMAGE_GATHER4_O 0x00000050 -#define SQ_IMAGE_GET_LOD 0x00000060 -#define SQ_IMAGE_GET_RESINFO 0x0000000e -#define SQ_IMAGE_LOAD 0x00000000 -#define SQ_IMAGE_LOAD_MIP 0x00000001 -#define SQ_IMAGE_LOAD_MIP_PCK 0x00000004 -#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x00000005 -#define SQ_IMAGE_LOAD_PCK 0x00000002 -#define SQ_IMAGE_LOAD_PCK_SGN 0x00000003 -#define SQ_IMAGE_RSRC256 0x0000007e -#define SQ_IMAGE_SAMPLE 0x00000020 -#define SQ_IMAGE_SAMPLER 0x0000007f -#define SQ_IMAGE_SAMPLE_B 0x00000025 -#define SQ_IMAGE_SAMPLE_B_CL 0x00000026 -#define SQ_IMAGE_SAMPLE_B_CL_O 0x00000036 -#define SQ_IMAGE_SAMPLE_B_O 0x00000035 -#define SQ_IMAGE_SAMPLE_C 0x00000028 -#define SQ_IMAGE_SAMPLE_CD 0x00000068 -#define SQ_IMAGE_SAMPLE_CD_CL 0x00000069 -#define SQ_IMAGE_SAMPLE_CD_CL_O 0x0000006d -#define SQ_IMAGE_SAMPLE_CD_O 0x0000006c -#define SQ_IMAGE_SAMPLE_CL 0x00000021 -#define SQ_IMAGE_SAMPLE_CL_O 0x00000031 -#define SQ_IMAGE_SAMPLE_C_B 0x0000002d -#define SQ_IMAGE_SAMPLE_C_B_CL 0x0000002e -#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x0000003e -#define SQ_IMAGE_SAMPLE_C_B_O 0x0000003d -#define SQ_IMAGE_SAMPLE_C_CD 0x0000006a -#define SQ_IMAGE_SAMPLE_C_CD_CL 0x0000006b -#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x0000006f -#define SQ_IMAGE_SAMPLE_C_CD_O 0x0000006e -#define SQ_IMAGE_SAMPLE_C_CL 0x00000029 -#define SQ_IMAGE_SAMPLE_C_CL_O 0x00000039 -#define SQ_IMAGE_SAMPLE_C_D 0x0000002a -#define SQ_IMAGE_SAMPLE_C_D_CL 0x0000002b -#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x0000003b -#define SQ_IMAGE_SAMPLE_C_D_O 0x0000003a -#define SQ_IMAGE_SAMPLE_C_L 0x0000002c -#define SQ_IMAGE_SAMPLE_C_LZ 0x0000002f -#define SQ_IMAGE_SAMPLE_C_LZ_O 0x0000003f -#define SQ_IMAGE_SAMPLE_C_L_O 0x0000003c -#define SQ_IMAGE_SAMPLE_C_O 0x00000038 -#define SQ_IMAGE_SAMPLE_D 0x00000022 -#define SQ_IMAGE_SAMPLE_D_CL 0x00000023 -#define SQ_IMAGE_SAMPLE_D_CL_O 0x00000033 -#define SQ_IMAGE_SAMPLE_D_O 0x00000032 -#define SQ_IMAGE_SAMPLE_L 0x00000024 -#define SQ_IMAGE_SAMPLE_LZ 0x00000027 -#define SQ_IMAGE_SAMPLE_LZ_O 0x00000037 -#define SQ_IMAGE_SAMPLE_L_O 0x00000034 -#define SQ_IMAGE_SAMPLE_O 0x00000030 -#define SQ_IMAGE_STORE 0x00000008 -#define SQ_IMAGE_STORE_MIP 0x00000009 -#define SQ_IMAGE_STORE_MIP_PCK 0x0000000b -#define SQ_IMAGE_STORE_PCK 0x0000000a -#define SQ_INTERRUPT_ID__SI__CI 0x000000ef -#define SQ_LE 0x00000003 -#define SQ_LG 0x00000005 -#define SQ_LT 0x00000001 -#define SQ_M0 0x0000007c -#define SQ_MAX_PGM_SGPRS 0x00000068 -#define SQ_MAX_PGM_VGPRS 0x00000100 -#define SQ_MSG_GS 0x00000002 -#define SQ_MSG_GS_DONE 0x00000003 -#define SQ_MSG_INTERRUPT 0x00000001 -#define SQ_MSG_SYSMSG 0x0000000f -#define SQ_NE 0x00000005 -#define SQ_NEQ 0x0000000d -#define SQ_NFMT_FLOAT__SI__CI 0x00000007 -#define SQ_NFMT_SINT__SI__CI 0x00000005 -#define SQ_NFMT_SNORM__SI__CI 0x00000001 -#define SQ_NFMT_SNORM_OGL__SI__CI 0x00000006 -#define SQ_NFMT_SSCALED__SI__CI 0x00000003 -#define SQ_NFMT_UINT__SI__CI 0x00000004 -#define SQ_NFMT_UNORM__SI__CI 0x00000000 -#define SQ_NFMT_USCALED__SI__CI 0x00000002 -#define SQ_NGE 0x00000009 -#define SQ_NGT 0x0000000b -#define SQ_NLE 0x0000000c -#define SQ_NLG 0x0000000a -#define SQ_NLT 0x0000000e -#define SQ_NUM_ATTR 0x00000021 -#define SQ_NUM_TTMP 0x0000000c -#define SQ_NUM_VGPR 0x00000100 -#define SQ_O 0x00000007 -#define SQ_OMOD_D2 0x00000003 -#define SQ_OMOD_M2 0x00000001 -#define SQ_OMOD_M4 0x00000002 -#define SQ_OMOD_OFF 0x00000000 -#define SQ_PARAM_P0 0x00000002 -#define SQ_PARAM_P10 0x00000000 -#define SQ_PARAM_P20 0x00000001 -#define SQ_SENDMSG_GSOP_SHIFT 0x00000004 -#define SQ_SENDMSG_GSOP_SIZE 0x00000002 -#define SQ_SENDMSG_MSG_SHIFT 0x00000000 -#define SQ_SENDMSG_MSG_SIZE 0x00000004 -#define SQ_SENDMSG_STREAMID_SHIFT 0x00000008 -#define SQ_SENDMSG_STREAMID_SIZE 0x00000002 -#define SQ_SENDMSG_SYSTEM_SHIFT 0x00000004 -#define SQ_SENDMSG_SYSTEM_SIZE 0x00000003 -#define SQ_SGPR0 0x00000000 -#define SQ_SRC_0 0x00000080 -#define SQ_SRC_0_5 0x000000f0 -#define SQ_SRC_1 0x000000f2 -#define SQ_SRC_10_INT 0x0000008a -#define SQ_SRC_11_INT 0x0000008b -#define SQ_SRC_12_INT 0x0000008c -#define SQ_SRC_13_INT 0x0000008d -#define SQ_SRC_14_INT 0x0000008e -#define SQ_SRC_15_INT 0x0000008f -#define SQ_SRC_16_INT 0x00000090 -#define SQ_SRC_17_INT 0x00000091 -#define SQ_SRC_18_INT 0x00000092 -#define SQ_SRC_19_INT 0x00000093 -#define SQ_SRC_1_INT 0x00000081 -#define SQ_SRC_2 0x000000f4 -#define SQ_SRC_20_INT 0x00000094 -#define SQ_SRC_21_INT 0x00000095 -#define SQ_SRC_22_INT 0x00000096 -#define SQ_SRC_23_INT 0x00000097 -#define SQ_SRC_24_INT 0x00000098 -#define SQ_SRC_25_INT 0x00000099 -#define SQ_SRC_26_INT 0x0000009a -#define SQ_SRC_27_INT 0x0000009b -#define SQ_SRC_28_INT 0x0000009c -#define SQ_SRC_29_INT 0x0000009d -#define SQ_SRC_2_INT 0x00000082 -#define SQ_SRC_30_INT 0x0000009e -#define SQ_SRC_31_INT 0x0000009f -#define SQ_SRC_32_INT 0x000000a0 -#define SQ_SRC_33_INT 0x000000a1 -#define SQ_SRC_34_INT 0x000000a2 -#define SQ_SRC_35_INT 0x000000a3 -#define SQ_SRC_36_INT 0x000000a4 -#define SQ_SRC_37_INT 0x000000a5 -#define SQ_SRC_38_INT 0x000000a6 -#define SQ_SRC_39_INT 0x000000a7 -#define SQ_SRC_3_INT 0x00000083 -#define SQ_SRC_4 0x000000f6 -#define SQ_SRC_40_INT 0x000000a8 -#define SQ_SRC_41_INT 0x000000a9 -#define SQ_SRC_42_INT 0x000000aa -#define SQ_SRC_43_INT 0x000000ab -#define SQ_SRC_44_INT 0x000000ac -#define SQ_SRC_45_INT 0x000000ad -#define SQ_SRC_46_INT 0x000000ae -#define SQ_SRC_47_INT 0x000000af -#define SQ_SRC_48_INT 0x000000b0 -#define SQ_SRC_49_INT 0x000000b1 -#define SQ_SRC_4_INT 0x00000084 -#define SQ_SRC_50_INT 0x000000b2 -#define SQ_SRC_51_INT 0x000000b3 -#define SQ_SRC_52_INT 0x000000b4 -#define SQ_SRC_53_INT 0x000000b5 -#define SQ_SRC_54_INT 0x000000b6 -#define SQ_SRC_55_INT 0x000000b7 -#define SQ_SRC_56_INT 0x000000b8 -#define SQ_SRC_57_INT 0x000000b9 -#define SQ_SRC_58_INT 0x000000ba -#define SQ_SRC_59_INT 0x000000bb -#define SQ_SRC_5_INT 0x00000085 -#define SQ_SRC_60_INT 0x000000bc -#define SQ_SRC_61_INT 0x000000bd -#define SQ_SRC_62_INT 0x000000be -#define SQ_SRC_63_INT 0x000000bf -#define SQ_SRC_64_INT 0x000000c0 -#define SQ_SRC_6_INT 0x00000086 -#define SQ_SRC_7_INT 0x00000087 -#define SQ_SRC_8_INT 0x00000088 -#define SQ_SRC_9_INT 0x00000089 -#define SQ_SRC_EXECZ 0x000000fc -#define SQ_SRC_LDS_DIRECT 0x000000fe -#define SQ_SRC_LITERAL 0x000000ff -#define SQ_SRC_M_0_5 0x000000f1 -#define SQ_SRC_M_1 0x000000f3 -#define SQ_SRC_M_10_INT 0x000000ca -#define SQ_SRC_M_11_INT 0x000000cb -#define SQ_SRC_M_12_INT 0x000000cc -#define SQ_SRC_M_13_INT 0x000000cd -#define SQ_SRC_M_14_INT 0x000000ce -#define SQ_SRC_M_15_INT 0x000000cf -#define SQ_SRC_M_16_INT 0x000000d0 -#define SQ_SRC_M_1_INT 0x000000c1 -#define SQ_SRC_M_2 0x000000f5 -#define SQ_SRC_M_2_INT 0x000000c2 -#define SQ_SRC_M_3_INT 0x000000c3 -#define SQ_SRC_M_4 0x000000f7 -#define SQ_SRC_M_4_INT 0x000000c4 -#define SQ_SRC_M_5_INT 0x000000c5 -#define SQ_SRC_M_6_INT 0x000000c6 -#define SQ_SRC_M_7_INT 0x000000c7 -#define SQ_SRC_M_8_INT 0x000000c8 -#define SQ_SRC_M_9_INT 0x000000c9 -#define SQ_SRC_SCC 0x000000fd -#define SQ_SRC_VCCZ 0x000000fb -#define SQ_SRC_VGPR0 0x00000100 -#define SQ_SRC_VGPR_BIT 0x00000100 -#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001 -#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x00000003 -#define SQ_SYSMSG_OP_REG_RD 0x00000002 -#define SQ_SYSMSG_OP_TTRACE_PC 0x00000004 -#define SQ_S_ADDC_U32 0x00000004 -#define SQ_S_ADD_I32 0x00000002 -#define SQ_S_ADD_U32 0x00000000 -#define SQ_S_BARRIER 0x0000000a -#define SQ_S_BITCMP0_B32 0x0000000c -#define SQ_S_BITCMP0_B64 0x0000000e -#define SQ_S_BITCMP1_B32 0x0000000d -#define SQ_S_BITCMP1_B64 0x0000000f -#define SQ_S_BRANCH 0x00000002 -#define SQ_S_BUFFER_LOAD_DWORD 0x00000008 -#define SQ_S_BUFFER_LOAD_DWORDX16 0x0000000c -#define SQ_S_BUFFER_LOAD_DWORDX2 0x00000009 -#define SQ_S_BUFFER_LOAD_DWORDX4 0x0000000a -#define SQ_S_BUFFER_LOAD_DWORDX8 0x0000000b -#define SQ_S_CBRANCH_CDBGSYS_AND_USER__CI__VI 0x0000001a -#define SQ_S_CBRANCH_CDBGSYS_OR_USER__CI__VI 0x00000019 -#define SQ_S_CBRANCH_CDBGSYS__CI__VI 0x00000017 -#define SQ_S_CBRANCH_CDBGUSER__CI__VI 0x00000018 -#define SQ_S_CBRANCH_EXECNZ 0x00000009 -#define SQ_S_CBRANCH_EXECZ 0x00000008 -#define SQ_S_CBRANCH_SCC0 0x00000004 -#define SQ_S_CBRANCH_SCC1 0x00000005 -#define SQ_S_CBRANCH_VCCNZ 0x00000007 -#define SQ_S_CBRANCH_VCCZ 0x00000006 -#define SQ_S_CMP_EQ_I32 0x00000000 -#define SQ_S_CMP_EQ_U32 0x00000006 -#define SQ_S_CMP_GE_I32 0x00000003 -#define SQ_S_CMP_GE_U32 0x00000009 -#define SQ_S_CMP_GT_I32 0x00000002 -#define SQ_S_CMP_GT_U32 0x00000008 -#define SQ_S_CMP_LE_I32 0x00000005 -#define SQ_S_CMP_LE_U32 0x0000000b -#define SQ_S_CMP_LG_I32 0x00000001 -#define SQ_S_CMP_LG_U32 0x00000007 -#define SQ_S_CMP_LT_I32 0x00000004 -#define SQ_S_CMP_LT_U32 0x0000000a -#define SQ_S_CSELECT_B32 0x0000000a -#define SQ_S_CSELECT_B64 0x0000000b -#define SQ_S_DCACHE_INV_VOL__CI 0x0000001d -#define SQ_S_DECPERFLEVEL 0x00000015 -#define SQ_S_ENDPGM 0x00000001 -#define SQ_S_ICACHE_INV 0x00000013 -#define SQ_S_INCPERFLEVEL 0x00000014 -#define SQ_S_LOAD_DWORD 0x00000000 -#define SQ_S_LOAD_DWORDX16 0x00000004 -#define SQ_S_LOAD_DWORDX2 0x00000001 -#define SQ_S_LOAD_DWORDX4 0x00000002 -#define SQ_S_LOAD_DWORDX8 0x00000003 -#define SQ_S_MAX_I32 0x00000008 -#define SQ_S_MAX_U32 0x00000009 -#define SQ_S_MIN_I32 0x00000006 -#define SQ_S_MIN_U32 0x00000007 -#define SQ_S_MOVK_I32 0x00000000 -#define SQ_S_NOP 0x00000000 -#define SQ_S_SENDMSG 0x00000010 -#define SQ_S_SENDMSGHALT 0x00000011 -#define SQ_S_SETHALT 0x0000000d -#define SQ_S_SETKILL__CI__VI 0x0000000b -#define SQ_S_SETPRIO 0x0000000f -#define SQ_S_SETVSKIP 0x00000010 -#define SQ_S_SLEEP 0x0000000e -#define SQ_S_SUBB_U32 0x00000005 -#define SQ_S_SUB_I32 0x00000003 -#define SQ_S_SUB_U32 0x00000001 -#define SQ_S_TRAP 0x00000012 -#define SQ_S_TTRACEDATA 0x00000016 -#define SQ_S_WAITCNT 0x0000000c -#define SQ_T 0x00000007 -#define SQ_TBA_HI 0x0000006d -#define SQ_TBA_LO 0x0000006c -#define SQ_TBUFFER_LOAD_FORMAT_X 0x00000000 -#define SQ_TBUFFER_LOAD_FORMAT_XY 0x00000001 -#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x00000002 -#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x00000003 -#define SQ_TBUFFER_STORE_FORMAT_X 0x00000004 -#define SQ_TBUFFER_STORE_FORMAT_XY 0x00000005 -#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x00000006 -#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x00000007 -#define SQ_THREAD_TRACE_LFSR_CS__SI__CI 0x00008097 -#define SQ_THREAD_TRACE_LFSR_ES__SI__CI 0x00008029 -#define SQ_THREAD_TRACE_LFSR_GS__SI__CI 0x0000801f -#define SQ_THREAD_TRACE_LFSR_HS__SI__CI 0x0000805e -#define SQ_THREAD_TRACE_LFSR_LS__SI__CI 0x0000806b -#define SQ_THREAD_TRACE_LFSR_PS__SI__CI 0x00008016 -#define SQ_THREAD_TRACE_LFSR_VS__SI__CI 0x0000801c -#define SQ_THREAD_TRACE_TIME_UNIT 0x00000004 -#define SQ_TMA_HI 0x0000006f -#define SQ_TMA_LO 0x0000006e -#define SQ_TRU 0x0000000f -#define SQ_TTMP0 0x00000070 -#define SQ_TTMP1 0x00000071 -#define SQ_TTMP10 0x0000007a -#define SQ_TTMP11 0x0000007b -#define SQ_TTMP2 0x00000072 -#define SQ_TTMP3 0x00000073 -#define SQ_TTMP4 0x00000074 -#define SQ_TTMP5 0x00000075 -#define SQ_TTMP6 0x00000076 -#define SQ_TTMP7 0x00000077 -#define SQ_TTMP8 0x00000078 -#define SQ_TTMP9 0x00000079 -#define SQ_U 0x00000008 -#define SQ_VCC_ALL 0x00000000 -#define SQ_VCC_HI 0x0000006b -#define SQ_VCC_LO 0x0000006a -#define SQ_VGPR0 0x00000000 -#define SQ_V_ADD_I32__SI__CI 0x00000025 -#define SQ_V_ASHR_I32__SI__CI 0x00000017 -#define SQ_V_ASHR_I64__SI__CI 0x00000163 -#define SQ_V_CEIL_F64__CI__VI 0x00000018 -#define SQ_V_CMPSX_EQ_F32__SI__CI 0x00000052 -#define SQ_V_CMPSX_EQ_F64__SI__CI 0x00000072 -#define SQ_V_CMPSX_F_F32__SI__CI 0x00000050 -#define SQ_V_CMPSX_F_F64__SI__CI 0x00000070 -#define SQ_V_CMPSX_GE_F32__SI__CI 0x00000056 -#define SQ_V_CMPSX_GE_F64__SI__CI 0x00000076 -#define SQ_V_CMPSX_GT_F32__SI__CI 0x00000054 -#define SQ_V_CMPSX_GT_F64__SI__CI 0x00000074 -#define SQ_V_CMPSX_LE_F32__SI__CI 0x00000053 -#define SQ_V_CMPSX_LE_F64__SI__CI 0x00000073 -#define SQ_V_CMPSX_LG_F32__SI__CI 0x00000055 -#define SQ_V_CMPSX_LG_F64__SI__CI 0x00000075 -#define SQ_V_CMPSX_LT_F32__SI__CI 0x00000051 -#define SQ_V_CMPSX_LT_F64__SI__CI 0x00000071 -#define SQ_V_CMPSX_NEQ_F32__SI__CI 0x0000005d -#define SQ_V_CMPSX_NEQ_F64__SI__CI 0x0000007d -#define SQ_V_CMPSX_NGE_F32__SI__CI 0x00000059 -#define SQ_V_CMPSX_NGE_F64__SI__CI 0x00000079 -#define SQ_V_CMPSX_NGT_F32__SI__CI 0x0000005b -#define SQ_V_CMPSX_NGT_F64__SI__CI 0x0000007b -#define SQ_V_CMPSX_NLE_F32__SI__CI 0x0000005c -#define SQ_V_CMPSX_NLE_F64__SI__CI 0x0000007c -#define SQ_V_CMPSX_NLG_F32__SI__CI 0x0000005a -#define SQ_V_CMPSX_NLG_F64__SI__CI 0x0000007a -#define SQ_V_CMPSX_NLT_F32__SI__CI 0x0000005e -#define SQ_V_CMPSX_NLT_F64__SI__CI 0x0000007e -#define SQ_V_CMPSX_O_F32__SI__CI 0x00000057 -#define SQ_V_CMPSX_O_F64__SI__CI 0x00000077 -#define SQ_V_CMPSX_TRU_F32__SI__CI 0x0000005f -#define SQ_V_CMPSX_TRU_F64__SI__CI 0x0000007f -#define SQ_V_CMPSX_U_F32__SI__CI 0x00000058 -#define SQ_V_CMPSX_U_F64__SI__CI 0x00000078 -#define SQ_V_CMPS_EQ_F32__SI__CI 0x00000042 -#define SQ_V_CMPS_EQ_F64__SI__CI 0x00000062 -#define SQ_V_CMPS_F_F32__SI__CI 0x00000040 -#define SQ_V_CMPS_F_F64__SI__CI 0x00000060 -#define SQ_V_CMPS_GE_F32__SI__CI 0x00000046 -#define SQ_V_CMPS_GE_F64__SI__CI 0x00000066 -#define SQ_V_CMPS_GT_F32__SI__CI 0x00000044 -#define SQ_V_CMPS_GT_F64__SI__CI 0x00000064 -#define SQ_V_CMPS_LE_F32__SI__CI 0x00000043 -#define SQ_V_CMPS_LE_F64__SI__CI 0x00000063 -#define SQ_V_CMPS_LG_F32__SI__CI 0x00000045 -#define SQ_V_CMPS_LG_F64__SI__CI 0x00000065 -#define SQ_V_CMPS_LT_F32__SI__CI 0x00000041 -#define SQ_V_CMPS_LT_F64__SI__CI 0x00000061 -#define SQ_V_CMPS_NEQ_F32__SI__CI 0x0000004d -#define SQ_V_CMPS_NEQ_F64__SI__CI 0x0000006d -#define SQ_V_CMPS_NGE_F32__SI__CI 0x00000049 -#define SQ_V_CMPS_NGE_F64__SI__CI 0x00000069 -#define SQ_V_CMPS_NGT_F32__SI__CI 0x0000004b -#define SQ_V_CMPS_NGT_F64__SI__CI 0x0000006b -#define SQ_V_CMPS_NLE_F32__SI__CI 0x0000004c -#define SQ_V_CMPS_NLE_F64__SI__CI 0x0000006c -#define SQ_V_CMPS_NLG_F32__SI__CI 0x0000004a -#define SQ_V_CMPS_NLG_F64__SI__CI 0x0000006a -#define SQ_V_CMPS_NLT_F32__SI__CI 0x0000004e -#define SQ_V_CMPS_NLT_F64__SI__CI 0x0000006e -#define SQ_V_CMPS_O_F32__SI__CI 0x00000047 -#define SQ_V_CMPS_O_F64__SI__CI 0x00000067 -#define SQ_V_CMPS_TRU_F32__SI__CI 0x0000004f -#define SQ_V_CMPS_TRU_F64__SI__CI 0x0000006f -#define SQ_V_CMPS_U_F32__SI__CI 0x00000048 -#define SQ_V_CMPS_U_F64__SI__CI 0x00000068 -#define SQ_V_CNDMASK_B32 0x00000000 -#define SQ_V_CVT_F16_F32 0x0000000a -#define SQ_V_CVT_F32_F16 0x0000000b -#define SQ_V_CVT_F32_F64 0x0000000f -#define SQ_V_CVT_F32_I32 0x00000005 -#define SQ_V_CVT_F32_U32 0x00000006 -#define SQ_V_CVT_F32_UBYTE0 0x00000011 -#define SQ_V_CVT_F32_UBYTE1 0x00000012 -#define SQ_V_CVT_F32_UBYTE2 0x00000013 -#define SQ_V_CVT_F32_UBYTE3 0x00000014 -#define SQ_V_CVT_F64_F32 0x00000010 -#define SQ_V_CVT_F64_I32 0x00000004 -#define SQ_V_CVT_F64_U32 0x00000016 -#define SQ_V_CVT_FLR_I32_F32 0x0000000d -#define SQ_V_CVT_I32_F32 0x00000008 -#define SQ_V_CVT_I32_F64 0x00000003 -#define SQ_V_CVT_OFF_F32_I4 0x0000000e -#define SQ_V_CVT_RPI_I32_F32 0x0000000c -#define SQ_V_CVT_U32_F32 0x00000007 -#define SQ_V_CVT_U32_F64 0x00000015 -#define SQ_V_EXP_LEGACY_F32__CI 0x00000046 -#define SQ_V_FLOOR_F64__CI__VI 0x0000001a -#define SQ_V_INTERP_MOV_F32 0x00000002 -#define SQ_V_INTERP_P1_F32 0x00000000 -#define SQ_V_INTERP_P2_F32 0x00000001 -#define SQ_V_LOG_CLAMP_F32__SI__CI 0x00000026 -#define SQ_V_LOG_LEGACY_F32__CI 0x00000045 -#define SQ_V_LSHL_B32__SI__CI 0x00000019 -#define SQ_V_LSHL_B64__SI__CI 0x00000161 -#define SQ_V_LSHR_B32__SI__CI 0x00000015 -#define SQ_V_LSHR_B64__SI__CI 0x00000162 -#define SQ_V_MAD_I64_I32__CI 0x00000177 -#define SQ_V_MAD_U64_U32__CI 0x00000176 -#define SQ_V_MAX_LEGACY_F32__SI__CI 0x0000000e -#define SQ_V_MIN_LEGACY_F32__SI__CI 0x0000000d -#define SQ_V_MOV_B32 0x00000001 -#define SQ_V_MOV_FED_B32 0x00000009 -#define SQ_V_MQSAD_PK_U16_U8__CI 0x00000173 -#define SQ_V_MQSAD_U32_U8__CI 0x00000175 -#define SQ_V_MULLIT_F32__SI__CI 0x00000150 -#define SQ_V_MUL_LO_I32__SI__CI 0x0000016b -#define SQ_V_NOP 0x00000000 -#define SQ_V_OP1_COUNT 0x00000080 -#define SQ_V_OP2_COUNT 0x00000040 -#define SQ_V_OP2_OFFSET 0x00000100 -#define SQ_V_OPC_COUNT 0x00000100 -#define SQ_V_OPC_OFFSET 0x00000000 -#define SQ_V_QSAD_PK_U16_U8__CI 0x00000172 -#define SQ_V_RCP_CLAMP_F32__SI__CI 0x00000028 -#define SQ_V_RCP_CLAMP_F64__SI__CI 0x00000030 -#define SQ_V_RCP_LEGACY_F32__SI__CI 0x00000029 -#define SQ_V_READFIRSTLANE_B32 0x00000002 -#define SQ_V_RNDNE_F64__CI__VI 0x00000019 -#define SQ_V_RSQ_CLAMP_F32__SI__CI 0x0000002c -#define SQ_V_RSQ_CLAMP_F64__SI__CI 0x00000032 -#define SQ_V_RSQ_LEGACY_F32__SI__CI 0x0000002d -#define SQ_V_SUBREV_I32__SI__CI 0x00000027 -#define SQ_V_SUB_I32__SI__CI 0x00000026 -#define SQ_V_TRUNC_F64__CI__VI 0x00000017 -#define SQ_WAITCNT_EXP_SHIFT 0x00000004 -#define SQ_WAITCNT_EXP_SIZE 0x00000003 -#define SQ_WAITCNT_LGKM_SHIFT 0x00000008 -#define SQ_WAITCNT_LGKM_SIZE 0x00000004 -#define SQ_WAITCNT_VM_SHIFT 0x00000000 -#define SQ_WAITCNT_VM_SIZE 0x00000004 -#define SQ_WAVE_TYPE_PS0 0x00000000 -#define UCONFIG_SPACE_END__CI__VI 0x0000ffff -#define UCONFIG_SPACE_START__CI__VI 0x0000c000 -#define VMID_SZ__CI__VI 0x00000004 - -//Merged Defines - -#define INST_ID_PRIV_START__VI 0x80000000 -#define INST_ID_SPI_WREXEC__VI 0xfffffff4 -#define KEYS_CHAIN_ADR__VI 0x00000002 -#define RCU_CCF_BITS__VI 0x000002a0 -#define RCU_CCF_BITS0__VI 0x00001400 -#define RCU_CCF_DWORDS__VI 0x00000015 -#define RCU_CCF_DWORDS0__VI 0x000000a0 -#define RCU_SAM_BYTES__VI 0x00000062 -#define RCU_SAM_RTL_BYTES__VI 0x00000062 -#define SAMU_KEY_CHAIN_ADR__VI 0x00000000 -#define SAMU_KEY_EADR__VI 0x00000061 -#define SAMU_KEY_SADR__VI 0x00000000 -#define SFP_BYTES__VI 0x00000080 -#define SFP_CHAIN_ADDR__VI 0x00000003 -#define SFP_EADR__VI 0x0000037f -#define SFP_SADR__VI 0x00000000 -#define SMU_KEY_CHAIN_ADR__VI 0x00000000 -#define SMU_KEY_EADR__VI 0x00000072 -#define SMU_KEY_SADR__VI 0x00000062 -#define SQGFXUDEC_BEGIN__VI 0x0000c330 -#define SQ_BUFFER_ATOMIC_ADD__SI__CI 0x00000032 -#define SQ_BUFFER_ATOMIC_ADD__VI 0x00000042 -#define SQ_BUFFER_ATOMIC_ADD_X2__SI__CI 0x00000052 -#define SQ_BUFFER_ATOMIC_ADD_X2__VI 0x00000062 -#define SQ_BUFFER_ATOMIC_AND__SI__CI 0x00000039 -#define SQ_BUFFER_ATOMIC_AND__VI 0x00000048 -#define SQ_BUFFER_ATOMIC_AND_X2__SI__CI 0x00000059 -#define SQ_BUFFER_ATOMIC_AND_X2__VI 0x00000068 -#define SQ_BUFFER_ATOMIC_CMPSWAP__SI__CI 0x00000031 -#define SQ_BUFFER_ATOMIC_CMPSWAP__VI 0x00000041 -#define SQ_BUFFER_ATOMIC_CMPSWAP_X2__SI__CI 0x00000051 -#define SQ_BUFFER_ATOMIC_CMPSWAP_X2__VI 0x00000061 -#define SQ_BUFFER_ATOMIC_DEC__SI__CI 0x0000003d -#define SQ_BUFFER_ATOMIC_DEC__VI 0x0000004c -#define SQ_BUFFER_ATOMIC_DEC_X2__SI__CI 0x0000005d -#define SQ_BUFFER_ATOMIC_DEC_X2__VI 0x0000006c -#define SQ_BUFFER_ATOMIC_INC__SI__CI 0x0000003c -#define SQ_BUFFER_ATOMIC_INC__VI 0x0000004b -#define SQ_BUFFER_ATOMIC_INC_X2__SI__CI 0x0000005c -#define SQ_BUFFER_ATOMIC_INC_X2__VI 0x0000006b -#define SQ_BUFFER_ATOMIC_OR__SI__CI 0x0000003a -#define SQ_BUFFER_ATOMIC_OR__VI 0x00000049 -#define SQ_BUFFER_ATOMIC_OR_X2__SI__CI 0x0000005a -#define SQ_BUFFER_ATOMIC_OR_X2__VI 0x00000069 -#define SQ_BUFFER_ATOMIC_SMAX__SI__CI 0x00000037 -#define SQ_BUFFER_ATOMIC_SMAX__VI 0x00000046 -#define SQ_BUFFER_ATOMIC_SMAX_X2__SI__CI 0x00000057 -#define SQ_BUFFER_ATOMIC_SMAX_X2__VI 0x00000066 -#define SQ_BUFFER_ATOMIC_SMIN__SI__CI 0x00000035 -#define SQ_BUFFER_ATOMIC_SMIN__VI 0x00000044 -#define SQ_BUFFER_ATOMIC_SMIN_X2__SI__CI 0x00000055 -#define SQ_BUFFER_ATOMIC_SMIN_X2__VI 0x00000064 -#define SQ_BUFFER_ATOMIC_SUB__SI__CI 0x00000033 -#define SQ_BUFFER_ATOMIC_SUB__VI 0x00000043 -#define SQ_BUFFER_ATOMIC_SUB_X2__SI__CI 0x00000053 -#define SQ_BUFFER_ATOMIC_SUB_X2__VI 0x00000063 -#define SQ_BUFFER_ATOMIC_SWAP__SI__CI 0x00000030 -#define SQ_BUFFER_ATOMIC_SWAP__VI 0x00000040 -#define SQ_BUFFER_ATOMIC_SWAP_X2__SI__CI 0x00000050 -#define SQ_BUFFER_ATOMIC_SWAP_X2__VI 0x00000060 -#define SQ_BUFFER_ATOMIC_UMAX__SI__CI 0x00000038 -#define SQ_BUFFER_ATOMIC_UMAX__VI 0x00000047 -#define SQ_BUFFER_ATOMIC_UMAX_X2__SI__CI 0x00000058 -#define SQ_BUFFER_ATOMIC_UMAX_X2__VI 0x00000067 -#define SQ_BUFFER_ATOMIC_UMIN__SI__CI 0x00000036 -#define SQ_BUFFER_ATOMIC_UMIN__VI 0x00000045 -#define SQ_BUFFER_ATOMIC_UMIN_X2__SI__CI 0x00000056 -#define SQ_BUFFER_ATOMIC_UMIN_X2__VI 0x00000065 -#define SQ_BUFFER_ATOMIC_XOR__SI__CI 0x0000003b -#define SQ_BUFFER_ATOMIC_XOR__VI 0x0000004a -#define SQ_BUFFER_ATOMIC_XOR_X2__SI__CI 0x0000005b -#define SQ_BUFFER_ATOMIC_XOR_X2__VI 0x0000006a -#define SQ_BUFFER_LOAD_DWORD__SI__CI 0x0000000c -#define SQ_BUFFER_LOAD_DWORD__VI 0x00000014 -#define SQ_BUFFER_LOAD_DWORDX2__SI__CI 0x0000000d -#define SQ_BUFFER_LOAD_DWORDX2__VI 0x00000015 -#define SQ_BUFFER_LOAD_DWORDX3__VI 0x00000016 -#define SQ_BUFFER_LOAD_DWORDX4__SI__CI 0x0000000e -#define SQ_BUFFER_LOAD_DWORDX4__VI 0x00000017 -#define SQ_BUFFER_LOAD_FORMAT_D16_X__VI 0x00000008 -#define SQ_BUFFER_LOAD_FORMAT_D16_XY__VI 0x00000009 -#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ__VI 0x0000000a -#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW__VI 0x0000000b -#define SQ_BUFFER_LOAD_SBYTE__SI__CI 0x00000009 -#define SQ_BUFFER_LOAD_SBYTE__VI 0x00000011 -#define SQ_BUFFER_LOAD_SSHORT__SI__CI 0x0000000b -#define SQ_BUFFER_LOAD_SSHORT__VI 0x00000013 -#define SQ_BUFFER_LOAD_UBYTE__SI__CI 0x00000008 -#define SQ_BUFFER_LOAD_UBYTE__VI 0x00000010 -#define SQ_BUFFER_LOAD_USHORT__SI__CI 0x0000000a -#define SQ_BUFFER_LOAD_USHORT__VI 0x00000012 -#define SQ_BUFFER_STORE_DWORDX3__VI 0x0000001e -#define SQ_BUFFER_STORE_DWORDX4__SI__CI 0x0000001e -#define SQ_BUFFER_STORE_DWORDX4__VI 0x0000001f -#define SQ_BUFFER_STORE_FORMAT_D16_X__VI 0x0000000c -#define SQ_BUFFER_STORE_FORMAT_D16_XY__VI 0x0000000d -#define SQ_BUFFER_STORE_FORMAT_D16_XYZ__VI 0x0000000e -#define SQ_BUFFER_STORE_FORMAT_D16_XYZW__VI 0x0000000f -#define SQ_BUFFER_STORE_LDS_DWORD__VI 0x0000003d -#define SQ_BUFFER_WBINVL1__SI__CI 0x00000071 -#define SQ_BUFFER_WBINVL1__VI 0x0000003e -#define SQ_BUFFER_WBINVL1_VOL__VI 0x0000003f -#define SQ_DPP_BOUND_OFF__VI 0x00000000 -#define SQ_DPP_BOUND_ZERO__VI 0x00000001 -#define SQ_DPP_QUAD_PERM__VI 0x00000000 -#define SQ_DPP_ROW_BCAST15__VI 0x00000142 -#define SQ_DPP_ROW_BCAST31__VI 0x00000143 -#define SQ_DPP_ROW_HALF_MIRROR__VI 0x00000141 -#define SQ_DPP_ROW_MIRROR__VI 0x00000140 -#define SQ_DPP_ROW_RR1__VI 0x00000121 -#define SQ_DPP_ROW_RR10__VI 0x0000012a -#define SQ_DPP_ROW_RR11__VI 0x0000012b -#define SQ_DPP_ROW_RR12__VI 0x0000012c -#define SQ_DPP_ROW_RR13__VI 0x0000012d -#define SQ_DPP_ROW_RR14__VI 0x0000012e -#define SQ_DPP_ROW_RR15__VI 0x0000012f -#define SQ_DPP_ROW_RR2__VI 0x00000122 -#define SQ_DPP_ROW_RR3__VI 0x00000123 -#define SQ_DPP_ROW_RR4__VI 0x00000124 -#define SQ_DPP_ROW_RR5__VI 0x00000125 -#define SQ_DPP_ROW_RR6__VI 0x00000126 -#define SQ_DPP_ROW_RR7__VI 0x00000127 -#define SQ_DPP_ROW_RR8__VI 0x00000128 -#define SQ_DPP_ROW_RR9__VI 0x00000129 -#define SQ_DPP_ROW_SL1__VI 0x00000101 -#define SQ_DPP_ROW_SL10__VI 0x0000010a -#define SQ_DPP_ROW_SL11__VI 0x0000010b -#define SQ_DPP_ROW_SL12__VI 0x0000010c -#define SQ_DPP_ROW_SL13__VI 0x0000010d -#define SQ_DPP_ROW_SL14__VI 0x0000010e -#define SQ_DPP_ROW_SL15__VI 0x0000010f -#define SQ_DPP_ROW_SL2__VI 0x00000102 -#define SQ_DPP_ROW_SL3__VI 0x00000103 -#define SQ_DPP_ROW_SL4__VI 0x00000104 -#define SQ_DPP_ROW_SL5__VI 0x00000105 -#define SQ_DPP_ROW_SL6__VI 0x00000106 -#define SQ_DPP_ROW_SL7__VI 0x00000107 -#define SQ_DPP_ROW_SL8__VI 0x00000108 -#define SQ_DPP_ROW_SL9__VI 0x00000109 -#define SQ_DPP_ROW_SR1__VI 0x00000111 -#define SQ_DPP_ROW_SR10__VI 0x0000011a -#define SQ_DPP_ROW_SR11__VI 0x0000011b -#define SQ_DPP_ROW_SR12__VI 0x0000011c -#define SQ_DPP_ROW_SR13__VI 0x0000011d -#define SQ_DPP_ROW_SR14__VI 0x0000011e -#define SQ_DPP_ROW_SR15__VI 0x0000011f -#define SQ_DPP_ROW_SR2__VI 0x00000112 -#define SQ_DPP_ROW_SR3__VI 0x00000113 -#define SQ_DPP_ROW_SR4__VI 0x00000114 -#define SQ_DPP_ROW_SR5__VI 0x00000115 -#define SQ_DPP_ROW_SR6__VI 0x00000116 -#define SQ_DPP_ROW_SR7__VI 0x00000117 -#define SQ_DPP_ROW_SR8__VI 0x00000118 -#define SQ_DPP_ROW_SR9__VI 0x00000119 -#define SQ_DPP_WF_RL1__VI 0x00000134 -#define SQ_DPP_WF_RR1__VI 0x0000013c -#define SQ_DPP_WF_SL1__VI 0x00000130 -#define SQ_DPP_WF_SR1__VI 0x00000138 -#define SQ_DS_ADD_F32__VI 0x00000015 -#define SQ_DS_ADD_RTN_F32__VI 0x00000035 -#define SQ_DS_ADD_SRC2_F32__VI 0x00000095 -#define SQ_DS_APPEND__SI__CI 0x0000003e -#define SQ_DS_APPEND__VI 0x000000be -#define SQ_DS_BPERMUTE_B32__VI 0x0000003f -#define SQ_DS_CONSUME__SI__CI 0x0000003d -#define SQ_DS_CONSUME__VI 0x000000bd -#define SQ_DS_GWS_BARRIER__SI__CI 0x0000001d -#define SQ_DS_GWS_BARRIER__VI 0x0000009d -#define SQ_DS_GWS_INIT__SI__CI 0x00000019 -#define SQ_DS_GWS_INIT__VI 0x00000099 -#define SQ_DS_GWS_SEMA_BR__SI__CI 0x0000001b -#define SQ_DS_GWS_SEMA_BR__VI 0x0000009b -#define SQ_DS_GWS_SEMA_P__SI__CI 0x0000001c -#define SQ_DS_GWS_SEMA_P__VI 0x0000009c -#define SQ_DS_GWS_SEMA_RELEASE_ALL__VI 0x00000098 -#define SQ_DS_GWS_SEMA_V__SI__CI 0x0000001a -#define SQ_DS_GWS_SEMA_V__VI 0x0000009a -#define SQ_DS_ORDERED_COUNT__SI__CI 0x0000003f -#define SQ_DS_ORDERED_COUNT__VI 0x000000bf -#define SQ_DS_PERMUTE_B32__VI 0x0000003e -#define SQ_DS_SWIZZLE_B32__SI__CI 0x00000035 -#define SQ_DS_SWIZZLE_B32__VI 0x0000003d -#define SQ_ENC_EXP_BITS__SI__CI 0xf8000000 -#define SQ_ENC_EXP_BITS__VI 0xc4000000 -#define SQ_ENC_EXP_FIELD__SI__CI 0x0000003e -#define SQ_ENC_EXP_FIELD__VI 0x00000031 -#define SQ_ENC_SMEM_BITS__VI 0xc0000000 -#define SQ_ENC_SMEM_FIELD__VI 0x00000030 -#define SQ_ENC_SMEM_MASK__VI 0xfc000000 -#define SQ_ENC_VINTRP_BITS__SI__CI 0xc8000000 -#define SQ_ENC_VINTRP_BITS__VI 0xd4000000 -#define SQ_ENC_VINTRP_FIELD__SI__CI 0x00000032 -#define SQ_ENC_VINTRP_FIELD__VI 0x00000035 -#define SQ_FLAT_ATOMIC_ADD__VI 0x00000042 -#define SQ_FLAT_ATOMIC_ADD_X2__VI 0x00000062 -#define SQ_FLAT_ATOMIC_AND__VI 0x00000048 -#define SQ_FLAT_ATOMIC_AND_X2__VI 0x00000068 -#define SQ_FLAT_ATOMIC_CMPSWAP__VI 0x00000041 -#define SQ_FLAT_ATOMIC_CMPSWAP_X2__VI 0x00000061 -#define SQ_FLAT_ATOMIC_DEC__VI 0x0000004c -#define SQ_FLAT_ATOMIC_DEC_X2__VI 0x0000006c -#define SQ_FLAT_ATOMIC_INC__VI 0x0000004b -#define SQ_FLAT_ATOMIC_INC_X2__VI 0x0000006b -#define SQ_FLAT_ATOMIC_OR__VI 0x00000049 -#define SQ_FLAT_ATOMIC_OR_X2__VI 0x00000069 -#define SQ_FLAT_ATOMIC_SMAX__VI 0x00000046 -#define SQ_FLAT_ATOMIC_SMAX_X2__VI 0x00000066 -#define SQ_FLAT_ATOMIC_SMIN__VI 0x00000044 -#define SQ_FLAT_ATOMIC_SMIN_X2__VI 0x00000064 -#define SQ_FLAT_ATOMIC_SUB__VI 0x00000043 -#define SQ_FLAT_ATOMIC_SUB_X2__VI 0x00000063 -#define SQ_FLAT_ATOMIC_SWAP__VI 0x00000040 -#define SQ_FLAT_ATOMIC_SWAP_X2__VI 0x00000060 -#define SQ_FLAT_ATOMIC_UMAX__VI 0x00000047 -#define SQ_FLAT_ATOMIC_UMAX_X2__VI 0x00000067 -#define SQ_FLAT_ATOMIC_UMIN__VI 0x00000045 -#define SQ_FLAT_ATOMIC_UMIN_X2__VI 0x00000065 -#define SQ_FLAT_ATOMIC_XOR__VI 0x0000004a -#define SQ_FLAT_ATOMIC_XOR_X2__VI 0x0000006a -#define SQ_FLAT_LOAD_DWORD__VI 0x00000014 -#define SQ_FLAT_LOAD_DWORDX2__VI 0x00000015 -#define SQ_FLAT_LOAD_DWORDX3__VI 0x00000016 -#define SQ_FLAT_LOAD_DWORDX4__VI 0x00000017 -#define SQ_FLAT_LOAD_SBYTE__VI 0x00000011 -#define SQ_FLAT_LOAD_SSHORT__VI 0x00000013 -#define SQ_FLAT_LOAD_UBYTE__VI 0x00000010 -#define SQ_FLAT_LOAD_USHORT__VI 0x00000012 -#define SQ_FLAT_SCRATCH_HI__VI 0x00000067 -#define SQ_FLAT_SCRATCH_LO__VI 0x00000066 -#define SQ_FLAT_STORE_DWORDX3__VI 0x0000001e -#define SQ_FLAT_STORE_DWORDX4__VI 0x0000001f -#define SQ_HW_REG_IB_DBG1__VI 0x0000000d -#define SQ_IMAGE_ATOMIC_ADD__SI__CI 0x00000011 -#define SQ_IMAGE_ATOMIC_ADD__VI 0x00000012 -#define SQ_IMAGE_ATOMIC_CMPSWAP__SI__CI 0x00000010 -#define SQ_IMAGE_ATOMIC_CMPSWAP__VI 0x00000011 -#define SQ_IMAGE_ATOMIC_SUB__SI__CI 0x00000012 -#define SQ_IMAGE_ATOMIC_SUB__VI 0x00000013 -#define SQ_IMAGE_ATOMIC_SWAP__SI__CI 0x0000000f -#define SQ_IMAGE_ATOMIC_SWAP__VI 0x00000010 -#define SQ_L1__VI 0x00000001 -#define SQ_L10__VI 0x0000000a -#define SQ_L11__VI 0x0000000b -#define SQ_L12__VI 0x0000000c -#define SQ_L13__VI 0x0000000d -#define SQ_L14__VI 0x0000000e -#define SQ_L15__VI 0x0000000f -#define SQ_L2__VI 0x00000002 -#define SQ_L3__VI 0x00000003 -#define SQ_L4__VI 0x00000004 -#define SQ_L5__VI 0x00000005 -#define SQ_L6__VI 0x00000006 -#define SQ_L7__VI 0x00000007 -#define SQ_L8__VI 0x00000008 -#define SQ_L9__VI 0x00000009 -#define SQ_MSG_SAVEWAVE__VI 0x00000004 -#define SQ_NUM_SGPR__SI__CI 0x00000068 -#define SQ_NUM_SGPR__VI 0x00000066 -#define SQ_R1__VI 0x00000001 -#define SQ_R10__VI 0x0000000a -#define SQ_R11__VI 0x0000000b -#define SQ_R12__VI 0x0000000c -#define SQ_R13__VI 0x0000000d -#define SQ_R14__VI 0x0000000e -#define SQ_R15__VI 0x0000000f -#define SQ_R2__VI 0x00000002 -#define SQ_R3__VI 0x00000003 -#define SQ_R4__VI 0x00000004 -#define SQ_R5__VI 0x00000005 -#define SQ_R6__VI 0x00000006 -#define SQ_R7__VI 0x00000007 -#define SQ_R8__VI 0x00000008 -#define SQ_R9__VI 0x00000009 -#define SQ_SDWA_BYTE_0__VI 0x00000000 -#define SQ_SDWA_BYTE_1__VI 0x00000001 -#define SQ_SDWA_BYTE_2__VI 0x00000002 -#define SQ_SDWA_BYTE_3__VI 0x00000003 -#define SQ_SDWA_DWORD__VI 0x00000006 -#define SQ_SDWA_UNUSED_PAD__VI 0x00000000 -#define SQ_SDWA_UNUSED_PRESERVE__VI 0x00000002 -#define SQ_SDWA_UNUSED_SEXT__VI 0x00000001 -#define SQ_SDWA_WORD_0__VI 0x00000004 -#define SQ_SDWA_WORD_1__VI 0x00000005 -#define SQ_SRC_DPP__VI 0x000000fa -#define SQ_SRC_INV_2PI__VI 0x000000f8 -#define SQ_SRC_SDWA__VI 0x000000f9 -#define SQ_S_ABSDIFF_I32__SI__CI 0x0000002c -#define SQ_S_ABSDIFF_I32__VI 0x0000002a -#define SQ_S_ABS_I32__SI__CI 0x00000034 -#define SQ_S_ABS_I32__VI 0x00000030 -#define SQ_S_ADDK_I32__SI__CI 0x0000000f -#define SQ_S_ADDK_I32__VI 0x0000000e -#define SQ_S_ANDN2_B32__SI__CI 0x00000014 -#define SQ_S_ANDN2_B32__VI 0x00000012 -#define SQ_S_ANDN2_B64__SI__CI 0x00000015 -#define SQ_S_ANDN2_B64__VI 0x00000013 -#define SQ_S_ANDN2_SAVEEXEC_B64__SI__CI 0x00000027 -#define SQ_S_ANDN2_SAVEEXEC_B64__VI 0x00000023 -#define SQ_S_AND_B32__SI__CI 0x0000000e -#define SQ_S_AND_B32__VI 0x0000000c -#define SQ_S_AND_B64__SI__CI 0x0000000f -#define SQ_S_AND_B64__VI 0x0000000d -#define SQ_S_AND_SAVEEXEC_B64__SI__CI 0x00000024 -#define SQ_S_AND_SAVEEXEC_B64__VI 0x00000020 -#define SQ_S_ASHR_I32__SI__CI 0x00000022 -#define SQ_S_ASHR_I32__VI 0x00000020 -#define SQ_S_ASHR_I64__SI__CI 0x00000023 -#define SQ_S_ASHR_I64__VI 0x00000021 -#define SQ_S_ATC_PROBE__VI 0x00000026 -#define SQ_S_ATC_PROBE_BUFFER__VI 0x00000027 -#define SQ_S_BCNT0_I32_B32__SI__CI 0x0000000d -#define SQ_S_BCNT0_I32_B32__VI 0x0000000a -#define SQ_S_BCNT0_I32_B64__SI__CI 0x0000000e -#define SQ_S_BCNT0_I32_B64__VI 0x0000000b -#define SQ_S_BCNT1_I32_B32__SI__CI 0x0000000f -#define SQ_S_BCNT1_I32_B32__VI 0x0000000c -#define SQ_S_BCNT1_I32_B64__SI__CI 0x00000010 -#define SQ_S_BCNT1_I32_B64__VI 0x0000000d -#define SQ_S_BFE_I32__SI__CI 0x00000028 -#define SQ_S_BFE_I32__VI 0x00000026 -#define SQ_S_BFE_I64__SI__CI 0x0000002a -#define SQ_S_BFE_I64__VI 0x00000028 -#define SQ_S_BFE_U32__SI__CI 0x00000027 -#define SQ_S_BFE_U32__VI 0x00000025 -#define SQ_S_BFE_U64__SI__CI 0x00000029 -#define SQ_S_BFE_U64__VI 0x00000027 -#define SQ_S_BFM_B32__SI__CI 0x00000024 -#define SQ_S_BFM_B32__VI 0x00000022 -#define SQ_S_BFM_B64__SI__CI 0x00000025 -#define SQ_S_BFM_B64__VI 0x00000023 -#define SQ_S_BITSET0_B32__SI__CI 0x0000001b -#define SQ_S_BITSET0_B32__VI 0x00000018 -#define SQ_S_BITSET0_B64__SI__CI 0x0000001c -#define SQ_S_BITSET0_B64__VI 0x00000019 -#define SQ_S_BITSET1_B32__SI__CI 0x0000001d -#define SQ_S_BITSET1_B32__VI 0x0000001a -#define SQ_S_BITSET1_B64__SI__CI 0x0000001e -#define SQ_S_BITSET1_B64__VI 0x0000001b -#define SQ_S_BREV_B32__SI__CI 0x0000000b -#define SQ_S_BREV_B32__VI 0x00000008 -#define SQ_S_BREV_B64__SI__CI 0x0000000c -#define SQ_S_BREV_B64__VI 0x00000009 -#define SQ_S_BUFFER_ATOMIC_ADD__VI 0x00000042 -#define SQ_S_BUFFER_ATOMIC_ADD_X2__VI 0x00000062 -#define SQ_S_BUFFER_ATOMIC_AND__VI 0x00000048 -#define SQ_S_BUFFER_ATOMIC_AND_X2__VI 0x00000068 -#define SQ_S_BUFFER_ATOMIC_CMPSWAP__VI 0x00000041 -#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2__VI 0x00000061 -#define SQ_S_BUFFER_ATOMIC_DEC__VI 0x0000004c -#define SQ_S_BUFFER_ATOMIC_DEC_X2__VI 0x0000006c -#define SQ_S_BUFFER_ATOMIC_INC__VI 0x0000004b -#define SQ_S_BUFFER_ATOMIC_INC_X2__VI 0x0000006b -#define SQ_S_BUFFER_ATOMIC_OR__VI 0x00000049 -#define SQ_S_BUFFER_ATOMIC_OR_X2__VI 0x00000069 -#define SQ_S_BUFFER_ATOMIC_SMAX__VI 0x00000046 -#define SQ_S_BUFFER_ATOMIC_SMAX_X2__VI 0x00000066 -#define SQ_S_BUFFER_ATOMIC_SMIN__VI 0x00000044 -#define SQ_S_BUFFER_ATOMIC_SMIN_X2__VI 0x00000064 -#define SQ_S_BUFFER_ATOMIC_SUB__VI 0x00000043 -#define SQ_S_BUFFER_ATOMIC_SUB_X2__VI 0x00000063 -#define SQ_S_BUFFER_ATOMIC_SWAP__VI 0x00000040 -#define SQ_S_BUFFER_ATOMIC_SWAP_X2__VI 0x00000060 -#define SQ_S_BUFFER_ATOMIC_UMAX__VI 0x00000047 -#define SQ_S_BUFFER_ATOMIC_UMAX_X2__VI 0x00000067 -#define SQ_S_BUFFER_ATOMIC_UMIN__VI 0x00000045 -#define SQ_S_BUFFER_ATOMIC_UMIN_X2__VI 0x00000065 -#define SQ_S_BUFFER_ATOMIC_XOR__VI 0x0000004a -#define SQ_S_BUFFER_ATOMIC_XOR_X2__VI 0x0000006a -#define SQ_S_BUFFER_STORE_DWORD__VI 0x00000018 -#define SQ_S_BUFFER_STORE_DWORDX2__VI 0x00000019 -#define SQ_S_BUFFER_STORE_DWORDX4__VI 0x0000001a -#define SQ_S_CBRANCH_G_FORK__SI__CI 0x0000002b -#define SQ_S_CBRANCH_G_FORK__VI 0x00000029 -#define SQ_S_CBRANCH_I_FORK__SI__CI 0x00000011 -#define SQ_S_CBRANCH_I_FORK__VI 0x00000010 -#define SQ_S_CBRANCH_JOIN__SI__CI 0x00000032 -#define SQ_S_CBRANCH_JOIN__VI 0x0000002e -#define SQ_S_CMOVK_I32__SI__CI 0x00000002 -#define SQ_S_CMOVK_I32__VI 0x00000001 -#define SQ_S_CMOV_B32__SI__CI 0x00000005 -#define SQ_S_CMOV_B32__VI 0x00000002 -#define SQ_S_CMOV_B64__SI__CI 0x00000006 -#define SQ_S_CMOV_B64__VI 0x00000003 -#define SQ_S_CMPK_EQ_I32__SI__CI 0x00000003 -#define SQ_S_CMPK_EQ_I32__VI 0x00000002 -#define SQ_S_CMPK_EQ_U32__SI__CI 0x00000009 -#define SQ_S_CMPK_EQ_U32__VI 0x00000008 -#define SQ_S_CMPK_GE_I32__SI__CI 0x00000006 -#define SQ_S_CMPK_GE_I32__VI 0x00000005 -#define SQ_S_CMPK_GE_U32__SI__CI 0x0000000c -#define SQ_S_CMPK_GE_U32__VI 0x0000000b -#define SQ_S_CMPK_GT_I32__SI__CI 0x00000005 -#define SQ_S_CMPK_GT_I32__VI 0x00000004 -#define SQ_S_CMPK_GT_U32__SI__CI 0x0000000b -#define SQ_S_CMPK_GT_U32__VI 0x0000000a -#define SQ_S_CMPK_LE_I32__SI__CI 0x00000008 -#define SQ_S_CMPK_LE_I32__VI 0x00000007 -#define SQ_S_CMPK_LE_U32__SI__CI 0x0000000e -#define SQ_S_CMPK_LE_U32__VI 0x0000000d -#define SQ_S_CMPK_LG_I32__SI__CI 0x00000004 -#define SQ_S_CMPK_LG_I32__VI 0x00000003 -#define SQ_S_CMPK_LG_U32__SI__CI 0x0000000a -#define SQ_S_CMPK_LG_U32__VI 0x00000009 -#define SQ_S_CMPK_LT_I32__SI__CI 0x00000007 -#define SQ_S_CMPK_LT_I32__VI 0x00000006 -#define SQ_S_CMPK_LT_U32__SI__CI 0x0000000d -#define SQ_S_CMPK_LT_U32__VI 0x0000000c -#define SQ_S_CMP_EQ_U64__VI 0x00000012 -#define SQ_S_CMP_LG_U64__VI 0x00000013 -#define SQ_S_DCACHE_INV__SI__CI 0x0000001f -#define SQ_S_DCACHE_INV__VI 0x00000020 -#define SQ_S_DCACHE_INV_VOL__VI 0x00000022 -#define SQ_S_DCACHE_WB__VI 0x00000021 -#define SQ_S_DCACHE_WB_VOL__VI 0x00000023 -#define SQ_S_ENDPGM_SAVED__VI 0x0000001b -#define SQ_S_FF0_I32_B32__SI__CI 0x00000011 -#define SQ_S_FF0_I32_B32__VI 0x0000000e -#define SQ_S_FF0_I32_B64__SI__CI 0x00000012 -#define SQ_S_FF0_I32_B64__VI 0x0000000f -#define SQ_S_FF1_I32_B32__SI__CI 0x00000013 -#define SQ_S_FF1_I32_B32__VI 0x00000010 -#define SQ_S_FF1_I32_B64__SI__CI 0x00000014 -#define SQ_S_FF1_I32_B64__VI 0x00000011 -#define SQ_S_FLBIT_I32__SI__CI 0x00000017 -#define SQ_S_FLBIT_I32__VI 0x00000014 -#define SQ_S_FLBIT_I32_B32__SI__CI 0x00000015 -#define SQ_S_FLBIT_I32_B32__VI 0x00000012 -#define SQ_S_FLBIT_I32_B64__SI__CI 0x00000016 -#define SQ_S_FLBIT_I32_B64__VI 0x00000013 -#define SQ_S_FLBIT_I32_I64__SI__CI 0x00000018 -#define SQ_S_FLBIT_I32_I64__VI 0x00000015 -#define SQ_S_GETPC_B64__SI__CI 0x0000001f -#define SQ_S_GETPC_B64__VI 0x0000001c -#define SQ_S_GETREG_B32__SI__CI 0x00000012 -#define SQ_S_GETREG_B32__VI 0x00000011 -#define SQ_S_GETREG_REGRD_B32__SI__CI 0x00000014 -#define SQ_S_GETREG_REGRD_B32__VI 0x00000013 -#define SQ_S_LSHL_B32__SI__CI 0x0000001e -#define SQ_S_LSHL_B32__VI 0x0000001c -#define SQ_S_LSHL_B64__SI__CI 0x0000001f -#define SQ_S_LSHL_B64__VI 0x0000001d -#define SQ_S_LSHR_B32__SI__CI 0x00000020 -#define SQ_S_LSHR_B32__VI 0x0000001e -#define SQ_S_LSHR_B64__SI__CI 0x00000021 -#define SQ_S_LSHR_B64__VI 0x0000001f -#define SQ_S_MEMREALTIME__VI 0x00000025 -#define SQ_S_MEMTIME__SI__CI 0x0000001e -#define SQ_S_MEMTIME__VI 0x00000024 -#define SQ_S_MOVRELD_B32__SI__CI 0x00000030 -#define SQ_S_MOVRELD_B32__VI 0x0000002c -#define SQ_S_MOVRELD_B64__SI__CI 0x00000031 -#define SQ_S_MOVRELD_B64__VI 0x0000002d -#define SQ_S_MOVRELS_B32__SI__CI 0x0000002e -#define SQ_S_MOVRELS_B32__VI 0x0000002a -#define SQ_S_MOVRELS_B64__SI__CI 0x0000002f -#define SQ_S_MOVRELS_B64__VI 0x0000002b -#define SQ_S_MOV_B32__SI__CI 0x00000003 -#define SQ_S_MOV_B32__VI 0x00000000 -#define SQ_S_MOV_B64__SI__CI 0x00000004 -#define SQ_S_MOV_B64__VI 0x00000001 -#define SQ_S_MOV_FED_B32__SI__CI 0x00000035 -#define SQ_S_MOV_FED_B32__VI 0x00000031 -#define SQ_S_MOV_REGRD_B32__SI__CI 0x00000033 -#define SQ_S_MOV_REGRD_B32__VI 0x0000002f -#define SQ_S_MULK_I32__SI__CI 0x00000010 -#define SQ_S_MULK_I32__VI 0x0000000f -#define SQ_S_MUL_I32__SI__CI 0x00000026 -#define SQ_S_MUL_I32__VI 0x00000024 -#define SQ_S_NAND_B32__SI__CI 0x00000018 -#define SQ_S_NAND_B32__VI 0x00000016 -#define SQ_S_NAND_B64__SI__CI 0x00000019 -#define SQ_S_NAND_B64__VI 0x00000017 -#define SQ_S_NAND_SAVEEXEC_B64__SI__CI 0x00000029 -#define SQ_S_NAND_SAVEEXEC_B64__VI 0x00000025 -#define SQ_S_NOR_B32__SI__CI 0x0000001a -#define SQ_S_NOR_B32__VI 0x00000018 -#define SQ_S_NOR_B64__SI__CI 0x0000001b -#define SQ_S_NOR_B64__VI 0x00000019 -#define SQ_S_NOR_SAVEEXEC_B64__SI__CI 0x0000002a -#define SQ_S_NOR_SAVEEXEC_B64__VI 0x00000026 -#define SQ_S_NOT_B32__SI__CI 0x00000007 -#define SQ_S_NOT_B32__VI 0x00000004 -#define SQ_S_NOT_B64__SI__CI 0x00000008 -#define SQ_S_NOT_B64__VI 0x00000005 -#define SQ_S_ORN2_B32__SI__CI 0x00000016 -#define SQ_S_ORN2_B32__VI 0x00000014 -#define SQ_S_ORN2_B64__SI__CI 0x00000017 -#define SQ_S_ORN2_B64__VI 0x00000015 -#define SQ_S_ORN2_SAVEEXEC_B64__SI__CI 0x00000028 -#define SQ_S_ORN2_SAVEEXEC_B64__VI 0x00000024 -#define SQ_S_OR_B32__SI__CI 0x00000010 -#define SQ_S_OR_B32__VI 0x0000000e -#define SQ_S_OR_B64__SI__CI 0x00000011 -#define SQ_S_OR_B64__VI 0x0000000f -#define SQ_S_OR_SAVEEXEC_B64__SI__CI 0x00000025 -#define SQ_S_OR_SAVEEXEC_B64__VI 0x00000021 -#define SQ_S_QUADMASK_B32__SI__CI 0x0000002c -#define SQ_S_QUADMASK_B32__VI 0x00000028 -#define SQ_S_QUADMASK_B64__SI__CI 0x0000002d -#define SQ_S_QUADMASK_B64__VI 0x00000029 -#define SQ_S_RFE_B64__SI__CI 0x00000022 -#define SQ_S_RFE_B64__VI 0x0000001f -#define SQ_S_RFE_RESTORE_B64__VI 0x0000002b -#define SQ_S_SETPC_B64__SI__CI 0x00000020 -#define SQ_S_SETPC_B64__VI 0x0000001d -#define SQ_S_SETREG_B32__SI__CI 0x00000013 -#define SQ_S_SETREG_B32__VI 0x00000012 -#define SQ_S_SETREG_IMM32_B32__SI__CI 0x00000015 -#define SQ_S_SETREG_IMM32_B32__VI 0x00000014 -#define SQ_S_SET_GPR_IDX_IDX__VI 0x00000032 -#define SQ_S_SET_GPR_IDX_MODE__VI 0x0000001d -#define SQ_S_SET_GPR_IDX_OFF__VI 0x0000001c -#define SQ_S_SET_GPR_IDX_ON__VI 0x00000011 -#define SQ_S_SEXT_I32_I16__SI__CI 0x0000001a -#define SQ_S_SEXT_I32_I16__VI 0x00000017 -#define SQ_S_SEXT_I32_I8__SI__CI 0x00000019 -#define SQ_S_SEXT_I32_I8__VI 0x00000016 -#define SQ_S_STORE_DWORD__VI 0x00000010 -#define SQ_S_STORE_DWORDX2__VI 0x00000011 -#define SQ_S_STORE_DWORDX4__VI 0x00000012 -#define SQ_S_SWAPPC_B64__SI__CI 0x00000021 -#define SQ_S_SWAPPC_B64__VI 0x0000001e -#define SQ_S_WAKEUP__VI 0x00000003 -#define SQ_S_WQM_B32__SI__CI 0x00000009 -#define SQ_S_WQM_B32__VI 0x00000006 -#define SQ_S_WQM_B64__SI__CI 0x0000000a -#define SQ_S_WQM_B64__VI 0x00000007 -#define SQ_S_XNOR_B32__SI__CI 0x0000001c -#define SQ_S_XNOR_B32__VI 0x0000001a -#define SQ_S_XNOR_B64__SI__CI 0x0000001d -#define SQ_S_XNOR_B64__VI 0x0000001b -#define SQ_S_XNOR_SAVEEXEC_B64__SI__CI 0x0000002b -#define SQ_S_XNOR_SAVEEXEC_B64__VI 0x00000027 -#define SQ_S_XOR_B32__SI__CI 0x00000012 -#define SQ_S_XOR_B32__VI 0x00000010 -#define SQ_S_XOR_B64__SI__CI 0x00000013 -#define SQ_S_XOR_B64__VI 0x00000011 -#define SQ_S_XOR_SAVEEXEC_B64__SI__CI 0x00000026 -#define SQ_S_XOR_SAVEEXEC_B64__VI 0x00000022 -#define SQ_TBUFFER_LOAD_FORMAT_D16_X__VI 0x00000008 -#define SQ_TBUFFER_LOAD_FORMAT_D16_XY__VI 0x00000009 -#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ__VI 0x0000000a -#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW__VI 0x0000000b -#define SQ_TBUFFER_STORE_FORMAT_D16_X__VI 0x0000000c -#define SQ_TBUFFER_STORE_FORMAT_D16_XY__VI 0x0000000d -#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ__VI 0x0000000e -#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW__VI 0x0000000f -#define SQ_V_ADDC_U32__SI__CI 0x00000028 -#define SQ_V_ADDC_U32__VI 0x0000001c -#define SQ_V_ADD_F16__VI 0x0000001f -#define SQ_V_ADD_F32__SI__CI 0x00000003 -#define SQ_V_ADD_F32__VI 0x00000001 -#define SQ_V_ADD_F64__SI__CI 0x00000164 -#define SQ_V_ADD_F64__VI 0x00000280 -#define SQ_V_ADD_U16__VI 0x00000026 -#define SQ_V_ADD_U32__VI 0x00000019 -#define SQ_V_ALIGNBIT_B32__SI__CI 0x0000014e -#define SQ_V_ALIGNBIT_B32__VI 0x000001ce -#define SQ_V_ALIGNBYTE_B32__SI__CI 0x0000014f -#define SQ_V_ALIGNBYTE_B32__VI 0x000001cf -#define SQ_V_AND_B32__SI__CI 0x0000001b -#define SQ_V_AND_B32__VI 0x00000013 -#define SQ_V_ASHRREV_I16__VI 0x0000002c -#define SQ_V_ASHRREV_I32__SI__CI 0x00000018 -#define SQ_V_ASHRREV_I32__VI 0x00000011 -#define SQ_V_ASHRREV_I64__VI 0x00000291 -#define SQ_V_BCNT_U32_B32__SI__CI 0x00000022 -#define SQ_V_BCNT_U32_B32__VI 0x0000028b -#define SQ_V_BFE_I32__SI__CI 0x00000149 -#define SQ_V_BFE_I32__VI 0x000001c9 -#define SQ_V_BFE_U32__SI__CI 0x00000148 -#define SQ_V_BFE_U32__VI 0x000001c8 -#define SQ_V_BFI_B32__SI__CI 0x0000014a -#define SQ_V_BFI_B32__VI 0x000001ca -#define SQ_V_BFM_B32__SI__CI 0x0000001e -#define SQ_V_BFM_B32__VI 0x00000293 -#define SQ_V_BFREV_B32__SI__CI 0x00000038 -#define SQ_V_BFREV_B32__VI 0x0000002c -#define SQ_V_CEIL_F16__VI 0x00000045 -#define SQ_V_CEIL_F32__SI__CI 0x00000022 -#define SQ_V_CEIL_F32__VI 0x0000001d -#define SQ_V_CLREXCP__SI__CI 0x00000041 -#define SQ_V_CLREXCP__VI 0x00000035 -#define SQ_V_CMPX_CLASS_F16__VI 0x00000015 -#define SQ_V_CMPX_CLASS_F32__SI__CI 0x00000098 -#define SQ_V_CMPX_CLASS_F32__VI 0x00000011 -#define SQ_V_CMPX_CLASS_F64__SI__CI 0x000000b8 -#define SQ_V_CMPX_CLASS_F64__VI 0x00000013 -#define SQ_V_CMPX_EQ_F16__VI 0x00000032 -#define SQ_V_CMPX_EQ_F32__SI__CI 0x00000012 -#define SQ_V_CMPX_EQ_F32__VI 0x00000052 -#define SQ_V_CMPX_EQ_F64__SI__CI 0x00000032 -#define SQ_V_CMPX_EQ_F64__VI 0x00000072 -#define SQ_V_CMPX_EQ_I16__VI 0x000000b2 -#define SQ_V_CMPX_EQ_I32__SI__CI 0x00000092 -#define SQ_V_CMPX_EQ_I32__VI 0x000000d2 -#define SQ_V_CMPX_EQ_I64__SI__CI 0x000000b2 -#define SQ_V_CMPX_EQ_I64__VI 0x000000f2 -#define SQ_V_CMPX_EQ_U16__VI 0x000000ba -#define SQ_V_CMPX_EQ_U32__SI__CI 0x000000d2 -#define SQ_V_CMPX_EQ_U32__VI 0x000000da -#define SQ_V_CMPX_EQ_U64__SI__CI 0x000000f2 -#define SQ_V_CMPX_EQ_U64__VI 0x000000fa -#define SQ_V_CMPX_F_F16__VI 0x00000030 -#define SQ_V_CMPX_F_F32__SI__CI 0x00000010 -#define SQ_V_CMPX_F_F32__VI 0x00000050 -#define SQ_V_CMPX_F_F64__SI__CI 0x00000030 -#define SQ_V_CMPX_F_F64__VI 0x00000070 -#define SQ_V_CMPX_F_I16__VI 0x000000b0 -#define SQ_V_CMPX_F_I32__SI__CI 0x00000090 -#define SQ_V_CMPX_F_I32__VI 0x000000d0 -#define SQ_V_CMPX_F_I64__SI__CI 0x000000b0 -#define SQ_V_CMPX_F_I64__VI 0x000000f0 -#define SQ_V_CMPX_F_U16__VI 0x000000b8 -#define SQ_V_CMPX_F_U32__SI__CI 0x000000d0 -#define SQ_V_CMPX_F_U32__VI 0x000000d8 -#define SQ_V_CMPX_F_U64__SI__CI 0x000000f0 -#define SQ_V_CMPX_F_U64__VI 0x000000f8 -#define SQ_V_CMPX_GE_F16__VI 0x00000036 -#define SQ_V_CMPX_GE_F32__SI__CI 0x00000016 -#define SQ_V_CMPX_GE_F32__VI 0x00000056 -#define SQ_V_CMPX_GE_F64__SI__CI 0x00000036 -#define SQ_V_CMPX_GE_F64__VI 0x00000076 -#define SQ_V_CMPX_GE_I16__VI 0x000000b6 -#define SQ_V_CMPX_GE_I32__SI__CI 0x00000096 -#define SQ_V_CMPX_GE_I32__VI 0x000000d6 -#define SQ_V_CMPX_GE_I64__SI__CI 0x000000b6 -#define SQ_V_CMPX_GE_I64__VI 0x000000f6 -#define SQ_V_CMPX_GE_U16__VI 0x000000be -#define SQ_V_CMPX_GE_U32__SI__CI 0x000000d6 -#define SQ_V_CMPX_GE_U32__VI 0x000000de -#define SQ_V_CMPX_GE_U64__SI__CI 0x000000f6 -#define SQ_V_CMPX_GE_U64__VI 0x000000fe -#define SQ_V_CMPX_GT_F16__VI 0x00000034 -#define SQ_V_CMPX_GT_F32__SI__CI 0x00000014 -#define SQ_V_CMPX_GT_F32__VI 0x00000054 -#define SQ_V_CMPX_GT_F64__SI__CI 0x00000034 -#define SQ_V_CMPX_GT_F64__VI 0x00000074 -#define SQ_V_CMPX_GT_I16__VI 0x000000b4 -#define SQ_V_CMPX_GT_I32__SI__CI 0x00000094 -#define SQ_V_CMPX_GT_I32__VI 0x000000d4 -#define SQ_V_CMPX_GT_I64__SI__CI 0x000000b4 -#define SQ_V_CMPX_GT_I64__VI 0x000000f4 -#define SQ_V_CMPX_GT_U16__VI 0x000000bc -#define SQ_V_CMPX_GT_U32__SI__CI 0x000000d4 -#define SQ_V_CMPX_GT_U32__VI 0x000000dc -#define SQ_V_CMPX_GT_U64__SI__CI 0x000000f4 -#define SQ_V_CMPX_GT_U64__VI 0x000000fc -#define SQ_V_CMPX_LE_F16__VI 0x00000033 -#define SQ_V_CMPX_LE_F32__SI__CI 0x00000013 -#define SQ_V_CMPX_LE_F32__VI 0x00000053 -#define SQ_V_CMPX_LE_F64__SI__CI 0x00000033 -#define SQ_V_CMPX_LE_F64__VI 0x00000073 -#define SQ_V_CMPX_LE_I16__VI 0x000000b3 -#define SQ_V_CMPX_LE_I32__SI__CI 0x00000093 -#define SQ_V_CMPX_LE_I32__VI 0x000000d3 -#define SQ_V_CMPX_LE_I64__SI__CI 0x000000b3 -#define SQ_V_CMPX_LE_I64__VI 0x000000f3 -#define SQ_V_CMPX_LE_U16__VI 0x000000bb -#define SQ_V_CMPX_LE_U32__SI__CI 0x000000d3 -#define SQ_V_CMPX_LE_U32__VI 0x000000db -#define SQ_V_CMPX_LE_U64__SI__CI 0x000000f3 -#define SQ_V_CMPX_LE_U64__VI 0x000000fb -#define SQ_V_CMPX_LG_F16__VI 0x00000035 -#define SQ_V_CMPX_LG_F32__SI__CI 0x00000015 -#define SQ_V_CMPX_LG_F32__VI 0x00000055 -#define SQ_V_CMPX_LG_F64__SI__CI 0x00000035 -#define SQ_V_CMPX_LG_F64__VI 0x00000075 -#define SQ_V_CMPX_LT_F16__VI 0x00000031 -#define SQ_V_CMPX_LT_F32__SI__CI 0x00000011 -#define SQ_V_CMPX_LT_F32__VI 0x00000051 -#define SQ_V_CMPX_LT_F64__SI__CI 0x00000031 -#define SQ_V_CMPX_LT_F64__VI 0x00000071 -#define SQ_V_CMPX_LT_I16__VI 0x000000b1 -#define SQ_V_CMPX_LT_I32__SI__CI 0x00000091 -#define SQ_V_CMPX_LT_I32__VI 0x000000d1 -#define SQ_V_CMPX_LT_I64__SI__CI 0x000000b1 -#define SQ_V_CMPX_LT_I64__VI 0x000000f1 -#define SQ_V_CMPX_LT_U16__VI 0x000000b9 -#define SQ_V_CMPX_LT_U32__SI__CI 0x000000d1 -#define SQ_V_CMPX_LT_U32__VI 0x000000d9 -#define SQ_V_CMPX_LT_U64__SI__CI 0x000000f1 -#define SQ_V_CMPX_LT_U64__VI 0x000000f9 -#define SQ_V_CMPX_NEQ_F16__VI 0x0000003d -#define SQ_V_CMPX_NEQ_F32__SI__CI 0x0000001d -#define SQ_V_CMPX_NEQ_F32__VI 0x0000005d -#define SQ_V_CMPX_NEQ_F64__SI__CI 0x0000003d -#define SQ_V_CMPX_NEQ_F64__VI 0x0000007d -#define SQ_V_CMPX_NE_I16__VI 0x000000b5 -#define SQ_V_CMPX_NE_I32__SI__CI 0x00000095 -#define SQ_V_CMPX_NE_I32__VI 0x000000d5 -#define SQ_V_CMPX_NE_I64__SI__CI 0x000000b5 -#define SQ_V_CMPX_NE_I64__VI 0x000000f5 -#define SQ_V_CMPX_NE_U16__VI 0x000000bd -#define SQ_V_CMPX_NE_U32__SI__CI 0x000000d5 -#define SQ_V_CMPX_NE_U32__VI 0x000000dd -#define SQ_V_CMPX_NE_U64__SI__CI 0x000000f5 -#define SQ_V_CMPX_NE_U64__VI 0x000000fd -#define SQ_V_CMPX_NGE_F16__VI 0x00000039 -#define SQ_V_CMPX_NGE_F32__SI__CI 0x00000019 -#define SQ_V_CMPX_NGE_F32__VI 0x00000059 -#define SQ_V_CMPX_NGE_F64__SI__CI 0x00000039 -#define SQ_V_CMPX_NGE_F64__VI 0x00000079 -#define SQ_V_CMPX_NGT_F16__VI 0x0000003b -#define SQ_V_CMPX_NGT_F32__SI__CI 0x0000001b -#define SQ_V_CMPX_NGT_F32__VI 0x0000005b -#define SQ_V_CMPX_NGT_F64__SI__CI 0x0000003b -#define SQ_V_CMPX_NGT_F64__VI 0x0000007b -#define SQ_V_CMPX_NLE_F16__VI 0x0000003c -#define SQ_V_CMPX_NLE_F32__SI__CI 0x0000001c -#define SQ_V_CMPX_NLE_F32__VI 0x0000005c -#define SQ_V_CMPX_NLE_F64__SI__CI 0x0000003c -#define SQ_V_CMPX_NLE_F64__VI 0x0000007c -#define SQ_V_CMPX_NLG_F16__VI 0x0000003a -#define SQ_V_CMPX_NLG_F32__SI__CI 0x0000001a -#define SQ_V_CMPX_NLG_F32__VI 0x0000005a -#define SQ_V_CMPX_NLG_F64__SI__CI 0x0000003a -#define SQ_V_CMPX_NLG_F64__VI 0x0000007a -#define SQ_V_CMPX_NLT_F16__VI 0x0000003e -#define SQ_V_CMPX_NLT_F32__SI__CI 0x0000001e -#define SQ_V_CMPX_NLT_F32__VI 0x0000005e -#define SQ_V_CMPX_NLT_F64__SI__CI 0x0000003e -#define SQ_V_CMPX_NLT_F64__VI 0x0000007e -#define SQ_V_CMPX_O_F16__VI 0x00000037 -#define SQ_V_CMPX_O_F32__SI__CI 0x00000017 -#define SQ_V_CMPX_O_F32__VI 0x00000057 -#define SQ_V_CMPX_O_F64__SI__CI 0x00000037 -#define SQ_V_CMPX_O_F64__VI 0x00000077 -#define SQ_V_CMPX_TRU_F16__VI 0x0000003f -#define SQ_V_CMPX_TRU_F32__SI__CI 0x0000001f -#define SQ_V_CMPX_TRU_F32__VI 0x0000005f -#define SQ_V_CMPX_TRU_F64__SI__CI 0x0000003f -#define SQ_V_CMPX_TRU_F64__VI 0x0000007f -#define SQ_V_CMPX_T_I16__VI 0x000000b7 -#define SQ_V_CMPX_T_I32__SI__CI 0x00000097 -#define SQ_V_CMPX_T_I32__VI 0x000000d7 -#define SQ_V_CMPX_T_I64__SI__CI 0x000000b7 -#define SQ_V_CMPX_T_I64__VI 0x000000f7 -#define SQ_V_CMPX_T_U16__VI 0x000000bf -#define SQ_V_CMPX_T_U32__SI__CI 0x000000d7 -#define SQ_V_CMPX_T_U32__VI 0x000000df -#define SQ_V_CMPX_T_U64__SI__CI 0x000000f7 -#define SQ_V_CMPX_T_U64__VI 0x000000ff -#define SQ_V_CMPX_U_F16__VI 0x00000038 -#define SQ_V_CMPX_U_F32__SI__CI 0x00000018 -#define SQ_V_CMPX_U_F32__VI 0x00000058 -#define SQ_V_CMPX_U_F64__SI__CI 0x00000038 -#define SQ_V_CMPX_U_F64__VI 0x00000078 -#define SQ_V_CMP_CLASS_F16__VI 0x00000014 -#define SQ_V_CMP_CLASS_F32__SI__CI 0x00000088 -#define SQ_V_CMP_CLASS_F32__VI 0x00000010 -#define SQ_V_CMP_CLASS_F64__SI__CI 0x000000a8 -#define SQ_V_CMP_CLASS_F64__VI 0x00000012 -#define SQ_V_CMP_EQ_F16__VI 0x00000022 -#define SQ_V_CMP_EQ_F32__SI__CI 0x00000002 -#define SQ_V_CMP_EQ_F32__VI 0x00000042 -#define SQ_V_CMP_EQ_F64__SI__CI 0x00000022 -#define SQ_V_CMP_EQ_F64__VI 0x00000062 -#define SQ_V_CMP_EQ_I16__VI 0x000000a2 -#define SQ_V_CMP_EQ_I32__SI__CI 0x00000082 -#define SQ_V_CMP_EQ_I32__VI 0x000000c2 -#define SQ_V_CMP_EQ_I64__SI__CI 0x000000a2 -#define SQ_V_CMP_EQ_I64__VI 0x000000e2 -#define SQ_V_CMP_EQ_U16__VI 0x000000aa -#define SQ_V_CMP_EQ_U32__SI__CI 0x000000c2 -#define SQ_V_CMP_EQ_U32__VI 0x000000ca -#define SQ_V_CMP_EQ_U64__SI__CI 0x000000e2 -#define SQ_V_CMP_EQ_U64__VI 0x000000ea -#define SQ_V_CMP_F_F16__VI 0x00000020 -#define SQ_V_CMP_F_F32__SI__CI 0x00000000 -#define SQ_V_CMP_F_F32__VI 0x00000040 -#define SQ_V_CMP_F_F64__SI__CI 0x00000020 -#define SQ_V_CMP_F_F64__VI 0x00000060 -#define SQ_V_CMP_F_I16__VI 0x000000a0 -#define SQ_V_CMP_F_I32__SI__CI 0x00000080 -#define SQ_V_CMP_F_I32__VI 0x000000c0 -#define SQ_V_CMP_F_I64__SI__CI 0x000000a0 -#define SQ_V_CMP_F_I64__VI 0x000000e0 -#define SQ_V_CMP_F_U16__VI 0x000000a8 -#define SQ_V_CMP_F_U32__SI__CI 0x000000c0 -#define SQ_V_CMP_F_U32__VI 0x000000c8 -#define SQ_V_CMP_F_U64__SI__CI 0x000000e0 -#define SQ_V_CMP_F_U64__VI 0x000000e8 -#define SQ_V_CMP_GE_F16__VI 0x00000026 -#define SQ_V_CMP_GE_F32__SI__CI 0x00000006 -#define SQ_V_CMP_GE_F32__VI 0x00000046 -#define SQ_V_CMP_GE_F64__SI__CI 0x00000026 -#define SQ_V_CMP_GE_F64__VI 0x00000066 -#define SQ_V_CMP_GE_I16__VI 0x000000a6 -#define SQ_V_CMP_GE_I32__SI__CI 0x00000086 -#define SQ_V_CMP_GE_I32__VI 0x000000c6 -#define SQ_V_CMP_GE_I64__SI__CI 0x000000a6 -#define SQ_V_CMP_GE_I64__VI 0x000000e6 -#define SQ_V_CMP_GE_U16__VI 0x000000ae -#define SQ_V_CMP_GE_U32__SI__CI 0x000000c6 -#define SQ_V_CMP_GE_U32__VI 0x000000ce -#define SQ_V_CMP_GE_U64__SI__CI 0x000000e6 -#define SQ_V_CMP_GE_U64__VI 0x000000ee -#define SQ_V_CMP_GT_F16__VI 0x00000024 -#define SQ_V_CMP_GT_F32__SI__CI 0x00000004 -#define SQ_V_CMP_GT_F32__VI 0x00000044 -#define SQ_V_CMP_GT_F64__SI__CI 0x00000024 -#define SQ_V_CMP_GT_F64__VI 0x00000064 -#define SQ_V_CMP_GT_I16__VI 0x000000a4 -#define SQ_V_CMP_GT_I32__SI__CI 0x00000084 -#define SQ_V_CMP_GT_I32__VI 0x000000c4 -#define SQ_V_CMP_GT_I64__SI__CI 0x000000a4 -#define SQ_V_CMP_GT_I64__VI 0x000000e4 -#define SQ_V_CMP_GT_U16__VI 0x000000ac -#define SQ_V_CMP_GT_U32__SI__CI 0x000000c4 -#define SQ_V_CMP_GT_U32__VI 0x000000cc -#define SQ_V_CMP_GT_U64__SI__CI 0x000000e4 -#define SQ_V_CMP_GT_U64__VI 0x000000ec -#define SQ_V_CMP_LE_F16__VI 0x00000023 -#define SQ_V_CMP_LE_F32__SI__CI 0x00000003 -#define SQ_V_CMP_LE_F32__VI 0x00000043 -#define SQ_V_CMP_LE_F64__SI__CI 0x00000023 -#define SQ_V_CMP_LE_F64__VI 0x00000063 -#define SQ_V_CMP_LE_I16__VI 0x000000a3 -#define SQ_V_CMP_LE_I32__SI__CI 0x00000083 -#define SQ_V_CMP_LE_I32__VI 0x000000c3 -#define SQ_V_CMP_LE_I64__SI__CI 0x000000a3 -#define SQ_V_CMP_LE_I64__VI 0x000000e3 -#define SQ_V_CMP_LE_U16__VI 0x000000ab -#define SQ_V_CMP_LE_U32__SI__CI 0x000000c3 -#define SQ_V_CMP_LE_U32__VI 0x000000cb -#define SQ_V_CMP_LE_U64__SI__CI 0x000000e3 -#define SQ_V_CMP_LE_U64__VI 0x000000eb -#define SQ_V_CMP_LG_F16__VI 0x00000025 -#define SQ_V_CMP_LG_F32__SI__CI 0x00000005 -#define SQ_V_CMP_LG_F32__VI 0x00000045 -#define SQ_V_CMP_LG_F64__SI__CI 0x00000025 -#define SQ_V_CMP_LG_F64__VI 0x00000065 -#define SQ_V_CMP_LT_F16__VI 0x00000021 -#define SQ_V_CMP_LT_F32__SI__CI 0x00000001 -#define SQ_V_CMP_LT_F32__VI 0x00000041 -#define SQ_V_CMP_LT_F64__SI__CI 0x00000021 -#define SQ_V_CMP_LT_F64__VI 0x00000061 -#define SQ_V_CMP_LT_I16__VI 0x000000a1 -#define SQ_V_CMP_LT_I32__SI__CI 0x00000081 -#define SQ_V_CMP_LT_I32__VI 0x000000c1 -#define SQ_V_CMP_LT_I64__SI__CI 0x000000a1 -#define SQ_V_CMP_LT_I64__VI 0x000000e1 -#define SQ_V_CMP_LT_U16__VI 0x000000a9 -#define SQ_V_CMP_LT_U32__SI__CI 0x000000c1 -#define SQ_V_CMP_LT_U32__VI 0x000000c9 -#define SQ_V_CMP_LT_U64__SI__CI 0x000000e1 -#define SQ_V_CMP_LT_U64__VI 0x000000e9 -#define SQ_V_CMP_NEQ_F16__VI 0x0000002d -#define SQ_V_CMP_NEQ_F32__SI__CI 0x0000000d -#define SQ_V_CMP_NEQ_F32__VI 0x0000004d -#define SQ_V_CMP_NEQ_F64__SI__CI 0x0000002d -#define SQ_V_CMP_NEQ_F64__VI 0x0000006d -#define SQ_V_CMP_NE_I16__VI 0x000000a5 -#define SQ_V_CMP_NE_I32__SI__CI 0x00000085 -#define SQ_V_CMP_NE_I32__VI 0x000000c5 -#define SQ_V_CMP_NE_I64__SI__CI 0x000000a5 -#define SQ_V_CMP_NE_I64__VI 0x000000e5 -#define SQ_V_CMP_NE_U16__VI 0x000000ad -#define SQ_V_CMP_NE_U32__SI__CI 0x000000c5 -#define SQ_V_CMP_NE_U32__VI 0x000000cd -#define SQ_V_CMP_NE_U64__SI__CI 0x000000e5 -#define SQ_V_CMP_NE_U64__VI 0x000000ed -#define SQ_V_CMP_NGE_F16__VI 0x00000029 -#define SQ_V_CMP_NGE_F32__SI__CI 0x00000009 -#define SQ_V_CMP_NGE_F32__VI 0x00000049 -#define SQ_V_CMP_NGE_F64__SI__CI 0x00000029 -#define SQ_V_CMP_NGE_F64__VI 0x00000069 -#define SQ_V_CMP_NGT_F16__VI 0x0000002b -#define SQ_V_CMP_NGT_F32__SI__CI 0x0000000b -#define SQ_V_CMP_NGT_F32__VI 0x0000004b -#define SQ_V_CMP_NGT_F64__SI__CI 0x0000002b -#define SQ_V_CMP_NGT_F64__VI 0x0000006b -#define SQ_V_CMP_NLE_F16__VI 0x0000002c -#define SQ_V_CMP_NLE_F32__SI__CI 0x0000000c -#define SQ_V_CMP_NLE_F32__VI 0x0000004c -#define SQ_V_CMP_NLE_F64__SI__CI 0x0000002c -#define SQ_V_CMP_NLE_F64__VI 0x0000006c -#define SQ_V_CMP_NLG_F16__VI 0x0000002a -#define SQ_V_CMP_NLG_F32__SI__CI 0x0000000a -#define SQ_V_CMP_NLG_F32__VI 0x0000004a -#define SQ_V_CMP_NLG_F64__SI__CI 0x0000002a -#define SQ_V_CMP_NLG_F64__VI 0x0000006a -#define SQ_V_CMP_NLT_F16__VI 0x0000002e -#define SQ_V_CMP_NLT_F32__SI__CI 0x0000000e -#define SQ_V_CMP_NLT_F32__VI 0x0000004e -#define SQ_V_CMP_NLT_F64__SI__CI 0x0000002e -#define SQ_V_CMP_NLT_F64__VI 0x0000006e -#define SQ_V_CMP_O_F16__VI 0x00000027 -#define SQ_V_CMP_O_F32__SI__CI 0x00000007 -#define SQ_V_CMP_O_F32__VI 0x00000047 -#define SQ_V_CMP_O_F64__SI__CI 0x00000027 -#define SQ_V_CMP_O_F64__VI 0x00000067 -#define SQ_V_CMP_TRU_F16__VI 0x0000002f -#define SQ_V_CMP_TRU_F32__SI__CI 0x0000000f -#define SQ_V_CMP_TRU_F32__VI 0x0000004f -#define SQ_V_CMP_TRU_F64__SI__CI 0x0000002f -#define SQ_V_CMP_TRU_F64__VI 0x0000006f -#define SQ_V_CMP_T_I16__VI 0x000000a7 -#define SQ_V_CMP_T_I32__SI__CI 0x00000087 -#define SQ_V_CMP_T_I32__VI 0x000000c7 -#define SQ_V_CMP_T_I64__SI__CI 0x000000a7 -#define SQ_V_CMP_T_I64__VI 0x000000e7 -#define SQ_V_CMP_T_U16__VI 0x000000af -#define SQ_V_CMP_T_U32__SI__CI 0x000000c7 -#define SQ_V_CMP_T_U32__VI 0x000000cf -#define SQ_V_CMP_T_U64__SI__CI 0x000000e7 -#define SQ_V_CMP_T_U64__VI 0x000000ef -#define SQ_V_CMP_U_F16__VI 0x00000028 -#define SQ_V_CMP_U_F32__SI__CI 0x00000008 -#define SQ_V_CMP_U_F32__VI 0x00000048 -#define SQ_V_CMP_U_F64__SI__CI 0x00000028 -#define SQ_V_CMP_U_F64__VI 0x00000068 -#define SQ_V_COS_F16__VI 0x0000004a -#define SQ_V_COS_F32__SI__CI 0x00000036 -#define SQ_V_COS_F32__VI 0x0000002a -#define SQ_V_CUBEID_F32__SI__CI 0x00000144 -#define SQ_V_CUBEID_F32__VI 0x000001c4 -#define SQ_V_CUBEMA_F32__SI__CI 0x00000147 -#define SQ_V_CUBEMA_F32__VI 0x000001c7 -#define SQ_V_CUBESC_F32__SI__CI 0x00000145 -#define SQ_V_CUBESC_F32__VI 0x000001c5 -#define SQ_V_CUBETC_F32__SI__CI 0x00000146 -#define SQ_V_CUBETC_F32__VI 0x000001c6 -#define SQ_V_CVT_F16_I16__VI 0x0000003a -#define SQ_V_CVT_F16_U16__VI 0x00000039 -#define SQ_V_CVT_I16_F16__VI 0x0000003c -#define SQ_V_CVT_NORM_I16_F16__VI 0x0000004d -#define SQ_V_CVT_NORM_U16_F16__VI 0x0000004e -#define SQ_V_CVT_PKACCUM_U8_F32__SI__CI 0x0000002c -#define SQ_V_CVT_PKACCUM_U8_F32__VI 0x000001f0 -#define SQ_V_CVT_PKNORM_I16_F16__VI 0x00000299 -#define SQ_V_CVT_PKNORM_I16_F32__SI__CI 0x0000002d -#define SQ_V_CVT_PKNORM_I16_F32__VI 0x00000294 -#define SQ_V_CVT_PKNORM_U16_F16__VI 0x0000029a -#define SQ_V_CVT_PKNORM_U16_F32__SI__CI 0x0000002e -#define SQ_V_CVT_PKNORM_U16_F32__VI 0x00000295 -#define SQ_V_CVT_PKRTZ_F16_F32__SI__CI 0x0000002f -#define SQ_V_CVT_PKRTZ_F16_F32__VI 0x00000296 -#define SQ_V_CVT_PK_I16_I32__SI__CI 0x00000031 -#define SQ_V_CVT_PK_I16_I32__VI 0x00000298 -#define SQ_V_CVT_PK_U16_U32__SI__CI 0x00000030 -#define SQ_V_CVT_PK_U16_U32__VI 0x00000297 -#define SQ_V_CVT_PK_U8_F32__SI__CI 0x0000015e -#define SQ_V_CVT_PK_U8_F32__VI 0x000001dd -#define SQ_V_CVT_U16_F16__VI 0x0000003b -#define SQ_V_DIV_FIXUP_F16__VI 0x000001ef -#define SQ_V_DIV_FIXUP_F32__SI__CI 0x0000015f -#define SQ_V_DIV_FIXUP_F32__VI 0x000001de -#define SQ_V_DIV_FIXUP_F64__SI__CI 0x00000160 -#define SQ_V_DIV_FIXUP_F64__VI 0x000001df -#define SQ_V_DIV_FMAS_F32__SI__CI 0x0000016f -#define SQ_V_DIV_FMAS_F32__VI 0x000001e2 -#define SQ_V_DIV_FMAS_F64__SI__CI 0x00000170 -#define SQ_V_DIV_FMAS_F64__VI 0x000001e3 -#define SQ_V_DIV_SCALE_F32__SI__CI 0x0000016d -#define SQ_V_DIV_SCALE_F32__VI 0x000001e0 -#define SQ_V_DIV_SCALE_F64__SI__CI 0x0000016e -#define SQ_V_DIV_SCALE_F64__VI 0x000001e1 -#define SQ_V_EXP_F16__VI 0x00000041 -#define SQ_V_EXP_F32__SI__CI 0x00000025 -#define SQ_V_EXP_F32__VI 0x00000020 -#define SQ_V_EXP_LEGACY_F32__VI 0x0000004b -#define SQ_V_FFBH_I32__SI__CI 0x0000003b -#define SQ_V_FFBH_I32__VI 0x0000002f -#define SQ_V_FFBH_U32__SI__CI 0x00000039 -#define SQ_V_FFBH_U32__VI 0x0000002d -#define SQ_V_FFBL_B32__SI__CI 0x0000003a -#define SQ_V_FFBL_B32__VI 0x0000002e -#define SQ_V_FLOOR_F16__VI 0x00000044 -#define SQ_V_FLOOR_F32__SI__CI 0x00000024 -#define SQ_V_FLOOR_F32__VI 0x0000001f -#define SQ_V_FMA_F16__VI 0x000001ee -#define SQ_V_FMA_F32__SI__CI 0x0000014b -#define SQ_V_FMA_F32__VI 0x000001cb -#define SQ_V_FMA_F64__SI__CI 0x0000014c -#define SQ_V_FMA_F64__VI 0x000001cc -#define SQ_V_FRACT_F16__VI 0x00000048 -#define SQ_V_FRACT_F32__SI__CI 0x00000020 -#define SQ_V_FRACT_F32__VI 0x0000001b -#define SQ_V_FRACT_F64__SI__CI 0x0000003e -#define SQ_V_FRACT_F64__VI 0x00000032 -#define SQ_V_FREXP_EXP_I16_F16__VI 0x00000043 -#define SQ_V_FREXP_EXP_I32_F32__SI__CI 0x0000003f -#define SQ_V_FREXP_EXP_I32_F32__VI 0x00000033 -#define SQ_V_FREXP_EXP_I32_F64__SI__CI 0x0000003c -#define SQ_V_FREXP_EXP_I32_F64__VI 0x00000030 -#define SQ_V_FREXP_MANT_F16__VI 0x00000042 -#define SQ_V_FREXP_MANT_F32__SI__CI 0x00000040 -#define SQ_V_FREXP_MANT_F32__VI 0x00000034 -#define SQ_V_FREXP_MANT_F64__SI__CI 0x0000003d -#define SQ_V_FREXP_MANT_F64__VI 0x00000031 -#define SQ_V_INTERP_P1LL_F16__VI 0x00000274 -#define SQ_V_INTERP_P1LV_F16__VI 0x00000275 -#define SQ_V_INTERP_P2_F16__VI 0x00000276 -#define SQ_V_INTRP_COUNT__VI 0x00000004 -#define SQ_V_INTRP_OFFSET__VI 0x00000270 -#define SQ_V_LDEXP_F16__VI 0x00000033 -#define SQ_V_LDEXP_F32__SI__CI 0x0000002b -#define SQ_V_LDEXP_F32__VI 0x00000288 -#define SQ_V_LDEXP_F64__SI__CI 0x00000168 -#define SQ_V_LDEXP_F64__VI 0x00000284 -#define SQ_V_LERP_U8__SI__CI 0x0000014d -#define SQ_V_LERP_U8__VI 0x000001cd -#define SQ_V_LOG_F16__VI 0x00000040 -#define SQ_V_LOG_F32__SI__CI 0x00000027 -#define SQ_V_LOG_F32__VI 0x00000021 -#define SQ_V_LOG_LEGACY_F32__VI 0x0000004c -#define SQ_V_LSHLREV_B16__VI 0x0000002a -#define SQ_V_LSHLREV_B32__SI__CI 0x0000001a -#define SQ_V_LSHLREV_B32__VI 0x00000012 -#define SQ_V_LSHLREV_B64__VI 0x0000028f -#define SQ_V_LSHRREV_B16__VI 0x0000002b -#define SQ_V_LSHRREV_B32__SI__CI 0x00000016 -#define SQ_V_LSHRREV_B32__VI 0x00000010 -#define SQ_V_LSHRREV_B64__VI 0x00000290 -#define SQ_V_MAC_F16__VI 0x00000023 -#define SQ_V_MAC_F32__SI__CI 0x0000001f -#define SQ_V_MAC_F32__VI 0x00000016 -#define SQ_V_MAC_LEGACY_F32__SI__CI 0x00000006 -#define SQ_V_MAC_LEGACY_F32__VI 0x0000028e -#define SQ_V_MADAK_F16__VI 0x00000025 -#define SQ_V_MADAK_F32__SI__CI 0x00000021 -#define SQ_V_MADAK_F32__VI 0x00000018 -#define SQ_V_MADMK_F16__VI 0x00000024 -#define SQ_V_MADMK_F32__SI__CI 0x00000020 -#define SQ_V_MADMK_F32__VI 0x00000017 -#define SQ_V_MAD_F16__VI 0x000001ea -#define SQ_V_MAD_F32__SI__CI 0x00000141 -#define SQ_V_MAD_F32__VI 0x000001c1 -#define SQ_V_MAD_I16__VI 0x000001ec -#define SQ_V_MAD_I32_I24__SI__CI 0x00000142 -#define SQ_V_MAD_I32_I24__VI 0x000001c2 -#define SQ_V_MAD_I64_I32__VI 0x000001e9 -#define SQ_V_MAD_LEGACY_F32__SI__CI 0x00000140 -#define SQ_V_MAD_LEGACY_F32__VI 0x000001c0 -#define SQ_V_MAD_U16__VI 0x000001eb -#define SQ_V_MAD_U32_U24__SI__CI 0x00000143 -#define SQ_V_MAD_U32_U24__VI 0x000001c3 -#define SQ_V_MAD_U64_U32__VI 0x000001e8 -#define SQ_V_MAX3_F32__SI__CI 0x00000154 -#define SQ_V_MAX3_F32__VI 0x000001d3 -#define SQ_V_MAX3_I32__SI__CI 0x00000155 -#define SQ_V_MAX3_I32__VI 0x000001d4 -#define SQ_V_MAX3_U32__SI__CI 0x00000156 -#define SQ_V_MAX3_U32__VI 0x000001d5 -#define SQ_V_MAX_F16__VI 0x0000002d -#define SQ_V_MAX_F32__SI__CI 0x00000010 -#define SQ_V_MAX_F32__VI 0x0000000b -#define SQ_V_MAX_F64__SI__CI 0x00000167 -#define SQ_V_MAX_F64__VI 0x00000283 -#define SQ_V_MAX_I16__VI 0x00000030 -#define SQ_V_MAX_I32__SI__CI 0x00000012 -#define SQ_V_MAX_I32__VI 0x0000000d -#define SQ_V_MAX_U16__VI 0x0000002f -#define SQ_V_MAX_U32__SI__CI 0x00000014 -#define SQ_V_MAX_U32__VI 0x0000000f -#define SQ_V_MBCNT_HI_U32_B32__SI__CI 0x00000024 -#define SQ_V_MBCNT_HI_U32_B32__VI 0x0000028d -#define SQ_V_MBCNT_LO_U32_B32__SI__CI 0x00000023 -#define SQ_V_MBCNT_LO_U32_B32__VI 0x0000028c -#define SQ_V_MED3_F32__SI__CI 0x00000157 -#define SQ_V_MED3_F32__VI 0x000001d6 -#define SQ_V_MED3_I32__SI__CI 0x00000158 -#define SQ_V_MED3_I32__VI 0x000001d7 -#define SQ_V_MED3_U32__SI__CI 0x00000159 -#define SQ_V_MED3_U32__VI 0x000001d8 -#define SQ_V_MIN3_F32__SI__CI 0x00000151 -#define SQ_V_MIN3_F32__VI 0x000001d0 -#define SQ_V_MIN3_I32__SI__CI 0x00000152 -#define SQ_V_MIN3_I32__VI 0x000001d1 -#define SQ_V_MIN3_U32__SI__CI 0x00000153 -#define SQ_V_MIN3_U32__VI 0x000001d2 -#define SQ_V_MIN_F16__VI 0x0000002e -#define SQ_V_MIN_F32__SI__CI 0x0000000f -#define SQ_V_MIN_F32__VI 0x0000000a -#define SQ_V_MIN_F64__SI__CI 0x00000166 -#define SQ_V_MIN_F64__VI 0x00000282 -#define SQ_V_MIN_I16__VI 0x00000032 -#define SQ_V_MIN_I32__SI__CI 0x00000011 -#define SQ_V_MIN_I32__VI 0x0000000c -#define SQ_V_MIN_U16__VI 0x00000031 -#define SQ_V_MIN_U32__SI__CI 0x00000013 -#define SQ_V_MIN_U32__VI 0x0000000e -#define SQ_V_MOVRELD_B32__SI__CI 0x00000042 -#define SQ_V_MOVRELD_B32__VI 0x00000036 -#define SQ_V_MOVRELSD_B32__SI__CI 0x00000044 -#define SQ_V_MOVRELSD_B32__VI 0x00000038 -#define SQ_V_MOVRELS_B32__SI__CI 0x00000043 -#define SQ_V_MOVRELS_B32__VI 0x00000037 -#define SQ_V_MQSAD_PK_U16_U8__VI 0x000001e6 -#define SQ_V_MQSAD_U32_U8__VI 0x000001e7 -#define SQ_V_MSAD_U8__SI__CI 0x00000171 -#define SQ_V_MSAD_U8__VI 0x000001e4 -#define SQ_V_MUL_F16__VI 0x00000022 -#define SQ_V_MUL_F32__SI__CI 0x00000008 -#define SQ_V_MUL_F32__VI 0x00000005 -#define SQ_V_MUL_F64__SI__CI 0x00000165 -#define SQ_V_MUL_F64__VI 0x00000281 -#define SQ_V_MUL_HI_I32__SI__CI 0x0000016c -#define SQ_V_MUL_HI_I32__VI 0x00000287 -#define SQ_V_MUL_HI_I32_I24__SI__CI 0x0000000a -#define SQ_V_MUL_HI_I32_I24__VI 0x00000007 -#define SQ_V_MUL_HI_U32__SI__CI 0x0000016a -#define SQ_V_MUL_HI_U32__VI 0x00000286 -#define SQ_V_MUL_HI_U32_U24__SI__CI 0x0000000c -#define SQ_V_MUL_HI_U32_U24__VI 0x00000009 -#define SQ_V_MUL_I32_I24__SI__CI 0x00000009 -#define SQ_V_MUL_I32_I24__VI 0x00000006 -#define SQ_V_MUL_LEGACY_F32__SI__CI 0x00000007 -#define SQ_V_MUL_LEGACY_F32__VI 0x00000004 -#define SQ_V_MUL_LO_U16__VI 0x00000029 -#define SQ_V_MUL_LO_U32__SI__CI 0x00000169 -#define SQ_V_MUL_LO_U32__VI 0x00000285 -#define SQ_V_MUL_U32_U24__SI__CI 0x0000000b -#define SQ_V_MUL_U32_U24__VI 0x00000008 -#define SQ_V_NOT_B32__SI__CI 0x00000037 -#define SQ_V_NOT_B32__VI 0x0000002b -#define SQ_V_OP1_OFFSET__SI__CI 0x00000180 -#define SQ_V_OP1_OFFSET__VI 0x00000140 -#define SQ_V_OP3_2IN_COUNT__VI 0x00000080 -#define SQ_V_OP3_2IN_OFFSET__VI 0x00000280 -#define SQ_V_OP3_3IN_COUNT__VI 0x000000b0 -#define SQ_V_OP3_3IN_OFFSET__VI 0x000001c0 -#define SQ_V_OP3_INTRP_COUNT__VI 0x0000000c -#define SQ_V_OP3_INTRP_OFFSET__VI 0x00000274 -#define SQ_V_OR_B32__SI__CI 0x0000001c -#define SQ_V_OR_B32__VI 0x00000014 -#define SQ_V_PERM_B32__VI 0x000001ed -#define SQ_V_QSAD_PK_U16_U8__VI 0x000001e5 -#define SQ_V_RCP_F16__VI 0x0000003d -#define SQ_V_RCP_F32__SI__CI 0x0000002a -#define SQ_V_RCP_F32__VI 0x00000022 -#define SQ_V_RCP_F64__SI__CI 0x0000002f -#define SQ_V_RCP_F64__VI 0x00000025 -#define SQ_V_RCP_IFLAG_F32__SI__CI 0x0000002b -#define SQ_V_RCP_IFLAG_F32__VI 0x00000023 -#define SQ_V_READLANE_B32__SI__CI 0x00000001 -#define SQ_V_READLANE_B32__VI 0x00000289 -#define SQ_V_RNDNE_F16__VI 0x00000047 -#define SQ_V_RNDNE_F32__SI__CI 0x00000023 -#define SQ_V_RNDNE_F32__VI 0x0000001e -#define SQ_V_RSQ_F16__VI 0x0000003f -#define SQ_V_RSQ_F32__SI__CI 0x0000002e -#define SQ_V_RSQ_F32__VI 0x00000024 -#define SQ_V_RSQ_F64__SI__CI 0x00000031 -#define SQ_V_RSQ_F64__VI 0x00000026 -#define SQ_V_SAD_HI_U8__SI__CI 0x0000015b -#define SQ_V_SAD_HI_U8__VI 0x000001da -#define SQ_V_SAD_U16__SI__CI 0x0000015c -#define SQ_V_SAD_U16__VI 0x000001db -#define SQ_V_SAD_U32__SI__CI 0x0000015d -#define SQ_V_SAD_U32__VI 0x000001dc -#define SQ_V_SAD_U8__SI__CI 0x0000015a -#define SQ_V_SAD_U8__VI 0x000001d9 -#define SQ_V_SIN_F16__VI 0x00000049 -#define SQ_V_SIN_F32__SI__CI 0x00000035 -#define SQ_V_SIN_F32__VI 0x00000029 -#define SQ_V_SQRT_F16__VI 0x0000003e -#define SQ_V_SQRT_F32__SI__CI 0x00000033 -#define SQ_V_SQRT_F32__VI 0x00000027 -#define SQ_V_SQRT_F64__SI__CI 0x00000034 -#define SQ_V_SQRT_F64__VI 0x00000028 -#define SQ_V_SUBBREV_U32__SI__CI 0x0000002a -#define SQ_V_SUBBREV_U32__VI 0x0000001e -#define SQ_V_SUBB_U32__SI__CI 0x00000029 -#define SQ_V_SUBB_U32__VI 0x0000001d -#define SQ_V_SUBREV_F16__VI 0x00000021 -#define SQ_V_SUBREV_F32__SI__CI 0x00000005 -#define SQ_V_SUBREV_F32__VI 0x00000003 -#define SQ_V_SUBREV_U16__VI 0x00000028 -#define SQ_V_SUBREV_U32__VI 0x0000001b -#define SQ_V_SUB_F16__VI 0x00000020 -#define SQ_V_SUB_F32__SI__CI 0x00000004 -#define SQ_V_SUB_F32__VI 0x00000002 -#define SQ_V_SUB_U16__VI 0x00000027 -#define SQ_V_SUB_U32__VI 0x0000001a -#define SQ_V_TRIG_PREOP_F64__SI__CI 0x00000174 -#define SQ_V_TRIG_PREOP_F64__VI 0x00000292 -#define SQ_V_TRUNC_F16__VI 0x00000046 -#define SQ_V_TRUNC_F32__SI__CI 0x00000021 -#define SQ_V_TRUNC_F32__VI 0x0000001c -#define SQ_V_WRITELANE_B32__SI__CI 0x00000002 -#define SQ_V_WRITELANE_B32__VI 0x0000028a -#define SQ_V_XOR_B32__SI__CI 0x0000001d -#define SQ_V_XOR_B32__VI 0x00000015 -#define SQ_XLATE_VOP3_TO_VINTRP_COUNT__VI 0x00000004 -#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET__VI 0x00000270 -#define SQ_XLATE_VOP3_TO_VOP1_COUNT__VI 0x00000080 -#define SQ_XLATE_VOP3_TO_VOP1_OFFSET__VI 0x00000140 -#define SQ_XLATE_VOP3_TO_VOP2_COUNT__VI 0x00000040 -#define SQ_XLATE_VOP3_TO_VOP2_OFFSET__VI 0x00000100 -#define SQ_XLATE_VOP3_TO_VOPC_COUNT__VI 0x00000100 -#define SQ_XLATE_VOP3_TO_VOPC_OFFSET__VI 0x00000000 -#define SQ_XNACK_MASK_HI__VI 0x00000069 -#define SQ_XNACK_MASK_LO__VI 0x00000068 - -} // inline namespace Chip -} // namespace Gfx6 -} // namespace Pal - -#endif diff --git a/tools/gfx6_chip/si_ci_vi_merged_offset.h b/tools/gfx6_chip/si_ci_vi_merged_offset.h deleted file mode 100644 index 589a58bf..00000000 --- a/tools/gfx6_chip/si_ci_vi_merged_offset.h +++ /dev/null @@ -1,15339 +0,0 @@ -/* - *********************************************************************************************************************** - * - * Copyright (c) 2014-2021 Advanced Micro Devices, Inc. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - **********************************************************************************************************************/ - -#if !defined __SI__CI__VIoffset_HEADER -#define __SI__CI__VIoffset_HEADER - -namespace Pal -{ -namespace Gfx6 -{ -inline namespace Chip -{ - -#define SI_CI_offset_HEADER__SI__CI -constexpr unsigned int cfgADAPTER_ID = 0x000B; -constexpr unsigned int cfgADAPTER_ID_W = 0x0013; -constexpr unsigned int cfgBASE_ADDR_1 = 0x0004; -constexpr unsigned int cfgBASE_ADDR_2 = 0x0005; -constexpr unsigned int cfgBASE_ADDR_3 = 0x0006; -constexpr unsigned int cfgBASE_ADDR_4 = 0x0007; -constexpr unsigned int cfgBASE_ADDR_5 = 0x0008; -constexpr unsigned int cfgBASE_ADDR_6 = 0x0009; -constexpr unsigned int cfgBASE_CLASS = 0x0002; -constexpr unsigned int cfgBIST = 0x0003; -constexpr unsigned int cfgCACHE_LINE = 0x0003; -constexpr unsigned int cfgCAP_PTR = 0x000D; -constexpr unsigned int cfgCOMMAND = 0x0001; -constexpr unsigned int cfgDEVICE_CAP = 0x0017; -constexpr unsigned int cfgDEVICE_CAP2 = 0x001F; -constexpr unsigned int cfgDEVICE_CNTL = 0x0018; -constexpr unsigned int cfgDEVICE_CNTL2 = 0x0020; -constexpr unsigned int cfgDEVICE_ID = 0x0000; -constexpr unsigned int cfgDEVICE_STATUS = 0x0018; -constexpr unsigned int cfgDEVICE_STATUS2 = 0x0020; -constexpr unsigned int cfgHEADER = 0x0003; -constexpr unsigned int cfgINTERRUPT_LINE = 0x000F; -constexpr unsigned int cfgINTERRUPT_PIN = 0x000F; -constexpr unsigned int cfgLATENCY = 0x0003; -constexpr unsigned int cfgLINK_CAP = 0x0019; -constexpr unsigned int cfgLINK_CAP2 = 0x0021; -constexpr unsigned int cfgLINK_CNTL = 0x001A; -constexpr unsigned int cfgLINK_CNTL2 = 0x0022; -constexpr unsigned int cfgLINK_STATUS = 0x001A; -constexpr unsigned int cfgLINK_STATUS2 = 0x0022; -constexpr unsigned int cfgMAX_LATENCY = 0x000F; -constexpr unsigned int cfgMIN_GRANT = 0x000F; -constexpr unsigned int cfgMSI_CAP_LIST = 0x0028; -constexpr unsigned int cfgMSI_MSG_ADDR_HI = 0x002A; -constexpr unsigned int cfgMSI_MSG_ADDR_LO = 0x0029; -constexpr unsigned int cfgMSI_MSG_CNTL = 0x0028; -constexpr unsigned int cfgMSI_MSG_DATA = 0x002A; -constexpr unsigned int cfgMSI_MSG_DATA_64 = 0x002B; -constexpr unsigned int cfgPCIE_ACS_CAP__CI__VI = 0x00A9; -constexpr unsigned int cfgPCIE_ACS_CNTL__CI__VI = 0x00A9; -constexpr unsigned int cfgPCIE_ACS_ENH_CAP_LIST__CI__VI = 0x00A8; -constexpr unsigned int cfgPCIE_ADV_ERR_CAP_CNTL = 0x005A; -constexpr unsigned int cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0054; -constexpr unsigned int cfgPCIE_ATS_CAP__CI__VI = 0x00AD; -constexpr unsigned int cfgPCIE_ATS_CNTL__CI__VI = 0x00AD; -constexpr unsigned int cfgPCIE_ATS_ENH_CAP_LIST__CI__VI = 0x00AC; -constexpr unsigned int cfgPCIE_BAR1_CAP__CI__VI = 0x0081; -constexpr unsigned int cfgPCIE_BAR1_CNTL__CI__VI = 0x0082; -constexpr unsigned int cfgPCIE_BAR2_CAP__CI__VI = 0x0083; -constexpr unsigned int cfgPCIE_BAR2_CNTL__CI__VI = 0x0084; -constexpr unsigned int cfgPCIE_BAR3_CAP__CI__VI = 0x0085; -constexpr unsigned int cfgPCIE_BAR3_CNTL__CI__VI = 0x0086; -constexpr unsigned int cfgPCIE_BAR4_CAP__CI__VI = 0x0087; -constexpr unsigned int cfgPCIE_BAR4_CNTL__CI__VI = 0x0088; -constexpr unsigned int cfgPCIE_BAR5_CAP__CI__VI = 0x0089; -constexpr unsigned int cfgPCIE_BAR5_CNTL__CI__VI = 0x008A; -constexpr unsigned int cfgPCIE_BAR6_CAP__CI__VI = 0x008B; -constexpr unsigned int cfgPCIE_BAR6_CNTL__CI__VI = 0x008C; -constexpr unsigned int cfgPCIE_BAR_ENH_CAP_LIST__CI__VI = 0x0080; -constexpr unsigned int cfgPCIE_CAP = 0x0016; -constexpr unsigned int cfgPCIE_CAP_LIST = 0x0016; -constexpr unsigned int cfgPCIE_CORR_ERR_MASK = 0x0059; -constexpr unsigned int cfgPCIE_CORR_ERR_STATUS = 0x0058; -constexpr unsigned int cfgPCIE_DEV_SERIAL_NUM_DW1 = 0x0051; -constexpr unsigned int cfgPCIE_DEV_SERIAL_NUM_DW2 = 0x0052; -constexpr unsigned int cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x0050; -constexpr unsigned int cfgPCIE_DPA_CAP__CI__VI = 0x0095; -constexpr unsigned int cfgPCIE_DPA_CNTL__CI__VI = 0x0097; -constexpr unsigned int cfgPCIE_DPA_ENH_CAP_LIST__CI__VI = 0x0094; -constexpr unsigned int cfgPCIE_DPA_LATENCY_INDICATOR__CI__VI = 0x0096; -constexpr unsigned int cfgPCIE_DPA_STATUS__CI__VI = 0x0097; -constexpr unsigned int cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI = 0x0098; -constexpr unsigned int cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI = 0x0098; -constexpr unsigned int cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI = 0x0098; -constexpr unsigned int cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI = 0x0098; -constexpr unsigned int cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI = 0x0099; -constexpr unsigned int cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI = 0x0099; -constexpr unsigned int cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI = 0x0099; -constexpr unsigned int cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI = 0x0099; -constexpr unsigned int cfgPCIE_HDR_LOG0 = 0x005B; -constexpr unsigned int cfgPCIE_HDR_LOG1 = 0x005C; -constexpr unsigned int cfgPCIE_HDR_LOG2 = 0x005D; -constexpr unsigned int cfgPCIE_HDR_LOG3 = 0x005E; -constexpr unsigned int cfgPCIE_LANE_0_EQUALIZATION_CNTL__CI__VI = 0x009F; -constexpr unsigned int cfgPCIE_LANE_10_EQUALIZATION_CNTL__CI__VI = 0x00A4; -constexpr unsigned int cfgPCIE_LANE_11_EQUALIZATION_CNTL__CI__VI = 0x00A4; -constexpr unsigned int cfgPCIE_LANE_12_EQUALIZATION_CNTL__CI__VI = 0x00A5; -constexpr unsigned int cfgPCIE_LANE_13_EQUALIZATION_CNTL__CI__VI = 0x00A5; -constexpr unsigned int cfgPCIE_LANE_14_EQUALIZATION_CNTL__CI__VI = 0x00A6; -constexpr unsigned int cfgPCIE_LANE_15_EQUALIZATION_CNTL__CI__VI = 0x00A6; -constexpr unsigned int cfgPCIE_LANE_1_EQUALIZATION_CNTL__CI__VI = 0x009F; -constexpr unsigned int cfgPCIE_LANE_2_EQUALIZATION_CNTL__CI__VI = 0x00A0; -constexpr unsigned int cfgPCIE_LANE_3_EQUALIZATION_CNTL__CI__VI = 0x00A0; -constexpr unsigned int cfgPCIE_LANE_4_EQUALIZATION_CNTL__CI__VI = 0x00A1; -constexpr unsigned int cfgPCIE_LANE_5_EQUALIZATION_CNTL__CI__VI = 0x00A1; -constexpr unsigned int cfgPCIE_LANE_6_EQUALIZATION_CNTL__CI__VI = 0x00A2; -constexpr unsigned int cfgPCIE_LANE_7_EQUALIZATION_CNTL__CI__VI = 0x00A2; -constexpr unsigned int cfgPCIE_LANE_8_EQUALIZATION_CNTL__CI__VI = 0x00A3; -constexpr unsigned int cfgPCIE_LANE_9_EQUALIZATION_CNTL__CI__VI = 0x00A3; -constexpr unsigned int cfgPCIE_LANE_ERROR_STATUS__CI__VI = 0x009E; -constexpr unsigned int cfgPCIE_LINK_CNTL3__CI__VI = 0x009D; -constexpr unsigned int cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI = 0x00B3; -constexpr unsigned int cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI = 0x00B2; -constexpr unsigned int cfgPCIE_PAGE_REQ_CNTL__CI__VI = 0x00B1; -constexpr unsigned int cfgPCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI = 0x00B0; -constexpr unsigned int cfgPCIE_PAGE_REQ_STATUS__CI__VI = 0x00B1; -constexpr unsigned int cfgPCIE_PASID_CAP__CI__VI = 0x00B5; -constexpr unsigned int cfgPCIE_PASID_CNTL__CI__VI = 0x00B5; -constexpr unsigned int cfgPCIE_PASID_ENH_CAP_LIST__CI__VI = 0x00B4; -constexpr unsigned int cfgPCIE_PORT_VC_CAP_REG1 = 0x0045; -constexpr unsigned int cfgPCIE_PORT_VC_CAP_REG2 = 0x0046; -constexpr unsigned int cfgPCIE_PORT_VC_CNTL = 0x0047; -constexpr unsigned int cfgPCIE_PORT_VC_STATUS = 0x0047; -constexpr unsigned int cfgPCIE_PWR_BUDGET_CAP__CI__VI = 0x0093; -constexpr unsigned int cfgPCIE_PWR_BUDGET_DATA_SELECT__CI__VI = 0x0091; -constexpr unsigned int cfgPCIE_PWR_BUDGET_DATA__CI__VI = 0x0092; -constexpr unsigned int cfgPCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI = 0x0090; -constexpr unsigned int cfgPCIE_SECONDARY_ENH_CAP_LIST__CI__VI = 0x009C; -constexpr unsigned int cfgPCIE_TLP_PREFIX_LOG0__CI__VI = 0x0062; -constexpr unsigned int cfgPCIE_TLP_PREFIX_LOG1__CI__VI = 0x0063; -constexpr unsigned int cfgPCIE_TLP_PREFIX_LOG2__CI__VI = 0x0064; -constexpr unsigned int cfgPCIE_TLP_PREFIX_LOG3__CI__VI = 0x0065; -constexpr unsigned int cfgPCIE_UNCORR_ERR_MASK = 0x0056; -constexpr unsigned int cfgPCIE_UNCORR_ERR_SEVERITY = 0x0057; -constexpr unsigned int cfgPCIE_UNCORR_ERR_STATUS = 0x0055; -constexpr unsigned int cfgPCIE_VC0_RESOURCE_CAP = 0x0048; -constexpr unsigned int cfgPCIE_VC0_RESOURCE_CNTL = 0x0049; -constexpr unsigned int cfgPCIE_VC0_RESOURCE_STATUS = 0x004A; -constexpr unsigned int cfgPCIE_VC1_RESOURCE_CAP = 0x004B; -constexpr unsigned int cfgPCIE_VC1_RESOURCE_CNTL = 0x004C; -constexpr unsigned int cfgPCIE_VC1_RESOURCE_STATUS = 0x004D; -constexpr unsigned int cfgPCIE_VC_ENH_CAP_LIST = 0x0044; -constexpr unsigned int cfgPCIE_VENDOR_SPECIFIC1 = 0x0042; -constexpr unsigned int cfgPCIE_VENDOR_SPECIFIC2 = 0x0043; -constexpr unsigned int cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0040; -constexpr unsigned int cfgPCIE_VENDOR_SPECIFIC_HDR = 0x0041; -constexpr unsigned int cfgPMI_CAP = 0x0014; -constexpr unsigned int cfgPMI_CAP_LIST = 0x0014; -constexpr unsigned int cfgPMI_STATUS_CNTL = 0x0015; -constexpr unsigned int cfgPROG_INTERFACE = 0x0002; -constexpr unsigned int cfgREVISION_ID = 0x0002; -constexpr unsigned int cfgROM_BASE_ADDR = 0x000C; -constexpr unsigned int cfgSTATUS = 0x0001; -constexpr unsigned int cfgSUB_CLASS = 0x0002; -constexpr unsigned int cfgVENDOR_CAP_LIST__CI__VI = 0x0012; -constexpr unsigned int cfgVENDOR_ID = 0x0000; -constexpr unsigned int ioATTRDR__SI__VI = 0x00F0; -constexpr unsigned int ioATTRDW__SI__VI = 0x00F0; -constexpr unsigned int ioATTRX__SI__VI = 0x00F0; -constexpr unsigned int ioBIF_RFE_SNOOP_REG__CI__VI = 0x0027; -constexpr unsigned int ioCRTC8_DATA__SI__VI = 0x00ED; -constexpr unsigned int ioCRTC8_IDX__SI__VI = 0x00ED; -constexpr unsigned int ioDAC_DATA__SI__VI = 0x00F2; -constexpr unsigned int ioDAC_MASK__SI__VI = 0x00F1; -constexpr unsigned int ioDAC_R_INDEX__SI__VI = 0x00F1; -constexpr unsigned int ioDAC_W_INDEX__SI__VI = 0x00F2; -constexpr unsigned int ioGENENB__SI__VI = 0x00F0; -constexpr unsigned int ioGENFC_RD__SI__VI = 0x00F2; -constexpr unsigned int ioGENFC_WT__SI__VI = 0x00EE; -constexpr unsigned int ioGENMO_RD__SI__VI = 0x00F3; -constexpr unsigned int ioGENMO_WT__SI__VI = 0x00F0; -constexpr unsigned int ioGENS0__SI__VI = 0x00F0; -constexpr unsigned int ioGENS1__SI__VI = 0x00EE; -constexpr unsigned int ioGRPH8_DATA__SI__VI = 0x00F3; -constexpr unsigned int ioGRPH8_IDX__SI__VI = 0x00F3; -constexpr unsigned int ioMM_DATA = 0x0001; -constexpr unsigned int ioMM_INDEX = 0x0000; -constexpr unsigned int ioMM_INDEX_HI__CI__VI = 0x0006; -constexpr unsigned int ioPCIE_DATA_2__CI__VI = 0x000D; -constexpr unsigned int ioPCIE_DATA__CI__VI = 0x000F; -constexpr unsigned int ioPCIE_DATA__SI = 0x000D; -constexpr unsigned int ioPCIE_INDEX_2__CI__VI = 0x000C; -constexpr unsigned int ioPCIE_INDEX__CI__VI = 0x000E; -constexpr unsigned int ioPCIE_INDEX__SI = 0x000C; -constexpr unsigned int ioROM_DATA__SI = 0x002B; -constexpr unsigned int ioROM_INDEX__SI = 0x002A; -constexpr unsigned int ioSEQ8_DATA__SI__VI = 0x00F1; -constexpr unsigned int ioSEQ8_IDX__SI__VI = 0x00F1; -constexpr unsigned int ioVGA_MEM_READ_PAGE_ADDR__SI__VI = 0x0013; -constexpr unsigned int ioVGA_MEM_WRITE_PAGE_ADDR__SI__VI = 0x0012; -constexpr unsigned int mmABM_TEST_DEBUG_DATA__SI__VI = 0x169F; -constexpr unsigned int mmABM_TEST_DEBUG_INDEX__SI__VI = 0x169E; -constexpr unsigned int mmACP_CONFIG__CI = 0x0F95; -constexpr unsigned int mmAFMT_60958_0__SI = 0x1C41; -constexpr unsigned int mmAFMT_60958_1__SI = 0x1C42; -constexpr unsigned int mmAFMT_60958_2__SI = 0x1C48; -constexpr unsigned int mmAFMT_AUDIO_CRC_CONTROL__SI = 0x1C43; -constexpr unsigned int mmAFMT_AUDIO_CRC_RESULT__SI = 0x1C49; -constexpr unsigned int mmAFMT_AUDIO_INFO0__SI = 0x1C3F; -constexpr unsigned int mmAFMT_AUDIO_INFO1__SI = 0x1C40; -constexpr unsigned int mmAFMT_AUDIO_PACKET_CONTROL2__SI = 0x1C17; -constexpr unsigned int mmAFMT_AUDIO_PACKET_CONTROL__SI = 0x1C4B; -constexpr unsigned int mmAFMT_AVI_INFO0__SI = 0x1C21; -constexpr unsigned int mmAFMT_AVI_INFO1__SI = 0x1C22; -constexpr unsigned int mmAFMT_AVI_INFO2__SI = 0x1C23; -constexpr unsigned int mmAFMT_AVI_INFO3__SI = 0x1C24; -constexpr unsigned int mmAFMT_INFOFRAME_CONTROL0__SI = 0x1C4D; -constexpr unsigned int mmAFMT_ISRC1_0__SI = 0x1C18; -constexpr unsigned int mmAFMT_ISRC1_1__SI = 0x1C19; -constexpr unsigned int mmAFMT_ISRC1_2__SI = 0x1C1A; -constexpr unsigned int mmAFMT_ISRC1_3__SI = 0x1C1B; -constexpr unsigned int mmAFMT_ISRC1_4__SI = 0x1C1C; -constexpr unsigned int mmAFMT_ISRC2_0__SI = 0x1C1D; -constexpr unsigned int mmAFMT_ISRC2_1__SI = 0x1C1E; -constexpr unsigned int mmAFMT_ISRC2_2__SI = 0x1C1F; -constexpr unsigned int mmAFMT_ISRC2_3__SI = 0x1C20; -constexpr unsigned int mmAFMT_MPEG_INFO0__SI = 0x1C25; -constexpr unsigned int mmAFMT_MPEG_INFO1__SI = 0x1C26; -constexpr unsigned int mmAFMT_RAMP_CONTROL0__SI = 0x1C44; -constexpr unsigned int mmAFMT_RAMP_CONTROL1__SI = 0x1C45; -constexpr unsigned int mmAFMT_RAMP_CONTROL2__SI = 0x1C46; -constexpr unsigned int mmAFMT_RAMP_CONTROL3__SI = 0x1C47; -constexpr unsigned int mmAFMT_STATUS__SI = 0x1C4A; -constexpr unsigned int mmAFMT_VBI_PACKET_CONTROL__SI = 0x1C4C; -constexpr unsigned int mmATC_ATS_CNTL__CI__VI = 0x0CC9; -constexpr unsigned int mmATC_ATS_DEBUG__CI__VI = 0x0CCA; -constexpr unsigned int mmATC_ATS_DEFAULT_PAGE_CNTL__CI__VI = 0x0CD1; -constexpr unsigned int mmATC_ATS_DEFAULT_PAGE_LOW__CI__VI = 0x0CD0; -constexpr unsigned int mmATC_ATS_FAULT_CNTL__CI__VI = 0x0CCD; -constexpr unsigned int mmATC_ATS_FAULT_DEBUG__CI__VI = 0x0CCB; -constexpr unsigned int mmATC_ATS_FAULT_STATUS_ADDR__CI__VI = 0x0CCF; -constexpr unsigned int mmATC_ATS_FAULT_STATUS_INFO__CI__VI = 0x0CCE; -constexpr unsigned int mmATC_ATS_STATUS__CI__VI = 0x0CCC; -constexpr unsigned int mmATC_L1RD_DEBUG_TLB__CI__VI = 0x0CDE; -constexpr unsigned int mmATC_L1RD_STATUS__CI__VI = 0x0CE0; -constexpr unsigned int mmATC_L1WR_DEBUG_TLB__CI__VI = 0x0CDF; -constexpr unsigned int mmATC_L1WR_STATUS__CI__VI = 0x0CE1; -constexpr unsigned int mmATC_L1_ADDRESS_OFFSET__CI__VI = 0x0CDD; -constexpr unsigned int mmATC_L1_CNTL__CI__VI = 0x0CDC; -constexpr unsigned int mmATC_L2_CNTL2__CI__VI = 0x0CD6; -constexpr unsigned int mmATC_L2_CNTL__CI__VI = 0x0CD5; -constexpr unsigned int mmATC_L2_DEBUG2__CI__VI = 0x0CD8; -constexpr unsigned int mmATC_L2_DEBUG__CI__VI = 0x0CD7; -constexpr unsigned int mmATC_MISC_CG__CI__VI = 0x0CD4; -constexpr unsigned int mmATC_PERFCOUNTER0_CFG__CI__VI = 0x07C8; -constexpr unsigned int mmATC_PERFCOUNTER1_CFG__CI__VI = 0x07C9; -constexpr unsigned int mmATC_PERFCOUNTER2_CFG__CI__VI = 0x07CA; -constexpr unsigned int mmATC_PERFCOUNTER3_CFG__CI__VI = 0x07CB; -constexpr unsigned int mmATC_PERFCOUNTER_HI__CI__VI = 0x07AF; -constexpr unsigned int mmATC_PERFCOUNTER_LO__CI__VI = 0x07A7; -constexpr unsigned int mmATC_PERFCOUNTER_RSLT_CNTL__CI__VI = 0x07D5; -constexpr unsigned int mmATC_VMID0_PASID_MAPPING__CI__VI = 0x0CE7; -constexpr unsigned int mmATC_VMID10_PASID_MAPPING__CI__VI = 0x0CF1; -constexpr unsigned int mmATC_VMID11_PASID_MAPPING__CI__VI = 0x0CF2; -constexpr unsigned int mmATC_VMID12_PASID_MAPPING__CI__VI = 0x0CF3; -constexpr unsigned int mmATC_VMID13_PASID_MAPPING__CI__VI = 0x0CF4; -constexpr unsigned int mmATC_VMID14_PASID_MAPPING__CI__VI = 0x0CF5; -constexpr unsigned int mmATC_VMID15_PASID_MAPPING__CI__VI = 0x0CF6; -constexpr unsigned int mmATC_VMID1_PASID_MAPPING__CI__VI = 0x0CE8; -constexpr unsigned int mmATC_VMID2_PASID_MAPPING__CI__VI = 0x0CE9; -constexpr unsigned int mmATC_VMID3_PASID_MAPPING__CI__VI = 0x0CEA; -constexpr unsigned int mmATC_VMID4_PASID_MAPPING__CI__VI = 0x0CEB; -constexpr unsigned int mmATC_VMID5_PASID_MAPPING__CI__VI = 0x0CEC; -constexpr unsigned int mmATC_VMID6_PASID_MAPPING__CI__VI = 0x0CED; -constexpr unsigned int mmATC_VMID7_PASID_MAPPING__CI__VI = 0x0CEE; -constexpr unsigned int mmATC_VMID8_PASID_MAPPING__CI__VI = 0x0CEF; -constexpr unsigned int mmATC_VMID9_PASID_MAPPING__CI__VI = 0x0CF0; -constexpr unsigned int mmATC_VMID_PASID_MAPPING_UPDATE_STATUS__CI__VI = 0x0CE6; -constexpr unsigned int mmATC_VM_APERTURE0_CNTL2__CI__VI = 0x0CC6; -constexpr unsigned int mmATC_VM_APERTURE0_CNTL__CI__VI = 0x0CC4; -constexpr unsigned int mmATC_VM_APERTURE0_HIGH_ADDR__CI__VI = 0x0CC2; -constexpr unsigned int mmATC_VM_APERTURE0_LOW_ADDR__CI__VI = 0x0CC0; -constexpr unsigned int mmATC_VM_APERTURE1_CNTL2__CI__VI = 0x0CC7; -constexpr unsigned int mmATC_VM_APERTURE1_CNTL__CI__VI = 0x0CC5; -constexpr unsigned int mmATC_VM_APERTURE1_HIGH_ADDR__CI__VI = 0x0CC3; -constexpr unsigned int mmATC_VM_APERTURE1_LOW_ADDR__CI__VI = 0x0CC1; -constexpr unsigned int mmATTRDR__SI__VI = 0x00F0; -constexpr unsigned int mmATTRDW__SI__VI = 0x00F0; -constexpr unsigned int mmATTRX__SI__VI = 0x00F0; -constexpr unsigned int mmAUXN_IMPCAL__SI = 0x194B; -constexpr unsigned int mmAUXP_IMPCAL__SI = 0x194A; -constexpr unsigned int mmAUX_ARB_CONTROL__SI = 0x1882; -constexpr unsigned int mmAUX_CONTROL__SI = 0x1880; -constexpr unsigned int mmAUX_DPHY_RX_CONTROL0__SI = 0x188A; -constexpr unsigned int mmAUX_DPHY_RX_CONTROL1__SI = 0x188B; -constexpr unsigned int mmAUX_DPHY_RX_STATUS__SI = 0x188D; -constexpr unsigned int mmAUX_DPHY_TX_CONTROL__SI = 0x1889; -constexpr unsigned int mmAUX_DPHY_TX_REF_CONTROL__SI = 0x1888; -constexpr unsigned int mmAUX_DPHY_TX_STATUS__SI = 0x188C; -constexpr unsigned int mmAUX_INTERRUPT_CONTROL__SI = 0x1883; -constexpr unsigned int mmAUX_LS_DATA__SI = 0x1887; -constexpr unsigned int mmAUX_LS_STATUS__SI = 0x1885; -constexpr unsigned int mmAUX_SW_CONTROL__SI = 0x1881; -constexpr unsigned int mmAUX_SW_DATA__SI = 0x1886; -constexpr unsigned int mmAUX_SW_STATUS__SI = 0x1884; -constexpr unsigned int mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__SI = 0x17F6; -constexpr unsigned int mmAZALIA_AUDIO_DTO_CONTROL__SI = 0x173D; -constexpr unsigned int mmAZALIA_AUDIO_DTO__SI = 0x173C; -constexpr unsigned int mmAZALIA_BDL_DMA_CONTROL__SI = 0x1730; -constexpr unsigned int mmAZALIA_CORB_DMA_CONTROL__SI = 0x172F; -constexpr unsigned int mmAZALIA_CUMULATIVE_LATENCY_COUNT__SI = 0x1737; -constexpr unsigned int mmAZALIA_CUMULATIVE_REQUEST_COUNT__SI = 0x1738; -constexpr unsigned int mmAZALIA_CYCLIC_BUFFER_SYNC__SI = 0x17F7; -constexpr unsigned int mmAZALIA_DATA_DMA_CONTROL__SI = 0x1731; -constexpr unsigned int mmAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__SI = 0x174F; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__SI = 0x174C; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__SI = 0x174D; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI = 0x1750; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI = 0x1742; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI = 0x1745; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI = 0x1744; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI = 0x1743; -constexpr unsigned int mmAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__SI = 0x174B; -constexpr unsigned int mmAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__SI = 0x1753; -constexpr unsigned int mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__SI = 0x173F; -constexpr unsigned int mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI = 0x173E; -constexpr unsigned int mmAZALIA_LATENCY_COUNTER_CONTROL__SI = 0x1735; -constexpr unsigned int mmAZALIA_RIRB_AND_DP_CONTROL__SI = 0x172D; -constexpr unsigned int mmAZALIA_UNDERFLOW_FILLER_SAMPLE__SI = 0x1732; -constexpr unsigned int mmAZALIA_WORSTCASE_LATENCY_COUNT__SI = 0x1736; -constexpr unsigned int mmAZ_TEST_DEBUG_DATA__SI = 0x1756; -constexpr unsigned int mmAZ_TEST_DEBUG_INDEX__SI = 0x1755; -constexpr unsigned int mmBACO_CNTL_MISC__CI__VI = 0x14DB; -constexpr unsigned int mmBACO_CNTL__CI__VI = 0x14E5; -constexpr unsigned int mmBCI_DEBUG_READ__CI__VI = 0x24EB; -constexpr unsigned int mmBCI_DEBUG_READ__SI = 0x24E3; -constexpr unsigned int mmBIF_BACO_DEBUG_LATCH__CI__VI = 0x14DC; -constexpr unsigned int mmBIF_BACO_DEBUG__CI__VI = 0x14DF; -constexpr unsigned int mmBIF_BACO_MSIC__CI = 0x1480; -constexpr unsigned int mmBIF_BUSNUM_CNTL1 = 0x1525; -constexpr unsigned int mmBIF_BUSNUM_CNTL2 = 0x152B; -constexpr unsigned int mmBIF_BUSNUM_LIST0 = 0x1526; -constexpr unsigned int mmBIF_BUSNUM_LIST1 = 0x1527; -constexpr unsigned int mmBIF_BUSY_DELAY_CNTR = 0x1529; -constexpr unsigned int mmBIF_CC_RFE_IMP_OVERRIDECNTL__CI__VI = 0x1455; -constexpr unsigned int mmBIF_CLK_PDWN_DELAY_TIMER__CI = 0x1483; -constexpr unsigned int mmBIF_CLK_PDWN_DELAY_TIMER__SI = 0x151F; -constexpr unsigned int mmBIF_DEBUG_CNTL = 0x151C; -constexpr unsigned int mmBIF_DEBUG_MUX = 0x151D; -constexpr unsigned int mmBIF_DEBUG_OUT = 0x151E; -constexpr unsigned int mmBIF_DEVFUNCNUM_LIST0__CI__VI = 0x14E8; -constexpr unsigned int mmBIF_DEVFUNCNUM_LIST1__CI__VI = 0x14E7; -constexpr unsigned int mmBIF_DOORBELL_CNTL__CI__VI = 0x14C3; -constexpr unsigned int mmBIF_FB_EN = 0x1524; -constexpr unsigned int mmBIF_FEATURES_CONTROL_MISC__CI__VI = 0x14C2; -constexpr unsigned int mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__CI__VI = 0x1454; -constexpr unsigned int mmBIF_IMPCTL_RXCNTL__CI__VI = 0x1451; -constexpr unsigned int mmBIF_IMPCTL_SMPLCNTL__CI__VI = 0x1450; -constexpr unsigned int mmBIF_IMPCTL_TXCNTL_pd__CI__VI = 0x1452; -constexpr unsigned int mmBIF_IMPCTL_TXCNTL_pu__CI__VI = 0x1453; -constexpr unsigned int mmBIF_LNCNT_RESET__CI = 0x1488; -constexpr unsigned int mmBIF_PERFCOUNTER0_RESULT__CI__VI = 0x152D; -constexpr unsigned int mmBIF_PERFCOUNTER1_RESULT__CI__VI = 0x152E; -constexpr unsigned int mmBIF_PERFMON_CNTL__CI__VI = 0x152C; -constexpr unsigned int mmBIF_PIF_TXCLK_SWITCH_TIMER__CI = 0x1481; -constexpr unsigned int mmBIF_PWDN_COMMAND__CI__VI = 0x1444; -constexpr unsigned int mmBIF_PWDN_STATUS__CI__VI = 0x1445; -constexpr unsigned int mmBIF_RESET_CNTL__CI = 0x1486; -constexpr unsigned int mmBIF_RESET_EN__CI = 0x1482; -constexpr unsigned int mmBIF_RESET_EN__SI = 0x1511; -constexpr unsigned int mmBIF_RFE_CLIENT_SOFTRST_TRIGGER__CI__VI = 0x1442; -constexpr unsigned int mmBIF_RFE_IMPRST_CNTL__CI__VI = 0x1458; -constexpr unsigned int mmBIF_RFE_MASTER_SOFTRST_TRIGGER__CI__VI = 0x1443; -constexpr unsigned int mmBIF_RFE_MMCFG_CNTL__CI__VI = 0x144C; -constexpr unsigned int mmBIF_RFE_MST_BU_CMDSTATUS__CI__VI = 0x1446; -constexpr unsigned int mmBIF_RFE_MST_BX_CMDSTATUS__CI = 0x1448; -constexpr unsigned int mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__CI__VI = 0x1447; -constexpr unsigned int mmBIF_RFE_MST_TMOUT_STATUS__CI__VI = 0x144B; -constexpr unsigned int mmBIF_RFE_SNOOP_REG__CI__VI = 0x0027; -constexpr unsigned int mmBIF_RFE_SOFTRST_CNTL__CI__VI = 0x1441; -constexpr unsigned int mmBIF_SCRATCH0 = 0x150E; -constexpr unsigned int mmBIF_SCRATCH1 = 0x150F; -constexpr unsigned int mmBIF_SLVARB_MODE__CI__VI = 0x14C4; -constexpr unsigned int mmBIF_SSA_DISP_LOWER__CI = 0x14D2; -constexpr unsigned int mmBIF_SSA_DISP_UPPER__CI = 0x14D3; -constexpr unsigned int mmBIF_SSA_GFX0_LOWER__CI = 0x14CA; -constexpr unsigned int mmBIF_SSA_GFX0_UPPER__CI = 0x14CB; -constexpr unsigned int mmBIF_SSA_GFX1_LOWER__CI = 0x14CC; -constexpr unsigned int mmBIF_SSA_GFX1_UPPER__CI = 0x14CD; -constexpr unsigned int mmBIF_SSA_GFX2_LOWER__CI = 0x14CE; -constexpr unsigned int mmBIF_SSA_GFX2_UPPER__CI = 0x14CF; -constexpr unsigned int mmBIF_SSA_GFX3_LOWER__CI = 0x14D0; -constexpr unsigned int mmBIF_SSA_GFX3_UPPER__CI = 0x14D1; -constexpr unsigned int mmBIF_SSA_MC_LOWER__CI = 0x14D4; -constexpr unsigned int mmBIF_SSA_MC_UPPER__CI = 0x14D5; -constexpr unsigned int mmBIF_SSA_PWR_STATUS__CI = 0x14C8; -constexpr unsigned int mmBIF_XDMA_HI__CI__VI = 0x14C1; -constexpr unsigned int mmBIF_XDMA_LO__CI__VI = 0x14C0; -constexpr unsigned int mmBIOS_SCRATCH_0 = 0x05C9; -constexpr unsigned int mmBIOS_SCRATCH_1 = 0x05CA; -constexpr unsigned int mmBIOS_SCRATCH_10 = 0x05D3; -constexpr unsigned int mmBIOS_SCRATCH_11 = 0x05D4; -constexpr unsigned int mmBIOS_SCRATCH_12 = 0x05D5; -constexpr unsigned int mmBIOS_SCRATCH_13 = 0x05D6; -constexpr unsigned int mmBIOS_SCRATCH_14 = 0x05D7; -constexpr unsigned int mmBIOS_SCRATCH_15 = 0x05D8; -constexpr unsigned int mmBIOS_SCRATCH_2 = 0x05CB; -constexpr unsigned int mmBIOS_SCRATCH_3 = 0x05CC; -constexpr unsigned int mmBIOS_SCRATCH_4 = 0x05CD; -constexpr unsigned int mmBIOS_SCRATCH_5 = 0x05CE; -constexpr unsigned int mmBIOS_SCRATCH_6 = 0x05CF; -constexpr unsigned int mmBIOS_SCRATCH_7 = 0x05D0; -constexpr unsigned int mmBIOS_SCRATCH_8 = 0x05D1; -constexpr unsigned int mmBIOS_SCRATCH_9 = 0x05D2; -constexpr unsigned int mmBL1_PWM_ABM_CNTL__SI__VI = 0x162E; -constexpr unsigned int mmBL1_PWM_AMBIENT_LIGHT_LEVEL__SI__VI = 0x1628; -constexpr unsigned int mmBL1_PWM_BL_UPDATE_SAMPLE_RATE__SI__VI = 0x162F; -constexpr unsigned int mmBL1_PWM_CURRENT_ABM_LEVEL__SI__VI = 0x162B; -constexpr unsigned int mmBL1_PWM_FINAL_DUTY_CYCLE__SI__VI = 0x162C; -constexpr unsigned int mmBL1_PWM_GRP2_REG_LOCK__SI__VI = 0x1630; -constexpr unsigned int mmBL1_PWM_MINIMUM_DUTY_CYCLE__SI__VI = 0x162D; -constexpr unsigned int mmBL1_PWM_TARGET_ABM_LEVEL__SI__VI = 0x162A; -constexpr unsigned int mmBL1_PWM_USER_LEVEL__SI__VI = 0x1629; -constexpr unsigned int mmBL_PWM_CNTL2__SI = 0x1968; -constexpr unsigned int mmBL_PWM_CNTL__SI = 0x1967; -constexpr unsigned int mmBL_PWM_GRP1_REG_LOCK__SI = 0x196A; -constexpr unsigned int mmBL_PWM_PERIOD_CNTL__SI = 0x1969; -constexpr unsigned int mmBUS_CNTL = 0x1508; -constexpr unsigned int mmBX_RESET_EN__CI__VI = 0x1514; -constexpr unsigned int mmCAPTURE_HOST_BUSNUM = 0x153C; -constexpr unsigned int mmCB_BLEND0_CONTROL = 0xA1E0; -constexpr unsigned int mmCB_BLEND1_CONTROL = 0xA1E1; -constexpr unsigned int mmCB_BLEND2_CONTROL = 0xA1E2; -constexpr unsigned int mmCB_BLEND3_CONTROL = 0xA1E3; -constexpr unsigned int mmCB_BLEND4_CONTROL = 0xA1E4; -constexpr unsigned int mmCB_BLEND5_CONTROL = 0xA1E5; -constexpr unsigned int mmCB_BLEND6_CONTROL = 0xA1E6; -constexpr unsigned int mmCB_BLEND7_CONTROL = 0xA1E7; -constexpr unsigned int mmCB_BLEND_ALPHA = 0xA108; -constexpr unsigned int mmCB_BLEND_BLUE = 0xA107; -constexpr unsigned int mmCB_BLEND_GREEN = 0xA106; -constexpr unsigned int mmCB_BLEND_RED = 0xA105; -constexpr unsigned int mmCB_CGTT_SCLK_CTRL__CI__VI = 0xF0A8; -constexpr unsigned int mmCB_CGTT_SCLK_CTRL__SI = 0x2698; -constexpr unsigned int mmCB_COLOR0_ATTRIB = 0xA31D; -constexpr unsigned int mmCB_COLOR0_BASE = 0xA318; -constexpr unsigned int mmCB_COLOR0_CLEAR_WORD0 = 0xA323; -constexpr unsigned int mmCB_COLOR0_CLEAR_WORD1 = 0xA324; -constexpr unsigned int mmCB_COLOR0_CMASK = 0xA31F; -constexpr unsigned int mmCB_COLOR0_CMASK_SLICE = 0xA320; -constexpr unsigned int mmCB_COLOR0_FMASK = 0xA321; -constexpr unsigned int mmCB_COLOR0_FMASK_SLICE = 0xA322; -constexpr unsigned int mmCB_COLOR0_INFO = 0xA31C; -constexpr unsigned int mmCB_COLOR0_PITCH = 0xA319; -constexpr unsigned int mmCB_COLOR0_SLICE = 0xA31A; -constexpr unsigned int mmCB_COLOR0_VIEW = 0xA31B; -constexpr unsigned int mmCB_COLOR1_ATTRIB = 0xA32C; -constexpr unsigned int mmCB_COLOR1_BASE = 0xA327; -constexpr unsigned int mmCB_COLOR1_CLEAR_WORD0 = 0xA332; -constexpr unsigned int mmCB_COLOR1_CLEAR_WORD1 = 0xA333; -constexpr unsigned int mmCB_COLOR1_CMASK = 0xA32E; -constexpr unsigned int mmCB_COLOR1_CMASK_SLICE = 0xA32F; -constexpr unsigned int mmCB_COLOR1_FMASK = 0xA330; -constexpr unsigned int mmCB_COLOR1_FMASK_SLICE = 0xA331; -constexpr unsigned int mmCB_COLOR1_INFO = 0xA32B; -constexpr unsigned int mmCB_COLOR1_PITCH = 0xA328; -constexpr unsigned int mmCB_COLOR1_SLICE = 0xA329; -constexpr unsigned int mmCB_COLOR1_VIEW = 0xA32A; -constexpr unsigned int mmCB_COLOR2_ATTRIB = 0xA33B; -constexpr unsigned int mmCB_COLOR2_BASE = 0xA336; -constexpr unsigned int mmCB_COLOR2_CLEAR_WORD0 = 0xA341; -constexpr unsigned int mmCB_COLOR2_CLEAR_WORD1 = 0xA342; -constexpr unsigned int mmCB_COLOR2_CMASK = 0xA33D; -constexpr unsigned int mmCB_COLOR2_CMASK_SLICE = 0xA33E; -constexpr unsigned int mmCB_COLOR2_FMASK = 0xA33F; -constexpr unsigned int mmCB_COLOR2_FMASK_SLICE = 0xA340; -constexpr unsigned int mmCB_COLOR2_INFO = 0xA33A; -constexpr unsigned int mmCB_COLOR2_PITCH = 0xA337; -constexpr unsigned int mmCB_COLOR2_SLICE = 0xA338; -constexpr unsigned int mmCB_COLOR2_VIEW = 0xA339; -constexpr unsigned int mmCB_COLOR3_ATTRIB = 0xA34A; -constexpr unsigned int mmCB_COLOR3_BASE = 0xA345; -constexpr unsigned int mmCB_COLOR3_CLEAR_WORD0 = 0xA350; -constexpr unsigned int mmCB_COLOR3_CLEAR_WORD1 = 0xA351; -constexpr unsigned int mmCB_COLOR3_CMASK = 0xA34C; -constexpr unsigned int mmCB_COLOR3_CMASK_SLICE = 0xA34D; -constexpr unsigned int mmCB_COLOR3_FMASK = 0xA34E; -constexpr unsigned int mmCB_COLOR3_FMASK_SLICE = 0xA34F; -constexpr unsigned int mmCB_COLOR3_INFO = 0xA349; -constexpr unsigned int mmCB_COLOR3_PITCH = 0xA346; -constexpr unsigned int mmCB_COLOR3_SLICE = 0xA347; -constexpr unsigned int mmCB_COLOR3_VIEW = 0xA348; -constexpr unsigned int mmCB_COLOR4_ATTRIB = 0xA359; -constexpr unsigned int mmCB_COLOR4_BASE = 0xA354; -constexpr unsigned int mmCB_COLOR4_CLEAR_WORD0 = 0xA35F; -constexpr unsigned int mmCB_COLOR4_CLEAR_WORD1 = 0xA360; -constexpr unsigned int mmCB_COLOR4_CMASK = 0xA35B; -constexpr unsigned int mmCB_COLOR4_CMASK_SLICE = 0xA35C; -constexpr unsigned int mmCB_COLOR4_FMASK = 0xA35D; -constexpr unsigned int mmCB_COLOR4_FMASK_SLICE = 0xA35E; -constexpr unsigned int mmCB_COLOR4_INFO = 0xA358; -constexpr unsigned int mmCB_COLOR4_PITCH = 0xA355; -constexpr unsigned int mmCB_COLOR4_SLICE = 0xA356; -constexpr unsigned int mmCB_COLOR4_VIEW = 0xA357; -constexpr unsigned int mmCB_COLOR5_ATTRIB = 0xA368; -constexpr unsigned int mmCB_COLOR5_BASE = 0xA363; -constexpr unsigned int mmCB_COLOR5_CLEAR_WORD0 = 0xA36E; -constexpr unsigned int mmCB_COLOR5_CLEAR_WORD1 = 0xA36F; -constexpr unsigned int mmCB_COLOR5_CMASK = 0xA36A; -constexpr unsigned int mmCB_COLOR5_CMASK_SLICE = 0xA36B; -constexpr unsigned int mmCB_COLOR5_FMASK = 0xA36C; -constexpr unsigned int mmCB_COLOR5_FMASK_SLICE = 0xA36D; -constexpr unsigned int mmCB_COLOR5_INFO = 0xA367; -constexpr unsigned int mmCB_COLOR5_PITCH = 0xA364; -constexpr unsigned int mmCB_COLOR5_SLICE = 0xA365; -constexpr unsigned int mmCB_COLOR5_VIEW = 0xA366; -constexpr unsigned int mmCB_COLOR6_ATTRIB = 0xA377; -constexpr unsigned int mmCB_COLOR6_BASE = 0xA372; -constexpr unsigned int mmCB_COLOR6_CLEAR_WORD0 = 0xA37D; -constexpr unsigned int mmCB_COLOR6_CLEAR_WORD1 = 0xA37E; -constexpr unsigned int mmCB_COLOR6_CMASK = 0xA379; -constexpr unsigned int mmCB_COLOR6_CMASK_SLICE = 0xA37A; -constexpr unsigned int mmCB_COLOR6_FMASK = 0xA37B; -constexpr unsigned int mmCB_COLOR6_FMASK_SLICE = 0xA37C; -constexpr unsigned int mmCB_COLOR6_INFO = 0xA376; -constexpr unsigned int mmCB_COLOR6_PITCH = 0xA373; -constexpr unsigned int mmCB_COLOR6_SLICE = 0xA374; -constexpr unsigned int mmCB_COLOR6_VIEW = 0xA375; -constexpr unsigned int mmCB_COLOR7_ATTRIB = 0xA386; -constexpr unsigned int mmCB_COLOR7_BASE = 0xA381; -constexpr unsigned int mmCB_COLOR7_CLEAR_WORD0 = 0xA38C; -constexpr unsigned int mmCB_COLOR7_CLEAR_WORD1 = 0xA38D; -constexpr unsigned int mmCB_COLOR7_CMASK = 0xA388; -constexpr unsigned int mmCB_COLOR7_CMASK_SLICE = 0xA389; -constexpr unsigned int mmCB_COLOR7_FMASK = 0xA38A; -constexpr unsigned int mmCB_COLOR7_FMASK_SLICE = 0xA38B; -constexpr unsigned int mmCB_COLOR7_INFO = 0xA385; -constexpr unsigned int mmCB_COLOR7_PITCH = 0xA382; -constexpr unsigned int mmCB_COLOR7_SLICE = 0xA383; -constexpr unsigned int mmCB_COLOR7_VIEW = 0xA384; -constexpr unsigned int mmCB_COLOR_CONTROL = 0xA202; -constexpr unsigned int mmCB_DEBUG_BUS_1 = 0x2699; -constexpr unsigned int mmCB_DEBUG_BUS_13 = 0x26A5; -constexpr unsigned int mmCB_DEBUG_BUS_14 = 0x26A6; -constexpr unsigned int mmCB_DEBUG_BUS_15 = 0x26A7; -constexpr unsigned int mmCB_DEBUG_BUS_16 = 0x26A8; -constexpr unsigned int mmCB_DEBUG_BUS_17 = 0x26A9; -constexpr unsigned int mmCB_DEBUG_BUS_18 = 0x26AA; -constexpr unsigned int mmCB_DEBUG_BUS_2 = 0x269A; -constexpr unsigned int mmCB_HW_CONTROL = 0x2684; -constexpr unsigned int mmCB_HW_CONTROL_1 = 0x2685; -constexpr unsigned int mmCB_HW_CONTROL_2 = 0x2686; -constexpr unsigned int mmCB_HW_CONTROL_3__CI__VI = 0x2683; -constexpr unsigned int mmCB_PERFCOUNTER0_HI__CI__VI = 0xD407; -constexpr unsigned int mmCB_PERFCOUNTER0_HI__SI = 0x2691; -constexpr unsigned int mmCB_PERFCOUNTER0_LO__CI__VI = 0xD406; -constexpr unsigned int mmCB_PERFCOUNTER0_LO__SI = 0x2690; -constexpr unsigned int mmCB_PERFCOUNTER0_SELECT0__SI = 0x2688; -constexpr unsigned int mmCB_PERFCOUNTER0_SELECT1__CI__VI = 0xDC02; -constexpr unsigned int mmCB_PERFCOUNTER0_SELECT1__SI = 0x2689; -constexpr unsigned int mmCB_PERFCOUNTER0_SELECT__CI__VI = 0xDC01; -constexpr unsigned int mmCB_PERFCOUNTER1_HI__CI__VI = 0xD409; -constexpr unsigned int mmCB_PERFCOUNTER1_HI__SI = 0x2693; -constexpr unsigned int mmCB_PERFCOUNTER1_LO__CI__VI = 0xD408; -constexpr unsigned int mmCB_PERFCOUNTER1_LO__SI = 0x2692; -constexpr unsigned int mmCB_PERFCOUNTER1_SELECT0__SI = 0x268A; -constexpr unsigned int mmCB_PERFCOUNTER1_SELECT1__SI = 0x268B; -constexpr unsigned int mmCB_PERFCOUNTER1_SELECT__CI__VI = 0xDC03; -constexpr unsigned int mmCB_PERFCOUNTER2_HI__CI__VI = 0xD40B; -constexpr unsigned int mmCB_PERFCOUNTER2_HI__SI = 0x2695; -constexpr unsigned int mmCB_PERFCOUNTER2_LO__CI__VI = 0xD40A; -constexpr unsigned int mmCB_PERFCOUNTER2_LO__SI = 0x2694; -constexpr unsigned int mmCB_PERFCOUNTER2_SELECT0__SI = 0x268C; -constexpr unsigned int mmCB_PERFCOUNTER2_SELECT1__SI = 0x268D; -constexpr unsigned int mmCB_PERFCOUNTER2_SELECT__CI__VI = 0xDC04; -constexpr unsigned int mmCB_PERFCOUNTER3_HI__CI__VI = 0xD40D; -constexpr unsigned int mmCB_PERFCOUNTER3_HI__SI = 0x2697; -constexpr unsigned int mmCB_PERFCOUNTER3_LO__CI__VI = 0xD40C; -constexpr unsigned int mmCB_PERFCOUNTER3_LO__SI = 0x2696; -constexpr unsigned int mmCB_PERFCOUNTER3_SELECT0__SI = 0x268E; -constexpr unsigned int mmCB_PERFCOUNTER3_SELECT1__SI = 0x268F; -constexpr unsigned int mmCB_PERFCOUNTER3_SELECT__CI__VI = 0xDC05; -constexpr unsigned int mmCB_PERFCOUNTER_FILTER__CI__VI = 0xDC00; -constexpr unsigned int mmCB_SHADER_MASK = 0xA08F; -constexpr unsigned int mmCB_TARGET_MASK = 0xA08E; -constexpr unsigned int mmCC_DRM_ID_STRAPS = 0x1559; -constexpr unsigned int mmCC_GC_EDC_CONFIG__CI__VI = 0x3098; -constexpr unsigned int mmCC_GC_PRIM_CONFIG__CI__VI = 0x2240; -constexpr unsigned int mmCC_GC_SHADER_ARRAY_CONFIG = 0x226F; -constexpr unsigned int mmCC_MC_MAX_CHANNEL = 0x096E; -constexpr unsigned int mmCC_RB_BACKEND_DISABLE = 0x263D; -constexpr unsigned int mmCC_RB_DAISY_CHAIN = 0x2641; -constexpr unsigned int mmCC_RB_REDUNDANCY = 0x263C; -constexpr unsigned int mmCC_SQC_BANK_DISABLE = 0x2307; -constexpr unsigned int mmCC_SYS_RB_BACKEND_DISABLE = 0x03A0; -constexpr unsigned int mmCC_SYS_RB_REDUNDANCY = 0x039F; -constexpr unsigned int mmCGTS_CU0_LDS_SQ_CTRL_REG__CI__VI = 0xF009; -constexpr unsigned int mmCGTS_CU0_SP0_CTRL_REG__CI__VI = 0xF008; -constexpr unsigned int mmCGTS_CU0_SP1_CTRL_REG__CI__VI = 0xF00B; -constexpr unsigned int mmCGTS_CU0_TA_SQC_CTRL_REG__CI__VI = 0xF00A; -constexpr unsigned int mmCGTS_CU0_TD_TCP_CTRL_REG__CI__VI = 0xF00C; -constexpr unsigned int mmCGTS_CU10_LDS_SQ_CTRL_REG__CI__VI = 0xF03B; -constexpr unsigned int mmCGTS_CU10_SP0_CTRL_REG__CI__VI = 0xF03A; -constexpr unsigned int mmCGTS_CU10_SP1_CTRL_REG__CI__VI = 0xF03D; -constexpr unsigned int mmCGTS_CU10_TA_CTRL_REG__CI__VI = 0xF03C; -constexpr unsigned int mmCGTS_CU10_TD_TCP_CTRL_REG__CI__VI = 0xF03E; -constexpr unsigned int mmCGTS_CU11_LDS_SQ_CTRL_REG__CI__VI = 0xF040; -constexpr unsigned int mmCGTS_CU11_SP0_CTRL_REG__CI__VI = 0xF03F; -constexpr unsigned int mmCGTS_CU11_SP1_CTRL_REG__CI__VI = 0xF042; -constexpr unsigned int mmCGTS_CU11_TA_CTRL_REG__CI__VI = 0xF041; -constexpr unsigned int mmCGTS_CU11_TD_TCP_CTRL_REG__CI__VI = 0xF043; -constexpr unsigned int mmCGTS_CU12_LDS_SQ_CTRL_REG__CI__VI = 0xF045; -constexpr unsigned int mmCGTS_CU12_SP0_CTRL_REG__CI__VI = 0xF044; -constexpr unsigned int mmCGTS_CU12_SP1_CTRL_REG__CI__VI = 0xF047; -constexpr unsigned int mmCGTS_CU12_TA_SQC_CTRL_REG__CI__VI = 0xF046; -constexpr unsigned int mmCGTS_CU12_TD_TCP_CTRL_REG__CI__VI = 0xF048; -constexpr unsigned int mmCGTS_CU13_LDS_SQ_CTRL_REG__CI__VI = 0xF04A; -constexpr unsigned int mmCGTS_CU13_SP0_CTRL_REG__CI__VI = 0xF049; -constexpr unsigned int mmCGTS_CU13_SP1_CTRL_REG__CI__VI = 0xF04C; -constexpr unsigned int mmCGTS_CU13_TA_CTRL_REG__CI__VI = 0xF04B; -constexpr unsigned int mmCGTS_CU13_TD_TCP_CTRL_REG__CI__VI = 0xF04D; -constexpr unsigned int mmCGTS_CU14_LDS_SQ_CTRL_REG__CI__VI = 0xF04F; -constexpr unsigned int mmCGTS_CU14_SP0_CTRL_REG__CI__VI = 0xF04E; -constexpr unsigned int mmCGTS_CU14_SP1_CTRL_REG__CI__VI = 0xF051; -constexpr unsigned int mmCGTS_CU14_TA_CTRL_REG__CI__VI = 0xF050; -constexpr unsigned int mmCGTS_CU14_TD_TCP_CTRL_REG__CI__VI = 0xF052; -constexpr unsigned int mmCGTS_CU15_LDS_SQ_CTRL_REG__CI__VI = 0xF054; -constexpr unsigned int mmCGTS_CU15_SP0_CTRL_REG__CI__VI = 0xF053; -constexpr unsigned int mmCGTS_CU15_SP1_CTRL_REG__CI__VI = 0xF056; -constexpr unsigned int mmCGTS_CU15_TA_CTRL_REG__CI__VI = 0xF055; -constexpr unsigned int mmCGTS_CU15_TD_TCP_CTRL_REG__CI__VI = 0xF057; -constexpr unsigned int mmCGTS_CU1_LDS_SQ_CTRL_REG__CI__VI = 0xF00E; -constexpr unsigned int mmCGTS_CU1_SP0_CTRL_REG__CI__VI = 0xF00D; -constexpr unsigned int mmCGTS_CU1_SP1_CTRL_REG__CI__VI = 0xF010; -constexpr unsigned int mmCGTS_CU1_TA_CTRL_REG__CI__VI = 0xF00F; -constexpr unsigned int mmCGTS_CU1_TD_TCP_CTRL_REG__CI__VI = 0xF011; -constexpr unsigned int mmCGTS_CU2_LDS_SQ_CTRL_REG__CI__VI = 0xF013; -constexpr unsigned int mmCGTS_CU2_SP0_CTRL_REG__CI__VI = 0xF012; -constexpr unsigned int mmCGTS_CU2_SP1_CTRL_REG__CI__VI = 0xF015; -constexpr unsigned int mmCGTS_CU2_TA_CTRL_REG__CI__VI = 0xF014; -constexpr unsigned int mmCGTS_CU2_TD_TCP_CTRL_REG__CI__VI = 0xF016; -constexpr unsigned int mmCGTS_CU3_LDS_SQ_CTRL_REG__CI__VI = 0xF018; -constexpr unsigned int mmCGTS_CU3_SP0_CTRL_REG__CI__VI = 0xF017; -constexpr unsigned int mmCGTS_CU3_SP1_CTRL_REG__CI__VI = 0xF01A; -constexpr unsigned int mmCGTS_CU3_TA_CTRL_REG__CI__VI = 0xF019; -constexpr unsigned int mmCGTS_CU3_TD_TCP_CTRL_REG__CI__VI = 0xF01B; -constexpr unsigned int mmCGTS_CU4_LDS_SQ_CTRL_REG__CI__VI = 0xF01D; -constexpr unsigned int mmCGTS_CU4_SP0_CTRL_REG__CI__VI = 0xF01C; -constexpr unsigned int mmCGTS_CU4_SP1_CTRL_REG__CI__VI = 0xF01F; -constexpr unsigned int mmCGTS_CU4_TA_SQC_CTRL_REG__CI__VI = 0xF01E; -constexpr unsigned int mmCGTS_CU4_TD_TCP_CTRL_REG__CI__VI = 0xF020; -constexpr unsigned int mmCGTS_CU5_LDS_SQ_CTRL_REG__CI__VI = 0xF022; -constexpr unsigned int mmCGTS_CU5_SP0_CTRL_REG__CI__VI = 0xF021; -constexpr unsigned int mmCGTS_CU5_SP1_CTRL_REG__CI__VI = 0xF024; -constexpr unsigned int mmCGTS_CU5_TA_CTRL_REG__CI__VI = 0xF023; -constexpr unsigned int mmCGTS_CU5_TD_TCP_CTRL_REG__CI__VI = 0xF025; -constexpr unsigned int mmCGTS_CU6_LDS_SQ_CTRL_REG__CI__VI = 0xF027; -constexpr unsigned int mmCGTS_CU6_SP0_CTRL_REG__CI__VI = 0xF026; -constexpr unsigned int mmCGTS_CU6_SP1_CTRL_REG__CI__VI = 0xF029; -constexpr unsigned int mmCGTS_CU6_TA_CTRL_REG__CI__VI = 0xF028; -constexpr unsigned int mmCGTS_CU6_TD_TCP_CTRL_REG__CI__VI = 0xF02A; -constexpr unsigned int mmCGTS_CU7_LDS_SQ_CTRL_REG__CI__VI = 0xF02C; -constexpr unsigned int mmCGTS_CU7_SP0_CTRL_REG__CI__VI = 0xF02B; -constexpr unsigned int mmCGTS_CU7_SP1_CTRL_REG__CI__VI = 0xF02E; -constexpr unsigned int mmCGTS_CU7_TA_CTRL_REG__CI__VI = 0xF02D; -constexpr unsigned int mmCGTS_CU7_TD_TCP_CTRL_REG__CI__VI = 0xF02F; -constexpr unsigned int mmCGTS_CU8_LDS_SQ_CTRL_REG__CI__VI = 0xF031; -constexpr unsigned int mmCGTS_CU8_SP0_CTRL_REG__CI__VI = 0xF030; -constexpr unsigned int mmCGTS_CU8_SP1_CTRL_REG__CI__VI = 0xF033; -constexpr unsigned int mmCGTS_CU8_TA_SQC_CTRL_REG__CI__VI = 0xF032; -constexpr unsigned int mmCGTS_CU8_TD_TCP_CTRL_REG__CI__VI = 0xF034; -constexpr unsigned int mmCGTS_CU9_LDS_SQ_CTRL_REG__CI__VI = 0xF036; -constexpr unsigned int mmCGTS_CU9_SP0_CTRL_REG__CI__VI = 0xF035; -constexpr unsigned int mmCGTS_CU9_SP1_CTRL_REG__CI__VI = 0xF038; -constexpr unsigned int mmCGTS_CU9_TA_CTRL_REG__CI__VI = 0xF037; -constexpr unsigned int mmCGTS_CU9_TD_TCP_CTRL_REG__CI__VI = 0xF039; -constexpr unsigned int mmCGTS_RD_CTRL_REG__CI__VI = 0xF001; -constexpr unsigned int mmCGTS_RD_CTRL_REG__SI = 0x2455; -constexpr unsigned int mmCGTS_RD_REG__CI__VI = 0xF002; -constexpr unsigned int mmCGTS_RD_REG__SI = 0x2456; -constexpr unsigned int mmCGTS_SM_CTRL_REG__CI__VI = 0xF000; -constexpr unsigned int mmCGTS_SM_CTRL_REG__SI = 0x2454; -constexpr unsigned int mmCGTS_TCC_DISABLE__CI__VI = 0xF003; -constexpr unsigned int mmCGTS_TCC_DISABLE__SI = 0x2452; -constexpr unsigned int mmCGTS_USER_TCC_DISABLE__CI__VI = 0xF004; -constexpr unsigned int mmCGTS_USER_TCC_DISABLE__SI = 0x2453; -constexpr unsigned int mmCGTT_BCI_CLK_CTRL__CI__VI = 0xF082; -constexpr unsigned int mmCGTT_BCI_CLK_CTRL__SI = 0x24A9; -constexpr unsigned int mmCGTT_CPC_CLK_CTRL__CI__VI = 0xF0B2; -constexpr unsigned int mmCGTT_CPF_CLK_CTRL__CI__VI = 0xF0B1; -constexpr unsigned int mmCGTT_CP_CLK_CTRL__CI__VI = 0xF0B0; -constexpr unsigned int mmCGTT_CP_CLK_CTRL__SI = 0x3059; -constexpr unsigned int mmCGTT_GDS_CLK_CTRL__CI__VI = 0xF0A0; -constexpr unsigned int mmCGTT_GDS_CLK_CTRL__SI = 0x25DD; -constexpr unsigned int mmCGTT_IA_CLK_CTRL__CI__VI = 0xF085; -constexpr unsigned int mmCGTT_IA_CLK_CTRL__SI = 0x2261; -constexpr unsigned int mmCGTT_PA_CLK_CTRL__CI__VI = 0xF088; -constexpr unsigned int mmCGTT_PA_CLK_CTRL__SI = 0x2286; -constexpr unsigned int mmCGTT_PC_CLK_CTRL__CI__VI = 0xF081; -constexpr unsigned int mmCGTT_PC_CLK_CTRL__SI = 0x24A8; -constexpr unsigned int mmCGTT_RLC_CLK_CTRL__CI__VI = 0xF0B8; -constexpr unsigned int mmCGTT_RLC_CLK_CTRL__SI = 0x30E0; -constexpr unsigned int mmCGTT_ROM_CLK_CTRL0__SI = 0x0583; -constexpr unsigned int mmCGTT_SC_CLK_CTRL__CI__VI = 0xF089; -constexpr unsigned int mmCGTT_SC_CLK_CTRL__SI = 0x22CA; -constexpr unsigned int mmCGTT_SPI_CLK_CTRL__CI__VI = 0xF080; -constexpr unsigned int mmCGTT_SPI_CLK_CTRL__SI = 0x2451; -constexpr unsigned int mmCGTT_SQG_CLK_CTRL__CI__VI = 0xF08D; -constexpr unsigned int mmCGTT_SQG_CLK_CTRL__SI = 0x2363; -constexpr unsigned int mmCGTT_SQ_CLK_CTRL__CI__VI = 0xF08C; -constexpr unsigned int mmCGTT_SQ_CLK_CTRL__SI = 0x2362; -constexpr unsigned int mmCGTT_SX_CLK_CTRL0__CI__VI = 0xF094; -constexpr unsigned int mmCGTT_SX_CLK_CTRL0__SI = 0x240C; -constexpr unsigned int mmCGTT_SX_CLK_CTRL1__CI__VI = 0xF095; -constexpr unsigned int mmCGTT_SX_CLK_CTRL1__SI = 0x240D; -constexpr unsigned int mmCGTT_SX_CLK_CTRL2__CI__VI = 0xF096; -constexpr unsigned int mmCGTT_SX_CLK_CTRL2__SI = 0x240E; -constexpr unsigned int mmCGTT_SX_CLK_CTRL3__CI__VI = 0xF097; -constexpr unsigned int mmCGTT_SX_CLK_CTRL3__SI = 0x240F; -constexpr unsigned int mmCGTT_SX_CLK_CTRL4__CI__VI = 0xF098; -constexpr unsigned int mmCGTT_SX_CLK_CTRL4__SI = 0x2410; -constexpr unsigned int mmCGTT_TCI_CLK_CTRL__CI__VI = 0xF09F; -constexpr unsigned int mmCGTT_TCI_CLK_CTRL__SI = 0x2B60; -constexpr unsigned int mmCGTT_TCP_CLK_CTRL__CI__VI = 0xF09E; -constexpr unsigned int mmCGTT_TCP_CLK_CTRL__SI = 0x2B15; -constexpr unsigned int mmCGTT_VGT_CLK_CTRL__CI__VI = 0xF084; -constexpr unsigned int mmCGTT_VGT_CLK_CTRL__SI = 0x225F; -constexpr unsigned int mmCGTT_WD_CLK_CTRL__CI__VI = 0xF086; -constexpr unsigned int mmCG_CLKPIN_CNTL__SI = 0x0198; -constexpr unsigned int mmCG_DISPLAY_GAP_CNTL__SI = 0x020A; -constexpr unsigned int mmCG_FDO_CTRL0__SI = 0x01D5; -constexpr unsigned int mmCG_FDO_CTRL1__SI = 0x01D6; -constexpr unsigned int mmCG_FDO_CTRL2__SI = 0x01D7; -constexpr unsigned int mmCG_FPS_CNT__CI = 0x0194; -constexpr unsigned int mmCG_FREQ_TRAN_VOTING__SI = 0x01EF; -constexpr unsigned int mmCG_MULT_THERMAL_CTRL__SI = 0x01C4; -constexpr unsigned int mmCG_MULT_THERMAL_STATUS__SI = 0x01C5; -constexpr unsigned int mmCG_SPLL_FUNC_CNTL_2__SI = 0x0181; -constexpr unsigned int mmCG_SPLL_FUNC_CNTL_3__SI = 0x0182; -constexpr unsigned int mmCG_SPLL_FUNC_CNTL_4__SI = 0x0183; -constexpr unsigned int mmCG_SPLL_FUNC_CNTL_5__SI = 0x0184; -constexpr unsigned int mmCG_SPLL_FUNC_CNTL__SI = 0x0180; -constexpr unsigned int mmCG_SPLL_SPREAD_SPECTRUM_2__SI = 0x0189; -constexpr unsigned int mmCG_SPLL_SPREAD_SPECTRUM__SI = 0x0188; -constexpr unsigned int mmCG_STATIC_SCREEN_PARAMETER__SI = 0x0203; -constexpr unsigned int mmCG_TACH_CTRL__SI = 0x01DC; -constexpr unsigned int mmCG_TACH_STATUS__SI = 0x01DD; -constexpr unsigned int mmCG_THERMAL_CTRL__SI = 0x01C0; -constexpr unsigned int mmCG_THERMAL_INT__SI = 0x01C2; -constexpr unsigned int mmCG_THERMAL_STATUS__SI = 0x01C1; -constexpr unsigned int mmCG_ULV_PARAMETER__SI = 0x021F; -constexpr unsigned int mmCHUB_ATC_PERFCOUNTER0_CFG__CI__VI = 0x07D8; -constexpr unsigned int mmCHUB_ATC_PERFCOUNTER1_CFG__CI__VI = 0x07D9; -constexpr unsigned int mmCHUB_ATC_PERFCOUNTER_HI__CI__VI = 0x07D7; -constexpr unsigned int mmCHUB_ATC_PERFCOUNTER_LO__CI__VI = 0x07D6; -constexpr unsigned int mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL__CI__VI = 0x07DA; -constexpr unsigned int mmCLKREQB_PAD_CNTL__CI__VI = 0x1521; -constexpr unsigned int mmCOHER_DEST_BASE_0 = 0xA092; -constexpr unsigned int mmCOHER_DEST_BASE_1 = 0xA093; -constexpr unsigned int mmCOHER_DEST_BASE_2 = 0xA07E; -constexpr unsigned int mmCOHER_DEST_BASE_3 = 0xA07F; -constexpr unsigned int mmCOHER_DEST_BASE_HI_0__CI__VI = 0xA07A; -constexpr unsigned int mmCOHER_DEST_BASE_HI_1__CI__VI = 0xA07B; -constexpr unsigned int mmCOHER_DEST_BASE_HI_2__CI__VI = 0xA07C; -constexpr unsigned int mmCOHER_DEST_BASE_HI_3__CI__VI = 0xA07D; -constexpr unsigned int mmCOMPUTE_DIM_X = 0x2E01; -constexpr unsigned int mmCOMPUTE_DIM_Y = 0x2E02; -constexpr unsigned int mmCOMPUTE_DIM_Z = 0x2E03; -constexpr unsigned int mmCOMPUTE_DISPATCH_INITIATOR = 0x2E00; -constexpr unsigned int mmCOMPUTE_MISC_RESERVED__CI__VI = 0x2E1F; -constexpr unsigned int mmCOMPUTE_NUM_THREAD_X = 0x2E07; -constexpr unsigned int mmCOMPUTE_NUM_THREAD_Y = 0x2E08; -constexpr unsigned int mmCOMPUTE_NUM_THREAD_Z = 0x2E09; -constexpr unsigned int mmCOMPUTE_PERFCOUNT_ENABLE__CI__VI = 0x2E0B; -constexpr unsigned int mmCOMPUTE_PGM_HI = 0x2E0D; -constexpr unsigned int mmCOMPUTE_PGM_LO = 0x2E0C; -constexpr unsigned int mmCOMPUTE_PGM_RSRC1 = 0x2E12; -constexpr unsigned int mmCOMPUTE_PGM_RSRC2 = 0x2E13; -constexpr unsigned int mmCOMPUTE_PIPELINESTAT_ENABLE__CI__VI = 0x2E0A; -constexpr unsigned int mmCOMPUTE_RESOURCE_LIMITS = 0x2E15; -constexpr unsigned int mmCOMPUTE_RESTART_X__CI__VI = 0x2E1B; -constexpr unsigned int mmCOMPUTE_RESTART_Y__CI__VI = 0x2E1C; -constexpr unsigned int mmCOMPUTE_RESTART_Z__CI__VI = 0x2E1D; -constexpr unsigned int mmCOMPUTE_START_X = 0x2E04; -constexpr unsigned int mmCOMPUTE_START_Y = 0x2E05; -constexpr unsigned int mmCOMPUTE_START_Z = 0x2E06; -constexpr unsigned int mmCOMPUTE_STATIC_THREAD_MGMT_SE0 = 0x2E16; -constexpr unsigned int mmCOMPUTE_STATIC_THREAD_MGMT_SE1 = 0x2E17; -constexpr unsigned int mmCOMPUTE_STATIC_THREAD_MGMT_SE2__CI__VI = 0x2E19; -constexpr unsigned int mmCOMPUTE_STATIC_THREAD_MGMT_SE3__CI__VI = 0x2E1A; -constexpr unsigned int mmCOMPUTE_TBA_HI = 0x2E0F; -constexpr unsigned int mmCOMPUTE_TBA_LO = 0x2E0E; -constexpr unsigned int mmCOMPUTE_THREAD_TRACE_ENABLE__CI__VI = 0x2E1E; -constexpr unsigned int mmCOMPUTE_TMA_HI = 0x2E11; -constexpr unsigned int mmCOMPUTE_TMA_LO = 0x2E10; -constexpr unsigned int mmCOMPUTE_TMPRING_SIZE = 0x2E18; -constexpr unsigned int mmCOMPUTE_USER_DATA_0 = 0x2E40; -constexpr unsigned int mmCOMPUTE_USER_DATA_1 = 0x2E41; -constexpr unsigned int mmCOMPUTE_USER_DATA_10 = 0x2E4A; -constexpr unsigned int mmCOMPUTE_USER_DATA_11 = 0x2E4B; -constexpr unsigned int mmCOMPUTE_USER_DATA_12 = 0x2E4C; -constexpr unsigned int mmCOMPUTE_USER_DATA_13 = 0x2E4D; -constexpr unsigned int mmCOMPUTE_USER_DATA_14 = 0x2E4E; -constexpr unsigned int mmCOMPUTE_USER_DATA_15 = 0x2E4F; -constexpr unsigned int mmCOMPUTE_USER_DATA_2 = 0x2E42; -constexpr unsigned int mmCOMPUTE_USER_DATA_3 = 0x2E43; -constexpr unsigned int mmCOMPUTE_USER_DATA_4 = 0x2E44; -constexpr unsigned int mmCOMPUTE_USER_DATA_5 = 0x2E45; -constexpr unsigned int mmCOMPUTE_USER_DATA_6 = 0x2E46; -constexpr unsigned int mmCOMPUTE_USER_DATA_7 = 0x2E47; -constexpr unsigned int mmCOMPUTE_USER_DATA_8 = 0x2E48; -constexpr unsigned int mmCOMPUTE_USER_DATA_9 = 0x2E49; -constexpr unsigned int mmCOMPUTE_VMID = 0x2E14; -constexpr unsigned int mmCONFIG_APER_SIZE = 0x150C; -constexpr unsigned int mmCONFIG_CNTL = 0x1509; -constexpr unsigned int mmCONFIG_F0_BASE = 0x150B; -constexpr unsigned int mmCONFIG_MEMSIZE = 0x150A; -constexpr unsigned int mmCONFIG_REG_APER_SIZE = 0x150D; -constexpr unsigned int mmCPC1_CONFIG__CI = 0x0F97; -constexpr unsigned int mmCPC2_CONFIG__CI = 0x0F98; -constexpr unsigned int mmCPC_INT_CNTL__CI__VI = 0x30B4; -constexpr unsigned int mmCPC_INT_CNTX_ID__CI__VI = 0x30B7; -constexpr unsigned int mmCPC_INT_STATUS__CI__VI = 0x30B5; -constexpr unsigned int mmCPC_PERFCOUNTER0_HI__CI__VI = 0xD007; -constexpr unsigned int mmCPC_PERFCOUNTER0_LO__CI__VI = 0xD006; -constexpr unsigned int mmCPC_PERFCOUNTER0_SELECT1__CI__VI = 0xD804; -constexpr unsigned int mmCPC_PERFCOUNTER0_SELECT__CI__VI = 0xD809; -constexpr unsigned int mmCPC_PERFCOUNTER1_HI__CI__VI = 0xD005; -constexpr unsigned int mmCPC_PERFCOUNTER1_LO__CI__VI = 0xD004; -constexpr unsigned int mmCPC_PERFCOUNTER1_SELECT__CI__VI = 0xD803; -constexpr unsigned int mmCPF_PERFCOUNTER0_HI__CI__VI = 0xD00B; -constexpr unsigned int mmCPF_PERFCOUNTER0_LO__CI__VI = 0xD00A; -constexpr unsigned int mmCPF_PERFCOUNTER0_SELECT1__CI__VI = 0xD806; -constexpr unsigned int mmCPF_PERFCOUNTER0_SELECT__CI__VI = 0xD807; -constexpr unsigned int mmCPF_PERFCOUNTER1_HI__CI__VI = 0xD009; -constexpr unsigned int mmCPF_PERFCOUNTER1_LO__CI__VI = 0xD008; -constexpr unsigned int mmCPF_PERFCOUNTER1_SELECT__CI__VI = 0xD805; -constexpr unsigned int mmCPG_CONFIG__CI = 0x0F96; -constexpr unsigned int mmCPG_PERFCOUNTER0_HI__CI__VI = 0xD003; -constexpr unsigned int mmCPG_PERFCOUNTER0_LO__CI__VI = 0xD002; -constexpr unsigned int mmCPG_PERFCOUNTER0_SELECT1__CI__VI = 0xD801; -constexpr unsigned int mmCPG_PERFCOUNTER0_SELECT__CI__VI = 0xD802; -constexpr unsigned int mmCPG_PERFCOUNTER1_HI__CI__VI = 0xD001; -constexpr unsigned int mmCPG_PERFCOUNTER1_LO__CI__VI = 0xD000; -constexpr unsigned int mmCPG_PERFCOUNTER1_SELECT__CI__VI = 0xD800; -constexpr unsigned int mmCP_APPEND_ADDR_HI__CI__VI = 0xC059; -constexpr unsigned int mmCP_APPEND_ADDR_HI__SI = 0x2159; -constexpr unsigned int mmCP_APPEND_ADDR_LO__CI__VI = 0xC058; -constexpr unsigned int mmCP_APPEND_ADDR_LO__SI = 0x2158; -constexpr unsigned int mmCP_APPEND_DATA__CI__VI = 0xC05A; -constexpr unsigned int mmCP_APPEND_DATA__SI = 0x215A; -constexpr unsigned int mmCP_APPEND_LAST_CS_FENCE__CI__VI = 0xC05B; -constexpr unsigned int mmCP_APPEND_LAST_CS_FENCE__SI = 0x215B; -constexpr unsigned int mmCP_APPEND_LAST_PS_FENCE__CI__VI = 0xC05C; -constexpr unsigned int mmCP_APPEND_LAST_PS_FENCE__SI = 0x215C; -constexpr unsigned int mmCP_ATOMIC_PREOP_HI__CI__VI = 0xC05E; -constexpr unsigned int mmCP_ATOMIC_PREOP_HI__SI = 0x215E; -constexpr unsigned int mmCP_ATOMIC_PREOP_LO__CI__VI = 0xC05D; -constexpr unsigned int mmCP_ATOMIC_PREOP_LO__SI = 0x215D; -constexpr unsigned int mmCP_BUSY_STAT = 0x219F; -constexpr unsigned int mmCP_CEQ1_AVAIL = 0x21E6; -constexpr unsigned int mmCP_CEQ2_AVAIL = 0x21E7; -constexpr unsigned int mmCP_CE_COMPARE_COUNT__CI__VI = 0x20C0; -constexpr unsigned int mmCP_CE_COUNTER__CI__VI = 0xC09A; -constexpr unsigned int mmCP_CE_DE_COUNT__CI__VI = 0x20C1; -constexpr unsigned int mmCP_CE_HEADER_DUMP = 0x21A4; -constexpr unsigned int mmCP_CE_IB1_BASE_HI__CI__VI = 0xC0C7; -constexpr unsigned int mmCP_CE_IB1_BASE_HI__SI = 0x21C7; -constexpr unsigned int mmCP_CE_IB1_BASE_LO__CI__VI = 0xC0C6; -constexpr unsigned int mmCP_CE_IB1_BASE_LO__SI = 0x21C6; -constexpr unsigned int mmCP_CE_IB1_BUFSZ__CI__VI = 0xC0C8; -constexpr unsigned int mmCP_CE_IB1_BUFSZ__SI = 0x21C8; -constexpr unsigned int mmCP_CE_IB1_OFFSET__CI__VI = 0xC098; -constexpr unsigned int mmCP_CE_IB2_BASE_HI__CI__VI = 0xC0CA; -constexpr unsigned int mmCP_CE_IB2_BASE_HI__SI = 0x21CA; -constexpr unsigned int mmCP_CE_IB2_BASE_LO__CI__VI = 0xC0C9; -constexpr unsigned int mmCP_CE_IB2_BASE_LO__SI = 0x21C9; -constexpr unsigned int mmCP_CE_IB2_BUFSZ__CI__VI = 0xC0CB; -constexpr unsigned int mmCP_CE_IB2_BUFSZ__SI = 0x21CB; -constexpr unsigned int mmCP_CE_IB2_OFFSET__CI__VI = 0xC099; -constexpr unsigned int mmCP_CE_INIT_BASE_HI__CI__VI = 0xC0C4; -constexpr unsigned int mmCP_CE_INIT_BASE_HI__SI = 0x21C4; -constexpr unsigned int mmCP_CE_INIT_BASE_LO__CI__VI = 0xC0C3; -constexpr unsigned int mmCP_CE_INIT_BASE_LO__SI = 0x21C3; -constexpr unsigned int mmCP_CE_INIT_BUFSZ__CI__VI = 0xC0C5; -constexpr unsigned int mmCP_CE_INIT_BUFSZ__SI = 0x21C5; -constexpr unsigned int mmCP_CE_INTR_ROUTINE_START__CI__VI = 0x30A8; -constexpr unsigned int mmCP_CE_PRGRM_CNTR_START__CI__VI = 0x30A3; -constexpr unsigned int mmCP_CE_ROQ_IB1_STAT = 0x21E9; -constexpr unsigned int mmCP_CE_ROQ_IB2_STAT = 0x21EA; -constexpr unsigned int mmCP_CE_ROQ_RB_STAT = 0x21E8; -constexpr unsigned int mmCP_CMD_DATA = 0x21DF; -constexpr unsigned int mmCP_CMD_INDEX = 0x21DE; -constexpr unsigned int mmCP_CNTX_STAT = 0x21B8; -constexpr unsigned int mmCP_COHER_BASE_HI__CI__VI = 0xC079; -constexpr unsigned int mmCP_COHER_BASE__CI__VI = 0xC07E; -constexpr unsigned int mmCP_COHER_BASE__SI = 0x217E; -constexpr unsigned int mmCP_COHER_CNTL__CI__VI = 0xC07C; -constexpr unsigned int mmCP_COHER_CNTL__SI = 0x217C; -constexpr unsigned int mmCP_COHER_SIZE_HI__CI__VI = 0xC08C; -constexpr unsigned int mmCP_COHER_SIZE__CI__VI = 0xC07D; -constexpr unsigned int mmCP_COHER_SIZE__SI = 0x217D; -constexpr unsigned int mmCP_COHER_START_DELAY__CI__VI = 0xC07B; -constexpr unsigned int mmCP_COHER_START_DELAY__SI = 0x217B; -constexpr unsigned int mmCP_COHER_STATUS__CI__VI = 0xC07F; -constexpr unsigned int mmCP_COHER_STATUS__SI = 0x217F; -constexpr unsigned int mmCP_CONFIG__SI = 0x0F92; -constexpr unsigned int mmCP_CONTEXT_CNTL__CI__VI = 0x30AD; -constexpr unsigned int mmCP_CPC_BUSY_STAT__CI__VI = 0x2085; -constexpr unsigned int mmCP_CPC_GRBM_FREE_COUNT__CI__VI = 0x208B; -constexpr unsigned int mmCP_CPC_HALT_HYST_COUNT__CI__VI = 0x20A7; -constexpr unsigned int mmCP_CPC_MC_CNTL__CI = 0x208A; -constexpr unsigned int mmCP_CPC_SCRATCH_DATA__CI__VI = 0x2091; -constexpr unsigned int mmCP_CPC_SCRATCH_INDEX__CI__VI = 0x2090; -constexpr unsigned int mmCP_CPC_STALLED_STAT1__CI__VI = 0x2086; -constexpr unsigned int mmCP_CPC_STATUS__CI__VI = 0x2084; -constexpr unsigned int mmCP_CPF_BUSY_STAT__CI__VI = 0x2088; -constexpr unsigned int mmCP_CPF_STALLED_STAT1__CI__VI = 0x2089; -constexpr unsigned int mmCP_CPF_STATUS__CI__VI = 0x2087; -constexpr unsigned int mmCP_CSF_CNTL = 0x21B5; -constexpr unsigned int mmCP_CSF_STAT = 0x21B4; -constexpr unsigned int mmCP_DEBUG = 0x307F; -constexpr unsigned int mmCP_DEVICE_ID__CI__VI = 0x304B; -constexpr unsigned int mmCP_DE_CE_COUNT__CI__VI = 0x20C2; -constexpr unsigned int mmCP_DE_DE_COUNT__CI__VI = 0x20C4; -constexpr unsigned int mmCP_DE_LAST_INVAL_COUNT__CI__VI = 0x20C3; -constexpr unsigned int mmCP_DFY_ADDR_HI__CI__VI = 0x3022; -constexpr unsigned int mmCP_DFY_ADDR_LO__CI__VI = 0x3023; -constexpr unsigned int mmCP_DFY_CNTL__CI__VI = 0x3020; -constexpr unsigned int mmCP_DFY_DATA_0__CI__VI = 0x3024; -constexpr unsigned int mmCP_DFY_DATA_10__CI__VI = 0x302E; -constexpr unsigned int mmCP_DFY_DATA_11__CI__VI = 0x302F; -constexpr unsigned int mmCP_DFY_DATA_12__CI__VI = 0x3030; -constexpr unsigned int mmCP_DFY_DATA_13__CI__VI = 0x3031; -constexpr unsigned int mmCP_DFY_DATA_14__CI__VI = 0x3032; -constexpr unsigned int mmCP_DFY_DATA_15__CI__VI = 0x3033; -constexpr unsigned int mmCP_DFY_DATA_1__CI__VI = 0x3025; -constexpr unsigned int mmCP_DFY_DATA_2__CI__VI = 0x3026; -constexpr unsigned int mmCP_DFY_DATA_3__CI__VI = 0x3027; -constexpr unsigned int mmCP_DFY_DATA_4__CI__VI = 0x3028; -constexpr unsigned int mmCP_DFY_DATA_5__CI__VI = 0x3029; -constexpr unsigned int mmCP_DFY_DATA_6__CI__VI = 0x302A; -constexpr unsigned int mmCP_DFY_DATA_7__CI__VI = 0x302B; -constexpr unsigned int mmCP_DFY_DATA_8__CI__VI = 0x302C; -constexpr unsigned int mmCP_DFY_DATA_9__CI__VI = 0x302D; -constexpr unsigned int mmCP_DFY_STAT__CI__VI = 0x3021; -constexpr unsigned int mmCP_DMA_CNTL__CI__VI = 0xC08A; -constexpr unsigned int mmCP_DMA_CNTL__SI = 0x218A; -constexpr unsigned int mmCP_DMA_ME_COMMAND__CI__VI = 0xC084; -constexpr unsigned int mmCP_DMA_ME_COMMAND__SI = 0x2184; -constexpr unsigned int mmCP_DMA_ME_CONTROL__CI__VI = 0xC078; -constexpr unsigned int mmCP_DMA_ME_DST_ADDR_HI__CI__VI = 0xC083; -constexpr unsigned int mmCP_DMA_ME_DST_ADDR_HI__SI = 0x2183; -constexpr unsigned int mmCP_DMA_ME_DST_ADDR__CI__VI = 0xC082; -constexpr unsigned int mmCP_DMA_ME_DST_ADDR__SI = 0x2182; -constexpr unsigned int mmCP_DMA_ME_SRC_ADDR_HI__CI__VI = 0xC081; -constexpr unsigned int mmCP_DMA_ME_SRC_ADDR_HI__SI = 0x2181; -constexpr unsigned int mmCP_DMA_ME_SRC_ADDR__CI__VI = 0xC080; -constexpr unsigned int mmCP_DMA_ME_SRC_ADDR__SI = 0x2180; -constexpr unsigned int mmCP_DMA_PFP_COMMAND__CI__VI = 0xC089; -constexpr unsigned int mmCP_DMA_PFP_COMMAND__SI = 0x2189; -constexpr unsigned int mmCP_DMA_PFP_CONTROL__CI__VI = 0xC077; -constexpr unsigned int mmCP_DMA_PFP_DST_ADDR_HI__CI__VI = 0xC088; -constexpr unsigned int mmCP_DMA_PFP_DST_ADDR_HI__SI = 0x2188; -constexpr unsigned int mmCP_DMA_PFP_DST_ADDR__CI__VI = 0xC087; -constexpr unsigned int mmCP_DMA_PFP_DST_ADDR__SI = 0x2187; -constexpr unsigned int mmCP_DMA_PFP_SRC_ADDR_HI__CI__VI = 0xC086; -constexpr unsigned int mmCP_DMA_PFP_SRC_ADDR_HI__SI = 0x2186; -constexpr unsigned int mmCP_DMA_PFP_SRC_ADDR__CI__VI = 0xC085; -constexpr unsigned int mmCP_DMA_PFP_SRC_ADDR__SI = 0x2185; -constexpr unsigned int mmCP_DMA_READ_TAGS__CI__VI = 0xC08B; -constexpr unsigned int mmCP_DMA_READ_TAGS__SI = 0x218B; -constexpr unsigned int mmCP_ECC_FIRSTOCCURRENCE = 0x307A; -constexpr unsigned int mmCP_ECC_FIRSTOCCURRENCE_RING0 = 0x307B; -constexpr unsigned int mmCP_ECC_FIRSTOCCURRENCE_RING1 = 0x307C; -constexpr unsigned int mmCP_ECC_FIRSTOCCURRENCE_RING2 = 0x307D; -constexpr unsigned int mmCP_ENDIAN_SWAP__CI__VI = 0x3050; -constexpr unsigned int mmCP_EOP_DONE_ADDR_HI__CI__VI = 0xC001; -constexpr unsigned int mmCP_EOP_DONE_ADDR_HI__SI = 0x2101; -constexpr unsigned int mmCP_EOP_DONE_ADDR_LO__CI__VI = 0xC000; -constexpr unsigned int mmCP_EOP_DONE_ADDR_LO__SI = 0x2100; -constexpr unsigned int mmCP_EOP_DONE_DATA_CNTL__CI__VI = 0xC0D6; -constexpr unsigned int mmCP_EOP_DONE_DATA_HI__CI__VI = 0xC003; -constexpr unsigned int mmCP_EOP_DONE_DATA_HI__SI = 0x2103; -constexpr unsigned int mmCP_EOP_DONE_DATA_LO__CI__VI = 0xC002; -constexpr unsigned int mmCP_EOP_DONE_DATA_LO__SI = 0x2102; -constexpr unsigned int mmCP_EOP_DONE_EVENT_CNTL__CI__VI = 0xC0D5; -constexpr unsigned int mmCP_EOP_LAST_FENCE_HI__CI__VI = 0xC005; -constexpr unsigned int mmCP_EOP_LAST_FENCE_HI__SI = 0x2105; -constexpr unsigned int mmCP_EOP_LAST_FENCE_LO__CI__VI = 0xC004; -constexpr unsigned int mmCP_EOP_LAST_FENCE_LO__SI = 0x2104; -constexpr unsigned int mmCP_FETCHER_SOURCE__CI = 0x3082; -constexpr unsigned int mmCP_GDS_ATOMIC0_PREOP_HI__CI__VI = 0xC060; -constexpr unsigned int mmCP_GDS_ATOMIC0_PREOP_HI__SI = 0x2160; -constexpr unsigned int mmCP_GDS_ATOMIC0_PREOP_LO__CI__VI = 0xC05F; -constexpr unsigned int mmCP_GDS_ATOMIC0_PREOP_LO__SI = 0x215F; -constexpr unsigned int mmCP_GDS_ATOMIC1_PREOP_HI__CI__VI = 0xC062; -constexpr unsigned int mmCP_GDS_ATOMIC1_PREOP_HI__SI = 0x2162; -constexpr unsigned int mmCP_GDS_ATOMIC1_PREOP_LO__CI__VI = 0xC061; -constexpr unsigned int mmCP_GDS_ATOMIC1_PREOP_LO__SI = 0x2161; -constexpr unsigned int mmCP_GRBM_FREE_COUNT = 0x21A3; -constexpr unsigned int mmCP_HPD_EOP_BASE_ADDR_HI__CI = 0x3242; -constexpr unsigned int mmCP_HPD_EOP_BASE_ADDR__CI = 0x3241; -constexpr unsigned int mmCP_HPD_EOP_CONTROL__CI = 0x3244; -constexpr unsigned int mmCP_HPD_EOP_VMID__CI = 0x3243; -constexpr unsigned int mmCP_HPD_ROQ_OFFSETS__CI__VI = 0x3240; -constexpr unsigned int mmCP_HQD_ACTIVE__CI__VI = 0x3247; -constexpr unsigned int mmCP_HQD_ATOMIC0_PREOP_HI__CI__VI = 0x3262; -constexpr unsigned int mmCP_HQD_ATOMIC0_PREOP_LO__CI__VI = 0x3261; -constexpr unsigned int mmCP_HQD_ATOMIC1_PREOP_HI__CI__VI = 0x3264; -constexpr unsigned int mmCP_HQD_ATOMIC1_PREOP_LO__CI__VI = 0x3263; -constexpr unsigned int mmCP_HQD_DEQUEUE_REQUEST__CI__VI = 0x325D; -constexpr unsigned int mmCP_HQD_DMA_OFFLOAD__CI__VI = 0x325E; -constexpr unsigned int mmCP_HQD_HQ_SCHEDULER0__CI__VI = 0x3265; -constexpr unsigned int mmCP_HQD_HQ_SCHEDULER1__CI__VI = 0x3266; -constexpr unsigned int mmCP_HQD_IB_BASE_ADDR_HI__CI__VI = 0x3258; -constexpr unsigned int mmCP_HQD_IB_BASE_ADDR__CI__VI = 0x3257; -constexpr unsigned int mmCP_HQD_IB_CONTROL__CI__VI = 0x325A; -constexpr unsigned int mmCP_HQD_IB_RPTR__CI__VI = 0x3259; -constexpr unsigned int mmCP_HQD_IQ_RPTR__CI__VI = 0x325C; -constexpr unsigned int mmCP_HQD_IQ_TIMER__CI__VI = 0x325B; -constexpr unsigned int mmCP_HQD_MSG_TYPE__CI__VI = 0x3260; -constexpr unsigned int mmCP_HQD_PERSISTENT_STATE__CI__VI = 0x3249; -constexpr unsigned int mmCP_HQD_PIPE_PRIORITY__CI__VI = 0x324A; -constexpr unsigned int mmCP_HQD_PQ_BASE_HI__CI__VI = 0x324E; -constexpr unsigned int mmCP_HQD_PQ_BASE__CI__VI = 0x324D; -constexpr unsigned int mmCP_HQD_PQ_CONTROL__CI__VI = 0x3256; -constexpr unsigned int mmCP_HQD_PQ_DOORBELL_CONTROL__CI__VI = 0x3254; -constexpr unsigned int mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI__CI__VI = 0x3251; -constexpr unsigned int mmCP_HQD_PQ_RPTR_REPORT_ADDR__CI__VI = 0x3250; -constexpr unsigned int mmCP_HQD_PQ_RPTR__CI__VI = 0x324F; -constexpr unsigned int mmCP_HQD_PQ_WPTR_POLL_ADDR_HI__CI__VI = 0x3253; -constexpr unsigned int mmCP_HQD_PQ_WPTR_POLL_ADDR__CI__VI = 0x3252; -constexpr unsigned int mmCP_HQD_PQ_WPTR__CI__VI = 0x3255; -constexpr unsigned int mmCP_HQD_QUANTUM__CI__VI = 0x324C; -constexpr unsigned int mmCP_HQD_QUEUE_PRIORITY__CI__VI = 0x324B; -constexpr unsigned int mmCP_HQD_SEMA_CMD__CI__VI = 0x325F; -constexpr unsigned int mmCP_HQD_VMID__CI__VI = 0x3248; -constexpr unsigned int mmCP_IB1_BASE_HI__CI__VI = 0xC0CD; -constexpr unsigned int mmCP_IB1_BASE_HI__SI = 0x21CD; -constexpr unsigned int mmCP_IB1_BASE_LO__CI__VI = 0xC0CC; -constexpr unsigned int mmCP_IB1_BASE_LO__SI = 0x21CC; -constexpr unsigned int mmCP_IB1_BUFSZ__CI__VI = 0xC0CE; -constexpr unsigned int mmCP_IB1_BUFSZ__SI = 0x21CE; -constexpr unsigned int mmCP_IB1_OFFSET__CI__VI = 0xC092; -constexpr unsigned int mmCP_IB1_OFFSET__SI = 0x2192; -constexpr unsigned int mmCP_IB1_PREAMBLE_BEGIN__CI__VI = 0xC094; -constexpr unsigned int mmCP_IB1_PREAMBLE_BEGIN__SI = 0x2194; -constexpr unsigned int mmCP_IB1_PREAMBLE_END__CI__VI = 0xC095; -constexpr unsigned int mmCP_IB1_PREAMBLE_END__SI = 0x2195; -constexpr unsigned int mmCP_IB2_BASE_HI__CI__VI = 0xC0D0; -constexpr unsigned int mmCP_IB2_BASE_HI__SI = 0x21D0; -constexpr unsigned int mmCP_IB2_BASE_LO__CI__VI = 0xC0CF; -constexpr unsigned int mmCP_IB2_BASE_LO__SI = 0x21CF; -constexpr unsigned int mmCP_IB2_BUFSZ__CI__VI = 0xC0D1; -constexpr unsigned int mmCP_IB2_BUFSZ__SI = 0x21D1; -constexpr unsigned int mmCP_IB2_OFFSET__CI__VI = 0xC093; -constexpr unsigned int mmCP_IB2_OFFSET__SI = 0x2193; -constexpr unsigned int mmCP_IB2_PREAMBLE_BEGIN__CI__VI = 0xC096; -constexpr unsigned int mmCP_IB2_PREAMBLE_BEGIN__SI = 0x2196; -constexpr unsigned int mmCP_IB2_PREAMBLE_END__CI__VI = 0xC097; -constexpr unsigned int mmCP_IB2_PREAMBLE_END__SI = 0x2197; -constexpr unsigned int mmCP_INT_CNTL = 0x3049; -constexpr unsigned int mmCP_INT_CNTL_RING0 = 0x306A; -constexpr unsigned int mmCP_INT_CNTL_RING1 = 0x306B; -constexpr unsigned int mmCP_INT_CNTL_RING2 = 0x306C; -constexpr unsigned int mmCP_INT_STATUS = 0x304A; -constexpr unsigned int mmCP_INT_STATUS_RING0 = 0x306D; -constexpr unsigned int mmCP_INT_STATUS_RING1 = 0x306E; -constexpr unsigned int mmCP_INT_STATUS_RING2 = 0x306F; -constexpr unsigned int mmCP_INT_STAT_DEBUG = 0x21F7; -constexpr unsigned int mmCP_IQ_WAIT_TIME1__CI__VI = 0x30AF; -constexpr unsigned int mmCP_IQ_WAIT_TIME2__CI__VI = 0x30B0; -constexpr unsigned int mmCP_MAX_CONTEXT__CI__VI = 0x30AE; -constexpr unsigned int mmCP_MC_PACK_DELAY_CNT__SI__CI = 0x21A7; -constexpr unsigned int mmCP_MC_TAG_CNTL__CI = 0x21A8; -constexpr unsigned int mmCP_MC_TAG_DATA__CI = 0x21A9; -constexpr unsigned int mmCP_ME0_PIPE0_PRIORITY__CI__VI = 0x304D; -constexpr unsigned int mmCP_ME0_PIPE0_VMID__CI__VI = 0x3052; -constexpr unsigned int mmCP_ME0_PIPE1_PRIORITY__CI__VI = 0x304E; -constexpr unsigned int mmCP_ME0_PIPE1_VMID__CI__VI = 0x3053; -constexpr unsigned int mmCP_ME0_PIPE2_PRIORITY__CI__VI = 0x304F; -constexpr unsigned int mmCP_ME0_PIPE_PRIORITY_CNTS__CI__VI = 0x304C; -constexpr unsigned int mmCP_ME1_INT_STAT_DEBUG__CI__VI = 0x3095; -constexpr unsigned int mmCP_ME1_PIPE0_INT_CNTL__CI__VI = 0x3085; -constexpr unsigned int mmCP_ME1_PIPE0_INT_STATUS__CI__VI = 0x308D; -constexpr unsigned int mmCP_ME1_PIPE0_PRIORITY__CI__VI = 0x309A; -constexpr unsigned int mmCP_ME1_PIPE1_INT_CNTL__CI__VI = 0x3086; -constexpr unsigned int mmCP_ME1_PIPE1_INT_STATUS__CI__VI = 0x308E; -constexpr unsigned int mmCP_ME1_PIPE1_PRIORITY__CI__VI = 0x309B; -constexpr unsigned int mmCP_ME1_PIPE2_INT_CNTL__CI__VI = 0x3087; -constexpr unsigned int mmCP_ME1_PIPE2_INT_STATUS__CI__VI = 0x308F; -constexpr unsigned int mmCP_ME1_PIPE2_PRIORITY__CI__VI = 0x309C; -constexpr unsigned int mmCP_ME1_PIPE3_INT_CNTL__CI__VI = 0x3088; -constexpr unsigned int mmCP_ME1_PIPE3_INT_STATUS__CI__VI = 0x3090; -constexpr unsigned int mmCP_ME1_PIPE3_PRIORITY__CI__VI = 0x309D; -constexpr unsigned int mmCP_ME1_PIPE_PRIORITY_CNTS__CI__VI = 0x3099; -constexpr unsigned int mmCP_ME2_INT_STAT_DEBUG__CI__VI = 0x3096; -constexpr unsigned int mmCP_ME2_PIPE0_INT_CNTL__CI__VI = 0x3089; -constexpr unsigned int mmCP_ME2_PIPE0_INT_STATUS__CI__VI = 0x3091; -constexpr unsigned int mmCP_ME2_PIPE0_PRIORITY__CI__VI = 0x309F; -constexpr unsigned int mmCP_ME2_PIPE1_INT_CNTL__CI__VI = 0x308A; -constexpr unsigned int mmCP_ME2_PIPE1_INT_STATUS__CI__VI = 0x3092; -constexpr unsigned int mmCP_ME2_PIPE1_PRIORITY__CI__VI = 0x30A0; -constexpr unsigned int mmCP_ME2_PIPE2_INT_CNTL__CI__VI = 0x308B; -constexpr unsigned int mmCP_ME2_PIPE2_INT_STATUS__CI__VI = 0x3093; -constexpr unsigned int mmCP_ME2_PIPE2_PRIORITY__CI__VI = 0x30A1; -constexpr unsigned int mmCP_ME2_PIPE3_INT_CNTL__CI__VI = 0x308C; -constexpr unsigned int mmCP_ME2_PIPE3_INT_STATUS__CI__VI = 0x3094; -constexpr unsigned int mmCP_ME2_PIPE3_PRIORITY__CI__VI = 0x30A2; -constexpr unsigned int mmCP_ME2_PIPE_PRIORITY_CNTS__CI__VI = 0x309E; -constexpr unsigned int mmCP_MEC1_INTR_ROUTINE_START__CI__VI = 0x30AB; -constexpr unsigned int mmCP_MEC1_PRGRM_CNTR_START__CI__VI = 0x30A6; -constexpr unsigned int mmCP_MEC2_INTR_ROUTINE_START__CI__VI = 0x30AC; -constexpr unsigned int mmCP_MEC2_PRGRM_CNTR_START__CI__VI = 0x30A7; -constexpr unsigned int mmCP_MEC_CNTL__CI__VI = 0x208D; -constexpr unsigned int mmCP_MEC_ME1_HEADER_DUMP__CI__VI = 0x208E; -constexpr unsigned int mmCP_MEC_ME1_UCODE_ADDR__CI = 0x305C; -constexpr unsigned int mmCP_MEC_ME1_UCODE_DATA__CI = 0x305D; -constexpr unsigned int mmCP_MEC_ME2_HEADER_DUMP__CI__VI = 0x208F; -constexpr unsigned int mmCP_MEC_ME2_UCODE_ADDR__CI = 0x305E; -constexpr unsigned int mmCP_MEC_ME2_UCODE_DATA__CI = 0x305F; -constexpr unsigned int mmCP_MEM_SLP_CNTL = 0x3079; -constexpr unsigned int mmCP_MEQ_AVAIL = 0x21DD; -constexpr unsigned int mmCP_MEQ_STAT = 0x21E5; -constexpr unsigned int mmCP_MEQ_STQ_THRESHOLD__CI__VI = 0x21BD; -constexpr unsigned int mmCP_MEQ_THRESHOLDS = 0x21D9; -constexpr unsigned int mmCP_ME_ATOMIC_PREOP_HI__CI__VI = 0xC05E; -constexpr unsigned int mmCP_ME_ATOMIC_PREOP_LO__CI__VI = 0xC05D; -constexpr unsigned int mmCP_ME_CNTL = 0x21B6; -constexpr unsigned int mmCP_ME_GDS_ATOMIC0_PREOP_HI__CI__VI = 0xC060; -constexpr unsigned int mmCP_ME_GDS_ATOMIC0_PREOP_LO__CI__VI = 0xC05F; -constexpr unsigned int mmCP_ME_GDS_ATOMIC1_PREOP_HI__CI__VI = 0xC062; -constexpr unsigned int mmCP_ME_GDS_ATOMIC1_PREOP_LO__CI__VI = 0xC061; -constexpr unsigned int mmCP_ME_HEADER_DUMP = 0x21A1; -constexpr unsigned int mmCP_ME_INTR_ROUTINE_START__CI__VI = 0x30AA; -constexpr unsigned int mmCP_ME_MC_RADDR_HI__CI__VI = 0xC06E; -constexpr unsigned int mmCP_ME_MC_RADDR_HI__SI = 0x216E; -constexpr unsigned int mmCP_ME_MC_RADDR_LO__CI__VI = 0xC06D; -constexpr unsigned int mmCP_ME_MC_RADDR_LO__SI = 0x216D; -constexpr unsigned int mmCP_ME_MC_WADDR_HI__CI__VI = 0xC06A; -constexpr unsigned int mmCP_ME_MC_WADDR_HI__SI = 0x216A; -constexpr unsigned int mmCP_ME_MC_WADDR_LO__CI__VI = 0xC069; -constexpr unsigned int mmCP_ME_MC_WADDR_LO__SI = 0x2169; -constexpr unsigned int mmCP_ME_MC_WDATA_HI__CI__VI = 0xC06C; -constexpr unsigned int mmCP_ME_MC_WDATA_HI__SI = 0x216C; -constexpr unsigned int mmCP_ME_MC_WDATA_LO__CI__VI = 0xC06B; -constexpr unsigned int mmCP_ME_MC_WDATA_LO__SI = 0x216B; -constexpr unsigned int mmCP_ME_PREEMPTION = 0x21B9; -constexpr unsigned int mmCP_ME_PRGRM_CNTR_START__CI__VI = 0x30A5; -constexpr unsigned int mmCP_MQD_BASE_ADDR_HI__CI__VI = 0x3246; -constexpr unsigned int mmCP_MQD_BASE_ADDR__CI__VI = 0x3245; -constexpr unsigned int mmCP_MQD_CONTROL__CI__VI = 0x3267; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT0_HI__CI__VI = 0xC00B; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT0_HI__SI = 0x210B; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT0_LO__CI__VI = 0xC00A; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT0_LO__SI = 0x210A; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT1_HI__CI__VI = 0xC00F; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT1_HI__SI = 0x210F; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT1_LO__CI__VI = 0xC00E; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT1_LO__SI = 0x210E; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT2_HI__CI__VI = 0xC013; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT2_HI__SI = 0x2113; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT2_LO__CI__VI = 0xC012; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT2_LO__SI = 0x2112; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT3_HI__CI__VI = 0xC017; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT3_HI__SI = 0x2117; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT3_LO__CI__VI = 0xC016; -constexpr unsigned int mmCP_NUM_PRIM_NEEDED_COUNT3_LO__SI = 0x2116; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT0_HI__CI__VI = 0xC009; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT0_HI__SI = 0x2109; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT0_LO__CI__VI = 0xC008; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT0_LO__SI = 0x2108; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT1_HI__CI__VI = 0xC00D; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT1_HI__SI = 0x210D; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT1_LO__CI__VI = 0xC00C; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT1_LO__SI = 0x210C; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT2_HI__CI__VI = 0xC011; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT2_HI__SI = 0x2111; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT2_LO__CI__VI = 0xC010; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT2_LO__SI = 0x2110; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT3_HI__CI__VI = 0xC015; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT3_HI__SI = 0x2115; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT3_LO__CI__VI = 0xC014; -constexpr unsigned int mmCP_NUM_PRIM_WRITTEN_COUNT3_LO__SI = 0x2114; -constexpr unsigned int mmCP_PA_CINVOC_COUNT_HI__CI__VI = 0xC029; -constexpr unsigned int mmCP_PA_CINVOC_COUNT_HI__SI = 0x2129; -constexpr unsigned int mmCP_PA_CINVOC_COUNT_LO__CI__VI = 0xC028; -constexpr unsigned int mmCP_PA_CINVOC_COUNT_LO__SI = 0x2128; -constexpr unsigned int mmCP_PA_CPRIM_COUNT_HI__CI__VI = 0xC02B; -constexpr unsigned int mmCP_PA_CPRIM_COUNT_HI__SI = 0x212B; -constexpr unsigned int mmCP_PA_CPRIM_COUNT_LO__CI__VI = 0xC02A; -constexpr unsigned int mmCP_PA_CPRIM_COUNT_LO__SI = 0x212A; -constexpr unsigned int mmCP_PERFCOUNTER_HI__SI = 0x21FE; -constexpr unsigned int mmCP_PERFCOUNTER_LO__SI = 0x21FD; -constexpr unsigned int mmCP_PERFCOUNTER_SELECT__SI = 0x21FC; -constexpr unsigned int mmCP_PERFMON_CNTL__CI__VI = 0xD808; -constexpr unsigned int mmCP_PERFMON_CNTL__SI = 0x21FF; -constexpr unsigned int mmCP_PERFMON_CNTX_CNTL = 0xA0D8; -constexpr unsigned int mmCP_PFP_ATOMIC_PREOP_HI__CI__VI = 0xC053; -constexpr unsigned int mmCP_PFP_ATOMIC_PREOP_LO__CI__VI = 0xC052; -constexpr unsigned int mmCP_PFP_GDS_ATOMIC0_PREOP_HI__CI__VI = 0xC055; -constexpr unsigned int mmCP_PFP_GDS_ATOMIC0_PREOP_LO__CI__VI = 0xC054; -constexpr unsigned int mmCP_PFP_GDS_ATOMIC1_PREOP_HI__CI__VI = 0xC057; -constexpr unsigned int mmCP_PFP_GDS_ATOMIC1_PREOP_LO__CI__VI = 0xC056; -constexpr unsigned int mmCP_PFP_HEADER_DUMP = 0x21A2; -constexpr unsigned int mmCP_PFP_IB_CONTROL__CI__VI = 0xC08D; -constexpr unsigned int mmCP_PFP_IB_CONTROL__SI = 0x218D; -constexpr unsigned int mmCP_PFP_INTR_ROUTINE_START__CI__VI = 0x30A9; -constexpr unsigned int mmCP_PFP_LOAD_CONTROL__CI__VI = 0xC08E; -constexpr unsigned int mmCP_PFP_LOAD_CONTROL__SI = 0x218E; -constexpr unsigned int mmCP_PFP_PRGRM_CNTR_START__CI__VI = 0x30A4; -constexpr unsigned int mmCP_PIPEID__CI__VI = 0xA0D9; -constexpr unsigned int mmCP_PIPE_STATS_ADDR_HI__CI__VI = 0xC019; -constexpr unsigned int mmCP_PIPE_STATS_ADDR_HI__SI = 0x2119; -constexpr unsigned int mmCP_PIPE_STATS_ADDR_LO__CI__VI = 0xC018; -constexpr unsigned int mmCP_PIPE_STATS_ADDR_LO__SI = 0x2118; -constexpr unsigned int mmCP_PQ_WPTR_POLL_CNTL1__CI__VI = 0x3084; -constexpr unsigned int mmCP_PQ_WPTR_POLL_CNTL__CI__VI = 0x3083; -constexpr unsigned int mmCP_PRT_LOD_STATS_CNTL0__CI__VI = 0x20AD; -constexpr unsigned int mmCP_PRT_LOD_STATS_CNTL1__CI__VI = 0x20AE; -constexpr unsigned int mmCP_PRT_LOD_STATS_CNTL2__CI__VI = 0x20AF; -constexpr unsigned int mmCP_PWR_CNTL = 0x3078; -constexpr unsigned int mmCP_QUEUE_THRESHOLDS = 0x21D8; -constexpr unsigned int mmCP_RB0_BASE = 0x3040; -constexpr unsigned int mmCP_RB0_BASE_HI__CI__VI = 0x30B1; -constexpr unsigned int mmCP_RB0_CNTL = 0x3041; -constexpr unsigned int mmCP_RB0_RPTR = 0x21C0; -constexpr unsigned int mmCP_RB0_RPTR_ADDR = 0x3043; -constexpr unsigned int mmCP_RB0_RPTR_ADDR_HI = 0x3044; -constexpr unsigned int mmCP_RB0_WPTR = 0x3045; -constexpr unsigned int mmCP_RB1_BASE = 0x3060; -constexpr unsigned int mmCP_RB1_BASE_HI__CI__VI = 0x30B2; -constexpr unsigned int mmCP_RB1_CNTL = 0x3061; -constexpr unsigned int mmCP_RB1_RPTR = 0x21BF; -constexpr unsigned int mmCP_RB1_RPTR_ADDR = 0x3062; -constexpr unsigned int mmCP_RB1_RPTR_ADDR_HI = 0x3063; -constexpr unsigned int mmCP_RB1_WPTR = 0x3064; -constexpr unsigned int mmCP_RB2_BASE = 0x3065; -constexpr unsigned int mmCP_RB2_CNTL = 0x3066; -constexpr unsigned int mmCP_RB2_RPTR = 0x21BE; -constexpr unsigned int mmCP_RB2_RPTR_ADDR = 0x3067; -constexpr unsigned int mmCP_RB2_RPTR_ADDR_HI = 0x3068; -constexpr unsigned int mmCP_RB2_WPTR = 0x3069; -constexpr unsigned int mmCP_RB_BASE = 0x3040; -constexpr unsigned int mmCP_RB_CNTL = 0x3041; -constexpr unsigned int mmCP_RB_OFFSET__CI__VI = 0xC091; -constexpr unsigned int mmCP_RB_OFFSET__SI = 0x2191; -constexpr unsigned int mmCP_RB_RPTR = 0x21C0; -constexpr unsigned int mmCP_RB_RPTR_ADDR = 0x3043; -constexpr unsigned int mmCP_RB_RPTR_ADDR_HI = 0x3044; -constexpr unsigned int mmCP_RB_RPTR_WR = 0x3042; -constexpr unsigned int mmCP_RB_VMID = 0x3051; -constexpr unsigned int mmCP_RB_WPTR = 0x3045; -constexpr unsigned int mmCP_RB_WPTR_DELAY = 0x21C1; -constexpr unsigned int mmCP_RB_WPTR_POLL_ADDR_HI = 0x3047; -constexpr unsigned int mmCP_RB_WPTR_POLL_ADDR_LO = 0x3046; -constexpr unsigned int mmCP_RB_WPTR_POLL_CNTL = 0x21C2; -constexpr unsigned int mmCP_RING0_PRIORITY = 0x304D; -constexpr unsigned int mmCP_RING1_PRIORITY = 0x304E; -constexpr unsigned int mmCP_RING2_PRIORITY = 0x304F; -constexpr unsigned int mmCP_RINGID = 0xA0D9; -constexpr unsigned int mmCP_RING_PRIORITY_CNTS = 0x304C; -constexpr unsigned int mmCP_ROQ1_THRESHOLDS = 0x21D5; -constexpr unsigned int mmCP_ROQ2_AVAIL = 0x21DC; -constexpr unsigned int mmCP_ROQ2_THRESHOLDS = 0x21D6; -constexpr unsigned int mmCP_ROQ_AVAIL = 0x21DA; -constexpr unsigned int mmCP_ROQ_IB1_STAT = 0x21E1; -constexpr unsigned int mmCP_ROQ_IB2_STAT = 0x21E2; -constexpr unsigned int mmCP_ROQ_RB_STAT = 0x21E0; -constexpr unsigned int mmCP_ROQ_THRESHOLDS__CI__VI = 0x21BC; -constexpr unsigned int mmCP_SCRATCH_DATA__CI__VI = 0xC090; -constexpr unsigned int mmCP_SCRATCH_DATA__SI = 0x2190; -constexpr unsigned int mmCP_SCRATCH_INDEX__CI__VI = 0xC08F; -constexpr unsigned int mmCP_SCRATCH_INDEX__SI = 0x218F; -constexpr unsigned int mmCP_SC_PSINVOC_COUNT0_HI__CI__VI = 0xC02D; -constexpr unsigned int mmCP_SC_PSINVOC_COUNT0_HI__SI = 0x212D; -constexpr unsigned int mmCP_SC_PSINVOC_COUNT0_LO__CI__VI = 0xC02C; -constexpr unsigned int mmCP_SC_PSINVOC_COUNT0_LO__SI = 0x212C; -constexpr unsigned int mmCP_SC_PSINVOC_COUNT1_HI__CI__VI = 0xC02F; -constexpr unsigned int mmCP_SC_PSINVOC_COUNT1_HI__SI = 0x212F; -constexpr unsigned int mmCP_SC_PSINVOC_COUNT1_LO__CI__VI = 0xC02E; -constexpr unsigned int mmCP_SC_PSINVOC_COUNT1_LO__SI = 0x212E; -constexpr unsigned int mmCP_SEM_WAIT_TIMER__CI__VI = 0xC06F; -constexpr unsigned int mmCP_SEM_WAIT_TIMER__SI = 0x216F; -constexpr unsigned int mmCP_SIG_SEM_ADDR_HI__CI__VI = 0xC071; -constexpr unsigned int mmCP_SIG_SEM_ADDR_HI__SI = 0x2171; -constexpr unsigned int mmCP_SIG_SEM_ADDR_LO__CI__VI = 0xC070; -constexpr unsigned int mmCP_SIG_SEM_ADDR_LO__SI = 0x2170; -constexpr unsigned int mmCP_STALLED_STAT1 = 0x219D; -constexpr unsigned int mmCP_STALLED_STAT2 = 0x219E; -constexpr unsigned int mmCP_STALLED_STAT3 = 0x219C; -constexpr unsigned int mmCP_STAT = 0x21A0; -constexpr unsigned int mmCP_STQ_AVAIL = 0x21DB; -constexpr unsigned int mmCP_STQ_STAT = 0x21E3; -constexpr unsigned int mmCP_STQ_THRESHOLDS = 0x21D7; -constexpr unsigned int mmCP_STQ_WR_STAT__CI__VI = 0x21E4; -constexpr unsigned int mmCP_STREAM_OUT_ADDR_HI__CI__VI = 0xC007; -constexpr unsigned int mmCP_STREAM_OUT_ADDR_HI__SI = 0x2107; -constexpr unsigned int mmCP_STREAM_OUT_ADDR_LO__CI__VI = 0xC006; -constexpr unsigned int mmCP_STREAM_OUT_ADDR_LO__SI = 0x2106; -constexpr unsigned int mmCP_STRMOUT_CNTL__CI__VI = 0xC03F; -constexpr unsigned int mmCP_STRMOUT_CNTL__SI = 0x213F; -constexpr unsigned int mmCP_ST_BASE_HI__CI__VI = 0xC0D3; -constexpr unsigned int mmCP_ST_BASE_HI__SI = 0x21D3; -constexpr unsigned int mmCP_ST_BASE_LO__CI__VI = 0xC0D2; -constexpr unsigned int mmCP_ST_BASE_LO__SI = 0x21D2; -constexpr unsigned int mmCP_ST_BUFSZ__CI__VI = 0xC0D4; -constexpr unsigned int mmCP_ST_BUFSZ__SI = 0x21D4; -constexpr unsigned int mmCP_VGT_CSINVOC_COUNT_HI__CI__VI = 0xC031; -constexpr unsigned int mmCP_VGT_CSINVOC_COUNT_HI__SI = 0x2131; -constexpr unsigned int mmCP_VGT_CSINVOC_COUNT_LO__CI__VI = 0xC030; -constexpr unsigned int mmCP_VGT_CSINVOC_COUNT_LO__SI = 0x2130; -constexpr unsigned int mmCP_VGT_DSINVOC_COUNT_HI__CI__VI = 0xC027; -constexpr unsigned int mmCP_VGT_DSINVOC_COUNT_HI__SI = 0x2127; -constexpr unsigned int mmCP_VGT_DSINVOC_COUNT_LO__CI__VI = 0xC026; -constexpr unsigned int mmCP_VGT_DSINVOC_COUNT_LO__SI = 0x2126; -constexpr unsigned int mmCP_VGT_GSINVOC_COUNT_HI__CI__VI = 0xC023; -constexpr unsigned int mmCP_VGT_GSINVOC_COUNT_HI__SI = 0x2123; -constexpr unsigned int mmCP_VGT_GSINVOC_COUNT_LO__CI__VI = 0xC022; -constexpr unsigned int mmCP_VGT_GSINVOC_COUNT_LO__SI = 0x2122; -constexpr unsigned int mmCP_VGT_GSPRIM_COUNT_HI__CI__VI = 0xC01F; -constexpr unsigned int mmCP_VGT_GSPRIM_COUNT_HI__SI = 0x211F; -constexpr unsigned int mmCP_VGT_GSPRIM_COUNT_LO__CI__VI = 0xC01E; -constexpr unsigned int mmCP_VGT_GSPRIM_COUNT_LO__SI = 0x211E; -constexpr unsigned int mmCP_VGT_HSINVOC_COUNT_HI__CI__VI = 0xC025; -constexpr unsigned int mmCP_VGT_HSINVOC_COUNT_HI__SI = 0x2125; -constexpr unsigned int mmCP_VGT_HSINVOC_COUNT_LO__CI__VI = 0xC024; -constexpr unsigned int mmCP_VGT_HSINVOC_COUNT_LO__SI = 0x2124; -constexpr unsigned int mmCP_VGT_IAPRIM_COUNT_HI__CI__VI = 0xC01D; -constexpr unsigned int mmCP_VGT_IAPRIM_COUNT_HI__SI = 0x211D; -constexpr unsigned int mmCP_VGT_IAPRIM_COUNT_LO__CI__VI = 0xC01C; -constexpr unsigned int mmCP_VGT_IAPRIM_COUNT_LO__SI = 0x211C; -constexpr unsigned int mmCP_VGT_IAVERT_COUNT_HI__CI__VI = 0xC01B; -constexpr unsigned int mmCP_VGT_IAVERT_COUNT_HI__SI = 0x211B; -constexpr unsigned int mmCP_VGT_IAVERT_COUNT_LO__CI__VI = 0xC01A; -constexpr unsigned int mmCP_VGT_IAVERT_COUNT_LO__SI = 0x211A; -constexpr unsigned int mmCP_VGT_VSINVOC_COUNT_HI__CI__VI = 0xC021; -constexpr unsigned int mmCP_VGT_VSINVOC_COUNT_HI__SI = 0x2121; -constexpr unsigned int mmCP_VGT_VSINVOC_COUNT_LO__CI__VI = 0xC020; -constexpr unsigned int mmCP_VGT_VSINVOC_COUNT_LO__SI = 0x2120; -constexpr unsigned int mmCP_VMID = 0xA0DA; -constexpr unsigned int mmCP_VMID_PREEMPT__CI__VI = 0x30B6; -constexpr unsigned int mmCP_VMID_RESET__CI__VI = 0x30B3; -constexpr unsigned int mmCP_WAIT_REG_MEM_TIMEOUT__CI__VI = 0xC074; -constexpr unsigned int mmCP_WAIT_REG_MEM_TIMEOUT__SI = 0x2174; -constexpr unsigned int mmCP_WAIT_SEM_ADDR_HI__CI__VI = 0xC076; -constexpr unsigned int mmCP_WAIT_SEM_ADDR_HI__SI = 0x2176; -constexpr unsigned int mmCP_WAIT_SEM_ADDR_LO__CI__VI = 0xC075; -constexpr unsigned int mmCP_WAIT_SEM_ADDR_LO__SI = 0x2175; -constexpr unsigned int mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT__SI__VI = 0x1BC3; -constexpr unsigned int mmCRTC0_CRTC_BLACK_COLOR__SI = 0x1BA2; -constexpr unsigned int mmCRTC0_CRTC_BLANK_CONTROL = 0x1B9D; -constexpr unsigned int mmCRTC0_CRTC_BLANK_DATA_COLOR__SI = 0x1BA1; -constexpr unsigned int mmCRTC0_CRTC_CONTROL__SI__VI = 0x1B9C; -constexpr unsigned int mmCRTC0_CRTC_COUNT_CONTROL__SI__VI = 0x1BA9; -constexpr unsigned int mmCRTC0_CRTC_COUNT_RESET__SI__VI = 0x1BAA; -constexpr unsigned int mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL__SI__VI = 0x1BB6; -constexpr unsigned int mmCRTC0_CRTC_DTMTEST_CNTL__SI__VI = 0x1B92; -constexpr unsigned int mmCRTC0_CRTC_DTMTEST_STATUS_POSITION__SI__VI = 0x1B93; -constexpr unsigned int mmCRTC0_CRTC_FLOW_CONTROL__SI__VI = 0x1B99; -constexpr unsigned int mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL__SI__VI = 0x1B98; -constexpr unsigned int mmCRTC0_CRTC_H_BLANK_START_END__SI__VI = 0x1B81; -constexpr unsigned int mmCRTC0_CRTC_H_SYNC_A_CNTL__SI__VI = 0x1B83; -constexpr unsigned int mmCRTC0_CRTC_H_SYNC_A__SI__VI = 0x1B82; -constexpr unsigned int mmCRTC0_CRTC_H_SYNC_B_CNTL__SI__VI = 0x1B85; -constexpr unsigned int mmCRTC0_CRTC_H_SYNC_B__SI__VI = 0x1B84; -constexpr unsigned int mmCRTC0_CRTC_H_TOTAL__SI__VI = 0x1B80; -constexpr unsigned int mmCRTC0_CRTC_INTERLACE_CONTROL__SI__VI = 0x1B9E; -constexpr unsigned int mmCRTC0_CRTC_INTERLACE_STATUS__SI__VI = 0x1B9F; -constexpr unsigned int mmCRTC0_CRTC_INTERRUPT_CONTROL__SI__VI = 0x1BB4; -constexpr unsigned int mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI__VI = 0x1BAB; -constexpr unsigned int mmCRTC0_CRTC_MASTER_EN__SI__VI = 0x1BC2; -constexpr unsigned int mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI__VI = 0x1BC0; -constexpr unsigned int mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT__SI__VI = 0x1BBF; -constexpr unsigned int mmCRTC0_CRTC_MVP_STATUS__SI__VI = 0x1BC1; -constexpr unsigned int mmCRTC0_CRTC_NOM_VERT_POSITION__SI__VI = 0x1BA5; -constexpr unsigned int mmCRTC0_CRTC_OVERSCAN_COLOR__SI = 0x1BA0; -constexpr unsigned int mmCRTC0_CRTC_PIXEL_DATA_READBACK__SI = 0x1B9A; -constexpr unsigned int mmCRTC0_CRTC_SNAPSHOT_CONTROL__SI__VI = 0x1BB0; -constexpr unsigned int mmCRTC0_CRTC_SNAPSHOT_FRAME__SI__VI = 0x1BB2; -constexpr unsigned int mmCRTC0_CRTC_SNAPSHOT_POSITION__SI__VI = 0x1BB1; -constexpr unsigned int mmCRTC0_CRTC_SNAPSHOT_STATUS__SI__VI = 0x1BAF; -constexpr unsigned int mmCRTC0_CRTC_START_LINE_CONTROL__SI__VI = 0x1BB3; -constexpr unsigned int mmCRTC0_CRTC_STATUS = 0x1BA3; -constexpr unsigned int mmCRTC0_CRTC_STATUS_FRAME_COUNT__SI__VI = 0x1BA6; -constexpr unsigned int mmCRTC0_CRTC_STATUS_HV_COUNT__SI__VI = 0x1BA8; -constexpr unsigned int mmCRTC0_CRTC_STATUS_POSITION = 0x1BA4; -constexpr unsigned int mmCRTC0_CRTC_STATUS_VF_COUNT__SI__VI = 0x1BA7; -constexpr unsigned int mmCRTC0_CRTC_STEREO_CONTROL__SI__VI = 0x1BAE; -constexpr unsigned int mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE__SI = 0x1B9B; -constexpr unsigned int mmCRTC0_CRTC_STEREO_STATUS__SI__VI = 0x1BAD; -constexpr unsigned int mmCRTC0_CRTC_TEST_DEBUG_DATA__SI__VI = 0x1BC7; -constexpr unsigned int mmCRTC0_CRTC_TEST_DEBUG_INDEX__SI__VI = 0x1BC6; -constexpr unsigned int mmCRTC0_CRTC_TEST_PATTERN_COLOR__SI__VI = 0x1BBC; -constexpr unsigned int mmCRTC0_CRTC_TEST_PATTERN_CONTROL__SI__VI = 0x1BBA; -constexpr unsigned int mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS__SI__VI = 0x1BBB; -constexpr unsigned int mmCRTC0_CRTC_TRIGA_CNTL__SI__VI = 0x1B94; -constexpr unsigned int mmCRTC0_CRTC_TRIGA_MANUAL_TRIG__SI__VI = 0x1B95; -constexpr unsigned int mmCRTC0_CRTC_TRIGB_CNTL__SI__VI = 0x1B96; -constexpr unsigned int mmCRTC0_CRTC_TRIGB_MANUAL_TRIG__SI__VI = 0x1B97; -constexpr unsigned int mmCRTC0_CRTC_UPDATE_LOCK__SI__VI = 0x1BB5; -constexpr unsigned int mmCRTC0_CRTC_VBI_END__SI__VI = 0x1B86; -constexpr unsigned int mmCRTC0_CRTC_VERT_SYNC_CONTROL__SI__VI = 0x1BAC; -constexpr unsigned int mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI__VI = 0x1BB7; -constexpr unsigned int mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS__SI__VI = 0x1B8C; -constexpr unsigned int mmCRTC0_CRTC_V_BLANK_START_END__SI__VI = 0x1B8D; -constexpr unsigned int mmCRTC0_CRTC_V_SYNC_A_CNTL__SI__VI = 0x1B8F; -constexpr unsigned int mmCRTC0_CRTC_V_SYNC_A__SI__VI = 0x1B8E; -constexpr unsigned int mmCRTC0_CRTC_V_SYNC_B_CNTL__SI__VI = 0x1B91; -constexpr unsigned int mmCRTC0_CRTC_V_SYNC_B__SI__VI = 0x1B90; -constexpr unsigned int mmCRTC0_CRTC_V_TOTAL_CONTROL__SI__VI = 0x1B8A; -constexpr unsigned int mmCRTC0_CRTC_V_TOTAL_INT_STATUS__SI__VI = 0x1B8B; -constexpr unsigned int mmCRTC0_CRTC_V_TOTAL_MAX__SI__VI = 0x1B89; -constexpr unsigned int mmCRTC0_CRTC_V_TOTAL_MIN__SI__VI = 0x1B88; -constexpr unsigned int mmCRTC0_CRTC_V_TOTAL__SI__VI = 0x1B87; -constexpr unsigned int mmCRTC0_CRTC_V_UPDATE_INT_STATUS__SI__VI = 0x1BC4; -constexpr unsigned int mmCRTC0_MASTER_UPDATE_LOCK__SI__VI = 0x1BBD; -constexpr unsigned int mmCRTC0_MASTER_UPDATE_MODE = 0x1BBE; -constexpr unsigned int mmCRTC0_PIXEL_RATE_CNTL__SI = 0x0120; -constexpr unsigned int mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__SI = 0x1EC3; -constexpr unsigned int mmCRTC1_CRTC_BLACK_COLOR__SI = 0x1EA2; -constexpr unsigned int mmCRTC1_CRTC_BLANK_DATA_COLOR__SI = 0x1EA1; -constexpr unsigned int mmCRTC1_CRTC_CONTROL__SI = 0x1E9C; -constexpr unsigned int mmCRTC1_CRTC_COUNT_CONTROL__SI = 0x1EA9; -constexpr unsigned int mmCRTC1_CRTC_COUNT_RESET__SI = 0x1EAA; -constexpr unsigned int mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL__SI = 0x1EB6; -constexpr unsigned int mmCRTC1_CRTC_DTMTEST_CNTL__SI = 0x1E92; -constexpr unsigned int mmCRTC1_CRTC_DTMTEST_STATUS_POSITION__SI = 0x1E93; -constexpr unsigned int mmCRTC1_CRTC_FLOW_CONTROL__SI = 0x1E99; -constexpr unsigned int mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL__SI = 0x1E98; -constexpr unsigned int mmCRTC1_CRTC_H_BLANK_START_END__SI = 0x1E81; -constexpr unsigned int mmCRTC1_CRTC_H_SYNC_A_CNTL__SI = 0x1E83; -constexpr unsigned int mmCRTC1_CRTC_H_SYNC_A__SI = 0x1E82; -constexpr unsigned int mmCRTC1_CRTC_H_SYNC_B_CNTL__SI = 0x1E85; -constexpr unsigned int mmCRTC1_CRTC_H_SYNC_B__SI = 0x1E84; -constexpr unsigned int mmCRTC1_CRTC_H_TOTAL__SI = 0x1E80; -constexpr unsigned int mmCRTC1_CRTC_INTERLACE_CONTROL__SI = 0x1E9E; -constexpr unsigned int mmCRTC1_CRTC_INTERLACE_STATUS__SI = 0x1E9F; -constexpr unsigned int mmCRTC1_CRTC_INTERRUPT_CONTROL__SI = 0x1EB4; -constexpr unsigned int mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI = 0x1EAB; -constexpr unsigned int mmCRTC1_CRTC_MASTER_EN__SI = 0x1EC2; -constexpr unsigned int mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI = 0x1EC0; -constexpr unsigned int mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT__SI = 0x1EBF; -constexpr unsigned int mmCRTC1_CRTC_MVP_STATUS__SI = 0x1EC1; -constexpr unsigned int mmCRTC1_CRTC_NOM_VERT_POSITION__SI = 0x1EA5; -constexpr unsigned int mmCRTC1_CRTC_OVERSCAN_COLOR__SI = 0x1EA0; -constexpr unsigned int mmCRTC1_CRTC_PIXEL_DATA_READBACK__SI = 0x1E9A; -constexpr unsigned int mmCRTC1_CRTC_SNAPSHOT_CONTROL__SI = 0x1EB0; -constexpr unsigned int mmCRTC1_CRTC_SNAPSHOT_FRAME__SI = 0x1EB2; -constexpr unsigned int mmCRTC1_CRTC_SNAPSHOT_POSITION__SI = 0x1EB1; -constexpr unsigned int mmCRTC1_CRTC_SNAPSHOT_STATUS__SI = 0x1EAF; -constexpr unsigned int mmCRTC1_CRTC_START_LINE_CONTROL__SI = 0x1EB3; -constexpr unsigned int mmCRTC1_CRTC_STATUS_FRAME_COUNT__SI = 0x1EA6; -constexpr unsigned int mmCRTC1_CRTC_STATUS_HV_COUNT__SI = 0x1EA8; -constexpr unsigned int mmCRTC1_CRTC_STATUS_VF_COUNT__SI = 0x1EA7; -constexpr unsigned int mmCRTC1_CRTC_STEREO_CONTROL__SI = 0x1EAE; -constexpr unsigned int mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE__SI = 0x1E9B; -constexpr unsigned int mmCRTC1_CRTC_STEREO_STATUS__SI = 0x1EAD; -constexpr unsigned int mmCRTC1_CRTC_TEST_DEBUG_DATA__SI = 0x1EC7; -constexpr unsigned int mmCRTC1_CRTC_TEST_DEBUG_INDEX__SI = 0x1EC6; -constexpr unsigned int mmCRTC1_CRTC_TEST_PATTERN_COLOR__SI = 0x1EBC; -constexpr unsigned int mmCRTC1_CRTC_TEST_PATTERN_CONTROL__SI = 0x1EBA; -constexpr unsigned int mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS__SI = 0x1EBB; -constexpr unsigned int mmCRTC1_CRTC_TRIGA_CNTL__SI = 0x1E94; -constexpr unsigned int mmCRTC1_CRTC_TRIGA_MANUAL_TRIG__SI = 0x1E95; -constexpr unsigned int mmCRTC1_CRTC_TRIGB_CNTL__SI = 0x1E96; -constexpr unsigned int mmCRTC1_CRTC_TRIGB_MANUAL_TRIG__SI = 0x1E97; -constexpr unsigned int mmCRTC1_CRTC_UPDATE_LOCK__SI = 0x1EB5; -constexpr unsigned int mmCRTC1_CRTC_VBI_END__SI = 0x1E86; -constexpr unsigned int mmCRTC1_CRTC_VERT_SYNC_CONTROL__SI = 0x1EAC; -constexpr unsigned int mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI = 0x1EB7; -constexpr unsigned int mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS__SI = 0x1E8C; -constexpr unsigned int mmCRTC1_CRTC_V_BLANK_START_END__SI = 0x1E8D; -constexpr unsigned int mmCRTC1_CRTC_V_SYNC_A_CNTL__SI = 0x1E8F; -constexpr unsigned int mmCRTC1_CRTC_V_SYNC_A__SI = 0x1E8E; -constexpr unsigned int mmCRTC1_CRTC_V_SYNC_B_CNTL__SI = 0x1E91; -constexpr unsigned int mmCRTC1_CRTC_V_SYNC_B__SI = 0x1E90; -constexpr unsigned int mmCRTC1_CRTC_V_TOTAL_CONTROL__SI = 0x1E8A; -constexpr unsigned int mmCRTC1_CRTC_V_TOTAL_INT_STATUS__SI = 0x1E8B; -constexpr unsigned int mmCRTC1_CRTC_V_TOTAL_MAX__SI = 0x1E89; -constexpr unsigned int mmCRTC1_CRTC_V_TOTAL_MIN__SI = 0x1E88; -constexpr unsigned int mmCRTC1_CRTC_V_TOTAL__SI = 0x1E87; -constexpr unsigned int mmCRTC1_CRTC_V_UPDATE_INT_STATUS__SI = 0x1EC4; -constexpr unsigned int mmCRTC1_MASTER_UPDATE_LOCK__SI = 0x1EBD; -constexpr unsigned int mmCRTC1_PIXEL_RATE_CNTL__SI = 0x0121; -constexpr unsigned int mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__SI = 0x41C3; -constexpr unsigned int mmCRTC2_CRTC_BLACK_COLOR__SI = 0x41A2; -constexpr unsigned int mmCRTC2_CRTC_BLANK_DATA_COLOR__SI = 0x41A1; -constexpr unsigned int mmCRTC2_CRTC_CONTROL__SI = 0x419C; -constexpr unsigned int mmCRTC2_CRTC_COUNT_CONTROL__SI = 0x41A9; -constexpr unsigned int mmCRTC2_CRTC_COUNT_RESET__SI = 0x41AA; -constexpr unsigned int mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL__SI = 0x41B6; -constexpr unsigned int mmCRTC2_CRTC_DTMTEST_CNTL__SI = 0x4192; -constexpr unsigned int mmCRTC2_CRTC_DTMTEST_STATUS_POSITION__SI = 0x4193; -constexpr unsigned int mmCRTC2_CRTC_FLOW_CONTROL__SI = 0x4199; -constexpr unsigned int mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL__SI = 0x4198; -constexpr unsigned int mmCRTC2_CRTC_H_BLANK_START_END__SI = 0x4181; -constexpr unsigned int mmCRTC2_CRTC_H_SYNC_A_CNTL__SI = 0x4183; -constexpr unsigned int mmCRTC2_CRTC_H_SYNC_A__SI = 0x4182; -constexpr unsigned int mmCRTC2_CRTC_H_SYNC_B_CNTL__SI = 0x4185; -constexpr unsigned int mmCRTC2_CRTC_H_SYNC_B__SI = 0x4184; -constexpr unsigned int mmCRTC2_CRTC_H_TOTAL__SI = 0x4180; -constexpr unsigned int mmCRTC2_CRTC_INTERLACE_CONTROL__SI = 0x419E; -constexpr unsigned int mmCRTC2_CRTC_INTERLACE_STATUS__SI = 0x419F; -constexpr unsigned int mmCRTC2_CRTC_INTERRUPT_CONTROL__SI = 0x41B4; -constexpr unsigned int mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI = 0x41AB; -constexpr unsigned int mmCRTC2_CRTC_MASTER_EN__SI = 0x41C2; -constexpr unsigned int mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI = 0x41C0; -constexpr unsigned int mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT__SI = 0x41BF; -constexpr unsigned int mmCRTC2_CRTC_MVP_STATUS__SI = 0x41C1; -constexpr unsigned int mmCRTC2_CRTC_NOM_VERT_POSITION__SI = 0x41A5; -constexpr unsigned int mmCRTC2_CRTC_OVERSCAN_COLOR__SI = 0x41A0; -constexpr unsigned int mmCRTC2_CRTC_PIXEL_DATA_READBACK__SI = 0x419A; -constexpr unsigned int mmCRTC2_CRTC_SNAPSHOT_CONTROL__SI = 0x41B0; -constexpr unsigned int mmCRTC2_CRTC_SNAPSHOT_FRAME__SI = 0x41B2; -constexpr unsigned int mmCRTC2_CRTC_SNAPSHOT_POSITION__SI = 0x41B1; -constexpr unsigned int mmCRTC2_CRTC_SNAPSHOT_STATUS__SI = 0x41AF; -constexpr unsigned int mmCRTC2_CRTC_START_LINE_CONTROL__SI = 0x41B3; -constexpr unsigned int mmCRTC2_CRTC_STATUS_FRAME_COUNT__SI = 0x41A6; -constexpr unsigned int mmCRTC2_CRTC_STATUS_HV_COUNT__SI = 0x41A8; -constexpr unsigned int mmCRTC2_CRTC_STATUS_VF_COUNT__SI = 0x41A7; -constexpr unsigned int mmCRTC2_CRTC_STEREO_CONTROL__SI = 0x41AE; -constexpr unsigned int mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE__SI = 0x419B; -constexpr unsigned int mmCRTC2_CRTC_STEREO_STATUS__SI = 0x41AD; -constexpr unsigned int mmCRTC2_CRTC_TEST_DEBUG_DATA__SI = 0x41C7; -constexpr unsigned int mmCRTC2_CRTC_TEST_DEBUG_INDEX__SI = 0x41C6; -constexpr unsigned int mmCRTC2_CRTC_TEST_PATTERN_COLOR__SI = 0x41BC; -constexpr unsigned int mmCRTC2_CRTC_TEST_PATTERN_CONTROL__SI = 0x41BA; -constexpr unsigned int mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS__SI = 0x41BB; -constexpr unsigned int mmCRTC2_CRTC_TRIGA_CNTL__SI = 0x4194; -constexpr unsigned int mmCRTC2_CRTC_TRIGA_MANUAL_TRIG__SI = 0x4195; -constexpr unsigned int mmCRTC2_CRTC_TRIGB_CNTL__SI = 0x4196; -constexpr unsigned int mmCRTC2_CRTC_TRIGB_MANUAL_TRIG__SI = 0x4197; -constexpr unsigned int mmCRTC2_CRTC_UPDATE_LOCK__SI = 0x41B5; -constexpr unsigned int mmCRTC2_CRTC_VBI_END__SI = 0x4186; -constexpr unsigned int mmCRTC2_CRTC_VERT_SYNC_CONTROL__SI = 0x41AC; -constexpr unsigned int mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI = 0x41B7; -constexpr unsigned int mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS__SI = 0x418C; -constexpr unsigned int mmCRTC2_CRTC_V_BLANK_START_END__SI = 0x418D; -constexpr unsigned int mmCRTC2_CRTC_V_SYNC_A_CNTL__SI = 0x418F; -constexpr unsigned int mmCRTC2_CRTC_V_SYNC_A__SI = 0x418E; -constexpr unsigned int mmCRTC2_CRTC_V_SYNC_B_CNTL__SI = 0x4191; -constexpr unsigned int mmCRTC2_CRTC_V_SYNC_B__SI = 0x4190; -constexpr unsigned int mmCRTC2_CRTC_V_TOTAL_CONTROL__SI = 0x418A; -constexpr unsigned int mmCRTC2_CRTC_V_TOTAL_INT_STATUS__SI = 0x418B; -constexpr unsigned int mmCRTC2_CRTC_V_TOTAL_MAX__SI = 0x4189; -constexpr unsigned int mmCRTC2_CRTC_V_TOTAL_MIN__SI = 0x4188; -constexpr unsigned int mmCRTC2_CRTC_V_TOTAL__SI = 0x4187; -constexpr unsigned int mmCRTC2_CRTC_V_UPDATE_INT_STATUS__SI = 0x41C4; -constexpr unsigned int mmCRTC2_MASTER_UPDATE_LOCK__SI = 0x41BD; -constexpr unsigned int mmCRTC2_PIXEL_RATE_CNTL__SI = 0x0122; -constexpr unsigned int mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__SI = 0x44C3; -constexpr unsigned int mmCRTC3_CRTC_BLACK_COLOR__SI = 0x44A2; -constexpr unsigned int mmCRTC3_CRTC_BLANK_DATA_COLOR__SI = 0x44A1; -constexpr unsigned int mmCRTC3_CRTC_CONTROL__SI = 0x449C; -constexpr unsigned int mmCRTC3_CRTC_COUNT_CONTROL__SI = 0x44A9; -constexpr unsigned int mmCRTC3_CRTC_COUNT_RESET__SI = 0x44AA; -constexpr unsigned int mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL__SI = 0x44B6; -constexpr unsigned int mmCRTC3_CRTC_DTMTEST_CNTL__SI = 0x4492; -constexpr unsigned int mmCRTC3_CRTC_DTMTEST_STATUS_POSITION__SI = 0x4493; -constexpr unsigned int mmCRTC3_CRTC_FLOW_CONTROL__SI = 0x4499; -constexpr unsigned int mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL__SI = 0x4498; -constexpr unsigned int mmCRTC3_CRTC_H_BLANK_START_END__SI = 0x4481; -constexpr unsigned int mmCRTC3_CRTC_H_SYNC_A_CNTL__SI = 0x4483; -constexpr unsigned int mmCRTC3_CRTC_H_SYNC_A__SI = 0x4482; -constexpr unsigned int mmCRTC3_CRTC_H_SYNC_B_CNTL__SI = 0x4485; -constexpr unsigned int mmCRTC3_CRTC_H_SYNC_B__SI = 0x4484; -constexpr unsigned int mmCRTC3_CRTC_H_TOTAL__SI = 0x4480; -constexpr unsigned int mmCRTC3_CRTC_INTERLACE_CONTROL__SI = 0x449E; -constexpr unsigned int mmCRTC3_CRTC_INTERLACE_STATUS__SI = 0x449F; -constexpr unsigned int mmCRTC3_CRTC_INTERRUPT_CONTROL__SI = 0x44B4; -constexpr unsigned int mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI = 0x44AB; -constexpr unsigned int mmCRTC3_CRTC_MASTER_EN__SI = 0x44C2; -constexpr unsigned int mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI = 0x44C0; -constexpr unsigned int mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT__SI = 0x44BF; -constexpr unsigned int mmCRTC3_CRTC_MVP_STATUS__SI = 0x44C1; -constexpr unsigned int mmCRTC3_CRTC_NOM_VERT_POSITION__SI = 0x44A5; -constexpr unsigned int mmCRTC3_CRTC_OVERSCAN_COLOR__SI = 0x44A0; -constexpr unsigned int mmCRTC3_CRTC_PIXEL_DATA_READBACK__SI = 0x449A; -constexpr unsigned int mmCRTC3_CRTC_SNAPSHOT_CONTROL__SI = 0x44B0; -constexpr unsigned int mmCRTC3_CRTC_SNAPSHOT_FRAME__SI = 0x44B2; -constexpr unsigned int mmCRTC3_CRTC_SNAPSHOT_POSITION__SI = 0x44B1; -constexpr unsigned int mmCRTC3_CRTC_SNAPSHOT_STATUS__SI = 0x44AF; -constexpr unsigned int mmCRTC3_CRTC_START_LINE_CONTROL__SI = 0x44B3; -constexpr unsigned int mmCRTC3_CRTC_STATUS_FRAME_COUNT__SI = 0x44A6; -constexpr unsigned int mmCRTC3_CRTC_STATUS_HV_COUNT__SI = 0x44A8; -constexpr unsigned int mmCRTC3_CRTC_STATUS_VF_COUNT__SI = 0x44A7; -constexpr unsigned int mmCRTC3_CRTC_STEREO_CONTROL__SI = 0x44AE; -constexpr unsigned int mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE__SI = 0x449B; -constexpr unsigned int mmCRTC3_CRTC_STEREO_STATUS__SI = 0x44AD; -constexpr unsigned int mmCRTC3_CRTC_TEST_DEBUG_DATA__SI = 0x44C7; -constexpr unsigned int mmCRTC3_CRTC_TEST_DEBUG_INDEX__SI = 0x44C6; -constexpr unsigned int mmCRTC3_CRTC_TEST_PATTERN_COLOR__SI = 0x44BC; -constexpr unsigned int mmCRTC3_CRTC_TEST_PATTERN_CONTROL__SI = 0x44BA; -constexpr unsigned int mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS__SI = 0x44BB; -constexpr unsigned int mmCRTC3_CRTC_TRIGA_CNTL__SI = 0x4494; -constexpr unsigned int mmCRTC3_CRTC_TRIGA_MANUAL_TRIG__SI = 0x4495; -constexpr unsigned int mmCRTC3_CRTC_TRIGB_CNTL__SI = 0x4496; -constexpr unsigned int mmCRTC3_CRTC_TRIGB_MANUAL_TRIG__SI = 0x4497; -constexpr unsigned int mmCRTC3_CRTC_UPDATE_LOCK__SI = 0x44B5; -constexpr unsigned int mmCRTC3_CRTC_VBI_END__SI = 0x4486; -constexpr unsigned int mmCRTC3_CRTC_VERT_SYNC_CONTROL__SI = 0x44AC; -constexpr unsigned int mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI = 0x44B7; -constexpr unsigned int mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS__SI = 0x448C; -constexpr unsigned int mmCRTC3_CRTC_V_BLANK_START_END__SI = 0x448D; -constexpr unsigned int mmCRTC3_CRTC_V_SYNC_A_CNTL__SI = 0x448F; -constexpr unsigned int mmCRTC3_CRTC_V_SYNC_A__SI = 0x448E; -constexpr unsigned int mmCRTC3_CRTC_V_SYNC_B_CNTL__SI = 0x4491; -constexpr unsigned int mmCRTC3_CRTC_V_SYNC_B__SI = 0x4490; -constexpr unsigned int mmCRTC3_CRTC_V_TOTAL_CONTROL__SI = 0x448A; -constexpr unsigned int mmCRTC3_CRTC_V_TOTAL_INT_STATUS__SI = 0x448B; -constexpr unsigned int mmCRTC3_CRTC_V_TOTAL_MAX__SI = 0x4489; -constexpr unsigned int mmCRTC3_CRTC_V_TOTAL_MIN__SI = 0x4488; -constexpr unsigned int mmCRTC3_CRTC_V_TOTAL__SI = 0x4487; -constexpr unsigned int mmCRTC3_CRTC_V_UPDATE_INT_STATUS__SI = 0x44C4; -constexpr unsigned int mmCRTC3_MASTER_UPDATE_LOCK__SI = 0x44BD; -constexpr unsigned int mmCRTC3_PIXEL_RATE_CNTL__SI = 0x0123; -constexpr unsigned int mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__SI = 0x47C3; -constexpr unsigned int mmCRTC4_CRTC_BLACK_COLOR__SI = 0x47A2; -constexpr unsigned int mmCRTC4_CRTC_BLANK_DATA_COLOR__SI = 0x47A1; -constexpr unsigned int mmCRTC4_CRTC_CONTROL__SI = 0x479C; -constexpr unsigned int mmCRTC4_CRTC_COUNT_CONTROL__SI = 0x47A9; -constexpr unsigned int mmCRTC4_CRTC_COUNT_RESET__SI = 0x47AA; -constexpr unsigned int mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL__SI = 0x47B6; -constexpr unsigned int mmCRTC4_CRTC_DTMTEST_CNTL__SI = 0x4792; -constexpr unsigned int mmCRTC4_CRTC_DTMTEST_STATUS_POSITION__SI = 0x4793; -constexpr unsigned int mmCRTC4_CRTC_FLOW_CONTROL__SI = 0x4799; -constexpr unsigned int mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL__SI = 0x4798; -constexpr unsigned int mmCRTC4_CRTC_H_BLANK_START_END__SI = 0x4781; -constexpr unsigned int mmCRTC4_CRTC_H_SYNC_A_CNTL__SI = 0x4783; -constexpr unsigned int mmCRTC4_CRTC_H_SYNC_A__SI = 0x4782; -constexpr unsigned int mmCRTC4_CRTC_H_SYNC_B_CNTL__SI = 0x4785; -constexpr unsigned int mmCRTC4_CRTC_H_SYNC_B__SI = 0x4784; -constexpr unsigned int mmCRTC4_CRTC_H_TOTAL__SI = 0x4780; -constexpr unsigned int mmCRTC4_CRTC_INTERLACE_CONTROL__SI = 0x479E; -constexpr unsigned int mmCRTC4_CRTC_INTERLACE_STATUS__SI = 0x479F; -constexpr unsigned int mmCRTC4_CRTC_INTERRUPT_CONTROL__SI = 0x47B4; -constexpr unsigned int mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI = 0x47AB; -constexpr unsigned int mmCRTC4_CRTC_MASTER_EN__SI = 0x47C2; -constexpr unsigned int mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI = 0x47C0; -constexpr unsigned int mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT__SI = 0x47BF; -constexpr unsigned int mmCRTC4_CRTC_MVP_STATUS__SI = 0x47C1; -constexpr unsigned int mmCRTC4_CRTC_NOM_VERT_POSITION__SI = 0x47A5; -constexpr unsigned int mmCRTC4_CRTC_OVERSCAN_COLOR__SI = 0x47A0; -constexpr unsigned int mmCRTC4_CRTC_PIXEL_DATA_READBACK__SI = 0x479A; -constexpr unsigned int mmCRTC4_CRTC_SNAPSHOT_CONTROL__SI = 0x47B0; -constexpr unsigned int mmCRTC4_CRTC_SNAPSHOT_FRAME__SI = 0x47B2; -constexpr unsigned int mmCRTC4_CRTC_SNAPSHOT_POSITION__SI = 0x47B1; -constexpr unsigned int mmCRTC4_CRTC_SNAPSHOT_STATUS__SI = 0x47AF; -constexpr unsigned int mmCRTC4_CRTC_START_LINE_CONTROL__SI = 0x47B3; -constexpr unsigned int mmCRTC4_CRTC_STATUS_FRAME_COUNT__SI = 0x47A6; -constexpr unsigned int mmCRTC4_CRTC_STATUS_HV_COUNT__SI = 0x47A8; -constexpr unsigned int mmCRTC4_CRTC_STATUS_VF_COUNT__SI = 0x47A7; -constexpr unsigned int mmCRTC4_CRTC_STEREO_CONTROL__SI = 0x47AE; -constexpr unsigned int mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE__SI = 0x479B; -constexpr unsigned int mmCRTC4_CRTC_STEREO_STATUS__SI = 0x47AD; -constexpr unsigned int mmCRTC4_CRTC_TEST_DEBUG_DATA__SI = 0x47C7; -constexpr unsigned int mmCRTC4_CRTC_TEST_DEBUG_INDEX__SI = 0x47C6; -constexpr unsigned int mmCRTC4_CRTC_TEST_PATTERN_COLOR__SI = 0x47BC; -constexpr unsigned int mmCRTC4_CRTC_TEST_PATTERN_CONTROL__SI = 0x47BA; -constexpr unsigned int mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS__SI = 0x47BB; -constexpr unsigned int mmCRTC4_CRTC_TRIGA_CNTL__SI = 0x4794; -constexpr unsigned int mmCRTC4_CRTC_TRIGA_MANUAL_TRIG__SI = 0x4795; -constexpr unsigned int mmCRTC4_CRTC_TRIGB_CNTL__SI = 0x4796; -constexpr unsigned int mmCRTC4_CRTC_TRIGB_MANUAL_TRIG__SI = 0x4797; -constexpr unsigned int mmCRTC4_CRTC_UPDATE_LOCK__SI = 0x47B5; -constexpr unsigned int mmCRTC4_CRTC_VBI_END__SI = 0x4786; -constexpr unsigned int mmCRTC4_CRTC_VERT_SYNC_CONTROL__SI = 0x47AC; -constexpr unsigned int mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI = 0x47B7; -constexpr unsigned int mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS__SI = 0x478C; -constexpr unsigned int mmCRTC4_CRTC_V_BLANK_START_END__SI = 0x478D; -constexpr unsigned int mmCRTC4_CRTC_V_SYNC_A_CNTL__SI = 0x478F; -constexpr unsigned int mmCRTC4_CRTC_V_SYNC_A__SI = 0x478E; -constexpr unsigned int mmCRTC4_CRTC_V_SYNC_B_CNTL__SI = 0x4791; -constexpr unsigned int mmCRTC4_CRTC_V_SYNC_B__SI = 0x4790; -constexpr unsigned int mmCRTC4_CRTC_V_TOTAL_CONTROL__SI = 0x478A; -constexpr unsigned int mmCRTC4_CRTC_V_TOTAL_INT_STATUS__SI = 0x478B; -constexpr unsigned int mmCRTC4_CRTC_V_TOTAL_MAX__SI = 0x4789; -constexpr unsigned int mmCRTC4_CRTC_V_TOTAL_MIN__SI = 0x4788; -constexpr unsigned int mmCRTC4_CRTC_V_TOTAL__SI = 0x4787; -constexpr unsigned int mmCRTC4_CRTC_V_UPDATE_INT_STATUS__SI = 0x47C4; -constexpr unsigned int mmCRTC4_MASTER_UPDATE_LOCK__SI = 0x47BD; -constexpr unsigned int mmCRTC4_PIXEL_RATE_CNTL__SI = 0x0124; -constexpr unsigned int mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__SI = 0x4AC3; -constexpr unsigned int mmCRTC5_CRTC_BLACK_COLOR__SI = 0x4AA2; -constexpr unsigned int mmCRTC5_CRTC_BLANK_DATA_COLOR__SI = 0x4AA1; -constexpr unsigned int mmCRTC5_CRTC_CONTROL__SI = 0x4A9C; -constexpr unsigned int mmCRTC5_CRTC_COUNT_CONTROL__SI = 0x4AA9; -constexpr unsigned int mmCRTC5_CRTC_COUNT_RESET__SI = 0x4AAA; -constexpr unsigned int mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL__SI = 0x4AB6; -constexpr unsigned int mmCRTC5_CRTC_DTMTEST_CNTL__SI = 0x4A92; -constexpr unsigned int mmCRTC5_CRTC_DTMTEST_STATUS_POSITION__SI = 0x4A93; -constexpr unsigned int mmCRTC5_CRTC_FLOW_CONTROL__SI = 0x4A99; -constexpr unsigned int mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL__SI = 0x4A98; -constexpr unsigned int mmCRTC5_CRTC_H_BLANK_START_END__SI = 0x4A81; -constexpr unsigned int mmCRTC5_CRTC_H_SYNC_A_CNTL__SI = 0x4A83; -constexpr unsigned int mmCRTC5_CRTC_H_SYNC_A__SI = 0x4A82; -constexpr unsigned int mmCRTC5_CRTC_H_SYNC_B_CNTL__SI = 0x4A85; -constexpr unsigned int mmCRTC5_CRTC_H_SYNC_B__SI = 0x4A84; -constexpr unsigned int mmCRTC5_CRTC_H_TOTAL__SI = 0x4A80; -constexpr unsigned int mmCRTC5_CRTC_INTERLACE_CONTROL__SI = 0x4A9E; -constexpr unsigned int mmCRTC5_CRTC_INTERLACE_STATUS__SI = 0x4A9F; -constexpr unsigned int mmCRTC5_CRTC_INTERRUPT_CONTROL__SI = 0x4AB4; -constexpr unsigned int mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI = 0x4AAB; -constexpr unsigned int mmCRTC5_CRTC_MASTER_EN__SI = 0x4AC2; -constexpr unsigned int mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI = 0x4AC0; -constexpr unsigned int mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT__SI = 0x4ABF; -constexpr unsigned int mmCRTC5_CRTC_MVP_STATUS__SI = 0x4AC1; -constexpr unsigned int mmCRTC5_CRTC_NOM_VERT_POSITION__SI = 0x4AA5; -constexpr unsigned int mmCRTC5_CRTC_OVERSCAN_COLOR__SI = 0x4AA0; -constexpr unsigned int mmCRTC5_CRTC_PIXEL_DATA_READBACK__SI = 0x4A9A; -constexpr unsigned int mmCRTC5_CRTC_SNAPSHOT_CONTROL__SI = 0x4AB0; -constexpr unsigned int mmCRTC5_CRTC_SNAPSHOT_FRAME__SI = 0x4AB2; -constexpr unsigned int mmCRTC5_CRTC_SNAPSHOT_POSITION__SI = 0x4AB1; -constexpr unsigned int mmCRTC5_CRTC_SNAPSHOT_STATUS__SI = 0x4AAF; -constexpr unsigned int mmCRTC5_CRTC_START_LINE_CONTROL__SI = 0x4AB3; -constexpr unsigned int mmCRTC5_CRTC_STATUS_FRAME_COUNT__SI = 0x4AA6; -constexpr unsigned int mmCRTC5_CRTC_STATUS_HV_COUNT__SI = 0x4AA8; -constexpr unsigned int mmCRTC5_CRTC_STATUS_VF_COUNT__SI = 0x4AA7; -constexpr unsigned int mmCRTC5_CRTC_STEREO_CONTROL__SI = 0x4AAE; -constexpr unsigned int mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE__SI = 0x4A9B; -constexpr unsigned int mmCRTC5_CRTC_STEREO_STATUS__SI = 0x4AAD; -constexpr unsigned int mmCRTC5_CRTC_TEST_DEBUG_DATA__SI = 0x4AC7; -constexpr unsigned int mmCRTC5_CRTC_TEST_DEBUG_INDEX__SI = 0x4AC6; -constexpr unsigned int mmCRTC5_CRTC_TEST_PATTERN_COLOR__SI = 0x4ABC; -constexpr unsigned int mmCRTC5_CRTC_TEST_PATTERN_CONTROL__SI = 0x4ABA; -constexpr unsigned int mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS__SI = 0x4ABB; -constexpr unsigned int mmCRTC5_CRTC_TRIGA_CNTL__SI = 0x4A94; -constexpr unsigned int mmCRTC5_CRTC_TRIGA_MANUAL_TRIG__SI = 0x4A95; -constexpr unsigned int mmCRTC5_CRTC_TRIGB_CNTL__SI = 0x4A96; -constexpr unsigned int mmCRTC5_CRTC_TRIGB_MANUAL_TRIG__SI = 0x4A97; -constexpr unsigned int mmCRTC5_CRTC_UPDATE_LOCK__SI = 0x4AB5; -constexpr unsigned int mmCRTC5_CRTC_VBI_END__SI = 0x4A86; -constexpr unsigned int mmCRTC5_CRTC_VERT_SYNC_CONTROL__SI = 0x4AAC; -constexpr unsigned int mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE__SI = 0x4AB7; -constexpr unsigned int mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS__SI = 0x4A8C; -constexpr unsigned int mmCRTC5_CRTC_V_BLANK_START_END__SI = 0x4A8D; -constexpr unsigned int mmCRTC5_CRTC_V_SYNC_A_CNTL__SI = 0x4A8F; -constexpr unsigned int mmCRTC5_CRTC_V_SYNC_A__SI = 0x4A8E; -constexpr unsigned int mmCRTC5_CRTC_V_SYNC_B_CNTL__SI = 0x4A91; -constexpr unsigned int mmCRTC5_CRTC_V_SYNC_B__SI = 0x4A90; -constexpr unsigned int mmCRTC5_CRTC_V_TOTAL_CONTROL__SI = 0x4A8A; -constexpr unsigned int mmCRTC5_CRTC_V_TOTAL_INT_STATUS__SI = 0x4A8B; -constexpr unsigned int mmCRTC5_CRTC_V_TOTAL_MAX__SI = 0x4A89; -constexpr unsigned int mmCRTC5_CRTC_V_TOTAL_MIN__SI = 0x4A88; -constexpr unsigned int mmCRTC5_CRTC_V_TOTAL__SI = 0x4A87; -constexpr unsigned int mmCRTC5_CRTC_V_UPDATE_INT_STATUS__SI = 0x4AC4; -constexpr unsigned int mmCRTC5_MASTER_UPDATE_LOCK__SI = 0x4ABD; -constexpr unsigned int mmCRTC5_PIXEL_RATE_CNTL__SI = 0x0125; -constexpr unsigned int mmCRTC8_DATA__SI__VI = 0x00ED; -constexpr unsigned int mmCRTC8_IDX__SI__VI = 0x00ED; -constexpr unsigned int mmCRTC_ALLOW_STOP_OFF_V_CNT__SI__VI = 0x1BC3; -constexpr unsigned int mmCRTC_BLACK_COLOR__SI = 0x1BA2; -constexpr unsigned int mmCRTC_BLANK_CONTROL = 0x1B9D; -constexpr unsigned int mmCRTC_BLANK_DATA_COLOR__SI = 0x1BA1; -constexpr unsigned int mmCRTC_CONTROL__SI__VI = 0x1B9C; -constexpr unsigned int mmCRTC_COUNT_CONTROL__SI__VI = 0x1BA9; -constexpr unsigned int mmCRTC_COUNT_RESET__SI__VI = 0x1BAA; -constexpr unsigned int mmCRTC_DOUBLE_BUFFER_CONTROL__SI__VI = 0x1BB6; -constexpr unsigned int mmCRTC_DTMTEST_CNTL__SI__VI = 0x1B92; -constexpr unsigned int mmCRTC_DTMTEST_STATUS_POSITION__SI__VI = 0x1B93; -constexpr unsigned int mmCRTC_FLOW_CONTROL__SI__VI = 0x1B99; -constexpr unsigned int mmCRTC_FORCE_COUNT_NOW_CNTL__SI__VI = 0x1B98; -constexpr unsigned int mmCRTC_H_BLANK_START_END__SI__VI = 0x1B81; -constexpr unsigned int mmCRTC_H_SYNC_A_CNTL__SI__VI = 0x1B83; -constexpr unsigned int mmCRTC_H_SYNC_A__SI__VI = 0x1B82; -constexpr unsigned int mmCRTC_H_SYNC_B_CNTL__SI__VI = 0x1B85; -constexpr unsigned int mmCRTC_H_SYNC_B__SI__VI = 0x1B84; -constexpr unsigned int mmCRTC_H_TOTAL__SI__VI = 0x1B80; -constexpr unsigned int mmCRTC_INTERLACE_CONTROL__SI__VI = 0x1B9E; -constexpr unsigned int mmCRTC_INTERLACE_STATUS__SI__VI = 0x1B9F; -constexpr unsigned int mmCRTC_INTERRUPT_CONTROL__SI__VI = 0x1BB4; -constexpr unsigned int mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI__VI = 0x1BAB; -constexpr unsigned int mmCRTC_MASTER_EN__SI__VI = 0x1BC2; -constexpr unsigned int mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI__VI = 0x1BC0; -constexpr unsigned int mmCRTC_MVP_INBAND_CNTL_INSERT__SI__VI = 0x1BBF; -constexpr unsigned int mmCRTC_MVP_STATUS__SI__VI = 0x1BC1; -constexpr unsigned int mmCRTC_NOM_VERT_POSITION__SI__VI = 0x1BA5; -constexpr unsigned int mmCRTC_OVERSCAN_COLOR__SI = 0x1BA0; -constexpr unsigned int mmCRTC_PIXEL_DATA_READBACK__SI = 0x1B9A; -constexpr unsigned int mmCRTC_SNAPSHOT_CONTROL__SI__VI = 0x1BB0; -constexpr unsigned int mmCRTC_SNAPSHOT_FRAME__SI__VI = 0x1BB2; -constexpr unsigned int mmCRTC_SNAPSHOT_POSITION__SI__VI = 0x1BB1; -constexpr unsigned int mmCRTC_SNAPSHOT_STATUS__SI__VI = 0x1BAF; -constexpr unsigned int mmCRTC_START_LINE_CONTROL__SI__VI = 0x1BB3; -constexpr unsigned int mmCRTC_STATUS = 0x1BA3; -constexpr unsigned int mmCRTC_STATUS_FRAME_COUNT__SI__VI = 0x1BA6; -constexpr unsigned int mmCRTC_STATUS_HV_COUNT__SI__VI = 0x1BA8; -constexpr unsigned int mmCRTC_STATUS_POSITION__SI__VI = 0x1BA4; -constexpr unsigned int mmCRTC_STATUS_VF_COUNT__SI__VI = 0x1BA7; -constexpr unsigned int mmCRTC_STEREO_CONTROL__SI__VI = 0x1BAE; -constexpr unsigned int mmCRTC_STEREO_FORCE_NEXT_EYE__SI = 0x1B9B; -constexpr unsigned int mmCRTC_STEREO_STATUS__SI__VI = 0x1BAD; -constexpr unsigned int mmCRTC_TEST_DEBUG_DATA__SI__VI = 0x1BC7; -constexpr unsigned int mmCRTC_TEST_DEBUG_INDEX__SI__VI = 0x1BC6; -constexpr unsigned int mmCRTC_TEST_PATTERN_COLOR__SI__VI = 0x1BBC; -constexpr unsigned int mmCRTC_TEST_PATTERN_CONTROL__SI__VI = 0x1BBA; -constexpr unsigned int mmCRTC_TEST_PATTERN_PARAMETERS__SI__VI = 0x1BBB; -constexpr unsigned int mmCRTC_TRIGA_CNTL__SI__VI = 0x1B94; -constexpr unsigned int mmCRTC_TRIGA_MANUAL_TRIG__SI__VI = 0x1B95; -constexpr unsigned int mmCRTC_TRIGB_CNTL__SI__VI = 0x1B96; -constexpr unsigned int mmCRTC_TRIGB_MANUAL_TRIG__SI__VI = 0x1B97; -constexpr unsigned int mmCRTC_UPDATE_LOCK__SI__VI = 0x1BB5; -constexpr unsigned int mmCRTC_VBI_END__SI__VI = 0x1B86; -constexpr unsigned int mmCRTC_VERT_SYNC_CONTROL__SI__VI = 0x1BAC; -constexpr unsigned int mmCRTC_VGA_PARAMETER_CAPTURE_MODE__SI__VI = 0x1BB7; -constexpr unsigned int mmCRTC_VSYNC_NOM_INT_STATUS__SI__VI = 0x1B8C; -constexpr unsigned int mmCRTC_V_BLANK_START_END__SI__VI = 0x1B8D; -constexpr unsigned int mmCRTC_V_SYNC_A_CNTL__SI__VI = 0x1B8F; -constexpr unsigned int mmCRTC_V_SYNC_A__SI__VI = 0x1B8E; -constexpr unsigned int mmCRTC_V_SYNC_B_CNTL__SI__VI = 0x1B91; -constexpr unsigned int mmCRTC_V_SYNC_B__SI__VI = 0x1B90; -constexpr unsigned int mmCRTC_V_TOTAL_CONTROL__SI__VI = 0x1B8A; -constexpr unsigned int mmCRTC_V_TOTAL_INT_STATUS__SI__VI = 0x1B8B; -constexpr unsigned int mmCRTC_V_TOTAL_MAX__SI__VI = 0x1B89; -constexpr unsigned int mmCRTC_V_TOTAL_MIN__SI__VI = 0x1B88; -constexpr unsigned int mmCRTC_V_TOTAL__SI__VI = 0x1B87; -constexpr unsigned int mmCRTC_V_UPDATE_INT_STATUS__SI__VI = 0x1BC4; -constexpr unsigned int mmCS_COPY_STATE = 0xA1F3; -constexpr unsigned int mmCUR_COLOR1__SI__VI = 0x1A6C; -constexpr unsigned int mmCUR_COLOR2__SI__VI = 0x1A6D; -constexpr unsigned int mmCUR_CONTROL__SI__VI = 0x1A66; -constexpr unsigned int mmCUR_HOT_SPOT__SI__VI = 0x1A6B; -constexpr unsigned int mmCUR_POSITION__SI__VI = 0x1A6A; -constexpr unsigned int mmCUR_SIZE__SI__VI = 0x1A68; -constexpr unsigned int mmCUR_SURFACE_ADDRESS_HIGH__SI__VI = 0x1A69; -constexpr unsigned int mmCUR_SURFACE_ADDRESS__SI__VI = 0x1A67; -constexpr unsigned int mmCUR_UPDATE__SI__VI = 0x1A6E; -constexpr unsigned int mmD1VGA_CONTROL__SI__VI = 0x00CC; -constexpr unsigned int mmD2VGA_CONTROL__SI__VI = 0x00CE; -constexpr unsigned int mmD3VGA_CONTROL__SI__VI = 0x00F8; -constexpr unsigned int mmD4VGA_CONTROL__SI__VI = 0x00F9; -constexpr unsigned int mmD5VGA_CONTROL__SI__VI = 0x00FA; -constexpr unsigned int mmD6VGA_CONTROL__SI__VI = 0x00FB; -constexpr unsigned int mmDAC_AUTODETECT_CONTROL2__SI = 0x19AF; -constexpr unsigned int mmDAC_AUTODETECT_CONTROL3__SI = 0x19B0; -constexpr unsigned int mmDAC_AUTODETECT_CONTROL__SI = 0x19AE; -constexpr unsigned int mmDAC_AUTODETECT_INT_CONTROL__SI = 0x19B2; -constexpr unsigned int mmDAC_AUTODETECT_STATUS__SI = 0x19B1; -constexpr unsigned int mmDAC_COMPARATOR_ENABLE__SI = 0x19B7; -constexpr unsigned int mmDAC_COMPARATOR_OUTPUT__SI = 0x19B8; -constexpr unsigned int mmDAC_CONTROL__SI = 0x19B6; -constexpr unsigned int mmDAC_CRC_CONTROL__SI = 0x19A7; -constexpr unsigned int mmDAC_CRC_EN__SI = 0x19A6; -constexpr unsigned int mmDAC_CRC_SIG_CONTROL_MASK__SI = 0x19A9; -constexpr unsigned int mmDAC_CRC_SIG_CONTROL__SI = 0x19AB; -constexpr unsigned int mmDAC_CRC_SIG_RGB_MASK__SI = 0x19A8; -constexpr unsigned int mmDAC_CRC_SIG_RGB__SI = 0x19AA; -constexpr unsigned int mmDAC_DATA__SI__VI = 0x00F2; -constexpr unsigned int mmDAC_DFT_CONFIG__SI = 0x19BA; -constexpr unsigned int mmDAC_ENABLE__SI = 0x19A4; -constexpr unsigned int mmDAC_FORCE_DATA__SI = 0x19B4; -constexpr unsigned int mmDAC_FORCE_OUTPUT_CNTL__SI = 0x19B3; -constexpr unsigned int mmDAC_MACRO_CNTL__SI = 0x1939; -constexpr unsigned int mmDAC_MASK__SI__VI = 0x00F1; -constexpr unsigned int mmDAC_POWERDOWN__SI = 0x19B5; -constexpr unsigned int mmDAC_PWR_CNTL__SI = 0x19B9; -constexpr unsigned int mmDAC_R_INDEX__SI__VI = 0x00F1; -constexpr unsigned int mmDAC_SOURCE_SELECT__SI = 0x19A5; -constexpr unsigned int mmDAC_STEREOSYNC_SELECT__SI = 0x19AD; -constexpr unsigned int mmDAC_SYNC_TRISTATE_CONTROL__SI = 0x19AC; -constexpr unsigned int mmDAC_W_INDEX__SI__VI = 0x00F2; -constexpr unsigned int mmDATA_FORMAT__SI = 0x1AC0; -constexpr unsigned int mmDBG_BYPASS_SRBM_ACCESS__CI = 0x14EB; -constexpr unsigned int mmDB_ALPHA_TO_MASK = 0xA2DC; -constexpr unsigned int mmDB_CGTT_CLK_CTRL_0__CI__VI = 0xF0A4; -constexpr unsigned int mmDB_CGTT_CLK_CTRL_0__SI = 0x261A; -constexpr unsigned int mmDB_COUNT_CONTROL = 0xA001; -constexpr unsigned int mmDB_CREDIT_LIMIT = 0x2614; -constexpr unsigned int mmDB_DEBUG = 0x260C; -constexpr unsigned int mmDB_DEBUG2 = 0x260D; -constexpr unsigned int mmDB_DEBUG3 = 0x260E; -constexpr unsigned int mmDB_DEBUG4 = 0x260F; -constexpr unsigned int mmDB_DEPTH_BOUNDS_MAX = 0xA009; -constexpr unsigned int mmDB_DEPTH_BOUNDS_MIN = 0xA008; -constexpr unsigned int mmDB_DEPTH_CLEAR = 0xA00B; -constexpr unsigned int mmDB_DEPTH_CONTROL = 0xA200; -constexpr unsigned int mmDB_DEPTH_INFO = 0xA00F; -constexpr unsigned int mmDB_DEPTH_SIZE = 0xA016; -constexpr unsigned int mmDB_DEPTH_SLICE = 0xA017; -constexpr unsigned int mmDB_DEPTH_VIEW = 0xA002; -constexpr unsigned int mmDB_EQAA = 0xA201; -constexpr unsigned int mmDB_FIFO_DEPTH1 = 0x2618; -constexpr unsigned int mmDB_FIFO_DEPTH2 = 0x2619; -constexpr unsigned int mmDB_FREE_CACHELINES = 0x2617; -constexpr unsigned int mmDB_HTILE_DATA_BASE = 0xA005; -constexpr unsigned int mmDB_HTILE_SURFACE = 0xA2AF; -constexpr unsigned int mmDB_OCCLUSION_COUNT0_HI__CI__VI = 0xC3C1; -constexpr unsigned int mmDB_OCCLUSION_COUNT0_LOW__CI__VI = 0xC3C0; -constexpr unsigned int mmDB_OCCLUSION_COUNT1_HI__CI__VI = 0xC3C3; -constexpr unsigned int mmDB_OCCLUSION_COUNT1_LOW__CI__VI = 0xC3C2; -constexpr unsigned int mmDB_OCCLUSION_COUNT2_HI__CI__VI = 0xC3C5; -constexpr unsigned int mmDB_OCCLUSION_COUNT2_LOW__CI__VI = 0xC3C4; -constexpr unsigned int mmDB_OCCLUSION_COUNT3_HI__CI__VI = 0xC3C7; -constexpr unsigned int mmDB_OCCLUSION_COUNT3_LOW__CI__VI = 0xC3C6; -constexpr unsigned int mmDB_PERFCOUNTER0_HI__CI__VI = 0xD441; -constexpr unsigned int mmDB_PERFCOUNTER0_HI__SI = 0x2602; -constexpr unsigned int mmDB_PERFCOUNTER0_LO__CI__VI = 0xD440; -constexpr unsigned int mmDB_PERFCOUNTER0_LO__SI = 0x2601; -constexpr unsigned int mmDB_PERFCOUNTER0_SELECT1__CI__VI = 0xDC41; -constexpr unsigned int mmDB_PERFCOUNTER0_SELECT__CI__VI = 0xDC40; -constexpr unsigned int mmDB_PERFCOUNTER0_SELECT__SI = 0x2600; -constexpr unsigned int mmDB_PERFCOUNTER1_HI__CI__VI = 0xD443; -constexpr unsigned int mmDB_PERFCOUNTER1_HI__SI = 0x2605; -constexpr unsigned int mmDB_PERFCOUNTER1_LO__CI__VI = 0xD442; -constexpr unsigned int mmDB_PERFCOUNTER1_LO__SI = 0x2604; -constexpr unsigned int mmDB_PERFCOUNTER1_SELECT1__CI__VI = 0xDC43; -constexpr unsigned int mmDB_PERFCOUNTER1_SELECT__CI__VI = 0xDC42; -constexpr unsigned int mmDB_PERFCOUNTER1_SELECT__SI = 0x2603; -constexpr unsigned int mmDB_PERFCOUNTER2_HI__CI__VI = 0xD445; -constexpr unsigned int mmDB_PERFCOUNTER2_HI__SI = 0x2608; -constexpr unsigned int mmDB_PERFCOUNTER2_LO__CI__VI = 0xD444; -constexpr unsigned int mmDB_PERFCOUNTER2_LO__SI = 0x2607; -constexpr unsigned int mmDB_PERFCOUNTER2_SELECT__CI__VI = 0xDC44; -constexpr unsigned int mmDB_PERFCOUNTER2_SELECT__SI = 0x2606; -constexpr unsigned int mmDB_PERFCOUNTER3_HI__CI__VI = 0xD447; -constexpr unsigned int mmDB_PERFCOUNTER3_HI__SI = 0x260B; -constexpr unsigned int mmDB_PERFCOUNTER3_LO__CI__VI = 0xD446; -constexpr unsigned int mmDB_PERFCOUNTER3_LO__SI = 0x260A; -constexpr unsigned int mmDB_PERFCOUNTER3_SELECT__CI__VI = 0xDC46; -constexpr unsigned int mmDB_PERFCOUNTER3_SELECT__SI = 0x2609; -constexpr unsigned int mmDB_PRELOAD_CONTROL = 0xA2B2; -constexpr unsigned int mmDB_READ_DEBUG_0 = 0x2620; -constexpr unsigned int mmDB_READ_DEBUG_1 = 0x2621; -constexpr unsigned int mmDB_READ_DEBUG_2 = 0x2622; -constexpr unsigned int mmDB_READ_DEBUG_3 = 0x2623; -constexpr unsigned int mmDB_READ_DEBUG_4 = 0x2624; -constexpr unsigned int mmDB_READ_DEBUG_5 = 0x2625; -constexpr unsigned int mmDB_READ_DEBUG_6 = 0x2626; -constexpr unsigned int mmDB_READ_DEBUG_7 = 0x2627; -constexpr unsigned int mmDB_READ_DEBUG_8 = 0x2628; -constexpr unsigned int mmDB_READ_DEBUG_9 = 0x2629; -constexpr unsigned int mmDB_READ_DEBUG_A = 0x262A; -constexpr unsigned int mmDB_READ_DEBUG_B = 0x262B; -constexpr unsigned int mmDB_READ_DEBUG_C = 0x262C; -constexpr unsigned int mmDB_READ_DEBUG_D = 0x262D; -constexpr unsigned int mmDB_READ_DEBUG_E = 0x262E; -constexpr unsigned int mmDB_READ_DEBUG_F = 0x262F; -constexpr unsigned int mmDB_RENDER_CONTROL = 0xA000; -constexpr unsigned int mmDB_RENDER_OVERRIDE = 0xA003; -constexpr unsigned int mmDB_RENDER_OVERRIDE2 = 0xA004; -constexpr unsigned int mmDB_RING_CONTROL__CI__VI = 0x261B; -constexpr unsigned int mmDB_SHADER_CONTROL = 0xA203; -constexpr unsigned int mmDB_SRESULTS_COMPARE_STATE0 = 0xA2B0; -constexpr unsigned int mmDB_SRESULTS_COMPARE_STATE1 = 0xA2B1; -constexpr unsigned int mmDB_STENCILREFMASK = 0xA10C; -constexpr unsigned int mmDB_STENCILREFMASK_BF = 0xA10D; -constexpr unsigned int mmDB_STENCIL_CLEAR = 0xA00A; -constexpr unsigned int mmDB_STENCIL_CONTROL = 0xA10B; -constexpr unsigned int mmDB_STENCIL_INFO = 0xA011; -constexpr unsigned int mmDB_STENCIL_READ_BASE = 0xA013; -constexpr unsigned int mmDB_STENCIL_WRITE_BASE = 0xA015; -constexpr unsigned int mmDB_SUBTILE_CONTROL = 0x2616; -constexpr unsigned int mmDB_WATERMARKS = 0x2615; -constexpr unsigned int mmDB_ZPASS_COUNT_HI__CI__VI = 0xC3FF; -constexpr unsigned int mmDB_ZPASS_COUNT_HI__SI = 0x261D; -constexpr unsigned int mmDB_ZPASS_COUNT_LOW__CI__VI = 0xC3FE; -constexpr unsigned int mmDB_ZPASS_COUNT_LOW__SI = 0x261C; -constexpr unsigned int mmDB_Z_INFO = 0xA010; -constexpr unsigned int mmDB_Z_READ_BASE = 0xA012; -constexpr unsigned int mmDB_Z_WRITE_BASE = 0xA014; -constexpr unsigned int mmDCCG_AUDIO_DTO0_MODULE__SI = 0x0154; -constexpr unsigned int mmDCCG_AUDIO_DTO0_PHASE__SI = 0x0153; -constexpr unsigned int mmDCCG_GATE_DISABLE_CNTL__SI = 0x011F; -constexpr unsigned int mmDCCG_TEST_CLK_SEL__SI = 0x0147; -constexpr unsigned int mmDCCG_TEST_DEBUG_DATA__SI = 0x0159; -constexpr unsigned int mmDCCG_TEST_DEBUG_INDEX__SI = 0x0158; -constexpr unsigned int mmDCCG_VPCLK_CNTL__SI = 0x015E; -constexpr unsigned int mmDCDEBUG_BUS_CLK1_SEL__SI = 0x1860; -constexpr unsigned int mmDCDEBUG_BUS_CLK2_SEL__SI = 0x1861; -constexpr unsigned int mmDCDEBUG_BUS_CLK3_SEL__SI = 0x1862; -constexpr unsigned int mmDCDEBUG_BUS_CLK4_SEL__SI = 0x1863; -constexpr unsigned int mmDCDEBUG_OUT_CNTL__SI = 0x186B; -constexpr unsigned int mmDCDEBUG_OUT_PIN_OVERRIDE__SI = 0x186A; -constexpr unsigned int mmDCIO_DEBUG__SI = 0x196F; -constexpr unsigned int mmDCIO_IMPCAL_CNTL_AB__SI = 0x194C; -constexpr unsigned int mmDCIO_IMPCAL_CNTL_CD__SI = 0x194F; -constexpr unsigned int mmDCIO_IMPCAL_CNTL_EF__SI = 0x1952; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION__SI = 0x1984; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT__SI = 0x1986; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION__SI = 0x1990; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT__SI = 0x1992; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION__SI = 0x199C; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT__SI = 0x199E; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION__SI = 0x19C4; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT__SI = 0x19C6; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION__SI = 0x19D0; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT__SI = 0x19D2; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION__SI = 0x19DC; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT__SI = 0x19DE; -constexpr unsigned int mmDCI_TEST_DEBUG_DATA__SI = 0x0321; -constexpr unsigned int mmDCI_TEST_DEBUG_INDEX__SI = 0x0320; -constexpr unsigned int mmDCP0_CUR_COLOR1__SI__VI = 0x1A6C; -constexpr unsigned int mmDCP0_CUR_COLOR2__SI__VI = 0x1A6D; -constexpr unsigned int mmDCP0_CUR_CONTROL__SI__VI = 0x1A66; -constexpr unsigned int mmDCP0_CUR_HOT_SPOT__SI__VI = 0x1A6B; -constexpr unsigned int mmDCP0_CUR_POSITION__SI__VI = 0x1A6A; -constexpr unsigned int mmDCP0_CUR_SIZE__SI__VI = 0x1A68; -constexpr unsigned int mmDCP0_CUR_SURFACE_ADDRESS_HIGH__SI__VI = 0x1A69; -constexpr unsigned int mmDCP0_CUR_SURFACE_ADDRESS__SI__VI = 0x1A67; -constexpr unsigned int mmDCP0_CUR_UPDATE__SI__VI = 0x1A6E; -constexpr unsigned int mmDCP0_DCP_CRC_CONTROL__SI__VI = 0x1A87; -constexpr unsigned int mmDCP0_DCP_CRC_CURRENT__SI__VI = 0x1A89; -constexpr unsigned int mmDCP0_DCP_CRC_LAST__SI__VI = 0x1A8B; -constexpr unsigned int mmDCP0_DCP_CRC_MASK__SI__VI = 0x1A88; -constexpr unsigned int mmDCP0_DCP_DEBUG__SI__VI = 0x1A8D; -constexpr unsigned int mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI__VI = 0x1A91; -constexpr unsigned int mmDCP0_DCP_TEST_DEBUG_DATA__SI__VI = 0x1A96; -constexpr unsigned int mmDCP0_DCP_TEST_DEBUG_INDEX__SI__VI = 0x1A95; -constexpr unsigned int mmDCP0_DC_LUT_30_COLOR__SI__VI = 0x1A7C; -constexpr unsigned int mmDCP0_DC_LUT_AUTOFILL__SI__VI = 0x1A7F; -constexpr unsigned int mmDCP0_DC_LUT_BLACK_OFFSET_BLUE__SI__VI = 0x1A81; -constexpr unsigned int mmDCP0_DC_LUT_BLACK_OFFSET_GREEN__SI__VI = 0x1A82; -constexpr unsigned int mmDCP0_DC_LUT_BLACK_OFFSET_RED__SI__VI = 0x1A83; -constexpr unsigned int mmDCP0_DC_LUT_CONTROL__SI__VI = 0x1A80; -constexpr unsigned int mmDCP0_DC_LUT_PWL_DATA__SI__VI = 0x1A7B; -constexpr unsigned int mmDCP0_DC_LUT_RW_INDEX__SI__VI = 0x1A79; -constexpr unsigned int mmDCP0_DC_LUT_RW_MODE__SI__VI = 0x1A78; -constexpr unsigned int mmDCP0_DC_LUT_SEQ_COLOR__SI__VI = 0x1A7A; -constexpr unsigned int mmDCP0_DC_LUT_WHITE_OFFSET_BLUE__SI__VI = 0x1A84; -constexpr unsigned int mmDCP0_DC_LUT_WHITE_OFFSET_GREEN__SI__VI = 0x1A85; -constexpr unsigned int mmDCP0_DC_LUT_WHITE_OFFSET_RED__SI__VI = 0x1A86; -constexpr unsigned int mmDCP0_DC_LUT_WRITE_EN_MASK__SI__VI = 0x1A7E; -constexpr unsigned int mmDCP0_GRPH_COMPRESS_PITCH__SI__VI = 0x1A1A; -constexpr unsigned int mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI__VI = 0x1A1B; -constexpr unsigned int mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS__SI__VI = 0x1A19; -constexpr unsigned int mmDCP0_GRPH_CONTROL = 0x1A01; -constexpr unsigned int mmDCP0_GRPH_DFQ_CONTROL__SI__VI = 0x1A14; -constexpr unsigned int mmDCP0_GRPH_DFQ_STATUS__SI__VI = 0x1A15; -constexpr unsigned int mmDCP0_GRPH_ENABLE__SI__VI = 0x1A00; -constexpr unsigned int mmDCP0_GRPH_FLIP_CONTROL = 0x1A12; -constexpr unsigned int mmDCP0_GRPH_INTERRUPT_CONTROL__SI__VI = 0x1A17; -constexpr unsigned int mmDCP0_GRPH_INTERRUPT_STATUS__SI__VI = 0x1A16; -constexpr unsigned int mmDCP0_GRPH_LUT_10BIT_BYPASS__SI__VI = 0x1A02; -constexpr unsigned int mmDCP0_GRPH_PITCH = 0x1A06; -constexpr unsigned int mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS = 0x1A04; -constexpr unsigned int mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH = 0x1A07; -constexpr unsigned int mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI__VI = 0x1A08; -constexpr unsigned int mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS__SI__VI = 0x1A05; -constexpr unsigned int mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI__VI = 0x1A18; -constexpr unsigned int mmDCP0_GRPH_SURFACE_ADDRESS_INUSE__SI__VI = 0x1A13; -constexpr unsigned int mmDCP0_GRPH_SURFACE_OFFSET_X__SI__VI = 0x1A09; -constexpr unsigned int mmDCP0_GRPH_SURFACE_OFFSET_Y__SI__VI = 0x1A0A; -constexpr unsigned int mmDCP0_GRPH_SWAP_CNTL__SI__VI = 0x1A03; -constexpr unsigned int mmDCP0_GRPH_UPDATE = 0x1A11; -constexpr unsigned int mmDCP0_GRPH_X_END__SI__VI = 0x1A0D; -constexpr unsigned int mmDCP0_GRPH_X_START__SI__VI = 0x1A0B; -constexpr unsigned int mmDCP0_GRPH_Y_END__SI__VI = 0x1A0E; -constexpr unsigned int mmDCP0_GRPH_Y_START__SI__VI = 0x1A0C; -constexpr unsigned int mmDCP0_OVLSCL_EDGE_PIXEL_CNTL__SI__VI = 0x1A2C; -constexpr unsigned int mmDCP0_OVL_CONTROL1__SI__VI = 0x1A1D; -constexpr unsigned int mmDCP0_OVL_CONTROL2__SI__VI = 0x1A1E; -constexpr unsigned int mmDCP0_OVL_DFQ_CONTROL__SI__VI = 0x1A29; -constexpr unsigned int mmDCP0_OVL_DFQ_STATUS__SI__VI = 0x1A2A; -constexpr unsigned int mmDCP0_OVL_ENABLE__SI__VI = 0x1A1C; -constexpr unsigned int mmDCP0_OVL_END__SI__VI = 0x1A26; -constexpr unsigned int mmDCP0_OVL_PITCH__SI__VI = 0x1A21; -constexpr unsigned int mmDCP0_OVL_START__SI__VI = 0x1A25; -constexpr unsigned int mmDCP0_OVL_SURFACE_ADDRESS = 0x1A20; -constexpr unsigned int mmDCP0_OVL_SURFACE_ADDRESS_HIGH = 0x1A22; -constexpr unsigned int mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI__VI = 0x1A2B; -constexpr unsigned int mmDCP0_OVL_SURFACE_ADDRESS_INUSE__SI__VI = 0x1A28; -constexpr unsigned int mmDCP0_OVL_SURFACE_OFFSET_X__SI__VI = 0x1A23; -constexpr unsigned int mmDCP0_OVL_SURFACE_OFFSET_Y__SI__VI = 0x1A24; -constexpr unsigned int mmDCP0_OVL_SWAP_CNTL__SI__VI = 0x1A1F; -constexpr unsigned int mmDCP0_OVL_UPDATE__SI__VI = 0x1A27; -constexpr unsigned int mmDCP1_CUR_COLOR1__SI = 0x1D6C; -constexpr unsigned int mmDCP1_CUR_COLOR2__SI = 0x1D6D; -constexpr unsigned int mmDCP1_CUR_CONTROL__SI = 0x1D66; -constexpr unsigned int mmDCP1_CUR_HOT_SPOT__SI = 0x1D6B; -constexpr unsigned int mmDCP1_CUR_POSITION__SI = 0x1D6A; -constexpr unsigned int mmDCP1_CUR_SIZE__SI = 0x1D68; -constexpr unsigned int mmDCP1_CUR_SURFACE_ADDRESS_HIGH__SI = 0x1D69; -constexpr unsigned int mmDCP1_CUR_SURFACE_ADDRESS__SI = 0x1D67; -constexpr unsigned int mmDCP1_CUR_UPDATE__SI = 0x1D6E; -constexpr unsigned int mmDCP1_DCP_CRC_CONTROL__SI = 0x1D87; -constexpr unsigned int mmDCP1_DCP_CRC_CURRENT__SI = 0x1D89; -constexpr unsigned int mmDCP1_DCP_CRC_LAST__SI = 0x1D8B; -constexpr unsigned int mmDCP1_DCP_CRC_MASK__SI = 0x1D88; -constexpr unsigned int mmDCP1_DCP_DEBUG__SI = 0x1D8D; -constexpr unsigned int mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI = 0x1D91; -constexpr unsigned int mmDCP1_DCP_TEST_DEBUG_DATA__SI = 0x1D96; -constexpr unsigned int mmDCP1_DCP_TEST_DEBUG_INDEX__SI = 0x1D95; -constexpr unsigned int mmDCP1_DC_LUT_30_COLOR__SI = 0x1D7C; -constexpr unsigned int mmDCP1_DC_LUT_AUTOFILL__SI = 0x1D7F; -constexpr unsigned int mmDCP1_DC_LUT_BLACK_OFFSET_BLUE__SI = 0x1D81; -constexpr unsigned int mmDCP1_DC_LUT_BLACK_OFFSET_GREEN__SI = 0x1D82; -constexpr unsigned int mmDCP1_DC_LUT_BLACK_OFFSET_RED__SI = 0x1D83; -constexpr unsigned int mmDCP1_DC_LUT_CONTROL__SI = 0x1D80; -constexpr unsigned int mmDCP1_DC_LUT_PWL_DATA__SI = 0x1D7B; -constexpr unsigned int mmDCP1_DC_LUT_RW_INDEX__SI = 0x1D79; -constexpr unsigned int mmDCP1_DC_LUT_RW_MODE__SI = 0x1D78; -constexpr unsigned int mmDCP1_DC_LUT_SEQ_COLOR__SI = 0x1D7A; -constexpr unsigned int mmDCP1_DC_LUT_WHITE_OFFSET_BLUE__SI = 0x1D84; -constexpr unsigned int mmDCP1_DC_LUT_WHITE_OFFSET_GREEN__SI = 0x1D85; -constexpr unsigned int mmDCP1_DC_LUT_WHITE_OFFSET_RED__SI = 0x1D86; -constexpr unsigned int mmDCP1_DC_LUT_WRITE_EN_MASK__SI = 0x1D7E; -constexpr unsigned int mmDCP1_GRPH_COMPRESS_PITCH__SI = 0x1D1A; -constexpr unsigned int mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI = 0x1D1B; -constexpr unsigned int mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS__SI = 0x1D19; -constexpr unsigned int mmDCP1_GRPH_DFQ_CONTROL__SI = 0x1D14; -constexpr unsigned int mmDCP1_GRPH_DFQ_STATUS__SI = 0x1D15; -constexpr unsigned int mmDCP1_GRPH_ENABLE__SI = 0x1D00; -constexpr unsigned int mmDCP1_GRPH_INTERRUPT_CONTROL__SI = 0x1D17; -constexpr unsigned int mmDCP1_GRPH_INTERRUPT_STATUS__SI = 0x1D16; -constexpr unsigned int mmDCP1_GRPH_LUT_10BIT_BYPASS__SI = 0x1D02; -constexpr unsigned int mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI = 0x1D07; -constexpr unsigned int mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI = 0x1D08; -constexpr unsigned int mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS__SI = 0x1D05; -constexpr unsigned int mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI = 0x1D18; -constexpr unsigned int mmDCP1_GRPH_SURFACE_ADDRESS_INUSE__SI = 0x1D13; -constexpr unsigned int mmDCP1_GRPH_SURFACE_OFFSET_X__SI = 0x1D09; -constexpr unsigned int mmDCP1_GRPH_SURFACE_OFFSET_Y__SI = 0x1D0A; -constexpr unsigned int mmDCP1_GRPH_SWAP_CNTL__SI = 0x1D03; -constexpr unsigned int mmDCP1_GRPH_X_END__SI = 0x1D0D; -constexpr unsigned int mmDCP1_GRPH_X_START__SI = 0x1D0B; -constexpr unsigned int mmDCP1_GRPH_Y_END__SI = 0x1D0E; -constexpr unsigned int mmDCP1_GRPH_Y_START__SI = 0x1D0C; -constexpr unsigned int mmDCP1_OVLSCL_EDGE_PIXEL_CNTL__SI = 0x1D2C; -constexpr unsigned int mmDCP1_OVL_CONTROL1__SI = 0x1D1D; -constexpr unsigned int mmDCP1_OVL_CONTROL2__SI = 0x1D1E; -constexpr unsigned int mmDCP1_OVL_DFQ_CONTROL__SI = 0x1D29; -constexpr unsigned int mmDCP1_OVL_DFQ_STATUS__SI = 0x1D2A; -constexpr unsigned int mmDCP1_OVL_ENABLE__SI = 0x1D1C; -constexpr unsigned int mmDCP1_OVL_END__SI = 0x1D26; -constexpr unsigned int mmDCP1_OVL_PITCH__SI = 0x1D21; -constexpr unsigned int mmDCP1_OVL_START__SI = 0x1D25; -constexpr unsigned int mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI = 0x1D2B; -constexpr unsigned int mmDCP1_OVL_SURFACE_ADDRESS_HIGH__SI = 0x1D22; -constexpr unsigned int mmDCP1_OVL_SURFACE_ADDRESS_INUSE__SI = 0x1D28; -constexpr unsigned int mmDCP1_OVL_SURFACE_OFFSET_X__SI = 0x1D23; -constexpr unsigned int mmDCP1_OVL_SURFACE_OFFSET_Y__SI = 0x1D24; -constexpr unsigned int mmDCP1_OVL_SWAP_CNTL__SI = 0x1D1F; -constexpr unsigned int mmDCP1_OVL_UPDATE__SI = 0x1D27; -constexpr unsigned int mmDCP2_CUR_COLOR1__SI = 0x406C; -constexpr unsigned int mmDCP2_CUR_COLOR2__SI = 0x406D; -constexpr unsigned int mmDCP2_CUR_CONTROL__SI = 0x4066; -constexpr unsigned int mmDCP2_CUR_HOT_SPOT__SI = 0x406B; -constexpr unsigned int mmDCP2_CUR_POSITION__SI = 0x406A; -constexpr unsigned int mmDCP2_CUR_SIZE__SI = 0x4068; -constexpr unsigned int mmDCP2_CUR_SURFACE_ADDRESS_HIGH__SI = 0x4069; -constexpr unsigned int mmDCP2_CUR_SURFACE_ADDRESS__SI = 0x4067; -constexpr unsigned int mmDCP2_CUR_UPDATE__SI = 0x406E; -constexpr unsigned int mmDCP2_DCP_CRC_CONTROL__SI = 0x4087; -constexpr unsigned int mmDCP2_DCP_CRC_CURRENT__SI = 0x4089; -constexpr unsigned int mmDCP2_DCP_CRC_LAST__SI = 0x408B; -constexpr unsigned int mmDCP2_DCP_CRC_MASK__SI = 0x4088; -constexpr unsigned int mmDCP2_DCP_DEBUG__SI = 0x408D; -constexpr unsigned int mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI = 0x4091; -constexpr unsigned int mmDCP2_DCP_TEST_DEBUG_DATA__SI = 0x4096; -constexpr unsigned int mmDCP2_DCP_TEST_DEBUG_INDEX__SI = 0x4095; -constexpr unsigned int mmDCP2_DC_LUT_30_COLOR__SI = 0x407C; -constexpr unsigned int mmDCP2_DC_LUT_AUTOFILL__SI = 0x407F; -constexpr unsigned int mmDCP2_DC_LUT_BLACK_OFFSET_BLUE__SI = 0x4081; -constexpr unsigned int mmDCP2_DC_LUT_BLACK_OFFSET_GREEN__SI = 0x4082; -constexpr unsigned int mmDCP2_DC_LUT_BLACK_OFFSET_RED__SI = 0x4083; -constexpr unsigned int mmDCP2_DC_LUT_CONTROL__SI = 0x4080; -constexpr unsigned int mmDCP2_DC_LUT_PWL_DATA__SI = 0x407B; -constexpr unsigned int mmDCP2_DC_LUT_RW_INDEX__SI = 0x4079; -constexpr unsigned int mmDCP2_DC_LUT_RW_MODE__SI = 0x4078; -constexpr unsigned int mmDCP2_DC_LUT_SEQ_COLOR__SI = 0x407A; -constexpr unsigned int mmDCP2_DC_LUT_WHITE_OFFSET_BLUE__SI = 0x4084; -constexpr unsigned int mmDCP2_DC_LUT_WHITE_OFFSET_GREEN__SI = 0x4085; -constexpr unsigned int mmDCP2_DC_LUT_WHITE_OFFSET_RED__SI = 0x4086; -constexpr unsigned int mmDCP2_DC_LUT_WRITE_EN_MASK__SI = 0x407E; -constexpr unsigned int mmDCP2_GRPH_COMPRESS_PITCH__SI = 0x401A; -constexpr unsigned int mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI = 0x401B; -constexpr unsigned int mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS__SI = 0x4019; -constexpr unsigned int mmDCP2_GRPH_DFQ_CONTROL__SI = 0x4014; -constexpr unsigned int mmDCP2_GRPH_DFQ_STATUS__SI = 0x4015; -constexpr unsigned int mmDCP2_GRPH_ENABLE__SI = 0x4000; -constexpr unsigned int mmDCP2_GRPH_INTERRUPT_CONTROL__SI = 0x4017; -constexpr unsigned int mmDCP2_GRPH_INTERRUPT_STATUS__SI = 0x4016; -constexpr unsigned int mmDCP2_GRPH_LUT_10BIT_BYPASS__SI = 0x4002; -constexpr unsigned int mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI = 0x4007; -constexpr unsigned int mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI = 0x4008; -constexpr unsigned int mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS__SI = 0x4005; -constexpr unsigned int mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI = 0x4018; -constexpr unsigned int mmDCP2_GRPH_SURFACE_ADDRESS_INUSE__SI = 0x4013; -constexpr unsigned int mmDCP2_GRPH_SURFACE_OFFSET_X__SI = 0x4009; -constexpr unsigned int mmDCP2_GRPH_SURFACE_OFFSET_Y__SI = 0x400A; -constexpr unsigned int mmDCP2_GRPH_SWAP_CNTL__SI = 0x4003; -constexpr unsigned int mmDCP2_GRPH_X_END__SI = 0x400D; -constexpr unsigned int mmDCP2_GRPH_X_START__SI = 0x400B; -constexpr unsigned int mmDCP2_GRPH_Y_END__SI = 0x400E; -constexpr unsigned int mmDCP2_GRPH_Y_START__SI = 0x400C; -constexpr unsigned int mmDCP2_OVLSCL_EDGE_PIXEL_CNTL__SI = 0x402C; -constexpr unsigned int mmDCP2_OVL_CONTROL1__SI = 0x401D; -constexpr unsigned int mmDCP2_OVL_CONTROL2__SI = 0x401E; -constexpr unsigned int mmDCP2_OVL_DFQ_CONTROL__SI = 0x4029; -constexpr unsigned int mmDCP2_OVL_DFQ_STATUS__SI = 0x402A; -constexpr unsigned int mmDCP2_OVL_ENABLE__SI = 0x401C; -constexpr unsigned int mmDCP2_OVL_END__SI = 0x4026; -constexpr unsigned int mmDCP2_OVL_PITCH__SI = 0x4021; -constexpr unsigned int mmDCP2_OVL_START__SI = 0x4025; -constexpr unsigned int mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI = 0x402B; -constexpr unsigned int mmDCP2_OVL_SURFACE_ADDRESS_HIGH__SI = 0x4022; -constexpr unsigned int mmDCP2_OVL_SURFACE_ADDRESS_INUSE__SI = 0x4028; -constexpr unsigned int mmDCP2_OVL_SURFACE_OFFSET_X__SI = 0x4023; -constexpr unsigned int mmDCP2_OVL_SURFACE_OFFSET_Y__SI = 0x4024; -constexpr unsigned int mmDCP2_OVL_SWAP_CNTL__SI = 0x401F; -constexpr unsigned int mmDCP2_OVL_UPDATE__SI = 0x4027; -constexpr unsigned int mmDCP3_CUR_COLOR1__SI = 0x436C; -constexpr unsigned int mmDCP3_CUR_COLOR2__SI = 0x436D; -constexpr unsigned int mmDCP3_CUR_CONTROL__SI = 0x4366; -constexpr unsigned int mmDCP3_CUR_HOT_SPOT__SI = 0x436B; -constexpr unsigned int mmDCP3_CUR_POSITION__SI = 0x436A; -constexpr unsigned int mmDCP3_CUR_SIZE__SI = 0x4368; -constexpr unsigned int mmDCP3_CUR_SURFACE_ADDRESS_HIGH__SI = 0x4369; -constexpr unsigned int mmDCP3_CUR_SURFACE_ADDRESS__SI = 0x4367; -constexpr unsigned int mmDCP3_CUR_UPDATE__SI = 0x436E; -constexpr unsigned int mmDCP3_DCP_CRC_CONTROL__SI = 0x4387; -constexpr unsigned int mmDCP3_DCP_CRC_CURRENT__SI = 0x4389; -constexpr unsigned int mmDCP3_DCP_CRC_LAST__SI = 0x438B; -constexpr unsigned int mmDCP3_DCP_CRC_MASK__SI = 0x4388; -constexpr unsigned int mmDCP3_DCP_DEBUG__SI = 0x438D; -constexpr unsigned int mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI = 0x4391; -constexpr unsigned int mmDCP3_DCP_TEST_DEBUG_DATA__SI = 0x4396; -constexpr unsigned int mmDCP3_DCP_TEST_DEBUG_INDEX__SI = 0x4395; -constexpr unsigned int mmDCP3_DC_LUT_30_COLOR__SI = 0x437C; -constexpr unsigned int mmDCP3_DC_LUT_AUTOFILL__SI = 0x437F; -constexpr unsigned int mmDCP3_DC_LUT_BLACK_OFFSET_BLUE__SI = 0x4381; -constexpr unsigned int mmDCP3_DC_LUT_BLACK_OFFSET_GREEN__SI = 0x4382; -constexpr unsigned int mmDCP3_DC_LUT_BLACK_OFFSET_RED__SI = 0x4383; -constexpr unsigned int mmDCP3_DC_LUT_CONTROL__SI = 0x4380; -constexpr unsigned int mmDCP3_DC_LUT_PWL_DATA__SI = 0x437B; -constexpr unsigned int mmDCP3_DC_LUT_RW_INDEX__SI = 0x4379; -constexpr unsigned int mmDCP3_DC_LUT_RW_MODE__SI = 0x4378; -constexpr unsigned int mmDCP3_DC_LUT_SEQ_COLOR__SI = 0x437A; -constexpr unsigned int mmDCP3_DC_LUT_WHITE_OFFSET_BLUE__SI = 0x4384; -constexpr unsigned int mmDCP3_DC_LUT_WHITE_OFFSET_GREEN__SI = 0x4385; -constexpr unsigned int mmDCP3_DC_LUT_WHITE_OFFSET_RED__SI = 0x4386; -constexpr unsigned int mmDCP3_DC_LUT_WRITE_EN_MASK__SI = 0x437E; -constexpr unsigned int mmDCP3_GRPH_COMPRESS_PITCH__SI = 0x431A; -constexpr unsigned int mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI = 0x431B; -constexpr unsigned int mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS__SI = 0x4319; -constexpr unsigned int mmDCP3_GRPH_DFQ_CONTROL__SI = 0x4314; -constexpr unsigned int mmDCP3_GRPH_DFQ_STATUS__SI = 0x4315; -constexpr unsigned int mmDCP3_GRPH_ENABLE__SI = 0x4300; -constexpr unsigned int mmDCP3_GRPH_INTERRUPT_CONTROL__SI = 0x4317; -constexpr unsigned int mmDCP3_GRPH_INTERRUPT_STATUS__SI = 0x4316; -constexpr unsigned int mmDCP3_GRPH_LUT_10BIT_BYPASS__SI = 0x4302; -constexpr unsigned int mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI = 0x4307; -constexpr unsigned int mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI = 0x4308; -constexpr unsigned int mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS__SI = 0x4305; -constexpr unsigned int mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI = 0x4318; -constexpr unsigned int mmDCP3_GRPH_SURFACE_ADDRESS_INUSE__SI = 0x4313; -constexpr unsigned int mmDCP3_GRPH_SURFACE_OFFSET_X__SI = 0x4309; -constexpr unsigned int mmDCP3_GRPH_SURFACE_OFFSET_Y__SI = 0x430A; -constexpr unsigned int mmDCP3_GRPH_SWAP_CNTL__SI = 0x4303; -constexpr unsigned int mmDCP3_GRPH_X_END__SI = 0x430D; -constexpr unsigned int mmDCP3_GRPH_X_START__SI = 0x430B; -constexpr unsigned int mmDCP3_GRPH_Y_END__SI = 0x430E; -constexpr unsigned int mmDCP3_GRPH_Y_START__SI = 0x430C; -constexpr unsigned int mmDCP3_OVLSCL_EDGE_PIXEL_CNTL__SI = 0x432C; -constexpr unsigned int mmDCP3_OVL_CONTROL1__SI = 0x431D; -constexpr unsigned int mmDCP3_OVL_CONTROL2__SI = 0x431E; -constexpr unsigned int mmDCP3_OVL_DFQ_CONTROL__SI = 0x4329; -constexpr unsigned int mmDCP3_OVL_DFQ_STATUS__SI = 0x432A; -constexpr unsigned int mmDCP3_OVL_ENABLE__SI = 0x431C; -constexpr unsigned int mmDCP3_OVL_END__SI = 0x4326; -constexpr unsigned int mmDCP3_OVL_PITCH__SI = 0x4321; -constexpr unsigned int mmDCP3_OVL_START__SI = 0x4325; -constexpr unsigned int mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI = 0x432B; -constexpr unsigned int mmDCP3_OVL_SURFACE_ADDRESS_HIGH__SI = 0x4322; -constexpr unsigned int mmDCP3_OVL_SURFACE_ADDRESS_INUSE__SI = 0x4328; -constexpr unsigned int mmDCP3_OVL_SURFACE_OFFSET_X__SI = 0x4323; -constexpr unsigned int mmDCP3_OVL_SURFACE_OFFSET_Y__SI = 0x4324; -constexpr unsigned int mmDCP3_OVL_SWAP_CNTL__SI = 0x431F; -constexpr unsigned int mmDCP3_OVL_UPDATE__SI = 0x4327; -constexpr unsigned int mmDCP4_CUR_COLOR1__SI = 0x466C; -constexpr unsigned int mmDCP4_CUR_COLOR2__SI = 0x466D; -constexpr unsigned int mmDCP4_CUR_CONTROL__SI = 0x4666; -constexpr unsigned int mmDCP4_CUR_HOT_SPOT__SI = 0x466B; -constexpr unsigned int mmDCP4_CUR_POSITION__SI = 0x466A; -constexpr unsigned int mmDCP4_CUR_SIZE__SI = 0x4668; -constexpr unsigned int mmDCP4_CUR_SURFACE_ADDRESS_HIGH__SI = 0x4669; -constexpr unsigned int mmDCP4_CUR_SURFACE_ADDRESS__SI = 0x4667; -constexpr unsigned int mmDCP4_CUR_UPDATE__SI = 0x466E; -constexpr unsigned int mmDCP4_DCP_CRC_CONTROL__SI = 0x4687; -constexpr unsigned int mmDCP4_DCP_CRC_CURRENT__SI = 0x4689; -constexpr unsigned int mmDCP4_DCP_CRC_LAST__SI = 0x468B; -constexpr unsigned int mmDCP4_DCP_CRC_MASK__SI = 0x4688; -constexpr unsigned int mmDCP4_DCP_DEBUG__SI = 0x468D; -constexpr unsigned int mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI = 0x4691; -constexpr unsigned int mmDCP4_DCP_TEST_DEBUG_DATA__SI = 0x4696; -constexpr unsigned int mmDCP4_DCP_TEST_DEBUG_INDEX__SI = 0x4695; -constexpr unsigned int mmDCP4_DC_LUT_30_COLOR__SI = 0x467C; -constexpr unsigned int mmDCP4_DC_LUT_AUTOFILL__SI = 0x467F; -constexpr unsigned int mmDCP4_DC_LUT_BLACK_OFFSET_BLUE__SI = 0x4681; -constexpr unsigned int mmDCP4_DC_LUT_BLACK_OFFSET_GREEN__SI = 0x4682; -constexpr unsigned int mmDCP4_DC_LUT_BLACK_OFFSET_RED__SI = 0x4683; -constexpr unsigned int mmDCP4_DC_LUT_CONTROL__SI = 0x4680; -constexpr unsigned int mmDCP4_DC_LUT_PWL_DATA__SI = 0x467B; -constexpr unsigned int mmDCP4_DC_LUT_RW_INDEX__SI = 0x4679; -constexpr unsigned int mmDCP4_DC_LUT_RW_MODE__SI = 0x4678; -constexpr unsigned int mmDCP4_DC_LUT_SEQ_COLOR__SI = 0x467A; -constexpr unsigned int mmDCP4_DC_LUT_WHITE_OFFSET_BLUE__SI = 0x4684; -constexpr unsigned int mmDCP4_DC_LUT_WHITE_OFFSET_GREEN__SI = 0x4685; -constexpr unsigned int mmDCP4_DC_LUT_WHITE_OFFSET_RED__SI = 0x4686; -constexpr unsigned int mmDCP4_DC_LUT_WRITE_EN_MASK__SI = 0x467E; -constexpr unsigned int mmDCP4_GRPH_COMPRESS_PITCH__SI = 0x461A; -constexpr unsigned int mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI = 0x461B; -constexpr unsigned int mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS__SI = 0x4619; -constexpr unsigned int mmDCP4_GRPH_DFQ_CONTROL__SI = 0x4614; -constexpr unsigned int mmDCP4_GRPH_DFQ_STATUS__SI = 0x4615; -constexpr unsigned int mmDCP4_GRPH_ENABLE__SI = 0x4600; -constexpr unsigned int mmDCP4_GRPH_INTERRUPT_CONTROL__SI = 0x4617; -constexpr unsigned int mmDCP4_GRPH_INTERRUPT_STATUS__SI = 0x4616; -constexpr unsigned int mmDCP4_GRPH_LUT_10BIT_BYPASS__SI = 0x4602; -constexpr unsigned int mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI = 0x4607; -constexpr unsigned int mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI = 0x4608; -constexpr unsigned int mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS__SI = 0x4605; -constexpr unsigned int mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI = 0x4618; -constexpr unsigned int mmDCP4_GRPH_SURFACE_ADDRESS_INUSE__SI = 0x4613; -constexpr unsigned int mmDCP4_GRPH_SURFACE_OFFSET_X__SI = 0x4609; -constexpr unsigned int mmDCP4_GRPH_SURFACE_OFFSET_Y__SI = 0x460A; -constexpr unsigned int mmDCP4_GRPH_SWAP_CNTL__SI = 0x4603; -constexpr unsigned int mmDCP4_GRPH_X_END__SI = 0x460D; -constexpr unsigned int mmDCP4_GRPH_X_START__SI = 0x460B; -constexpr unsigned int mmDCP4_GRPH_Y_END__SI = 0x460E; -constexpr unsigned int mmDCP4_GRPH_Y_START__SI = 0x460C; -constexpr unsigned int mmDCP4_OVLSCL_EDGE_PIXEL_CNTL__SI = 0x462C; -constexpr unsigned int mmDCP4_OVL_CONTROL1__SI = 0x461D; -constexpr unsigned int mmDCP4_OVL_CONTROL2__SI = 0x461E; -constexpr unsigned int mmDCP4_OVL_DFQ_CONTROL__SI = 0x4629; -constexpr unsigned int mmDCP4_OVL_DFQ_STATUS__SI = 0x462A; -constexpr unsigned int mmDCP4_OVL_ENABLE__SI = 0x461C; -constexpr unsigned int mmDCP4_OVL_END__SI = 0x4626; -constexpr unsigned int mmDCP4_OVL_PITCH__SI = 0x4621; -constexpr unsigned int mmDCP4_OVL_START__SI = 0x4625; -constexpr unsigned int mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI = 0x462B; -constexpr unsigned int mmDCP4_OVL_SURFACE_ADDRESS_HIGH__SI = 0x4622; -constexpr unsigned int mmDCP4_OVL_SURFACE_ADDRESS_INUSE__SI = 0x4628; -constexpr unsigned int mmDCP4_OVL_SURFACE_OFFSET_X__SI = 0x4623; -constexpr unsigned int mmDCP4_OVL_SURFACE_OFFSET_Y__SI = 0x4624; -constexpr unsigned int mmDCP4_OVL_SWAP_CNTL__SI = 0x461F; -constexpr unsigned int mmDCP4_OVL_UPDATE__SI = 0x4627; -constexpr unsigned int mmDCP5_CUR_COLOR1__SI = 0x496C; -constexpr unsigned int mmDCP5_CUR_COLOR2__SI = 0x496D; -constexpr unsigned int mmDCP5_CUR_CONTROL__SI = 0x4966; -constexpr unsigned int mmDCP5_CUR_HOT_SPOT__SI = 0x496B; -constexpr unsigned int mmDCP5_CUR_POSITION__SI = 0x496A; -constexpr unsigned int mmDCP5_CUR_SIZE__SI = 0x4968; -constexpr unsigned int mmDCP5_CUR_SURFACE_ADDRESS_HIGH__SI = 0x4969; -constexpr unsigned int mmDCP5_CUR_SURFACE_ADDRESS__SI = 0x4967; -constexpr unsigned int mmDCP5_CUR_UPDATE__SI = 0x496E; -constexpr unsigned int mmDCP5_DCP_CRC_CONTROL__SI = 0x4987; -constexpr unsigned int mmDCP5_DCP_CRC_CURRENT__SI = 0x4989; -constexpr unsigned int mmDCP5_DCP_CRC_LAST__SI = 0x498B; -constexpr unsigned int mmDCP5_DCP_CRC_MASK__SI = 0x4988; -constexpr unsigned int mmDCP5_DCP_DEBUG__SI = 0x498D; -constexpr unsigned int mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI = 0x4991; -constexpr unsigned int mmDCP5_DCP_TEST_DEBUG_DATA__SI = 0x4996; -constexpr unsigned int mmDCP5_DCP_TEST_DEBUG_INDEX__SI = 0x4995; -constexpr unsigned int mmDCP5_DC_LUT_30_COLOR__SI = 0x497C; -constexpr unsigned int mmDCP5_DC_LUT_AUTOFILL__SI = 0x497F; -constexpr unsigned int mmDCP5_DC_LUT_BLACK_OFFSET_BLUE__SI = 0x4981; -constexpr unsigned int mmDCP5_DC_LUT_BLACK_OFFSET_GREEN__SI = 0x4982; -constexpr unsigned int mmDCP5_DC_LUT_BLACK_OFFSET_RED__SI = 0x4983; -constexpr unsigned int mmDCP5_DC_LUT_CONTROL__SI = 0x4980; -constexpr unsigned int mmDCP5_DC_LUT_PWL_DATA__SI = 0x497B; -constexpr unsigned int mmDCP5_DC_LUT_RW_INDEX__SI = 0x4979; -constexpr unsigned int mmDCP5_DC_LUT_RW_MODE__SI = 0x4978; -constexpr unsigned int mmDCP5_DC_LUT_SEQ_COLOR__SI = 0x497A; -constexpr unsigned int mmDCP5_DC_LUT_WHITE_OFFSET_BLUE__SI = 0x4984; -constexpr unsigned int mmDCP5_DC_LUT_WHITE_OFFSET_GREEN__SI = 0x4985; -constexpr unsigned int mmDCP5_DC_LUT_WHITE_OFFSET_RED__SI = 0x4986; -constexpr unsigned int mmDCP5_DC_LUT_WRITE_EN_MASK__SI = 0x497E; -constexpr unsigned int mmDCP5_GRPH_COMPRESS_PITCH__SI = 0x491A; -constexpr unsigned int mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI = 0x491B; -constexpr unsigned int mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS__SI = 0x4919; -constexpr unsigned int mmDCP5_GRPH_DFQ_CONTROL__SI = 0x4914; -constexpr unsigned int mmDCP5_GRPH_DFQ_STATUS__SI = 0x4915; -constexpr unsigned int mmDCP5_GRPH_ENABLE__SI = 0x4900; -constexpr unsigned int mmDCP5_GRPH_INTERRUPT_CONTROL__SI = 0x4917; -constexpr unsigned int mmDCP5_GRPH_INTERRUPT_STATUS__SI = 0x4916; -constexpr unsigned int mmDCP5_GRPH_LUT_10BIT_BYPASS__SI = 0x4902; -constexpr unsigned int mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI = 0x4907; -constexpr unsigned int mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI = 0x4908; -constexpr unsigned int mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS__SI = 0x4905; -constexpr unsigned int mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI = 0x4918; -constexpr unsigned int mmDCP5_GRPH_SURFACE_ADDRESS_INUSE__SI = 0x4913; -constexpr unsigned int mmDCP5_GRPH_SURFACE_OFFSET_X__SI = 0x4909; -constexpr unsigned int mmDCP5_GRPH_SURFACE_OFFSET_Y__SI = 0x490A; -constexpr unsigned int mmDCP5_GRPH_SWAP_CNTL__SI = 0x4903; -constexpr unsigned int mmDCP5_GRPH_X_END__SI = 0x490D; -constexpr unsigned int mmDCP5_GRPH_X_START__SI = 0x490B; -constexpr unsigned int mmDCP5_GRPH_Y_END__SI = 0x490E; -constexpr unsigned int mmDCP5_GRPH_Y_START__SI = 0x490C; -constexpr unsigned int mmDCP5_OVLSCL_EDGE_PIXEL_CNTL__SI = 0x492C; -constexpr unsigned int mmDCP5_OVL_CONTROL1__SI = 0x491D; -constexpr unsigned int mmDCP5_OVL_CONTROL2__SI = 0x491E; -constexpr unsigned int mmDCP5_OVL_DFQ_CONTROL__SI = 0x4929; -constexpr unsigned int mmDCP5_OVL_DFQ_STATUS__SI = 0x492A; -constexpr unsigned int mmDCP5_OVL_ENABLE__SI = 0x491C; -constexpr unsigned int mmDCP5_OVL_END__SI = 0x4926; -constexpr unsigned int mmDCP5_OVL_PITCH__SI = 0x4921; -constexpr unsigned int mmDCP5_OVL_START__SI = 0x4925; -constexpr unsigned int mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE__SI = 0x492B; -constexpr unsigned int mmDCP5_OVL_SURFACE_ADDRESS_HIGH__SI = 0x4922; -constexpr unsigned int mmDCP5_OVL_SURFACE_ADDRESS_INUSE__SI = 0x4928; -constexpr unsigned int mmDCP5_OVL_SURFACE_OFFSET_X__SI = 0x4923; -constexpr unsigned int mmDCP5_OVL_SURFACE_OFFSET_Y__SI = 0x4924; -constexpr unsigned int mmDCP5_OVL_SWAP_CNTL__SI = 0x491F; -constexpr unsigned int mmDCP5_OVL_UPDATE__SI = 0x4927; -constexpr unsigned int mmDCP_CRC_CONTROL__SI__VI = 0x1A87; -constexpr unsigned int mmDCP_CRC_CURRENT__SI__VI = 0x1A89; -constexpr unsigned int mmDCP_CRC_LAST__SI__VI = 0x1A8B; -constexpr unsigned int mmDCP_CRC_MASK__SI__VI = 0x1A88; -constexpr unsigned int mmDCP_DEBUG__SI__VI = 0x1A8D; -constexpr unsigned int mmDCP_LB_DATA_GAP_BETWEEN_CHUNK__SI__VI = 0x1A91; -constexpr unsigned int mmDCP_TEST_DEBUG_DATA__SI__VI = 0x1A96; -constexpr unsigned int mmDCP_TEST_DEBUG_INDEX__SI__VI = 0x1A95; -constexpr unsigned int mmDC_ABM1_ACE_CNTL_MISC__SI__VI = 0x1641; -constexpr unsigned int mmDC_ABM1_ACE_OFFSET_SLOPE_0__SI__VI = 0x163A; -constexpr unsigned int mmDC_ABM1_ACE_OFFSET_SLOPE_1__SI__VI = 0x163B; -constexpr unsigned int mmDC_ABM1_ACE_OFFSET_SLOPE_2__SI__VI = 0x163C; -constexpr unsigned int mmDC_ABM1_ACE_OFFSET_SLOPE_3__SI__VI = 0x163D; -constexpr unsigned int mmDC_ABM1_ACE_OFFSET_SLOPE_4__SI__VI = 0x163E; -constexpr unsigned int mmDC_ABM1_ACE_THRES_12__SI__VI = 0x163F; -constexpr unsigned int mmDC_ABM1_ACE_THRES_34__SI__VI = 0x1640; -constexpr unsigned int mmDC_ABM1_BL_MASTER_LOCK__SI__VI = 0x169C; -constexpr unsigned int mmDC_ABM1_CNTL__SI__VI = 0x1638; -constexpr unsigned int mmDC_ABM1_DEBUG_MISC__SI__VI = 0x1649; -constexpr unsigned int mmDC_ABM1_HGLS_REG_READ_PROGRESS__SI__VI = 0x164A; -constexpr unsigned int mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX__SI__VI = 0x1659; -constexpr unsigned int mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG__SI__VI = 0x1656; -constexpr unsigned int mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX__SI__VI = 0x1657; -constexpr unsigned int mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX__SI__VI = 0x165A; -constexpr unsigned int mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX__SI__VI = 0x1658; -constexpr unsigned int mmDC_ABM1_HG_MISC_CTRL__SI__VI = 0x164B; -constexpr unsigned int mmDC_ABM1_HG_RESULT_10__SI__VI = 0x1664; -constexpr unsigned int mmDC_ABM1_HG_RESULT_11__SI__VI = 0x1665; -constexpr unsigned int mmDC_ABM1_HG_RESULT_12__SI__VI = 0x1666; -constexpr unsigned int mmDC_ABM1_HG_RESULT_13__SI__VI = 0x1667; -constexpr unsigned int mmDC_ABM1_HG_RESULT_14__SI__VI = 0x1668; -constexpr unsigned int mmDC_ABM1_HG_RESULT_15__SI__VI = 0x1669; -constexpr unsigned int mmDC_ABM1_HG_RESULT_16__SI__VI = 0x166A; -constexpr unsigned int mmDC_ABM1_HG_RESULT_17__SI__VI = 0x166B; -constexpr unsigned int mmDC_ABM1_HG_RESULT_18__SI__VI = 0x166C; -constexpr unsigned int mmDC_ABM1_HG_RESULT_19__SI__VI = 0x166D; -constexpr unsigned int mmDC_ABM1_HG_RESULT_1__SI__VI = 0x165B; -constexpr unsigned int mmDC_ABM1_HG_RESULT_20__SI__VI = 0x166E; -constexpr unsigned int mmDC_ABM1_HG_RESULT_21__SI__VI = 0x166F; -constexpr unsigned int mmDC_ABM1_HG_RESULT_22__SI__VI = 0x1670; -constexpr unsigned int mmDC_ABM1_HG_RESULT_23__SI__VI = 0x1671; -constexpr unsigned int mmDC_ABM1_HG_RESULT_24__SI__VI = 0x1672; -constexpr unsigned int mmDC_ABM1_HG_RESULT_2__SI__VI = 0x165C; -constexpr unsigned int mmDC_ABM1_HG_RESULT_3__SI__VI = 0x165D; -constexpr unsigned int mmDC_ABM1_HG_RESULT_4__SI__VI = 0x165E; -constexpr unsigned int mmDC_ABM1_HG_RESULT_5__SI__VI = 0x165F; -constexpr unsigned int mmDC_ABM1_HG_RESULT_6__SI__VI = 0x1660; -constexpr unsigned int mmDC_ABM1_HG_RESULT_7__SI__VI = 0x1661; -constexpr unsigned int mmDC_ABM1_HG_RESULT_8__SI__VI = 0x1662; -constexpr unsigned int mmDC_ABM1_HG_RESULT_9__SI__VI = 0x1663; -constexpr unsigned int mmDC_ABM1_HG_SAMPLE_RATE__SI__VI = 0x1654; -constexpr unsigned int mmDC_ABM1_IPCSC_COEFF_SEL__SI__VI = 0x1639; -constexpr unsigned int mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA__SI__VI = 0x164E; -constexpr unsigned int mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__SI__VI = 0x1653; -constexpr unsigned int mmDC_ABM1_LS_MIN_MAX_LUMA__SI__VI = 0x164D; -constexpr unsigned int mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__SI__VI = 0x1651; -constexpr unsigned int mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__SI__VI = 0x1652; -constexpr unsigned int mmDC_ABM1_LS_OVR_SCAN_BIN__SI__VI = 0x1650; -constexpr unsigned int mmDC_ABM1_LS_PIXEL_COUNT__SI__VI = 0x164F; -constexpr unsigned int mmDC_ABM1_LS_SAMPLE_RATE__SI__VI = 0x1655; -constexpr unsigned int mmDC_ABM1_LS_SUM_OF_LUMA__SI__VI = 0x164C; -constexpr unsigned int mmDC_DMCU_SCRATCH__SI__VI = 0x1618; -constexpr unsigned int mmDC_GENERICA__SI = 0x1900; -constexpr unsigned int mmDC_GENERICB__SI = 0x1901; -constexpr unsigned int mmDC_GPIO_DDC1_A__SI = 0x190D; -constexpr unsigned int mmDC_GPIO_DDC1_EN__SI = 0x190E; -constexpr unsigned int mmDC_GPIO_DDC1_MASK__SI = 0x190C; -constexpr unsigned int mmDC_GPIO_DDC1_Y__SI = 0x190F; -constexpr unsigned int mmDC_GPIO_DDC2_A__SI = 0x1911; -constexpr unsigned int mmDC_GPIO_DDC2_EN__SI = 0x1912; -constexpr unsigned int mmDC_GPIO_DDC2_MASK__SI = 0x1910; -constexpr unsigned int mmDC_GPIO_DDC2_Y__SI = 0x1913; -constexpr unsigned int mmDC_GPIO_DDC3_A__SI = 0x1915; -constexpr unsigned int mmDC_GPIO_DDC3_EN__SI = 0x1916; -constexpr unsigned int mmDC_GPIO_DDC3_MASK__SI = 0x1914; -constexpr unsigned int mmDC_GPIO_DDC3_Y__SI = 0x1917; -constexpr unsigned int mmDC_GPIO_DDC4_A__SI = 0x1919; -constexpr unsigned int mmDC_GPIO_DDC4_EN__SI = 0x191A; -constexpr unsigned int mmDC_GPIO_DDC4_MASK__SI = 0x1918; -constexpr unsigned int mmDC_GPIO_DDC4_Y__SI = 0x191B; -constexpr unsigned int mmDC_GPIO_DDC5_A__SI = 0x191D; -constexpr unsigned int mmDC_GPIO_DDC5_EN__SI = 0x191E; -constexpr unsigned int mmDC_GPIO_DDC5_MASK__SI = 0x191C; -constexpr unsigned int mmDC_GPIO_DDC5_Y__SI = 0x191F; -constexpr unsigned int mmDC_GPIO_DDC6_A__SI = 0x1921; -constexpr unsigned int mmDC_GPIO_DDC6_EN__SI = 0x1922; -constexpr unsigned int mmDC_GPIO_DDC6_MASK__SI = 0x1920; -constexpr unsigned int mmDC_GPIO_DDC6_Y__SI = 0x1923; -constexpr unsigned int mmDC_GPIO_DEBUG__SI = 0x1946; -constexpr unsigned int mmDC_GPIO_DVODATA_A__SI = 0x1909; -constexpr unsigned int mmDC_GPIO_DVODATA_EN__SI = 0x190A; -constexpr unsigned int mmDC_GPIO_DVODATA_MASK__SI = 0x1908; -constexpr unsigned int mmDC_GPIO_DVODATA_Y__SI = 0x190B; -constexpr unsigned int mmDC_GPIO_GENERIC_A__SI = 0x1905; -constexpr unsigned int mmDC_GPIO_GENERIC_EN__SI = 0x1906; -constexpr unsigned int mmDC_GPIO_GENERIC_MASK__SI = 0x1904; -constexpr unsigned int mmDC_GPIO_GENERIC_Y__SI = 0x1907; -constexpr unsigned int mmDC_GPIO_HPD_A__SI = 0x192D; -constexpr unsigned int mmDC_GPIO_HPD_EN__SI = 0x192E; -constexpr unsigned int mmDC_GPIO_HPD_MASK__SI = 0x192C; -constexpr unsigned int mmDC_GPIO_HPD_Y__SI = 0x192F; -constexpr unsigned int mmDC_GPIO_PAD_STRENGTH_1__SI = 0x1944; -constexpr unsigned int mmDC_GPIO_PAD_STRENGTH_2__SI = 0x1945; -constexpr unsigned int mmDC_GPIO_PWRSEQ_A__SI = 0x1941; -constexpr unsigned int mmDC_GPIO_PWRSEQ_EN__SI = 0x1942; -constexpr unsigned int mmDC_GPIO_PWRSEQ_MASK__SI = 0x1940; -constexpr unsigned int mmDC_GPIO_PWRSEQ_Y__SI = 0x1943; -constexpr unsigned int mmDC_GPIO_SYNCA_A__SI = 0x1925; -constexpr unsigned int mmDC_GPIO_SYNCA_EN__SI = 0x1926; -constexpr unsigned int mmDC_GPIO_SYNCA_MASK__SI = 0x1924; -constexpr unsigned int mmDC_GPIO_SYNCA_Y__SI = 0x1927; -constexpr unsigned int mmDC_GPU_TIMER_READ_CNTL__SI = 0x1972; -constexpr unsigned int mmDC_GPU_TIMER_READ__SI = 0x1971; -constexpr unsigned int mmDC_GPU_TIMER_START_POSITION__SI = 0x1970; -constexpr unsigned int mmDC_HPD1_CONTROL__SI = 0x1809; -constexpr unsigned int mmDC_HPD1_INT_CONTROL__SI = 0x1808; -constexpr unsigned int mmDC_HPD1_INT_STATUS__SI = 0x1807; -constexpr unsigned int mmDC_HPD2_CONTROL__SI = 0x180C; -constexpr unsigned int mmDC_HPD2_INT_CONTROL__SI = 0x180B; -constexpr unsigned int mmDC_HPD2_INT_STATUS__SI = 0x180A; -constexpr unsigned int mmDC_HPD3_CONTROL__SI = 0x180F; -constexpr unsigned int mmDC_HPD3_INT_CONTROL__SI = 0x180E; -constexpr unsigned int mmDC_HPD3_INT_STATUS__SI = 0x180D; -constexpr unsigned int mmDC_HPD4_CONTROL__SI = 0x1812; -constexpr unsigned int mmDC_HPD4_INT_CONTROL__SI = 0x1811; -constexpr unsigned int mmDC_HPD4_INT_STATUS__SI = 0x1810; -constexpr unsigned int mmDC_HPD5_CONTROL__SI = 0x1815; -constexpr unsigned int mmDC_HPD5_INT_CONTROL__SI = 0x1814; -constexpr unsigned int mmDC_HPD5_INT_STATUS__SI = 0x1813; -constexpr unsigned int mmDC_HPD6_CONTROL__SI = 0x1818; -constexpr unsigned int mmDC_HPD6_INT_CONTROL__SI = 0x1817; -constexpr unsigned int mmDC_HPD6_INT_STATUS__SI = 0x1816; -constexpr unsigned int mmDC_I2C_ARBITRATION__SI = 0x181A; -constexpr unsigned int mmDC_I2C_CONTROL__SI = 0x1819; -constexpr unsigned int mmDC_I2C_DATA__SI = 0x1833; -constexpr unsigned int mmDC_I2C_DDC1_HW_STATUS__SI = 0x181D; -constexpr unsigned int mmDC_I2C_DDC1_SETUP__SI = 0x1824; -constexpr unsigned int mmDC_I2C_DDC1_SPEED__SI = 0x1823; -constexpr unsigned int mmDC_I2C_DDC2_HW_STATUS__SI = 0x181E; -constexpr unsigned int mmDC_I2C_DDC2_SETUP__SI = 0x1826; -constexpr unsigned int mmDC_I2C_DDC2_SPEED__SI = 0x1825; -constexpr unsigned int mmDC_I2C_DDC3_HW_STATUS__SI = 0x181F; -constexpr unsigned int mmDC_I2C_DDC3_SETUP__SI = 0x1828; -constexpr unsigned int mmDC_I2C_DDC3_SPEED__SI = 0x1827; -constexpr unsigned int mmDC_I2C_DDC4_HW_STATUS__SI = 0x1820; -constexpr unsigned int mmDC_I2C_DDC4_SETUP__SI = 0x182A; -constexpr unsigned int mmDC_I2C_DDC4_SPEED__SI = 0x1829; -constexpr unsigned int mmDC_I2C_DDC5_HW_STATUS__SI = 0x1821; -constexpr unsigned int mmDC_I2C_DDC5_SETUP__SI = 0x182C; -constexpr unsigned int mmDC_I2C_DDC5_SPEED__SI = 0x182B; -constexpr unsigned int mmDC_I2C_DDC6_HW_STATUS__SI = 0x1822; -constexpr unsigned int mmDC_I2C_DDC6_SETUP__SI = 0x182E; -constexpr unsigned int mmDC_I2C_DDC6_SPEED__SI = 0x182D; -constexpr unsigned int mmDC_I2C_INTERRUPT_CONTROL__SI = 0x181B; -constexpr unsigned int mmDC_I2C_SW_STATUS__SI = 0x181C; -constexpr unsigned int mmDC_I2C_TRANSACTION0__SI = 0x182F; -constexpr unsigned int mmDC_I2C_TRANSACTION1__SI = 0x1830; -constexpr unsigned int mmDC_I2C_TRANSACTION2__SI = 0x1831; -constexpr unsigned int mmDC_I2C_TRANSACTION3__SI = 0x1832; -constexpr unsigned int mmDC_LUT_30_COLOR__SI__VI = 0x1A7C; -constexpr unsigned int mmDC_LUT_AUTOFILL__SI__VI = 0x1A7F; -constexpr unsigned int mmDC_LUT_BLACK_OFFSET_BLUE__SI__VI = 0x1A81; -constexpr unsigned int mmDC_LUT_BLACK_OFFSET_GREEN__SI__VI = 0x1A82; -constexpr unsigned int mmDC_LUT_BLACK_OFFSET_RED__SI__VI = 0x1A83; -constexpr unsigned int mmDC_LUT_CONTROL__SI__VI = 0x1A80; -constexpr unsigned int mmDC_LUT_PWL_DATA__SI__VI = 0x1A7B; -constexpr unsigned int mmDC_LUT_RW_INDEX__SI__VI = 0x1A79; -constexpr unsigned int mmDC_LUT_RW_MODE__SI__VI = 0x1A78; -constexpr unsigned int mmDC_LUT_SEQ_COLOR__SI__VI = 0x1A7A; -constexpr unsigned int mmDC_LUT_WHITE_OFFSET_BLUE__SI__VI = 0x1A84; -constexpr unsigned int mmDC_LUT_WHITE_OFFSET_GREEN__SI__VI = 0x1A85; -constexpr unsigned int mmDC_LUT_WHITE_OFFSET_RED__SI__VI = 0x1A86; -constexpr unsigned int mmDC_LUT_WRITE_EN_MASK__SI__VI = 0x1A7E; -constexpr unsigned int mmDC_MVP_LB_CONTROL__SI = 0x1ADB; -constexpr unsigned int mmDC_PAD_EXTERN_SIG__SI = 0x1902; -constexpr unsigned int mmDC_PINSTRAPS__SI = 0x1954; -constexpr unsigned int mmDC_REF_CLK_CNTL__SI = 0x1903; -constexpr unsigned int mmDC_TEST_DEBUG_DATA__SI = 0x186D; -constexpr unsigned int mmDC_TEST_DEBUG_INDEX__SI = 0x186C; -constexpr unsigned int mmDEBUG_DATA = 0x203D; -constexpr unsigned int mmDEBUG_INDEX = 0x203C; -constexpr unsigned int mmDENTIST_DISPCLK_CNTL__SI = 0x015F; -constexpr unsigned int mmDESKTOP_HEIGHT__SI = 0x1AC1; -constexpr unsigned int mmDIDT_IND_DATA__CI__VI = 0x3281; -constexpr unsigned int mmDIDT_IND_INDEX__CI__VI = 0x3280; -constexpr unsigned int mmDIG0_AFMT_60958_0__SI = 0x1C41; -constexpr unsigned int mmDIG0_AFMT_60958_1__SI = 0x1C42; -constexpr unsigned int mmDIG0_AFMT_60958_2__SI = 0x1C48; -constexpr unsigned int mmDIG0_AFMT_AUDIO_CRC_CONTROL__SI = 0x1C43; -constexpr unsigned int mmDIG0_AFMT_AUDIO_CRC_RESULT__SI = 0x1C49; -constexpr unsigned int mmDIG0_AFMT_AUDIO_INFO0__SI = 0x1C3F; -constexpr unsigned int mmDIG0_AFMT_AUDIO_INFO1__SI = 0x1C40; -constexpr unsigned int mmDIG0_AFMT_AUDIO_PACKET_CONTROL2__SI = 0x1C17; -constexpr unsigned int mmDIG0_AFMT_AUDIO_PACKET_CONTROL__SI = 0x1C4B; -constexpr unsigned int mmDIG0_AFMT_AVI_INFO0__SI = 0x1C21; -constexpr unsigned int mmDIG0_AFMT_AVI_INFO1__SI = 0x1C22; -constexpr unsigned int mmDIG0_AFMT_AVI_INFO2__SI = 0x1C23; -constexpr unsigned int mmDIG0_AFMT_AVI_INFO3__SI = 0x1C24; -constexpr unsigned int mmDIG0_AFMT_INFOFRAME_CONTROL0__SI = 0x1C4D; -constexpr unsigned int mmDIG0_AFMT_ISRC1_0__SI = 0x1C18; -constexpr unsigned int mmDIG0_AFMT_ISRC1_1__SI = 0x1C19; -constexpr unsigned int mmDIG0_AFMT_ISRC1_2__SI = 0x1C1A; -constexpr unsigned int mmDIG0_AFMT_ISRC1_3__SI = 0x1C1B; -constexpr unsigned int mmDIG0_AFMT_ISRC1_4__SI = 0x1C1C; -constexpr unsigned int mmDIG0_AFMT_ISRC2_0__SI = 0x1C1D; -constexpr unsigned int mmDIG0_AFMT_ISRC2_1__SI = 0x1C1E; -constexpr unsigned int mmDIG0_AFMT_ISRC2_2__SI = 0x1C1F; -constexpr unsigned int mmDIG0_AFMT_ISRC2_3__SI = 0x1C20; -constexpr unsigned int mmDIG0_AFMT_MPEG_INFO0__SI = 0x1C25; -constexpr unsigned int mmDIG0_AFMT_MPEG_INFO1__SI = 0x1C26; -constexpr unsigned int mmDIG0_AFMT_RAMP_CONTROL0__SI = 0x1C44; -constexpr unsigned int mmDIG0_AFMT_RAMP_CONTROL1__SI = 0x1C45; -constexpr unsigned int mmDIG0_AFMT_RAMP_CONTROL2__SI = 0x1C46; -constexpr unsigned int mmDIG0_AFMT_RAMP_CONTROL3__SI = 0x1C47; -constexpr unsigned int mmDIG0_AFMT_STATUS__SI = 0x1C4A; -constexpr unsigned int mmDIG0_AFMT_VBI_PACKET_CONTROL__SI = 0x1C4C; -constexpr unsigned int mmDIG0_DIG_CLOCK_PATTERN__SI = 0x1C03; -constexpr unsigned int mmDIG0_DIG_OUTPUT_CRC_CNTL__SI = 0x1C01; -constexpr unsigned int mmDIG0_DIG_OUTPUT_CRC_RESULT__SI = 0x1C02; -constexpr unsigned int mmDIG0_DIG_RANDOM_PATTERN_SEED__SI = 0x1C05; -constexpr unsigned int mmDIG0_DIG_TEST_PATTERN__SI = 0x1C04; -constexpr unsigned int mmDIG0_HDMI_ACR_32_0__SI = 0x1C37; -constexpr unsigned int mmDIG0_HDMI_ACR_32_1__SI = 0x1C38; -constexpr unsigned int mmDIG0_HDMI_ACR_44_0__SI = 0x1C39; -constexpr unsigned int mmDIG0_HDMI_ACR_44_1__SI = 0x1C3A; -constexpr unsigned int mmDIG0_HDMI_ACR_48_0__SI = 0x1C3B; -constexpr unsigned int mmDIG0_HDMI_ACR_48_1__SI = 0x1C3C; -constexpr unsigned int mmDIG0_HDMI_ACR_PACKET_CONTROL__SI = 0x1C0F; -constexpr unsigned int mmDIG0_HDMI_ACR_STATUS_0__SI = 0x1C3D; -constexpr unsigned int mmDIG0_HDMI_ACR_STATUS_1__SI = 0x1C3E; -constexpr unsigned int mmDIG0_HDMI_AUDIO_PACKET_CONTROL__SI = 0x1C0E; -constexpr unsigned int mmDIG0_HDMI_CONTROL__SI = 0x1C0C; -constexpr unsigned int mmDIG0_HDMI_GC__SI = 0x1C16; -constexpr unsigned int mmDIG0_HDMI_GENERIC_PACKET_CONTROL__SI = 0x1C13; -constexpr unsigned int mmDIG0_HDMI_INFOFRAME_CONTROL0__SI = 0x1C11; -constexpr unsigned int mmDIG0_HDMI_INFOFRAME_CONTROL1__SI = 0x1C12; -constexpr unsigned int mmDIG0_HDMI_STATUS__SI = 0x1C0D; -constexpr unsigned int mmDIG0_HDMI_VBI_PACKET_CONTROL__SI = 0x1C10; -constexpr unsigned int mmDIG0_LVDS_DATA_CNTL__SI = 0x1C8C; -constexpr unsigned int mmDIG0_TMDS_CNTL__SI = 0x1C7C; -constexpr unsigned int mmDIG0_TMDS_CONTROL0_FEEDBACK__SI = 0x1C7E; -constexpr unsigned int mmDIG0_TMDS_CONTROL_CHAR__SI = 0x1C7D; -constexpr unsigned int mmDIG0_TMDS_CTL0_1_GEN_CNTL__SI = 0x1C86; -constexpr unsigned int mmDIG0_TMDS_CTL2_3_GEN_CNTL__SI = 0x1C87; -constexpr unsigned int mmDIG0_TMDS_CTL_BITS__SI = 0x1C83; -constexpr unsigned int mmDIG0_TMDS_DCBALANCER_CONTROL__SI = 0x1C84; -constexpr unsigned int mmDIG0_TMDS_DEBUG__SI = 0x1C82; -constexpr unsigned int mmDIG0_TMDS_STEREOSYNC_CTL_SEL__SI = 0x1C7F; -constexpr unsigned int mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1__SI = 0x1C80; -constexpr unsigned int mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3__SI = 0x1C81; -constexpr unsigned int mmDIG1_AFMT_60958_0__SI = 0x1F41; -constexpr unsigned int mmDIG1_AFMT_60958_1__SI = 0x1F42; -constexpr unsigned int mmDIG1_AFMT_60958_2__SI = 0x1F48; -constexpr unsigned int mmDIG1_AFMT_AUDIO_CRC_CONTROL__SI = 0x1F43; -constexpr unsigned int mmDIG1_AFMT_AUDIO_CRC_RESULT__SI = 0x1F49; -constexpr unsigned int mmDIG1_AFMT_AUDIO_INFO0__SI = 0x1F3F; -constexpr unsigned int mmDIG1_AFMT_AUDIO_INFO1__SI = 0x1F40; -constexpr unsigned int mmDIG1_AFMT_AUDIO_PACKET_CONTROL2__SI = 0x1F17; -constexpr unsigned int mmDIG1_AFMT_AUDIO_PACKET_CONTROL__SI = 0x1F4B; -constexpr unsigned int mmDIG1_AFMT_AVI_INFO0__SI = 0x1F21; -constexpr unsigned int mmDIG1_AFMT_AVI_INFO1__SI = 0x1F22; -constexpr unsigned int mmDIG1_AFMT_AVI_INFO2__SI = 0x1F23; -constexpr unsigned int mmDIG1_AFMT_AVI_INFO3__SI = 0x1F24; -constexpr unsigned int mmDIG1_AFMT_INFOFRAME_CONTROL0__SI = 0x1F4D; -constexpr unsigned int mmDIG1_AFMT_ISRC1_0__SI = 0x1F18; -constexpr unsigned int mmDIG1_AFMT_ISRC1_1__SI = 0x1F19; -constexpr unsigned int mmDIG1_AFMT_ISRC1_2__SI = 0x1F1A; -constexpr unsigned int mmDIG1_AFMT_ISRC1_3__SI = 0x1F1B; -constexpr unsigned int mmDIG1_AFMT_ISRC1_4__SI = 0x1F1C; -constexpr unsigned int mmDIG1_AFMT_ISRC2_0__SI = 0x1F1D; -constexpr unsigned int mmDIG1_AFMT_ISRC2_1__SI = 0x1F1E; -constexpr unsigned int mmDIG1_AFMT_ISRC2_2__SI = 0x1F1F; -constexpr unsigned int mmDIG1_AFMT_ISRC2_3__SI = 0x1F20; -constexpr unsigned int mmDIG1_AFMT_MPEG_INFO0__SI = 0x1F25; -constexpr unsigned int mmDIG1_AFMT_MPEG_INFO1__SI = 0x1F26; -constexpr unsigned int mmDIG1_AFMT_RAMP_CONTROL0__SI = 0x1F44; -constexpr unsigned int mmDIG1_AFMT_RAMP_CONTROL1__SI = 0x1F45; -constexpr unsigned int mmDIG1_AFMT_RAMP_CONTROL2__SI = 0x1F46; -constexpr unsigned int mmDIG1_AFMT_RAMP_CONTROL3__SI = 0x1F47; -constexpr unsigned int mmDIG1_AFMT_STATUS__SI = 0x1F4A; -constexpr unsigned int mmDIG1_AFMT_VBI_PACKET_CONTROL__SI = 0x1F4C; -constexpr unsigned int mmDIG1_DIG_CLOCK_PATTERN__SI = 0x1F03; -constexpr unsigned int mmDIG1_DIG_OUTPUT_CRC_CNTL__SI = 0x1F01; -constexpr unsigned int mmDIG1_DIG_OUTPUT_CRC_RESULT__SI = 0x1F02; -constexpr unsigned int mmDIG1_DIG_RANDOM_PATTERN_SEED__SI = 0x1F05; -constexpr unsigned int mmDIG1_DIG_TEST_PATTERN__SI = 0x1F04; -constexpr unsigned int mmDIG1_HDMI_ACR_32_0__SI = 0x1F37; -constexpr unsigned int mmDIG1_HDMI_ACR_32_1__SI = 0x1F38; -constexpr unsigned int mmDIG1_HDMI_ACR_44_0__SI = 0x1F39; -constexpr unsigned int mmDIG1_HDMI_ACR_44_1__SI = 0x1F3A; -constexpr unsigned int mmDIG1_HDMI_ACR_48_0__SI = 0x1F3B; -constexpr unsigned int mmDIG1_HDMI_ACR_48_1__SI = 0x1F3C; -constexpr unsigned int mmDIG1_HDMI_ACR_PACKET_CONTROL__SI = 0x1F0F; -constexpr unsigned int mmDIG1_HDMI_ACR_STATUS_0__SI = 0x1F3D; -constexpr unsigned int mmDIG1_HDMI_ACR_STATUS_1__SI = 0x1F3E; -constexpr unsigned int mmDIG1_HDMI_AUDIO_PACKET_CONTROL__SI = 0x1F0E; -constexpr unsigned int mmDIG1_HDMI_CONTROL__SI = 0x1F0C; -constexpr unsigned int mmDIG1_HDMI_GC__SI = 0x1F16; -constexpr unsigned int mmDIG1_HDMI_GENERIC_PACKET_CONTROL__SI = 0x1F13; -constexpr unsigned int mmDIG1_HDMI_INFOFRAME_CONTROL0__SI = 0x1F11; -constexpr unsigned int mmDIG1_HDMI_INFOFRAME_CONTROL1__SI = 0x1F12; -constexpr unsigned int mmDIG1_HDMI_STATUS__SI = 0x1F0D; -constexpr unsigned int mmDIG1_HDMI_VBI_PACKET_CONTROL__SI = 0x1F10; -constexpr unsigned int mmDIG1_LVDS_DATA_CNTL__SI = 0x1F8C; -constexpr unsigned int mmDIG1_TMDS_CNTL__SI = 0x1F7C; -constexpr unsigned int mmDIG1_TMDS_CONTROL0_FEEDBACK__SI = 0x1F7E; -constexpr unsigned int mmDIG1_TMDS_CONTROL_CHAR__SI = 0x1F7D; -constexpr unsigned int mmDIG1_TMDS_CTL0_1_GEN_CNTL__SI = 0x1F86; -constexpr unsigned int mmDIG1_TMDS_CTL2_3_GEN_CNTL__SI = 0x1F87; -constexpr unsigned int mmDIG1_TMDS_CTL_BITS__SI = 0x1F83; -constexpr unsigned int mmDIG1_TMDS_DCBALANCER_CONTROL__SI = 0x1F84; -constexpr unsigned int mmDIG1_TMDS_DEBUG__SI = 0x1F82; -constexpr unsigned int mmDIG1_TMDS_STEREOSYNC_CTL_SEL__SI = 0x1F7F; -constexpr unsigned int mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1__SI = 0x1F80; -constexpr unsigned int mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3__SI = 0x1F81; -constexpr unsigned int mmDIG2_AFMT_60958_0__SI = 0x4241; -constexpr unsigned int mmDIG2_AFMT_60958_1__SI = 0x4242; -constexpr unsigned int mmDIG2_AFMT_60958_2__SI = 0x4248; -constexpr unsigned int mmDIG2_AFMT_AUDIO_CRC_CONTROL__SI = 0x4243; -constexpr unsigned int mmDIG2_AFMT_AUDIO_CRC_RESULT__SI = 0x4249; -constexpr unsigned int mmDIG2_AFMT_AUDIO_INFO0__SI = 0x423F; -constexpr unsigned int mmDIG2_AFMT_AUDIO_INFO1__SI = 0x4240; -constexpr unsigned int mmDIG2_AFMT_AUDIO_PACKET_CONTROL2__SI = 0x4217; -constexpr unsigned int mmDIG2_AFMT_AUDIO_PACKET_CONTROL__SI = 0x424B; -constexpr unsigned int mmDIG2_AFMT_AVI_INFO0__SI = 0x4221; -constexpr unsigned int mmDIG2_AFMT_AVI_INFO1__SI = 0x4222; -constexpr unsigned int mmDIG2_AFMT_AVI_INFO2__SI = 0x4223; -constexpr unsigned int mmDIG2_AFMT_AVI_INFO3__SI = 0x4224; -constexpr unsigned int mmDIG2_AFMT_INFOFRAME_CONTROL0__SI = 0x424D; -constexpr unsigned int mmDIG2_AFMT_ISRC1_0__SI = 0x4218; -constexpr unsigned int mmDIG2_AFMT_ISRC1_1__SI = 0x4219; -constexpr unsigned int mmDIG2_AFMT_ISRC1_2__SI = 0x421A; -constexpr unsigned int mmDIG2_AFMT_ISRC1_3__SI = 0x421B; -constexpr unsigned int mmDIG2_AFMT_ISRC1_4__SI = 0x421C; -constexpr unsigned int mmDIG2_AFMT_ISRC2_0__SI = 0x421D; -constexpr unsigned int mmDIG2_AFMT_ISRC2_1__SI = 0x421E; -constexpr unsigned int mmDIG2_AFMT_ISRC2_2__SI = 0x421F; -constexpr unsigned int mmDIG2_AFMT_ISRC2_3__SI = 0x4220; -constexpr unsigned int mmDIG2_AFMT_MPEG_INFO0__SI = 0x4225; -constexpr unsigned int mmDIG2_AFMT_MPEG_INFO1__SI = 0x4226; -constexpr unsigned int mmDIG2_AFMT_RAMP_CONTROL0__SI = 0x4244; -constexpr unsigned int mmDIG2_AFMT_RAMP_CONTROL1__SI = 0x4245; -constexpr unsigned int mmDIG2_AFMT_RAMP_CONTROL2__SI = 0x4246; -constexpr unsigned int mmDIG2_AFMT_RAMP_CONTROL3__SI = 0x4247; -constexpr unsigned int mmDIG2_AFMT_STATUS__SI = 0x424A; -constexpr unsigned int mmDIG2_AFMT_VBI_PACKET_CONTROL__SI = 0x424C; -constexpr unsigned int mmDIG2_DIG_CLOCK_PATTERN__SI = 0x4203; -constexpr unsigned int mmDIG2_DIG_OUTPUT_CRC_CNTL__SI = 0x4201; -constexpr unsigned int mmDIG2_DIG_OUTPUT_CRC_RESULT__SI = 0x4202; -constexpr unsigned int mmDIG2_DIG_RANDOM_PATTERN_SEED__SI = 0x4205; -constexpr unsigned int mmDIG2_DIG_TEST_PATTERN__SI = 0x4204; -constexpr unsigned int mmDIG2_HDMI_ACR_32_0__SI = 0x4237; -constexpr unsigned int mmDIG2_HDMI_ACR_32_1__SI = 0x4238; -constexpr unsigned int mmDIG2_HDMI_ACR_44_0__SI = 0x4239; -constexpr unsigned int mmDIG2_HDMI_ACR_44_1__SI = 0x423A; -constexpr unsigned int mmDIG2_HDMI_ACR_48_0__SI = 0x423B; -constexpr unsigned int mmDIG2_HDMI_ACR_48_1__SI = 0x423C; -constexpr unsigned int mmDIG2_HDMI_ACR_PACKET_CONTROL__SI = 0x420F; -constexpr unsigned int mmDIG2_HDMI_ACR_STATUS_0__SI = 0x423D; -constexpr unsigned int mmDIG2_HDMI_ACR_STATUS_1__SI = 0x423E; -constexpr unsigned int mmDIG2_HDMI_AUDIO_PACKET_CONTROL__SI = 0x420E; -constexpr unsigned int mmDIG2_HDMI_CONTROL__SI = 0x420C; -constexpr unsigned int mmDIG2_HDMI_GC__SI = 0x4216; -constexpr unsigned int mmDIG2_HDMI_GENERIC_PACKET_CONTROL__SI = 0x4213; -constexpr unsigned int mmDIG2_HDMI_INFOFRAME_CONTROL0__SI = 0x4211; -constexpr unsigned int mmDIG2_HDMI_INFOFRAME_CONTROL1__SI = 0x4212; -constexpr unsigned int mmDIG2_HDMI_STATUS__SI = 0x420D; -constexpr unsigned int mmDIG2_HDMI_VBI_PACKET_CONTROL__SI = 0x4210; -constexpr unsigned int mmDIG2_LVDS_DATA_CNTL__SI = 0x428C; -constexpr unsigned int mmDIG2_TMDS_CNTL__SI = 0x427C; -constexpr unsigned int mmDIG2_TMDS_CONTROL0_FEEDBACK__SI = 0x427E; -constexpr unsigned int mmDIG2_TMDS_CONTROL_CHAR__SI = 0x427D; -constexpr unsigned int mmDIG2_TMDS_CTL0_1_GEN_CNTL__SI = 0x4286; -constexpr unsigned int mmDIG2_TMDS_CTL2_3_GEN_CNTL__SI = 0x4287; -constexpr unsigned int mmDIG2_TMDS_CTL_BITS__SI = 0x4283; -constexpr unsigned int mmDIG2_TMDS_DCBALANCER_CONTROL__SI = 0x4284; -constexpr unsigned int mmDIG2_TMDS_DEBUG__SI = 0x4282; -constexpr unsigned int mmDIG2_TMDS_STEREOSYNC_CTL_SEL__SI = 0x427F; -constexpr unsigned int mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1__SI = 0x4280; -constexpr unsigned int mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3__SI = 0x4281; -constexpr unsigned int mmDIG3_AFMT_60958_0__SI = 0x4541; -constexpr unsigned int mmDIG3_AFMT_60958_1__SI = 0x4542; -constexpr unsigned int mmDIG3_AFMT_60958_2__SI = 0x4548; -constexpr unsigned int mmDIG3_AFMT_AUDIO_CRC_CONTROL__SI = 0x4543; -constexpr unsigned int mmDIG3_AFMT_AUDIO_CRC_RESULT__SI = 0x4549; -constexpr unsigned int mmDIG3_AFMT_AUDIO_INFO0__SI = 0x453F; -constexpr unsigned int mmDIG3_AFMT_AUDIO_INFO1__SI = 0x4540; -constexpr unsigned int mmDIG3_AFMT_AUDIO_PACKET_CONTROL2__SI = 0x4517; -constexpr unsigned int mmDIG3_AFMT_AUDIO_PACKET_CONTROL__SI = 0x454B; -constexpr unsigned int mmDIG3_AFMT_AVI_INFO0__SI = 0x4521; -constexpr unsigned int mmDIG3_AFMT_AVI_INFO1__SI = 0x4522; -constexpr unsigned int mmDIG3_AFMT_AVI_INFO2__SI = 0x4523; -constexpr unsigned int mmDIG3_AFMT_AVI_INFO3__SI = 0x4524; -constexpr unsigned int mmDIG3_AFMT_INFOFRAME_CONTROL0__SI = 0x454D; -constexpr unsigned int mmDIG3_AFMT_ISRC1_0__SI = 0x4518; -constexpr unsigned int mmDIG3_AFMT_ISRC1_1__SI = 0x4519; -constexpr unsigned int mmDIG3_AFMT_ISRC1_2__SI = 0x451A; -constexpr unsigned int mmDIG3_AFMT_ISRC1_3__SI = 0x451B; -constexpr unsigned int mmDIG3_AFMT_ISRC1_4__SI = 0x451C; -constexpr unsigned int mmDIG3_AFMT_ISRC2_0__SI = 0x451D; -constexpr unsigned int mmDIG3_AFMT_ISRC2_1__SI = 0x451E; -constexpr unsigned int mmDIG3_AFMT_ISRC2_2__SI = 0x451F; -constexpr unsigned int mmDIG3_AFMT_ISRC2_3__SI = 0x4520; -constexpr unsigned int mmDIG3_AFMT_MPEG_INFO0__SI = 0x4525; -constexpr unsigned int mmDIG3_AFMT_MPEG_INFO1__SI = 0x4526; -constexpr unsigned int mmDIG3_AFMT_RAMP_CONTROL0__SI = 0x4544; -constexpr unsigned int mmDIG3_AFMT_RAMP_CONTROL1__SI = 0x4545; -constexpr unsigned int mmDIG3_AFMT_RAMP_CONTROL2__SI = 0x4546; -constexpr unsigned int mmDIG3_AFMT_RAMP_CONTROL3__SI = 0x4547; -constexpr unsigned int mmDIG3_AFMT_STATUS__SI = 0x454A; -constexpr unsigned int mmDIG3_AFMT_VBI_PACKET_CONTROL__SI = 0x454C; -constexpr unsigned int mmDIG3_DIG_CLOCK_PATTERN__SI = 0x4503; -constexpr unsigned int mmDIG3_DIG_OUTPUT_CRC_CNTL__SI = 0x4501; -constexpr unsigned int mmDIG3_DIG_OUTPUT_CRC_RESULT__SI = 0x4502; -constexpr unsigned int mmDIG3_DIG_RANDOM_PATTERN_SEED__SI = 0x4505; -constexpr unsigned int mmDIG3_DIG_TEST_PATTERN__SI = 0x4504; -constexpr unsigned int mmDIG3_HDMI_ACR_32_0__SI = 0x4537; -constexpr unsigned int mmDIG3_HDMI_ACR_32_1__SI = 0x4538; -constexpr unsigned int mmDIG3_HDMI_ACR_44_0__SI = 0x4539; -constexpr unsigned int mmDIG3_HDMI_ACR_44_1__SI = 0x453A; -constexpr unsigned int mmDIG3_HDMI_ACR_48_0__SI = 0x453B; -constexpr unsigned int mmDIG3_HDMI_ACR_48_1__SI = 0x453C; -constexpr unsigned int mmDIG3_HDMI_ACR_PACKET_CONTROL__SI = 0x450F; -constexpr unsigned int mmDIG3_HDMI_ACR_STATUS_0__SI = 0x453D; -constexpr unsigned int mmDIG3_HDMI_ACR_STATUS_1__SI = 0x453E; -constexpr unsigned int mmDIG3_HDMI_AUDIO_PACKET_CONTROL__SI = 0x450E; -constexpr unsigned int mmDIG3_HDMI_CONTROL__SI = 0x450C; -constexpr unsigned int mmDIG3_HDMI_GC__SI = 0x4516; -constexpr unsigned int mmDIG3_HDMI_GENERIC_PACKET_CONTROL__SI = 0x4513; -constexpr unsigned int mmDIG3_HDMI_INFOFRAME_CONTROL0__SI = 0x4511; -constexpr unsigned int mmDIG3_HDMI_INFOFRAME_CONTROL1__SI = 0x4512; -constexpr unsigned int mmDIG3_HDMI_STATUS__SI = 0x450D; -constexpr unsigned int mmDIG3_HDMI_VBI_PACKET_CONTROL__SI = 0x4510; -constexpr unsigned int mmDIG3_LVDS_DATA_CNTL__SI = 0x458C; -constexpr unsigned int mmDIG3_TMDS_CNTL__SI = 0x457C; -constexpr unsigned int mmDIG3_TMDS_CONTROL0_FEEDBACK__SI = 0x457E; -constexpr unsigned int mmDIG3_TMDS_CONTROL_CHAR__SI = 0x457D; -constexpr unsigned int mmDIG3_TMDS_CTL0_1_GEN_CNTL__SI = 0x4586; -constexpr unsigned int mmDIG3_TMDS_CTL2_3_GEN_CNTL__SI = 0x4587; -constexpr unsigned int mmDIG3_TMDS_CTL_BITS__SI = 0x4583; -constexpr unsigned int mmDIG3_TMDS_DCBALANCER_CONTROL__SI = 0x4584; -constexpr unsigned int mmDIG3_TMDS_DEBUG__SI = 0x4582; -constexpr unsigned int mmDIG3_TMDS_STEREOSYNC_CTL_SEL__SI = 0x457F; -constexpr unsigned int mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1__SI = 0x4580; -constexpr unsigned int mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3__SI = 0x4581; -constexpr unsigned int mmDIG4_AFMT_60958_0__SI = 0x4841; -constexpr unsigned int mmDIG4_AFMT_60958_1__SI = 0x4842; -constexpr unsigned int mmDIG4_AFMT_60958_2__SI = 0x4848; -constexpr unsigned int mmDIG4_AFMT_AUDIO_CRC_CONTROL__SI = 0x4843; -constexpr unsigned int mmDIG4_AFMT_AUDIO_CRC_RESULT__SI = 0x4849; -constexpr unsigned int mmDIG4_AFMT_AUDIO_INFO0__SI = 0x483F; -constexpr unsigned int mmDIG4_AFMT_AUDIO_INFO1__SI = 0x4840; -constexpr unsigned int mmDIG4_AFMT_AUDIO_PACKET_CONTROL2__SI = 0x4817; -constexpr unsigned int mmDIG4_AFMT_AUDIO_PACKET_CONTROL__SI = 0x484B; -constexpr unsigned int mmDIG4_AFMT_AVI_INFO0__SI = 0x4821; -constexpr unsigned int mmDIG4_AFMT_AVI_INFO1__SI = 0x4822; -constexpr unsigned int mmDIG4_AFMT_AVI_INFO2__SI = 0x4823; -constexpr unsigned int mmDIG4_AFMT_AVI_INFO3__SI = 0x4824; -constexpr unsigned int mmDIG4_AFMT_INFOFRAME_CONTROL0__SI = 0x484D; -constexpr unsigned int mmDIG4_AFMT_ISRC1_0__SI = 0x4818; -constexpr unsigned int mmDIG4_AFMT_ISRC1_1__SI = 0x4819; -constexpr unsigned int mmDIG4_AFMT_ISRC1_2__SI = 0x481A; -constexpr unsigned int mmDIG4_AFMT_ISRC1_3__SI = 0x481B; -constexpr unsigned int mmDIG4_AFMT_ISRC1_4__SI = 0x481C; -constexpr unsigned int mmDIG4_AFMT_ISRC2_0__SI = 0x481D; -constexpr unsigned int mmDIG4_AFMT_ISRC2_1__SI = 0x481E; -constexpr unsigned int mmDIG4_AFMT_ISRC2_2__SI = 0x481F; -constexpr unsigned int mmDIG4_AFMT_ISRC2_3__SI = 0x4820; -constexpr unsigned int mmDIG4_AFMT_MPEG_INFO0__SI = 0x4825; -constexpr unsigned int mmDIG4_AFMT_MPEG_INFO1__SI = 0x4826; -constexpr unsigned int mmDIG4_AFMT_RAMP_CONTROL0__SI = 0x4844; -constexpr unsigned int mmDIG4_AFMT_RAMP_CONTROL1__SI = 0x4845; -constexpr unsigned int mmDIG4_AFMT_RAMP_CONTROL2__SI = 0x4846; -constexpr unsigned int mmDIG4_AFMT_RAMP_CONTROL3__SI = 0x4847; -constexpr unsigned int mmDIG4_AFMT_STATUS__SI = 0x484A; -constexpr unsigned int mmDIG4_AFMT_VBI_PACKET_CONTROL__SI = 0x484C; -constexpr unsigned int mmDIG4_DIG_CLOCK_PATTERN__SI = 0x4803; -constexpr unsigned int mmDIG4_DIG_OUTPUT_CRC_CNTL__SI = 0x4801; -constexpr unsigned int mmDIG4_DIG_OUTPUT_CRC_RESULT__SI = 0x4802; -constexpr unsigned int mmDIG4_DIG_RANDOM_PATTERN_SEED__SI = 0x4805; -constexpr unsigned int mmDIG4_DIG_TEST_PATTERN__SI = 0x4804; -constexpr unsigned int mmDIG4_HDMI_ACR_32_0__SI = 0x4837; -constexpr unsigned int mmDIG4_HDMI_ACR_32_1__SI = 0x4838; -constexpr unsigned int mmDIG4_HDMI_ACR_44_0__SI = 0x4839; -constexpr unsigned int mmDIG4_HDMI_ACR_44_1__SI = 0x483A; -constexpr unsigned int mmDIG4_HDMI_ACR_48_0__SI = 0x483B; -constexpr unsigned int mmDIG4_HDMI_ACR_48_1__SI = 0x483C; -constexpr unsigned int mmDIG4_HDMI_ACR_PACKET_CONTROL__SI = 0x480F; -constexpr unsigned int mmDIG4_HDMI_ACR_STATUS_0__SI = 0x483D; -constexpr unsigned int mmDIG4_HDMI_ACR_STATUS_1__SI = 0x483E; -constexpr unsigned int mmDIG4_HDMI_AUDIO_PACKET_CONTROL__SI = 0x480E; -constexpr unsigned int mmDIG4_HDMI_CONTROL__SI = 0x480C; -constexpr unsigned int mmDIG4_HDMI_GC__SI = 0x4816; -constexpr unsigned int mmDIG4_HDMI_GENERIC_PACKET_CONTROL__SI = 0x4813; -constexpr unsigned int mmDIG4_HDMI_INFOFRAME_CONTROL0__SI = 0x4811; -constexpr unsigned int mmDIG4_HDMI_INFOFRAME_CONTROL1__SI = 0x4812; -constexpr unsigned int mmDIG4_HDMI_STATUS__SI = 0x480D; -constexpr unsigned int mmDIG4_HDMI_VBI_PACKET_CONTROL__SI = 0x4810; -constexpr unsigned int mmDIG4_LVDS_DATA_CNTL__SI = 0x488C; -constexpr unsigned int mmDIG4_TMDS_CNTL__SI = 0x487C; -constexpr unsigned int mmDIG4_TMDS_CONTROL0_FEEDBACK__SI = 0x487E; -constexpr unsigned int mmDIG4_TMDS_CONTROL_CHAR__SI = 0x487D; -constexpr unsigned int mmDIG4_TMDS_CTL0_1_GEN_CNTL__SI = 0x4886; -constexpr unsigned int mmDIG4_TMDS_CTL2_3_GEN_CNTL__SI = 0x4887; -constexpr unsigned int mmDIG4_TMDS_CTL_BITS__SI = 0x4883; -constexpr unsigned int mmDIG4_TMDS_DCBALANCER_CONTROL__SI = 0x4884; -constexpr unsigned int mmDIG4_TMDS_DEBUG__SI = 0x4882; -constexpr unsigned int mmDIG4_TMDS_STEREOSYNC_CTL_SEL__SI = 0x487F; -constexpr unsigned int mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1__SI = 0x4880; -constexpr unsigned int mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3__SI = 0x4881; -constexpr unsigned int mmDIG5_AFMT_60958_0__SI = 0x4B41; -constexpr unsigned int mmDIG5_AFMT_60958_1__SI = 0x4B42; -constexpr unsigned int mmDIG5_AFMT_60958_2__SI = 0x4B48; -constexpr unsigned int mmDIG5_AFMT_AUDIO_CRC_CONTROL__SI = 0x4B43; -constexpr unsigned int mmDIG5_AFMT_AUDIO_CRC_RESULT__SI = 0x4B49; -constexpr unsigned int mmDIG5_AFMT_AUDIO_INFO0__SI = 0x4B3F; -constexpr unsigned int mmDIG5_AFMT_AUDIO_INFO1__SI = 0x4B40; -constexpr unsigned int mmDIG5_AFMT_AUDIO_PACKET_CONTROL2__SI = 0x4B17; -constexpr unsigned int mmDIG5_AFMT_AUDIO_PACKET_CONTROL__SI = 0x4B4B; -constexpr unsigned int mmDIG5_AFMT_AVI_INFO0__SI = 0x4B21; -constexpr unsigned int mmDIG5_AFMT_AVI_INFO1__SI = 0x4B22; -constexpr unsigned int mmDIG5_AFMT_AVI_INFO2__SI = 0x4B23; -constexpr unsigned int mmDIG5_AFMT_AVI_INFO3__SI = 0x4B24; -constexpr unsigned int mmDIG5_AFMT_INFOFRAME_CONTROL0__SI = 0x4B4D; -constexpr unsigned int mmDIG5_AFMT_ISRC1_0__SI = 0x4B18; -constexpr unsigned int mmDIG5_AFMT_ISRC1_1__SI = 0x4B19; -constexpr unsigned int mmDIG5_AFMT_ISRC1_2__SI = 0x4B1A; -constexpr unsigned int mmDIG5_AFMT_ISRC1_3__SI = 0x4B1B; -constexpr unsigned int mmDIG5_AFMT_ISRC1_4__SI = 0x4B1C; -constexpr unsigned int mmDIG5_AFMT_ISRC2_0__SI = 0x4B1D; -constexpr unsigned int mmDIG5_AFMT_ISRC2_1__SI = 0x4B1E; -constexpr unsigned int mmDIG5_AFMT_ISRC2_2__SI = 0x4B1F; -constexpr unsigned int mmDIG5_AFMT_ISRC2_3__SI = 0x4B20; -constexpr unsigned int mmDIG5_AFMT_MPEG_INFO0__SI = 0x4B25; -constexpr unsigned int mmDIG5_AFMT_MPEG_INFO1__SI = 0x4B26; -constexpr unsigned int mmDIG5_AFMT_RAMP_CONTROL0__SI = 0x4B44; -constexpr unsigned int mmDIG5_AFMT_RAMP_CONTROL1__SI = 0x4B45; -constexpr unsigned int mmDIG5_AFMT_RAMP_CONTROL2__SI = 0x4B46; -constexpr unsigned int mmDIG5_AFMT_RAMP_CONTROL3__SI = 0x4B47; -constexpr unsigned int mmDIG5_AFMT_STATUS__SI = 0x4B4A; -constexpr unsigned int mmDIG5_AFMT_VBI_PACKET_CONTROL__SI = 0x4B4C; -constexpr unsigned int mmDIG5_DIG_CLOCK_PATTERN__SI = 0x4B03; -constexpr unsigned int mmDIG5_DIG_OUTPUT_CRC_CNTL__SI = 0x4B01; -constexpr unsigned int mmDIG5_DIG_OUTPUT_CRC_RESULT__SI = 0x4B02; -constexpr unsigned int mmDIG5_DIG_RANDOM_PATTERN_SEED__SI = 0x4B05; -constexpr unsigned int mmDIG5_DIG_TEST_PATTERN__SI = 0x4B04; -constexpr unsigned int mmDIG5_HDMI_ACR_32_0__SI = 0x4B37; -constexpr unsigned int mmDIG5_HDMI_ACR_32_1__SI = 0x4B38; -constexpr unsigned int mmDIG5_HDMI_ACR_44_0__SI = 0x4B39; -constexpr unsigned int mmDIG5_HDMI_ACR_44_1__SI = 0x4B3A; -constexpr unsigned int mmDIG5_HDMI_ACR_48_0__SI = 0x4B3B; -constexpr unsigned int mmDIG5_HDMI_ACR_48_1__SI = 0x4B3C; -constexpr unsigned int mmDIG5_HDMI_ACR_PACKET_CONTROL__SI = 0x4B0F; -constexpr unsigned int mmDIG5_HDMI_ACR_STATUS_0__SI = 0x4B3D; -constexpr unsigned int mmDIG5_HDMI_ACR_STATUS_1__SI = 0x4B3E; -constexpr unsigned int mmDIG5_HDMI_AUDIO_PACKET_CONTROL__SI = 0x4B0E; -constexpr unsigned int mmDIG5_HDMI_CONTROL__SI = 0x4B0C; -constexpr unsigned int mmDIG5_HDMI_GC__SI = 0x4B16; -constexpr unsigned int mmDIG5_HDMI_GENERIC_PACKET_CONTROL__SI = 0x4B13; -constexpr unsigned int mmDIG5_HDMI_INFOFRAME_CONTROL0__SI = 0x4B11; -constexpr unsigned int mmDIG5_HDMI_INFOFRAME_CONTROL1__SI = 0x4B12; -constexpr unsigned int mmDIG5_HDMI_STATUS__SI = 0x4B0D; -constexpr unsigned int mmDIG5_HDMI_VBI_PACKET_CONTROL__SI = 0x4B10; -constexpr unsigned int mmDIG5_LVDS_DATA_CNTL__SI = 0x4B8C; -constexpr unsigned int mmDIG5_TMDS_CNTL__SI = 0x4B7C; -constexpr unsigned int mmDIG5_TMDS_CONTROL0_FEEDBACK__SI = 0x4B7E; -constexpr unsigned int mmDIG5_TMDS_CONTROL_CHAR__SI = 0x4B7D; -constexpr unsigned int mmDIG5_TMDS_CTL0_1_GEN_CNTL__SI = 0x4B86; -constexpr unsigned int mmDIG5_TMDS_CTL2_3_GEN_CNTL__SI = 0x4B87; -constexpr unsigned int mmDIG5_TMDS_CTL_BITS__SI = 0x4B83; -constexpr unsigned int mmDIG5_TMDS_DCBALANCER_CONTROL__SI = 0x4B84; -constexpr unsigned int mmDIG5_TMDS_DEBUG__SI = 0x4B82; -constexpr unsigned int mmDIG5_TMDS_STEREOSYNC_CTL_SEL__SI = 0x4B7F; -constexpr unsigned int mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1__SI = 0x4B80; -constexpr unsigned int mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3__SI = 0x4B81; -constexpr unsigned int mmDIG_CLOCK_PATTERN__SI = 0x1C03; -constexpr unsigned int mmDIG_OUTPUT_CRC_CNTL__SI = 0x1C01; -constexpr unsigned int mmDIG_OUTPUT_CRC_RESULT__SI = 0x1C02; -constexpr unsigned int mmDIG_RANDOM_PATTERN_SEED__SI = 0x1C05; -constexpr unsigned int mmDIG_TEST_PATTERN__SI = 0x1C04; -constexpr unsigned int mmDISPCLK_CGTT_BLK_CTRL_REG__SI = 0x0128; -constexpr unsigned int mmDISP_INTERRUPT_STATUS_CONTINUE2__SI = 0x183F; -constexpr unsigned int mmDISP_INTERRUPT_STATUS_CONTINUE__SI = 0x183E; -constexpr unsigned int mmDISP_INTERRUPT_STATUS__SI = 0x183D; -constexpr unsigned int mmDISP_TIMER_CONTROL__SI = 0x1842; -constexpr unsigned int mmDLL_CNTL__SI__CI = 0x0AE9; -constexpr unsigned int mmDMCU_CTRL__SI__VI = 0x1600; -constexpr unsigned int mmDMCU_ERAM_RD_CTRL__SI__VI = 0x160B; -constexpr unsigned int mmDMCU_ERAM_RD_DATA__SI__VI = 0x160C; -constexpr unsigned int mmDMCU_ERAM_WR_CTRL__SI__VI = 0x1609; -constexpr unsigned int mmDMCU_ERAM_WR_DATA__SI__VI = 0x160A; -constexpr unsigned int mmDMCU_EVENT_TRIGGER__SI__VI = 0x1611; -constexpr unsigned int mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS__SI__VI = 0x161A; -constexpr unsigned int mmDMCU_FW_CS_HI__SI__VI = 0x1606; -constexpr unsigned int mmDMCU_FW_CS_LO__SI__VI = 0x1607; -constexpr unsigned int mmDMCU_FW_END_ADDR__SI__VI = 0x1604; -constexpr unsigned int mmDMCU_FW_ISR_START_ADDR__SI__VI = 0x1605; -constexpr unsigned int mmDMCU_FW_START_ADDR__SI__VI = 0x1603; -constexpr unsigned int mmDMCU_INTERRUPT_STATUS__SI__VI = 0x1614; -constexpr unsigned int mmDMCU_INTERRUPT_TO_HOST_EN_MASK__SI__VI = 0x1615; -constexpr unsigned int mmDMCU_INTERRUPT_TO_UC_EN_MASK__SI__VI = 0x1616; -constexpr unsigned int mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__SI__VI = 0x1617; -constexpr unsigned int mmDMCU_INT_CNT__SI__VI = 0x1619; -constexpr unsigned int mmDMCU_IRAM_RD_CTRL__SI__VI = 0x160F; -constexpr unsigned int mmDMCU_IRAM_RD_DATA__SI__VI = 0x1610; -constexpr unsigned int mmDMCU_IRAM_WR_CTRL__SI__VI = 0x160D; -constexpr unsigned int mmDMCU_IRAM_WR_DATA__SI__VI = 0x160E; -constexpr unsigned int mmDMCU_PC_START_ADDR__SI__VI = 0x1602; -constexpr unsigned int mmDMCU_RAM_ACCESS_CTRL__SI__VI = 0x1608; -constexpr unsigned int mmDMCU_STATUS__SI__VI = 0x1601; -constexpr unsigned int mmDMCU_TEST_DEBUG_DATA__SI__VI = 0x1627; -constexpr unsigned int mmDMCU_TEST_DEBUG_INDEX__SI__VI = 0x1626; -constexpr unsigned int mmDMCU_UC_INTERNAL_INT_STATUS__SI__VI = 0x1612; -constexpr unsigned int mmDMIF_ARBITRATION_CONTROL__SI__VI = 0x02F9; -constexpr unsigned int mmDMIF_CONTROL__SI__VI = 0x02F6; -constexpr unsigned int mmDMIF_HW_DEBUG__SI__VI = 0x02F8; -constexpr unsigned int mmDMIF_STATUS__SI__VI = 0x02F7; -constexpr unsigned int mmDMIF_TEST_DEBUG_DATA__SI = 0x0313; -constexpr unsigned int mmDMIF_TEST_DEBUG_INDEX__SI = 0x0312; -constexpr unsigned int mmDOUT_POWER_MANAGEMENT_CNTL__SI = 0x1841; -constexpr unsigned int mmDOUT_SCRATCH0__SI = 0x1844; -constexpr unsigned int mmDOUT_SCRATCH1__SI = 0x1845; -constexpr unsigned int mmDOUT_SCRATCH2__SI = 0x1846; -constexpr unsigned int mmDOUT_SCRATCH3__SI = 0x1847; -constexpr unsigned int mmDOUT_SCRATCH4__SI = 0x1848; -constexpr unsigned int mmDOUT_SCRATCH5__SI = 0x1849; -constexpr unsigned int mmDOUT_SCRATCH6__SI = 0x184A; -constexpr unsigned int mmDOUT_SCRATCH7__SI = 0x184B; -constexpr unsigned int mmDOUT_TEST_DEBUG_DATA__SI = 0x184E; -constexpr unsigned int mmDOUT_TEST_DEBUG_INDEX__SI = 0x184D; -constexpr unsigned int mmDP0_DP_CONFIG__SI = 0x1CC2; -constexpr unsigned int mmDP0_DP_DPHY_8B10B_CNTL__SI = 0x1CD3; -constexpr unsigned int mmDP0_DP_DPHY_CNTL__SI = 0x1CD0; -constexpr unsigned int mmDP0_DP_DPHY_CRC_CNTL__SI = 0x1CD7; -constexpr unsigned int mmDP0_DP_DPHY_CRC_EN__SI = 0x1CD6; -constexpr unsigned int mmDP0_DP_DPHY_CRC_RESULT__SI = 0x1CD8; -constexpr unsigned int mmDP0_DP_DPHY_FAST_TRAINING__SI = 0x1CCE; -constexpr unsigned int mmDP0_DP_DPHY_PRBS_CNTL__SI = 0x1CD4; -constexpr unsigned int mmDP0_DP_DPHY_SYM__SI = 0x1CD2; -constexpr unsigned int mmDP0_DP_DPHY_TRAINING_PATTERN_SEL__SI = 0x1CD1; -constexpr unsigned int mmDP0_DP_LINK_CNTL__SI = 0x1CC0; -constexpr unsigned int mmDP0_DP_PIXEL_FORMAT__SI = 0x1CC1; -constexpr unsigned int mmDP0_DP_SEC_AUD_M_READBACK__SI = 0x1CA8; -constexpr unsigned int mmDP0_DP_SEC_AUD_M__SI = 0x1CA7; -constexpr unsigned int mmDP0_DP_SEC_AUD_N_READBACK__SI = 0x1CA6; -constexpr unsigned int mmDP0_DP_SEC_AUD_N__SI = 0x1CA5; -constexpr unsigned int mmDP0_DP_SEC_CNTL__SI = 0x1CA0; -constexpr unsigned int mmDP0_DP_SEC_FRAMING1__SI = 0x1CA1; -constexpr unsigned int mmDP0_DP_SEC_FRAMING2__SI = 0x1CA2; -constexpr unsigned int mmDP0_DP_SEC_FRAMING3__SI = 0x1CA3; -constexpr unsigned int mmDP0_DP_SEC_FRAMING4__SI = 0x1CA4; -constexpr unsigned int mmDP0_DP_SEC_PACKET_CNTL__SI = 0x1CAA; -constexpr unsigned int mmDP0_DP_SEC_TIMESTAMP__SI = 0x1CA9; -constexpr unsigned int mmDP0_DP_STEER_FIFO__SI = 0x1CC4; -constexpr unsigned int mmDP0_DP_TEST_DEBUG_DATA__SI = 0x1CFD; -constexpr unsigned int mmDP0_DP_TEST_DEBUG_INDEX__SI = 0x1CFC; -constexpr unsigned int mmDP0_DP_VID_INTERRUPT_CNTL__SI = 0x1CCF; -constexpr unsigned int mmDP0_DP_VID_MSA_VBID__SI = 0x1CCD; -constexpr unsigned int mmDP0_DP_VID_M__SI = 0x1CCB; -constexpr unsigned int mmDP0_DP_VID_N__SI = 0x1CCA; -constexpr unsigned int mmDP0_DP_VID_STREAM_CNTL__SI = 0x1CC3; -constexpr unsigned int mmDP0_DP_VID_TIMING__SI = 0x1CC9; -constexpr unsigned int mmDP1_DP_CONFIG__SI = 0x1FC2; -constexpr unsigned int mmDP1_DP_DPHY_8B10B_CNTL__SI = 0x1FD3; -constexpr unsigned int mmDP1_DP_DPHY_CNTL__SI = 0x1FD0; -constexpr unsigned int mmDP1_DP_DPHY_CRC_CNTL__SI = 0x1FD7; -constexpr unsigned int mmDP1_DP_DPHY_CRC_EN__SI = 0x1FD6; -constexpr unsigned int mmDP1_DP_DPHY_CRC_RESULT__SI = 0x1FD8; -constexpr unsigned int mmDP1_DP_DPHY_FAST_TRAINING__SI = 0x1FCE; -constexpr unsigned int mmDP1_DP_DPHY_PRBS_CNTL__SI = 0x1FD4; -constexpr unsigned int mmDP1_DP_DPHY_SYM__SI = 0x1FD2; -constexpr unsigned int mmDP1_DP_DPHY_TRAINING_PATTERN_SEL__SI = 0x1FD1; -constexpr unsigned int mmDP1_DP_LINK_CNTL__SI = 0x1FC0; -constexpr unsigned int mmDP1_DP_PIXEL_FORMAT__SI = 0x1FC1; -constexpr unsigned int mmDP1_DP_SEC_AUD_M_READBACK__SI = 0x1FA8; -constexpr unsigned int mmDP1_DP_SEC_AUD_M__SI = 0x1FA7; -constexpr unsigned int mmDP1_DP_SEC_AUD_N_READBACK__SI = 0x1FA6; -constexpr unsigned int mmDP1_DP_SEC_AUD_N__SI = 0x1FA5; -constexpr unsigned int mmDP1_DP_SEC_CNTL__SI = 0x1FA0; -constexpr unsigned int mmDP1_DP_SEC_FRAMING1__SI = 0x1FA1; -constexpr unsigned int mmDP1_DP_SEC_FRAMING2__SI = 0x1FA2; -constexpr unsigned int mmDP1_DP_SEC_FRAMING3__SI = 0x1FA3; -constexpr unsigned int mmDP1_DP_SEC_FRAMING4__SI = 0x1FA4; -constexpr unsigned int mmDP1_DP_SEC_PACKET_CNTL__SI = 0x1FAA; -constexpr unsigned int mmDP1_DP_SEC_TIMESTAMP__SI = 0x1FA9; -constexpr unsigned int mmDP1_DP_STEER_FIFO__SI = 0x1FC4; -constexpr unsigned int mmDP1_DP_TEST_DEBUG_DATA__SI = 0x1FFD; -constexpr unsigned int mmDP1_DP_TEST_DEBUG_INDEX__SI = 0x1FFC; -constexpr unsigned int mmDP1_DP_VID_INTERRUPT_CNTL__SI = 0x1FCF; -constexpr unsigned int mmDP1_DP_VID_MSA_VBID__SI = 0x1FCD; -constexpr unsigned int mmDP1_DP_VID_M__SI = 0x1FCB; -constexpr unsigned int mmDP1_DP_VID_N__SI = 0x1FCA; -constexpr unsigned int mmDP1_DP_VID_STREAM_CNTL__SI = 0x1FC3; -constexpr unsigned int mmDP1_DP_VID_TIMING__SI = 0x1FC9; -constexpr unsigned int mmDP2_DP_CONFIG__SI = 0x42C2; -constexpr unsigned int mmDP2_DP_DPHY_8B10B_CNTL__SI = 0x42D3; -constexpr unsigned int mmDP2_DP_DPHY_CNTL__SI = 0x42D0; -constexpr unsigned int mmDP2_DP_DPHY_CRC_CNTL__SI = 0x42D7; -constexpr unsigned int mmDP2_DP_DPHY_CRC_EN__SI = 0x42D6; -constexpr unsigned int mmDP2_DP_DPHY_CRC_RESULT__SI = 0x42D8; -constexpr unsigned int mmDP2_DP_DPHY_FAST_TRAINING__SI = 0x42CE; -constexpr unsigned int mmDP2_DP_DPHY_PRBS_CNTL__SI = 0x42D4; -constexpr unsigned int mmDP2_DP_DPHY_SYM__SI = 0x42D2; -constexpr unsigned int mmDP2_DP_DPHY_TRAINING_PATTERN_SEL__SI = 0x42D1; -constexpr unsigned int mmDP2_DP_LINK_CNTL__SI = 0x42C0; -constexpr unsigned int mmDP2_DP_PIXEL_FORMAT__SI = 0x42C1; -constexpr unsigned int mmDP2_DP_SEC_AUD_M_READBACK__SI = 0x42A8; -constexpr unsigned int mmDP2_DP_SEC_AUD_M__SI = 0x42A7; -constexpr unsigned int mmDP2_DP_SEC_AUD_N_READBACK__SI = 0x42A6; -constexpr unsigned int mmDP2_DP_SEC_AUD_N__SI = 0x42A5; -constexpr unsigned int mmDP2_DP_SEC_CNTL__SI = 0x42A0; -constexpr unsigned int mmDP2_DP_SEC_FRAMING1__SI = 0x42A1; -constexpr unsigned int mmDP2_DP_SEC_FRAMING2__SI = 0x42A2; -constexpr unsigned int mmDP2_DP_SEC_FRAMING3__SI = 0x42A3; -constexpr unsigned int mmDP2_DP_SEC_FRAMING4__SI = 0x42A4; -constexpr unsigned int mmDP2_DP_SEC_PACKET_CNTL__SI = 0x42AA; -constexpr unsigned int mmDP2_DP_SEC_TIMESTAMP__SI = 0x42A9; -constexpr unsigned int mmDP2_DP_STEER_FIFO__SI = 0x42C4; -constexpr unsigned int mmDP2_DP_TEST_DEBUG_DATA__SI = 0x42FD; -constexpr unsigned int mmDP2_DP_TEST_DEBUG_INDEX__SI = 0x42FC; -constexpr unsigned int mmDP2_DP_VID_INTERRUPT_CNTL__SI = 0x42CF; -constexpr unsigned int mmDP2_DP_VID_MSA_VBID__SI = 0x42CD; -constexpr unsigned int mmDP2_DP_VID_M__SI = 0x42CB; -constexpr unsigned int mmDP2_DP_VID_N__SI = 0x42CA; -constexpr unsigned int mmDP2_DP_VID_STREAM_CNTL__SI = 0x42C3; -constexpr unsigned int mmDP2_DP_VID_TIMING__SI = 0x42C9; -constexpr unsigned int mmDP3_DP_CONFIG__SI = 0x45C2; -constexpr unsigned int mmDP3_DP_DPHY_8B10B_CNTL__SI = 0x45D3; -constexpr unsigned int mmDP3_DP_DPHY_CNTL__SI = 0x45D0; -constexpr unsigned int mmDP3_DP_DPHY_CRC_CNTL__SI = 0x45D7; -constexpr unsigned int mmDP3_DP_DPHY_CRC_EN__SI = 0x45D6; -constexpr unsigned int mmDP3_DP_DPHY_CRC_RESULT__SI = 0x45D8; -constexpr unsigned int mmDP3_DP_DPHY_FAST_TRAINING__SI = 0x45CE; -constexpr unsigned int mmDP3_DP_DPHY_PRBS_CNTL__SI = 0x45D4; -constexpr unsigned int mmDP3_DP_DPHY_SYM__SI = 0x45D2; -constexpr unsigned int mmDP3_DP_DPHY_TRAINING_PATTERN_SEL__SI = 0x45D1; -constexpr unsigned int mmDP3_DP_LINK_CNTL__SI = 0x45C0; -constexpr unsigned int mmDP3_DP_PIXEL_FORMAT__SI = 0x45C1; -constexpr unsigned int mmDP3_DP_SEC_AUD_M_READBACK__SI = 0x45A8; -constexpr unsigned int mmDP3_DP_SEC_AUD_M__SI = 0x45A7; -constexpr unsigned int mmDP3_DP_SEC_AUD_N_READBACK__SI = 0x45A6; -constexpr unsigned int mmDP3_DP_SEC_AUD_N__SI = 0x45A5; -constexpr unsigned int mmDP3_DP_SEC_CNTL__SI = 0x45A0; -constexpr unsigned int mmDP3_DP_SEC_FRAMING1__SI = 0x45A1; -constexpr unsigned int mmDP3_DP_SEC_FRAMING2__SI = 0x45A2; -constexpr unsigned int mmDP3_DP_SEC_FRAMING3__SI = 0x45A3; -constexpr unsigned int mmDP3_DP_SEC_FRAMING4__SI = 0x45A4; -constexpr unsigned int mmDP3_DP_SEC_PACKET_CNTL__SI = 0x45AA; -constexpr unsigned int mmDP3_DP_SEC_TIMESTAMP__SI = 0x45A9; -constexpr unsigned int mmDP3_DP_STEER_FIFO__SI = 0x45C4; -constexpr unsigned int mmDP3_DP_TEST_DEBUG_DATA__SI = 0x45FD; -constexpr unsigned int mmDP3_DP_TEST_DEBUG_INDEX__SI = 0x45FC; -constexpr unsigned int mmDP3_DP_VID_INTERRUPT_CNTL__SI = 0x45CF; -constexpr unsigned int mmDP3_DP_VID_MSA_VBID__SI = 0x45CD; -constexpr unsigned int mmDP3_DP_VID_M__SI = 0x45CB; -constexpr unsigned int mmDP3_DP_VID_N__SI = 0x45CA; -constexpr unsigned int mmDP3_DP_VID_STREAM_CNTL__SI = 0x45C3; -constexpr unsigned int mmDP3_DP_VID_TIMING__SI = 0x45C9; -constexpr unsigned int mmDP4_DP_CONFIG__SI = 0x48C2; -constexpr unsigned int mmDP4_DP_DPHY_8B10B_CNTL__SI = 0x48D3; -constexpr unsigned int mmDP4_DP_DPHY_CNTL__SI = 0x48D0; -constexpr unsigned int mmDP4_DP_DPHY_CRC_CNTL__SI = 0x48D7; -constexpr unsigned int mmDP4_DP_DPHY_CRC_EN__SI = 0x48D6; -constexpr unsigned int mmDP4_DP_DPHY_CRC_RESULT__SI = 0x48D8; -constexpr unsigned int mmDP4_DP_DPHY_FAST_TRAINING__SI = 0x48CE; -constexpr unsigned int mmDP4_DP_DPHY_PRBS_CNTL__SI = 0x48D4; -constexpr unsigned int mmDP4_DP_DPHY_SYM__SI = 0x48D2; -constexpr unsigned int mmDP4_DP_DPHY_TRAINING_PATTERN_SEL__SI = 0x48D1; -constexpr unsigned int mmDP4_DP_LINK_CNTL__SI = 0x48C0; -constexpr unsigned int mmDP4_DP_PIXEL_FORMAT__SI = 0x48C1; -constexpr unsigned int mmDP4_DP_SEC_AUD_M_READBACK__SI = 0x48A8; -constexpr unsigned int mmDP4_DP_SEC_AUD_M__SI = 0x48A7; -constexpr unsigned int mmDP4_DP_SEC_AUD_N_READBACK__SI = 0x48A6; -constexpr unsigned int mmDP4_DP_SEC_AUD_N__SI = 0x48A5; -constexpr unsigned int mmDP4_DP_SEC_CNTL__SI = 0x48A0; -constexpr unsigned int mmDP4_DP_SEC_FRAMING1__SI = 0x48A1; -constexpr unsigned int mmDP4_DP_SEC_FRAMING2__SI = 0x48A2; -constexpr unsigned int mmDP4_DP_SEC_FRAMING3__SI = 0x48A3; -constexpr unsigned int mmDP4_DP_SEC_FRAMING4__SI = 0x48A4; -constexpr unsigned int mmDP4_DP_SEC_PACKET_CNTL__SI = 0x48AA; -constexpr unsigned int mmDP4_DP_SEC_TIMESTAMP__SI = 0x48A9; -constexpr unsigned int mmDP4_DP_STEER_FIFO__SI = 0x48C4; -constexpr unsigned int mmDP4_DP_TEST_DEBUG_DATA__SI = 0x48FD; -constexpr unsigned int mmDP4_DP_TEST_DEBUG_INDEX__SI = 0x48FC; -constexpr unsigned int mmDP4_DP_VID_INTERRUPT_CNTL__SI = 0x48CF; -constexpr unsigned int mmDP4_DP_VID_MSA_VBID__SI = 0x48CD; -constexpr unsigned int mmDP4_DP_VID_M__SI = 0x48CB; -constexpr unsigned int mmDP4_DP_VID_N__SI = 0x48CA; -constexpr unsigned int mmDP4_DP_VID_STREAM_CNTL__SI = 0x48C3; -constexpr unsigned int mmDP4_DP_VID_TIMING__SI = 0x48C9; -constexpr unsigned int mmDP5_DP_CONFIG__SI = 0x4BC2; -constexpr unsigned int mmDP5_DP_DPHY_8B10B_CNTL__SI = 0x4BD3; -constexpr unsigned int mmDP5_DP_DPHY_CNTL__SI = 0x4BD0; -constexpr unsigned int mmDP5_DP_DPHY_CRC_CNTL__SI = 0x4BD7; -constexpr unsigned int mmDP5_DP_DPHY_CRC_EN__SI = 0x4BD6; -constexpr unsigned int mmDP5_DP_DPHY_CRC_RESULT__SI = 0x4BD8; -constexpr unsigned int mmDP5_DP_DPHY_FAST_TRAINING__SI = 0x4BCE; -constexpr unsigned int mmDP5_DP_DPHY_PRBS_CNTL__SI = 0x4BD4; -constexpr unsigned int mmDP5_DP_DPHY_SYM__SI = 0x4BD2; -constexpr unsigned int mmDP5_DP_DPHY_TRAINING_PATTERN_SEL__SI = 0x4BD1; -constexpr unsigned int mmDP5_DP_LINK_CNTL__SI = 0x4BC0; -constexpr unsigned int mmDP5_DP_PIXEL_FORMAT__SI = 0x4BC1; -constexpr unsigned int mmDP5_DP_SEC_AUD_M_READBACK__SI = 0x4BA8; -constexpr unsigned int mmDP5_DP_SEC_AUD_M__SI = 0x4BA7; -constexpr unsigned int mmDP5_DP_SEC_AUD_N_READBACK__SI = 0x4BA6; -constexpr unsigned int mmDP5_DP_SEC_AUD_N__SI = 0x4BA5; -constexpr unsigned int mmDP5_DP_SEC_CNTL__SI = 0x4BA0; -constexpr unsigned int mmDP5_DP_SEC_FRAMING1__SI = 0x4BA1; -constexpr unsigned int mmDP5_DP_SEC_FRAMING2__SI = 0x4BA2; -constexpr unsigned int mmDP5_DP_SEC_FRAMING3__SI = 0x4BA3; -constexpr unsigned int mmDP5_DP_SEC_FRAMING4__SI = 0x4BA4; -constexpr unsigned int mmDP5_DP_SEC_PACKET_CNTL__SI = 0x4BAA; -constexpr unsigned int mmDP5_DP_SEC_TIMESTAMP__SI = 0x4BA9; -constexpr unsigned int mmDP5_DP_STEER_FIFO__SI = 0x4BC4; -constexpr unsigned int mmDP5_DP_TEST_DEBUG_DATA__SI = 0x4BFD; -constexpr unsigned int mmDP5_DP_TEST_DEBUG_INDEX__SI = 0x4BFC; -constexpr unsigned int mmDP5_DP_VID_INTERRUPT_CNTL__SI = 0x4BCF; -constexpr unsigned int mmDP5_DP_VID_MSA_VBID__SI = 0x4BCD; -constexpr unsigned int mmDP5_DP_VID_M__SI = 0x4BCB; -constexpr unsigned int mmDP5_DP_VID_N__SI = 0x4BCA; -constexpr unsigned int mmDP5_DP_VID_STREAM_CNTL__SI = 0x4BC3; -constexpr unsigned int mmDP5_DP_VID_TIMING__SI = 0x4BC9; -constexpr unsigned int mmDP_AUX0_AUX_ARB_CONTROL__SI = 0x1882; -constexpr unsigned int mmDP_AUX0_AUX_CONTROL__SI = 0x1880; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_RX_CONTROL0__SI = 0x188A; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_RX_CONTROL1__SI = 0x188B; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_RX_STATUS__SI = 0x188D; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_TX_CONTROL__SI = 0x1889; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL__SI = 0x1888; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_TX_STATUS__SI = 0x188C; -constexpr unsigned int mmDP_AUX0_AUX_INTERRUPT_CONTROL__SI = 0x1883; -constexpr unsigned int mmDP_AUX0_AUX_LS_DATA__SI = 0x1887; -constexpr unsigned int mmDP_AUX0_AUX_LS_STATUS__SI = 0x1885; -constexpr unsigned int mmDP_AUX0_AUX_SW_CONTROL__SI = 0x1881; -constexpr unsigned int mmDP_AUX0_AUX_SW_DATA__SI = 0x1886; -constexpr unsigned int mmDP_AUX0_AUX_SW_STATUS__SI = 0x1884; -constexpr unsigned int mmDP_AUX1_AUX_ARB_CONTROL__SI = 0x1896; -constexpr unsigned int mmDP_AUX1_AUX_CONTROL__SI = 0x1894; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_RX_CONTROL0__SI = 0x189E; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_RX_CONTROL1__SI = 0x189F; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_RX_STATUS__SI = 0x18A1; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_TX_CONTROL__SI = 0x189D; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL__SI = 0x189C; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_TX_STATUS__SI = 0x18A0; -constexpr unsigned int mmDP_AUX1_AUX_INTERRUPT_CONTROL__SI = 0x1897; -constexpr unsigned int mmDP_AUX1_AUX_LS_DATA__SI = 0x189B; -constexpr unsigned int mmDP_AUX1_AUX_LS_STATUS__SI = 0x1899; -constexpr unsigned int mmDP_AUX1_AUX_SW_CONTROL__SI = 0x1895; -constexpr unsigned int mmDP_AUX1_AUX_SW_DATA__SI = 0x189A; -constexpr unsigned int mmDP_AUX1_AUX_SW_STATUS__SI = 0x1898; -constexpr unsigned int mmDP_AUX2_AUX_ARB_CONTROL__SI = 0x18AA; -constexpr unsigned int mmDP_AUX2_AUX_CONTROL__SI = 0x18A8; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_RX_CONTROL0__SI = 0x18B2; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_RX_CONTROL1__SI = 0x18B3; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_RX_STATUS__SI = 0x18B5; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_TX_CONTROL__SI = 0x18B1; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL__SI = 0x18B0; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_TX_STATUS__SI = 0x18B4; -constexpr unsigned int mmDP_AUX2_AUX_INTERRUPT_CONTROL__SI = 0x18AB; -constexpr unsigned int mmDP_AUX2_AUX_LS_DATA__SI = 0x18AF; -constexpr unsigned int mmDP_AUX2_AUX_LS_STATUS__SI = 0x18AD; -constexpr unsigned int mmDP_AUX2_AUX_SW_CONTROL__SI = 0x18A9; -constexpr unsigned int mmDP_AUX2_AUX_SW_DATA__SI = 0x18AE; -constexpr unsigned int mmDP_AUX2_AUX_SW_STATUS__SI = 0x18AC; -constexpr unsigned int mmDP_AUX3_AUX_ARB_CONTROL__SI = 0x18C2; -constexpr unsigned int mmDP_AUX3_AUX_CONTROL__SI = 0x18C0; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_RX_CONTROL0__SI = 0x18CA; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_RX_CONTROL1__SI = 0x18CB; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_RX_STATUS__SI = 0x18CD; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_TX_CONTROL__SI = 0x18C9; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL__SI = 0x18C8; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_TX_STATUS__SI = 0x18CC; -constexpr unsigned int mmDP_AUX3_AUX_INTERRUPT_CONTROL__SI = 0x18C3; -constexpr unsigned int mmDP_AUX3_AUX_LS_DATA__SI = 0x18C7; -constexpr unsigned int mmDP_AUX3_AUX_LS_STATUS__SI = 0x18C5; -constexpr unsigned int mmDP_AUX3_AUX_SW_CONTROL__SI = 0x18C1; -constexpr unsigned int mmDP_AUX3_AUX_SW_DATA__SI = 0x18C6; -constexpr unsigned int mmDP_AUX3_AUX_SW_STATUS__SI = 0x18C4; -constexpr unsigned int mmDP_AUX4_AUX_ARB_CONTROL__SI = 0x18D6; -constexpr unsigned int mmDP_AUX4_AUX_CONTROL__SI = 0x18D4; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_RX_CONTROL0__SI = 0x18DE; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_RX_CONTROL1__SI = 0x18DF; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_RX_STATUS__SI = 0x18E1; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_TX_CONTROL__SI = 0x18DD; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL__SI = 0x18DC; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_TX_STATUS__SI = 0x18E0; -constexpr unsigned int mmDP_AUX4_AUX_INTERRUPT_CONTROL__SI = 0x18D7; -constexpr unsigned int mmDP_AUX4_AUX_LS_DATA__SI = 0x18DB; -constexpr unsigned int mmDP_AUX4_AUX_LS_STATUS__SI = 0x18D9; -constexpr unsigned int mmDP_AUX4_AUX_SW_CONTROL__SI = 0x18D5; -constexpr unsigned int mmDP_AUX4_AUX_SW_DATA__SI = 0x18DA; -constexpr unsigned int mmDP_AUX4_AUX_SW_STATUS__SI = 0x18D8; -constexpr unsigned int mmDP_AUX5_AUX_ARB_CONTROL__SI = 0x18EA; -constexpr unsigned int mmDP_AUX5_AUX_CONTROL__SI = 0x18E8; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_RX_CONTROL0__SI = 0x18F2; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_RX_CONTROL1__SI = 0x18F3; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_RX_STATUS__SI = 0x18F5; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_TX_CONTROL__SI = 0x18F1; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL__SI = 0x18F0; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_TX_STATUS__SI = 0x18F4; -constexpr unsigned int mmDP_AUX5_AUX_INTERRUPT_CONTROL__SI = 0x18EB; -constexpr unsigned int mmDP_AUX5_AUX_LS_DATA__SI = 0x18EF; -constexpr unsigned int mmDP_AUX5_AUX_LS_STATUS__SI = 0x18ED; -constexpr unsigned int mmDP_AUX5_AUX_SW_CONTROL__SI = 0x18E9; -constexpr unsigned int mmDP_AUX5_AUX_SW_DATA__SI = 0x18EE; -constexpr unsigned int mmDP_AUX5_AUX_SW_STATUS__SI = 0x18EC; -constexpr unsigned int mmDP_CONFIG__SI = 0x1CC2; -constexpr unsigned int mmDP_DPHY_8B10B_CNTL__SI = 0x1CD3; -constexpr unsigned int mmDP_DPHY_CNTL__SI = 0x1CD0; -constexpr unsigned int mmDP_DPHY_CRC_CNTL__SI = 0x1CD7; -constexpr unsigned int mmDP_DPHY_CRC_EN__SI = 0x1CD6; -constexpr unsigned int mmDP_DPHY_CRC_RESULT__SI = 0x1CD8; -constexpr unsigned int mmDP_DPHY_FAST_TRAINING__SI = 0x1CCE; -constexpr unsigned int mmDP_DPHY_PRBS_CNTL__SI = 0x1CD4; -constexpr unsigned int mmDP_DPHY_SYM__SI = 0x1CD2; -constexpr unsigned int mmDP_DPHY_TRAINING_PATTERN_SEL__SI = 0x1CD1; -constexpr unsigned int mmDP_DTO0_MODULO__SI = 0x0171; -constexpr unsigned int mmDP_DTO0_PHASE__SI = 0x0170; -constexpr unsigned int mmDP_DTO1_MODULO__SI = 0x0173; -constexpr unsigned int mmDP_DTO1_PHASE__SI = 0x0172; -constexpr unsigned int mmDP_DTO2_MODULO__SI = 0x0175; -constexpr unsigned int mmDP_DTO2_PHASE__SI = 0x0174; -constexpr unsigned int mmDP_DTO3_MODULO__SI = 0x0177; -constexpr unsigned int mmDP_DTO3_PHASE__SI = 0x0176; -constexpr unsigned int mmDP_DTO4_MODULO__SI = 0x0179; -constexpr unsigned int mmDP_DTO4_PHASE__SI = 0x0178; -constexpr unsigned int mmDP_DTO5_MODULO__SI = 0x017B; -constexpr unsigned int mmDP_DTO5_PHASE__SI = 0x017A; -constexpr unsigned int mmDP_LINK_CNTL__SI = 0x1CC0; -constexpr unsigned int mmDP_PIXEL_FORMAT__SI = 0x1CC1; -constexpr unsigned int mmDP_SEC_AUD_M_READBACK__SI = 0x1CA8; -constexpr unsigned int mmDP_SEC_AUD_M__SI = 0x1CA7; -constexpr unsigned int mmDP_SEC_AUD_N_READBACK__SI = 0x1CA6; -constexpr unsigned int mmDP_SEC_AUD_N__SI = 0x1CA5; -constexpr unsigned int mmDP_SEC_CNTL__SI = 0x1CA0; -constexpr unsigned int mmDP_SEC_FRAMING1__SI = 0x1CA1; -constexpr unsigned int mmDP_SEC_FRAMING2__SI = 0x1CA2; -constexpr unsigned int mmDP_SEC_FRAMING3__SI = 0x1CA3; -constexpr unsigned int mmDP_SEC_FRAMING4__SI = 0x1CA4; -constexpr unsigned int mmDP_SEC_PACKET_CNTL__SI = 0x1CAA; -constexpr unsigned int mmDP_SEC_TIMESTAMP__SI = 0x1CA9; -constexpr unsigned int mmDP_STEER_FIFO__SI = 0x1CC4; -constexpr unsigned int mmDP_TEST_DEBUG_DATA__SI = 0x1CFD; -constexpr unsigned int mmDP_TEST_DEBUG_INDEX__SI = 0x1CFC; -constexpr unsigned int mmDP_VID_INTERRUPT_CNTL__SI = 0x1CCF; -constexpr unsigned int mmDP_VID_MSA_VBID__SI = 0x1CCD; -constexpr unsigned int mmDP_VID_M__SI = 0x1CCB; -constexpr unsigned int mmDP_VID_N__SI = 0x1CCA; -constexpr unsigned int mmDP_VID_STREAM_CNTL__SI = 0x1CC3; -constexpr unsigned int mmDP_VID_TIMING__SI = 0x1CC9; -constexpr unsigned int mmDVOACLKC_CNTL__SI = 0x014E; -constexpr unsigned int mmDVOACLKC_MVP_CNTL__SI = 0x014D; -constexpr unsigned int mmDVOACLKD_CNTL__SI = 0x014C; -constexpr unsigned int mmDVO_CONTROL__SI = 0x185B; -constexpr unsigned int mmDVO_CRC2_SIG_MASK__SI = 0x185D; -constexpr unsigned int mmDVO_CRC2_SIG_RESULT__SI = 0x185E; -constexpr unsigned int mmDVO_CRC_EN__SI = 0x185C; -constexpr unsigned int mmDVO_ENABLE__SI = 0x1858; -constexpr unsigned int mmDVO_OUTPUT__SI = 0x185A; -constexpr unsigned int mmDVO_SOURCE_SELECT__SI = 0x1859; -constexpr unsigned int mmDVO_STRENGTH_CONTROL__SI = 0x195D; -constexpr unsigned int mmEXT_OVERSCAN_LEFT_RIGHT__SI__VI = 0x1B5E; -constexpr unsigned int mmEXT_OVERSCAN_TOP_BOTTOM__SI__VI = 0x1B5F; -constexpr unsigned int mmFBC_CLIENT_REGION_MASK__SI = 0x16EB; -constexpr unsigned int mmFBC_CNTL__SI = 0x16D0; -constexpr unsigned int mmFBC_COMP_CNTL__SI = 0x16D4; -constexpr unsigned int mmFBC_COMP_MODE__SI = 0x16D5; -constexpr unsigned int mmFBC_CSM_REGION_OFFSET_01__SI = 0x16E9; -constexpr unsigned int mmFBC_CSM_REGION_OFFSET_23__SI = 0x16EA; -constexpr unsigned int mmFBC_DEBUG0__SI = 0x16D6; -constexpr unsigned int mmFBC_DEBUG1__SI = 0x16D7; -constexpr unsigned int mmFBC_DEBUG2__SI = 0x16D8; -constexpr unsigned int mmFBC_DEBUG_COMP__SI = 0x16EC; -constexpr unsigned int mmFBC_DEBUG_CSR_RDATA__SI = 0x16EE; -constexpr unsigned int mmFBC_DEBUG_CSR_WDATA__SI = 0x16EF; -constexpr unsigned int mmFBC_DEBUG_CSR__SI = 0x16ED; -constexpr unsigned int mmFBC_IDLE_FORCE_CLEAR_MASK__SI = 0x16D2; -constexpr unsigned int mmFBC_IDLE_MASK__SI = 0x16D1; -constexpr unsigned int mmFBC_IND_LUT0__SI = 0x16D9; -constexpr unsigned int mmFBC_IND_LUT10__SI = 0x16E3; -constexpr unsigned int mmFBC_IND_LUT11__SI = 0x16E4; -constexpr unsigned int mmFBC_IND_LUT12__SI = 0x16E5; -constexpr unsigned int mmFBC_IND_LUT13__SI = 0x16E6; -constexpr unsigned int mmFBC_IND_LUT14__SI = 0x16E7; -constexpr unsigned int mmFBC_IND_LUT15__SI = 0x16E8; -constexpr unsigned int mmFBC_IND_LUT1__SI = 0x16DA; -constexpr unsigned int mmFBC_IND_LUT2__SI = 0x16DB; -constexpr unsigned int mmFBC_IND_LUT3__SI = 0x16DC; -constexpr unsigned int mmFBC_IND_LUT4__SI = 0x16DD; -constexpr unsigned int mmFBC_IND_LUT5__SI = 0x16DE; -constexpr unsigned int mmFBC_IND_LUT6__SI = 0x16DF; -constexpr unsigned int mmFBC_IND_LUT7__SI = 0x16E0; -constexpr unsigned int mmFBC_IND_LUT8__SI = 0x16E1; -constexpr unsigned int mmFBC_IND_LUT9__SI = 0x16E2; -constexpr unsigned int mmFBC_MISC__SI = 0x16F0; -constexpr unsigned int mmFBC_START_STOP_DELAY__SI = 0x16D3; -constexpr unsigned int mmFBC_TEST_DEBUG_DATA__SI = 0x16F5; -constexpr unsigned int mmFBC_TEST_DEBUG_INDEX__SI = 0x16F4; -constexpr unsigned int mmFMT0_FMT_BIT_DEPTH_CONTROL__SI__VI = 0x1BF2; -constexpr unsigned int mmFMT0_FMT_CLAMP_CNTL__SI__VI = 0x1BF9; -constexpr unsigned int mmFMT0_FMT_CONTROL__SI__VI = 0x1BEE; -constexpr unsigned int mmFMT0_FMT_CRC_CNTL__SI__VI = 0x1BFA; -constexpr unsigned int mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI__VI = 0x1BFC; -constexpr unsigned int mmFMT0_FMT_CRC_SIG_BLUE_CONTROL__SI__VI = 0x1BFE; -constexpr unsigned int mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK__SI__VI = 0x1BFB; -constexpr unsigned int mmFMT0_FMT_CRC_SIG_RED_GREEN__SI__VI = 0x1BFD; -constexpr unsigned int mmFMT0_FMT_DEBUG_CNTL__SI__VI = 0x1BFF; -constexpr unsigned int mmFMT0_FMT_DITHER_RAND_B_SEED__SI__VI = 0x1BF5; -constexpr unsigned int mmFMT0_FMT_DITHER_RAND_G_SEED__SI__VI = 0x1BF4; -constexpr unsigned int mmFMT0_FMT_DITHER_RAND_R_SEED__SI__VI = 0x1BF3; -constexpr unsigned int mmFMT0_FMT_DYNAMIC_EXP_CNTL__SI__VI = 0x1BED; -constexpr unsigned int mmFMT0_FMT_FORCE_DATA_0_1__SI__VI = 0x1BF0; -constexpr unsigned int mmFMT0_FMT_FORCE_DATA_2_3__SI__VI = 0x1BF1; -constexpr unsigned int mmFMT0_FMT_FORCE_OUTPUT_CNTL__SI__VI = 0x1BEF; -constexpr unsigned int mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI__VI = 0x1BF6; -constexpr unsigned int mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI__VI = 0x1BF7; -constexpr unsigned int mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI__VI = 0x1BF8; -constexpr unsigned int mmFMT1_FMT_BIT_DEPTH_CONTROL__SI = 0x1EF2; -constexpr unsigned int mmFMT1_FMT_CLAMP_CNTL__SI = 0x1EF9; -constexpr unsigned int mmFMT1_FMT_CONTROL__SI = 0x1EEE; -constexpr unsigned int mmFMT1_FMT_CRC_CNTL__SI = 0x1EFA; -constexpr unsigned int mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI = 0x1EFC; -constexpr unsigned int mmFMT1_FMT_CRC_SIG_BLUE_CONTROL__SI = 0x1EFE; -constexpr unsigned int mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK__SI = 0x1EFB; -constexpr unsigned int mmFMT1_FMT_CRC_SIG_RED_GREEN__SI = 0x1EFD; -constexpr unsigned int mmFMT1_FMT_DEBUG_CNTL__SI = 0x1EFF; -constexpr unsigned int mmFMT1_FMT_DITHER_RAND_B_SEED__SI = 0x1EF5; -constexpr unsigned int mmFMT1_FMT_DITHER_RAND_G_SEED__SI = 0x1EF4; -constexpr unsigned int mmFMT1_FMT_DITHER_RAND_R_SEED__SI = 0x1EF3; -constexpr unsigned int mmFMT1_FMT_DYNAMIC_EXP_CNTL__SI = 0x1EED; -constexpr unsigned int mmFMT1_FMT_FORCE_DATA_0_1__SI = 0x1EF0; -constexpr unsigned int mmFMT1_FMT_FORCE_DATA_2_3__SI = 0x1EF1; -constexpr unsigned int mmFMT1_FMT_FORCE_OUTPUT_CNTL__SI = 0x1EEF; -constexpr unsigned int mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI = 0x1EF6; -constexpr unsigned int mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI = 0x1EF7; -constexpr unsigned int mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI = 0x1EF8; -constexpr unsigned int mmFMT2_FMT_BIT_DEPTH_CONTROL__SI = 0x41F2; -constexpr unsigned int mmFMT2_FMT_CLAMP_CNTL__SI = 0x41F9; -constexpr unsigned int mmFMT2_FMT_CONTROL__SI = 0x41EE; -constexpr unsigned int mmFMT2_FMT_CRC_CNTL__SI = 0x41FA; -constexpr unsigned int mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI = 0x41FC; -constexpr unsigned int mmFMT2_FMT_CRC_SIG_BLUE_CONTROL__SI = 0x41FE; -constexpr unsigned int mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK__SI = 0x41FB; -constexpr unsigned int mmFMT2_FMT_CRC_SIG_RED_GREEN__SI = 0x41FD; -constexpr unsigned int mmFMT2_FMT_DEBUG_CNTL__SI = 0x41FF; -constexpr unsigned int mmFMT2_FMT_DITHER_RAND_B_SEED__SI = 0x41F5; -constexpr unsigned int mmFMT2_FMT_DITHER_RAND_G_SEED__SI = 0x41F4; -constexpr unsigned int mmFMT2_FMT_DITHER_RAND_R_SEED__SI = 0x41F3; -constexpr unsigned int mmFMT2_FMT_DYNAMIC_EXP_CNTL__SI = 0x41ED; -constexpr unsigned int mmFMT2_FMT_FORCE_DATA_0_1__SI = 0x41F0; -constexpr unsigned int mmFMT2_FMT_FORCE_DATA_2_3__SI = 0x41F1; -constexpr unsigned int mmFMT2_FMT_FORCE_OUTPUT_CNTL__SI = 0x41EF; -constexpr unsigned int mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI = 0x41F6; -constexpr unsigned int mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI = 0x41F7; -constexpr unsigned int mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI = 0x41F8; -constexpr unsigned int mmFMT3_FMT_BIT_DEPTH_CONTROL__SI = 0x44F2; -constexpr unsigned int mmFMT3_FMT_CLAMP_CNTL__SI = 0x44F9; -constexpr unsigned int mmFMT3_FMT_CONTROL__SI = 0x44EE; -constexpr unsigned int mmFMT3_FMT_CRC_CNTL__SI = 0x44FA; -constexpr unsigned int mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI = 0x44FC; -constexpr unsigned int mmFMT3_FMT_CRC_SIG_BLUE_CONTROL__SI = 0x44FE; -constexpr unsigned int mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK__SI = 0x44FB; -constexpr unsigned int mmFMT3_FMT_CRC_SIG_RED_GREEN__SI = 0x44FD; -constexpr unsigned int mmFMT3_FMT_DEBUG_CNTL__SI = 0x44FF; -constexpr unsigned int mmFMT3_FMT_DITHER_RAND_B_SEED__SI = 0x44F5; -constexpr unsigned int mmFMT3_FMT_DITHER_RAND_G_SEED__SI = 0x44F4; -constexpr unsigned int mmFMT3_FMT_DITHER_RAND_R_SEED__SI = 0x44F3; -constexpr unsigned int mmFMT3_FMT_DYNAMIC_EXP_CNTL__SI = 0x44ED; -constexpr unsigned int mmFMT3_FMT_FORCE_DATA_0_1__SI = 0x44F0; -constexpr unsigned int mmFMT3_FMT_FORCE_DATA_2_3__SI = 0x44F1; -constexpr unsigned int mmFMT3_FMT_FORCE_OUTPUT_CNTL__SI = 0x44EF; -constexpr unsigned int mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI = 0x44F6; -constexpr unsigned int mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI = 0x44F7; -constexpr unsigned int mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI = 0x44F8; -constexpr unsigned int mmFMT4_FMT_BIT_DEPTH_CONTROL__SI = 0x47F2; -constexpr unsigned int mmFMT4_FMT_CLAMP_CNTL__SI = 0x47F9; -constexpr unsigned int mmFMT4_FMT_CONTROL__SI = 0x47EE; -constexpr unsigned int mmFMT4_FMT_CRC_CNTL__SI = 0x47FA; -constexpr unsigned int mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI = 0x47FC; -constexpr unsigned int mmFMT4_FMT_CRC_SIG_BLUE_CONTROL__SI = 0x47FE; -constexpr unsigned int mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK__SI = 0x47FB; -constexpr unsigned int mmFMT4_FMT_CRC_SIG_RED_GREEN__SI = 0x47FD; -constexpr unsigned int mmFMT4_FMT_DEBUG_CNTL__SI = 0x47FF; -constexpr unsigned int mmFMT4_FMT_DITHER_RAND_B_SEED__SI = 0x47F5; -constexpr unsigned int mmFMT4_FMT_DITHER_RAND_G_SEED__SI = 0x47F4; -constexpr unsigned int mmFMT4_FMT_DITHER_RAND_R_SEED__SI = 0x47F3; -constexpr unsigned int mmFMT4_FMT_DYNAMIC_EXP_CNTL__SI = 0x47ED; -constexpr unsigned int mmFMT4_FMT_FORCE_DATA_0_1__SI = 0x47F0; -constexpr unsigned int mmFMT4_FMT_FORCE_DATA_2_3__SI = 0x47F1; -constexpr unsigned int mmFMT4_FMT_FORCE_OUTPUT_CNTL__SI = 0x47EF; -constexpr unsigned int mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI = 0x47F6; -constexpr unsigned int mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI = 0x47F7; -constexpr unsigned int mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI = 0x47F8; -constexpr unsigned int mmFMT5_FMT_BIT_DEPTH_CONTROL__SI = 0x4AF2; -constexpr unsigned int mmFMT5_FMT_CLAMP_CNTL__SI = 0x4AF9; -constexpr unsigned int mmFMT5_FMT_CONTROL__SI = 0x4AEE; -constexpr unsigned int mmFMT5_FMT_CRC_CNTL__SI = 0x4AFA; -constexpr unsigned int mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__SI = 0x4AFC; -constexpr unsigned int mmFMT5_FMT_CRC_SIG_BLUE_CONTROL__SI = 0x4AFE; -constexpr unsigned int mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK__SI = 0x4AFB; -constexpr unsigned int mmFMT5_FMT_CRC_SIG_RED_GREEN__SI = 0x4AFD; -constexpr unsigned int mmFMT5_FMT_DEBUG_CNTL__SI = 0x4AFF; -constexpr unsigned int mmFMT5_FMT_DITHER_RAND_B_SEED__SI = 0x4AF5; -constexpr unsigned int mmFMT5_FMT_DITHER_RAND_G_SEED__SI = 0x4AF4; -constexpr unsigned int mmFMT5_FMT_DITHER_RAND_R_SEED__SI = 0x4AF3; -constexpr unsigned int mmFMT5_FMT_DYNAMIC_EXP_CNTL__SI = 0x4AED; -constexpr unsigned int mmFMT5_FMT_FORCE_DATA_0_1__SI = 0x4AF0; -constexpr unsigned int mmFMT5_FMT_FORCE_DATA_2_3__SI = 0x4AF1; -constexpr unsigned int mmFMT5_FMT_FORCE_OUTPUT_CNTL__SI = 0x4AEF; -constexpr unsigned int mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI = 0x4AF6; -constexpr unsigned int mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI = 0x4AF7; -constexpr unsigned int mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI = 0x4AF8; -constexpr unsigned int mmFMT_BIT_DEPTH_CONTROL__SI__VI = 0x1BF2; -constexpr unsigned int mmFMT_CLAMP_CNTL__SI__VI = 0x1BF9; -constexpr unsigned int mmFMT_CONTROL__SI__VI = 0x1BEE; -constexpr unsigned int mmFMT_CRC_CNTL__SI__VI = 0x1BFA; -constexpr unsigned int mmFMT_CRC_SIG_BLUE_CONTROL_MASK__SI__VI = 0x1BFC; -constexpr unsigned int mmFMT_CRC_SIG_BLUE_CONTROL__SI__VI = 0x1BFE; -constexpr unsigned int mmFMT_CRC_SIG_RED_GREEN_MASK__SI__VI = 0x1BFB; -constexpr unsigned int mmFMT_CRC_SIG_RED_GREEN__SI__VI = 0x1BFD; -constexpr unsigned int mmFMT_DEBUG_CNTL__SI__VI = 0x1BFF; -constexpr unsigned int mmFMT_DITHER_RAND_B_SEED__SI__VI = 0x1BF5; -constexpr unsigned int mmFMT_DITHER_RAND_G_SEED__SI__VI = 0x1BF4; -constexpr unsigned int mmFMT_DITHER_RAND_R_SEED__SI__VI = 0x1BF3; -constexpr unsigned int mmFMT_DYNAMIC_EXP_CNTL__SI__VI = 0x1BED; -constexpr unsigned int mmFMT_FORCE_DATA_0_1__SI__VI = 0x1BF0; -constexpr unsigned int mmFMT_FORCE_DATA_2_3__SI__VI = 0x1BF1; -constexpr unsigned int mmFMT_FORCE_OUTPUT_CNTL__SI__VI = 0x1BEF; -constexpr unsigned int mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI__VI = 0x1BF6; -constexpr unsigned int mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI__VI = 0x1BF7; -constexpr unsigned int mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI__VI = 0x1BF8; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_END_0__CI__VI = 0x1403; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_END_1__CI__VI = 0x1405; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_END_2__CI__VI = 0x1407; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_END_3__CI__VI = 0x1409; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_END_4__CI__VI = 0x140B; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_END_5__CI__VI = 0x140D; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_END_6__CI__VI = 0x140F; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_END_7__CI__VI = 0x1411; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_START_0__CI__VI = 0x1402; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_START_1__CI__VI = 0x1404; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_START_2__CI__VI = 0x1406; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_START_3__CI__VI = 0x1408; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_START_4__CI__VI = 0x140A; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_START_5__CI__VI = 0x140C; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_START_6__CI__VI = 0x140E; -constexpr unsigned int mmGARLIC_FLUSH_ADDR_START_7__CI__VI = 0x1410; -constexpr unsigned int mmGARLIC_FLUSH_CNTL__CI__VI = 0x1401; -constexpr unsigned int mmGARLIC_FLUSH_REQ__CI__VI = 0x1412; -constexpr unsigned int mmGB_ADDR_CONFIG = 0x263E; -constexpr unsigned int mmGB_BACKEND_MAP = 0x263F; -constexpr unsigned int mmGB_EDC_MODE = 0x307E; -constexpr unsigned int mmGB_GPU_ID = 0x2640; -constexpr unsigned int mmGB_MACROTILE_MODE0__CI__VI = 0x2664; -constexpr unsigned int mmGB_MACROTILE_MODE10__CI__VI = 0x266E; -constexpr unsigned int mmGB_MACROTILE_MODE11__CI__VI = 0x266F; -constexpr unsigned int mmGB_MACROTILE_MODE12__CI__VI = 0x2670; -constexpr unsigned int mmGB_MACROTILE_MODE13__CI__VI = 0x2671; -constexpr unsigned int mmGB_MACROTILE_MODE14__CI__VI = 0x2672; -constexpr unsigned int mmGB_MACROTILE_MODE15__CI__VI = 0x2673; -constexpr unsigned int mmGB_MACROTILE_MODE1__CI__VI = 0x2665; -constexpr unsigned int mmGB_MACROTILE_MODE2__CI__VI = 0x2666; -constexpr unsigned int mmGB_MACROTILE_MODE3__CI__VI = 0x2667; -constexpr unsigned int mmGB_MACROTILE_MODE4__CI__VI = 0x2668; -constexpr unsigned int mmGB_MACROTILE_MODE5__CI__VI = 0x2669; -constexpr unsigned int mmGB_MACROTILE_MODE6__CI__VI = 0x266A; -constexpr unsigned int mmGB_MACROTILE_MODE7__CI__VI = 0x266B; -constexpr unsigned int mmGB_MACROTILE_MODE8__CI__VI = 0x266C; -constexpr unsigned int mmGB_MACROTILE_MODE9__CI__VI = 0x266D; -constexpr unsigned int mmGB_TILE_MODE0 = 0x2644; -constexpr unsigned int mmGB_TILE_MODE1 = 0x2645; -constexpr unsigned int mmGB_TILE_MODE10 = 0x264E; -constexpr unsigned int mmGB_TILE_MODE11 = 0x264F; -constexpr unsigned int mmGB_TILE_MODE12 = 0x2650; -constexpr unsigned int mmGB_TILE_MODE13 = 0x2651; -constexpr unsigned int mmGB_TILE_MODE14 = 0x2652; -constexpr unsigned int mmGB_TILE_MODE15 = 0x2653; -constexpr unsigned int mmGB_TILE_MODE16 = 0x2654; -constexpr unsigned int mmGB_TILE_MODE17 = 0x2655; -constexpr unsigned int mmGB_TILE_MODE18 = 0x2656; -constexpr unsigned int mmGB_TILE_MODE19 = 0x2657; -constexpr unsigned int mmGB_TILE_MODE2 = 0x2646; -constexpr unsigned int mmGB_TILE_MODE20 = 0x2658; -constexpr unsigned int mmGB_TILE_MODE21 = 0x2659; -constexpr unsigned int mmGB_TILE_MODE22 = 0x265A; -constexpr unsigned int mmGB_TILE_MODE23 = 0x265B; -constexpr unsigned int mmGB_TILE_MODE24 = 0x265C; -constexpr unsigned int mmGB_TILE_MODE25 = 0x265D; -constexpr unsigned int mmGB_TILE_MODE26 = 0x265E; -constexpr unsigned int mmGB_TILE_MODE27 = 0x265F; -constexpr unsigned int mmGB_TILE_MODE28 = 0x2660; -constexpr unsigned int mmGB_TILE_MODE29 = 0x2661; -constexpr unsigned int mmGB_TILE_MODE3 = 0x2647; -constexpr unsigned int mmGB_TILE_MODE30 = 0x2662; -constexpr unsigned int mmGB_TILE_MODE31 = 0x2663; -constexpr unsigned int mmGB_TILE_MODE4 = 0x2648; -constexpr unsigned int mmGB_TILE_MODE5 = 0x2649; -constexpr unsigned int mmGB_TILE_MODE6 = 0x264A; -constexpr unsigned int mmGB_TILE_MODE7 = 0x264B; -constexpr unsigned int mmGB_TILE_MODE8 = 0x264C; -constexpr unsigned int mmGB_TILE_MODE9 = 0x264D; -constexpr unsigned int mmGCK_SMC_IND_DATA__CI__VI = 0x0081; -constexpr unsigned int mmGCK_SMC_IND_INDEX__CI__VI = 0x0080; -constexpr unsigned int mmGC_USER_PRIM_CONFIG__CI__VI = 0x2241; -constexpr unsigned int mmGC_USER_RB_BACKEND_DISABLE = 0x26DF; -constexpr unsigned int mmGC_USER_RB_REDUNDANCY__CI__VI = 0x26DE; -constexpr unsigned int mmGC_USER_SHADER_ARRAY_CONFIG = 0x2270; -constexpr unsigned int mmGC_USER_SYS_RB_BACKEND_DISABLE = 0x03A1; -constexpr unsigned int mmGDS_ATOM_BASE__CI__VI = 0xC40C; -constexpr unsigned int mmGDS_ATOM_BASE__SI = 0x25CE; -constexpr unsigned int mmGDS_ATOM_CNTL__CI__VI = 0xC40A; -constexpr unsigned int mmGDS_ATOM_CNTL__SI = 0x25CC; -constexpr unsigned int mmGDS_ATOM_COMPLETE__CI__VI = 0xC40B; -constexpr unsigned int mmGDS_ATOM_COMPLETE__SI = 0x25CD; -constexpr unsigned int mmGDS_ATOM_DST__CI__VI = 0xC410; -constexpr unsigned int mmGDS_ATOM_DST__SI = 0x25D2; -constexpr unsigned int mmGDS_ATOM_OFFSET0__CI__VI = 0xC40E; -constexpr unsigned int mmGDS_ATOM_OFFSET0__SI = 0x25D0; -constexpr unsigned int mmGDS_ATOM_OFFSET1__CI__VI = 0xC40F; -constexpr unsigned int mmGDS_ATOM_OFFSET1__SI = 0x25D1; -constexpr unsigned int mmGDS_ATOM_OP__CI__VI = 0xC411; -constexpr unsigned int mmGDS_ATOM_OP__SI = 0x25D3; -constexpr unsigned int mmGDS_ATOM_READ0_U__CI__VI = 0xC417; -constexpr unsigned int mmGDS_ATOM_READ0_U__SI = 0x25D9; -constexpr unsigned int mmGDS_ATOM_READ0__CI__VI = 0xC416; -constexpr unsigned int mmGDS_ATOM_READ0__SI = 0x25D8; -constexpr unsigned int mmGDS_ATOM_READ1_U__CI__VI = 0xC419; -constexpr unsigned int mmGDS_ATOM_READ1_U__SI = 0x25DB; -constexpr unsigned int mmGDS_ATOM_READ1__CI__VI = 0xC418; -constexpr unsigned int mmGDS_ATOM_READ1__SI = 0x25DA; -constexpr unsigned int mmGDS_ATOM_SIZE__CI__VI = 0xC40D; -constexpr unsigned int mmGDS_ATOM_SIZE__SI = 0x25CF; -constexpr unsigned int mmGDS_ATOM_SRC0_U__CI__VI = 0xC413; -constexpr unsigned int mmGDS_ATOM_SRC0_U__SI = 0x25D5; -constexpr unsigned int mmGDS_ATOM_SRC0__CI__VI = 0xC412; -constexpr unsigned int mmGDS_ATOM_SRC0__SI = 0x25D4; -constexpr unsigned int mmGDS_ATOM_SRC1_U__CI__VI = 0xC415; -constexpr unsigned int mmGDS_ATOM_SRC1_U__SI = 0x25D7; -constexpr unsigned int mmGDS_ATOM_SRC1__CI__VI = 0xC414; -constexpr unsigned int mmGDS_ATOM_SRC1__SI = 0x25D6; -constexpr unsigned int mmGDS_CNTL_STATUS = 0x25C1; -constexpr unsigned int mmGDS_COMPUTE_MAX_WAVE_ID__CI__VI = 0x3348; -constexpr unsigned int mmGDS_CONFIG = 0x25C0; -constexpr unsigned int mmGDS_DEBUG_CNTL__CI__VI = 0x25C8; -constexpr unsigned int mmGDS_DEBUG_CNTL__SI = 0x25DE; -constexpr unsigned int mmGDS_DEBUG_DATA__CI__VI = 0x25C9; -constexpr unsigned int mmGDS_DEBUG_DATA__SI = 0x25DF; -constexpr unsigned int mmGDS_ENHANCE2__CI__VI = 0x25C2; -constexpr unsigned int mmGDS_ENHANCE__CI__VI = 0x334B; -constexpr unsigned int mmGDS_ENHANCE__SI = 0x25DC; -constexpr unsigned int mmGDS_GRBM_SECDED_CNT__CI = 0x25C6; -constexpr unsigned int mmGDS_GRBM_SECDED_CNT__SI = 0x25E3; -constexpr unsigned int mmGDS_GWS_RESET0__CI__VI = 0x3344; -constexpr unsigned int mmGDS_GWS_RESET1__CI__VI = 0x3345; -constexpr unsigned int mmGDS_GWS_RESOURCE_CNTL__CI__VI = 0xC41A; -constexpr unsigned int mmGDS_GWS_RESOURCE_CNTL__SI = 0x25E0; -constexpr unsigned int mmGDS_GWS_RESOURCE_CNT__CI__VI = 0xC41C; -constexpr unsigned int mmGDS_GWS_RESOURCE_RESET__CI__VI = 0x3346; -constexpr unsigned int mmGDS_GWS_RESOURCE__CI__VI = 0xC41B; -constexpr unsigned int mmGDS_GWS_RESOURCE__SI = 0x25E1; -constexpr unsigned int mmGDS_GWS_VMID0__CI__VI = 0x3320; -constexpr unsigned int mmGDS_GWS_VMID10__CI__VI = 0x332A; -constexpr unsigned int mmGDS_GWS_VMID11__CI__VI = 0x332B; -constexpr unsigned int mmGDS_GWS_VMID12__CI__VI = 0x332C; -constexpr unsigned int mmGDS_GWS_VMID13__CI__VI = 0x332D; -constexpr unsigned int mmGDS_GWS_VMID14__CI__VI = 0x332E; -constexpr unsigned int mmGDS_GWS_VMID15__CI__VI = 0x332F; -constexpr unsigned int mmGDS_GWS_VMID1__CI__VI = 0x3321; -constexpr unsigned int mmGDS_GWS_VMID2__CI__VI = 0x3322; -constexpr unsigned int mmGDS_GWS_VMID3__CI__VI = 0x3323; -constexpr unsigned int mmGDS_GWS_VMID4__CI__VI = 0x3324; -constexpr unsigned int mmGDS_GWS_VMID5__CI__VI = 0x3325; -constexpr unsigned int mmGDS_GWS_VMID6__CI__VI = 0x3326; -constexpr unsigned int mmGDS_GWS_VMID7__CI__VI = 0x3327; -constexpr unsigned int mmGDS_GWS_VMID8__CI__VI = 0x3328; -constexpr unsigned int mmGDS_GWS_VMID9__CI__VI = 0x3329; -constexpr unsigned int mmGDS_OA_ADDRESS__CI__VI = 0xC41F; -constexpr unsigned int mmGDS_OA_CGPG_RESTORE__CI__VI = 0x334C; -constexpr unsigned int mmGDS_OA_CNTL__CI__VI = 0xC41D; -constexpr unsigned int mmGDS_OA_COUNTER__CI__VI = 0xC41E; -constexpr unsigned int mmGDS_OA_DED__CI = 0x25C7; -constexpr unsigned int mmGDS_OA_DED__SI = 0x25E4; -constexpr unsigned int mmGDS_OA_INCDEC__CI__VI = 0xC420; -constexpr unsigned int mmGDS_OA_RESET_MASK__CI__VI = 0x3349; -constexpr unsigned int mmGDS_OA_RESET__CI__VI = 0x334A; -constexpr unsigned int mmGDS_OA_RING_SIZE__CI__VI = 0xC421; -constexpr unsigned int mmGDS_OA_VMID0__CI__VI = 0x3330; -constexpr unsigned int mmGDS_OA_VMID10__CI__VI = 0x333A; -constexpr unsigned int mmGDS_OA_VMID11__CI__VI = 0x333B; -constexpr unsigned int mmGDS_OA_VMID12__CI__VI = 0x333C; -constexpr unsigned int mmGDS_OA_VMID13__CI__VI = 0x333D; -constexpr unsigned int mmGDS_OA_VMID14__CI__VI = 0x333E; -constexpr unsigned int mmGDS_OA_VMID15__CI__VI = 0x333F; -constexpr unsigned int mmGDS_OA_VMID1__CI__VI = 0x3331; -constexpr unsigned int mmGDS_OA_VMID2__CI__VI = 0x3332; -constexpr unsigned int mmGDS_OA_VMID3__CI__VI = 0x3333; -constexpr unsigned int mmGDS_OA_VMID4__CI__VI = 0x3334; -constexpr unsigned int mmGDS_OA_VMID5__CI__VI = 0x3335; -constexpr unsigned int mmGDS_OA_VMID6__CI__VI = 0x3336; -constexpr unsigned int mmGDS_OA_VMID7__CI__VI = 0x3337; -constexpr unsigned int mmGDS_OA_VMID8__CI__VI = 0x3338; -constexpr unsigned int mmGDS_OA_VMID9__CI__VI = 0x3339; -constexpr unsigned int mmGDS_PERFCOUNTER0_HI__CI__VI = 0xD281; -constexpr unsigned int mmGDS_PERFCOUNTER0_HI__SI = 0x25E7; -constexpr unsigned int mmGDS_PERFCOUNTER0_LO__CI__VI = 0xD280; -constexpr unsigned int mmGDS_PERFCOUNTER0_LO__SI = 0x25E6; -constexpr unsigned int mmGDS_PERFCOUNTER0_SELECT1__CI__VI = 0xDA84; -constexpr unsigned int mmGDS_PERFCOUNTER0_SELECT__CI__VI = 0xDA80; -constexpr unsigned int mmGDS_PERFCOUNTER0_SELECT__SI = 0x25E5; -constexpr unsigned int mmGDS_PERFCOUNTER1_HI__CI__VI = 0xD283; -constexpr unsigned int mmGDS_PERFCOUNTER1_HI__SI = 0x25EA; -constexpr unsigned int mmGDS_PERFCOUNTER1_LO__CI__VI = 0xD282; -constexpr unsigned int mmGDS_PERFCOUNTER1_LO__SI = 0x25E9; -constexpr unsigned int mmGDS_PERFCOUNTER1_SELECT__CI__VI = 0xDA81; -constexpr unsigned int mmGDS_PERFCOUNTER1_SELECT__SI = 0x25E8; -constexpr unsigned int mmGDS_PERFCOUNTER2_HI__CI__VI = 0xD285; -constexpr unsigned int mmGDS_PERFCOUNTER2_HI__SI = 0x25ED; -constexpr unsigned int mmGDS_PERFCOUNTER2_LO__CI__VI = 0xD284; -constexpr unsigned int mmGDS_PERFCOUNTER2_LO__SI = 0x25EC; -constexpr unsigned int mmGDS_PERFCOUNTER2_SELECT__CI__VI = 0xDA82; -constexpr unsigned int mmGDS_PERFCOUNTER2_SELECT__SI = 0x25EB; -constexpr unsigned int mmGDS_PERFCOUNTER3_HI__CI__VI = 0xD287; -constexpr unsigned int mmGDS_PERFCOUNTER3_HI__SI = 0x25F0; -constexpr unsigned int mmGDS_PERFCOUNTER3_LO__CI__VI = 0xD286; -constexpr unsigned int mmGDS_PERFCOUNTER3_LO__SI = 0x25EF; -constexpr unsigned int mmGDS_PERFCOUNTER3_SELECT__CI__VI = 0xDA83; -constexpr unsigned int mmGDS_PERFCOUNTER3_SELECT__SI = 0x25EE; -constexpr unsigned int mmGDS_PROTECTION_FAULT__CI__VI = 0x25C3; -constexpr unsigned int mmGDS_RD_ADDR__CI__VI = 0xC400; -constexpr unsigned int mmGDS_RD_ADDR__SI = 0x25C2; -constexpr unsigned int mmGDS_RD_BURST_ADDR__CI__VI = 0xC402; -constexpr unsigned int mmGDS_RD_BURST_ADDR__SI = 0x25C4; -constexpr unsigned int mmGDS_RD_BURST_COUNT__CI__VI = 0xC403; -constexpr unsigned int mmGDS_RD_BURST_COUNT__SI = 0x25C5; -constexpr unsigned int mmGDS_RD_BURST_DATA__CI__VI = 0xC404; -constexpr unsigned int mmGDS_RD_BURST_DATA__SI = 0x25C6; -constexpr unsigned int mmGDS_RD_DATA__CI__VI = 0xC401; -constexpr unsigned int mmGDS_RD_DATA__SI = 0x25C3; -constexpr unsigned int mmGDS_SECDED_CNT__CI = 0x25C5; -constexpr unsigned int mmGDS_SECDED_CNT__SI = 0x25E2; -constexpr unsigned int mmGDS_VMID0_BASE__CI__VI = 0x3300; -constexpr unsigned int mmGDS_VMID0_SIZE__CI__VI = 0x3301; -constexpr unsigned int mmGDS_VMID10_BASE__CI__VI = 0x3314; -constexpr unsigned int mmGDS_VMID10_SIZE__CI__VI = 0x3315; -constexpr unsigned int mmGDS_VMID11_BASE__CI__VI = 0x3316; -constexpr unsigned int mmGDS_VMID11_SIZE__CI__VI = 0x3317; -constexpr unsigned int mmGDS_VMID12_BASE__CI__VI = 0x3318; -constexpr unsigned int mmGDS_VMID12_SIZE__CI__VI = 0x3319; -constexpr unsigned int mmGDS_VMID13_BASE__CI__VI = 0x331A; -constexpr unsigned int mmGDS_VMID13_SIZE__CI__VI = 0x331B; -constexpr unsigned int mmGDS_VMID14_BASE__CI__VI = 0x331C; -constexpr unsigned int mmGDS_VMID14_SIZE__CI__VI = 0x331D; -constexpr unsigned int mmGDS_VMID15_BASE__CI__VI = 0x331E; -constexpr unsigned int mmGDS_VMID15_SIZE__CI__VI = 0x331F; -constexpr unsigned int mmGDS_VMID1_BASE__CI__VI = 0x3302; -constexpr unsigned int mmGDS_VMID1_SIZE__CI__VI = 0x3303; -constexpr unsigned int mmGDS_VMID2_BASE__CI__VI = 0x3304; -constexpr unsigned int mmGDS_VMID2_SIZE__CI__VI = 0x3305; -constexpr unsigned int mmGDS_VMID3_BASE__CI__VI = 0x3306; -constexpr unsigned int mmGDS_VMID3_SIZE__CI__VI = 0x3307; -constexpr unsigned int mmGDS_VMID4_BASE__CI__VI = 0x3308; -constexpr unsigned int mmGDS_VMID4_SIZE__CI__VI = 0x3309; -constexpr unsigned int mmGDS_VMID5_BASE__CI__VI = 0x330A; -constexpr unsigned int mmGDS_VMID5_SIZE__CI__VI = 0x330B; -constexpr unsigned int mmGDS_VMID6_BASE__CI__VI = 0x330C; -constexpr unsigned int mmGDS_VMID6_SIZE__CI__VI = 0x330D; -constexpr unsigned int mmGDS_VMID7_BASE__CI__VI = 0x330E; -constexpr unsigned int mmGDS_VMID7_SIZE__CI__VI = 0x330F; -constexpr unsigned int mmGDS_VMID8_BASE__CI__VI = 0x3310; -constexpr unsigned int mmGDS_VMID8_SIZE__CI__VI = 0x3311; -constexpr unsigned int mmGDS_VMID9_BASE__CI__VI = 0x3312; -constexpr unsigned int mmGDS_VMID9_SIZE__CI__VI = 0x3313; -constexpr unsigned int mmGDS_VM_PROTECTION_FAULT__CI__VI = 0x25C4; -constexpr unsigned int mmGDS_WRITE_COMPLETE__CI__VI = 0xC409; -constexpr unsigned int mmGDS_WRITE_COMPLETE__SI = 0x25CB; -constexpr unsigned int mmGDS_WR_ADDR__CI__VI = 0xC405; -constexpr unsigned int mmGDS_WR_ADDR__SI = 0x25C7; -constexpr unsigned int mmGDS_WR_BURST_ADDR__CI__VI = 0xC407; -constexpr unsigned int mmGDS_WR_BURST_ADDR__SI = 0x25C9; -constexpr unsigned int mmGDS_WR_BURST_DATA__CI__VI = 0xC408; -constexpr unsigned int mmGDS_WR_BURST_DATA__SI = 0x25CA; -constexpr unsigned int mmGDS_WR_DATA__CI__VI = 0xC406; -constexpr unsigned int mmGDS_WR_DATA__SI = 0x25C8; -constexpr unsigned int mmGENENB__SI__VI = 0x00F0; -constexpr unsigned int mmGENERAL_PWRMGT__SI = 0x01E0; -constexpr unsigned int mmGENERIC_I2C_CONTROL__SI = 0x1834; -constexpr unsigned int mmGENERIC_I2C_DATA__SI = 0x183A; -constexpr unsigned int mmGENERIC_I2C_INTERRUPT_CONTROL__SI = 0x1835; -constexpr unsigned int mmGENERIC_I2C_PIN_DEBUG__SI = 0x183C; -constexpr unsigned int mmGENERIC_I2C_PIN_SELECTION__SI = 0x183B; -constexpr unsigned int mmGENERIC_I2C_SETUP__SI = 0x1838; -constexpr unsigned int mmGENERIC_I2C_SPEED__SI = 0x1837; -constexpr unsigned int mmGENERIC_I2C_STATUS__SI = 0x1836; -constexpr unsigned int mmGENERIC_I2C_TRANSACTION__SI = 0x1839; -constexpr unsigned int mmGENFC_RD__SI__VI = 0x00F2; -constexpr unsigned int mmGENFC_WT__SI__VI = 0x00EE; -constexpr unsigned int mmGENMO_RD__SI__VI = 0x00F3; -constexpr unsigned int mmGENMO_WT__SI__VI = 0x00F0; -constexpr unsigned int mmGENS0__SI__VI = 0x00F0; -constexpr unsigned int mmGENS1__SI__VI = 0x00EE; -constexpr unsigned int mmGFX_COPY_STATE = 0xA1F4; -constexpr unsigned int mmGFX_PIPE_CONTROL__CI__VI = 0x226D; -constexpr unsigned int mmGFX_PIPE_PRIORITY__CI__VI = 0xF87F; -constexpr unsigned int mmGMCON_DEBUG__CI__VI = 0x0D5F; -constexpr unsigned int mmGMCON_MASK__CI__VI = 0x0D52; -constexpr unsigned int mmGMCON_MISC2__CI__VI = 0x0D44; -constexpr unsigned int mmGMCON_MISC3__CI__VI = 0x0D51; -constexpr unsigned int mmGMCON_MISC__CI__VI = 0x0D43; -constexpr unsigned int mmGMCON_PERF_MON_CNTL0__CI__VI = 0x0D4A; -constexpr unsigned int mmGMCON_PERF_MON_CNTL1__CI__VI = 0x0D4B; -constexpr unsigned int mmGMCON_PERF_MON_RSLT0__CI__VI = 0x0D4C; -constexpr unsigned int mmGMCON_PERF_MON_RSLT1__CI__VI = 0x0D4D; -constexpr unsigned int mmGMCON_PGFSM_CONFIG__CI__VI = 0x0D4E; -constexpr unsigned int mmGMCON_PGFSM_READ__CI__VI = 0x0D50; -constexpr unsigned int mmGMCON_PGFSM_WRITE__CI__VI = 0x0D4F; -constexpr unsigned int mmGMCON_RENG_EXECUTE__CI__VI = 0x0D42; -constexpr unsigned int mmGMCON_RENG_RAM_DATA__CI__VI = 0x0D41; -constexpr unsigned int mmGMCON_RENG_RAM_INDEX__CI__VI = 0x0D40; -constexpr unsigned int mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__CI__VI = 0x0D48; -constexpr unsigned int mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__CI__VI = 0x0D49; -constexpr unsigned int mmGMCON_STCTRL_REGISTER_SAVE_RANGE0__CI__VI = 0x0D45; -constexpr unsigned int mmGMCON_STCTRL_REGISTER_SAVE_RANGE1__CI__VI = 0x0D46; -constexpr unsigned int mmGMCON_STCTRL_REGISTER_SAVE_RANGE2__CI__VI = 0x0D47; -constexpr unsigned int mmGPIOPAD_A__CI__VI = 0x0183; -constexpr unsigned int mmGPIOPAD_A__SI = 0x05E7; -constexpr unsigned int mmGPIOPAD_EN__CI__VI = 0x0184; -constexpr unsigned int mmGPIOPAD_EN__SI = 0x05E8; -constexpr unsigned int mmGPIOPAD_EXTERN_TRIG_CNTL__CI__VI = 0x018D; -constexpr unsigned int mmGPIOPAD_EXTERN_TRIG_CNTL__SI = 0x05F1; -constexpr unsigned int mmGPIOPAD_INT_EN__CI__VI = 0x018A; -constexpr unsigned int mmGPIOPAD_INT_EN__SI = 0x05EE; -constexpr unsigned int mmGPIOPAD_INT_POLARITY__CI__VI = 0x018C; -constexpr unsigned int mmGPIOPAD_INT_POLARITY__SI = 0x05F0; -constexpr unsigned int mmGPIOPAD_INT_STAT_AK__CI__VI = 0x0189; -constexpr unsigned int mmGPIOPAD_INT_STAT_AK__SI = 0x05ED; -constexpr unsigned int mmGPIOPAD_INT_STAT_EN__CI__VI = 0x0187; -constexpr unsigned int mmGPIOPAD_INT_STAT_EN__SI = 0x05EB; -constexpr unsigned int mmGPIOPAD_INT_STAT__CI__VI = 0x0188; -constexpr unsigned int mmGPIOPAD_INT_STAT__SI = 0x05EC; -constexpr unsigned int mmGPIOPAD_INT_TYPE__CI__VI = 0x018B; -constexpr unsigned int mmGPIOPAD_INT_TYPE__SI = 0x05EF; -constexpr unsigned int mmGPIOPAD_MASK__CI__VI = 0x0182; -constexpr unsigned int mmGPIOPAD_MASK__SI = 0x05E6; -constexpr unsigned int mmGPIOPAD_PD_EN__CI__VI = 0x0193; -constexpr unsigned int mmGPIOPAD_PD_EN__SI = 0x05F4; -constexpr unsigned int mmGPIOPAD_PINSTRAPS__CI__VI = 0x0186; -constexpr unsigned int mmGPIOPAD_PINSTRAPS__SI = 0x05EA; -constexpr unsigned int mmGPIOPAD_PU_EN__CI__VI = 0x0192; -constexpr unsigned int mmGPIOPAD_PU_EN__SI = 0x05F3; -constexpr unsigned int mmGPIOPAD_RCVR_SEL__CI__VI = 0x0191; -constexpr unsigned int mmGPIOPAD_RCVR_SEL__SI = 0x05F2; -constexpr unsigned int mmGPIOPAD_STRENGTH__CI__VI = 0x0181; -constexpr unsigned int mmGPIOPAD_STRENGTH__SI = 0x05E5; -constexpr unsigned int mmGPIOPAD_SW_INT_STAT__CI__VI = 0x0180; -constexpr unsigned int mmGPIOPAD_SW_INT_STAT__SI = 0x05E4; -constexpr unsigned int mmGPIOPAD_Y__CI__VI = 0x0185; -constexpr unsigned int mmGPIOPAD_Y__SI = 0x05E9; -constexpr unsigned int mmGPU_GARLIC_FLUSH_DONE__CI__VI = 0x1414; -constexpr unsigned int mmGPU_GARLIC_FLUSH_REQ__CI__VI = 0x1413; -constexpr unsigned int mmGPU_HDP_FLUSH_DONE__CI__VI = 0x1538; -constexpr unsigned int mmGPU_HDP_FLUSH_REQ__CI__VI = 0x1537; -constexpr unsigned int mmGRBM_CNTL = 0x2000; -constexpr unsigned int mmGRBM_DEBUG = 0x2014; -constexpr unsigned int mmGRBM_DEBUG_CNTL = 0x2009; -constexpr unsigned int mmGRBM_DEBUG_DATA = 0x200A; -constexpr unsigned int mmGRBM_DEBUG_SNAPSHOT = 0x2015; -constexpr unsigned int mmGRBM_GFX_CLKEN_CNTL = 0x200C; -constexpr unsigned int mmGRBM_GFX_INDEX__CI__VI = 0xC200; -constexpr unsigned int mmGRBM_GFX_INDEX__SI = 0x200B; -constexpr unsigned int mmGRBM_INT_CNTL = 0x2018; -constexpr unsigned int mmGRBM_NOWHERE = 0x203F; -constexpr unsigned int mmGRBM_PERFCOUNTER0_HI__CI__VI = 0xD041; -constexpr unsigned int mmGRBM_PERFCOUNTER0_HI__SI = 0x201F; -constexpr unsigned int mmGRBM_PERFCOUNTER0_LO__CI__VI = 0xD040; -constexpr unsigned int mmGRBM_PERFCOUNTER0_LO__SI = 0x201E; -constexpr unsigned int mmGRBM_PERFCOUNTER0_SELECT__CI__VI = 0xD840; -constexpr unsigned int mmGRBM_PERFCOUNTER0_SELECT__SI = 0x201C; -constexpr unsigned int mmGRBM_PERFCOUNTER1_HI__CI__VI = 0xD044; -constexpr unsigned int mmGRBM_PERFCOUNTER1_HI__SI = 0x2021; -constexpr unsigned int mmGRBM_PERFCOUNTER1_LO__CI__VI = 0xD043; -constexpr unsigned int mmGRBM_PERFCOUNTER1_LO__SI = 0x2020; -constexpr unsigned int mmGRBM_PERFCOUNTER1_SELECT__CI__VI = 0xD841; -constexpr unsigned int mmGRBM_PERFCOUNTER1_SELECT__SI = 0x201D; -constexpr unsigned int mmGRBM_PWR_CNTL = 0x2003; -constexpr unsigned int mmGRBM_READ_ERROR = 0x2016; -constexpr unsigned int mmGRBM_READ_ERROR2__CI__VI = 0x2017; -constexpr unsigned int mmGRBM_SCRATCH_REG0 = 0x2040; -constexpr unsigned int mmGRBM_SCRATCH_REG1 = 0x2041; -constexpr unsigned int mmGRBM_SCRATCH_REG2 = 0x2042; -constexpr unsigned int mmGRBM_SCRATCH_REG3 = 0x2043; -constexpr unsigned int mmGRBM_SCRATCH_REG4 = 0x2044; -constexpr unsigned int mmGRBM_SCRATCH_REG5 = 0x2045; -constexpr unsigned int mmGRBM_SCRATCH_REG6 = 0x2046; -constexpr unsigned int mmGRBM_SCRATCH_REG7 = 0x2047; -constexpr unsigned int mmGRBM_SE0_PERFCOUNTER_HI__CI__VI = 0xD046; -constexpr unsigned int mmGRBM_SE0_PERFCOUNTER_HI__SI = 0x202B; -constexpr unsigned int mmGRBM_SE0_PERFCOUNTER_LO__CI__VI = 0xD045; -constexpr unsigned int mmGRBM_SE0_PERFCOUNTER_LO__SI = 0x202A; -constexpr unsigned int mmGRBM_SE0_PERFCOUNTER_SELECT__CI__VI = 0xD842; -constexpr unsigned int mmGRBM_SE0_PERFCOUNTER_SELECT__SI = 0x2026; -constexpr unsigned int mmGRBM_SE1_PERFCOUNTER_HI__CI__VI = 0xD048; -constexpr unsigned int mmGRBM_SE1_PERFCOUNTER_HI__SI = 0x202D; -constexpr unsigned int mmGRBM_SE1_PERFCOUNTER_LO__CI__VI = 0xD047; -constexpr unsigned int mmGRBM_SE1_PERFCOUNTER_LO__SI = 0x202C; -constexpr unsigned int mmGRBM_SE1_PERFCOUNTER_SELECT__CI__VI = 0xD843; -constexpr unsigned int mmGRBM_SE1_PERFCOUNTER_SELECT__SI = 0x2027; -constexpr unsigned int mmGRBM_SE2_PERFCOUNTER_HI__CI__VI = 0xD04A; -constexpr unsigned int mmGRBM_SE2_PERFCOUNTER_LO__CI__VI = 0xD049; -constexpr unsigned int mmGRBM_SE2_PERFCOUNTER_SELECT__CI__VI = 0xD844; -constexpr unsigned int mmGRBM_SE3_PERFCOUNTER_HI__CI__VI = 0xD04C; -constexpr unsigned int mmGRBM_SE3_PERFCOUNTER_LO__CI__VI = 0xD04B; -constexpr unsigned int mmGRBM_SE3_PERFCOUNTER_SELECT__CI__VI = 0xD845; -constexpr unsigned int mmGRBM_SKEW_CNTL = 0x2001; -constexpr unsigned int mmGRBM_SOFT_RESET = 0x2008; -constexpr unsigned int mmGRBM_STATUS = 0x2004; -constexpr unsigned int mmGRBM_STATUS2 = 0x2002; -constexpr unsigned int mmGRBM_STATUS_SE0 = 0x2005; -constexpr unsigned int mmGRBM_STATUS_SE1 = 0x2006; -constexpr unsigned int mmGRBM_STATUS_SE2__CI__VI = 0x200E; -constexpr unsigned int mmGRBM_STATUS_SE3__CI__VI = 0x200F; -constexpr unsigned int mmGRBM_WAIT_IDLE_CLOCKS = 0x200D; -constexpr unsigned int mmGRPH8_DATA__SI__VI = 0x00F3; -constexpr unsigned int mmGRPH8_IDX__SI__VI = 0x00F3; -constexpr unsigned int mmGRPH_COMPRESS_PITCH__SI__VI = 0x1A1A; -constexpr unsigned int mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI__VI = 0x1A1B; -constexpr unsigned int mmGRPH_COMPRESS_SURFACE_ADDRESS__SI__VI = 0x1A19; -constexpr unsigned int mmGRPH_CONTROL = 0x1A01; -constexpr unsigned int mmGRPH_DFQ_CONTROL__SI__VI = 0x1A14; -constexpr unsigned int mmGRPH_DFQ_STATUS__SI__VI = 0x1A15; -constexpr unsigned int mmGRPH_ENABLE__SI__VI = 0x1A00; -constexpr unsigned int mmGRPH_FLIP_CONTROL__SI__VI = 0x1A12; -constexpr unsigned int mmGRPH_INTERRUPT_CONTROL__SI__VI = 0x1A17; -constexpr unsigned int mmGRPH_INTERRUPT_STATUS__SI__VI = 0x1A16; -constexpr unsigned int mmGRPH_LUT_10BIT_BYPASS__SI__VI = 0x1A02; -constexpr unsigned int mmGRPH_PITCH__SI__VI = 0x1A06; -constexpr unsigned int mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SI__VI = 0x1A07; -constexpr unsigned int mmGRPH_PRIMARY_SURFACE_ADDRESS__SI__VI = 0x1A04; -constexpr unsigned int mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI__VI = 0x1A08; -constexpr unsigned int mmGRPH_SECONDARY_SURFACE_ADDRESS__SI__VI = 0x1A05; -constexpr unsigned int mmGRPH_SURFACE_ADDRESS_HIGH_INUSE__SI__VI = 0x1A18; -constexpr unsigned int mmGRPH_SURFACE_ADDRESS_INUSE__SI__VI = 0x1A13; -constexpr unsigned int mmGRPH_SURFACE_OFFSET_X__SI__VI = 0x1A09; -constexpr unsigned int mmGRPH_SURFACE_OFFSET_Y__SI__VI = 0x1A0A; -constexpr unsigned int mmGRPH_SWAP_CNTL__SI__VI = 0x1A03; -constexpr unsigned int mmGRPH_UPDATE__SI__VI = 0x1A11; -constexpr unsigned int mmGRPH_X_END__SI__VI = 0x1A0D; -constexpr unsigned int mmGRPH_X_START__SI__VI = 0x1A0B; -constexpr unsigned int mmGRPH_Y_END__SI__VI = 0x1A0E; -constexpr unsigned int mmGRPH_Y_START__SI__VI = 0x1A0C; -constexpr unsigned int mmHDMI_ACR_32_0__SI = 0x1C37; -constexpr unsigned int mmHDMI_ACR_32_1__SI = 0x1C38; -constexpr unsigned int mmHDMI_ACR_44_0__SI = 0x1C39; -constexpr unsigned int mmHDMI_ACR_44_1__SI = 0x1C3A; -constexpr unsigned int mmHDMI_ACR_48_0__SI = 0x1C3B; -constexpr unsigned int mmHDMI_ACR_48_1__SI = 0x1C3C; -constexpr unsigned int mmHDMI_ACR_PACKET_CONTROL__SI = 0x1C0F; -constexpr unsigned int mmHDMI_ACR_STATUS_0__SI = 0x1C3D; -constexpr unsigned int mmHDMI_ACR_STATUS_1__SI = 0x1C3E; -constexpr unsigned int mmHDMI_AUDIO_PACKET_CONTROL__SI = 0x1C0E; -constexpr unsigned int mmHDMI_CONTROL__SI = 0x1C0C; -constexpr unsigned int mmHDMI_GC__SI = 0x1C16; -constexpr unsigned int mmHDMI_GENERIC_PACKET_CONTROL__SI = 0x1C13; -constexpr unsigned int mmHDMI_INFOFRAME_CONTROL0__SI = 0x1C11; -constexpr unsigned int mmHDMI_INFOFRAME_CONTROL1__SI = 0x1C12; -constexpr unsigned int mmHDMI_STATUS__SI = 0x1C0D; -constexpr unsigned int mmHDMI_VBI_PACKET_CONTROL__SI = 0x1C10; -constexpr unsigned int mmHDP_DEBUG0 = 0x0BCC; -constexpr unsigned int mmHDP_DEBUG1 = 0x0BCD; -constexpr unsigned int mmHDP_HOST_PATH_CNTL = 0x0B00; -constexpr unsigned int mmHDP_LAST_SURFACE_HIT = 0x0BCE; -constexpr unsigned int mmHDP_MEM_COHERENCY_FLUSH_CNTL = 0x1520; -constexpr unsigned int mmHDP_NONSURFACE_BASE = 0x0B01; -constexpr unsigned int mmHDP_NONSURFACE_INFO = 0x0B02; -constexpr unsigned int mmHDP_NONSURFACE_SIZE = 0x0B03; -constexpr unsigned int mmHDP_NONSURF_FLAGS = 0x0BC9; -constexpr unsigned int mmHDP_NONSURF_FLAGS_CLR = 0x0BCA; -constexpr unsigned int mmHDP_OUTSTANDING_REQ = 0x0BD1; -constexpr unsigned int mmHDP_REG_COHERENCY_FLUSH_CNTL = 0x1528; -constexpr unsigned int mmHDP_SC_MULTI_CHIP_CNTL = 0x0BD0; -constexpr unsigned int mmHDP_SW_SEMAPHORE = 0x0BCB; -constexpr unsigned int mmHDP_TILING_CONFIG = 0x0BCF; -constexpr unsigned int mmHDP_XDP_BUSY_STS = 0x0C3E; -constexpr unsigned int mmHDP_XDP_CGTT_BLK_CTRL = 0x0C33; -constexpr unsigned int mmHDP_XDP_CHKN = 0x0C40; -constexpr unsigned int mmHDP_XDP_D2H_BAR_UPDATE = 0x0C02; -constexpr unsigned int mmHDP_XDP_D2H_FLUSH = 0x0C01; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_10 = 0x0C0A; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_11 = 0x0C0B; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_12 = 0x0C0C; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_13 = 0x0C0D; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_14 = 0x0C0E; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_15 = 0x0C0F; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_16 = 0x0C10; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_17 = 0x0C11; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_18 = 0x0C12; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_19 = 0x0C13; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_20 = 0x0C14; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_21 = 0x0C15; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_22 = 0x0C16; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_23 = 0x0C17; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_24 = 0x0C18; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_25 = 0x0C19; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_26 = 0x0C1A; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_27 = 0x0C1B; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_28 = 0x0C1C; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_29 = 0x0C1D; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_3 = 0x0C03; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_30 = 0x0C1E; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_31 = 0x0C1F; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_32 = 0x0C20; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_33 = 0x0C21; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_34 = 0x0C22; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_4 = 0x0C04; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_5 = 0x0C05; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_6 = 0x0C06; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_7 = 0x0C07; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_8 = 0x0C08; -constexpr unsigned int mmHDP_XDP_D2H_RSVD_9 = 0x0C09; -constexpr unsigned int mmHDP_XDP_DBG_ADDR = 0x0C41; -constexpr unsigned int mmHDP_XDP_DBG_DATA = 0x0C42; -constexpr unsigned int mmHDP_XDP_DBG_MASK = 0x0C43; -constexpr unsigned int mmHDP_XDP_DIRECT2HDP_FIRST = 0x0C00; -constexpr unsigned int mmHDP_XDP_DIRECT2HDP_LAST = 0x0C23; -constexpr unsigned int mmHDP_XDP_FLUSH_ARMED_STS = 0x0C3C; -constexpr unsigned int mmHDP_XDP_FLUSH_CNTR0_STS = 0x0C3D; -constexpr unsigned int mmHDP_XDP_HDP_IPH_CFG = 0x0C31; -constexpr unsigned int mmHDP_XDP_HDP_MBX_MC_CFG = 0x0C2D; -constexpr unsigned int mmHDP_XDP_HDP_MC_CFG = 0x0C2E; -constexpr unsigned int mmHDP_XDP_HST_CFG = 0x0C2F; -constexpr unsigned int mmHDP_XDP_P2P_BAR0 = 0x0C34; -constexpr unsigned int mmHDP_XDP_P2P_BAR1 = 0x0C35; -constexpr unsigned int mmHDP_XDP_P2P_BAR2 = 0x0C36; -constexpr unsigned int mmHDP_XDP_P2P_BAR3 = 0x0C37; -constexpr unsigned int mmHDP_XDP_P2P_BAR4 = 0x0C38; -constexpr unsigned int mmHDP_XDP_P2P_BAR5 = 0x0C39; -constexpr unsigned int mmHDP_XDP_P2P_BAR6 = 0x0C3A; -constexpr unsigned int mmHDP_XDP_P2P_BAR7 = 0x0C3B; -constexpr unsigned int mmHDP_XDP_P2P_BAR_CFG = 0x0C24; -constexpr unsigned int mmHDP_XDP_P2P_MBX_ADDR0 = 0x0C26; -constexpr unsigned int mmHDP_XDP_P2P_MBX_ADDR1 = 0x0C27; -constexpr unsigned int mmHDP_XDP_P2P_MBX_ADDR2 = 0x0C28; -constexpr unsigned int mmHDP_XDP_P2P_MBX_ADDR3 = 0x0C29; -constexpr unsigned int mmHDP_XDP_P2P_MBX_ADDR4 = 0x0C2A; -constexpr unsigned int mmHDP_XDP_P2P_MBX_ADDR5 = 0x0C2B; -constexpr unsigned int mmHDP_XDP_P2P_MBX_ADDR6 = 0x0C2C; -constexpr unsigned int mmHDP_XDP_P2P_MBX_OFFSET = 0x0C25; -constexpr unsigned int mmHDP_XDP_SID_CFG = 0x0C30; -constexpr unsigned int mmHDP_XDP_SRBM_CFG = 0x0C32; -constexpr unsigned int mmHDP_XDP_STICKY = 0x0C3F; -constexpr unsigned int mmHOST_BUSNUM = 0x153D; -constexpr unsigned int mmHW_DEBUG = 0x1515; -constexpr unsigned int mmIA_CNTL_STATUS = 0x2237; -constexpr unsigned int mmIA_DEBUG_CNTL = 0x223A; -constexpr unsigned int mmIA_DEBUG_DATA = 0x223B; -constexpr unsigned int mmIA_ENHANCE = 0xA29C; -constexpr unsigned int mmIA_MULTI_VGT_PARAM = 0xA2AA; -constexpr unsigned int mmIA_PERFCOUNTER0_HI__CI__VI = 0xD089; -constexpr unsigned int mmIA_PERFCOUNTER0_HI__SI = 0x2225; -constexpr unsigned int mmIA_PERFCOUNTER0_LO__CI__VI = 0xD088; -constexpr unsigned int mmIA_PERFCOUNTER0_LO__SI = 0x2224; -constexpr unsigned int mmIA_PERFCOUNTER0_SELECT1__CI__VI = 0xD888; -constexpr unsigned int mmIA_PERFCOUNTER0_SELECT__CI__VI = 0xD884; -constexpr unsigned int mmIA_PERFCOUNTER0_SELECT__SI = 0x2220; -constexpr unsigned int mmIA_PERFCOUNTER1_HI__CI__VI = 0xD08B; -constexpr unsigned int mmIA_PERFCOUNTER1_HI__SI = 0x2227; -constexpr unsigned int mmIA_PERFCOUNTER1_LO__CI__VI = 0xD08A; -constexpr unsigned int mmIA_PERFCOUNTER1_LO__SI = 0x2226; -constexpr unsigned int mmIA_PERFCOUNTER1_SELECT__CI__VI = 0xD885; -constexpr unsigned int mmIA_PERFCOUNTER1_SELECT__SI = 0x2221; -constexpr unsigned int mmIA_PERFCOUNTER2_HI__CI__VI = 0xD08D; -constexpr unsigned int mmIA_PERFCOUNTER2_HI__SI = 0x2229; -constexpr unsigned int mmIA_PERFCOUNTER2_LO__CI__VI = 0xD08C; -constexpr unsigned int mmIA_PERFCOUNTER2_LO__SI = 0x2228; -constexpr unsigned int mmIA_PERFCOUNTER2_SELECT__CI__VI = 0xD886; -constexpr unsigned int mmIA_PERFCOUNTER2_SELECT__SI = 0x2222; -constexpr unsigned int mmIA_PERFCOUNTER3_HI__CI__VI = 0xD08F; -constexpr unsigned int mmIA_PERFCOUNTER3_HI__SI = 0x222B; -constexpr unsigned int mmIA_PERFCOUNTER3_LO__CI__VI = 0xD08E; -constexpr unsigned int mmIA_PERFCOUNTER3_LO__SI = 0x222A; -constexpr unsigned int mmIA_PERFCOUNTER3_SELECT__CI__VI = 0xD887; -constexpr unsigned int mmIA_PERFCOUNTER3_SELECT__SI = 0x2223; -constexpr unsigned int mmIA_VMID_OVERRIDE__SI__CI = 0x2260; -constexpr unsigned int mmIH_ADVFAULT_CNTL__SI__CI = 0x0F8C; -constexpr unsigned int mmIH_PERFCOUNTER0_RESULT__CI = 0x0F8A; -constexpr unsigned int mmIH_PERFCOUNTER1_RESULT__CI = 0x0F8B; -constexpr unsigned int mmIH_PERFMON_CNTL__CI = 0x0F89; -constexpr unsigned int mmIH_VMID_0_LUT__CI = 0x0F50; -constexpr unsigned int mmIH_VMID_10_LUT__CI = 0x0F5A; -constexpr unsigned int mmIH_VMID_11_LUT__CI = 0x0F5B; -constexpr unsigned int mmIH_VMID_12_LUT__CI = 0x0F5C; -constexpr unsigned int mmIH_VMID_13_LUT__CI = 0x0F5D; -constexpr unsigned int mmIH_VMID_14_LUT__CI = 0x0F5E; -constexpr unsigned int mmIH_VMID_15_LUT__CI = 0x0F5F; -constexpr unsigned int mmIH_VMID_1_LUT__CI = 0x0F51; -constexpr unsigned int mmIH_VMID_2_LUT__CI = 0x0F52; -constexpr unsigned int mmIH_VMID_3_LUT__CI = 0x0F53; -constexpr unsigned int mmIH_VMID_4_LUT__CI = 0x0F54; -constexpr unsigned int mmIH_VMID_5_LUT__CI = 0x0F55; -constexpr unsigned int mmIH_VMID_6_LUT__CI = 0x0F56; -constexpr unsigned int mmIH_VMID_7_LUT__CI = 0x0F57; -constexpr unsigned int mmIH_VMID_8_LUT__CI = 0x0F58; -constexpr unsigned int mmIH_VMID_9_LUT__CI = 0x0F59; -constexpr unsigned int mmIMPCTL_RESET__CI__VI = 0x14F5; -constexpr unsigned int mmINTERRUPT_CNTL = 0x151A; -constexpr unsigned int mmINTERRUPT_CNTL2 = 0x151B; -constexpr unsigned int mmINT_MASK__SI = 0x1AD0; -constexpr unsigned int mmLB0_DC_MVP_LB_CONTROL__SI = 0x1ADB; -constexpr unsigned int mmLB0_LB_DEBUG__SI = 0x1AFC; -constexpr unsigned int mmLB0_LB_SYNC_RESET_SEL__SI = 0x1ACA; -constexpr unsigned int mmLB0_LB_TEST_DEBUG_DATA__SI__VI = 0x1AFF; -constexpr unsigned int mmLB0_LB_TEST_DEBUG_INDEX__SI__VI = 0x1AFE; -constexpr unsigned int mmLB0_MVP_AFR_FLIP_FIFO_CNTL__SI = 0x1AD9; -constexpr unsigned int mmLB0_MVP_AFR_FLIP_MODE__SI = 0x1AD8; -constexpr unsigned int mmLB0_MVP_FLIP_LINE_NUM_INSERT__SI = 0x1ADA; -constexpr unsigned int mmLB1_DC_MVP_LB_CONTROL__SI = 0x1DDB; -constexpr unsigned int mmLB1_LB_DEBUG__SI = 0x1DFC; -constexpr unsigned int mmLB1_LB_SYNC_RESET_SEL__SI = 0x1DCA; -constexpr unsigned int mmLB1_LB_TEST_DEBUG_DATA__SI = 0x1DFF; -constexpr unsigned int mmLB1_LB_TEST_DEBUG_INDEX__SI = 0x1DFE; -constexpr unsigned int mmLB1_MVP_AFR_FLIP_FIFO_CNTL__SI = 0x1DD9; -constexpr unsigned int mmLB1_MVP_AFR_FLIP_MODE__SI = 0x1DD8; -constexpr unsigned int mmLB1_MVP_FLIP_LINE_NUM_INSERT__SI = 0x1DDA; -constexpr unsigned int mmLB2_DC_MVP_LB_CONTROL__SI = 0x40DB; -constexpr unsigned int mmLB2_LB_DEBUG__SI = 0x40FC; -constexpr unsigned int mmLB2_LB_SYNC_RESET_SEL__SI = 0x40CA; -constexpr unsigned int mmLB2_LB_TEST_DEBUG_DATA__SI = 0x40FF; -constexpr unsigned int mmLB2_LB_TEST_DEBUG_INDEX__SI = 0x40FE; -constexpr unsigned int mmLB2_MVP_AFR_FLIP_FIFO_CNTL__SI = 0x40D9; -constexpr unsigned int mmLB2_MVP_AFR_FLIP_MODE__SI = 0x40D8; -constexpr unsigned int mmLB2_MVP_FLIP_LINE_NUM_INSERT__SI = 0x40DA; -constexpr unsigned int mmLB3_DC_MVP_LB_CONTROL__SI = 0x43DB; -constexpr unsigned int mmLB3_LB_DEBUG__SI = 0x43FC; -constexpr unsigned int mmLB3_LB_SYNC_RESET_SEL__SI = 0x43CA; -constexpr unsigned int mmLB3_LB_TEST_DEBUG_DATA__SI = 0x43FF; -constexpr unsigned int mmLB3_LB_TEST_DEBUG_INDEX__SI = 0x43FE; -constexpr unsigned int mmLB3_MVP_AFR_FLIP_FIFO_CNTL__SI = 0x43D9; -constexpr unsigned int mmLB3_MVP_AFR_FLIP_MODE__SI = 0x43D8; -constexpr unsigned int mmLB3_MVP_FLIP_LINE_NUM_INSERT__SI = 0x43DA; -constexpr unsigned int mmLB4_DC_MVP_LB_CONTROL__SI = 0x46DB; -constexpr unsigned int mmLB4_LB_DEBUG__SI = 0x46FC; -constexpr unsigned int mmLB4_LB_SYNC_RESET_SEL__SI = 0x46CA; -constexpr unsigned int mmLB4_LB_TEST_DEBUG_DATA__SI = 0x46FF; -constexpr unsigned int mmLB4_LB_TEST_DEBUG_INDEX__SI = 0x46FE; -constexpr unsigned int mmLB4_MVP_AFR_FLIP_FIFO_CNTL__SI = 0x46D9; -constexpr unsigned int mmLB4_MVP_AFR_FLIP_MODE__SI = 0x46D8; -constexpr unsigned int mmLB4_MVP_FLIP_LINE_NUM_INSERT__SI = 0x46DA; -constexpr unsigned int mmLB5_DC_MVP_LB_CONTROL__SI = 0x49DB; -constexpr unsigned int mmLB5_LB_DEBUG__SI = 0x49FC; -constexpr unsigned int mmLB5_LB_SYNC_RESET_SEL__SI = 0x49CA; -constexpr unsigned int mmLB5_LB_TEST_DEBUG_DATA__SI = 0x49FF; -constexpr unsigned int mmLB5_LB_TEST_DEBUG_INDEX__SI = 0x49FE; -constexpr unsigned int mmLB5_MVP_AFR_FLIP_FIFO_CNTL__SI = 0x49D9; -constexpr unsigned int mmLB5_MVP_AFR_FLIP_MODE__SI = 0x49D8; -constexpr unsigned int mmLB5_MVP_FLIP_LINE_NUM_INSERT__SI = 0x49DA; -constexpr unsigned int mmLB_DEBUG__SI = 0x1AFC; -constexpr unsigned int mmLB_SYNC_RESET_SEL__SI = 0x1ACA; -constexpr unsigned int mmLB_TEST_DEBUG_DATA__SI__VI = 0x1AFF; -constexpr unsigned int mmLB_TEST_DEBUG_INDEX__SI__VI = 0x1AFE; -constexpr unsigned int mmLNCNT_CONTROL__CI = 0x1487; -constexpr unsigned int mmLVDS_DATA_CNTL__SI = 0x1C8C; -constexpr unsigned int mmLVTMA_PWRSEQ_CNTL__SI = 0x1962; -constexpr unsigned int mmLVTMA_PWRSEQ_DELAY1__SI = 0x1965; -constexpr unsigned int mmLVTMA_PWRSEQ_DELAY2__SI = 0x1966; -constexpr unsigned int mmLVTMA_PWRSEQ_REF_DIV__SI = 0x1964; -constexpr unsigned int mmLVTMA_PWRSEQ_STATE__SI = 0x1963; -constexpr unsigned int mmMASTER_COMM_CMD_REG__SI__VI = 0x161F; -constexpr unsigned int mmMASTER_COMM_CNTL_REG__SI__VI = 0x1620; -constexpr unsigned int mmMASTER_COMM_DATA_REG1__SI__VI = 0x161C; -constexpr unsigned int mmMASTER_COMM_DATA_REG2__SI__VI = 0x161D; -constexpr unsigned int mmMASTER_COMM_DATA_REG3__SI__VI = 0x161E; -constexpr unsigned int mmMASTER_CREDIT_CNTL = 0x1516; -constexpr unsigned int mmMASTER_UPDATE_LOCK__SI__VI = 0x1BBD; -constexpr unsigned int mmMASTER_UPDATE_MODE__SI__VI = 0x1BBE; -constexpr unsigned int mmMCIF_CONTROL__SI = 0x0314; -constexpr unsigned int mmMCIF_TEST_DEBUG_DATA__SI = 0x0317; -constexpr unsigned int mmMCIF_TEST_DEBUG_INDEX__SI = 0x0316; -constexpr unsigned int mmMCIF_WRITE_COMBINE_CONTROL__SI = 0x0315; -constexpr unsigned int mmMCLK_PWRMGT_CNTL__SI__CI = 0x0AE8; -constexpr unsigned int mmMC_ARB_ADDR_HASH = 0x09DC; -constexpr unsigned int mmMC_ARB_ADDR_SWIZ0__CI__VI = 0x09CB; -constexpr unsigned int mmMC_ARB_ADDR_SWIZ1__CI__VI = 0x09CC; -constexpr unsigned int mmMC_ARB_AGE_CNTL__CI__VI = 0x09BF; -constexpr unsigned int mmMC_ARB_AGE_RD = 0x09E9; -constexpr unsigned int mmMC_ARB_AGE_WR = 0x09EA; -constexpr unsigned int mmMC_ARB_BANKMAP = 0x09D7; -constexpr unsigned int mmMC_ARB_BURST_TIME = 0x0A02; -constexpr unsigned int mmMC_ARB_BUSY_STATUS__CI__VI = 0x09FD; -constexpr unsigned int mmMC_ARB_CAC_CNTL = 0x09D4; -constexpr unsigned int mmMC_ARB_CG = 0x09FA; -constexpr unsigned int mmMC_ARB_DRAM_TIMING = 0x09DD; -constexpr unsigned int mmMC_ARB_DRAM_TIMING2 = 0x09DE; -constexpr unsigned int mmMC_ARB_DRAM_TIMING2_1 = 0x09FF; -constexpr unsigned int mmMC_ARB_DRAM_TIMING_1 = 0x09FC; -constexpr unsigned int mmMC_ARB_FED_CNTL = 0x09C1; -constexpr unsigned int mmMC_ARB_GDEC_RD_CNTL = 0x09EE; -constexpr unsigned int mmMC_ARB_GDEC_WR_CNTL = 0x09EF; -constexpr unsigned int mmMC_ARB_GECC2 = 0x09C9; -constexpr unsigned int mmMC_ARB_GECC2_CLI = 0x09CA; -constexpr unsigned int mmMC_ARB_GECC2_DEBUG = 0x09C4; -constexpr unsigned int mmMC_ARB_GECC2_DEBUG2 = 0x09C5; -constexpr unsigned int mmMC_ARB_GECC2_MISC = 0x09C3; -constexpr unsigned int mmMC_ARB_GECC2_STATUS = 0x09C2; -constexpr unsigned int mmMC_ARB_HARSH_BWCNT0_RD__CI__VI = 0x0DCE; -constexpr unsigned int mmMC_ARB_HARSH_BWCNT0_WR__CI__VI = 0x0DCF; -constexpr unsigned int mmMC_ARB_HARSH_BWCNT1_RD__CI__VI = 0x0DD0; -constexpr unsigned int mmMC_ARB_HARSH_BWCNT1_WR__CI__VI = 0x0DD1; -constexpr unsigned int mmMC_ARB_HARSH_BWPERIOD0_RD__CI__VI = 0x0DCA; -constexpr unsigned int mmMC_ARB_HARSH_BWPERIOD0_WR__CI__VI = 0x0DCB; -constexpr unsigned int mmMC_ARB_HARSH_BWPERIOD1_RD__CI__VI = 0x0DCC; -constexpr unsigned int mmMC_ARB_HARSH_BWPERIOD1_WR__CI__VI = 0x0DCD; -constexpr unsigned int mmMC_ARB_HARSH_CTL_RD__CI__VI = 0x0DD6; -constexpr unsigned int mmMC_ARB_HARSH_CTL_WR__CI__VI = 0x0DD7; -constexpr unsigned int mmMC_ARB_HARSH_EN_RD__CI__VI = 0x0DC0; -constexpr unsigned int mmMC_ARB_HARSH_EN_WR__CI__VI = 0x0DC1; -constexpr unsigned int mmMC_ARB_HARSH_SAT0_RD__CI__VI = 0x0DD2; -constexpr unsigned int mmMC_ARB_HARSH_SAT0_WR__CI__VI = 0x0DD3; -constexpr unsigned int mmMC_ARB_HARSH_SAT1_RD__CI__VI = 0x0DD4; -constexpr unsigned int mmMC_ARB_HARSH_SAT1_WR__CI__VI = 0x0DD5; -constexpr unsigned int mmMC_ARB_HARSH_TX_HI0_RD__CI__VI = 0x0DC2; -constexpr unsigned int mmMC_ARB_HARSH_TX_HI0_WR__CI__VI = 0x0DC3; -constexpr unsigned int mmMC_ARB_HARSH_TX_HI1_RD__CI__VI = 0x0DC4; -constexpr unsigned int mmMC_ARB_HARSH_TX_HI1_WR__CI__VI = 0x0DC5; -constexpr unsigned int mmMC_ARB_HARSH_TX_LO0_RD__CI__VI = 0x0DC6; -constexpr unsigned int mmMC_ARB_HARSH_TX_LO0_WR__CI__VI = 0x0DC7; -constexpr unsigned int mmMC_ARB_HARSH_TX_LO1_RD__CI__VI = 0x0DC8; -constexpr unsigned int mmMC_ARB_HARSH_TX_LO1_WR__CI__VI = 0x0DC9; -constexpr unsigned int mmMC_ARB_LAZY0_RD = 0x09E5; -constexpr unsigned int mmMC_ARB_LAZY0_WR = 0x09E6; -constexpr unsigned int mmMC_ARB_LAZY1_RD = 0x09E7; -constexpr unsigned int mmMC_ARB_LAZY1_WR = 0x09E8; -constexpr unsigned int mmMC_ARB_LM_RD = 0x09F0; -constexpr unsigned int mmMC_ARB_LM_WR = 0x09F1; -constexpr unsigned int mmMC_ARB_MAX_LAT_CID__CI__VI = 0x09F6; -constexpr unsigned int mmMC_ARB_MAX_LAT_RSLT0__CI__VI = 0x09F7; -constexpr unsigned int mmMC_ARB_MAX_LAT_RSLT1__CI__VI = 0x09F8; -constexpr unsigned int mmMC_ARB_MINCLKS = 0x09DA; -constexpr unsigned int mmMC_ARB_MISC = 0x09D6; -constexpr unsigned int mmMC_ARB_MISC2 = 0x09D5; -constexpr unsigned int mmMC_ARB_MISC3__CI__VI = 0x09CD; -constexpr unsigned int mmMC_ARB_PERFCOUNTER0_CFG__CI__VI = 0x07BC; -constexpr unsigned int mmMC_ARB_PERFCOUNTER1_CFG__CI__VI = 0x07BD; -constexpr unsigned int mmMC_ARB_PERFCOUNTER2_CFG__CI__VI = 0x07BE; -constexpr unsigned int mmMC_ARB_PERFCOUNTER3_CFG__CI__VI = 0x07BF; -constexpr unsigned int mmMC_ARB_PERFCOUNTER_HI__CI__VI = 0x07AE; -constexpr unsigned int mmMC_ARB_PERFCOUNTER_LO__CI__VI = 0x07A6; -constexpr unsigned int mmMC_ARB_PERFCOUNTER_RSLT_CNTL__CI__VI = 0x07D4; -constexpr unsigned int mmMC_ARB_PERF_MON_CNTL0_ECC__CI = 0x07DB; -constexpr unsigned int mmMC_ARB_PERF_MON_CNTL0__SI = 0x09F6; -constexpr unsigned int mmMC_ARB_PM_CNTL = 0x09ED; -constexpr unsigned int mmMC_ARB_POP = 0x09D9; -constexpr unsigned int mmMC_ARB_RAMCFG = 0x09D8; -constexpr unsigned int mmMC_ARB_REMREQ = 0x09F2; -constexpr unsigned int mmMC_ARB_REPLAY = 0x09F3; -constexpr unsigned int mmMC_ARB_RET_CREDITS2__CI__VI = 0x09C0; -constexpr unsigned int mmMC_ARB_RET_CREDITS_RD = 0x09F4; -constexpr unsigned int mmMC_ARB_RET_CREDITS_WR = 0x09F5; -constexpr unsigned int mmMC_ARB_RFSH_CNTL = 0x09EB; -constexpr unsigned int mmMC_ARB_RFSH_RATE = 0x09EC; -constexpr unsigned int mmMC_ARB_RTT_CNTL0 = 0x09D0; -constexpr unsigned int mmMC_ARB_RTT_CNTL1 = 0x09D1; -constexpr unsigned int mmMC_ARB_RTT_CNTL2 = 0x09D2; -constexpr unsigned int mmMC_ARB_RTT_DATA = 0x09CF; -constexpr unsigned int mmMC_ARB_RTT_DEBUG = 0x09D3; -constexpr unsigned int mmMC_ARB_SQM_CNTL = 0x09DB; -constexpr unsigned int mmMC_ARB_SSM__CI = 0x09F9; -constexpr unsigned int mmMC_ARB_TM_CNTL_RD = 0x09E3; -constexpr unsigned int mmMC_ARB_TM_CNTL_WR = 0x09E4; -constexpr unsigned int mmMC_ARB_WCDR__SI__CI = 0x09FB; -constexpr unsigned int mmMC_ARB_WCDR_2__SI__CI = 0x09CE; -constexpr unsigned int mmMC_ARB_WTM_CNTL_RD = 0x09DF; -constexpr unsigned int mmMC_ARB_WTM_CNTL_WR = 0x09E0; -constexpr unsigned int mmMC_ARB_WTM_GRPWT_RD = 0x09E1; -constexpr unsigned int mmMC_ARB_WTM_GRPWT_WR = 0x09E2; -constexpr unsigned int mmMC_BIST_AUTO_CNTL__SI__CI = 0x0A06; -constexpr unsigned int mmMC_BIST_CMD_CNTL__SI__CI = 0x0A8E; -constexpr unsigned int mmMC_BIST_CMP_CNTL__SI__CI = 0x0A8D; -constexpr unsigned int mmMC_BIST_CMP_CNTL_2__SI__CI = 0x0AB6; -constexpr unsigned int mmMC_BIST_DATA_MASK__SI__CI = 0x0A12; -constexpr unsigned int mmMC_BIST_DIR_CNTL__SI__CI = 0x0A07; -constexpr unsigned int mmMC_BIST_EADDR__SI__CI = 0x0A09; -constexpr unsigned int mmMC_BIST_RDATA_EDC__SI__CI = 0x0A1D; -constexpr unsigned int mmMC_BIST_RDATA_MASK__SI__CI = 0x0A1C; -constexpr unsigned int mmMC_BIST_SADDR__SI__CI = 0x0A08; -constexpr unsigned int mmMC_CG_CONFIG = 0x096F; -constexpr unsigned int mmMC_CG_CONFIG_MCD = 0x0829; -constexpr unsigned int mmMC_CITF_CNTL = 0x0970; -constexpr unsigned int mmMC_CITF_CREDITS_ARB_RD = 0x0972; -constexpr unsigned int mmMC_CITF_CREDITS_ARB_WR = 0x0973; -constexpr unsigned int mmMC_CITF_CREDITS_VM = 0x0971; -constexpr unsigned int mmMC_CITF_CREDITS_XBAR = 0x0989; -constexpr unsigned int mmMC_CITF_DAGB_CNTL = 0x0974; -constexpr unsigned int mmMC_CITF_DAGB_DLY = 0x0977; -constexpr unsigned int mmMC_CITF_INT_CREDITS = 0x0975; -constexpr unsigned int mmMC_CITF_INT_CREDITS_WR__CI__VI = 0x097D; -constexpr unsigned int mmMC_CITF_MISC_RD_CG = 0x0992; -constexpr unsigned int mmMC_CITF_MISC_VM_CG = 0x0994; -constexpr unsigned int mmMC_CITF_MISC_WR_CG = 0x0993; -constexpr unsigned int mmMC_CITF_PERFCOUNTER0_CFG__CI__VI = 0x07B0; -constexpr unsigned int mmMC_CITF_PERFCOUNTER1_CFG__CI__VI = 0x07B1; -constexpr unsigned int mmMC_CITF_PERFCOUNTER2_CFG__CI__VI = 0x07B2; -constexpr unsigned int mmMC_CITF_PERFCOUNTER3_CFG__CI__VI = 0x07B3; -constexpr unsigned int mmMC_CITF_PERFCOUNTER_HI__CI__VI = 0x07A8; -constexpr unsigned int mmMC_CITF_PERFCOUNTER_LO__CI__VI = 0x07A0; -constexpr unsigned int mmMC_CITF_PERFCOUNTER_RSLT_CNTL__CI__VI = 0x07CE; -constexpr unsigned int mmMC_CITF_PERF_MON_CNTL2 = 0x098E; -constexpr unsigned int mmMC_CITF_PERF_MON_RSLT2 = 0x0991; -constexpr unsigned int mmMC_CITF_REMREQ = 0x097A; -constexpr unsigned int mmMC_CITF_RET_MODE = 0x0976; -constexpr unsigned int mmMC_CITF_WTM_RD_CNTL = 0x097F; -constexpr unsigned int mmMC_CITF_WTM_WR_CNTL = 0x0980; -constexpr unsigned int mmMC_CITF_XTRA_ENABLE = 0x096D; -constexpr unsigned int mmMC_CONFIG = 0x0800; -constexpr unsigned int mmMC_CONFIG_MCD = 0x0828; -constexpr unsigned int mmMC_DC_INTERFACE_NACK_STATUS__SI = 0x031C; -constexpr unsigned int mmMC_DLB_CONFIG0__CI = 0x0D93; -constexpr unsigned int mmMC_DLB_CONFIG1__CI = 0x0D94; -constexpr unsigned int mmMC_DLB_MISCCTRL0__CI = 0x0D90; -constexpr unsigned int mmMC_DLB_MISCCTRL1__CI = 0x0D91; -constexpr unsigned int mmMC_DLB_MISCCTRL2__CI = 0x0D92; -constexpr unsigned int mmMC_DLB_SETUPFIFO__CI = 0x0D97; -constexpr unsigned int mmMC_DLB_SETUPSWEEP__CI = 0x0D96; -constexpr unsigned int mmMC_DLB_SETUP__CI = 0x0D95; -constexpr unsigned int mmMC_DLB_STATUS_MISC0__CI = 0x0D9A; -constexpr unsigned int mmMC_DLB_STATUS_MISC1__CI = 0x0D9B; -constexpr unsigned int mmMC_DLB_STATUS_MISC2__CI = 0x0D9C; -constexpr unsigned int mmMC_DLB_STATUS_MISC3__CI = 0x0D9D; -constexpr unsigned int mmMC_DLB_STATUS_MISC4__CI = 0x0D9E; -constexpr unsigned int mmMC_DLB_STATUS_MISC5__CI = 0x0D9F; -constexpr unsigned int mmMC_DLB_STATUS_MISC6__CI = 0x0DA0; -constexpr unsigned int mmMC_DLB_STATUS_MISC7__CI = 0x0DA1; -constexpr unsigned int mmMC_DLB_STATUS__CI = 0x0D99; -constexpr unsigned int mmMC_DLB_WRITE_MASK__CI = 0x0D98; -constexpr unsigned int mmMC_HUB_MISC_DBG__SI__CI = 0x0831; -constexpr unsigned int mmMC_HUB_MISC_FRAMING = 0x0834; -constexpr unsigned int mmMC_HUB_MISC_HUB_CG = 0x082E; -constexpr unsigned int mmMC_HUB_MISC_IDLE_STATUS = 0x0847; -constexpr unsigned int mmMC_HUB_MISC_OVERRIDE = 0x0833; -constexpr unsigned int mmMC_HUB_MISC_POWER = 0x082D; -constexpr unsigned int mmMC_HUB_MISC_SIP_CG = 0x0830; -constexpr unsigned int mmMC_HUB_MISC_STATUS = 0x0832; -constexpr unsigned int mmMC_HUB_MISC_VM_CG = 0x082F; -constexpr unsigned int mmMC_HUB_PERFCOUNTER0_CFG__CI__VI = 0x07B4; -constexpr unsigned int mmMC_HUB_PERFCOUNTER1_CFG__CI__VI = 0x07B5; -constexpr unsigned int mmMC_HUB_PERFCOUNTER2_CFG__CI__VI = 0x07B6; -constexpr unsigned int mmMC_HUB_PERFCOUNTER3_CFG__CI__VI = 0x07B7; -constexpr unsigned int mmMC_HUB_PERFCOUNTER_HI__CI__VI = 0x07A9; -constexpr unsigned int mmMC_HUB_PERFCOUNTER_LO__CI__VI = 0x07A1; -constexpr unsigned int mmMC_HUB_PERFCOUNTER_RSLT_CNTL__CI__VI = 0x07CF; -constexpr unsigned int mmMC_HUB_RDREQ_ACPG_LIMIT__CI__VI = 0x0849; -constexpr unsigned int mmMC_HUB_RDREQ_ACPG__CI = 0x0887; -constexpr unsigned int mmMC_HUB_RDREQ_ACPO__CI = 0x0888; -constexpr unsigned int mmMC_HUB_RDREQ_CNTL = 0x083B; -constexpr unsigned int mmMC_HUB_RDREQ_CPC__CI = 0x085A; -constexpr unsigned int mmMC_HUB_RDREQ_CPF__CI = 0x085B; -constexpr unsigned int mmMC_HUB_RDREQ_CPG__CI = 0x0859; -constexpr unsigned int mmMC_HUB_RDREQ_CP__SI = 0x0859; -constexpr unsigned int mmMC_HUB_RDREQ_CREDITS = 0x0844; -constexpr unsigned int mmMC_HUB_RDREQ_CREDITS2 = 0x0845; -constexpr unsigned int mmMC_HUB_RDREQ_DMIF_LIMIT = 0x0848; -constexpr unsigned int mmMC_HUB_RDREQ_DMIF__CI = 0x0865; -constexpr unsigned int mmMC_HUB_RDREQ_DMIF__SI = 0x0863; -constexpr unsigned int mmMC_HUB_RDREQ_GBL0 = 0x0856; -constexpr unsigned int mmMC_HUB_RDREQ_GBL1 = 0x0857; -constexpr unsigned int mmMC_HUB_RDREQ_HDP__CI = 0x085E; -constexpr unsigned int mmMC_HUB_RDREQ_HDP__SI = 0x085B; -constexpr unsigned int mmMC_HUB_RDREQ_IA0__CI = 0x084F; -constexpr unsigned int mmMC_HUB_RDREQ_IA1__CI = 0x0850; -constexpr unsigned int mmMC_HUB_RDREQ_IA__CI = 0x0864; -constexpr unsigned int mmMC_HUB_RDREQ_MCDW = 0x0851; -constexpr unsigned int mmMC_HUB_RDREQ_MCDX = 0x0852; -constexpr unsigned int mmMC_HUB_RDREQ_MCDY = 0x0853; -constexpr unsigned int mmMC_HUB_RDREQ_MCDZ = 0x0854; -constexpr unsigned int mmMC_HUB_RDREQ_MCIF__CI = 0x0866; -constexpr unsigned int mmMC_HUB_RDREQ_MCIF__SI = 0x0864; -constexpr unsigned int mmMC_HUB_RDREQ_RLC__CI = 0x085F; -constexpr unsigned int mmMC_HUB_RDREQ_RLC__SI = 0x085D; -constexpr unsigned int mmMC_HUB_RDREQ_SAM__CI = 0x0889; -constexpr unsigned int mmMC_HUB_RDREQ_SDMA0__CI = 0x085C; -constexpr unsigned int mmMC_HUB_RDREQ_SDMA1__CI = 0x085D; -constexpr unsigned int mmMC_HUB_RDREQ_SEM__CI = 0x0860; -constexpr unsigned int mmMC_HUB_RDREQ_SEM__SI = 0x085E; -constexpr unsigned int mmMC_HUB_RDREQ_SIP = 0x0855; -constexpr unsigned int mmMC_HUB_RDREQ_SMU = 0x0858; -constexpr unsigned int mmMC_HUB_RDREQ_STATUS = 0x0839; -constexpr unsigned int mmMC_HUB_RDREQ_UMC__CI = 0x0862; -constexpr unsigned int mmMC_HUB_RDREQ_UMC__SI = 0x0860; -constexpr unsigned int mmMC_HUB_RDREQ_UVD__CI = 0x0863; -constexpr unsigned int mmMC_HUB_RDREQ_UVD__SI = 0x0861; -constexpr unsigned int mmMC_HUB_RDREQ_VCEU__CI = 0x0868; -constexpr unsigned int mmMC_HUB_RDREQ_VCEU__SI = 0x0866; -constexpr unsigned int mmMC_HUB_RDREQ_VCE__CI = 0x0861; -constexpr unsigned int mmMC_HUB_RDREQ_VCE__SI = 0x085F; -constexpr unsigned int mmMC_HUB_RDREQ_VMC__CI = 0x0867; -constexpr unsigned int mmMC_HUB_RDREQ_VMC__SI = 0x0865; -constexpr unsigned int mmMC_HUB_RDREQ_WTM_CNTL = 0x083D; -constexpr unsigned int mmMC_HUB_RDREQ_XDMAM__CI = 0x0886; -constexpr unsigned int mmMC_HUB_RDREQ_XDMAM__SI = 0x0882; -constexpr unsigned int mmMC_HUB_SHARED_DAGB_DLY = 0x0846; -constexpr unsigned int mmMC_HUB_WDP_ACPG__CI = 0x088A; -constexpr unsigned int mmMC_HUB_WDP_ACPO__CI = 0x088B; -constexpr unsigned int mmMC_HUB_WDP_BP = 0x0837; -constexpr unsigned int mmMC_HUB_WDP_CNTL = 0x0835; -constexpr unsigned int mmMC_HUB_WDP_CPC__CI = 0x086F; -constexpr unsigned int mmMC_HUB_WDP_CPF__CI = 0x0870; -constexpr unsigned int mmMC_HUB_WDP_CPG__CI = 0x086E; -constexpr unsigned int mmMC_HUB_WDP_CP__SI = 0x086C; -constexpr unsigned int mmMC_HUB_WDP_CREDITS = 0x083F; -constexpr unsigned int mmMC_HUB_WDP_ERR = 0x0836; -constexpr unsigned int mmMC_HUB_WDP_GBL0 = 0x0841; -constexpr unsigned int mmMC_HUB_WDP_GBL1 = 0x0842; -constexpr unsigned int mmMC_HUB_WDP_HDP__CI = 0x087C; -constexpr unsigned int mmMC_HUB_WDP_HDP__SI = 0x0879; -constexpr unsigned int mmMC_HUB_WDP_IH__CI = 0x0875; -constexpr unsigned int mmMC_HUB_WDP_IH__SI = 0x0872; -constexpr unsigned int mmMC_HUB_WDP_MCDW__CI = 0x0869; -constexpr unsigned int mmMC_HUB_WDP_MCDW__SI = 0x0867; -constexpr unsigned int mmMC_HUB_WDP_MCDX__CI = 0x086A; -constexpr unsigned int mmMC_HUB_WDP_MCDX__SI = 0x0868; -constexpr unsigned int mmMC_HUB_WDP_MCDY__CI = 0x086B; -constexpr unsigned int mmMC_HUB_WDP_MCDY__SI = 0x0869; -constexpr unsigned int mmMC_HUB_WDP_MCDZ__CI = 0x086C; -constexpr unsigned int mmMC_HUB_WDP_MCDZ__SI = 0x086A; -constexpr unsigned int mmMC_HUB_WDP_MCIF__CI = 0x0872; -constexpr unsigned int mmMC_HUB_WDP_MCIF__SI = 0x086F; -constexpr unsigned int mmMC_HUB_WDP_MGPU__SI__CI = 0x0843; -constexpr unsigned int mmMC_HUB_WDP_MGPU2__SI__CI = 0x0840; -constexpr unsigned int mmMC_HUB_WDP_RLC__CI = 0x0876; -constexpr unsigned int mmMC_HUB_WDP_RLC__SI = 0x0873; -constexpr unsigned int mmMC_HUB_WDP_SAM__CI = 0x088C; -constexpr unsigned int mmMC_HUB_WDP_SDMA0__CI = 0x087D; -constexpr unsigned int mmMC_HUB_WDP_SDMA1__CI = 0x087E; -constexpr unsigned int mmMC_HUB_WDP_SEM__CI = 0x0877; -constexpr unsigned int mmMC_HUB_WDP_SEM__SI = 0x0874; -constexpr unsigned int mmMC_HUB_WDP_SH0__CI = 0x0871; -constexpr unsigned int mmMC_HUB_WDP_SH0__SI = 0x086E; -constexpr unsigned int mmMC_HUB_WDP_SH1__CI = 0x0879; -constexpr unsigned int mmMC_HUB_WDP_SH1__SI = 0x0876; -constexpr unsigned int mmMC_HUB_WDP_SH2__CI__VI = 0x084D; -constexpr unsigned int mmMC_HUB_WDP_SH3__CI__VI = 0x084E; -constexpr unsigned int mmMC_HUB_WDP_SIP__CI = 0x086D; -constexpr unsigned int mmMC_HUB_WDP_SIP__SI = 0x086B; -constexpr unsigned int mmMC_HUB_WDP_SMU__CI = 0x0878; -constexpr unsigned int mmMC_HUB_WDP_SMU__SI = 0x0875; -constexpr unsigned int mmMC_HUB_WDP_STATUS = 0x0838; -constexpr unsigned int mmMC_HUB_WDP_UMC__CI = 0x087A; -constexpr unsigned int mmMC_HUB_WDP_UMC__SI = 0x0877; -constexpr unsigned int mmMC_HUB_WDP_UVD__CI = 0x087B; -constexpr unsigned int mmMC_HUB_WDP_UVD__SI = 0x0878; -constexpr unsigned int mmMC_HUB_WDP_VCEU__CI = 0x0883; -constexpr unsigned int mmMC_HUB_WDP_VCEU__SI = 0x087F; -constexpr unsigned int mmMC_HUB_WDP_VCE__CI = 0x0873; -constexpr unsigned int mmMC_HUB_WDP_VCE__SI = 0x0870; -constexpr unsigned int mmMC_HUB_WDP_WTM_CNTL = 0x083E; -constexpr unsigned int mmMC_HUB_WDP_XDMAM__CI = 0x0884; -constexpr unsigned int mmMC_HUB_WDP_XDMAM__SI = 0x0880; -constexpr unsigned int mmMC_HUB_WDP_XDMA__CI = 0x0885; -constexpr unsigned int mmMC_HUB_WDP_XDMA__SI = 0x0881; -constexpr unsigned int mmMC_HUB_WDP_XDP__CI = 0x0874; -constexpr unsigned int mmMC_HUB_WDP_XDP__SI = 0x0871; -constexpr unsigned int mmMC_HUB_WRRET_CNTL = 0x083C; -constexpr unsigned int mmMC_HUB_WRRET_MCDW__CI = 0x087F; -constexpr unsigned int mmMC_HUB_WRRET_MCDW__SI = 0x087B; -constexpr unsigned int mmMC_HUB_WRRET_MCDX__CI = 0x0880; -constexpr unsigned int mmMC_HUB_WRRET_MCDX__SI = 0x087C; -constexpr unsigned int mmMC_HUB_WRRET_MCDY__CI = 0x0881; -constexpr unsigned int mmMC_HUB_WRRET_MCDY__SI = 0x087D; -constexpr unsigned int mmMC_HUB_WRRET_MCDZ__CI = 0x0882; -constexpr unsigned int mmMC_HUB_WRRET_MCDZ__SI = 0x087E; -constexpr unsigned int mmMC_HUB_WRRET_STATUS = 0x083A; -constexpr unsigned int mmMC_IMP_CNTL__SI__CI = 0x0A36; -constexpr unsigned int mmMC_IMP_DEBUG__SI__CI = 0x0A37; -constexpr unsigned int mmMC_IMP_DQ_STATUS__SI__CI = 0x0ABC; -constexpr unsigned int mmMC_IMP_STATUS__SI__CI = 0x0A38; -constexpr unsigned int mmMC_IO_APHY_STR_CNTL_D0__SI__CI = 0x0A97; -constexpr unsigned int mmMC_IO_APHY_STR_CNTL_D1__SI__CI = 0x0A98; -constexpr unsigned int mmMC_IO_CDRCNTL1_D0__SI__CI = 0x0ADD; -constexpr unsigned int mmMC_IO_CDRCNTL1_D1__SI__CI = 0x0ADE; -constexpr unsigned int mmMC_IO_CDRCNTL2_D0__SI__CI = 0x0AE4; -constexpr unsigned int mmMC_IO_CDRCNTL2_D1__SI__CI = 0x0AE5; -constexpr unsigned int mmMC_IO_CDRCNTL_D0__SI__CI = 0x0A55; -constexpr unsigned int mmMC_IO_CDRCNTL_D1__SI__CI = 0x0A56; -constexpr unsigned int mmMC_IO_DPHY_STR_CNTL_D0__SI__CI = 0x0A4E; -constexpr unsigned int mmMC_IO_DPHY_STR_CNTL_D1__SI__CI = 0x0A54; -constexpr unsigned int mmMC_IO_PAD_CNTL__SI__CI = 0x0A73; -constexpr unsigned int mmMC_IO_PAD_CNTL_D0__SI__CI = 0x0A74; -constexpr unsigned int mmMC_IO_PAD_CNTL_D1__SI__CI = 0x0A75; -constexpr unsigned int mmMC_IO_RXCNTL1_DPHY0_D0__SI__CI = 0x0ADF; -constexpr unsigned int mmMC_IO_RXCNTL1_DPHY0_D1__SI__CI = 0x0AE1; -constexpr unsigned int mmMC_IO_RXCNTL1_DPHY1_D0__SI__CI = 0x0AE0; -constexpr unsigned int mmMC_IO_RXCNTL1_DPHY1_D1__SI__CI = 0x0AE2; -constexpr unsigned int mmMC_IO_RXCNTL_DPHY0_D0__SI__CI = 0x0A4C; -constexpr unsigned int mmMC_IO_RXCNTL_DPHY0_D1__SI__CI = 0x0A52; -constexpr unsigned int mmMC_IO_RXCNTL_DPHY1_D0__SI__CI = 0x0A4D; -constexpr unsigned int mmMC_IO_RXCNTL_DPHY1_D1__SI__CI = 0x0A53; -constexpr unsigned int mmMC_IO_TXCNTL_APHY_D0__SI__CI = 0x0A4B; -constexpr unsigned int mmMC_IO_TXCNTL_APHY_D1__SI__CI = 0x0A51; -constexpr unsigned int mmMC_IO_TXCNTL_DPHY0_D0__SI__CI = 0x0A49; -constexpr unsigned int mmMC_IO_TXCNTL_DPHY0_D1__SI__CI = 0x0A4F; -constexpr unsigned int mmMC_IO_TXCNTL_DPHY1_D0__SI__CI = 0x0A4A; -constexpr unsigned int mmMC_IO_TXCNTL_DPHY1_D1__SI__CI = 0x0A50; -constexpr unsigned int mmMC_MCBVM_PERFCOUNTER0_CFG__CI__VI = 0x07C0; -constexpr unsigned int mmMC_MCBVM_PERFCOUNTER1_CFG__CI__VI = 0x07C1; -constexpr unsigned int mmMC_MCBVM_PERFCOUNTER2_CFG__CI__VI = 0x07C2; -constexpr unsigned int mmMC_MCBVM_PERFCOUNTER3_CFG__CI__VI = 0x07C3; -constexpr unsigned int mmMC_MCBVM_PERFCOUNTER_HI__CI__VI = 0x07AA; -constexpr unsigned int mmMC_MCBVM_PERFCOUNTER_LO__CI__VI = 0x07A3; -constexpr unsigned int mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL__CI__VI = 0x07D1; -constexpr unsigned int mmMC_MCDVM_PERFCOUNTER0_CFG__CI__VI = 0x07C4; -constexpr unsigned int mmMC_MCDVM_PERFCOUNTER1_CFG__CI__VI = 0x07C5; -constexpr unsigned int mmMC_MCDVM_PERFCOUNTER2_CFG__CI__VI = 0x07C6; -constexpr unsigned int mmMC_MCDVM_PERFCOUNTER3_CFG__CI__VI = 0x07C7; -constexpr unsigned int mmMC_MCDVM_PERFCOUNTER_HI__CI__VI = 0x07AB; -constexpr unsigned int mmMC_MCDVM_PERFCOUNTER_LO__CI__VI = 0x07A4; -constexpr unsigned int mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL__CI__VI = 0x07D2; -constexpr unsigned int mmMC_MEM_POWER_LS = 0x082A; -constexpr unsigned int mmMC_NPL_STATUS__SI__CI = 0x0A76; -constexpr unsigned int mmMC_PHY_TIMING_2__SI__CI = 0x0ACE; -constexpr unsigned int mmMC_PHY_TIMING_D0__SI__CI = 0x0ACC; -constexpr unsigned int mmMC_PHY_TIMING_D1__SI__CI = 0x0ACD; -constexpr unsigned int mmMC_PMG_AUTO_CFG__SI__CI = 0x0A35; -constexpr unsigned int mmMC_PMG_AUTO_CMD__SI__CI = 0x0A34; -constexpr unsigned int mmMC_RD_CB = 0x0981; -constexpr unsigned int mmMC_RD_DB = 0x0982; -constexpr unsigned int mmMC_RD_GRP_EXT = 0x0978; -constexpr unsigned int mmMC_RD_GRP_GFX = 0x0803; -constexpr unsigned int mmMC_RD_GRP_LCL = 0x098A; -constexpr unsigned int mmMC_RD_GRP_OTH = 0x0807; -constexpr unsigned int mmMC_RD_GRP_SYS = 0x0805; -constexpr unsigned int mmMC_RD_HUB = 0x0985; -constexpr unsigned int mmMC_RD_TC0 = 0x0983; -constexpr unsigned int mmMC_RD_TC1 = 0x0984; -constexpr unsigned int mmMC_RPB_ARB_CNTL = 0x0951; -constexpr unsigned int mmMC_RPB_BIF_CNTL = 0x0952; -constexpr unsigned int mmMC_RPB_CID_QUEUE_EX = 0x095A; -constexpr unsigned int mmMC_RPB_CID_QUEUE_EX_DATA = 0x095B; -constexpr unsigned int mmMC_RPB_CID_QUEUE_RD = 0x0957; -constexpr unsigned int mmMC_RPB_CID_QUEUE_WR = 0x0956; -constexpr unsigned int mmMC_RPB_CONF = 0x094D; -constexpr unsigned int mmMC_RPB_DBG1 = 0x094F; -constexpr unsigned int mmMC_RPB_EFF_CNTL = 0x0950; -constexpr unsigned int mmMC_RPB_IF_CONF = 0x094E; -constexpr unsigned int mmMC_RPB_PERFCOUNTER0_CFG__CI__VI = 0x07B8; -constexpr unsigned int mmMC_RPB_PERFCOUNTER1_CFG__CI__VI = 0x07B9; -constexpr unsigned int mmMC_RPB_PERFCOUNTER2_CFG__CI__VI = 0x07BA; -constexpr unsigned int mmMC_RPB_PERFCOUNTER3_CFG__CI__VI = 0x07BB; -constexpr unsigned int mmMC_RPB_PERFCOUNTER_HI__CI__VI = 0x07AC; -constexpr unsigned int mmMC_RPB_PERFCOUNTER_LO__CI__VI = 0x07A2; -constexpr unsigned int mmMC_RPB_PERFCOUNTER_RSLT_CNTL__CI__VI = 0x07D0; -constexpr unsigned int mmMC_RPB_PERF_COUNTER_CNTL = 0x0958; -constexpr unsigned int mmMC_RPB_PERF_COUNTER_STATUS = 0x0959; -constexpr unsigned int mmMC_RPB_RD_SWITCH_CNTL = 0x0955; -constexpr unsigned int mmMC_RPB_WR_COMBINE_CNTL = 0x0954; -constexpr unsigned int mmMC_RPB_WR_SWITCH_CNTL = 0x0953; -constexpr unsigned int mmMC_SEQ_BIT_REMAP_B0_D0__SI__CI = 0x0AA3; -constexpr unsigned int mmMC_SEQ_BIT_REMAP_B0_D1__SI__CI = 0x0AA7; -constexpr unsigned int mmMC_SEQ_BIT_REMAP_B1_D0__SI__CI = 0x0AA4; -constexpr unsigned int mmMC_SEQ_BIT_REMAP_B1_D1__SI__CI = 0x0AA8; -constexpr unsigned int mmMC_SEQ_BIT_REMAP_B2_D0__SI__CI = 0x0AA5; -constexpr unsigned int mmMC_SEQ_BIT_REMAP_B2_D1__SI__CI = 0x0AA9; -constexpr unsigned int mmMC_SEQ_BIT_REMAP_B3_D0__SI__CI = 0x0AA6; -constexpr unsigned int mmMC_SEQ_BIT_REMAP_B3_D1__SI__CI = 0x0AAA; -constexpr unsigned int mmMC_SEQ_BYTE_REMAP_D0__SI__CI = 0x0A93; -constexpr unsigned int mmMC_SEQ_BYTE_REMAP_D1__SI__CI = 0x0A94; -constexpr unsigned int mmMC_SEQ_CNTL_3__CI = 0x0D80; -constexpr unsigned int mmMC_SEQ_DLL_STBY_LP__CI = 0x0D8F; -constexpr unsigned int mmMC_SEQ_DLL_STBY__CI = 0x0D8E; -constexpr unsigned int mmMC_SEQ_DRAM_ERROR_INSERTION__SI__CI = 0x0ACB; -constexpr unsigned int mmMC_SEQ_G5PDX_CMD0_LP__CI = 0x0D84; -constexpr unsigned int mmMC_SEQ_G5PDX_CMD0__CI = 0x0D83; -constexpr unsigned int mmMC_SEQ_G5PDX_CMD1_LP__CI = 0x0D86; -constexpr unsigned int mmMC_SEQ_G5PDX_CMD1__CI = 0x0D85; -constexpr unsigned int mmMC_SEQ_G5PDX_CTRL_LP__CI = 0x0D82; -constexpr unsigned int mmMC_SEQ_G5PDX_CTRL__CI = 0x0D81; -constexpr unsigned int mmMC_SEQ_IO_RDBI__SI__CI = 0x0AB4; -constexpr unsigned int mmMC_SEQ_IO_REDC__SI__CI = 0x0AB5; -constexpr unsigned int mmMC_SEQ_IO_RESERVE_D0__SI__CI = 0x0AB7; -constexpr unsigned int mmMC_SEQ_IO_RESERVE_D1__SI__CI = 0x0AB8; -constexpr unsigned int mmMC_SEQ_IO_RWORD0__SI__CI = 0x0AAC; -constexpr unsigned int mmMC_SEQ_IO_RWORD1__SI__CI = 0x0AAD; -constexpr unsigned int mmMC_SEQ_IO_RWORD2__SI__CI = 0x0AAE; -constexpr unsigned int mmMC_SEQ_IO_RWORD3__SI__CI = 0x0AAF; -constexpr unsigned int mmMC_SEQ_IO_RWORD4__SI__CI = 0x0AB0; -constexpr unsigned int mmMC_SEQ_IO_RWORD5__SI__CI = 0x0AB1; -constexpr unsigned int mmMC_SEQ_IO_RWORD6__SI__CI = 0x0AB2; -constexpr unsigned int mmMC_SEQ_IO_RWORD7__SI__CI = 0x0AB3; -constexpr unsigned int mmMC_SEQ_MPLL_OVERRIDE__SI__CI = 0x0A22; -constexpr unsigned int mmMC_SEQ_PERF_CNTL__SI__CI = 0x0A77; -constexpr unsigned int mmMC_SEQ_PERF_CNTL_1__SI__CI = 0x0AFD; -constexpr unsigned int mmMC_SEQ_PERF_SEQ_CNT_A_I0__SI__CI = 0x0A79; -constexpr unsigned int mmMC_SEQ_PERF_SEQ_CNT_A_I1__SI__CI = 0x0A7A; -constexpr unsigned int mmMC_SEQ_PERF_SEQ_CNT_B_I0__SI__CI = 0x0A7B; -constexpr unsigned int mmMC_SEQ_PERF_SEQ_CNT_B_I1__SI__CI = 0x0A7C; -constexpr unsigned int mmMC_SEQ_PERF_SEQ_CNT_C_I0__SI__CI = 0x0AD9; -constexpr unsigned int mmMC_SEQ_PERF_SEQ_CNT_C_I1__SI__CI = 0x0ADA; -constexpr unsigned int mmMC_SEQ_PERF_SEQ_CNT_D_I0__SI__CI = 0x0ADB; -constexpr unsigned int mmMC_SEQ_PERF_SEQ_CNT_D_I1__SI__CI = 0x0ADC; -constexpr unsigned int mmMC_SEQ_PERF_SEQ_CTL__SI__CI = 0x0A78; -constexpr unsigned int mmMC_SEQ_PHYREG_BCAST__CI = 0x0D89; -constexpr unsigned int mmMC_SEQ_PMG_CMD_EMRS_LP__SI__CI = 0x0AA1; -constexpr unsigned int mmMC_SEQ_PMG_CMD_MRS1_LP__SI__CI = 0x0AD2; -constexpr unsigned int mmMC_SEQ_PMG_CMD_MRS2_LP__SI__CI = 0x0AD8; -constexpr unsigned int mmMC_SEQ_PMG_CMD_MRS_LP__SI__CI = 0x0AA2; -constexpr unsigned int mmMC_SEQ_PMG_DVS_CMD_LP__CI = 0x0D8D; -constexpr unsigned int mmMC_SEQ_PMG_DVS_CMD__CI = 0x0D8C; -constexpr unsigned int mmMC_SEQ_PMG_DVS_CTL_LP__CI = 0x0D8B; -constexpr unsigned int mmMC_SEQ_PMG_DVS_CTL__CI = 0x0D8A; -constexpr unsigned int mmMC_SEQ_PMG_PG_HWCNTL__SI__CI = 0x0AB9; -constexpr unsigned int mmMC_SEQ_PMG_PG_SWCNTL_0__SI__CI = 0x0ABA; -constexpr unsigned int mmMC_SEQ_PMG_PG_SWCNTL_1__SI__CI = 0x0ABB; -constexpr unsigned int mmMC_SEQ_RXFRAMING_BYTE0_D0__SI__CI = 0x0A67; -constexpr unsigned int mmMC_SEQ_RXFRAMING_BYTE0_D1__SI__CI = 0x0A6D; -constexpr unsigned int mmMC_SEQ_RXFRAMING_BYTE1_D0__SI__CI = 0x0A68; -constexpr unsigned int mmMC_SEQ_RXFRAMING_BYTE1_D1__SI__CI = 0x0A6E; -constexpr unsigned int mmMC_SEQ_RXFRAMING_BYTE2_D0__SI__CI = 0x0A69; -constexpr unsigned int mmMC_SEQ_RXFRAMING_BYTE2_D1__SI__CI = 0x0A6F; -constexpr unsigned int mmMC_SEQ_RXFRAMING_BYTE3_D0__SI__CI = 0x0A6A; -constexpr unsigned int mmMC_SEQ_RXFRAMING_BYTE3_D1__SI__CI = 0x0A70; -constexpr unsigned int mmMC_SEQ_RXFRAMING_DBI_D0__SI__CI = 0x0A6B; -constexpr unsigned int mmMC_SEQ_RXFRAMING_DBI_D1__SI__CI = 0x0A71; -constexpr unsigned int mmMC_SEQ_RXFRAMING_EDC_D0__SI__CI = 0x0A6C; -constexpr unsigned int mmMC_SEQ_RXFRAMING_EDC_D1__SI__CI = 0x0A72; -constexpr unsigned int mmMC_SEQ_SREG_READ__CI = 0x0D87; -constexpr unsigned int mmMC_SEQ_SREG_STATUS__CI = 0x0D88; -constexpr unsigned int mmMC_SEQ_TCG_CNTL__SI__CI = 0x0ABD; -constexpr unsigned int mmMC_SEQ_TRAIN_EDC_THRESHOLD__SI__CI = 0x0A3B; -constexpr unsigned int mmMC_SEQ_TRAIN_EDC_THRESHOLD2__SI__CI = 0x0AFE; -constexpr unsigned int mmMC_SEQ_TRAIN_EDC_THRESHOLD3__SI__CI = 0x0AFF; -constexpr unsigned int mmMC_SEQ_TRAIN_TIMING__SI__CI = 0x0A40; -constexpr unsigned int mmMC_SEQ_TSM_BCNT__SI__CI = 0x0AC2; -constexpr unsigned int mmMC_SEQ_TSM_CTRL__SI__CI = 0x0ABE; -constexpr unsigned int mmMC_SEQ_TSM_DBI__SI__CI = 0x0AC6; -constexpr unsigned int mmMC_SEQ_TSM_DEBUG_DATA__SI__CI = 0x0AD0; -constexpr unsigned int mmMC_SEQ_TSM_DEBUG_INDEX__SI__CI = 0x0ACF; -constexpr unsigned int mmMC_SEQ_TSM_EDC__SI__CI = 0x0AC5; -constexpr unsigned int mmMC_SEQ_TSM_FLAG__SI__CI = 0x0AC3; -constexpr unsigned int mmMC_SEQ_TSM_GCNT__SI__CI = 0x0ABF; -constexpr unsigned int mmMC_SEQ_TSM_MISC__SI__CI = 0x0AE6; -constexpr unsigned int mmMC_SEQ_TSM_NCNT__SI__CI = 0x0AC1; -constexpr unsigned int mmMC_SEQ_TSM_OCNT__SI__CI = 0x0AC0; -constexpr unsigned int mmMC_SEQ_TSM_UPDATE__SI__CI = 0x0AC4; -constexpr unsigned int mmMC_SEQ_TSM_WCDR__SI__CI = 0x0AE3; -constexpr unsigned int mmMC_SEQ_TXFRAMING_BYTE0_D0__SI__CI = 0x0A58; -constexpr unsigned int mmMC_SEQ_TXFRAMING_BYTE0_D1__SI__CI = 0x0A60; -constexpr unsigned int mmMC_SEQ_TXFRAMING_BYTE1_D0__SI__CI = 0x0A59; -constexpr unsigned int mmMC_SEQ_TXFRAMING_BYTE1_D1__SI__CI = 0x0A61; -constexpr unsigned int mmMC_SEQ_TXFRAMING_BYTE2_D0__SI__CI = 0x0A5A; -constexpr unsigned int mmMC_SEQ_TXFRAMING_BYTE2_D1__SI__CI = 0x0A62; -constexpr unsigned int mmMC_SEQ_TXFRAMING_BYTE3_D0__SI__CI = 0x0A5B; -constexpr unsigned int mmMC_SEQ_TXFRAMING_BYTE3_D1__SI__CI = 0x0A63; -constexpr unsigned int mmMC_SEQ_TXFRAMING_DBI_D0__SI__CI = 0x0A5C; -constexpr unsigned int mmMC_SEQ_TXFRAMING_DBI_D1__SI__CI = 0x0A64; -constexpr unsigned int mmMC_SEQ_TXFRAMING_EDC_D0__SI__CI = 0x0A5D; -constexpr unsigned int mmMC_SEQ_TXFRAMING_EDC_D1__SI__CI = 0x0A65; -constexpr unsigned int mmMC_SEQ_TXFRAMING_FCK_D0__SI__CI = 0x0A5E; -constexpr unsigned int mmMC_SEQ_TXFRAMING_FCK_D1__SI__CI = 0x0A66; -constexpr unsigned int mmMC_SEQ_VENDOR_ID_I0__SI__CI = 0x0A7E; -constexpr unsigned int mmMC_SEQ_VENDOR_ID_I1__SI__CI = 0x0A7F; -constexpr unsigned int mmMC_SEQ_WCDR_CTRL__SI__CI = 0x0A39; -constexpr unsigned int mmMC_SEQ_WR_CTL_2__SI__CI = 0x0AD5; -constexpr unsigned int mmMC_SEQ_WR_CTL_2_LP__SI__CI = 0x0AD6; -constexpr unsigned int mmMC_SHARED_BLACKOUT_CNTL = 0x082B; -constexpr unsigned int mmMC_SHARED_CHMAP = 0x0801; -constexpr unsigned int mmMC_SHARED_CHREMAP = 0x0802; -constexpr unsigned int mmMC_TRAIN_EDCCDR_R_D0__SI__CI = 0x0A41; -constexpr unsigned int mmMC_TRAIN_EDCCDR_R_D1__SI__CI = 0x0A42; -constexpr unsigned int mmMC_TRAIN_EDC_STATUS_D0__SI__CI = 0x0A45; -constexpr unsigned int mmMC_TRAIN_EDC_STATUS_D1__SI__CI = 0x0A48; -constexpr unsigned int mmMC_TRAIN_PRBSERR_0_D0__SI__CI = 0x0A43; -constexpr unsigned int mmMC_TRAIN_PRBSERR_0_D1__SI__CI = 0x0A46; -constexpr unsigned int mmMC_TRAIN_PRBSERR_1_D0__SI__CI = 0x0A44; -constexpr unsigned int mmMC_TRAIN_PRBSERR_1_D1__SI__CI = 0x0A47; -constexpr unsigned int mmMC_TRAIN_PRBSERR_2_D0__SI__CI = 0x0AFB; -constexpr unsigned int mmMC_TRAIN_PRBSERR_2_D1__SI__CI = 0x0AFC; -constexpr unsigned int mmMC_VM_AGP_BASE = 0x080C; -constexpr unsigned int mmMC_VM_AGP_BOT = 0x080B; -constexpr unsigned int mmMC_VM_AGP_TOP = 0x080A; -constexpr unsigned int mmMC_VM_DC_WRITE_CNTL = 0x0810; -constexpr unsigned int mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR = 0x0815; -constexpr unsigned int mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR = 0x0811; -constexpr unsigned int mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR = 0x0816; -constexpr unsigned int mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR = 0x0812; -constexpr unsigned int mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR = 0x0817; -constexpr unsigned int mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR = 0x0813; -constexpr unsigned int mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR = 0x0818; -constexpr unsigned int mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR = 0x0814; -constexpr unsigned int mmMC_VM_FB_LOCATION = 0x0809; -constexpr unsigned int mmMC_VM_FB_OFFSET = 0x081A; -constexpr unsigned int mmMC_VM_L2_PERFCOUNTER0_CFG__CI__VI = 0x07CC; -constexpr unsigned int mmMC_VM_L2_PERFCOUNTER1_CFG__CI__VI = 0x07CD; -constexpr unsigned int mmMC_VM_L2_PERFCOUNTER_HI__CI__VI = 0x07AD; -constexpr unsigned int mmMC_VM_L2_PERFCOUNTER_LO__CI__VI = 0x07A5; -constexpr unsigned int mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CI__VI = 0x07D3; -constexpr unsigned int mmMC_VM_MB_L1_TLB0_DEBUG = 0x0891; -constexpr unsigned int mmMC_VM_MB_L1_TLB0_STATUS = 0x0895; -constexpr unsigned int mmMC_VM_MB_L1_TLB1_STATUS = 0x0896; -constexpr unsigned int mmMC_VM_MB_L1_TLB2_DEBUG = 0x0893; -constexpr unsigned int mmMC_VM_MB_L1_TLB2_STATUS = 0x0897; -constexpr unsigned int mmMC_VM_MB_L1_TLB3_DEBUG = 0x08A5; -constexpr unsigned int mmMC_VM_MB_L1_TLB3_STATUS = 0x08A6; -constexpr unsigned int mmMC_VM_MB_L2ARBITER_L2_CREDITS = 0x08A1; -constexpr unsigned int mmMC_VM_MD_L1_TLB0_DEBUG = 0x0998; -constexpr unsigned int mmMC_VM_MD_L1_TLB0_STATUS = 0x099B; -constexpr unsigned int mmMC_VM_MD_L1_TLB1_DEBUG = 0x0999; -constexpr unsigned int mmMC_VM_MD_L1_TLB1_STATUS = 0x099C; -constexpr unsigned int mmMC_VM_MD_L1_TLB2_DEBUG = 0x099A; -constexpr unsigned int mmMC_VM_MD_L1_TLB2_STATUS = 0x099D; -constexpr unsigned int mmMC_VM_MD_L1_TLB3_DEBUG = 0x09A7; -constexpr unsigned int mmMC_VM_MD_L1_TLB3_STATUS = 0x09A8; -constexpr unsigned int mmMC_VM_MD_L2ARBITER_L2_CREDITS = 0x09A4; -constexpr unsigned int mmMC_VM_MX_L1_TLB_CNTL = 0x0819; -constexpr unsigned int mmMC_VM_STEERING__CI__VI = 0x081B; -constexpr unsigned int mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR = 0x080F; -constexpr unsigned int mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x080E; -constexpr unsigned int mmMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x080D; -constexpr unsigned int mmMC_WR_CB = 0x0986; -constexpr unsigned int mmMC_WR_DB = 0x0987; -constexpr unsigned int mmMC_WR_GRP_EXT = 0x0979; -constexpr unsigned int mmMC_WR_GRP_GFX = 0x0804; -constexpr unsigned int mmMC_WR_GRP_LCL = 0x098B; -constexpr unsigned int mmMC_WR_GRP_OTH = 0x0808; -constexpr unsigned int mmMC_WR_GRP_SYS = 0x0806; -constexpr unsigned int mmMC_WR_HUB = 0x0988; -constexpr unsigned int mmMC_WR_TC0 = 0x097B; -constexpr unsigned int mmMC_WR_TC1 = 0x097C; -constexpr unsigned int mmMC_XBAR_ADDR_DEC = 0x0C80; -constexpr unsigned int mmMC_XBAR_ARB = 0x0C8D; -constexpr unsigned int mmMC_XBAR_ARB_MAX_BURST = 0x0C8E; -constexpr unsigned int mmMC_XBAR_CHTRIREMAP = 0x0C8B; -constexpr unsigned int mmMC_XBAR_PERF_MON_CNTL0__SI__CI = 0x0C8F; -constexpr unsigned int mmMC_XBAR_PERF_MON_CNTL1__SI__CI = 0x0C90; -constexpr unsigned int mmMC_XBAR_PERF_MON_CNTL2__SI__CI = 0x0C91; -constexpr unsigned int mmMC_XBAR_PERF_MON_MAX_THSH__SI__CI = 0x0C96; -constexpr unsigned int mmMC_XBAR_PERF_MON_RSLT0__SI__CI = 0x0C92; -constexpr unsigned int mmMC_XBAR_PERF_MON_RSLT1__SI__CI = 0x0C93; -constexpr unsigned int mmMC_XBAR_PERF_MON_RSLT2__SI__CI = 0x0C94; -constexpr unsigned int mmMC_XBAR_PERF_MON_RSLT3__SI__CI = 0x0C95; -constexpr unsigned int mmMC_XBAR_RDREQ_CREDIT = 0x0C83; -constexpr unsigned int mmMC_XBAR_RDREQ_PRI_CREDIT = 0x0C84; -constexpr unsigned int mmMC_XBAR_RDRET_CREDIT1 = 0x0C87; -constexpr unsigned int mmMC_XBAR_RDRET_CREDIT2 = 0x0C88; -constexpr unsigned int mmMC_XBAR_RDRET_PRI_CREDIT1 = 0x0C89; -constexpr unsigned int mmMC_XBAR_RDRET_PRI_CREDIT2 = 0x0C8A; -constexpr unsigned int mmMC_XBAR_REMOTE = 0x0C81; -constexpr unsigned int mmMC_XBAR_SPARE0 = 0x0C97; -constexpr unsigned int mmMC_XBAR_SPARE1 = 0x0C98; -constexpr unsigned int mmMC_XBAR_TWOCHAN = 0x0C8C; -constexpr unsigned int mmMC_XBAR_WRREQ_CREDIT = 0x0C82; -constexpr unsigned int mmMC_XBAR_WRRET_CREDIT1 = 0x0C85; -constexpr unsigned int mmMC_XBAR_WRRET_CREDIT2 = 0x0C86; -constexpr unsigned int mmMC_XPB_CLG_CFG0 = 0x08E9; -constexpr unsigned int mmMC_XPB_CLG_CFG1 = 0x08EA; -constexpr unsigned int mmMC_XPB_CLG_CFG10 = 0x08F3; -constexpr unsigned int mmMC_XPB_CLG_CFG11 = 0x08F4; -constexpr unsigned int mmMC_XPB_CLG_CFG12 = 0x08F5; -constexpr unsigned int mmMC_XPB_CLG_CFG13 = 0x08F6; -constexpr unsigned int mmMC_XPB_CLG_CFG14 = 0x08F7; -constexpr unsigned int mmMC_XPB_CLG_CFG15 = 0x08F8; -constexpr unsigned int mmMC_XPB_CLG_CFG16 = 0x08F9; -constexpr unsigned int mmMC_XPB_CLG_CFG17 = 0x08FA; -constexpr unsigned int mmMC_XPB_CLG_CFG18 = 0x08FB; -constexpr unsigned int mmMC_XPB_CLG_CFG19 = 0x08FC; -constexpr unsigned int mmMC_XPB_CLG_CFG2 = 0x08EB; -constexpr unsigned int mmMC_XPB_CLG_CFG20 = 0x0928; -constexpr unsigned int mmMC_XPB_CLG_CFG21 = 0x0929; -constexpr unsigned int mmMC_XPB_CLG_CFG22 = 0x092A; -constexpr unsigned int mmMC_XPB_CLG_CFG23 = 0x092B; -constexpr unsigned int mmMC_XPB_CLG_CFG24 = 0x092C; -constexpr unsigned int mmMC_XPB_CLG_CFG25 = 0x092D; -constexpr unsigned int mmMC_XPB_CLG_CFG26 = 0x092E; -constexpr unsigned int mmMC_XPB_CLG_CFG27 = 0x092F; -constexpr unsigned int mmMC_XPB_CLG_CFG28 = 0x0930; -constexpr unsigned int mmMC_XPB_CLG_CFG29 = 0x0931; -constexpr unsigned int mmMC_XPB_CLG_CFG3 = 0x08EC; -constexpr unsigned int mmMC_XPB_CLG_CFG30 = 0x0932; -constexpr unsigned int mmMC_XPB_CLG_CFG31 = 0x0933; -constexpr unsigned int mmMC_XPB_CLG_CFG32 = 0x0936; -constexpr unsigned int mmMC_XPB_CLG_CFG33 = 0x0937; -constexpr unsigned int mmMC_XPB_CLG_CFG34 = 0x0938; -constexpr unsigned int mmMC_XPB_CLG_CFG35 = 0x0939; -constexpr unsigned int mmMC_XPB_CLG_CFG36 = 0x093A; -constexpr unsigned int mmMC_XPB_CLG_CFG4 = 0x08ED; -constexpr unsigned int mmMC_XPB_CLG_CFG5 = 0x08EE; -constexpr unsigned int mmMC_XPB_CLG_CFG6 = 0x08EF; -constexpr unsigned int mmMC_XPB_CLG_CFG7 = 0x08F0; -constexpr unsigned int mmMC_XPB_CLG_CFG8 = 0x08F1; -constexpr unsigned int mmMC_XPB_CLG_CFG9 = 0x08F2; -constexpr unsigned int mmMC_XPB_CLG_EXTRA = 0x08FD; -constexpr unsigned int mmMC_XPB_CLG_EXTRA_RD = 0x0935; -constexpr unsigned int mmMC_XPB_CLK_GAT = 0x091E; -constexpr unsigned int mmMC_XPB_INTF_CFG = 0x091F; -constexpr unsigned int mmMC_XPB_INTF_CFG2 = 0x0934; -constexpr unsigned int mmMC_XPB_INTF_STS = 0x0920; -constexpr unsigned int mmMC_XPB_LB_ADDR = 0x08FE; -constexpr unsigned int mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB = 0x0923; -constexpr unsigned int mmMC_XPB_MISC_CFG = 0x0927; -constexpr unsigned int mmMC_XPB_P2P_BAR0 = 0x0904; -constexpr unsigned int mmMC_XPB_P2P_BAR1 = 0x0905; -constexpr unsigned int mmMC_XPB_P2P_BAR2 = 0x0906; -constexpr unsigned int mmMC_XPB_P2P_BAR3 = 0x0907; -constexpr unsigned int mmMC_XPB_P2P_BAR4 = 0x0908; -constexpr unsigned int mmMC_XPB_P2P_BAR5 = 0x0909; -constexpr unsigned int mmMC_XPB_P2P_BAR6 = 0x090A; -constexpr unsigned int mmMC_XPB_P2P_BAR7 = 0x090B; -constexpr unsigned int mmMC_XPB_P2P_BAR_CFG = 0x0903; -constexpr unsigned int mmMC_XPB_P2P_BAR_DEBUG = 0x090D; -constexpr unsigned int mmMC_XPB_P2P_BAR_DELTA_ABOVE = 0x090E; -constexpr unsigned int mmMC_XPB_P2P_BAR_DELTA_BELOW = 0x090F; -constexpr unsigned int mmMC_XPB_P2P_BAR_SETUP = 0x090C; -constexpr unsigned int mmMC_XPB_PEER_SYS_BAR0 = 0x0910; -constexpr unsigned int mmMC_XPB_PEER_SYS_BAR1 = 0x0911; -constexpr unsigned int mmMC_XPB_PEER_SYS_BAR2 = 0x0912; -constexpr unsigned int mmMC_XPB_PEER_SYS_BAR3 = 0x0913; -constexpr unsigned int mmMC_XPB_PEER_SYS_BAR4 = 0x0914; -constexpr unsigned int mmMC_XPB_PEER_SYS_BAR5 = 0x0915; -constexpr unsigned int mmMC_XPB_PEER_SYS_BAR6 = 0x0916; -constexpr unsigned int mmMC_XPB_PEER_SYS_BAR7 = 0x0917; -constexpr unsigned int mmMC_XPB_PEER_SYS_BAR8 = 0x0918; -constexpr unsigned int mmMC_XPB_PEER_SYS_BAR9 = 0x0919; -constexpr unsigned int mmMC_XPB_PERF_KNOBS = 0x0924; -constexpr unsigned int mmMC_XPB_PIPE_STS = 0x0921; -constexpr unsigned int mmMC_XPB_RTR_DEST_MAP0 = 0x08DB; -constexpr unsigned int mmMC_XPB_RTR_DEST_MAP1 = 0x08DC; -constexpr unsigned int mmMC_XPB_RTR_DEST_MAP2 = 0x08DD; -constexpr unsigned int mmMC_XPB_RTR_DEST_MAP3 = 0x08DE; -constexpr unsigned int mmMC_XPB_RTR_DEST_MAP4 = 0x08DF; -constexpr unsigned int mmMC_XPB_RTR_DEST_MAP5 = 0x08E0; -constexpr unsigned int mmMC_XPB_RTR_DEST_MAP6 = 0x08E1; -constexpr unsigned int mmMC_XPB_RTR_DEST_MAP7 = 0x08E2; -constexpr unsigned int mmMC_XPB_RTR_DEST_MAP8 = 0x08E3; -constexpr unsigned int mmMC_XPB_RTR_DEST_MAP9 = 0x08E4; -constexpr unsigned int mmMC_XPB_RTR_SRC_APRTR0 = 0x08CD; -constexpr unsigned int mmMC_XPB_RTR_SRC_APRTR1 = 0x08CE; -constexpr unsigned int mmMC_XPB_RTR_SRC_APRTR2 = 0x08CF; -constexpr unsigned int mmMC_XPB_RTR_SRC_APRTR3 = 0x08D0; -constexpr unsigned int mmMC_XPB_RTR_SRC_APRTR4 = 0x08D1; -constexpr unsigned int mmMC_XPB_RTR_SRC_APRTR5 = 0x08D2; -constexpr unsigned int mmMC_XPB_RTR_SRC_APRTR6 = 0x08D3; -constexpr unsigned int mmMC_XPB_RTR_SRC_APRTR7 = 0x08D4; -constexpr unsigned int mmMC_XPB_RTR_SRC_APRTR8 = 0x08D5; -constexpr unsigned int mmMC_XPB_RTR_SRC_APRTR9 = 0x08D6; -constexpr unsigned int mmMC_XPB_STICKY = 0x0925; -constexpr unsigned int mmMC_XPB_STICKY_W1C = 0x0926; -constexpr unsigned int mmMC_XPB_SUB_CTRL = 0x0922; -constexpr unsigned int mmMC_XPB_UNC_THRESH_HST = 0x08FF; -constexpr unsigned int mmMC_XPB_UNC_THRESH_SID = 0x0900; -constexpr unsigned int mmMC_XPB_WCB_CFG = 0x0902; -constexpr unsigned int mmMC_XPB_WCB_STS = 0x0901; -constexpr unsigned int mmMC_XPB_XDMA_PEER_SYS_BAR0 = 0x091A; -constexpr unsigned int mmMC_XPB_XDMA_PEER_SYS_BAR1 = 0x091B; -constexpr unsigned int mmMC_XPB_XDMA_PEER_SYS_BAR2 = 0x091C; -constexpr unsigned int mmMC_XPB_XDMA_PEER_SYS_BAR3 = 0x091D; -constexpr unsigned int mmMC_XPB_XDMA_RTR_DEST_MAP0 = 0x08E5; -constexpr unsigned int mmMC_XPB_XDMA_RTR_DEST_MAP1 = 0x08E6; -constexpr unsigned int mmMC_XPB_XDMA_RTR_DEST_MAP2 = 0x08E7; -constexpr unsigned int mmMC_XPB_XDMA_RTR_DEST_MAP3 = 0x08E8; -constexpr unsigned int mmMC_XPB_XDMA_RTR_SRC_APRTR0 = 0x08D7; -constexpr unsigned int mmMC_XPB_XDMA_RTR_SRC_APRTR1 = 0x08D8; -constexpr unsigned int mmMC_XPB_XDMA_RTR_SRC_APRTR2 = 0x08D9; -constexpr unsigned int mmMC_XPB_XDMA_RTR_SRC_APRTR3 = 0x08DA; -constexpr unsigned int mmMEM_TYPE_CNTL__CI__VI = 0x14E4; -constexpr unsigned int mmMICROSECOND_TIME_BASE_DIV__SI = 0x0148; -constexpr unsigned int mmMM_CFGREGS_CNTL = 0x1513; -constexpr unsigned int mmMM_DATA = 0x0001; -constexpr unsigned int mmMM_INDEX = 0x0000; -constexpr unsigned int mmMM_INDEX_HI__CI__VI = 0x0006; -constexpr unsigned int mmMPLL_AD_FUNC_CNTL__SI__CI = 0x0AF0; -constexpr unsigned int mmMPLL_AD_STATUS__SI__CI = 0x0AF6; -constexpr unsigned int mmMPLL_BYPASSCLK_SEL__SI = 0x0197; -constexpr unsigned int mmMPLL_CNTL_MODE__SI__CI = 0x0AEC; -constexpr unsigned int mmMPLL_CONTROL__SI__CI = 0x0AF5; -constexpr unsigned int mmMPLL_DQ_0_0_STATUS__SI__CI = 0x0AF7; -constexpr unsigned int mmMPLL_DQ_0_1_STATUS__SI__CI = 0x0AF8; -constexpr unsigned int mmMPLL_DQ_1_0_STATUS__SI__CI = 0x0AF9; -constexpr unsigned int mmMPLL_DQ_1_1_STATUS__SI__CI = 0x0AFA; -constexpr unsigned int mmMPLL_DQ_FUNC_CNTL__SI__CI = 0x0AF1; -constexpr unsigned int mmMPLL_FUNC_CNTL__SI__CI = 0x0AED; -constexpr unsigned int mmMPLL_FUNC_CNTL_1__SI__CI = 0x0AEE; -constexpr unsigned int mmMPLL_FUNC_CNTL_2__SI__CI = 0x0AEF; -constexpr unsigned int mmMPLL_SEQ_UCODE_1__SI__CI = 0x0AEA; -constexpr unsigned int mmMPLL_SEQ_UCODE_2__SI__CI = 0x0AEB; -constexpr unsigned int mmMPLL_SS1__SI__CI = 0x0AF3; -constexpr unsigned int mmMPLL_SS2__SI__CI = 0x0AF4; -constexpr unsigned int mmMPLL_TIME__SI__CI = 0x0AF2; -constexpr unsigned int mmMVP_AFR_FLIP_FIFO_CNTL__SI = 0x1AD9; -constexpr unsigned int mmMVP_AFR_FLIP_MODE__SI = 0x1AD8; -constexpr unsigned int mmMVP_BLACK_KEYER__SI = 0x1686; -constexpr unsigned int mmMVP_CONTROL1__SI = 0x1680; -constexpr unsigned int mmMVP_CONTROL2__SI = 0x1681; -constexpr unsigned int mmMVP_CONTROL3__SI = 0x168A; -constexpr unsigned int mmMVP_CRC_CNTL__SI = 0x1687; -constexpr unsigned int mmMVP_CRC_RESULT_BLUE_GREEN__SI = 0x1688; -constexpr unsigned int mmMVP_CRC_RESULT_RED__SI = 0x1689; -constexpr unsigned int mmMVP_FIFO_CONTROL__SI = 0x1682; -constexpr unsigned int mmMVP_FIFO_STATUS__SI = 0x1683; -constexpr unsigned int mmMVP_FLIP_LINE_NUM_INSERT__SI = 0x1ADA; -constexpr unsigned int mmMVP_INBAND_CNTL_CAP__SI = 0x1685; -constexpr unsigned int mmMVP_RECEIVE_CNT_CNTL1__SI = 0x168B; -constexpr unsigned int mmMVP_RECEIVE_CNT_CNTL2__SI = 0x168C; -constexpr unsigned int mmMVP_SLAVE_STATUS__SI = 0x1684; -constexpr unsigned int mmMVP_TEST_DEBUG_DATA__SI = 0x168E; -constexpr unsigned int mmMVP_TEST_DEBUG_INDEX__SI = 0x168D; -constexpr unsigned int mmNEW_REFCLKB_TIMER_1__CI = 0x1484; -constexpr unsigned int mmNEW_REFCLKB_TIMER__CI = 0x1485; -constexpr unsigned int mmOVLSCL_EDGE_PIXEL_CNTL__SI__VI = 0x1A2C; -constexpr unsigned int mmOVL_CONTROL1__SI__VI = 0x1A1D; -constexpr unsigned int mmOVL_CONTROL2__SI__VI = 0x1A1E; -constexpr unsigned int mmOVL_DFQ_CONTROL__SI__VI = 0x1A29; -constexpr unsigned int mmOVL_DFQ_STATUS__SI__VI = 0x1A2A; -constexpr unsigned int mmOVL_ENABLE__SI__VI = 0x1A1C; -constexpr unsigned int mmOVL_END__SI__VI = 0x1A26; -constexpr unsigned int mmOVL_PITCH__SI__VI = 0x1A21; -constexpr unsigned int mmOVL_START__SI__VI = 0x1A25; -constexpr unsigned int mmOVL_SURFACE_ADDRESS = 0x1A20; -constexpr unsigned int mmOVL_SURFACE_ADDRESS_HIGH = 0x1A22; -constexpr unsigned int mmOVL_SURFACE_ADDRESS_HIGH_INUSE__SI__VI = 0x1A2B; -constexpr unsigned int mmOVL_SURFACE_ADDRESS_INUSE__SI__VI = 0x1A28; -constexpr unsigned int mmOVL_SURFACE_OFFSET_X__SI__VI = 0x1A23; -constexpr unsigned int mmOVL_SURFACE_OFFSET_Y__SI__VI = 0x1A24; -constexpr unsigned int mmOVL_SWAP_CNTL__SI__VI = 0x1A1F; -constexpr unsigned int mmOVL_UPDATE__SI__VI = 0x1A27; -constexpr unsigned int mmPAGE_MIRROR_CNTL__SI = 0x0581; -constexpr unsigned int mmPA_CL_CLIP_CNTL = 0xA204; -constexpr unsigned int mmPA_CL_CNTL_STATUS = 0x2284; -constexpr unsigned int mmPA_CL_ENHANCE = 0x2285; -constexpr unsigned int mmPA_CL_GB_HORZ_CLIP_ADJ = 0xA2FC; -constexpr unsigned int mmPA_CL_GB_HORZ_DISC_ADJ = 0xA2FD; -constexpr unsigned int mmPA_CL_GB_VERT_CLIP_ADJ = 0xA2FA; -constexpr unsigned int mmPA_CL_GB_VERT_DISC_ADJ = 0xA2FB; -constexpr unsigned int mmPA_CL_NANINF_CNTL = 0xA208; -constexpr unsigned int mmPA_CL_POINT_CULL_RAD = 0xA1F8; -constexpr unsigned int mmPA_CL_POINT_SIZE = 0xA1F7; -constexpr unsigned int mmPA_CL_POINT_X_RAD = 0xA1F5; -constexpr unsigned int mmPA_CL_POINT_Y_RAD = 0xA1F6; -constexpr unsigned int mmPA_CL_RESET_DEBUG__CI__VI = 0x2286; -constexpr unsigned int mmPA_CL_UCP_0_W = 0xA172; -constexpr unsigned int mmPA_CL_UCP_0_X = 0xA16F; -constexpr unsigned int mmPA_CL_UCP_0_Y = 0xA170; -constexpr unsigned int mmPA_CL_UCP_0_Z = 0xA171; -constexpr unsigned int mmPA_CL_UCP_1_W = 0xA176; -constexpr unsigned int mmPA_CL_UCP_1_X = 0xA173; -constexpr unsigned int mmPA_CL_UCP_1_Y = 0xA174; -constexpr unsigned int mmPA_CL_UCP_1_Z = 0xA175; -constexpr unsigned int mmPA_CL_UCP_2_W = 0xA17A; -constexpr unsigned int mmPA_CL_UCP_2_X = 0xA177; -constexpr unsigned int mmPA_CL_UCP_2_Y = 0xA178; -constexpr unsigned int mmPA_CL_UCP_2_Z = 0xA179; -constexpr unsigned int mmPA_CL_UCP_3_W = 0xA17E; -constexpr unsigned int mmPA_CL_UCP_3_X = 0xA17B; -constexpr unsigned int mmPA_CL_UCP_3_Y = 0xA17C; -constexpr unsigned int mmPA_CL_UCP_3_Z = 0xA17D; -constexpr unsigned int mmPA_CL_UCP_4_W = 0xA182; -constexpr unsigned int mmPA_CL_UCP_4_X = 0xA17F; -constexpr unsigned int mmPA_CL_UCP_4_Y = 0xA180; -constexpr unsigned int mmPA_CL_UCP_4_Z = 0xA181; -constexpr unsigned int mmPA_CL_UCP_5_W = 0xA186; -constexpr unsigned int mmPA_CL_UCP_5_X = 0xA183; -constexpr unsigned int mmPA_CL_UCP_5_Y = 0xA184; -constexpr unsigned int mmPA_CL_UCP_5_Z = 0xA185; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET = 0xA110; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_1 = 0xA116; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_10 = 0xA14C; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_11 = 0xA152; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_12 = 0xA158; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_13 = 0xA15E; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_14 = 0xA164; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_15 = 0xA16A; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_2 = 0xA11C; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_3 = 0xA122; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_4 = 0xA128; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_5 = 0xA12E; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_6 = 0xA134; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_7 = 0xA13A; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_8 = 0xA140; -constexpr unsigned int mmPA_CL_VPORT_XOFFSET_9 = 0xA146; -constexpr unsigned int mmPA_CL_VPORT_XSCALE = 0xA10F; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_1 = 0xA115; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_10 = 0xA14B; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_11 = 0xA151; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_12 = 0xA157; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_13 = 0xA15D; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_14 = 0xA163; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_15 = 0xA169; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_2 = 0xA11B; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_3 = 0xA121; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_4 = 0xA127; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_5 = 0xA12D; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_6 = 0xA133; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_7 = 0xA139; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_8 = 0xA13F; -constexpr unsigned int mmPA_CL_VPORT_XSCALE_9 = 0xA145; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET = 0xA112; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_1 = 0xA118; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_10 = 0xA14E; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_11 = 0xA154; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_12 = 0xA15A; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_13 = 0xA160; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_14 = 0xA166; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_15 = 0xA16C; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_2 = 0xA11E; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_3 = 0xA124; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_4 = 0xA12A; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_5 = 0xA130; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_6 = 0xA136; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_7 = 0xA13C; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_8 = 0xA142; -constexpr unsigned int mmPA_CL_VPORT_YOFFSET_9 = 0xA148; -constexpr unsigned int mmPA_CL_VPORT_YSCALE = 0xA111; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_1 = 0xA117; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_10 = 0xA14D; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_11 = 0xA153; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_12 = 0xA159; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_13 = 0xA15F; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_14 = 0xA165; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_15 = 0xA16B; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_2 = 0xA11D; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_3 = 0xA123; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_4 = 0xA129; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_5 = 0xA12F; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_6 = 0xA135; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_7 = 0xA13B; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_8 = 0xA141; -constexpr unsigned int mmPA_CL_VPORT_YSCALE_9 = 0xA147; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET = 0xA114; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_1 = 0xA11A; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_10 = 0xA150; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_11 = 0xA156; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_12 = 0xA15C; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_13 = 0xA162; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_14 = 0xA168; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_15 = 0xA16E; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_2 = 0xA120; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_3 = 0xA126; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_4 = 0xA12C; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_5 = 0xA132; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_6 = 0xA138; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_7 = 0xA13E; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_8 = 0xA144; -constexpr unsigned int mmPA_CL_VPORT_ZOFFSET_9 = 0xA14A; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE = 0xA113; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_1 = 0xA119; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_10 = 0xA14F; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_11 = 0xA155; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_12 = 0xA15B; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_13 = 0xA161; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_14 = 0xA167; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_15 = 0xA16D; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_2 = 0xA11F; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_3 = 0xA125; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_4 = 0xA12B; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_5 = 0xA131; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_6 = 0xA137; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_7 = 0xA13D; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_8 = 0xA143; -constexpr unsigned int mmPA_CL_VPORT_ZSCALE_9 = 0xA149; -constexpr unsigned int mmPA_CL_VS_OUT_CNTL = 0xA207; -constexpr unsigned int mmPA_CL_VTE_CNTL = 0xA206; -constexpr unsigned int mmPA_SC_AA_CONFIG = 0xA2F8; -constexpr unsigned int mmPA_SC_AA_MASK_X0Y0_X1Y0 = 0xA30E; -constexpr unsigned int mmPA_SC_AA_MASK_X0Y1_X1Y1 = 0xA30F; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0xA2FE; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0xA2FF; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0xA300; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0xA301; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0xA306; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0xA307; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0xA308; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0xA309; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0xA302; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0xA303; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0xA304; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0xA305; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0xA30A; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0xA30B; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0xA30C; -constexpr unsigned int mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0xA30D; -constexpr unsigned int mmPA_SC_CENTROID_PRIORITY_0 = 0xA2F5; -constexpr unsigned int mmPA_SC_CENTROID_PRIORITY_1 = 0xA2F6; -constexpr unsigned int mmPA_SC_CLIPRECT_0_BR = 0xA085; -constexpr unsigned int mmPA_SC_CLIPRECT_0_TL = 0xA084; -constexpr unsigned int mmPA_SC_CLIPRECT_1_BR = 0xA087; -constexpr unsigned int mmPA_SC_CLIPRECT_1_TL = 0xA086; -constexpr unsigned int mmPA_SC_CLIPRECT_2_BR = 0xA089; -constexpr unsigned int mmPA_SC_CLIPRECT_2_TL = 0xA088; -constexpr unsigned int mmPA_SC_CLIPRECT_3_BR = 0xA08B; -constexpr unsigned int mmPA_SC_CLIPRECT_3_TL = 0xA08A; -constexpr unsigned int mmPA_SC_CLIPRECT_RULE = 0xA083; -constexpr unsigned int mmPA_SC_DEBUG_CNTL = 0x22F6; -constexpr unsigned int mmPA_SC_DEBUG_DATA = 0x22F7; -constexpr unsigned int mmPA_SC_EDGERULE = 0xA08C; -constexpr unsigned int mmPA_SC_ENHANCE = 0x22FC; -constexpr unsigned int mmPA_SC_FIFO_DEPTH_CNTL = 0x2295; -constexpr unsigned int mmPA_SC_FIFO_SIZE = 0x22F3; -constexpr unsigned int mmPA_SC_FORCE_EOV_MAX_CNTS = 0x22C9; -constexpr unsigned int mmPA_SC_GENERIC_SCISSOR_BR = 0xA091; -constexpr unsigned int mmPA_SC_GENERIC_SCISSOR_TL = 0xA090; -constexpr unsigned int mmPA_SC_HP3D_TRAP_SCREEN_COUNT__CI__VI = 0xC2AC; -constexpr unsigned int mmPA_SC_HP3D_TRAP_SCREEN_HV_EN__CI__VI = 0xC2A8; -constexpr unsigned int mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK__CI__VI = 0x22C1; -constexpr unsigned int mmPA_SC_HP3D_TRAP_SCREEN_H__CI__VI = 0xC2A9; -constexpr unsigned int mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__CI__VI = 0xC2AB; -constexpr unsigned int mmPA_SC_HP3D_TRAP_SCREEN_V__CI__VI = 0xC2AA; -constexpr unsigned int mmPA_SC_IF_FIFO_SIZE = 0x22F5; -constexpr unsigned int mmPA_SC_LINE_CNTL = 0xA2F7; -constexpr unsigned int mmPA_SC_LINE_STIPPLE = 0xA283; -constexpr unsigned int mmPA_SC_LINE_STIPPLE_STATE__CI__VI = 0xC281; -constexpr unsigned int mmPA_SC_LINE_STIPPLE_STATE__SI = 0x22C4; -constexpr unsigned int mmPA_SC_MODE_CNTL_0 = 0xA292; -constexpr unsigned int mmPA_SC_MODE_CNTL_1 = 0xA293; -constexpr unsigned int mmPA_SC_P3D_TRAP_SCREEN_COUNT__CI__VI = 0xC2A4; -constexpr unsigned int mmPA_SC_P3D_TRAP_SCREEN_HV_EN__CI__VI = 0xC2A0; -constexpr unsigned int mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK__CI__VI = 0x22C0; -constexpr unsigned int mmPA_SC_P3D_TRAP_SCREEN_H__CI__VI = 0xC2A1; -constexpr unsigned int mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE__CI__VI = 0xC2A3; -constexpr unsigned int mmPA_SC_P3D_TRAP_SCREEN_V__CI__VI = 0xC2A2; -constexpr unsigned int mmPA_SC_PERFCOUNTER0_HI__CI__VI = 0xD141; -constexpr unsigned int mmPA_SC_PERFCOUNTER0_HI__SI = 0x22A9; -constexpr unsigned int mmPA_SC_PERFCOUNTER0_LO__CI__VI = 0xD140; -constexpr unsigned int mmPA_SC_PERFCOUNTER0_LO__SI = 0x22A8; -constexpr unsigned int mmPA_SC_PERFCOUNTER0_SELECT1__CI__VI = 0xD941; -constexpr unsigned int mmPA_SC_PERFCOUNTER0_SELECT__CI__VI = 0xD940; -constexpr unsigned int mmPA_SC_PERFCOUNTER0_SELECT__SI = 0x22A0; -constexpr unsigned int mmPA_SC_PERFCOUNTER1_HI__CI__VI = 0xD143; -constexpr unsigned int mmPA_SC_PERFCOUNTER1_HI__SI = 0x22AB; -constexpr unsigned int mmPA_SC_PERFCOUNTER1_LO__CI__VI = 0xD142; -constexpr unsigned int mmPA_SC_PERFCOUNTER1_LO__SI = 0x22AA; -constexpr unsigned int mmPA_SC_PERFCOUNTER1_SELECT__CI__VI = 0xD942; -constexpr unsigned int mmPA_SC_PERFCOUNTER1_SELECT__SI = 0x22A1; -constexpr unsigned int mmPA_SC_PERFCOUNTER2_HI__CI__VI = 0xD145; -constexpr unsigned int mmPA_SC_PERFCOUNTER2_HI__SI = 0x22AD; -constexpr unsigned int mmPA_SC_PERFCOUNTER2_LO__CI__VI = 0xD144; -constexpr unsigned int mmPA_SC_PERFCOUNTER2_LO__SI = 0x22AC; -constexpr unsigned int mmPA_SC_PERFCOUNTER2_SELECT__CI__VI = 0xD943; -constexpr unsigned int mmPA_SC_PERFCOUNTER2_SELECT__SI = 0x22A2; -constexpr unsigned int mmPA_SC_PERFCOUNTER3_HI__CI__VI = 0xD147; -constexpr unsigned int mmPA_SC_PERFCOUNTER3_HI__SI = 0x22AF; -constexpr unsigned int mmPA_SC_PERFCOUNTER3_LO__CI__VI = 0xD146; -constexpr unsigned int mmPA_SC_PERFCOUNTER3_LO__SI = 0x22AE; -constexpr unsigned int mmPA_SC_PERFCOUNTER3_SELECT__CI__VI = 0xD944; -constexpr unsigned int mmPA_SC_PERFCOUNTER3_SELECT__SI = 0x22A3; -constexpr unsigned int mmPA_SC_PERFCOUNTER4_HI__CI__VI = 0xD149; -constexpr unsigned int mmPA_SC_PERFCOUNTER4_HI__SI = 0x22B1; -constexpr unsigned int mmPA_SC_PERFCOUNTER4_LO__CI__VI = 0xD148; -constexpr unsigned int mmPA_SC_PERFCOUNTER4_LO__SI = 0x22B0; -constexpr unsigned int mmPA_SC_PERFCOUNTER4_SELECT__CI__VI = 0xD945; -constexpr unsigned int mmPA_SC_PERFCOUNTER4_SELECT__SI = 0x22A4; -constexpr unsigned int mmPA_SC_PERFCOUNTER5_HI__CI__VI = 0xD14B; -constexpr unsigned int mmPA_SC_PERFCOUNTER5_HI__SI = 0x22B3; -constexpr unsigned int mmPA_SC_PERFCOUNTER5_LO__CI__VI = 0xD14A; -constexpr unsigned int mmPA_SC_PERFCOUNTER5_LO__SI = 0x22B2; -constexpr unsigned int mmPA_SC_PERFCOUNTER5_SELECT__CI__VI = 0xD946; -constexpr unsigned int mmPA_SC_PERFCOUNTER5_SELECT__SI = 0x22A5; -constexpr unsigned int mmPA_SC_PERFCOUNTER6_HI__CI__VI = 0xD14D; -constexpr unsigned int mmPA_SC_PERFCOUNTER6_HI__SI = 0x22B5; -constexpr unsigned int mmPA_SC_PERFCOUNTER6_LO__CI__VI = 0xD14C; -constexpr unsigned int mmPA_SC_PERFCOUNTER6_LO__SI = 0x22B4; -constexpr unsigned int mmPA_SC_PERFCOUNTER6_SELECT__CI__VI = 0xD947; -constexpr unsigned int mmPA_SC_PERFCOUNTER6_SELECT__SI = 0x22A6; -constexpr unsigned int mmPA_SC_PERFCOUNTER7_HI__CI__VI = 0xD14F; -constexpr unsigned int mmPA_SC_PERFCOUNTER7_HI__SI = 0x22B7; -constexpr unsigned int mmPA_SC_PERFCOUNTER7_LO__CI__VI = 0xD14E; -constexpr unsigned int mmPA_SC_PERFCOUNTER7_LO__SI = 0x22B6; -constexpr unsigned int mmPA_SC_PERFCOUNTER7_SELECT__CI__VI = 0xD948; -constexpr unsigned int mmPA_SC_PERFCOUNTER7_SELECT__SI = 0x22A7; -constexpr unsigned int mmPA_SC_RASTER_CONFIG = 0xA0D4; -constexpr unsigned int mmPA_SC_RASTER_CONFIG_1__CI__VI = 0xA0D5; -constexpr unsigned int mmPA_SC_SCREEN_SCISSOR_BR = 0xA00D; -constexpr unsigned int mmPA_SC_SCREEN_SCISSOR_TL = 0xA00C; -constexpr unsigned int mmPA_SC_TRAP_SCREEN_COUNT__CI__VI = 0xC2B4; -constexpr unsigned int mmPA_SC_TRAP_SCREEN_HV_EN__CI__VI = 0xC2B0; -constexpr unsigned int mmPA_SC_TRAP_SCREEN_HV_LOCK__CI__VI = 0x22C2; -constexpr unsigned int mmPA_SC_TRAP_SCREEN_H__CI__VI = 0xC2B1; -constexpr unsigned int mmPA_SC_TRAP_SCREEN_OCCURRENCE__CI__VI = 0xC2B3; -constexpr unsigned int mmPA_SC_TRAP_SCREEN_V__CI__VI = 0xC2B2; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_0_BR = 0xA095; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_0_TL = 0xA094; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_10_BR = 0xA0A9; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_10_TL = 0xA0A8; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_11_BR = 0xA0AB; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_11_TL = 0xA0AA; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_12_BR = 0xA0AD; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_12_TL = 0xA0AC; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_13_BR = 0xA0AF; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_13_TL = 0xA0AE; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_14_BR = 0xA0B1; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_14_TL = 0xA0B0; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_15_BR = 0xA0B3; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_15_TL = 0xA0B2; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_1_BR = 0xA097; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_1_TL = 0xA096; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_2_BR = 0xA099; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_2_TL = 0xA098; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_3_BR = 0xA09B; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_3_TL = 0xA09A; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_4_BR = 0xA09D; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_4_TL = 0xA09C; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_5_BR = 0xA09F; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_5_TL = 0xA09E; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_6_BR = 0xA0A1; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_6_TL = 0xA0A0; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_7_BR = 0xA0A3; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_7_TL = 0xA0A2; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_8_BR = 0xA0A5; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_8_TL = 0xA0A4; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_9_BR = 0xA0A7; -constexpr unsigned int mmPA_SC_VPORT_SCISSOR_9_TL = 0xA0A6; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_0 = 0xA0B5; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_1 = 0xA0B7; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_10 = 0xA0C9; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_11 = 0xA0CB; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_12 = 0xA0CD; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_13 = 0xA0CF; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_14 = 0xA0D1; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_15 = 0xA0D3; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_2 = 0xA0B9; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_3 = 0xA0BB; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_4 = 0xA0BD; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_5 = 0xA0BF; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_6 = 0xA0C1; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_7 = 0xA0C3; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_8 = 0xA0C5; -constexpr unsigned int mmPA_SC_VPORT_ZMAX_9 = 0xA0C7; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_0 = 0xA0B4; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_1 = 0xA0B6; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_10 = 0xA0C8; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_11 = 0xA0CA; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_12 = 0xA0CC; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_13 = 0xA0CE; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_14 = 0xA0D0; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_15 = 0xA0D2; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_2 = 0xA0B8; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_3 = 0xA0BA; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_4 = 0xA0BC; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_5 = 0xA0BE; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_6 = 0xA0C0; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_7 = 0xA0C2; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_8 = 0xA0C4; -constexpr unsigned int mmPA_SC_VPORT_ZMIN_9 = 0xA0C6; -constexpr unsigned int mmPA_SC_WINDOW_OFFSET = 0xA080; -constexpr unsigned int mmPA_SC_WINDOW_SCISSOR_BR = 0xA082; -constexpr unsigned int mmPA_SC_WINDOW_SCISSOR_TL = 0xA081; -constexpr unsigned int mmPA_SU_CNTL_STATUS = 0x2294; -constexpr unsigned int mmPA_SU_DEBUG_CNTL = 0x2280; -constexpr unsigned int mmPA_SU_DEBUG_DATA = 0x2281; -constexpr unsigned int mmPA_SU_HARDWARE_SCREEN_OFFSET = 0xA08D; -constexpr unsigned int mmPA_SU_LINE_CNTL = 0xA282; -constexpr unsigned int mmPA_SU_LINE_STIPPLE_CNTL = 0xA209; -constexpr unsigned int mmPA_SU_LINE_STIPPLE_SCALE = 0xA20A; -constexpr unsigned int mmPA_SU_LINE_STIPPLE_VALUE__CI__VI = 0xC280; -constexpr unsigned int mmPA_SU_LINE_STIPPLE_VALUE__SI = 0x2298; -constexpr unsigned int mmPA_SU_PERFCOUNTER0_HI__CI__VI = 0xD101; -constexpr unsigned int mmPA_SU_PERFCOUNTER0_HI__SI = 0x228D; -constexpr unsigned int mmPA_SU_PERFCOUNTER0_LO__CI__VI = 0xD100; -constexpr unsigned int mmPA_SU_PERFCOUNTER0_LO__SI = 0x228C; -constexpr unsigned int mmPA_SU_PERFCOUNTER0_SELECT1__CI__VI = 0xD901; -constexpr unsigned int mmPA_SU_PERFCOUNTER0_SELECT__CI__VI = 0xD900; -constexpr unsigned int mmPA_SU_PERFCOUNTER0_SELECT__SI = 0x2288; -constexpr unsigned int mmPA_SU_PERFCOUNTER1_HI__CI__VI = 0xD103; -constexpr unsigned int mmPA_SU_PERFCOUNTER1_HI__SI = 0x228F; -constexpr unsigned int mmPA_SU_PERFCOUNTER1_LO__CI__VI = 0xD102; -constexpr unsigned int mmPA_SU_PERFCOUNTER1_LO__SI = 0x228E; -constexpr unsigned int mmPA_SU_PERFCOUNTER1_SELECT1__CI__VI = 0xD903; -constexpr unsigned int mmPA_SU_PERFCOUNTER1_SELECT__CI__VI = 0xD902; -constexpr unsigned int mmPA_SU_PERFCOUNTER1_SELECT__SI = 0x2289; -constexpr unsigned int mmPA_SU_PERFCOUNTER2_HI__CI__VI = 0xD105; -constexpr unsigned int mmPA_SU_PERFCOUNTER2_HI__SI = 0x2291; -constexpr unsigned int mmPA_SU_PERFCOUNTER2_LO__CI__VI = 0xD104; -constexpr unsigned int mmPA_SU_PERFCOUNTER2_LO__SI = 0x2290; -constexpr unsigned int mmPA_SU_PERFCOUNTER2_SELECT__CI__VI = 0xD904; -constexpr unsigned int mmPA_SU_PERFCOUNTER2_SELECT__SI = 0x228A; -constexpr unsigned int mmPA_SU_PERFCOUNTER3_HI__CI__VI = 0xD107; -constexpr unsigned int mmPA_SU_PERFCOUNTER3_HI__SI = 0x2293; -constexpr unsigned int mmPA_SU_PERFCOUNTER3_LO__CI__VI = 0xD106; -constexpr unsigned int mmPA_SU_PERFCOUNTER3_LO__SI = 0x2292; -constexpr unsigned int mmPA_SU_PERFCOUNTER3_SELECT__CI__VI = 0xD905; -constexpr unsigned int mmPA_SU_PERFCOUNTER3_SELECT__SI = 0x228B; -constexpr unsigned int mmPA_SU_POINT_MINMAX = 0xA281; -constexpr unsigned int mmPA_SU_POINT_SIZE = 0xA280; -constexpr unsigned int mmPA_SU_POLY_OFFSET_BACK_OFFSET = 0xA2E3; -constexpr unsigned int mmPA_SU_POLY_OFFSET_BACK_SCALE = 0xA2E2; -constexpr unsigned int mmPA_SU_POLY_OFFSET_CLAMP = 0xA2DF; -constexpr unsigned int mmPA_SU_POLY_OFFSET_DB_FMT_CNTL = 0xA2DE; -constexpr unsigned int mmPA_SU_POLY_OFFSET_FRONT_OFFSET = 0xA2E1; -constexpr unsigned int mmPA_SU_POLY_OFFSET_FRONT_SCALE = 0xA2E0; -constexpr unsigned int mmPA_SU_PRIM_FILTER_CNTL = 0xA20B; -constexpr unsigned int mmPA_SU_SC_MODE_CNTL = 0xA205; -constexpr unsigned int mmPA_SU_VTX_CNTL = 0xA2F9; -constexpr unsigned int mmPCIE_DATA_2__CI__VI = 0x000D; -constexpr unsigned int mmPCIE_DATA__CI__VI = 0x000F; -constexpr unsigned int mmPCIE_DATA__SI = 0x000D; -constexpr unsigned int mmPCIE_INDEX_2__CI__VI = 0x000C; -constexpr unsigned int mmPCIE_INDEX__CI__VI = 0x000E; -constexpr unsigned int mmPCIE_INDEX__SI = 0x000C; -constexpr unsigned int mmPEER0_FB_OFFSET_HI__CI__VI = 0x14F3; -constexpr unsigned int mmPEER0_FB_OFFSET_LO__CI__VI = 0x14F2; -constexpr unsigned int mmPEER1_FB_OFFSET_HI__CI__VI = 0x14F1; -constexpr unsigned int mmPEER1_FB_OFFSET_LO__CI__VI = 0x14F0; -constexpr unsigned int mmPEER2_FB_OFFSET_HI__CI__VI = 0x14EF; -constexpr unsigned int mmPEER2_FB_OFFSET_LO__CI__VI = 0x14EE; -constexpr unsigned int mmPEER3_FB_OFFSET_HI__CI__VI = 0x14ED; -constexpr unsigned int mmPEER3_FB_OFFSET_LO__CI__VI = 0x14EC; -constexpr unsigned int mmPEER_REG_RANGE0 = 0x153E; -constexpr unsigned int mmPEER_REG_RANGE1 = 0x153F; -constexpr unsigned int mmPHY_AUX_CNTL__SI = 0x1953; -constexpr unsigned int mmPIPE0_ARBITRATION_CONTROL3__SI = 0x02FC; -constexpr unsigned int mmPIPE1_ARBITRATION_CONTROL3__SI = 0x0300; -constexpr unsigned int mmPIPE2_ARBITRATION_CONTROL3__SI = 0x0304; -constexpr unsigned int mmPIPE3_ARBITRATION_CONTROL3__SI = 0x0308; -constexpr unsigned int mmPIPE4_ARBITRATION_CONTROL3__SI = 0x030C; -constexpr unsigned int mmPIPE5_ARBITRATION_CONTROL3__SI = 0x0310; -constexpr unsigned int mmPIXCLK1_RESYNC_CNTL__SI = 0x0126; -constexpr unsigned int mmPIXCLK2_RESYNC_CNTL__SI = 0x0127; -constexpr unsigned int mmPLL_TEST_CNTL__SI = 0x0199; -constexpr unsigned int mmRAS_BCI_SIGNATURE0 = 0x339E; -constexpr unsigned int mmRAS_BCI_SIGNATURE1 = 0x339F; -constexpr unsigned int mmRAS_CB_SIGNATURE0 = 0x339D; -constexpr unsigned int mmRAS_DB_SIGNATURE0 = 0x338B; -constexpr unsigned int mmRAS_IA_SIGNATURE0 = 0x3397; -constexpr unsigned int mmRAS_IA_SIGNATURE1 = 0x3398; -constexpr unsigned int mmRAS_PA_SIGNATURE0 = 0x338C; -constexpr unsigned int mmRAS_SC_SIGNATURE0 = 0x338F; -constexpr unsigned int mmRAS_SC_SIGNATURE1 = 0x3390; -constexpr unsigned int mmRAS_SC_SIGNATURE2 = 0x3391; -constexpr unsigned int mmRAS_SC_SIGNATURE3 = 0x3392; -constexpr unsigned int mmRAS_SC_SIGNATURE4 = 0x3393; -constexpr unsigned int mmRAS_SC_SIGNATURE5 = 0x3394; -constexpr unsigned int mmRAS_SC_SIGNATURE6 = 0x3395; -constexpr unsigned int mmRAS_SC_SIGNATURE7 = 0x3396; -constexpr unsigned int mmRAS_SIGNATURE_CONTROL = 0x3380; -constexpr unsigned int mmRAS_SIGNATURE_MASK = 0x3381; -constexpr unsigned int mmRAS_SPI_SIGNATURE0 = 0x3399; -constexpr unsigned int mmRAS_SPI_SIGNATURE1 = 0x339A; -constexpr unsigned int mmRAS_SQ_SIGNATURE0 = 0x338E; -constexpr unsigned int mmRAS_SX_SIGNATURE0 = 0x3382; -constexpr unsigned int mmRAS_SX_SIGNATURE1 = 0x3383; -constexpr unsigned int mmRAS_SX_SIGNATURE2 = 0x3384; -constexpr unsigned int mmRAS_SX_SIGNATURE3 = 0x3385; -constexpr unsigned int mmRAS_TA_SIGNATURE0 = 0x339B; -constexpr unsigned int mmRAS_TD_SIGNATURE0 = 0x339C; -constexpr unsigned int mmRAS_VGT_SIGNATURE0 = 0x338D; -constexpr unsigned int mmRCU_MISC_CTRL__SI = 0x0043; -constexpr unsigned int mmRCU_UC_EVENTS__SI = 0x0045; -constexpr unsigned int mmRLC_AUTO_PG_CTRL__CI = 0x3115; -constexpr unsigned int mmRLC_AUTO_PG_CTRL__SI = 0x310D; -constexpr unsigned int mmRLC_CAPTURE_GPU_CLOCK_COUNT__CI = 0x30E6; -constexpr unsigned int mmRLC_CAPTURE_GPU_CLOCK_COUNT__SI = 0x30D0; -constexpr unsigned int mmRLC_CGCG_CGLS_CTRL__CI = 0x3109; -constexpr unsigned int mmRLC_CGCG_CGLS_CTRL__SI = 0x3101; -constexpr unsigned int mmRLC_CGCG_RAMP_CTRL__CI = 0x310A; -constexpr unsigned int mmRLC_CGCG_RAMP_CTRL__SI = 0x3102; -constexpr unsigned int mmRLC_CGTT_MGCG_OVERRIDE__CI = 0x3108; -constexpr unsigned int mmRLC_CGTT_MGCG_OVERRIDE__SI = 0x3100; -constexpr unsigned int mmRLC_CU_STATUS__CI = 0x310E; -constexpr unsigned int mmRLC_CU_STATUS__SI = 0x3106; -constexpr unsigned int mmRLC_DEBUG_SELECT__CI = 0x30C1; -constexpr unsigned int mmRLC_DEBUG_SELECT__SI = 0x30C9; -constexpr unsigned int mmRLC_DEBUG__CI = 0x30C2; -constexpr unsigned int mmRLC_DEBUG__SI = 0x30CA; -constexpr unsigned int mmRLC_DRIVER_CPDMA_STATUS__CI = 0x30DE; -constexpr unsigned int mmRLC_DRIVER_CPDMA_STATUS__SI = 0x30C7; -constexpr unsigned int mmRLC_DYN_PG_REQUEST__CI = 0x310C; -constexpr unsigned int mmRLC_DYN_PG_REQUEST__SI = 0x3104; -constexpr unsigned int mmRLC_DYN_PG_STATUS__CI = 0x310B; -constexpr unsigned int mmRLC_DYN_PG_STATUS__SI = 0x3103; -constexpr unsigned int mmRLC_GPM_CU_PD_TIMEOUT__CI = 0x312B; -constexpr unsigned int mmRLC_GPM_DEBUG_SELECT__CI = 0x30E0; -constexpr unsigned int mmRLC_GPM_DEBUG__CI = 0x30E1; -constexpr unsigned int mmRLC_GPM_GENERAL_0__CI = 0x3123; -constexpr unsigned int mmRLC_GPM_GENERAL_1__CI = 0x3124; -constexpr unsigned int mmRLC_GPM_GENERAL_2__CI = 0x3125; -constexpr unsigned int mmRLC_GPM_GENERAL_3__CI = 0x3126; -constexpr unsigned int mmRLC_GPM_GENERAL_4__CI = 0x3127; -constexpr unsigned int mmRLC_GPM_GENERAL_5__CI = 0x3128; -constexpr unsigned int mmRLC_GPM_GENERAL_6__CI = 0x3129; -constexpr unsigned int mmRLC_GPM_GENERAL_7__CI = 0x312A; -constexpr unsigned int mmRLC_GPM_LOG_ADDR__CI = 0x3136; -constexpr unsigned int mmRLC_GPM_LOG_CONT__CI = 0x3138; -constexpr unsigned int mmRLC_GPM_LOG_SIZE__CI = 0x3137; -constexpr unsigned int mmRLC_GPM_PERF_COUNT_0__CI = 0x312F; -constexpr unsigned int mmRLC_GPM_PERF_COUNT_1__CI = 0x3130; -constexpr unsigned int mmRLC_GPM_SCRATCH_ADDR__CI = 0x312C; -constexpr unsigned int mmRLC_GPM_SCRATCH_DATA__CI = 0x312D; -constexpr unsigned int mmRLC_GPM_STAT__CI = 0x3100; -constexpr unsigned int mmRLC_GPM_THREAD_ENABLE__CI = 0x3105; -constexpr unsigned int mmRLC_GPM_THREAD_PRIORITY__CI = 0x3104; -constexpr unsigned int mmRLC_GPM_UCODE_ADDR__CI = 0x30E2; -constexpr unsigned int mmRLC_GPM_UCODE_DATA__CI = 0x30E3; -constexpr unsigned int mmRLC_GPM_VMID_THREAD0__CI = 0x3106; -constexpr unsigned int mmRLC_GPM_VMID_THREAD1__CI = 0x3107; -constexpr unsigned int mmRLC_GPR_REG1__CI = 0x3139; -constexpr unsigned int mmRLC_GPR_REG2__CI = 0x313A; -constexpr unsigned int mmRLC_GPU_CLOCK_32_RES_SEL__CI = 0x3101; -constexpr unsigned int mmRLC_GPU_CLOCK_32_RES_SEL__SI = 0x30D4; -constexpr unsigned int mmRLC_GPU_CLOCK_32__CI = 0x3102; -constexpr unsigned int mmRLC_GPU_CLOCK_32__SI = 0x30D5; -constexpr unsigned int mmRLC_GPU_CLOCK_COUNT_LSB__CI = 0x30E4; -constexpr unsigned int mmRLC_GPU_CLOCK_COUNT_LSB__SI = 0x30CE; -constexpr unsigned int mmRLC_GPU_CLOCK_COUNT_MSB__CI = 0x30E5; -constexpr unsigned int mmRLC_GPU_CLOCK_COUNT_MSB__SI = 0x30CF; -constexpr unsigned int mmRLC_JUMP_TABLE_RESTORE__CI = 0x30DE; -constexpr unsigned int mmRLC_LB_ALWAYS_ACTIVE_CU_MASK__CI = 0x3110; -constexpr unsigned int mmRLC_LB_ALWAYS_ACTIVE_CU_MASK__SI = 0x3108; -constexpr unsigned int mmRLC_LB_CNTL__CI = 0x30D9; -constexpr unsigned int mmRLC_LB_CNTL__SI = 0x30C3; -constexpr unsigned int mmRLC_LB_CNTR_INIT__CI = 0x30DB; -constexpr unsigned int mmRLC_LB_CNTR_INIT__SI = 0x30C6; -constexpr unsigned int mmRLC_LB_CNTR_MAX__CI = 0x30D2; -constexpr unsigned int mmRLC_LB_CNTR_MAX__SI = 0x30C5; -constexpr unsigned int mmRLC_LB_INIT_CU_MASK__CI = 0x310F; -constexpr unsigned int mmRLC_LB_INIT_CU_MASK__SI = 0x3107; -constexpr unsigned int mmRLC_LB_PARAMS__CI = 0x3111; -constexpr unsigned int mmRLC_LB_PARAMS__SI = 0x3109; -constexpr unsigned int mmRLC_LOAD_BALANCE_CNTR__CI = 0x30DC; -constexpr unsigned int mmRLC_LOAD_BALANCE_CNTR__SI = 0x30F6; -constexpr unsigned int mmRLC_MAX_PG_CU__CI = 0x3114; -constexpr unsigned int mmRLC_MAX_PG_CU__SI = 0x310C; -constexpr unsigned int mmRLC_MC_CNTL__CI = 0x30C3; -constexpr unsigned int mmRLC_MC_CNTL__SI = 0x30D1; -constexpr unsigned int mmRLC_MEM_SLP_CNTL__CI = 0x30C6; -constexpr unsigned int mmRLC_MEM_SLP_CNTL__SI = 0x30D8; -constexpr unsigned int mmRLC_PERFCOUNTER0_HI__CI__VI = 0xD481; -constexpr unsigned int mmRLC_PERFCOUNTER0_HI__SI = 0x30DC; -constexpr unsigned int mmRLC_PERFCOUNTER0_LO__CI__VI = 0xD480; -constexpr unsigned int mmRLC_PERFCOUNTER0_LO__SI = 0x30DB; -constexpr unsigned int mmRLC_PERFCOUNTER0_SELECT__CI__VI = 0xDCC1; -constexpr unsigned int mmRLC_PERFCOUNTER0_SELECT__SI = 0x30DA; -constexpr unsigned int mmRLC_PERFCOUNTER1_HI__CI__VI = 0xD483; -constexpr unsigned int mmRLC_PERFCOUNTER1_HI__SI = 0x30DF; -constexpr unsigned int mmRLC_PERFCOUNTER1_LO__CI__VI = 0xD482; -constexpr unsigned int mmRLC_PERFCOUNTER1_LO__SI = 0x30DE; -constexpr unsigned int mmRLC_PERFCOUNTER1_SELECT__CI__VI = 0xDCC2; -constexpr unsigned int mmRLC_PERFCOUNTER1_SELECT__SI = 0x30DD; -constexpr unsigned int mmRLC_PERFMON_CNTL__CI__VI = 0xDCC0; -constexpr unsigned int mmRLC_PERFMON_CNTL__SI = 0x30D9; -constexpr unsigned int mmRLC_PG_ALWAYS_ON_CU_MASK__CI = 0x3113; -constexpr unsigned int mmRLC_PG_ALWAYS_ON_CU_MASK__SI = 0x310B; -constexpr unsigned int mmRLC_PG_CNTL__CI = 0x3103; -constexpr unsigned int mmRLC_PG_CNTL__SI = 0x30D7; -constexpr unsigned int mmRLC_PG_DELAY_2__CI = 0x30DF; -constexpr unsigned int mmRLC_PG_DELAY__CI = 0x310D; -constexpr unsigned int mmRLC_SAFE_MODE__CI = 0x313A; -constexpr unsigned int mmRLC_SAVE_AND_RESTORE_BASE__CI = 0x30DD; -constexpr unsigned int mmRLC_SAVE_AND_RESTORE_BASE__SI = 0x30C4; -constexpr unsigned int mmRLC_SERDES_CU_MASTER_BUSY__CI = 0x3121; -constexpr unsigned int mmRLC_SERDES_NONCU_MASTER_BUSY__CI = 0x3122; -constexpr unsigned int mmRLC_SERDES_RD_DATA_0__CI = 0x311A; -constexpr unsigned int mmRLC_SERDES_RD_DATA_0__SI = 0x3112; -constexpr unsigned int mmRLC_SERDES_RD_DATA_1__CI = 0x311B; -constexpr unsigned int mmRLC_SERDES_RD_DATA_1__SI = 0x3113; -constexpr unsigned int mmRLC_SERDES_RD_DATA_2__CI = 0x311C; -constexpr unsigned int mmRLC_SERDES_RD_DATA_2__SI = 0x3114; -constexpr unsigned int mmRLC_SERDES_RD_MASTER_INDEX__CI = 0x3119; -constexpr unsigned int mmRLC_SERDES_RD_MASTER_INDEX__SI = 0x3111; -constexpr unsigned int mmRLC_SERDES_WR_CTRL__CI = 0x311F; -constexpr unsigned int mmRLC_SERDES_WR_CTRL__SI = 0x3117; -constexpr unsigned int mmRLC_SERDES_WR_CU_MASTER_MASK__CI = 0x311D; -constexpr unsigned int mmRLC_SERDES_WR_DATA__CI = 0x3120; -constexpr unsigned int mmRLC_SERDES_WR_DATA__SI = 0x3118; -constexpr unsigned int mmRLC_SERDES_WR_NONCU_MASTER_MASK__CI = 0x311E; -constexpr unsigned int mmRLC_SMU_GRBM_REG_SAVE_CTRL__CI = 0x3116; -constexpr unsigned int mmRLC_SMU_GRBM_REG_SAVE_CTRL__SI = 0x310E; -constexpr unsigned int mmRLC_SMU_PG_CTRL__CI = 0x3117; -constexpr unsigned int mmRLC_SMU_PG_CTRL__SI = 0x310F; -constexpr unsigned int mmRLC_SMU_PG_WAKE_UP_CTRL__CI = 0x3118; -constexpr unsigned int mmRLC_SMU_PG_WAKE_UP_CTRL__SI = 0x3110; -constexpr unsigned int mmRLC_SOFT_RESET_GPU__CI = 0x30C5; -constexpr unsigned int mmRLC_SOFT_RESET_GPU__SI = 0x30D6; -constexpr unsigned int mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC8A; -constexpr unsigned int mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC88; -constexpr unsigned int mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC89; -constexpr unsigned int mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC87; -constexpr unsigned int mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC8B; -constexpr unsigned int mmRLC_SPM_DEBUG_SELECT__CI = 0x3134; -constexpr unsigned int mmRLC_SPM_DEBUG__CI = 0x3135; -constexpr unsigned int mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC8D; -constexpr unsigned int mmRLC_SPM_GLOBAL_MUXSEL_ADDR__CI__VI = 0xDC9B; -constexpr unsigned int mmRLC_SPM_GLOBAL_MUXSEL_DATA__CI__VI = 0xDC9C; -constexpr unsigned int mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC8E; -constexpr unsigned int mmRLC_SPM_INT_CNTL__CI = 0x3132; -constexpr unsigned int mmRLC_SPM_INT_STATUS__CI = 0x3133; -constexpr unsigned int mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC8C; -constexpr unsigned int mmRLC_SPM_PERFMON_CNTL__CI__VI = 0xDC80; -constexpr unsigned int mmRLC_SPM_PERFMON_RING_BASE_HI__CI__VI = 0xDC82; -constexpr unsigned int mmRLC_SPM_PERFMON_RING_BASE_LO__CI__VI = 0xDC81; -constexpr unsigned int mmRLC_SPM_PERFMON_RING_SIZE__CI__VI = 0xDC83; -constexpr unsigned int mmRLC_SPM_PERFMON_SEGMENT_SIZE__CI__VI = 0xDC84; -constexpr unsigned int mmRLC_SPM_RING_RDPTR__CI__VI = 0xDC9D; -constexpr unsigned int mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC90; -constexpr unsigned int mmRLC_SPM_SEGMENT_THRESHOLD__CI__VI = 0xDC9E; -constexpr unsigned int mmRLC_SPM_SE_MUXSEL_ADDR__CI__VI = 0xDC85; -constexpr unsigned int mmRLC_SPM_SE_MUXSEL_DATA__CI__VI = 0xDC86; -constexpr unsigned int mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC97; -constexpr unsigned int mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC98; -constexpr unsigned int mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC9A; -constexpr unsigned int mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC94; -constexpr unsigned int mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC92; -constexpr unsigned int mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC91; -constexpr unsigned int mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC93; -constexpr unsigned int mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY__CI = 0xDC99; -constexpr unsigned int mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC95; -constexpr unsigned int mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY__CI__VI = 0xDC96; -constexpr unsigned int mmRLC_SPM_VMID__CI = 0x3131; -constexpr unsigned int mmRLC_STATIC_PG_STATUS__CI = 0x312E; -constexpr unsigned int mmRLC_STAT__CI = 0x30C4; -constexpr unsigned int mmRLC_STAT__SI = 0x30D3; -constexpr unsigned int mmRLC_THREAD1_DELAY__CI = 0x3112; -constexpr unsigned int mmRLC_THREAD1_DELAY__SI = 0x310A; -constexpr unsigned int mmRLC_UCODE_CNTL__CI = 0x30E7; -constexpr unsigned int mmRLC_UCODE_CNTL__SI = 0x30D2; -constexpr unsigned int mmROM_CNTL__SI = 0x0580; -constexpr unsigned int mmROM_DATA__SI = 0x002B; -constexpr unsigned int mmROM_INDEX__SI = 0x002A; -constexpr unsigned int mmROM_SMC_IND_DATA__CI__VI = 0x0081; -constexpr unsigned int mmROM_SMC_IND_INDEX__CI__VI = 0x0080; -constexpr unsigned int mmROM_START__SI = 0x0585; -constexpr unsigned int mmROM_STATUS__SI = 0x0582; -constexpr unsigned int mmROM_SW_CNTL__SI = 0x0586; -constexpr unsigned int mmROM_SW_COMMAND__SI = 0x0588; -constexpr unsigned int mmROM_SW_DATA_10__SI = 0x0592; -constexpr unsigned int mmROM_SW_DATA_11__SI = 0x0593; -constexpr unsigned int mmROM_SW_DATA_12__SI = 0x0594; -constexpr unsigned int mmROM_SW_DATA_13__SI = 0x0595; -constexpr unsigned int mmROM_SW_DATA_14__SI = 0x0596; -constexpr unsigned int mmROM_SW_DATA_15__SI = 0x0597; -constexpr unsigned int mmROM_SW_DATA_16__SI = 0x0598; -constexpr unsigned int mmROM_SW_DATA_17__SI = 0x0599; -constexpr unsigned int mmROM_SW_DATA_18__SI = 0x059A; -constexpr unsigned int mmROM_SW_DATA_19__SI = 0x059B; -constexpr unsigned int mmROM_SW_DATA_1__SI = 0x0589; -constexpr unsigned int mmROM_SW_DATA_20__SI = 0x059C; -constexpr unsigned int mmROM_SW_DATA_21__SI = 0x059D; -constexpr unsigned int mmROM_SW_DATA_22__SI = 0x059E; -constexpr unsigned int mmROM_SW_DATA_23__SI = 0x059F; -constexpr unsigned int mmROM_SW_DATA_24__SI = 0x05A0; -constexpr unsigned int mmROM_SW_DATA_25__SI = 0x05A1; -constexpr unsigned int mmROM_SW_DATA_26__SI = 0x05A2; -constexpr unsigned int mmROM_SW_DATA_27__SI = 0x05A3; -constexpr unsigned int mmROM_SW_DATA_28__SI = 0x05A4; -constexpr unsigned int mmROM_SW_DATA_29__SI = 0x05A5; -constexpr unsigned int mmROM_SW_DATA_2__SI = 0x058A; -constexpr unsigned int mmROM_SW_DATA_30__SI = 0x05A6; -constexpr unsigned int mmROM_SW_DATA_31__SI = 0x05A7; -constexpr unsigned int mmROM_SW_DATA_32__SI = 0x05A8; -constexpr unsigned int mmROM_SW_DATA_33__SI = 0x05A9; -constexpr unsigned int mmROM_SW_DATA_34__SI = 0x05AA; -constexpr unsigned int mmROM_SW_DATA_35__SI = 0x05AB; -constexpr unsigned int mmROM_SW_DATA_36__SI = 0x05AC; -constexpr unsigned int mmROM_SW_DATA_37__SI = 0x05AD; -constexpr unsigned int mmROM_SW_DATA_38__SI = 0x05AE; -constexpr unsigned int mmROM_SW_DATA_39__SI = 0x05AF; -constexpr unsigned int mmROM_SW_DATA_3__SI = 0x058B; -constexpr unsigned int mmROM_SW_DATA_40__SI = 0x05B0; -constexpr unsigned int mmROM_SW_DATA_41__SI = 0x05B1; -constexpr unsigned int mmROM_SW_DATA_42__SI = 0x05B2; -constexpr unsigned int mmROM_SW_DATA_43__SI = 0x05B3; -constexpr unsigned int mmROM_SW_DATA_44__SI = 0x05B4; -constexpr unsigned int mmROM_SW_DATA_45__SI = 0x05B5; -constexpr unsigned int mmROM_SW_DATA_46__SI = 0x05B6; -constexpr unsigned int mmROM_SW_DATA_47__SI = 0x05B7; -constexpr unsigned int mmROM_SW_DATA_48__SI = 0x05B8; -constexpr unsigned int mmROM_SW_DATA_49__SI = 0x05B9; -constexpr unsigned int mmROM_SW_DATA_4__SI = 0x058C; -constexpr unsigned int mmROM_SW_DATA_50__SI = 0x05BA; -constexpr unsigned int mmROM_SW_DATA_51__SI = 0x05BB; -constexpr unsigned int mmROM_SW_DATA_52__SI = 0x05BC; -constexpr unsigned int mmROM_SW_DATA_53__SI = 0x05BD; -constexpr unsigned int mmROM_SW_DATA_54__SI = 0x05BE; -constexpr unsigned int mmROM_SW_DATA_55__SI = 0x05BF; -constexpr unsigned int mmROM_SW_DATA_56__SI = 0x05C0; -constexpr unsigned int mmROM_SW_DATA_57__SI = 0x05C1; -constexpr unsigned int mmROM_SW_DATA_58__SI = 0x05C2; -constexpr unsigned int mmROM_SW_DATA_59__SI = 0x05C3; -constexpr unsigned int mmROM_SW_DATA_5__SI = 0x058D; -constexpr unsigned int mmROM_SW_DATA_60__SI = 0x05C4; -constexpr unsigned int mmROM_SW_DATA_61__SI = 0x05C5; -constexpr unsigned int mmROM_SW_DATA_62__SI = 0x05C6; -constexpr unsigned int mmROM_SW_DATA_63__SI = 0x05C7; -constexpr unsigned int mmROM_SW_DATA_64__SI = 0x05C8; -constexpr unsigned int mmROM_SW_DATA_6__SI = 0x058E; -constexpr unsigned int mmROM_SW_DATA_7__SI = 0x058F; -constexpr unsigned int mmROM_SW_DATA_8__SI = 0x0590; -constexpr unsigned int mmROM_SW_DATA_9__SI = 0x0591; -constexpr unsigned int mmROM_SW_STATUS__SI = 0x0587; -constexpr unsigned int mmSCL0_EXT_OVERSCAN_LEFT_RIGHT__SI__VI = 0x1B5E; -constexpr unsigned int mmSCL0_EXT_OVERSCAN_TOP_BOTTOM__SI__VI = 0x1B5F; -constexpr unsigned int mmSCL0_SCL_ALU_CONTROL__SI__VI = 0x1B54; -constexpr unsigned int mmSCL0_SCL_AUTOMATIC_MODE_CONTROL__SI__VI = 0x1B47; -constexpr unsigned int mmSCL0_SCL_BYPASS_CONTROL__SI__VI = 0x1B45; -constexpr unsigned int mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS__SI__VI = 0x1B55; -constexpr unsigned int mmSCL0_SCL_COEF_RAM_SELECT__SI__VI = 0x1B40; -constexpr unsigned int mmSCL0_SCL_COEF_RAM_TAP_DATA__SI__VI = 0x1B41; -constexpr unsigned int mmSCL0_SCL_CONTROL__SI__VI = 0x1B44; -constexpr unsigned int mmSCL0_SCL_DEBUG__SI__VI = 0x1B6A; -constexpr unsigned int mmSCL0_SCL_F_SHARP_CONTROL__SI__VI = 0x1B53; -constexpr unsigned int mmSCL0_SCL_HORZ_FILTER_CONTROL__SI = 0x1B4A; -constexpr unsigned int mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SI = 0x1B4B; -constexpr unsigned int mmSCL0_SCL_MANUAL_REPLICATE_CONTROL__SI__VI = 0x1B46; -constexpr unsigned int mmSCL0_SCL_MODE_CHANGE_DET1__SI__VI = 0x1B60; -constexpr unsigned int mmSCL0_SCL_MODE_CHANGE_DET2__SI__VI = 0x1B61; -constexpr unsigned int mmSCL0_SCL_MODE_CHANGE_DET3__SI__VI = 0x1B62; -constexpr unsigned int mmSCL0_SCL_MODE_CHANGE_MASK__SI__VI = 0x1B63; -constexpr unsigned int mmSCL0_SCL_TAP_CONTROL__SI__VI = 0x1B43; -constexpr unsigned int mmSCL0_SCL_TEST_DEBUG_DATA__SI__VI = 0x1B6C; -constexpr unsigned int mmSCL0_SCL_TEST_DEBUG_INDEX__SI__VI = 0x1B6B; -constexpr unsigned int mmSCL0_SCL_UPDATE__SI__VI = 0x1B51; -constexpr unsigned int mmSCL0_SCL_VERT_FILTER_CONTROL__SI = 0x1B4E; -constexpr unsigned int mmSCL0_SCL_VERT_FILTER_INIT_BOT__SI = 0x1B57; -constexpr unsigned int mmSCL0_SCL_VERT_FILTER_INIT__SI = 0x1B50; -constexpr unsigned int mmSCL0_SCL_VERT_FILTER_SCALE_RATIO__SI = 0x1B4F; -constexpr unsigned int mmSCL0_VIEWPORT_SIZE__SI__VI = 0x1B5D; -constexpr unsigned int mmSCL0_VIEWPORT_START__SI__VI = 0x1B5C; -constexpr unsigned int mmSCL1_EXT_OVERSCAN_LEFT_RIGHT__SI = 0x1E5E; -constexpr unsigned int mmSCL1_EXT_OVERSCAN_TOP_BOTTOM__SI = 0x1E5F; -constexpr unsigned int mmSCL1_SCL_ALU_CONTROL__SI = 0x1E54; -constexpr unsigned int mmSCL1_SCL_AUTOMATIC_MODE_CONTROL__SI = 0x1E47; -constexpr unsigned int mmSCL1_SCL_BYPASS_CONTROL__SI = 0x1E45; -constexpr unsigned int mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS__SI = 0x1E55; -constexpr unsigned int mmSCL1_SCL_COEF_RAM_SELECT__SI = 0x1E40; -constexpr unsigned int mmSCL1_SCL_COEF_RAM_TAP_DATA__SI = 0x1E41; -constexpr unsigned int mmSCL1_SCL_CONTROL__SI = 0x1E44; -constexpr unsigned int mmSCL1_SCL_DEBUG__SI = 0x1E6A; -constexpr unsigned int mmSCL1_SCL_F_SHARP_CONTROL__SI = 0x1E53; -constexpr unsigned int mmSCL1_SCL_HORZ_FILTER_CONTROL__SI = 0x1E4A; -constexpr unsigned int mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SI = 0x1E4B; -constexpr unsigned int mmSCL1_SCL_MANUAL_REPLICATE_CONTROL__SI = 0x1E46; -constexpr unsigned int mmSCL1_SCL_MODE_CHANGE_DET1__SI = 0x1E60; -constexpr unsigned int mmSCL1_SCL_MODE_CHANGE_DET2__SI = 0x1E61; -constexpr unsigned int mmSCL1_SCL_MODE_CHANGE_DET3__SI = 0x1E62; -constexpr unsigned int mmSCL1_SCL_MODE_CHANGE_MASK__SI = 0x1E63; -constexpr unsigned int mmSCL1_SCL_TAP_CONTROL__SI = 0x1E43; -constexpr unsigned int mmSCL1_SCL_TEST_DEBUG_DATA__SI = 0x1E6C; -constexpr unsigned int mmSCL1_SCL_TEST_DEBUG_INDEX__SI = 0x1E6B; -constexpr unsigned int mmSCL1_SCL_UPDATE__SI = 0x1E51; -constexpr unsigned int mmSCL1_SCL_VERT_FILTER_CONTROL__SI = 0x1E4E; -constexpr unsigned int mmSCL1_SCL_VERT_FILTER_INIT_BOT__SI = 0x1E57; -constexpr unsigned int mmSCL1_SCL_VERT_FILTER_INIT__SI = 0x1E50; -constexpr unsigned int mmSCL1_SCL_VERT_FILTER_SCALE_RATIO__SI = 0x1E4F; -constexpr unsigned int mmSCL1_VIEWPORT_SIZE__SI = 0x1E5D; -constexpr unsigned int mmSCL1_VIEWPORT_START__SI = 0x1E5C; -constexpr unsigned int mmSCL2_EXT_OVERSCAN_LEFT_RIGHT__SI = 0x415E; -constexpr unsigned int mmSCL2_EXT_OVERSCAN_TOP_BOTTOM__SI = 0x415F; -constexpr unsigned int mmSCL2_SCL_ALU_CONTROL__SI = 0x4154; -constexpr unsigned int mmSCL2_SCL_AUTOMATIC_MODE_CONTROL__SI = 0x4147; -constexpr unsigned int mmSCL2_SCL_BYPASS_CONTROL__SI = 0x4145; -constexpr unsigned int mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS__SI = 0x4155; -constexpr unsigned int mmSCL2_SCL_COEF_RAM_SELECT__SI = 0x4140; -constexpr unsigned int mmSCL2_SCL_COEF_RAM_TAP_DATA__SI = 0x4141; -constexpr unsigned int mmSCL2_SCL_CONTROL__SI = 0x4144; -constexpr unsigned int mmSCL2_SCL_DEBUG__SI = 0x416A; -constexpr unsigned int mmSCL2_SCL_F_SHARP_CONTROL__SI = 0x4153; -constexpr unsigned int mmSCL2_SCL_HORZ_FILTER_CONTROL__SI = 0x414A; -constexpr unsigned int mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SI = 0x414B; -constexpr unsigned int mmSCL2_SCL_MANUAL_REPLICATE_CONTROL__SI = 0x4146; -constexpr unsigned int mmSCL2_SCL_MODE_CHANGE_DET1__SI = 0x4160; -constexpr unsigned int mmSCL2_SCL_MODE_CHANGE_DET2__SI = 0x4161; -constexpr unsigned int mmSCL2_SCL_MODE_CHANGE_DET3__SI = 0x4162; -constexpr unsigned int mmSCL2_SCL_MODE_CHANGE_MASK__SI = 0x4163; -constexpr unsigned int mmSCL2_SCL_TAP_CONTROL__SI = 0x4143; -constexpr unsigned int mmSCL2_SCL_TEST_DEBUG_DATA__SI = 0x416C; -constexpr unsigned int mmSCL2_SCL_TEST_DEBUG_INDEX__SI = 0x416B; -constexpr unsigned int mmSCL2_SCL_UPDATE__SI = 0x4151; -constexpr unsigned int mmSCL2_SCL_VERT_FILTER_CONTROL__SI = 0x414E; -constexpr unsigned int mmSCL2_SCL_VERT_FILTER_INIT_BOT__SI = 0x4157; -constexpr unsigned int mmSCL2_SCL_VERT_FILTER_INIT__SI = 0x4150; -constexpr unsigned int mmSCL2_SCL_VERT_FILTER_SCALE_RATIO__SI = 0x414F; -constexpr unsigned int mmSCL2_VIEWPORT_SIZE__SI = 0x415D; -constexpr unsigned int mmSCL2_VIEWPORT_START__SI = 0x415C; -constexpr unsigned int mmSCL3_EXT_OVERSCAN_LEFT_RIGHT__SI = 0x445E; -constexpr unsigned int mmSCL3_EXT_OVERSCAN_TOP_BOTTOM__SI = 0x445F; -constexpr unsigned int mmSCL3_SCL_ALU_CONTROL__SI = 0x4454; -constexpr unsigned int mmSCL3_SCL_AUTOMATIC_MODE_CONTROL__SI = 0x4447; -constexpr unsigned int mmSCL3_SCL_BYPASS_CONTROL__SI = 0x4445; -constexpr unsigned int mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS__SI = 0x4455; -constexpr unsigned int mmSCL3_SCL_COEF_RAM_SELECT__SI = 0x4440; -constexpr unsigned int mmSCL3_SCL_COEF_RAM_TAP_DATA__SI = 0x4441; -constexpr unsigned int mmSCL3_SCL_CONTROL__SI = 0x4444; -constexpr unsigned int mmSCL3_SCL_DEBUG__SI = 0x446A; -constexpr unsigned int mmSCL3_SCL_F_SHARP_CONTROL__SI = 0x4453; -constexpr unsigned int mmSCL3_SCL_HORZ_FILTER_CONTROL__SI = 0x444A; -constexpr unsigned int mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SI = 0x444B; -constexpr unsigned int mmSCL3_SCL_MANUAL_REPLICATE_CONTROL__SI = 0x4446; -constexpr unsigned int mmSCL3_SCL_MODE_CHANGE_DET1__SI = 0x4460; -constexpr unsigned int mmSCL3_SCL_MODE_CHANGE_DET2__SI = 0x4461; -constexpr unsigned int mmSCL3_SCL_MODE_CHANGE_DET3__SI = 0x4462; -constexpr unsigned int mmSCL3_SCL_MODE_CHANGE_MASK__SI = 0x4463; -constexpr unsigned int mmSCL3_SCL_TAP_CONTROL__SI = 0x4443; -constexpr unsigned int mmSCL3_SCL_TEST_DEBUG_DATA__SI = 0x446C; -constexpr unsigned int mmSCL3_SCL_TEST_DEBUG_INDEX__SI = 0x446B; -constexpr unsigned int mmSCL3_SCL_UPDATE__SI = 0x4451; -constexpr unsigned int mmSCL3_SCL_VERT_FILTER_CONTROL__SI = 0x444E; -constexpr unsigned int mmSCL3_SCL_VERT_FILTER_INIT_BOT__SI = 0x4457; -constexpr unsigned int mmSCL3_SCL_VERT_FILTER_INIT__SI = 0x4450; -constexpr unsigned int mmSCL3_SCL_VERT_FILTER_SCALE_RATIO__SI = 0x444F; -constexpr unsigned int mmSCL3_VIEWPORT_SIZE__SI = 0x445D; -constexpr unsigned int mmSCL3_VIEWPORT_START__SI = 0x445C; -constexpr unsigned int mmSCL4_EXT_OVERSCAN_LEFT_RIGHT__SI = 0x475E; -constexpr unsigned int mmSCL4_EXT_OVERSCAN_TOP_BOTTOM__SI = 0x475F; -constexpr unsigned int mmSCL4_SCL_ALU_CONTROL__SI = 0x4754; -constexpr unsigned int mmSCL4_SCL_AUTOMATIC_MODE_CONTROL__SI = 0x4747; -constexpr unsigned int mmSCL4_SCL_BYPASS_CONTROL__SI = 0x4745; -constexpr unsigned int mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS__SI = 0x4755; -constexpr unsigned int mmSCL4_SCL_COEF_RAM_SELECT__SI = 0x4740; -constexpr unsigned int mmSCL4_SCL_COEF_RAM_TAP_DATA__SI = 0x4741; -constexpr unsigned int mmSCL4_SCL_CONTROL__SI = 0x4744; -constexpr unsigned int mmSCL4_SCL_DEBUG__SI = 0x476A; -constexpr unsigned int mmSCL4_SCL_F_SHARP_CONTROL__SI = 0x4753; -constexpr unsigned int mmSCL4_SCL_HORZ_FILTER_CONTROL__SI = 0x474A; -constexpr unsigned int mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO__SI = 0x474B; -constexpr unsigned int mmSCL4_SCL_MANUAL_REPLICATE_CONTROL__SI = 0x4746; -constexpr unsigned int mmSCL4_SCL_MODE_CHANGE_DET1__SI = 0x4760; -constexpr unsigned int mmSCL4_SCL_MODE_CHANGE_DET2__SI = 0x4761; -constexpr unsigned int mmSCL4_SCL_MODE_CHANGE_DET3__SI = 0x4762; -constexpr unsigned int mmSCL4_SCL_MODE_CHANGE_MASK__SI = 0x4763; -constexpr unsigned int mmSCL4_SCL_TAP_CONTROL__SI = 0x4743; -constexpr unsigned int mmSCL4_SCL_TEST_DEBUG_DATA__SI = 0x476C; -constexpr unsigned int mmSCL4_SCL_TEST_DEBUG_INDEX__SI = 0x476B; -constexpr unsigned int mmSCL4_SCL_UPDATE__SI = 0x4751; -constexpr unsigned int mmSCL4_SCL_VERT_FILTER_CONTROL__SI = 0x474E; -constexpr unsigned int mmSCL4_SCL_VERT_FILTER_INIT_BOT__SI = 0x4757; -constexpr unsigned int mmSCL4_SCL_VERT_FILTER_INIT__SI = 0x4750; -constexpr unsigned int mmSCL4_SCL_VERT_FILTER_SCALE_RATIO__SI = 0x474F; -constexpr unsigned int mmSCL4_VIEWPORT_SIZE__SI = 0x475D; -constexpr unsigned int mmSCL4_VIEWPORT_START__SI = 0x475C; -constexpr unsigned int mmSCL5_EXT_OVERSCAN_LEFT_RIGHT__SI = 0x4A5E; -constexpr unsigned int mmSCL5_EXT_OVERSCAN_TOP_BOTTOM__SI = 0x4A5F; -constexpr unsigned int mmSCL5_SCL_ALU_CONTROL__SI = 0x4A54; -constexpr unsigned int mmSCL5_SCL_AUTOMATIC_MODE_CONTROL__SI = 0x4A47; -constexpr unsigned int mmSCL5_SCL_BYPASS_CONTROL__SI = 0x4A45; -constexpr unsigned int mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS__SI = 0x4A55; -constexpr unsigned int mmSCL5_SCL_COEF_RAM_SELECT__SI = 0x4A40; -constexpr unsigned int mmSCL5_SCL_COEF_RAM_TAP_DATA__SI = 0x4A41; -constexpr unsigned int mmSCL5_SCL_CONTROL__SI = 0x4A44; -constexpr unsigned int mmSCL5_SCL_DEBUG__SI = 0x4A6A; -constexpr unsigned int mmSCL5_SCL_F_SHARP_CONTROL__SI = 0x4A53; -constexpr unsigned int mmSCL5_SCL_HORZ_FILTER_CONTROL__SI = 0x4A4A; -constexpr unsigned int mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO__SI = 0x4A4B; -constexpr unsigned int mmSCL5_SCL_MANUAL_REPLICATE_CONTROL__SI = 0x4A46; -constexpr unsigned int mmSCL5_SCL_MODE_CHANGE_DET1__SI = 0x4A60; -constexpr unsigned int mmSCL5_SCL_MODE_CHANGE_DET2__SI = 0x4A61; -constexpr unsigned int mmSCL5_SCL_MODE_CHANGE_DET3__SI = 0x4A62; -constexpr unsigned int mmSCL5_SCL_MODE_CHANGE_MASK__SI = 0x4A63; -constexpr unsigned int mmSCL5_SCL_TAP_CONTROL__SI = 0x4A43; -constexpr unsigned int mmSCL5_SCL_TEST_DEBUG_DATA__SI = 0x4A6C; -constexpr unsigned int mmSCL5_SCL_TEST_DEBUG_INDEX__SI = 0x4A6B; -constexpr unsigned int mmSCL5_SCL_UPDATE__SI = 0x4A51; -constexpr unsigned int mmSCL5_SCL_VERT_FILTER_CONTROL__SI = 0x4A4E; -constexpr unsigned int mmSCL5_SCL_VERT_FILTER_INIT_BOT__SI = 0x4A57; -constexpr unsigned int mmSCL5_SCL_VERT_FILTER_INIT__SI = 0x4A50; -constexpr unsigned int mmSCL5_SCL_VERT_FILTER_SCALE_RATIO__SI = 0x4A4F; -constexpr unsigned int mmSCL5_VIEWPORT_SIZE__SI = 0x4A5D; -constexpr unsigned int mmSCL5_VIEWPORT_START__SI = 0x4A5C; -constexpr unsigned int mmSCLK_CGTT_BLK_CTRL_REG__SI = 0x0129; -constexpr unsigned int mmSCLK_PWRMGT_CNTL__SI = 0x01E2; -constexpr unsigned int mmSCL_ALU_CONTROL__SI__VI = 0x1B54; -constexpr unsigned int mmSCL_AUTOMATIC_MODE_CONTROL__SI__VI = 0x1B47; -constexpr unsigned int mmSCL_BYPASS_CONTROL__SI__VI = 0x1B45; -constexpr unsigned int mmSCL_COEF_RAM_CONFLICT_STATUS__SI__VI = 0x1B55; -constexpr unsigned int mmSCL_COEF_RAM_SELECT__SI__VI = 0x1B40; -constexpr unsigned int mmSCL_COEF_RAM_TAP_DATA__SI__VI = 0x1B41; -constexpr unsigned int mmSCL_CONTROL__SI__VI = 0x1B44; -constexpr unsigned int mmSCL_DEBUG__SI__VI = 0x1B6A; -constexpr unsigned int mmSCL_F_SHARP_CONTROL__SI__VI = 0x1B53; -constexpr unsigned int mmSCL_HORZ_FILTER_CONTROL__SI = 0x1B4A; -constexpr unsigned int mmSCL_HORZ_FILTER_SCALE_RATIO__SI = 0x1B4B; -constexpr unsigned int mmSCL_MANUAL_REPLICATE_CONTROL__SI__VI = 0x1B46; -constexpr unsigned int mmSCL_MODE_CHANGE_DET1__SI__VI = 0x1B60; -constexpr unsigned int mmSCL_MODE_CHANGE_DET2__SI__VI = 0x1B61; -constexpr unsigned int mmSCL_MODE_CHANGE_DET3__SI__VI = 0x1B62; -constexpr unsigned int mmSCL_MODE_CHANGE_MASK__SI__VI = 0x1B63; -constexpr unsigned int mmSCL_TAP_CONTROL__SI__VI = 0x1B43; -constexpr unsigned int mmSCL_TEST_DEBUG_DATA__SI__VI = 0x1B6C; -constexpr unsigned int mmSCL_TEST_DEBUG_INDEX__SI__VI = 0x1B6B; -constexpr unsigned int mmSCL_UPDATE__SI__VI = 0x1B51; -constexpr unsigned int mmSCL_VERT_FILTER_CONTROL__SI = 0x1B4E; -constexpr unsigned int mmSCL_VERT_FILTER_INIT_BOT__SI = 0x1B57; -constexpr unsigned int mmSCL_VERT_FILTER_INIT__SI = 0x1B50; -constexpr unsigned int mmSCL_VERT_FILTER_SCALE_RATIO__SI = 0x1B4F; -constexpr unsigned int mmSCRATCH_ADDR__CI__VI = 0xC051; -constexpr unsigned int mmSCRATCH_ADDR__SI = 0x2151; -constexpr unsigned int mmSCRATCH_REG0__CI__VI = 0xC040; -constexpr unsigned int mmSCRATCH_REG0__SI = 0x2140; -constexpr unsigned int mmSCRATCH_REG1__CI__VI = 0xC041; -constexpr unsigned int mmSCRATCH_REG1__SI = 0x2141; -constexpr unsigned int mmSCRATCH_REG2__CI__VI = 0xC042; -constexpr unsigned int mmSCRATCH_REG2__SI = 0x2142; -constexpr unsigned int mmSCRATCH_REG3__CI__VI = 0xC043; -constexpr unsigned int mmSCRATCH_REG3__SI = 0x2143; -constexpr unsigned int mmSCRATCH_REG4__CI__VI = 0xC044; -constexpr unsigned int mmSCRATCH_REG4__SI = 0x2144; -constexpr unsigned int mmSCRATCH_REG5__CI__VI = 0xC045; -constexpr unsigned int mmSCRATCH_REG5__SI = 0x2145; -constexpr unsigned int mmSCRATCH_REG6__CI__VI = 0xC046; -constexpr unsigned int mmSCRATCH_REG6__SI = 0x2146; -constexpr unsigned int mmSCRATCH_REG7__CI__VI = 0xC047; -constexpr unsigned int mmSCRATCH_REG7__SI = 0x2147; -constexpr unsigned int mmSCRATCH_UMSK__CI__VI = 0xC050; -constexpr unsigned int mmSCRATCH_UMSK__SI = 0x2150; -constexpr unsigned int mmSDMA0_CHICKEN_BITS__CI__VI = 0x3405; -constexpr unsigned int mmSDMA0_CLK_CTRL__CI__VI = 0x3403; -constexpr unsigned int mmSDMA0_CNTL__CI__VI = 0x3404; -constexpr unsigned int mmSDMA0_F32_CNTL__CI__VI = 0x3412; -constexpr unsigned int mmSDMA0_FREEZE__CI__VI = 0x3413; -constexpr unsigned int mmSDMA0_GFX_APE1_CNTL__CI__VI = 0x34A8; -constexpr unsigned int mmSDMA0_GFX_CONTEXT_CNTL__CI__VI = 0x3493; -constexpr unsigned int mmSDMA0_GFX_CONTEXT_STATUS__CI__VI = 0x3491; -constexpr unsigned int mmSDMA0_GFX_IB_BASE_HI__CI__VI = 0x348E; -constexpr unsigned int mmSDMA0_GFX_IB_BASE_LO__CI__VI = 0x348D; -constexpr unsigned int mmSDMA0_GFX_IB_CNTL__CI__VI = 0x348A; -constexpr unsigned int mmSDMA0_GFX_IB_OFFSET__CI__VI = 0x348C; -constexpr unsigned int mmSDMA0_GFX_IB_RPTR__CI__VI = 0x348B; -constexpr unsigned int mmSDMA0_GFX_IB_SIZE__CI__VI = 0x348F; -constexpr unsigned int mmSDMA0_GFX_RB_BASE_HI__CI__VI = 0x3482; -constexpr unsigned int mmSDMA0_GFX_RB_BASE__CI__VI = 0x3481; -constexpr unsigned int mmSDMA0_GFX_RB_CNTL__CI__VI = 0x3480; -constexpr unsigned int mmSDMA0_GFX_RB_RPTR_ADDR_HI__CI__VI = 0x3488; -constexpr unsigned int mmSDMA0_GFX_RB_RPTR_ADDR_LO__CI__VI = 0x3489; -constexpr unsigned int mmSDMA0_GFX_RB_RPTR__CI__VI = 0x3483; -constexpr unsigned int mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI = 0x3486; -constexpr unsigned int mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI = 0x3487; -constexpr unsigned int mmSDMA0_GFX_RB_WPTR_POLL_CNTL__CI__VI = 0x3485; -constexpr unsigned int mmSDMA0_GFX_RB_WPTR__CI__VI = 0x3484; -constexpr unsigned int mmSDMA0_GFX_SKIP_CNTL__CI__VI = 0x3490; -constexpr unsigned int mmSDMA0_GFX_VIRTUAL_ADDR__CI__VI = 0x34A7; -constexpr unsigned int mmSDMA0_HASH__CI__VI = 0x3407; -constexpr unsigned int mmSDMA0_IB_OFFSET_FETCH__CI__VI = 0x340B; -constexpr unsigned int mmSDMA0_PERFCOUNTER0_RESULT__CI = 0x3410; -constexpr unsigned int mmSDMA0_PERFCOUNTER1_RESULT__CI = 0x3411; -constexpr unsigned int mmSDMA0_PERFMON_CNTL__CI = 0x340F; -constexpr unsigned int mmSDMA0_PHASE0_QUANTUM__CI__VI = 0x3414; -constexpr unsigned int mmSDMA0_PHASE1_QUANTUM__CI__VI = 0x3415; -constexpr unsigned int mmSDMA0_POWER_CNTL__CI__VI = 0x3402; -constexpr unsigned int mmSDMA0_PROGRAM__CI__VI = 0x340C; -constexpr unsigned int mmSDMA0_RB_RPTR_FETCH__CI__VI = 0x340A; -constexpr unsigned int mmSDMA0_RLC0_APE1_CNTL__CI__VI = 0x3528; -constexpr unsigned int mmSDMA0_RLC0_CONTEXT_STATUS__CI__VI = 0x3511; -constexpr unsigned int mmSDMA0_RLC0_DOORBELL_LOG__CI__VI = 0x3529; -constexpr unsigned int mmSDMA0_RLC0_DOORBELL__CI__VI = 0x3512; -constexpr unsigned int mmSDMA0_RLC0_IB_BASE_HI__CI__VI = 0x350E; -constexpr unsigned int mmSDMA0_RLC0_IB_BASE_LO__CI__VI = 0x350D; -constexpr unsigned int mmSDMA0_RLC0_IB_CNTL__CI__VI = 0x350A; -constexpr unsigned int mmSDMA0_RLC0_IB_OFFSET__CI__VI = 0x350C; -constexpr unsigned int mmSDMA0_RLC0_IB_RPTR__CI__VI = 0x350B; -constexpr unsigned int mmSDMA0_RLC0_IB_SIZE__CI__VI = 0x350F; -constexpr unsigned int mmSDMA0_RLC0_RB_BASE_HI__CI__VI = 0x3502; -constexpr unsigned int mmSDMA0_RLC0_RB_BASE__CI__VI = 0x3501; -constexpr unsigned int mmSDMA0_RLC0_RB_CNTL__CI__VI = 0x3500; -constexpr unsigned int mmSDMA0_RLC0_RB_RPTR_ADDR_HI__CI__VI = 0x3508; -constexpr unsigned int mmSDMA0_RLC0_RB_RPTR_ADDR_LO__CI__VI = 0x3509; -constexpr unsigned int mmSDMA0_RLC0_RB_RPTR__CI__VI = 0x3503; -constexpr unsigned int mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI = 0x3506; -constexpr unsigned int mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI = 0x3507; -constexpr unsigned int mmSDMA0_RLC0_RB_WPTR_POLL_CNTL__CI__VI = 0x3505; -constexpr unsigned int mmSDMA0_RLC0_RB_WPTR__CI__VI = 0x3504; -constexpr unsigned int mmSDMA0_RLC0_SKIP_CNTL__CI__VI = 0x3510; -constexpr unsigned int mmSDMA0_RLC0_VIRTUAL_ADDR__CI__VI = 0x3527; -constexpr unsigned int mmSDMA0_RLC1_APE1_CNTL__CI__VI = 0x35A8; -constexpr unsigned int mmSDMA0_RLC1_CONTEXT_STATUS__CI__VI = 0x3591; -constexpr unsigned int mmSDMA0_RLC1_DOORBELL_LOG__CI__VI = 0x35A9; -constexpr unsigned int mmSDMA0_RLC1_DOORBELL__CI__VI = 0x3592; -constexpr unsigned int mmSDMA0_RLC1_IB_BASE_HI__CI__VI = 0x358E; -constexpr unsigned int mmSDMA0_RLC1_IB_BASE_LO__CI__VI = 0x358D; -constexpr unsigned int mmSDMA0_RLC1_IB_CNTL__CI__VI = 0x358A; -constexpr unsigned int mmSDMA0_RLC1_IB_OFFSET__CI__VI = 0x358C; -constexpr unsigned int mmSDMA0_RLC1_IB_RPTR__CI__VI = 0x358B; -constexpr unsigned int mmSDMA0_RLC1_IB_SIZE__CI__VI = 0x358F; -constexpr unsigned int mmSDMA0_RLC1_RB_BASE_HI__CI__VI = 0x3582; -constexpr unsigned int mmSDMA0_RLC1_RB_BASE__CI__VI = 0x3581; -constexpr unsigned int mmSDMA0_RLC1_RB_CNTL__CI__VI = 0x3580; -constexpr unsigned int mmSDMA0_RLC1_RB_RPTR_ADDR_HI__CI__VI = 0x3588; -constexpr unsigned int mmSDMA0_RLC1_RB_RPTR_ADDR_LO__CI__VI = 0x3589; -constexpr unsigned int mmSDMA0_RLC1_RB_RPTR__CI__VI = 0x3583; -constexpr unsigned int mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI = 0x3586; -constexpr unsigned int mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI = 0x3587; -constexpr unsigned int mmSDMA0_RLC1_RB_WPTR_POLL_CNTL__CI__VI = 0x3585; -constexpr unsigned int mmSDMA0_RLC1_RB_WPTR__CI__VI = 0x3584; -constexpr unsigned int mmSDMA0_RLC1_SKIP_CNTL__CI__VI = 0x3590; -constexpr unsigned int mmSDMA0_RLC1_VIRTUAL_ADDR__CI__VI = 0x35A7; -constexpr unsigned int mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL__CI = 0x3408; -constexpr unsigned int mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI = 0x3409; -constexpr unsigned int mmSDMA0_STATUS1_REG__CI__VI = 0x340E; -constexpr unsigned int mmSDMA0_STATUS_REG__CI__VI = 0x340D; -constexpr unsigned int mmSDMA0_TILING_CONFIG__CI__VI = 0x3406; -constexpr unsigned int mmSDMA0_UCODE_ADDR__CI__VI = 0x3400; -constexpr unsigned int mmSDMA0_UCODE_DATA__CI__VI = 0x3401; -constexpr unsigned int mmSDMA1_CHICKEN_BITS__CI__VI = 0x3605; -constexpr unsigned int mmSDMA1_CLK_CTRL__CI__VI = 0x3603; -constexpr unsigned int mmSDMA1_CNTL__CI__VI = 0x3604; -constexpr unsigned int mmSDMA1_CONFIG__CI__VI = 0x0F92; -constexpr unsigned int mmSDMA1_F32_CNTL__CI__VI = 0x3612; -constexpr unsigned int mmSDMA1_FREEZE__CI__VI = 0x3613; -constexpr unsigned int mmSDMA1_GFX_APE1_CNTL__CI__VI = 0x36A8; -constexpr unsigned int mmSDMA1_GFX_CONTEXT_CNTL__CI__VI = 0x3693; -constexpr unsigned int mmSDMA1_GFX_CONTEXT_STATUS__CI__VI = 0x3691; -constexpr unsigned int mmSDMA1_GFX_IB_BASE_HI__CI__VI = 0x368E; -constexpr unsigned int mmSDMA1_GFX_IB_BASE_LO__CI__VI = 0x368D; -constexpr unsigned int mmSDMA1_GFX_IB_CNTL__CI__VI = 0x368A; -constexpr unsigned int mmSDMA1_GFX_IB_OFFSET__CI__VI = 0x368C; -constexpr unsigned int mmSDMA1_GFX_IB_RPTR__CI__VI = 0x368B; -constexpr unsigned int mmSDMA1_GFX_IB_SIZE__CI__VI = 0x368F; -constexpr unsigned int mmSDMA1_GFX_RB_BASE_HI__CI__VI = 0x3682; -constexpr unsigned int mmSDMA1_GFX_RB_BASE__CI__VI = 0x3681; -constexpr unsigned int mmSDMA1_GFX_RB_CNTL__CI__VI = 0x3680; -constexpr unsigned int mmSDMA1_GFX_RB_RPTR_ADDR_HI__CI__VI = 0x3688; -constexpr unsigned int mmSDMA1_GFX_RB_RPTR_ADDR_LO__CI__VI = 0x3689; -constexpr unsigned int mmSDMA1_GFX_RB_RPTR__CI__VI = 0x3683; -constexpr unsigned int mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI = 0x3686; -constexpr unsigned int mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI = 0x3687; -constexpr unsigned int mmSDMA1_GFX_RB_WPTR_POLL_CNTL__CI__VI = 0x3685; -constexpr unsigned int mmSDMA1_GFX_RB_WPTR__CI__VI = 0x3684; -constexpr unsigned int mmSDMA1_GFX_SKIP_CNTL__CI__VI = 0x3690; -constexpr unsigned int mmSDMA1_GFX_VIRTUAL_ADDR__CI__VI = 0x36A7; -constexpr unsigned int mmSDMA1_HASH__CI__VI = 0x3607; -constexpr unsigned int mmSDMA1_IB_OFFSET_FETCH__CI__VI = 0x360B; -constexpr unsigned int mmSDMA1_PERFCOUNTER0_RESULT__CI = 0x3610; -constexpr unsigned int mmSDMA1_PERFCOUNTER1_RESULT__CI = 0x3611; -constexpr unsigned int mmSDMA1_PERFMON_CNTL__CI = 0x360F; -constexpr unsigned int mmSDMA1_PHASE0_QUANTUM__CI__VI = 0x3614; -constexpr unsigned int mmSDMA1_PHASE1_QUANTUM__CI__VI = 0x3615; -constexpr unsigned int mmSDMA1_POWER_CNTL__CI__VI = 0x3602; -constexpr unsigned int mmSDMA1_PROGRAM__CI__VI = 0x360C; -constexpr unsigned int mmSDMA1_RB_RPTR_FETCH__CI__VI = 0x360A; -constexpr unsigned int mmSDMA1_RLC0_APE1_CNTL__CI__VI = 0x3728; -constexpr unsigned int mmSDMA1_RLC0_CONTEXT_STATUS__CI__VI = 0x3711; -constexpr unsigned int mmSDMA1_RLC0_DOORBELL_LOG__CI__VI = 0x3729; -constexpr unsigned int mmSDMA1_RLC0_DOORBELL__CI__VI = 0x3712; -constexpr unsigned int mmSDMA1_RLC0_IB_BASE_HI__CI__VI = 0x370E; -constexpr unsigned int mmSDMA1_RLC0_IB_BASE_LO__CI__VI = 0x370D; -constexpr unsigned int mmSDMA1_RLC0_IB_CNTL__CI__VI = 0x370A; -constexpr unsigned int mmSDMA1_RLC0_IB_OFFSET__CI__VI = 0x370C; -constexpr unsigned int mmSDMA1_RLC0_IB_RPTR__CI__VI = 0x370B; -constexpr unsigned int mmSDMA1_RLC0_IB_SIZE__CI__VI = 0x370F; -constexpr unsigned int mmSDMA1_RLC0_RB_BASE_HI__CI__VI = 0x3702; -constexpr unsigned int mmSDMA1_RLC0_RB_BASE__CI__VI = 0x3701; -constexpr unsigned int mmSDMA1_RLC0_RB_CNTL__CI__VI = 0x3700; -constexpr unsigned int mmSDMA1_RLC0_RB_RPTR_ADDR_HI__CI__VI = 0x3708; -constexpr unsigned int mmSDMA1_RLC0_RB_RPTR_ADDR_LO__CI__VI = 0x3709; -constexpr unsigned int mmSDMA1_RLC0_RB_RPTR__CI__VI = 0x3703; -constexpr unsigned int mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI = 0x3706; -constexpr unsigned int mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI = 0x3707; -constexpr unsigned int mmSDMA1_RLC0_RB_WPTR_POLL_CNTL__CI__VI = 0x3705; -constexpr unsigned int mmSDMA1_RLC0_RB_WPTR__CI__VI = 0x3704; -constexpr unsigned int mmSDMA1_RLC0_SKIP_CNTL__CI__VI = 0x3710; -constexpr unsigned int mmSDMA1_RLC0_VIRTUAL_ADDR__CI__VI = 0x3727; -constexpr unsigned int mmSDMA1_RLC1_APE1_CNTL__CI__VI = 0x37A8; -constexpr unsigned int mmSDMA1_RLC1_CONTEXT_STATUS__CI__VI = 0x3791; -constexpr unsigned int mmSDMA1_RLC1_DOORBELL_LOG__CI__VI = 0x37A9; -constexpr unsigned int mmSDMA1_RLC1_DOORBELL__CI__VI = 0x3792; -constexpr unsigned int mmSDMA1_RLC1_IB_BASE_HI__CI__VI = 0x378E; -constexpr unsigned int mmSDMA1_RLC1_IB_BASE_LO__CI__VI = 0x378D; -constexpr unsigned int mmSDMA1_RLC1_IB_CNTL__CI__VI = 0x378A; -constexpr unsigned int mmSDMA1_RLC1_IB_OFFSET__CI__VI = 0x378C; -constexpr unsigned int mmSDMA1_RLC1_IB_RPTR__CI__VI = 0x378B; -constexpr unsigned int mmSDMA1_RLC1_IB_SIZE__CI__VI = 0x378F; -constexpr unsigned int mmSDMA1_RLC1_RB_BASE_HI__CI__VI = 0x3782; -constexpr unsigned int mmSDMA1_RLC1_RB_BASE__CI__VI = 0x3781; -constexpr unsigned int mmSDMA1_RLC1_RB_CNTL__CI__VI = 0x3780; -constexpr unsigned int mmSDMA1_RLC1_RB_RPTR_ADDR_HI__CI__VI = 0x3788; -constexpr unsigned int mmSDMA1_RLC1_RB_RPTR_ADDR_LO__CI__VI = 0x3789; -constexpr unsigned int mmSDMA1_RLC1_RB_RPTR__CI__VI = 0x3783; -constexpr unsigned int mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI = 0x3786; -constexpr unsigned int mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI = 0x3787; -constexpr unsigned int mmSDMA1_RLC1_RB_WPTR_POLL_CNTL__CI__VI = 0x3785; -constexpr unsigned int mmSDMA1_RLC1_RB_WPTR__CI__VI = 0x3784; -constexpr unsigned int mmSDMA1_RLC1_SKIP_CNTL__CI__VI = 0x3790; -constexpr unsigned int mmSDMA1_RLC1_VIRTUAL_ADDR__CI__VI = 0x37A7; -constexpr unsigned int mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL__CI = 0x3608; -constexpr unsigned int mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI = 0x3609; -constexpr unsigned int mmSDMA1_STATUS1_REG__CI__VI = 0x360E; -constexpr unsigned int mmSDMA1_STATUS_REG__CI__VI = 0x360D; -constexpr unsigned int mmSDMA1_TILING_CONFIG__CI__VI = 0x3606; -constexpr unsigned int mmSDMA1_UCODE_ADDR__CI__VI = 0x3600; -constexpr unsigned int mmSDMA1_UCODE_DATA__CI__VI = 0x3601; -constexpr unsigned int mmSDMA_CONFIG__CI__VI = 0x0F91; -constexpr unsigned int mmSDMA_PGFSM_CONFIG__CI__VI = 0x3417; -constexpr unsigned int mmSDMA_PGFSM_READ__CI__VI = 0x3419; -constexpr unsigned int mmSDMA_PGFSM_WRITE__CI__VI = 0x3418; -constexpr unsigned int mmSDMA_POWER_GATING__CI__VI = 0x3416; -constexpr unsigned int mmSEM_CHICKEN_BITS__CI__VI = 0x0F9E; -constexpr unsigned int mmSEM_EDC_CONFIG__CI__VI = 0x0F9A; -constexpr unsigned int mmSEM_MAILBOX_CLIENTCONFIG__CI__VI = 0x0F9B; -constexpr unsigned int mmSEM_MAILBOX_CLIENTCONFIG__SI = 0x0F9A; -constexpr unsigned int mmSEM_MAILBOX_CONTROL__CI__VI = 0x0F9D; -constexpr unsigned int mmSEM_MAILBOX_CONTROL__SI = 0x0F9C; -constexpr unsigned int mmSEM_MAILBOX__CI__VI = 0x0F9C; -constexpr unsigned int mmSEM_MAILBOX__SI = 0x0F9B; -constexpr unsigned int mmSEM_MCIF_CONFIG = 0x0F90; -constexpr unsigned int mmSEM_STATUS__CI__VI = 0x0F99; -constexpr unsigned int mmSEQ8_DATA__SI__VI = 0x00F1; -constexpr unsigned int mmSEQ8_IDX__SI__VI = 0x00F1; -constexpr unsigned int mmSH_HIDDEN_PRIVATE_BASE_VMID__CI__VI = 0x2580; -constexpr unsigned int mmSH_MEM_APE1_BASE__CI__VI = 0x230B; -constexpr unsigned int mmSH_MEM_APE1_LIMIT__CI__VI = 0x230C; -constexpr unsigned int mmSH_MEM_BASES__CI__VI = 0x230A; -constexpr unsigned int mmSH_MEM_CONFIG__CI__VI = 0x230D; -constexpr unsigned int mmSH_STATIC_MEM_CONFIG__CI__VI = 0x2581; -constexpr unsigned int mmSLAVE_COMM_CMD_REG__SI__VI = 0x1624; -constexpr unsigned int mmSLAVE_COMM_CNTL_REG__SI__VI = 0x1625; -constexpr unsigned int mmSLAVE_COMM_DATA_REG1__SI__VI = 0x1621; -constexpr unsigned int mmSLAVE_COMM_DATA_REG2__SI__VI = 0x1622; -constexpr unsigned int mmSLAVE_COMM_DATA_REG3__SI__VI = 0x1623; -constexpr unsigned int mmSLAVE_HANG_ERROR = 0x153B; -constexpr unsigned int mmSLAVE_HANG_PROTECTION_CNTL = 0x1536; -constexpr unsigned int mmSLAVE_REQ_CREDIT_CNTL = 0x1517; -constexpr unsigned int mmSMBCLK_PAD_CNTL__CI = 0x1523; -constexpr unsigned int mmSMBDAT_PAD_CNTL__CI = 0x1522; -constexpr unsigned int mmSMBUS_SLV_CNTL__CI = 0x14FD; -constexpr unsigned int mmSMC_IND_ACCESS_CNTL__CI__VI = 0x0090; -constexpr unsigned int mmSMC_IND_ACCESS_CNTL__SI = 0x008A; -constexpr unsigned int mmSMC_IND_DATA = 0x0081; -constexpr unsigned int mmSMC_IND_DATA_0__CI__VI = 0x0081; -constexpr unsigned int mmSMC_IND_DATA_1__CI__VI = 0x0083; -constexpr unsigned int mmSMC_IND_DATA_2__CI__VI = 0x0085; -constexpr unsigned int mmSMC_IND_DATA_3__CI__VI = 0x0087; -constexpr unsigned int mmSMC_IND_DATA_4__CI__VI = 0x0089; -constexpr unsigned int mmSMC_IND_DATA_5__CI__VI = 0x008B; -constexpr unsigned int mmSMC_IND_DATA_6__CI__VI = 0x008D; -constexpr unsigned int mmSMC_IND_DATA_7__CI__VI = 0x008F; -constexpr unsigned int mmSMC_IND_INDEX = 0x0080; -constexpr unsigned int mmSMC_IND_INDEX_0__CI__VI = 0x0080; -constexpr unsigned int mmSMC_IND_INDEX_1__CI__VI = 0x0082; -constexpr unsigned int mmSMC_IND_INDEX_2__CI__VI = 0x0084; -constexpr unsigned int mmSMC_IND_INDEX_3__CI__VI = 0x0086; -constexpr unsigned int mmSMC_IND_INDEX_4__CI__VI = 0x0088; -constexpr unsigned int mmSMC_IND_INDEX_5__CI__VI = 0x008A; -constexpr unsigned int mmSMC_IND_INDEX_6__CI__VI = 0x008C; -constexpr unsigned int mmSMC_IND_INDEX_7__CI__VI = 0x008E; -constexpr unsigned int mmSMC_MESSAGE_0__CI__VI = 0x0094; -constexpr unsigned int mmSMC_MESSAGE_0__SI = 0x008B; -constexpr unsigned int mmSMC_MESSAGE_10__CI__VI = 0x00B9; -constexpr unsigned int mmSMC_MESSAGE_11__CI__VI = 0x00BB; -constexpr unsigned int mmSMC_MESSAGE_1__CI__VI = 0x0096; -constexpr unsigned int mmSMC_MESSAGE_1__SI = 0x008D; -constexpr unsigned int mmSMC_MESSAGE_2__CI__VI = 0x0098; -constexpr unsigned int mmSMC_MESSAGE_3__CI__VI = 0x009A; -constexpr unsigned int mmSMC_MESSAGE_4__CI__VI = 0x009C; -constexpr unsigned int mmSMC_MESSAGE_5__CI__VI = 0x009E; -constexpr unsigned int mmSMC_MESSAGE_6__CI__VI = 0x00A0; -constexpr unsigned int mmSMC_MESSAGE_7__CI__VI = 0x00A2; -constexpr unsigned int mmSMC_MESSAGE_8__CI__VI = 0x00B5; -constexpr unsigned int mmSMC_MESSAGE_9__CI__VI = 0x00B7; -constexpr unsigned int mmSMC_MSG_ARG_0__CI__VI = 0x00A4; -constexpr unsigned int mmSMC_MSG_ARG_10__CI__VI = 0x00BF; -constexpr unsigned int mmSMC_MSG_ARG_11__CI = 0x0091; -constexpr unsigned int mmSMC_MSG_ARG_1__CI__VI = 0x00A5; -constexpr unsigned int mmSMC_MSG_ARG_2__CI__VI = 0x00A6; -constexpr unsigned int mmSMC_MSG_ARG_3__CI__VI = 0x00A7; -constexpr unsigned int mmSMC_MSG_ARG_4__CI__VI = 0x00A8; -constexpr unsigned int mmSMC_MSG_ARG_5__CI__VI = 0x00A9; -constexpr unsigned int mmSMC_MSG_ARG_6__CI__VI = 0x00AA; -constexpr unsigned int mmSMC_MSG_ARG_7__CI__VI = 0x00AB; -constexpr unsigned int mmSMC_MSG_ARG_8__CI__VI = 0x00BD; -constexpr unsigned int mmSMC_MSG_ARG_9__CI__VI = 0x00BE; -constexpr unsigned int mmSMC_RESP_0__CI__VI = 0x0095; -constexpr unsigned int mmSMC_RESP_0__SI = 0x008C; -constexpr unsigned int mmSMC_RESP_10__CI__VI = 0x00BA; -constexpr unsigned int mmSMC_RESP_11__CI__VI = 0x00BC; -constexpr unsigned int mmSMC_RESP_1__CI__VI = 0x0097; -constexpr unsigned int mmSMC_RESP_1__SI = 0x008E; -constexpr unsigned int mmSMC_RESP_2__CI__VI = 0x0099; -constexpr unsigned int mmSMC_RESP_3__CI__VI = 0x009B; -constexpr unsigned int mmSMC_RESP_4__CI__VI = 0x009D; -constexpr unsigned int mmSMC_RESP_5__CI__VI = 0x009F; -constexpr unsigned int mmSMC_RESP_6__CI__VI = 0x00A1; -constexpr unsigned int mmSMC_RESP_7__CI__VI = 0x00A3; -constexpr unsigned int mmSMC_RESP_8__CI__VI = 0x00B6; -constexpr unsigned int mmSMC_RESP_9__CI__VI = 0x00B8; -constexpr unsigned int mmSMC_SCRATCH9__SI = 0x022A; -constexpr unsigned int mmSMU_SMC_IND_DATA__CI__VI = 0x0081; -constexpr unsigned int mmSMU_SMC_IND_INDEX__CI__VI = 0x0080; -constexpr unsigned int mmSPI_ARB_CYCLES_0__CI__VI = 0x31C1; -constexpr unsigned int mmSPI_ARB_CYCLES_0__SI = 0x243D; -constexpr unsigned int mmSPI_ARB_CYCLES_1__CI__VI = 0x31C2; -constexpr unsigned int mmSPI_ARB_CYCLES_1__SI = 0x243E; -constexpr unsigned int mmSPI_ARB_PRIORITY__CI__VI = 0x31C0; -constexpr unsigned int mmSPI_ARB_PRIORITY__SI = 0x243C; -constexpr unsigned int mmSPI_BARYC_CNTL = 0xA1B8; -constexpr unsigned int mmSPI_CDBG_SYS_CS0__CI__VI = 0x31C5; -constexpr unsigned int mmSPI_CDBG_SYS_CS1__CI__VI = 0x31C6; -constexpr unsigned int mmSPI_CDBG_SYS_GFX__CI__VI = 0x31C3; -constexpr unsigned int mmSPI_CDBG_SYS_HP3D__CI__VI = 0x31C4; -constexpr unsigned int mmSPI_COMPUTE_QUEUE_RESET__CI__VI = 0x31DB; -constexpr unsigned int mmSPI_CONFIG_CNTL = 0x2440; -constexpr unsigned int mmSPI_CONFIG_CNTL_1 = 0x244F; -constexpr unsigned int mmSPI_CSQ_WF_ACTIVE_COUNT_0__CI__VI = 0x24DC; -constexpr unsigned int mmSPI_CSQ_WF_ACTIVE_COUNT_1__CI__VI = 0x24DD; -constexpr unsigned int mmSPI_CSQ_WF_ACTIVE_COUNT_2__CI__VI = 0x24DE; -constexpr unsigned int mmSPI_CSQ_WF_ACTIVE_COUNT_3__CI__VI = 0x24DF; -constexpr unsigned int mmSPI_CSQ_WF_ACTIVE_COUNT_4__CI__VI = 0x24E0; -constexpr unsigned int mmSPI_CSQ_WF_ACTIVE_COUNT_5__CI__VI = 0x24E1; -constexpr unsigned int mmSPI_CSQ_WF_ACTIVE_COUNT_6__CI__VI = 0x24E2; -constexpr unsigned int mmSPI_CSQ_WF_ACTIVE_COUNT_7__CI__VI = 0x24E3; -constexpr unsigned int mmSPI_CSQ_WF_ACTIVE_STATUS__CI__VI = 0x24DB; -constexpr unsigned int mmSPI_DEBUG_BUSY = 0x2450; -constexpr unsigned int mmSPI_DEBUG_CNTL = 0x2441; -constexpr unsigned int mmSPI_DEBUG_READ = 0x2442; -constexpr unsigned int mmSPI_GDBG_TBA_HI__CI__VI = 0x31D5; -constexpr unsigned int mmSPI_GDBG_TBA_LO__CI__VI = 0x31D4; -constexpr unsigned int mmSPI_GDBG_TMA_HI__CI__VI = 0x31D7; -constexpr unsigned int mmSPI_GDBG_TMA_LO__CI__VI = 0x31D6; -constexpr unsigned int mmSPI_GDBG_TRAP_CONFIG__CI__VI = 0x31D2; -constexpr unsigned int mmSPI_GDBG_TRAP_DATA0__CI__VI = 0x31D8; -constexpr unsigned int mmSPI_GDBG_TRAP_DATA1__CI__VI = 0x31D9; -constexpr unsigned int mmSPI_GDBG_TRAP_MASK__CI__VI = 0x31D3; -constexpr unsigned int mmSPI_GDBG_WAVE_CNTL__CI__VI = 0x31D1; -constexpr unsigned int mmSPI_GDS_CREDITS = 0x24D8; -constexpr unsigned int mmSPI_INTERP_CONTROL_0 = 0xA1B5; -constexpr unsigned int mmSPI_LB_CTR_CTRL = 0x24D4; -constexpr unsigned int mmSPI_LB_CU_MASK = 0x24D5; -constexpr unsigned int mmSPI_LB_DATA_REG = 0x24D6; -constexpr unsigned int mmSPI_P0_TRAP_SCREEN_GPR_MIN__CI__VI = 0x24F0; -constexpr unsigned int mmSPI_P0_TRAP_SCREEN_PSBA_HI__CI__VI = 0x24ED; -constexpr unsigned int mmSPI_P0_TRAP_SCREEN_PSBA_LO__CI__VI = 0x24EC; -constexpr unsigned int mmSPI_P0_TRAP_SCREEN_PSMA_HI__CI__VI = 0x24EF; -constexpr unsigned int mmSPI_P0_TRAP_SCREEN_PSMA_LO__CI__VI = 0x24EE; -constexpr unsigned int mmSPI_P1_TRAP_SCREEN_GPR_MIN__CI__VI = 0x24F5; -constexpr unsigned int mmSPI_P1_TRAP_SCREEN_PSBA_HI__CI__VI = 0x24F2; -constexpr unsigned int mmSPI_P1_TRAP_SCREEN_PSBA_LO__CI__VI = 0x24F1; -constexpr unsigned int mmSPI_P1_TRAP_SCREEN_PSMA_HI__CI__VI = 0x24F4; -constexpr unsigned int mmSPI_P1_TRAP_SCREEN_PSMA_LO__CI__VI = 0x24F3; -constexpr unsigned int mmSPI_PERFCOUNTER0_HI__CI__VI = 0xD180; -constexpr unsigned int mmSPI_PERFCOUNTER0_HI__SI = 0x2447; -constexpr unsigned int mmSPI_PERFCOUNTER0_LO__CI__VI = 0xD181; -constexpr unsigned int mmSPI_PERFCOUNTER0_LO__SI = 0x2448; -constexpr unsigned int mmSPI_PERFCOUNTER0_SELECT1__CI__VI = 0xD984; -constexpr unsigned int mmSPI_PERFCOUNTER0_SELECT__CI__VI = 0xD980; -constexpr unsigned int mmSPI_PERFCOUNTER0_SELECT__SI = 0x2443; -constexpr unsigned int mmSPI_PERFCOUNTER1_HI__CI__VI = 0xD182; -constexpr unsigned int mmSPI_PERFCOUNTER1_HI__SI = 0x2449; -constexpr unsigned int mmSPI_PERFCOUNTER1_LO__CI__VI = 0xD183; -constexpr unsigned int mmSPI_PERFCOUNTER1_LO__SI = 0x244A; -constexpr unsigned int mmSPI_PERFCOUNTER1_SELECT1__CI__VI = 0xD985; -constexpr unsigned int mmSPI_PERFCOUNTER1_SELECT__CI__VI = 0xD981; -constexpr unsigned int mmSPI_PERFCOUNTER1_SELECT__SI = 0x2444; -constexpr unsigned int mmSPI_PERFCOUNTER2_HI__CI__VI = 0xD184; -constexpr unsigned int mmSPI_PERFCOUNTER2_HI__SI = 0x244B; -constexpr unsigned int mmSPI_PERFCOUNTER2_LO__CI__VI = 0xD185; -constexpr unsigned int mmSPI_PERFCOUNTER2_LO__SI = 0x244C; -constexpr unsigned int mmSPI_PERFCOUNTER2_SELECT1__CI__VI = 0xD986; -constexpr unsigned int mmSPI_PERFCOUNTER2_SELECT__CI__VI = 0xD982; -constexpr unsigned int mmSPI_PERFCOUNTER2_SELECT__SI = 0x2445; -constexpr unsigned int mmSPI_PERFCOUNTER3_HI__CI__VI = 0xD186; -constexpr unsigned int mmSPI_PERFCOUNTER3_HI__SI = 0x244D; -constexpr unsigned int mmSPI_PERFCOUNTER3_LO__CI__VI = 0xD187; -constexpr unsigned int mmSPI_PERFCOUNTER3_LO__SI = 0x244E; -constexpr unsigned int mmSPI_PERFCOUNTER3_SELECT1__CI__VI = 0xD987; -constexpr unsigned int mmSPI_PERFCOUNTER3_SELECT__CI__VI = 0xD983; -constexpr unsigned int mmSPI_PERFCOUNTER3_SELECT__SI = 0x2446; -constexpr unsigned int mmSPI_PERFCOUNTER4_HI__CI__VI = 0xD188; -constexpr unsigned int mmSPI_PERFCOUNTER4_LO__CI__VI = 0xD189; -constexpr unsigned int mmSPI_PERFCOUNTER4_SELECT__CI__VI = 0xD988; -constexpr unsigned int mmSPI_PERFCOUNTER5_HI__CI__VI = 0xD18A; -constexpr unsigned int mmSPI_PERFCOUNTER5_LO__CI__VI = 0xD18B; -constexpr unsigned int mmSPI_PERFCOUNTER5_SELECT__CI__VI = 0xD989; -constexpr unsigned int mmSPI_PERFCOUNTER_BINS__CI__VI = 0xD98A; -constexpr unsigned int mmSPI_PERFCOUNTER_BINS__SI = 0x243F; -constexpr unsigned int mmSPI_PG_ENABLE_STATIC_CU_MASK = 0x24D7; -constexpr unsigned int mmSPI_PS_INPUT_ADDR = 0xA1B4; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_0 = 0xA191; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_1 = 0xA192; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_10 = 0xA19B; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_11 = 0xA19C; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_12 = 0xA19D; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_13 = 0xA19E; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_14 = 0xA19F; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_15 = 0xA1A0; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_16 = 0xA1A1; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_17 = 0xA1A2; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_18 = 0xA1A3; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_19 = 0xA1A4; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_2 = 0xA193; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_20 = 0xA1A5; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_21 = 0xA1A6; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_22 = 0xA1A7; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_23 = 0xA1A8; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_24 = 0xA1A9; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_25 = 0xA1AA; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_26 = 0xA1AB; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_27 = 0xA1AC; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_28 = 0xA1AD; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_29 = 0xA1AE; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_3 = 0xA194; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_30 = 0xA1AF; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_31 = 0xA1B0; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_4 = 0xA195; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_5 = 0xA196; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_6 = 0xA197; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_7 = 0xA198; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_8 = 0xA199; -constexpr unsigned int mmSPI_PS_INPUT_CNTL_9 = 0xA19A; -constexpr unsigned int mmSPI_PS_INPUT_ENA = 0xA1B3; -constexpr unsigned int mmSPI_PS_IN_CONTROL = 0xA1B6; -constexpr unsigned int mmSPI_PS_MAX_WAVE_ID__CI__VI = 0x243A; -constexpr unsigned int mmSPI_PS_MAX_WAVE_ID__SI = 0x243B; -constexpr unsigned int mmSPI_RESET_DEBUG__CI__VI = 0x31DA; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_0__CI__VI = 0x31DC; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_10__CI__VI = 0x31F0; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_11__CI__VI = 0x31F1; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_1__CI__VI = 0x31DD; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_2__CI__VI = 0x31DE; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_3__CI__VI = 0x31DF; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_4__CI__VI = 0x31E0; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_5__CI__VI = 0x31E1; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_6__CI__VI = 0x31E2; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_7__CI__VI = 0x31E3; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_8__CI__VI = 0x31E4; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_9__CI__VI = 0x31E5; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_0__CI__VI = 0x31E6; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_10__CI__VI = 0x31F2; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_11__CI__VI = 0x31F3; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_1__CI__VI = 0x31E7; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_2__CI__VI = 0x31E8; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_3__CI__VI = 0x31E9; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_4__CI__VI = 0x31EA; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_5__CI__VI = 0x31EB; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_6__CI__VI = 0x31EC; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_7__CI__VI = 0x31ED; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_8__CI__VI = 0x31EE; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_9__CI__VI = 0x31EF; -constexpr unsigned int mmSPI_SHADER_COL_FORMAT = 0xA1C5; -constexpr unsigned int mmSPI_SHADER_LATE_ALLOC_VS__CI__VI = 0x2C47; -constexpr unsigned int mmSPI_SHADER_PGM_HI_ES = 0x2CC9; -constexpr unsigned int mmSPI_SHADER_PGM_HI_GS = 0x2C89; -constexpr unsigned int mmSPI_SHADER_PGM_HI_HS = 0x2D09; -constexpr unsigned int mmSPI_SHADER_PGM_HI_LS = 0x2D49; -constexpr unsigned int mmSPI_SHADER_PGM_HI_PS = 0x2C09; -constexpr unsigned int mmSPI_SHADER_PGM_HI_VS = 0x2C49; -constexpr unsigned int mmSPI_SHADER_PGM_LO_ES = 0x2CC8; -constexpr unsigned int mmSPI_SHADER_PGM_LO_GS = 0x2C88; -constexpr unsigned int mmSPI_SHADER_PGM_LO_HS = 0x2D08; -constexpr unsigned int mmSPI_SHADER_PGM_LO_LS = 0x2D48; -constexpr unsigned int mmSPI_SHADER_PGM_LO_PS = 0x2C08; -constexpr unsigned int mmSPI_SHADER_PGM_LO_VS = 0x2C48; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC1_ES = 0x2CCA; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC1_GS = 0x2C8A; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC1_HS = 0x2D0A; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC1_LS = 0x2D4A; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC1_PS = 0x2C0A; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC1_VS = 0x2C4A; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC2_ES = 0x2CCB; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC2_ES_GS__CI__VI = 0x2CBC; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC2_ES_VS__CI__VI = 0x2C7C; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC2_GS = 0x2C8B; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC2_HS = 0x2D0B; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC2_LS = 0x2D4B; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC2_LS_ES__CI__VI = 0x2CFD; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC2_LS_HS__CI__VI = 0x2D3D; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC2_LS_VS__CI__VI = 0x2C7D; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC2_PS = 0x2C0B; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC2_VS = 0x2C4B; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC3_ES__CI__VI = 0x2CC7; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC3_GS__CI__VI = 0x2C87; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC3_HS__CI__VI = 0x2D07; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC3_LS__CI__VI = 0x2D47; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC3_PS__CI__VI = 0x2C07; -constexpr unsigned int mmSPI_SHADER_PGM_RSRC3_VS__CI__VI = 0x2C46; -constexpr unsigned int mmSPI_SHADER_POS_FORMAT = 0xA1C3; -constexpr unsigned int mmSPI_SHADER_TBA_HI_ES = 0x2CC1; -constexpr unsigned int mmSPI_SHADER_TBA_HI_GS = 0x2C81; -constexpr unsigned int mmSPI_SHADER_TBA_HI_HS = 0x2D01; -constexpr unsigned int mmSPI_SHADER_TBA_HI_LS = 0x2D41; -constexpr unsigned int mmSPI_SHADER_TBA_HI_PS = 0x2C01; -constexpr unsigned int mmSPI_SHADER_TBA_HI_VS = 0x2C41; -constexpr unsigned int mmSPI_SHADER_TBA_LO_ES = 0x2CC0; -constexpr unsigned int mmSPI_SHADER_TBA_LO_GS = 0x2C80; -constexpr unsigned int mmSPI_SHADER_TBA_LO_HS = 0x2D00; -constexpr unsigned int mmSPI_SHADER_TBA_LO_LS = 0x2D40; -constexpr unsigned int mmSPI_SHADER_TBA_LO_PS = 0x2C00; -constexpr unsigned int mmSPI_SHADER_TBA_LO_VS = 0x2C40; -constexpr unsigned int mmSPI_SHADER_TMA_HI_ES = 0x2CC3; -constexpr unsigned int mmSPI_SHADER_TMA_HI_GS = 0x2C83; -constexpr unsigned int mmSPI_SHADER_TMA_HI_HS = 0x2D03; -constexpr unsigned int mmSPI_SHADER_TMA_HI_LS = 0x2D43; -constexpr unsigned int mmSPI_SHADER_TMA_HI_PS = 0x2C03; -constexpr unsigned int mmSPI_SHADER_TMA_HI_VS = 0x2C43; -constexpr unsigned int mmSPI_SHADER_TMA_LO_ES = 0x2CC2; -constexpr unsigned int mmSPI_SHADER_TMA_LO_GS = 0x2C82; -constexpr unsigned int mmSPI_SHADER_TMA_LO_HS = 0x2D02; -constexpr unsigned int mmSPI_SHADER_TMA_LO_LS = 0x2D42; -constexpr unsigned int mmSPI_SHADER_TMA_LO_PS = 0x2C02; -constexpr unsigned int mmSPI_SHADER_TMA_LO_VS = 0x2C42; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_0 = 0x2CCC; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_1 = 0x2CCD; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_10 = 0x2CD6; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_11 = 0x2CD7; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_12 = 0x2CD8; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_13 = 0x2CD9; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_14 = 0x2CDA; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_15 = 0x2CDB; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_2 = 0x2CCE; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_3 = 0x2CCF; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_4 = 0x2CD0; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_5 = 0x2CD1; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_6 = 0x2CD2; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_7 = 0x2CD3; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_8 = 0x2CD4; -constexpr unsigned int mmSPI_SHADER_USER_DATA_ES_9 = 0x2CD5; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_0 = 0x2C8C; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_1 = 0x2C8D; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_10 = 0x2C96; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_11 = 0x2C97; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_12 = 0x2C98; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_13 = 0x2C99; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_14 = 0x2C9A; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_15 = 0x2C9B; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_2 = 0x2C8E; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_3 = 0x2C8F; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_4 = 0x2C90; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_5 = 0x2C91; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_6 = 0x2C92; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_7 = 0x2C93; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_8 = 0x2C94; -constexpr unsigned int mmSPI_SHADER_USER_DATA_GS_9 = 0x2C95; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_0 = 0x2D0C; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_1 = 0x2D0D; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_10 = 0x2D16; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_11 = 0x2D17; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_12 = 0x2D18; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_13 = 0x2D19; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_14 = 0x2D1A; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_15 = 0x2D1B; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_2 = 0x2D0E; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_3 = 0x2D0F; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_4 = 0x2D10; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_5 = 0x2D11; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_6 = 0x2D12; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_7 = 0x2D13; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_8 = 0x2D14; -constexpr unsigned int mmSPI_SHADER_USER_DATA_HS_9 = 0x2D15; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_0 = 0x2D4C; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_1 = 0x2D4D; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_10 = 0x2D56; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_11 = 0x2D57; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_12 = 0x2D58; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_13 = 0x2D59; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_14 = 0x2D5A; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_15 = 0x2D5B; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_2 = 0x2D4E; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_3 = 0x2D4F; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_4 = 0x2D50; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_5 = 0x2D51; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_6 = 0x2D52; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_7 = 0x2D53; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_8 = 0x2D54; -constexpr unsigned int mmSPI_SHADER_USER_DATA_LS_9 = 0x2D55; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_0 = 0x2C0C; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_1 = 0x2C0D; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_10 = 0x2C16; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_11 = 0x2C17; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_12 = 0x2C18; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_13 = 0x2C19; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_14 = 0x2C1A; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_15 = 0x2C1B; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_2 = 0x2C0E; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_3 = 0x2C0F; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_4 = 0x2C10; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_5 = 0x2C11; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_6 = 0x2C12; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_7 = 0x2C13; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_8 = 0x2C14; -constexpr unsigned int mmSPI_SHADER_USER_DATA_PS_9 = 0x2C15; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_0 = 0x2C4C; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_1 = 0x2C4D; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_10 = 0x2C56; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_11 = 0x2C57; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_12 = 0x2C58; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_13 = 0x2C59; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_14 = 0x2C5A; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_15 = 0x2C5B; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_2 = 0x2C4E; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_3 = 0x2C4F; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_4 = 0x2C50; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_5 = 0x2C51; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_6 = 0x2C52; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_7 = 0x2C53; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_8 = 0x2C54; -constexpr unsigned int mmSPI_SHADER_USER_DATA_VS_9 = 0x2C55; -constexpr unsigned int mmSPI_SHADER_Z_FORMAT = 0xA1C4; -constexpr unsigned int mmSPI_SLAVE_DEBUG_BUSY = 0x24D3; -constexpr unsigned int mmSPI_STATIC_THREAD_MGMT_3__SI = 0x243A; -constexpr unsigned int mmSPI_SX_EXPORT_BUFFER_SIZES = 0x24D9; -constexpr unsigned int mmSPI_SX_SCOREBOARD_BUFFER_SIZES = 0x24DA; -constexpr unsigned int mmSPI_TMPRING_SIZE = 0xA1BA; -constexpr unsigned int mmSPI_VS_OUT_CONFIG = 0xA1B1; -constexpr unsigned int mmSPI_WCL_PIPE_PERCENT_CS0__CI__VI = 0x31C9; -constexpr unsigned int mmSPI_WCL_PIPE_PERCENT_CS1__CI__VI = 0x31CA; -constexpr unsigned int mmSPI_WCL_PIPE_PERCENT_CS2__CI__VI = 0x31CB; -constexpr unsigned int mmSPI_WCL_PIPE_PERCENT_CS3__CI__VI = 0x31CC; -constexpr unsigned int mmSPI_WCL_PIPE_PERCENT_CS4__CI__VI = 0x31CD; -constexpr unsigned int mmSPI_WCL_PIPE_PERCENT_CS5__CI__VI = 0x31CE; -constexpr unsigned int mmSPI_WCL_PIPE_PERCENT_CS6__CI__VI = 0x31CF; -constexpr unsigned int mmSPI_WCL_PIPE_PERCENT_CS7__CI__VI = 0x31D0; -constexpr unsigned int mmSPI_WCL_PIPE_PERCENT_GFX__CI__VI = 0x31C7; -constexpr unsigned int mmSPI_WCL_PIPE_PERCENT_HP3D__CI__VI = 0x31C8; -constexpr unsigned int mmSPI_WF_LIFETIME_CNTL__CI__VI = 0x24AA; -constexpr unsigned int mmSPI_WF_LIFETIME_DEBUG__CI__VI = 0x24CA; -constexpr unsigned int mmSPI_WF_LIFETIME_LIMIT_0__CI__VI = 0x24AB; -constexpr unsigned int mmSPI_WF_LIFETIME_LIMIT_1__CI__VI = 0x24AC; -constexpr unsigned int mmSPI_WF_LIFETIME_LIMIT_2__CI__VI = 0x24AD; -constexpr unsigned int mmSPI_WF_LIFETIME_LIMIT_3__CI__VI = 0x24AE; -constexpr unsigned int mmSPI_WF_LIFETIME_LIMIT_4__CI__VI = 0x24AF; -constexpr unsigned int mmSPI_WF_LIFETIME_LIMIT_5__CI__VI = 0x24B0; -constexpr unsigned int mmSPI_WF_LIFETIME_LIMIT_6__CI__VI = 0x24B1; -constexpr unsigned int mmSPI_WF_LIFETIME_LIMIT_7__CI__VI = 0x24B2; -constexpr unsigned int mmSPI_WF_LIFETIME_LIMIT_8__CI__VI = 0x24B3; -constexpr unsigned int mmSPI_WF_LIFETIME_LIMIT_9__CI__VI = 0x24B4; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_0__CI__VI = 0x24B5; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_10__CI__VI = 0x24BF; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_11__CI__VI = 0x24C0; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_12__CI__VI = 0x24C1; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_13__CI__VI = 0x24C2; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_14__CI__VI = 0x24C3; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_15__CI__VI = 0x24C4; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_16__CI__VI = 0x24C5; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_17__CI__VI = 0x24C6; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_18__CI__VI = 0x24C7; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_19__CI__VI = 0x24C8; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_1__CI__VI = 0x24B6; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_20__CI__VI = 0x24C9; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_2__CI__VI = 0x24B7; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_3__CI__VI = 0x24B8; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_4__CI__VI = 0x24B9; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_5__CI__VI = 0x24BA; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_6__CI__VI = 0x24BB; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_7__CI__VI = 0x24BC; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_8__CI__VI = 0x24BD; -constexpr unsigned int mmSPI_WF_LIFETIME_STATUS_9__CI__VI = 0x24BE; -constexpr unsigned int mmSPLL_CNTL_MODE__SI = 0x0186; -constexpr unsigned int mmSQC_CACHES__CI__VI = 0xC348; -constexpr unsigned int mmSQC_CACHES__SI = 0x2302; -constexpr unsigned int mmSQC_CONFIG = 0x2301; -constexpr unsigned int mmSQC_POLICY__CI = 0x230E; -constexpr unsigned int mmSQC_SECDED_CNT__SI__CI = 0x23A0; -constexpr unsigned int mmSQC_VOLATILE__CI = 0x230F; -constexpr unsigned int mmSQ_ALU_CLK_CTRL__CI__VI = 0xF08E; -constexpr unsigned int mmSQ_ALU_CLK_CTRL__SI = 0x2360; -constexpr unsigned int mmSQ_BUF_RSRC_WORD0 = 0x23C0; -constexpr unsigned int mmSQ_BUF_RSRC_WORD1 = 0x23C1; -constexpr unsigned int mmSQ_BUF_RSRC_WORD2 = 0x23C2; -constexpr unsigned int mmSQ_BUF_RSRC_WORD3 = 0x23C3; -constexpr unsigned int mmSQ_CMD_TIMESTAMP__CI__VI = 0x2375; -constexpr unsigned int mmSQ_CMD__CI__VI = 0x237B; -constexpr unsigned int mmSQ_CONFIG = 0x2300; -constexpr unsigned int mmSQ_DEBUG_STS_GLOBAL = 0x2309; -constexpr unsigned int mmSQ_DEBUG_STS_GLOBAL2__CI__VI = 0x2310; -constexpr unsigned int mmSQ_DEBUG_STS_GLOBAL3__CI__VI = 0x2311; -constexpr unsigned int mmSQ_DED_CNT__SI__CI = 0x23A2; -constexpr unsigned int mmSQ_DED_INFO__SI__CI = 0x23A3; -constexpr unsigned int mmSQ_DS_0 = 0x237F; -constexpr unsigned int mmSQ_DS_1 = 0x237F; -constexpr unsigned int mmSQ_EXP_0 = 0x237F; -constexpr unsigned int mmSQ_EXP_1 = 0x237F; -constexpr unsigned int mmSQ_FIFO_SIZES = 0x2305; -constexpr unsigned int mmSQ_FLAT_0__CI__VI = 0x237F; -constexpr unsigned int mmSQ_FLAT_1__CI__VI = 0x237F; -constexpr unsigned int mmSQ_FLAT_SCRATCH_WORD0__CI__VI = 0x23D0; -constexpr unsigned int mmSQ_FLAT_SCRATCH_WORD1__CI__VI = 0x23D1; -constexpr unsigned int mmSQ_HV_VMID_CTRL__CI__VI = 0xF840; -constexpr unsigned int mmSQ_IMG_RSRC_WORD0 = 0x23C4; -constexpr unsigned int mmSQ_IMG_RSRC_WORD1 = 0x23C5; -constexpr unsigned int mmSQ_IMG_RSRC_WORD2 = 0x23C6; -constexpr unsigned int mmSQ_IMG_RSRC_WORD3 = 0x23C7; -constexpr unsigned int mmSQ_IMG_RSRC_WORD4 = 0x23C8; -constexpr unsigned int mmSQ_IMG_RSRC_WORD5 = 0x23C9; -constexpr unsigned int mmSQ_IMG_RSRC_WORD6 = 0x23CA; -constexpr unsigned int mmSQ_IMG_RSRC_WORD7 = 0x23CB; -constexpr unsigned int mmSQ_IMG_SAMP_WORD0 = 0x23CC; -constexpr unsigned int mmSQ_IMG_SAMP_WORD1 = 0x23CD; -constexpr unsigned int mmSQ_IMG_SAMP_WORD2 = 0x23CE; -constexpr unsigned int mmSQ_IMG_SAMP_WORD3 = 0x23CF; -constexpr unsigned int mmSQ_IND_DATA = 0x2379; -constexpr unsigned int mmSQ_IND_INDEX = 0x2378; -constexpr unsigned int mmSQ_INST = 0x237F; -constexpr unsigned int mmSQ_INTERRUPT_AUTO_MASK__CI__VI = 0x2314; -constexpr unsigned int mmSQ_INTERRUPT_MSG_CTRL__CI__VI = 0x2315; -constexpr unsigned int mmSQ_LB_CTR_CTRL = 0x2398; -constexpr unsigned int mmSQ_LB_DATA_ALU_CYCLES = 0x2399; -constexpr unsigned int mmSQ_LB_DATA_ALU_STALLS = 0x239B; -constexpr unsigned int mmSQ_LB_DATA_TEX_CYCLES = 0x239A; -constexpr unsigned int mmSQ_LB_DATA_TEX_STALLS = 0x239C; -constexpr unsigned int mmSQ_LDS_CLK_CTRL__CI__VI = 0xF090; -constexpr unsigned int mmSQ_MIMG_0 = 0x237F; -constexpr unsigned int mmSQ_MIMG_1 = 0x237F; -constexpr unsigned int mmSQ_MTBUF_0 = 0x237F; -constexpr unsigned int mmSQ_MTBUF_1 = 0x237F; -constexpr unsigned int mmSQ_MUBUF_0 = 0x237F; -constexpr unsigned int mmSQ_MUBUF_1 = 0x237F; -constexpr unsigned int mmSQ_PERFCOUNTER0_HI__CI__VI = 0xD1C1; -constexpr unsigned int mmSQ_PERFCOUNTER0_HI__SI = 0x2321; -constexpr unsigned int mmSQ_PERFCOUNTER0_LO__CI__VI = 0xD1C0; -constexpr unsigned int mmSQ_PERFCOUNTER0_LO__SI = 0x2320; -constexpr unsigned int mmSQ_PERFCOUNTER0_SELECT__CI__VI = 0xD9C0; -constexpr unsigned int mmSQ_PERFCOUNTER0_SELECT__SI = 0x2340; -constexpr unsigned int mmSQ_PERFCOUNTER10_HI__CI__VI = 0xD1D5; -constexpr unsigned int mmSQ_PERFCOUNTER10_HI__SI = 0x2335; -constexpr unsigned int mmSQ_PERFCOUNTER10_LO__CI__VI = 0xD1D4; -constexpr unsigned int mmSQ_PERFCOUNTER10_LO__SI = 0x2334; -constexpr unsigned int mmSQ_PERFCOUNTER10_SELECT__CI__VI = 0xD9CA; -constexpr unsigned int mmSQ_PERFCOUNTER10_SELECT__SI = 0x234A; -constexpr unsigned int mmSQ_PERFCOUNTER11_HI__CI__VI = 0xD1D7; -constexpr unsigned int mmSQ_PERFCOUNTER11_HI__SI = 0x2337; -constexpr unsigned int mmSQ_PERFCOUNTER11_LO__CI__VI = 0xD1D6; -constexpr unsigned int mmSQ_PERFCOUNTER11_LO__SI = 0x2336; -constexpr unsigned int mmSQ_PERFCOUNTER11_SELECT__CI__VI = 0xD9CB; -constexpr unsigned int mmSQ_PERFCOUNTER11_SELECT__SI = 0x234B; -constexpr unsigned int mmSQ_PERFCOUNTER12_HI__CI__VI = 0xD1D9; -constexpr unsigned int mmSQ_PERFCOUNTER12_HI__SI = 0x2339; -constexpr unsigned int mmSQ_PERFCOUNTER12_LO__CI__VI = 0xD1D8; -constexpr unsigned int mmSQ_PERFCOUNTER12_LO__SI = 0x2338; -constexpr unsigned int mmSQ_PERFCOUNTER12_SELECT__CI__VI = 0xD9CC; -constexpr unsigned int mmSQ_PERFCOUNTER12_SELECT__SI = 0x234C; -constexpr unsigned int mmSQ_PERFCOUNTER13_HI__CI__VI = 0xD1DB; -constexpr unsigned int mmSQ_PERFCOUNTER13_HI__SI = 0x233B; -constexpr unsigned int mmSQ_PERFCOUNTER13_LO__CI__VI = 0xD1DA; -constexpr unsigned int mmSQ_PERFCOUNTER13_LO__SI = 0x233A; -constexpr unsigned int mmSQ_PERFCOUNTER13_SELECT__CI__VI = 0xD9CD; -constexpr unsigned int mmSQ_PERFCOUNTER13_SELECT__SI = 0x234D; -constexpr unsigned int mmSQ_PERFCOUNTER14_HI__CI__VI = 0xD1DD; -constexpr unsigned int mmSQ_PERFCOUNTER14_HI__SI = 0x233D; -constexpr unsigned int mmSQ_PERFCOUNTER14_LO__CI__VI = 0xD1DC; -constexpr unsigned int mmSQ_PERFCOUNTER14_LO__SI = 0x233C; -constexpr unsigned int mmSQ_PERFCOUNTER14_SELECT__CI__VI = 0xD9CE; -constexpr unsigned int mmSQ_PERFCOUNTER14_SELECT__SI = 0x234E; -constexpr unsigned int mmSQ_PERFCOUNTER15_HI__CI__VI = 0xD1DF; -constexpr unsigned int mmSQ_PERFCOUNTER15_HI__SI = 0x233F; -constexpr unsigned int mmSQ_PERFCOUNTER15_LO__CI__VI = 0xD1DE; -constexpr unsigned int mmSQ_PERFCOUNTER15_LO__SI = 0x233E; -constexpr unsigned int mmSQ_PERFCOUNTER15_SELECT__CI__VI = 0xD9CF; -constexpr unsigned int mmSQ_PERFCOUNTER15_SELECT__SI = 0x234F; -constexpr unsigned int mmSQ_PERFCOUNTER1_HI__CI__VI = 0xD1C3; -constexpr unsigned int mmSQ_PERFCOUNTER1_HI__SI = 0x2323; -constexpr unsigned int mmSQ_PERFCOUNTER1_LO__CI__VI = 0xD1C2; -constexpr unsigned int mmSQ_PERFCOUNTER1_LO__SI = 0x2322; -constexpr unsigned int mmSQ_PERFCOUNTER1_SELECT__CI__VI = 0xD9C1; -constexpr unsigned int mmSQ_PERFCOUNTER1_SELECT__SI = 0x2341; -constexpr unsigned int mmSQ_PERFCOUNTER2_HI__CI__VI = 0xD1C5; -constexpr unsigned int mmSQ_PERFCOUNTER2_HI__SI = 0x2325; -constexpr unsigned int mmSQ_PERFCOUNTER2_LO__CI__VI = 0xD1C4; -constexpr unsigned int mmSQ_PERFCOUNTER2_LO__SI = 0x2324; -constexpr unsigned int mmSQ_PERFCOUNTER2_SELECT__CI__VI = 0xD9C2; -constexpr unsigned int mmSQ_PERFCOUNTER2_SELECT__SI = 0x2342; -constexpr unsigned int mmSQ_PERFCOUNTER3_HI__CI__VI = 0xD1C7; -constexpr unsigned int mmSQ_PERFCOUNTER3_HI__SI = 0x2327; -constexpr unsigned int mmSQ_PERFCOUNTER3_LO__CI__VI = 0xD1C6; -constexpr unsigned int mmSQ_PERFCOUNTER3_LO__SI = 0x2326; -constexpr unsigned int mmSQ_PERFCOUNTER3_SELECT__CI__VI = 0xD9C3; -constexpr unsigned int mmSQ_PERFCOUNTER3_SELECT__SI = 0x2343; -constexpr unsigned int mmSQ_PERFCOUNTER4_HI__CI__VI = 0xD1C9; -constexpr unsigned int mmSQ_PERFCOUNTER4_HI__SI = 0x2329; -constexpr unsigned int mmSQ_PERFCOUNTER4_LO__CI__VI = 0xD1C8; -constexpr unsigned int mmSQ_PERFCOUNTER4_LO__SI = 0x2328; -constexpr unsigned int mmSQ_PERFCOUNTER4_SELECT__CI__VI = 0xD9C4; -constexpr unsigned int mmSQ_PERFCOUNTER4_SELECT__SI = 0x2344; -constexpr unsigned int mmSQ_PERFCOUNTER5_HI__CI__VI = 0xD1CB; -constexpr unsigned int mmSQ_PERFCOUNTER5_HI__SI = 0x232B; -constexpr unsigned int mmSQ_PERFCOUNTER5_LO__CI__VI = 0xD1CA; -constexpr unsigned int mmSQ_PERFCOUNTER5_LO__SI = 0x232A; -constexpr unsigned int mmSQ_PERFCOUNTER5_SELECT__CI__VI = 0xD9C5; -constexpr unsigned int mmSQ_PERFCOUNTER5_SELECT__SI = 0x2345; -constexpr unsigned int mmSQ_PERFCOUNTER6_HI__CI__VI = 0xD1CD; -constexpr unsigned int mmSQ_PERFCOUNTER6_HI__SI = 0x232D; -constexpr unsigned int mmSQ_PERFCOUNTER6_LO__CI__VI = 0xD1CC; -constexpr unsigned int mmSQ_PERFCOUNTER6_LO__SI = 0x232C; -constexpr unsigned int mmSQ_PERFCOUNTER6_SELECT__CI__VI = 0xD9C6; -constexpr unsigned int mmSQ_PERFCOUNTER6_SELECT__SI = 0x2346; -constexpr unsigned int mmSQ_PERFCOUNTER7_HI__CI__VI = 0xD1CF; -constexpr unsigned int mmSQ_PERFCOUNTER7_HI__SI = 0x232F; -constexpr unsigned int mmSQ_PERFCOUNTER7_LO__CI__VI = 0xD1CE; -constexpr unsigned int mmSQ_PERFCOUNTER7_LO__SI = 0x232E; -constexpr unsigned int mmSQ_PERFCOUNTER7_SELECT__CI__VI = 0xD9C7; -constexpr unsigned int mmSQ_PERFCOUNTER7_SELECT__SI = 0x2347; -constexpr unsigned int mmSQ_PERFCOUNTER8_HI__CI__VI = 0xD1D1; -constexpr unsigned int mmSQ_PERFCOUNTER8_HI__SI = 0x2331; -constexpr unsigned int mmSQ_PERFCOUNTER8_LO__CI__VI = 0xD1D0; -constexpr unsigned int mmSQ_PERFCOUNTER8_LO__SI = 0x2330; -constexpr unsigned int mmSQ_PERFCOUNTER8_SELECT__CI__VI = 0xD9C8; -constexpr unsigned int mmSQ_PERFCOUNTER8_SELECT__SI = 0x2348; -constexpr unsigned int mmSQ_PERFCOUNTER9_HI__CI__VI = 0xD1D3; -constexpr unsigned int mmSQ_PERFCOUNTER9_HI__SI = 0x2333; -constexpr unsigned int mmSQ_PERFCOUNTER9_LO__CI__VI = 0xD1D2; -constexpr unsigned int mmSQ_PERFCOUNTER9_LO__SI = 0x2332; -constexpr unsigned int mmSQ_PERFCOUNTER9_SELECT__CI__VI = 0xD9C9; -constexpr unsigned int mmSQ_PERFCOUNTER9_SELECT__SI = 0x2349; -constexpr unsigned int mmSQ_PERFCOUNTER_CTRL2__CI__VI = 0xD9E2; -constexpr unsigned int mmSQ_PERFCOUNTER_CTRL__CI__VI = 0xD9E0; -constexpr unsigned int mmSQ_PERFCOUNTER_CTRL__SI = 0x2306; -constexpr unsigned int mmSQ_PERFCOUNTER_MASK__CI__VI = 0xD9E1; -constexpr unsigned int mmSQ_POWER_THROTTLE2__CI__VI = 0xF092; -constexpr unsigned int mmSQ_POWER_THROTTLE2__SI = 0x2397; -constexpr unsigned int mmSQ_POWER_THROTTLE__CI__VI = 0xF091; -constexpr unsigned int mmSQ_POWER_THROTTLE__SI = 0x2396; -constexpr unsigned int mmSQ_RANDOM_WAVE_PRI = 0x2303; -constexpr unsigned int mmSQ_REG_CREDITS = 0x2304; -constexpr unsigned int mmSQ_REG_TIMESTAMP__CI__VI = 0x2374; -constexpr unsigned int mmSQ_SEC_CNT__SI__CI = 0x23A1; -constexpr unsigned int mmSQ_SMRD__SI__CI = 0x237F; -constexpr unsigned int mmSQ_SOP1 = 0x237F; -constexpr unsigned int mmSQ_SOP2 = 0x237F; -constexpr unsigned int mmSQ_SOPC = 0x237F; -constexpr unsigned int mmSQ_SOPK = 0x237F; -constexpr unsigned int mmSQ_SOPP = 0x237F; -constexpr unsigned int mmSQ_TEX_CLK_CTRL__CI__VI = 0xF08F; -constexpr unsigned int mmSQ_TEX_CLK_CTRL__SI = 0x2361; -constexpr unsigned int mmSQ_THREAD_TRACE_BASE2__CI = 0x2385; -constexpr unsigned int mmSQ_THREAD_TRACE_CNTR = 0x2390; -constexpr unsigned int mmSQ_THREAD_TRACE_TOKEN_MASK2__CI = 0x2386; -constexpr unsigned int mmSQ_THREAD_TRACE_USERDATA_0__CI__VI = 0xC340; -constexpr unsigned int mmSQ_THREAD_TRACE_USERDATA_0__SI = 0x2388; -constexpr unsigned int mmSQ_THREAD_TRACE_USERDATA_1__CI__VI = 0xC341; -constexpr unsigned int mmSQ_THREAD_TRACE_USERDATA_1__SI = 0x2389; -constexpr unsigned int mmSQ_THREAD_TRACE_USERDATA_2__CI__VI = 0xC342; -constexpr unsigned int mmSQ_THREAD_TRACE_USERDATA_2__SI = 0x238A; -constexpr unsigned int mmSQ_THREAD_TRACE_USERDATA_3__CI__VI = 0xC343; -constexpr unsigned int mmSQ_THREAD_TRACE_USERDATA_3__SI = 0x238B; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_CMN = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_EVENT = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_INST = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 = 0x23B1; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 = 0x23B1; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_ISSUE = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_MISC = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 = 0x23B1; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__CI__VI = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__CI__VI = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 = 0x23B1; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_TIME__SI = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_WAVE = 0x23B0; -constexpr unsigned int mmSQ_THREAD_TRACE_WORD_WAVE_START = 0x23B0; -constexpr unsigned int mmSQ_TIME_HI = 0x237C; -constexpr unsigned int mmSQ_TIME_LO = 0x237D; -constexpr unsigned int mmSQ_VINTRP = 0x237F; -constexpr unsigned int mmSQ_VOP1 = 0x237F; -constexpr unsigned int mmSQ_VOP2 = 0x237F; -constexpr unsigned int mmSQ_VOP3_0 = 0x237F; -constexpr unsigned int mmSQ_VOP3_0_SDST_ENC = 0x237F; -constexpr unsigned int mmSQ_VOP3_1 = 0x237F; -constexpr unsigned int mmSQ_VOPC = 0x237F; -constexpr unsigned int mmSRBM_CHIP_REVISION = 0x039B; -constexpr unsigned int mmSRBM_CNTL = 0x0390; -constexpr unsigned int mmSRBM_DEBUG = 0x03A4; -constexpr unsigned int mmSRBM_DEBUG_CNTL = 0x0399; -constexpr unsigned int mmSRBM_DEBUG_DATA = 0x039A; -constexpr unsigned int mmSRBM_DEBUG_SNAPSHOT = 0x03A5; -constexpr unsigned int mmSRBM_GFX_CNTL = 0x0391; -constexpr unsigned int mmSRBM_INT_ACK = 0x03AA; -constexpr unsigned int mmSRBM_INT_CNTL = 0x03A8; -constexpr unsigned int mmSRBM_INT_STATUS = 0x03A9; -constexpr unsigned int mmSRBM_MC_CLKEN_CNTL__CI__VI = 0x03B3; -constexpr unsigned int mmSRBM_READ_ERROR = 0x03A6; -constexpr unsigned int mmSRBM_SAM_CLKEN_CNTL__CI__VI = 0x03B8; -constexpr unsigned int mmSRBM_SDMA_CLKEN_CNTL__CI__VI = 0x03B7; -constexpr unsigned int mmSRBM_SOFT_RESET = 0x0398; -constexpr unsigned int mmSRBM_STATUS = 0x0394; -constexpr unsigned int mmSRBM_STATUS2 = 0x0393; -constexpr unsigned int mmSRBM_SYS_CLKEN_CNTL = 0x03B4; -constexpr unsigned int mmSRBM_UVD_CLKEN_CNTL = 0x03B6; -constexpr unsigned int mmSRBM_VCE_CLKEN_CNTL = 0x03B5; -constexpr unsigned int mmSX_DEBUG_1 = 0x2418; -constexpr unsigned int mmSX_DEBUG_BUSY = 0x2414; -constexpr unsigned int mmSX_DEBUG_BUSY_2 = 0x2415; -constexpr unsigned int mmSX_DEBUG_BUSY_3 = 0x2416; -constexpr unsigned int mmSX_DEBUG_BUSY_4 = 0x2417; -constexpr unsigned int mmSX_PERFCOUNTER0_HI__CI__VI = 0xD241; -constexpr unsigned int mmSX_PERFCOUNTER0_HI__SI = 0x2421; -constexpr unsigned int mmSX_PERFCOUNTER0_LO__CI__VI = 0xD240; -constexpr unsigned int mmSX_PERFCOUNTER0_LO__SI = 0x2420; -constexpr unsigned int mmSX_PERFCOUNTER0_SELECT1__CI__VI = 0xDA44; -constexpr unsigned int mmSX_PERFCOUNTER0_SELECT__CI__VI = 0xDA40; -constexpr unsigned int mmSX_PERFCOUNTER0_SELECT__SI = 0x241C; -constexpr unsigned int mmSX_PERFCOUNTER1_HI__CI__VI = 0xD243; -constexpr unsigned int mmSX_PERFCOUNTER1_HI__SI = 0x2423; -constexpr unsigned int mmSX_PERFCOUNTER1_LO__CI__VI = 0xD242; -constexpr unsigned int mmSX_PERFCOUNTER1_LO__SI = 0x2422; -constexpr unsigned int mmSX_PERFCOUNTER1_SELECT1__CI__VI = 0xDA45; -constexpr unsigned int mmSX_PERFCOUNTER1_SELECT__CI__VI = 0xDA41; -constexpr unsigned int mmSX_PERFCOUNTER1_SELECT__SI = 0x241D; -constexpr unsigned int mmSX_PERFCOUNTER2_HI__CI__VI = 0xD245; -constexpr unsigned int mmSX_PERFCOUNTER2_HI__SI = 0x2425; -constexpr unsigned int mmSX_PERFCOUNTER2_LO__CI__VI = 0xD244; -constexpr unsigned int mmSX_PERFCOUNTER2_LO__SI = 0x2424; -constexpr unsigned int mmSX_PERFCOUNTER2_SELECT__CI__VI = 0xDA42; -constexpr unsigned int mmSX_PERFCOUNTER2_SELECT__SI = 0x241E; -constexpr unsigned int mmSX_PERFCOUNTER3_HI__CI__VI = 0xD247; -constexpr unsigned int mmSX_PERFCOUNTER3_HI__SI = 0x2427; -constexpr unsigned int mmSX_PERFCOUNTER3_LO__CI__VI = 0xD246; -constexpr unsigned int mmSX_PERFCOUNTER3_LO__SI = 0x2426; -constexpr unsigned int mmSX_PERFCOUNTER3_SELECT__CI__VI = 0xDA43; -constexpr unsigned int mmSX_PERFCOUNTER3_SELECT__SI = 0x241F; -constexpr unsigned int mmTARGET_AND_CURRENT_PROFILE_INDEX_1__SI = 0x021D; -constexpr unsigned int mmTARGET_AND_CURRENT_PROFILE_INDEX__SI = 0x01E6; -constexpr unsigned int mmTA_BC_BASE_ADDR = 0xA020; -constexpr unsigned int mmTA_BC_BASE_ADDR_HI__CI__VI = 0xA021; -constexpr unsigned int mmTA_CGTT_CTRL__CI__VI = 0xF09D; -constexpr unsigned int mmTA_CGTT_CTRL__SI = 0x2544; -constexpr unsigned int mmTA_CNTL = 0x2541; -constexpr unsigned int mmTA_CNTL_AUX = 0x2542; -constexpr unsigned int mmTA_CS_BC_BASE_ADDR_HI__CI__VI = 0xC381; -constexpr unsigned int mmTA_CS_BC_BASE_ADDR__CI__VI = 0xC380; -constexpr unsigned int mmTA_CS_BC_BASE_ADDR__SI = 0x2543; -constexpr unsigned int mmTA_DEBUG_DATA = 0x254D; -constexpr unsigned int mmTA_DEBUG_INDEX = 0x254C; -constexpr unsigned int mmTA_PERFCOUNTER0_HI__CI__VI = 0xD2C1; -constexpr unsigned int mmTA_PERFCOUNTER0_HI__SI = 0x2556; -constexpr unsigned int mmTA_PERFCOUNTER0_LO__CI__VI = 0xD2C0; -constexpr unsigned int mmTA_PERFCOUNTER0_LO__SI = 0x2555; -constexpr unsigned int mmTA_PERFCOUNTER0_SELECT1__CI__VI = 0xDAC1; -constexpr unsigned int mmTA_PERFCOUNTER0_SELECT__CI__VI = 0xDAC0; -constexpr unsigned int mmTA_PERFCOUNTER0_SELECT__SI = 0x2554; -constexpr unsigned int mmTA_PERFCOUNTER1_HI__CI__VI = 0xD2C3; -constexpr unsigned int mmTA_PERFCOUNTER1_HI__SI = 0x2562; -constexpr unsigned int mmTA_PERFCOUNTER1_LO__CI__VI = 0xD2C2; -constexpr unsigned int mmTA_PERFCOUNTER1_LO__SI = 0x2561; -constexpr unsigned int mmTA_PERFCOUNTER1_SELECT__CI__VI = 0xDAC2; -constexpr unsigned int mmTA_PERFCOUNTER1_SELECT__SI = 0x2560; -constexpr unsigned int mmTA_RESERVED_010C__CI__VI = 0x2543; -constexpr unsigned int mmTA_SCRATCH = 0x2564; -constexpr unsigned int mmTA_STATUS = 0x2548; -constexpr unsigned int mmTCA_CGTT_SCLK_CTRL__CI__VI = 0xF0AD; -constexpr unsigned int mmTCA_CGTT_SCLK_CTRL__SI = 0x2BC1; -constexpr unsigned int mmTCA_CTRL = 0x2BC0; -constexpr unsigned int mmTCA_PERFCOUNTER0_HI__CI__VI = 0xD391; -constexpr unsigned int mmTCA_PERFCOUNTER0_HI__SI = 0x2BD2; -constexpr unsigned int mmTCA_PERFCOUNTER0_LO__CI__VI = 0xD390; -constexpr unsigned int mmTCA_PERFCOUNTER0_LO__SI = 0x2BD1; -constexpr unsigned int mmTCA_PERFCOUNTER0_SELECT1__CI__VI = 0xDB91; -constexpr unsigned int mmTCA_PERFCOUNTER0_SELECT__CI__VI = 0xDB90; -constexpr unsigned int mmTCA_PERFCOUNTER0_SELECT__SI = 0x2BD0; -constexpr unsigned int mmTCA_PERFCOUNTER1_HI__CI__VI = 0xD393; -constexpr unsigned int mmTCA_PERFCOUNTER1_HI__SI = 0x2BD5; -constexpr unsigned int mmTCA_PERFCOUNTER1_LO__CI__VI = 0xD392; -constexpr unsigned int mmTCA_PERFCOUNTER1_LO__SI = 0x2BD4; -constexpr unsigned int mmTCA_PERFCOUNTER1_SELECT1__CI__VI = 0xDB93; -constexpr unsigned int mmTCA_PERFCOUNTER1_SELECT__CI__VI = 0xDB92; -constexpr unsigned int mmTCA_PERFCOUNTER1_SELECT__SI = 0x2BD3; -constexpr unsigned int mmTCA_PERFCOUNTER2_HI__CI__VI = 0xD395; -constexpr unsigned int mmTCA_PERFCOUNTER2_HI__SI = 0x2BD8; -constexpr unsigned int mmTCA_PERFCOUNTER2_LO__CI__VI = 0xD394; -constexpr unsigned int mmTCA_PERFCOUNTER2_LO__SI = 0x2BD7; -constexpr unsigned int mmTCA_PERFCOUNTER2_SELECT__CI__VI = 0xDB94; -constexpr unsigned int mmTCA_PERFCOUNTER2_SELECT__SI = 0x2BD6; -constexpr unsigned int mmTCA_PERFCOUNTER3_HI__CI__VI = 0xD397; -constexpr unsigned int mmTCA_PERFCOUNTER3_HI__SI = 0x2BDB; -constexpr unsigned int mmTCA_PERFCOUNTER3_LO__CI__VI = 0xD396; -constexpr unsigned int mmTCA_PERFCOUNTER3_LO__SI = 0x2BDA; -constexpr unsigned int mmTCA_PERFCOUNTER3_SELECT__CI__VI = 0xDB95; -constexpr unsigned int mmTCA_PERFCOUNTER3_SELECT__SI = 0x2BD9; -constexpr unsigned int mmTCC_CGTT_SCLK_CTRL__CI__VI = 0xF0AC; -constexpr unsigned int mmTCC_CGTT_SCLK_CTRL__SI = 0x2B81; -constexpr unsigned int mmTCC_CTRL = 0x2B80; -constexpr unsigned int mmTCC_EDC_COUNTER__SI__CI = 0x2B82; -constexpr unsigned int mmTCC_PERFCOUNTER0_HI__CI__VI = 0xD381; -constexpr unsigned int mmTCC_PERFCOUNTER0_HI__SI = 0x2B92; -constexpr unsigned int mmTCC_PERFCOUNTER0_LO__CI__VI = 0xD380; -constexpr unsigned int mmTCC_PERFCOUNTER0_LO__SI = 0x2B91; -constexpr unsigned int mmTCC_PERFCOUNTER0_SELECT1__CI__VI = 0xDB81; -constexpr unsigned int mmTCC_PERFCOUNTER0_SELECT__CI__VI = 0xDB80; -constexpr unsigned int mmTCC_PERFCOUNTER0_SELECT__SI = 0x2B90; -constexpr unsigned int mmTCC_PERFCOUNTER1_HI__CI__VI = 0xD383; -constexpr unsigned int mmTCC_PERFCOUNTER1_HI__SI = 0x2B95; -constexpr unsigned int mmTCC_PERFCOUNTER1_LO__CI__VI = 0xD382; -constexpr unsigned int mmTCC_PERFCOUNTER1_LO__SI = 0x2B94; -constexpr unsigned int mmTCC_PERFCOUNTER1_SELECT1__CI__VI = 0xDB83; -constexpr unsigned int mmTCC_PERFCOUNTER1_SELECT__CI__VI = 0xDB82; -constexpr unsigned int mmTCC_PERFCOUNTER1_SELECT__SI = 0x2B93; -constexpr unsigned int mmTCC_PERFCOUNTER2_HI__CI__VI = 0xD385; -constexpr unsigned int mmTCC_PERFCOUNTER2_HI__SI = 0x2B98; -constexpr unsigned int mmTCC_PERFCOUNTER2_LO__CI__VI = 0xD384; -constexpr unsigned int mmTCC_PERFCOUNTER2_LO__SI = 0x2B97; -constexpr unsigned int mmTCC_PERFCOUNTER2_SELECT__CI__VI = 0xDB84; -constexpr unsigned int mmTCC_PERFCOUNTER2_SELECT__SI = 0x2B96; -constexpr unsigned int mmTCC_PERFCOUNTER3_HI__CI__VI = 0xD387; -constexpr unsigned int mmTCC_PERFCOUNTER3_HI__SI = 0x2B9B; -constexpr unsigned int mmTCC_PERFCOUNTER3_LO__CI__VI = 0xD386; -constexpr unsigned int mmTCC_PERFCOUNTER3_LO__SI = 0x2B9A; -constexpr unsigned int mmTCC_PERFCOUNTER3_SELECT__CI__VI = 0xDB85; -constexpr unsigned int mmTCC_PERFCOUNTER3_SELECT__SI = 0x2B99; -constexpr unsigned int mmTCC_REDUNDANCY__CI__VI = 0x2B83; -constexpr unsigned int mmTCI_CNTL_1 = 0x2B62; -constexpr unsigned int mmTCI_CNTL_2 = 0x2B63; -constexpr unsigned int mmTCI_STATUS = 0x2B61; -constexpr unsigned int mmTCP_ADDR_CONFIG = 0x2B05; -constexpr unsigned int mmTCP_BUFFER_ADDR_HASH_CNTL = 0x2B16; -constexpr unsigned int mmTCP_CHAN_STEER_HI = 0x2B04; -constexpr unsigned int mmTCP_CHAN_STEER_LO = 0x2B03; -constexpr unsigned int mmTCP_CNTL = 0x2B02; -constexpr unsigned int mmTCP_CREDIT = 0x2B06; -constexpr unsigned int mmTCP_EDC_COUNTER__SI__CI = 0x2B17; -constexpr unsigned int mmTCP_INVALIDATE = 0x2B00; -constexpr unsigned int mmTCP_PERFCOUNTER0_HI__CI__VI = 0xD341; -constexpr unsigned int mmTCP_PERFCOUNTER0_HI__SI = 0x2B0A; -constexpr unsigned int mmTCP_PERFCOUNTER0_LO__CI__VI = 0xD340; -constexpr unsigned int mmTCP_PERFCOUNTER0_LO__SI = 0x2B0B; -constexpr unsigned int mmTCP_PERFCOUNTER0_SELECT1__CI__VI = 0xDB41; -constexpr unsigned int mmTCP_PERFCOUNTER0_SELECT__CI__VI = 0xDB40; -constexpr unsigned int mmTCP_PERFCOUNTER0_SELECT__SI = 0x2B09; -constexpr unsigned int mmTCP_PERFCOUNTER1_HI__CI__VI = 0xD343; -constexpr unsigned int mmTCP_PERFCOUNTER1_HI__SI = 0x2B0D; -constexpr unsigned int mmTCP_PERFCOUNTER1_LO__CI__VI = 0xD342; -constexpr unsigned int mmTCP_PERFCOUNTER1_LO__SI = 0x2B0E; -constexpr unsigned int mmTCP_PERFCOUNTER1_SELECT1__CI__VI = 0xDB43; -constexpr unsigned int mmTCP_PERFCOUNTER1_SELECT__CI__VI = 0xDB42; -constexpr unsigned int mmTCP_PERFCOUNTER1_SELECT__SI = 0x2B0C; -constexpr unsigned int mmTCP_PERFCOUNTER2_HI__CI__VI = 0xD345; -constexpr unsigned int mmTCP_PERFCOUNTER2_HI__SI = 0x2B10; -constexpr unsigned int mmTCP_PERFCOUNTER2_LO__CI__VI = 0xD344; -constexpr unsigned int mmTCP_PERFCOUNTER2_LO__SI = 0x2B11; -constexpr unsigned int mmTCP_PERFCOUNTER2_SELECT__CI__VI = 0xDB44; -constexpr unsigned int mmTCP_PERFCOUNTER2_SELECT__SI = 0x2B0F; -constexpr unsigned int mmTCP_PERFCOUNTER3_HI__CI__VI = 0xD347; -constexpr unsigned int mmTCP_PERFCOUNTER3_HI__SI = 0x2B13; -constexpr unsigned int mmTCP_PERFCOUNTER3_LO__CI__VI = 0xD346; -constexpr unsigned int mmTCP_PERFCOUNTER3_LO__SI = 0x2B14; -constexpr unsigned int mmTCP_PERFCOUNTER3_SELECT__CI__VI = 0xDB45; -constexpr unsigned int mmTCP_PERFCOUNTER3_SELECT__SI = 0x2B12; -constexpr unsigned int mmTCP_STATUS = 0x2B01; -constexpr unsigned int mmTCP_WATCH0_ADDR_H__CI__VI = 0x32A0; -constexpr unsigned int mmTCP_WATCH0_ADDR_L__CI__VI = 0x32A1; -constexpr unsigned int mmTCP_WATCH0_CNTL__CI__VI = 0x32A2; -constexpr unsigned int mmTCP_WATCH1_ADDR_H__CI__VI = 0x32A3; -constexpr unsigned int mmTCP_WATCH1_ADDR_L__CI__VI = 0x32A4; -constexpr unsigned int mmTCP_WATCH1_CNTL__CI__VI = 0x32A5; -constexpr unsigned int mmTCP_WATCH2_ADDR_H__CI__VI = 0x32A6; -constexpr unsigned int mmTCP_WATCH2_ADDR_L__CI__VI = 0x32A7; -constexpr unsigned int mmTCP_WATCH2_CNTL__CI__VI = 0x32A8; -constexpr unsigned int mmTCP_WATCH3_ADDR_H__CI__VI = 0x32A9; -constexpr unsigned int mmTCP_WATCH3_ADDR_L__CI__VI = 0x32AA; -constexpr unsigned int mmTCP_WATCH3_CNTL__CI__VI = 0x32AB; -constexpr unsigned int mmTCS_CGTT_SCLK_CTRL__CI = 0xF0AE; -constexpr unsigned int mmTCS_CTRL__CI = 0x2BE0; -constexpr unsigned int mmTCS_PERFCOUNTER0_HI__CI = 0xD3A1; -constexpr unsigned int mmTCS_PERFCOUNTER0_LO__CI = 0xD3A0; -constexpr unsigned int mmTCS_PERFCOUNTER0_SELECT1__CI = 0xDBA1; -constexpr unsigned int mmTCS_PERFCOUNTER0_SELECT__CI = 0xDBA0; -constexpr unsigned int mmTCS_PERFCOUNTER1_HI__CI = 0xD3A3; -constexpr unsigned int mmTCS_PERFCOUNTER1_LO__CI = 0xD3A2; -constexpr unsigned int mmTCS_PERFCOUNTER1_SELECT__CI = 0xDBA2; -constexpr unsigned int mmTCS_PERFCOUNTER2_HI__CI = 0xD3A5; -constexpr unsigned int mmTCS_PERFCOUNTER2_LO__CI = 0xD3A4; -constexpr unsigned int mmTCS_PERFCOUNTER2_SELECT__CI = 0xDBA3; -constexpr unsigned int mmTCS_PERFCOUNTER3_HI__CI = 0xD3A7; -constexpr unsigned int mmTCS_PERFCOUNTER3_LO__CI = 0xD3A6; -constexpr unsigned int mmTCS_PERFCOUNTER3_SELECT__CI = 0xDBA4; -constexpr unsigned int mmTC_CFG_L1_LOAD_POLICY0__CI__VI = 0x2B1A; -constexpr unsigned int mmTC_CFG_L1_LOAD_POLICY1__CI__VI = 0x2B1B; -constexpr unsigned int mmTC_CFG_L1_STORE_POLICY__CI__VI = 0x2B1C; -constexpr unsigned int mmTC_CFG_L1_VOLATILE__CI__VI = 0x2B22; -constexpr unsigned int mmTC_CFG_L2_ATOMIC_POLICY__CI__VI = 0x2B21; -constexpr unsigned int mmTC_CFG_L2_LOAD_POLICY0__CI__VI = 0x2B1D; -constexpr unsigned int mmTC_CFG_L2_LOAD_POLICY1__CI__VI = 0x2B1E; -constexpr unsigned int mmTC_CFG_L2_STORE_POLICY0__CI__VI = 0x2B1F; -constexpr unsigned int mmTC_CFG_L2_STORE_POLICY1__CI__VI = 0x2B20; -constexpr unsigned int mmTC_CFG_L2_VOLATILE__CI__VI = 0x2B23; -constexpr unsigned int mmTD_CGTT_CTRL__CI__VI = 0xF09C; -constexpr unsigned int mmTD_CGTT_CTRL__SI = 0x2527; -constexpr unsigned int mmTD_CNTL = 0x2525; -constexpr unsigned int mmTD_DEBUG_DATA = 0x2529; -constexpr unsigned int mmTD_DEBUG_INDEX = 0x2528; -constexpr unsigned int mmTD_PERFCOUNTER0_HI__CI__VI = 0xD301; -constexpr unsigned int mmTD_PERFCOUNTER0_HI__SI = 0x252E; -constexpr unsigned int mmTD_PERFCOUNTER0_LO__CI__VI = 0xD300; -constexpr unsigned int mmTD_PERFCOUNTER0_LO__SI = 0x252D; -constexpr unsigned int mmTD_PERFCOUNTER0_SELECT1__CI__VI = 0xDB01; -constexpr unsigned int mmTD_PERFCOUNTER0_SELECT__CI__VI = 0xDB00; -constexpr unsigned int mmTD_PERFCOUNTER0_SELECT__SI = 0x252C; -constexpr unsigned int mmTD_PERFCOUNTER1_HI__CI__VI = 0xD303; -constexpr unsigned int mmTD_PERFCOUNTER1_LO__CI__VI = 0xD302; -constexpr unsigned int mmTD_PERFCOUNTER1_SELECT__CI__VI = 0xDB02; -constexpr unsigned int mmTD_SCRATCH__CI__VI = 0x2533; -constexpr unsigned int mmTD_SCRATCH__SI = 0x2530; -constexpr unsigned int mmTD_STATUS = 0x2526; -constexpr unsigned int mmTHM_CLK_CNTL__SI = 0x019A; -constexpr unsigned int mmTMDS_CNTL__SI = 0x1C7C; -constexpr unsigned int mmTMDS_CONTROL0_FEEDBACK__SI = 0x1C7E; -constexpr unsigned int mmTMDS_CONTROL_CHAR__SI = 0x1C7D; -constexpr unsigned int mmTMDS_CTL0_1_GEN_CNTL__SI = 0x1C86; -constexpr unsigned int mmTMDS_CTL2_3_GEN_CNTL__SI = 0x1C87; -constexpr unsigned int mmTMDS_CTL_BITS__SI = 0x1C83; -constexpr unsigned int mmTMDS_DCBALANCER_CONTROL__SI = 0x1C84; -constexpr unsigned int mmTMDS_DEBUG__SI = 0x1C82; -constexpr unsigned int mmTMDS_STEREOSYNC_CTL_SEL__SI = 0x1C7F; -constexpr unsigned int mmTMDS_SYNC_CHAR_PATTERN_0_1__SI = 0x1C80; -constexpr unsigned int mmTMDS_SYNC_CHAR_PATTERN_2_3__SI = 0x1C81; -constexpr unsigned int mmUNIPHY_DATA_SYNCHRONIZATION__SI = 0x1984; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKA__SI = 0x1947; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKB__SI = 0x1948; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKC__SI = 0x194D; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKD__SI = 0x194E; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKE__SI = 0x1950; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKF__SI = 0x1951; -constexpr unsigned int mmUNIPHY_IMPCAL_PERIOD__SI = 0x1949; -constexpr unsigned int mmUNIPHY_REG_TEST_OUTPUT__SI = 0x1986; -constexpr unsigned int mmUSER_SQC_BANK_DISABLE = 0x2308; -constexpr unsigned int mmUVD_CGC_CTRL__SI__VI = 0x3D2C; -constexpr unsigned int mmUVD_CGC_GATE__SI__VI = 0x3D2A; -constexpr unsigned int mmUVD_CGC_STATUS__SI__VI = 0x3D2B; -constexpr unsigned int mmUVD_CONFIG__CI__VI = 0x0F93; -constexpr unsigned int mmUVD_CONFIG__SI = 0x0F98; -constexpr unsigned int mmUVD_CONTEXT_ID__SI__VI = 0x3DBD; -constexpr unsigned int mmUVD_CTX_DATA__SI__VI = 0x3D29; -constexpr unsigned int mmUVD_CTX_INDEX__SI__VI = 0x3D28; -constexpr unsigned int mmUVD_ENGINE_CNTL__SI__VI = 0x3BC6; -constexpr unsigned int mmUVD_GPCOM_VCPU_CMD__SI__VI = 0x3BC3; -constexpr unsigned int mmUVD_GPCOM_VCPU_DATA0__SI__VI = 0x3BC4; -constexpr unsigned int mmUVD_GPCOM_VCPU_DATA1__SI__VI = 0x3BC5; -constexpr unsigned int mmUVD_LMI_ADDR_EXT__SI__VI = 0x3D65; -constexpr unsigned int mmUVD_LMI_CTRL2__SI__VI = 0x3D3D; -constexpr unsigned int mmUVD_LMI_CTRL__SI__VI = 0x3D66; -constexpr unsigned int mmUVD_LMI_EXT40_ADDR__SI__VI = 0x3D26; -constexpr unsigned int mmUVD_LMI_STATUS__SI__VI = 0x3D67; -constexpr unsigned int mmUVD_LMI_SWAP_CNTL__SI__VI = 0x3D6D; -constexpr unsigned int mmUVD_MASTINT_EN__SI__VI = 0x3D40; -constexpr unsigned int mmUVD_MPC_CNTL__SI__VI = 0x3D77; -constexpr unsigned int mmUVD_MPC_SET_ALU__SI__VI = 0x3D7E; -constexpr unsigned int mmUVD_MPC_SET_MUXA0__SI__VI = 0x3D79; -constexpr unsigned int mmUVD_MPC_SET_MUXA1__SI__VI = 0x3D7A; -constexpr unsigned int mmUVD_MPC_SET_MUXB0__SI__VI = 0x3D7B; -constexpr unsigned int mmUVD_MPC_SET_MUXB1__SI__VI = 0x3D7C; -constexpr unsigned int mmUVD_MPC_SET_MUX__SI__VI = 0x3D7D; -constexpr unsigned int mmUVD_MP_SWAP_CNTL__SI__VI = 0x3D6F; -constexpr unsigned int mmUVD_RBC_IB_BASE__SI = 0x3DA1; -constexpr unsigned int mmUVD_RBC_IB_SIZE__SI__VI = 0x3DA2; -constexpr unsigned int mmUVD_RBC_RB_BASE__SI = 0x3DA3; -constexpr unsigned int mmUVD_RBC_RB_CNTL__SI__VI = 0x3DA9; -constexpr unsigned int mmUVD_RBC_RB_RPTR_ADDR__SI__VI = 0x3DAA; -constexpr unsigned int mmUVD_RBC_RB_RPTR__SI__VI = 0x3DA4; -constexpr unsigned int mmUVD_RBC_RB_WPTR__SI__VI = 0x3DA5; -constexpr unsigned int mmUVD_SEMA_ADDR_HIGH__SI__VI = 0x3BC1; -constexpr unsigned int mmUVD_SEMA_ADDR_LOW__SI__VI = 0x3BC0; -constexpr unsigned int mmUVD_SEMA_CMD__SI__VI = 0x3BC2; -constexpr unsigned int mmUVD_SEMA_CNTL__SI__VI = 0x3D00; -constexpr unsigned int mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SI__VI = 0x3DB3; -constexpr unsigned int mmUVD_SEMA_TIMEOUT_STATUS__SI__VI = 0x3DB0; -constexpr unsigned int mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__SI__VI = 0x3DB2; -constexpr unsigned int mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__SI__VI = 0x3DB1; -constexpr unsigned int mmUVD_SOFT_RESET__SI__VI = 0x3DA0; -constexpr unsigned int mmUVD_STATUS__SI__VI = 0x3DAF; -constexpr unsigned int mmUVD_VCPU_CACHE_OFFSET0__SI__VI = 0x3D82; -constexpr unsigned int mmUVD_VCPU_CACHE_OFFSET1__SI__VI = 0x3D84; -constexpr unsigned int mmUVD_VCPU_CACHE_OFFSET2__SI__VI = 0x3D86; -constexpr unsigned int mmUVD_VCPU_CACHE_SIZE0__SI__VI = 0x3D83; -constexpr unsigned int mmUVD_VCPU_CACHE_SIZE1__SI__VI = 0x3D85; -constexpr unsigned int mmUVD_VCPU_CACHE_SIZE2__SI__VI = 0x3D87; -constexpr unsigned int mmUVD_VCPU_CNTL__SI__VI = 0x3D98; -constexpr unsigned int mmVBLANK_STATUS__SI = 0x1AEF; -constexpr unsigned int mmVCE_CONFIG__CI__VI = 0x0F94; -constexpr unsigned int mmVGA25_PPLL_FB_DIV__SI = 0x00DE; -constexpr unsigned int mmVGA25_PPLL_POST_DIV__SI = 0x00E2; -constexpr unsigned int mmVGA25_PPLL_REF_DIV__SI = 0x00D9; -constexpr unsigned int mmVGA28_PPLL_FB_DIV__SI = 0x00DF; -constexpr unsigned int mmVGA28_PPLL_POST_DIV__SI = 0x00E4; -constexpr unsigned int mmVGA28_PPLL_REF_DIV__SI = 0x00DB; -constexpr unsigned int mmVGA41_PPLL_FB_DIV__SI = 0x00E0; -constexpr unsigned int mmVGA41_PPLL_POST_DIV__SI = 0x00E6; -constexpr unsigned int mmVGA41_PPLL_REF_DIV__SI = 0x00DD; -constexpr unsigned int mmVGA_CACHE_CONTROL__SI__VI = 0x00CB; -constexpr unsigned int mmVGA_DEBUG_READBACK_DATA__SI__VI = 0x00D7; -constexpr unsigned int mmVGA_DEBUG_READBACK_INDEX__SI__VI = 0x00D6; -constexpr unsigned int mmVGA_DISPBUF1_SURFACE_ADDR__SI__VI = 0x00C6; -constexpr unsigned int mmVGA_DISPBUF2_SURFACE_ADDR__SI__VI = 0x00C8; -constexpr unsigned int mmVGA_HDP_CONTROL__SI__VI = 0x00CA; -constexpr unsigned int mmVGA_HW_DEBUG__SI__VI = 0x00CF; -constexpr unsigned int mmVGA_INTERRUPT_CONTROL__SI__VI = 0x00D1; -constexpr unsigned int mmVGA_INTERRUPT_STATUS__SI__VI = 0x00D3; -constexpr unsigned int mmVGA_MAIN_CONTROL__SI__VI = 0x00D4; -constexpr unsigned int mmVGA_MEMORY_BASE_ADDRESS_HIGH__SI__VI = 0x00C9; -constexpr unsigned int mmVGA_MEMORY_BASE_ADDRESS__SI__VI = 0x00C4; -constexpr unsigned int mmVGA_MEM_READ_PAGE_ADDR__SI__VI = 0x0013; -constexpr unsigned int mmVGA_MEM_WRITE_PAGE_ADDR__SI__VI = 0x0012; -constexpr unsigned int mmVGA_MODE_CONTROL__SI__VI = 0x00C2; -constexpr unsigned int mmVGA_RENDER_CONTROL__SI__VI = 0x00C0; -constexpr unsigned int mmVGA_SEQUENCER_RESET_CONTROL__SI__VI = 0x00C1; -constexpr unsigned int mmVGA_SOURCE_SELECT__SI__VI = 0x00FC; -constexpr unsigned int mmVGA_STATUS_CLEAR__SI__VI = 0x00D2; -constexpr unsigned int mmVGA_STATUS__SI__VI = 0x00D0; -constexpr unsigned int mmVGA_SURFACE_PITCH_SELECT__SI__VI = 0x00C3; -constexpr unsigned int mmVGA_TEST_CONTROL__SI__VI = 0x00D5; -constexpr unsigned int mmVGA_TEST_DEBUG_DATA__SI__VI = 0x00C7; -constexpr unsigned int mmVGA_TEST_DEBUG_INDEX__SI__VI = 0x00C5; -constexpr unsigned int mmVGT_CACHE_INVALIDATION = 0x2231; -constexpr unsigned int mmVGT_CNTL_STATUS = 0x223C; -constexpr unsigned int mmVGT_DEBUG_CNTL = 0x2238; -constexpr unsigned int mmVGT_DEBUG_DATA = 0x2239; -constexpr unsigned int mmVGT_DMA_BASE = 0xA1FA; -constexpr unsigned int mmVGT_DMA_BASE_HI = 0xA1F9; -constexpr unsigned int mmVGT_DMA_CONTROL__CI__VI = 0x2272; -constexpr unsigned int mmVGT_DMA_DATA_FIFO_DEPTH = 0x222D; -constexpr unsigned int mmVGT_DMA_INDEX_TYPE = 0xA29F; -constexpr unsigned int mmVGT_DMA_LS_HS_CONFIG__CI__VI = 0x2273; -constexpr unsigned int mmVGT_DMA_MAX_SIZE = 0xA29E; -constexpr unsigned int mmVGT_DMA_NUM_INSTANCES = 0xA2A2; -constexpr unsigned int mmVGT_DMA_PRIMITIVE_TYPE__CI__VI = 0x2271; -constexpr unsigned int mmVGT_DMA_REQ_FIFO_DEPTH = 0x222E; -constexpr unsigned int mmVGT_DMA_SIZE = 0xA29D; -constexpr unsigned int mmVGT_DRAW_INITIATOR = 0xA1FC; -constexpr unsigned int mmVGT_DRAW_INIT_FIFO_DEPTH = 0x222F; -constexpr unsigned int mmVGT_ENHANCE = 0xA294; -constexpr unsigned int mmVGT_ESGS_RING_ITEMSIZE = 0xA2AB; -constexpr unsigned int mmVGT_ESGS_RING_SIZE__CI__VI = 0xC240; -constexpr unsigned int mmVGT_ESGS_RING_SIZE__SI = 0x2232; -constexpr unsigned int mmVGT_ES_PER_GS = 0xA296; -constexpr unsigned int mmVGT_EVENT_ADDRESS_REG = 0xA1FE; -constexpr unsigned int mmVGT_EVENT_INITIATOR = 0xA2A4; -constexpr unsigned int mmVGT_FIFO_DEPTHS = 0x2234; -constexpr unsigned int mmVGT_GROUP_DECR = 0xA28B; -constexpr unsigned int mmVGT_GROUP_FIRST_DECR = 0xA28A; -constexpr unsigned int mmVGT_GROUP_PRIM_TYPE = 0xA289; -constexpr unsigned int mmVGT_GROUP_VECT_0_CNTL = 0xA28C; -constexpr unsigned int mmVGT_GROUP_VECT_0_FMT_CNTL = 0xA28E; -constexpr unsigned int mmVGT_GROUP_VECT_1_CNTL = 0xA28D; -constexpr unsigned int mmVGT_GROUP_VECT_1_FMT_CNTL = 0xA28F; -constexpr unsigned int mmVGT_GSVS_RING_ITEMSIZE = 0xA2AC; -constexpr unsigned int mmVGT_GSVS_RING_OFFSET_1 = 0xA298; -constexpr unsigned int mmVGT_GSVS_RING_OFFSET_2 = 0xA299; -constexpr unsigned int mmVGT_GSVS_RING_OFFSET_3 = 0xA29A; -constexpr unsigned int mmVGT_GSVS_RING_SIZE__CI__VI = 0xC241; -constexpr unsigned int mmVGT_GSVS_RING_SIZE__SI = 0x2233; -constexpr unsigned int mmVGT_GS_INSTANCE_CNT = 0xA2E4; -constexpr unsigned int mmVGT_GS_MAX_VERT_OUT = 0xA2CE; -constexpr unsigned int mmVGT_GS_MODE = 0xA290; -constexpr unsigned int mmVGT_GS_ONCHIP_CNTL__CI__VI = 0xA291; -constexpr unsigned int mmVGT_GS_OUT_PRIM_TYPE = 0xA29B; -constexpr unsigned int mmVGT_GS_PER_ES = 0xA295; -constexpr unsigned int mmVGT_GS_PER_VS = 0xA297; -constexpr unsigned int mmVGT_GS_VERTEX_REUSE = 0x2235; -constexpr unsigned int mmVGT_GS_VERT_ITEMSIZE = 0xA2D7; -constexpr unsigned int mmVGT_GS_VERT_ITEMSIZE_1 = 0xA2D8; -constexpr unsigned int mmVGT_GS_VERT_ITEMSIZE_2 = 0xA2D9; -constexpr unsigned int mmVGT_GS_VERT_ITEMSIZE_3 = 0xA2DA; -constexpr unsigned int mmVGT_HOS_CNTL = 0xA285; -constexpr unsigned int mmVGT_HOS_MAX_TESS_LEVEL = 0xA286; -constexpr unsigned int mmVGT_HOS_MIN_TESS_LEVEL = 0xA287; -constexpr unsigned int mmVGT_HOS_REUSE_DEPTH = 0xA288; -constexpr unsigned int mmVGT_HS_OFFCHIP_PARAM__CI__VI = 0xC24F; -constexpr unsigned int mmVGT_HS_OFFCHIP_PARAM__SI = 0x226C; -constexpr unsigned int mmVGT_IMMED_DATA = 0xA1FD; -constexpr unsigned int mmVGT_INDEX_TYPE__CI__VI = 0xC243; -constexpr unsigned int mmVGT_INDEX_TYPE__SI = 0x2257; -constexpr unsigned int mmVGT_INDX_OFFSET = 0xA102; -constexpr unsigned int mmVGT_INSTANCE_STEP_RATE_0 = 0xA2A8; -constexpr unsigned int mmVGT_INSTANCE_STEP_RATE_1 = 0xA2A9; -constexpr unsigned int mmVGT_LAST_COPY_STATE = 0x2230; -constexpr unsigned int mmVGT_LS_HS_CONFIG = 0xA2D6; -constexpr unsigned int mmVGT_MAX_VTX_INDX = 0xA100; -constexpr unsigned int mmVGT_MC_LAT_CNTL = 0x2236; -constexpr unsigned int mmVGT_MIN_VTX_INDX = 0xA101; -constexpr unsigned int mmVGT_MULTI_PRIM_IB_RESET_EN = 0xA2A5; -constexpr unsigned int mmVGT_MULTI_PRIM_IB_RESET_INDX = 0xA103; -constexpr unsigned int mmVGT_NUM_INDICES__CI__VI = 0xC24C; -constexpr unsigned int mmVGT_NUM_INDICES__SI = 0x225C; -constexpr unsigned int mmVGT_NUM_INSTANCES__CI__VI = 0xC24D; -constexpr unsigned int mmVGT_NUM_INSTANCES__SI = 0x225D; -constexpr unsigned int mmVGT_OUTPUT_PATH_CNTL = 0xA284; -constexpr unsigned int mmVGT_OUT_DEALLOC_CNTL = 0xA317; -constexpr unsigned int mmVGT_PERFCOUNTER0_HI__CI__VI = 0xD091; -constexpr unsigned int mmVGT_PERFCOUNTER0_HI__SI = 0x224D; -constexpr unsigned int mmVGT_PERFCOUNTER0_LO__CI__VI = 0xD090; -constexpr unsigned int mmVGT_PERFCOUNTER0_LO__SI = 0x224C; -constexpr unsigned int mmVGT_PERFCOUNTER0_SELECT1__CI__VI = 0xD890; -constexpr unsigned int mmVGT_PERFCOUNTER0_SELECT__CI__VI = 0xD88C; -constexpr unsigned int mmVGT_PERFCOUNTER0_SELECT__SI = 0x2248; -constexpr unsigned int mmVGT_PERFCOUNTER1_HI__CI__VI = 0xD093; -constexpr unsigned int mmVGT_PERFCOUNTER1_HI__SI = 0x224F; -constexpr unsigned int mmVGT_PERFCOUNTER1_LO__CI__VI = 0xD092; -constexpr unsigned int mmVGT_PERFCOUNTER1_LO__SI = 0x224E; -constexpr unsigned int mmVGT_PERFCOUNTER1_SELECT1__CI__VI = 0xD891; -constexpr unsigned int mmVGT_PERFCOUNTER1_SELECT__CI__VI = 0xD88D; -constexpr unsigned int mmVGT_PERFCOUNTER1_SELECT__SI = 0x2249; -constexpr unsigned int mmVGT_PERFCOUNTER2_HI__CI__VI = 0xD095; -constexpr unsigned int mmVGT_PERFCOUNTER2_HI__SI = 0x2251; -constexpr unsigned int mmVGT_PERFCOUNTER2_LO__CI__VI = 0xD094; -constexpr unsigned int mmVGT_PERFCOUNTER2_LO__SI = 0x2250; -constexpr unsigned int mmVGT_PERFCOUNTER2_SELECT__CI__VI = 0xD88E; -constexpr unsigned int mmVGT_PERFCOUNTER2_SELECT__SI = 0x224A; -constexpr unsigned int mmVGT_PERFCOUNTER3_HI__CI__VI = 0xD097; -constexpr unsigned int mmVGT_PERFCOUNTER3_HI__SI = 0x2253; -constexpr unsigned int mmVGT_PERFCOUNTER3_LO__CI__VI = 0xD096; -constexpr unsigned int mmVGT_PERFCOUNTER3_LO__SI = 0x2252; -constexpr unsigned int mmVGT_PERFCOUNTER3_SELECT__CI__VI = 0xD88F; -constexpr unsigned int mmVGT_PERFCOUNTER3_SELECT__SI = 0x224B; -constexpr unsigned int mmVGT_PERFCOUNTER_SEID_MASK__CI__VI = 0xD894; -constexpr unsigned int mmVGT_PERFCOUNTER_SEID_MASK__SI = 0x2247; -constexpr unsigned int mmVGT_PRIMITIVEID_EN = 0xA2A1; -constexpr unsigned int mmVGT_PRIMITIVEID_RESET = 0xA2A3; -constexpr unsigned int mmVGT_PRIMITIVE_TYPE__CI__VI = 0xC242; -constexpr unsigned int mmVGT_PRIMITIVE_TYPE__SI = 0x2256; -constexpr unsigned int mmVGT_RESET_DEBUG__CI__VI = 0x2232; -constexpr unsigned int mmVGT_REUSE_OFF = 0xA2AD; -constexpr unsigned int mmVGT_SHADER_STAGES_EN = 0xA2D5; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_CONFIG = 0xA2E6; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0__CI__VI = 0xC244; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0__SI = 0x2258; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1__CI__VI = 0xC245; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1__SI = 0x2259; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2__CI__VI = 0xC246; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2__SI = 0x225A; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3__CI__VI = 0xC247; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3__SI = 0x225B; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_OFFSET_0 = 0xA2B7; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_OFFSET_1 = 0xA2BB; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_OFFSET_2 = 0xA2BF; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_OFFSET_3 = 0xA2C3; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_SIZE_0 = 0xA2B4; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_SIZE_1 = 0xA2B8; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_SIZE_2 = 0xA2BC; -constexpr unsigned int mmVGT_STRMOUT_BUFFER_SIZE_3 = 0xA2C0; -constexpr unsigned int mmVGT_STRMOUT_CONFIG = 0xA2E5; -constexpr unsigned int mmVGT_STRMOUT_DELAY__CI__VI = 0x2233; -constexpr unsigned int mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0xA2CB; -constexpr unsigned int mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0xA2CA; -constexpr unsigned int mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0xA2CC; -constexpr unsigned int mmVGT_STRMOUT_VTX_STRIDE_0 = 0xA2B5; -constexpr unsigned int mmVGT_STRMOUT_VTX_STRIDE_1 = 0xA2B9; -constexpr unsigned int mmVGT_STRMOUT_VTX_STRIDE_2 = 0xA2BD; -constexpr unsigned int mmVGT_STRMOUT_VTX_STRIDE_3 = 0xA2C1; -constexpr unsigned int mmVGT_SYS_CONFIG = 0x2263; -constexpr unsigned int mmVGT_TF_MEMORY_BASE__CI__VI = 0xC250; -constexpr unsigned int mmVGT_TF_MEMORY_BASE__SI = 0x226E; -constexpr unsigned int mmVGT_TF_PARAM = 0xA2DB; -constexpr unsigned int mmVGT_TF_RING_SIZE__CI__VI = 0xC24E; -constexpr unsigned int mmVGT_TF_RING_SIZE__SI = 0x2262; -constexpr unsigned int mmVGT_VERTEX_REUSE_BLOCK_CNTL = 0xA316; -constexpr unsigned int mmVGT_VS_MAX_WAVE_ID__CI__VI = 0x2268; -constexpr unsigned int mmVGT_VTX_CNT_EN = 0xA2AE; -constexpr unsigned int mmVGT_VTX_VECT_EJECT_REG = 0x222C; -constexpr unsigned int mmVIEWPORT_SIZE__SI__VI = 0x1B5D; -constexpr unsigned int mmVIEWPORT_START__SI__VI = 0x1B5C; -constexpr unsigned int mmVLINE_STATUS__SI = 0x1AEE; -constexpr unsigned int mmVM_CONTEXT0_CNTL = 0x0504; -constexpr unsigned int mmVM_CONTEXT0_CNTL2 = 0x050C; -constexpr unsigned int mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR = 0x054F; -constexpr unsigned int mmVM_CONTEXT0_PAGE_TABLE_END_ADDR = 0x055F; -constexpr unsigned int mmVM_CONTEXT0_PAGE_TABLE_START_ADDR = 0x0557; -constexpr unsigned int mmVM_CONTEXT0_PROTECTION_FAULT_ADDR = 0x053E; -constexpr unsigned int mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR = 0x0546; -constexpr unsigned int mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__CI__VI = 0x0538; -constexpr unsigned int mmVM_CONTEXT0_PROTECTION_FAULT_STATUS = 0x0536; -constexpr unsigned int mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR = 0x0510; -constexpr unsigned int mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR = 0x0511; -constexpr unsigned int mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR = 0x0512; -constexpr unsigned int mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR = 0x0513; -constexpr unsigned int mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR = 0x0514; -constexpr unsigned int mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR = 0x0515; -constexpr unsigned int mmVM_CONTEXT1_CNTL = 0x0505; -constexpr unsigned int mmVM_CONTEXT1_CNTL2 = 0x050D; -constexpr unsigned int mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR = 0x0550; -constexpr unsigned int mmVM_CONTEXT1_PAGE_TABLE_END_ADDR = 0x0560; -constexpr unsigned int mmVM_CONTEXT1_PAGE_TABLE_START_ADDR = 0x0558; -constexpr unsigned int mmVM_CONTEXT1_PROTECTION_FAULT_ADDR = 0x053F; -constexpr unsigned int mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR = 0x0547; -constexpr unsigned int mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__CI__VI = 0x0539; -constexpr unsigned int mmVM_CONTEXT1_PROTECTION_FAULT_STATUS = 0x0537; -constexpr unsigned int mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR = 0x0551; -constexpr unsigned int mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR = 0x0552; -constexpr unsigned int mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR = 0x0553; -constexpr unsigned int mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR = 0x0554; -constexpr unsigned int mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR = 0x0555; -constexpr unsigned int mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR = 0x0556; -constexpr unsigned int mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR = 0x050E; -constexpr unsigned int mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR = 0x050F; -constexpr unsigned int mmVM_CONTEXTS_DISABLE = 0x0535; -constexpr unsigned int mmVM_DEBUG = 0x056F; -constexpr unsigned int mmVM_DUMMY_PAGE_FAULT_ADDR = 0x0507; -constexpr unsigned int mmVM_DUMMY_PAGE_FAULT_CNTL = 0x0506; -constexpr unsigned int mmVM_FAULT_CLIENT_ID = 0x054E; -constexpr unsigned int mmVM_INVALIDATE_REQUEST = 0x051E; -constexpr unsigned int mmVM_INVALIDATE_RESPONSE = 0x051F; -constexpr unsigned int mmVM_L2_BANK_SELECT_MASKA = 0x0572; -constexpr unsigned int mmVM_L2_BANK_SELECT_MASKB = 0x0573; -constexpr unsigned int mmVM_L2_CG = 0x0570; -constexpr unsigned int mmVM_L2_CNTL = 0x0500; -constexpr unsigned int mmVM_L2_CNTL2 = 0x0501; -constexpr unsigned int mmVM_L2_CNTL3 = 0x0502; -constexpr unsigned int mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR = 0x0576; -constexpr unsigned int mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR = 0x0575; -constexpr unsigned int mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET = 0x0577; -constexpr unsigned int mmVM_L2_STATUS = 0x0503; -constexpr unsigned int mmVM_PRT_APERTURE0_HIGH_ADDR = 0x0530; -constexpr unsigned int mmVM_PRT_APERTURE0_LOW_ADDR = 0x052C; -constexpr unsigned int mmVM_PRT_APERTURE1_HIGH_ADDR = 0x0531; -constexpr unsigned int mmVM_PRT_APERTURE1_LOW_ADDR = 0x052D; -constexpr unsigned int mmVM_PRT_APERTURE2_HIGH_ADDR = 0x0532; -constexpr unsigned int mmVM_PRT_APERTURE2_LOW_ADDR = 0x052E; -constexpr unsigned int mmVM_PRT_APERTURE3_HIGH_ADDR = 0x0533; -constexpr unsigned int mmVM_PRT_APERTURE3_LOW_ADDR = 0x052F; -constexpr unsigned int mmVM_PRT_CNTL = 0x0534; -constexpr unsigned int mmWD_CNTL_STATUS__CI__VI = 0x223F; -constexpr unsigned int mmWD_DEBUG_CNTL__CI__VI = 0x223D; -constexpr unsigned int mmWD_DEBUG_DATA__CI__VI = 0x223E; -constexpr unsigned int mmWD_ENHANCE__CI__VI = 0xA2A0; -constexpr unsigned int mmWD_PERFCOUNTER0_HI__CI__VI = 0xD081; -constexpr unsigned int mmWD_PERFCOUNTER0_LO__CI__VI = 0xD080; -constexpr unsigned int mmWD_PERFCOUNTER0_SELECT__CI__VI = 0xD880; -constexpr unsigned int mmWD_PERFCOUNTER1_HI__CI__VI = 0xD083; -constexpr unsigned int mmWD_PERFCOUNTER1_LO__CI__VI = 0xD082; -constexpr unsigned int mmWD_PERFCOUNTER1_SELECT__CI__VI = 0xD881; -constexpr unsigned int mmWD_PERFCOUNTER2_HI__CI__VI = 0xD085; -constexpr unsigned int mmWD_PERFCOUNTER2_LO__CI__VI = 0xD084; -constexpr unsigned int mmWD_PERFCOUNTER2_SELECT__CI__VI = 0xD882; -constexpr unsigned int mmWD_PERFCOUNTER3_HI__CI__VI = 0xD087; -constexpr unsigned int mmWD_PERFCOUNTER3_LO__CI__VI = 0xD086; -constexpr unsigned int mmWD_PERFCOUNTER3_SELECT__CI__VI = 0xD883; -constexpr unsigned int mmXDMA_SLV_FLIP_PENDING__CI__VI = 0x046C; -constexpr unsigned int mmXDMA_SLV_FLIP_PENDING__SI = 0x0407; -constexpr unsigned int pciADAPTER_ID = 0x000B; -constexpr unsigned int pciADAPTER_ID_W = 0x0013; -constexpr unsigned int pciBASE_ADDR_1 = 0x0004; -constexpr unsigned int pciBASE_ADDR_2 = 0x0005; -constexpr unsigned int pciBASE_ADDR_3 = 0x0006; -constexpr unsigned int pciBASE_ADDR_4 = 0x0007; -constexpr unsigned int pciBASE_ADDR_5 = 0x0008; -constexpr unsigned int pciBASE_ADDR_6 = 0x0009; -constexpr unsigned int pciBASE_CLASS = 0x0002; -constexpr unsigned int pciBIST = 0x0003; -constexpr unsigned int pciCACHE_LINE = 0x0003; -constexpr unsigned int pciCAP_PTR = 0x000D; -constexpr unsigned int pciCOMMAND = 0x0001; -constexpr unsigned int pciDEVICE_CAP = 0x0017; -constexpr unsigned int pciDEVICE_CAP2 = 0x001F; -constexpr unsigned int pciDEVICE_CNTL = 0x0018; -constexpr unsigned int pciDEVICE_CNTL2 = 0x0020; -constexpr unsigned int pciDEVICE_ID = 0x0000; -constexpr unsigned int pciDEVICE_STATUS = 0x0018; -constexpr unsigned int pciDEVICE_STATUS2 = 0x0020; -constexpr unsigned int pciHEADER = 0x0003; -constexpr unsigned int pciINTERRUPT_LINE = 0x000F; -constexpr unsigned int pciINTERRUPT_PIN = 0x000F; -constexpr unsigned int pciLATENCY = 0x0003; -constexpr unsigned int pciLINK_CAP = 0x0019; -constexpr unsigned int pciLINK_CAP2 = 0x0021; -constexpr unsigned int pciLINK_CNTL = 0x001A; -constexpr unsigned int pciLINK_CNTL2 = 0x0022; -constexpr unsigned int pciLINK_STATUS = 0x001A; -constexpr unsigned int pciLINK_STATUS2 = 0x0022; -constexpr unsigned int pciMAX_LATENCY = 0x000F; -constexpr unsigned int pciMIN_GRANT = 0x000F; -constexpr unsigned int pciMSI_CAP_LIST = 0x0028; -constexpr unsigned int pciMSI_MSG_ADDR_HI = 0x002A; -constexpr unsigned int pciMSI_MSG_ADDR_LO = 0x0029; -constexpr unsigned int pciMSI_MSG_CNTL = 0x0028; -constexpr unsigned int pciMSI_MSG_DATA = 0x002A; -constexpr unsigned int pciMSI_MSG_DATA_64 = 0x002B; -constexpr unsigned int pciPCIE_ACS_CAP__CI__VI = 0x00A9; -constexpr unsigned int pciPCIE_ACS_CNTL__CI__VI = 0x00A9; -constexpr unsigned int pciPCIE_ACS_ENH_CAP_LIST__CI__VI = 0x00A8; -constexpr unsigned int pciPCIE_ADV_ERR_CAP_CNTL = 0x005A; -constexpr unsigned int pciPCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0054; -constexpr unsigned int pciPCIE_ATS_CAP__CI__VI = 0x00AD; -constexpr unsigned int pciPCIE_ATS_CNTL__CI__VI = 0x00AD; -constexpr unsigned int pciPCIE_ATS_ENH_CAP_LIST__CI__VI = 0x00AC; -constexpr unsigned int pciPCIE_BAR1_CAP__CI__VI = 0x0081; -constexpr unsigned int pciPCIE_BAR1_CNTL__CI__VI = 0x0082; -constexpr unsigned int pciPCIE_BAR2_CAP__CI__VI = 0x0083; -constexpr unsigned int pciPCIE_BAR2_CNTL__CI__VI = 0x0084; -constexpr unsigned int pciPCIE_BAR3_CAP__CI__VI = 0x0085; -constexpr unsigned int pciPCIE_BAR3_CNTL__CI__VI = 0x0086; -constexpr unsigned int pciPCIE_BAR4_CAP__CI__VI = 0x0087; -constexpr unsigned int pciPCIE_BAR4_CNTL__CI__VI = 0x0088; -constexpr unsigned int pciPCIE_BAR5_CAP__CI__VI = 0x0089; -constexpr unsigned int pciPCIE_BAR5_CNTL__CI__VI = 0x008A; -constexpr unsigned int pciPCIE_BAR6_CAP__CI__VI = 0x008B; -constexpr unsigned int pciPCIE_BAR6_CNTL__CI__VI = 0x008C; -constexpr unsigned int pciPCIE_BAR_ENH_CAP_LIST__CI__VI = 0x0080; -constexpr unsigned int pciPCIE_CAP = 0x0016; -constexpr unsigned int pciPCIE_CAP_LIST = 0x0016; -constexpr unsigned int pciPCIE_CORR_ERR_MASK = 0x0059; -constexpr unsigned int pciPCIE_CORR_ERR_STATUS = 0x0058; -constexpr unsigned int pciPCIE_DEV_SERIAL_NUM_DW1 = 0x0051; -constexpr unsigned int pciPCIE_DEV_SERIAL_NUM_DW2 = 0x0052; -constexpr unsigned int pciPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x0050; -constexpr unsigned int pciPCIE_DPA_CAP__CI__VI = 0x0095; -constexpr unsigned int pciPCIE_DPA_CNTL__CI__VI = 0x0097; -constexpr unsigned int pciPCIE_DPA_ENH_CAP_LIST__CI__VI = 0x0094; -constexpr unsigned int pciPCIE_DPA_LATENCY_INDICATOR__CI__VI = 0x0096; -constexpr unsigned int pciPCIE_DPA_STATUS__CI__VI = 0x0097; -constexpr unsigned int pciPCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI = 0x0098; -constexpr unsigned int pciPCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI = 0x0098; -constexpr unsigned int pciPCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI = 0x0098; -constexpr unsigned int pciPCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI = 0x0098; -constexpr unsigned int pciPCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI = 0x0099; -constexpr unsigned int pciPCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI = 0x0099; -constexpr unsigned int pciPCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI = 0x0099; -constexpr unsigned int pciPCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI = 0x0099; -constexpr unsigned int pciPCIE_HDR_LOG0 = 0x005B; -constexpr unsigned int pciPCIE_HDR_LOG1 = 0x005C; -constexpr unsigned int pciPCIE_HDR_LOG2 = 0x005D; -constexpr unsigned int pciPCIE_HDR_LOG3 = 0x005E; -constexpr unsigned int pciPCIE_LANE_0_EQUALIZATION_CNTL__CI__VI = 0x009F; -constexpr unsigned int pciPCIE_LANE_10_EQUALIZATION_CNTL__CI__VI = 0x00A4; -constexpr unsigned int pciPCIE_LANE_11_EQUALIZATION_CNTL__CI__VI = 0x00A4; -constexpr unsigned int pciPCIE_LANE_12_EQUALIZATION_CNTL__CI__VI = 0x00A5; -constexpr unsigned int pciPCIE_LANE_13_EQUALIZATION_CNTL__CI__VI = 0x00A5; -constexpr unsigned int pciPCIE_LANE_14_EQUALIZATION_CNTL__CI__VI = 0x00A6; -constexpr unsigned int pciPCIE_LANE_15_EQUALIZATION_CNTL__CI__VI = 0x00A6; -constexpr unsigned int pciPCIE_LANE_1_EQUALIZATION_CNTL__CI__VI = 0x009F; -constexpr unsigned int pciPCIE_LANE_2_EQUALIZATION_CNTL__CI__VI = 0x00A0; -constexpr unsigned int pciPCIE_LANE_3_EQUALIZATION_CNTL__CI__VI = 0x00A0; -constexpr unsigned int pciPCIE_LANE_4_EQUALIZATION_CNTL__CI__VI = 0x00A1; -constexpr unsigned int pciPCIE_LANE_5_EQUALIZATION_CNTL__CI__VI = 0x00A1; -constexpr unsigned int pciPCIE_LANE_6_EQUALIZATION_CNTL__CI__VI = 0x00A2; -constexpr unsigned int pciPCIE_LANE_7_EQUALIZATION_CNTL__CI__VI = 0x00A2; -constexpr unsigned int pciPCIE_LANE_8_EQUALIZATION_CNTL__CI__VI = 0x00A3; -constexpr unsigned int pciPCIE_LANE_9_EQUALIZATION_CNTL__CI__VI = 0x00A3; -constexpr unsigned int pciPCIE_LANE_ERROR_STATUS__CI__VI = 0x009E; -constexpr unsigned int pciPCIE_LINK_CNTL3__CI__VI = 0x009D; -constexpr unsigned int pciPCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI = 0x00B3; -constexpr unsigned int pciPCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI = 0x00B2; -constexpr unsigned int pciPCIE_PAGE_REQ_CNTL__CI__VI = 0x00B1; -constexpr unsigned int pciPCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI = 0x00B0; -constexpr unsigned int pciPCIE_PAGE_REQ_STATUS__CI__VI = 0x00B1; -constexpr unsigned int pciPCIE_PASID_CAP__CI__VI = 0x00B5; -constexpr unsigned int pciPCIE_PASID_CNTL__CI__VI = 0x00B5; -constexpr unsigned int pciPCIE_PASID_ENH_CAP_LIST__CI__VI = 0x00B4; -constexpr unsigned int pciPCIE_PORT_VC_CAP_REG1 = 0x0045; -constexpr unsigned int pciPCIE_PORT_VC_CAP_REG2 = 0x0046; -constexpr unsigned int pciPCIE_PORT_VC_CNTL = 0x0047; -constexpr unsigned int pciPCIE_PORT_VC_STATUS = 0x0047; -constexpr unsigned int pciPCIE_PWR_BUDGET_CAP__CI__VI = 0x0093; -constexpr unsigned int pciPCIE_PWR_BUDGET_DATA_SELECT__CI__VI = 0x0091; -constexpr unsigned int pciPCIE_PWR_BUDGET_DATA__CI__VI = 0x0092; -constexpr unsigned int pciPCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI = 0x0090; -constexpr unsigned int pciPCIE_SECONDARY_ENH_CAP_LIST__CI__VI = 0x009C; -constexpr unsigned int pciPCIE_TLP_PREFIX_LOG0__CI__VI = 0x0062; -constexpr unsigned int pciPCIE_TLP_PREFIX_LOG1__CI__VI = 0x0063; -constexpr unsigned int pciPCIE_TLP_PREFIX_LOG2__CI__VI = 0x0064; -constexpr unsigned int pciPCIE_TLP_PREFIX_LOG3__CI__VI = 0x0065; -constexpr unsigned int pciPCIE_UNCORR_ERR_MASK = 0x0056; -constexpr unsigned int pciPCIE_UNCORR_ERR_SEVERITY = 0x0057; -constexpr unsigned int pciPCIE_UNCORR_ERR_STATUS = 0x0055; -constexpr unsigned int pciPCIE_VC0_RESOURCE_CAP = 0x0048; -constexpr unsigned int pciPCIE_VC0_RESOURCE_CNTL = 0x0049; -constexpr unsigned int pciPCIE_VC0_RESOURCE_STATUS = 0x004A; -constexpr unsigned int pciPCIE_VC1_RESOURCE_CAP = 0x004B; -constexpr unsigned int pciPCIE_VC1_RESOURCE_CNTL = 0x004C; -constexpr unsigned int pciPCIE_VC1_RESOURCE_STATUS = 0x004D; -constexpr unsigned int pciPCIE_VC_ENH_CAP_LIST = 0x0044; -constexpr unsigned int pciPCIE_VENDOR_SPECIFIC1 = 0x0042; -constexpr unsigned int pciPCIE_VENDOR_SPECIFIC2 = 0x0043; -constexpr unsigned int pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0040; -constexpr unsigned int pciPCIE_VENDOR_SPECIFIC_HDR = 0x0041; -constexpr unsigned int pciPMI_CAP = 0x0014; -constexpr unsigned int pciPMI_CAP_LIST = 0x0014; -constexpr unsigned int pciPMI_STATUS_CNTL = 0x0015; -constexpr unsigned int pciPROG_INTERFACE = 0x0002; -constexpr unsigned int pciREVISION_ID = 0x0002; -constexpr unsigned int pciROM_BASE_ADDR = 0x000C; -constexpr unsigned int pciSTATUS = 0x0001; -constexpr unsigned int pciSUB_CLASS = 0x0002; -constexpr unsigned int pciVENDOR_CAP_LIST__CI__VI = 0x0012; -constexpr unsigned int pciVENDOR_ID = 0x0000; - -//Merged Defines - -constexpr unsigned int cfgMSI_MASK__VI = 0x002B; -constexpr unsigned int cfgMSI_MASK_64__VI = 0x002C; -constexpr unsigned int cfgMSI_PENDING__VI = 0x002C; -constexpr unsigned int cfgMSI_PENDING_64__VI = 0x002D; -constexpr unsigned int cfgPCIE_ARI_CAP__VI = 0x00CB; -constexpr unsigned int cfgPCIE_ARI_CNTL__VI = 0x00CB; -constexpr unsigned int cfgPCIE_ARI_ENH_CAP_LIST__VI = 0x00CA; -constexpr unsigned int cfgPCIE_LTR_CAP__VI = 0x00C9; -constexpr unsigned int cfgPCIE_LTR_ENH_CAP_LIST__VI = 0x00C8; -constexpr unsigned int cfgPCIE_MC_ADDR0__VI = 0x00BE; -constexpr unsigned int cfgPCIE_MC_ADDR1__VI = 0x00BF; -constexpr unsigned int cfgPCIE_MC_BLOCK_ALL0__VI = 0x00C2; -constexpr unsigned int cfgPCIE_MC_BLOCK_ALL1__VI = 0x00C3; -constexpr unsigned int cfgPCIE_MC_BLOCK_UNTRANSLATED_0__VI = 0x00C4; -constexpr unsigned int cfgPCIE_MC_BLOCK_UNTRANSLATED_1__VI = 0x00C5; -constexpr unsigned int cfgPCIE_MC_CAP__VI = 0x00BD; -constexpr unsigned int cfgPCIE_MC_CNTL__VI = 0x00BD; -constexpr unsigned int cfgPCIE_MC_ENH_CAP_LIST__VI = 0x00BC; -constexpr unsigned int cfgPCIE_MC_RCV0__VI = 0x00C0; -constexpr unsigned int cfgPCIE_MC_RCV1__VI = 0x00C1; -constexpr unsigned int cfgPCIE_SRIOV_CAP__VI = 0x00CD; -constexpr unsigned int cfgPCIE_SRIOV_CONTROL__VI = 0x00CE; -constexpr unsigned int cfgPCIE_SRIOV_ENH_CAP_LIST__VI = 0x00CC; -constexpr unsigned int cfgPCIE_SRIOV_FIRST_VF_OFFSET__VI = 0x00D1; -constexpr unsigned int cfgPCIE_SRIOV_FUNC_DEP_LINK__VI = 0x00D0; -constexpr unsigned int cfgPCIE_SRIOV_INITIAL_VFS__VI = 0x00CF; -constexpr unsigned int cfgPCIE_SRIOV_NUM_VFS__VI = 0x00D0; -constexpr unsigned int cfgPCIE_SRIOV_STATUS__VI = 0x00CE; -constexpr unsigned int cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI = 0x00D3; -constexpr unsigned int cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE__VI = 0x00D4; -constexpr unsigned int cfgPCIE_SRIOV_TOTAL_VFS__VI = 0x00CF; -constexpr unsigned int cfgPCIE_SRIOV_VF_BASE_ADDR_0__VI = 0x00D5; -constexpr unsigned int cfgPCIE_SRIOV_VF_BASE_ADDR_1__VI = 0x00D6; -constexpr unsigned int cfgPCIE_SRIOV_VF_BASE_ADDR_2__VI = 0x00D7; -constexpr unsigned int cfgPCIE_SRIOV_VF_BASE_ADDR_3__VI = 0x00D8; -constexpr unsigned int cfgPCIE_SRIOV_VF_BASE_ADDR_4__VI = 0x00D9; -constexpr unsigned int cfgPCIE_SRIOV_VF_BASE_ADDR_5__VI = 0x00DA; -constexpr unsigned int cfgPCIE_SRIOV_VF_DEVICE_ID__VI = 0x00D2; -constexpr unsigned int cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI = 0x00DB; -constexpr unsigned int cfgPCIE_SRIOV_VF_STRIDE__VI = 0x00D1; -constexpr unsigned int cfgPCIE_TPH_REQR_CAP__VI = 0x00B9; -constexpr unsigned int cfgPCIE_TPH_REQR_CNTL__VI = 0x00BA; -constexpr unsigned int cfgPCIE_TPH_REQR_ENH_CAP_LIST__VI = 0x00B8; -constexpr unsigned int cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI = 0x0100; -constexpr unsigned int cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI = 0x0101; -constexpr unsigned int cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI = 0x0105; -constexpr unsigned int mmAFMT_60958_0__VI = 0x4A38; -constexpr unsigned int mmAFMT_60958_1__VI = 0x4A39; -constexpr unsigned int mmAFMT_60958_2__VI = 0x4A3F; -constexpr unsigned int mmAFMT_AUDIO_CRC_CONTROL__VI = 0x4A3A; -constexpr unsigned int mmAFMT_AUDIO_CRC_RESULT__VI = 0x4A40; -constexpr unsigned int mmAFMT_AUDIO_DBG_DTO_CNTL__VI = 0x4A46; -constexpr unsigned int mmAFMT_AUDIO_INFO0__VI = 0x4A36; -constexpr unsigned int mmAFMT_AUDIO_INFO1__VI = 0x4A37; -constexpr unsigned int mmAFMT_AUDIO_PACKET_CONTROL__VI = 0x4A42; -constexpr unsigned int mmAFMT_AUDIO_PACKET_CONTROL2__VI = 0x4A14; -constexpr unsigned int mmAFMT_AUDIO_SRC_CONTROL__VI = 0x4A45; -constexpr unsigned int mmAFMT_AVI_INFO0__VI = 0x4A1E; -constexpr unsigned int mmAFMT_AVI_INFO1__VI = 0x4A1F; -constexpr unsigned int mmAFMT_AVI_INFO2__VI = 0x4A20; -constexpr unsigned int mmAFMT_AVI_INFO3__VI = 0x4A21; -constexpr unsigned int mmAFMT_GENERIC_0__VI = 0x4A25; -constexpr unsigned int mmAFMT_GENERIC_1__VI = 0x4A26; -constexpr unsigned int mmAFMT_GENERIC_2__VI = 0x4A27; -constexpr unsigned int mmAFMT_GENERIC_3__VI = 0x4A28; -constexpr unsigned int mmAFMT_GENERIC_4__VI = 0x4A29; -constexpr unsigned int mmAFMT_GENERIC_5__VI = 0x4A2A; -constexpr unsigned int mmAFMT_GENERIC_6__VI = 0x4A2B; -constexpr unsigned int mmAFMT_GENERIC_7__VI = 0x4A2C; -constexpr unsigned int mmAFMT_GENERIC_HDR__VI = 0x4A24; -constexpr unsigned int mmAFMT_INFOFRAME_CONTROL0__VI = 0x4A44; -constexpr unsigned int mmAFMT_ISRC1_0__VI = 0x4A15; -constexpr unsigned int mmAFMT_ISRC1_1__VI = 0x4A16; -constexpr unsigned int mmAFMT_ISRC1_2__VI = 0x4A17; -constexpr unsigned int mmAFMT_ISRC1_3__VI = 0x4A18; -constexpr unsigned int mmAFMT_ISRC1_4__VI = 0x4A19; -constexpr unsigned int mmAFMT_ISRC2_0__VI = 0x4A1A; -constexpr unsigned int mmAFMT_ISRC2_1__VI = 0x4A1B; -constexpr unsigned int mmAFMT_ISRC2_2__VI = 0x4A1C; -constexpr unsigned int mmAFMT_ISRC2_3__VI = 0x4A1D; -constexpr unsigned int mmAFMT_MPEG_INFO0__VI = 0x4A22; -constexpr unsigned int mmAFMT_MPEG_INFO1__VI = 0x4A23; -constexpr unsigned int mmAFMT_RAMP_CONTROL0__VI = 0x4A3B; -constexpr unsigned int mmAFMT_RAMP_CONTROL1__VI = 0x4A3C; -constexpr unsigned int mmAFMT_RAMP_CONTROL2__VI = 0x4A3D; -constexpr unsigned int mmAFMT_RAMP_CONTROL3__VI = 0x4A3E; -constexpr unsigned int mmAFMT_STATUS__VI = 0x4A41; -constexpr unsigned int mmAFMT_VBI_PACKET_CONTROL__VI = 0x4A43; -constexpr unsigned int mmALPHA_CONTROL__VI = 0x1ABC; -constexpr unsigned int mmATC_ATS_FAULT_STATUS_INFO2__VI = 0x0CD2; -constexpr unsigned int mmATC_ATS_SMU_STATUS__VI = 0x0D08; -constexpr unsigned int mmATC_ATS_VMID_STATUS__VI = 0x0D07; -constexpr unsigned int mmATC_L1RD_DEBUG2_TLB__VI = 0x0CE2; -constexpr unsigned int mmATC_L1WR_DEBUG2_TLB__VI = 0x0CE3; -constexpr unsigned int mmATC_L2_CACHE_DATA0__VI = 0x0CD9; -constexpr unsigned int mmATC_L2_CACHE_DATA1__VI = 0x0CDA; -constexpr unsigned int mmATC_L2_CACHE_DATA2__VI = 0x0CDB; -constexpr unsigned int mmATC_L2_CNTL3__VI = 0x0D08; -constexpr unsigned int mmATC_L2_STATUS__VI = 0x0D09; -constexpr unsigned int mmATC_L2_STATUS2__VI = 0x0D0A; -constexpr unsigned int mmAUXN_IMPCAL__VI = 0x483C; -constexpr unsigned int mmAUXP_IMPCAL__VI = 0x483B; -constexpr unsigned int mmAUX_ARB_CONTROL__VI = 0x5C02; -constexpr unsigned int mmAUX_CONTROL__VI = 0x5C00; -constexpr unsigned int mmAUX_DPHY_RX_CONTROL0__VI = 0x5C0A; -constexpr unsigned int mmAUX_DPHY_RX_CONTROL1__VI = 0x5C0B; -constexpr unsigned int mmAUX_DPHY_RX_STATUS__VI = 0x5C0D; -constexpr unsigned int mmAUX_DPHY_TX_CONTROL__VI = 0x5C09; -constexpr unsigned int mmAUX_DPHY_TX_REF_CONTROL__VI = 0x5C08; -constexpr unsigned int mmAUX_DPHY_TX_STATUS__VI = 0x5C0C; -constexpr unsigned int mmAUX_GTC_SYNC_CONTROL__VI = 0x5C0E; -constexpr unsigned int mmAUX_GTC_SYNC_CONTROLLER_STATUS__VI = 0x5C10; -constexpr unsigned int mmAUX_GTC_SYNC_DATA__VI = 0x5C12; -constexpr unsigned int mmAUX_GTC_SYNC_ERROR_CONTROL__VI = 0x5C0F; -constexpr unsigned int mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI = 0x5C13; -constexpr unsigned int mmAUX_GTC_SYNC_STATUS__VI = 0x5C11; -constexpr unsigned int mmAUX_INTERRUPT_CONTROL__VI = 0x5C03; -constexpr unsigned int mmAUX_LS_DATA__VI = 0x5C07; -constexpr unsigned int mmAUX_LS_STATUS__VI = 0x5C05; -constexpr unsigned int mmAUX_SW_CONTROL__VI = 0x5C01; -constexpr unsigned int mmAUX_SW_DATA__VI = 0x5C06; -constexpr unsigned int mmAUX_SW_STATUS__VI = 0x5C04; -constexpr unsigned int mmAUX_TEST_DEBUG_DATA__VI = 0x5C15; -constexpr unsigned int mmAUX_TEST_DEBUG_INDEX__VI = 0x5C14; -constexpr unsigned int mmAVSYNC_COUNTER_CONTROL__VI = 0x012B; -constexpr unsigned int mmAVSYNC_COUNTER_READ__VI = 0x012F; -constexpr unsigned int mmAVSYNC_COUNTER_WRITE__VI = 0x012A; -constexpr unsigned int mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__VI = 0x17F3; -constexpr unsigned int mmAZALIA_AUDIO_DTO__VI = 0x17E5; -constexpr unsigned int mmAZALIA_AUDIO_DTO_CONTROL__VI = 0x17E6; -constexpr unsigned int mmAZALIA_BDL_DMA_CONTROL__VI = 0x17EA; -constexpr unsigned int mmAZALIA_CONTROLLER_CLOCK_GATING__VI = 0x17E4; -constexpr unsigned int mmAZALIA_CONTROLLER_DEBUG__VI = 0x17F9; -constexpr unsigned int mmAZALIA_CORB_DMA_CONTROL__VI = 0x17EC; -constexpr unsigned int mmAZALIA_CRC0_CONTROL0__VI = 0x1805; -constexpr unsigned int mmAZALIA_CRC0_CONTROL1__VI = 0x1806; -constexpr unsigned int mmAZALIA_CRC0_CONTROL2__VI = 0x1807; -constexpr unsigned int mmAZALIA_CRC0_CONTROL3__VI = 0x1808; -constexpr unsigned int mmAZALIA_CRC0_RESULT__VI = 0x1809; -constexpr unsigned int mmAZALIA_CRC1_CONTROL0__VI = 0x180A; -constexpr unsigned int mmAZALIA_CRC1_CONTROL1__VI = 0x180B; -constexpr unsigned int mmAZALIA_CRC1_CONTROL2__VI = 0x180C; -constexpr unsigned int mmAZALIA_CRC1_CONTROL3__VI = 0x180D; -constexpr unsigned int mmAZALIA_CRC1_RESULT__VI = 0x180E; -constexpr unsigned int mmAZALIA_CYCLIC_BUFFER_SYNC__VI = 0x17F4; -constexpr unsigned int mmAZALIA_DATA_DMA_CONTROL__VI = 0x17E9; -constexpr unsigned int mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__VI = 0x182A; -constexpr unsigned int mmAZALIA_F0_CODEC_DEBUG__VI = 0x1836; -constexpr unsigned int mmAZALIA_F0_CODEC_ENDPOINT_DATA__VI = 0x17A9; -constexpr unsigned int mmAZALIA_F0_CODEC_ENDPOINT_INDEX__VI = 0x17A8; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__VI = 0x1833; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__VI = 0x1830; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__VI = 0x1831; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__VI = 0x1832; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__VI = 0x182C; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__VI = 0x182F; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__VI = 0x182E; -constexpr unsigned int mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__VI = 0x182D; -constexpr unsigned int mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI = 0x59D5; -constexpr unsigned int mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI = 0x59D4; -constexpr unsigned int mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__VI = 0x182B; -constexpr unsigned int mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__VI = 0x1829; -constexpr unsigned int mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__VI = 0x1828; -constexpr unsigned int mmAZALIA_F0_GTC_GROUP_OFFSET0__VI = 0x1837; -constexpr unsigned int mmAZALIA_F0_GTC_GROUP_OFFSET1__VI = 0x1838; -constexpr unsigned int mmAZALIA_F0_GTC_GROUP_OFFSET2__VI = 0x1839; -constexpr unsigned int mmAZALIA_F0_GTC_GROUP_OFFSET3__VI = 0x183A; -constexpr unsigned int mmAZALIA_F0_GTC_GROUP_OFFSET4__VI = 0x183B; -constexpr unsigned int mmAZALIA_F0_GTC_GROUP_OFFSET5__VI = 0x183C; -constexpr unsigned int mmAZALIA_F0_GTC_GROUP_OFFSET6__VI = 0x183D; -constexpr unsigned int mmAZALIA_GLOBAL_CAPABILITIES__VI = 0x17F5; -constexpr unsigned int mmAZALIA_INPUT_CRC0_CONTROL0__VI = 0x17FB; -constexpr unsigned int mmAZALIA_INPUT_CRC0_CONTROL1__VI = 0x17FC; -constexpr unsigned int mmAZALIA_INPUT_CRC0_CONTROL2__VI = 0x17FD; -constexpr unsigned int mmAZALIA_INPUT_CRC0_CONTROL3__VI = 0x17FE; -constexpr unsigned int mmAZALIA_INPUT_CRC0_RESULT__VI = 0x17FF; -constexpr unsigned int mmAZALIA_INPUT_CRC1_CONTROL0__VI = 0x1800; -constexpr unsigned int mmAZALIA_INPUT_CRC1_CONTROL1__VI = 0x1801; -constexpr unsigned int mmAZALIA_INPUT_CRC1_CONTROL2__VI = 0x1802; -constexpr unsigned int mmAZALIA_INPUT_CRC1_CONTROL3__VI = 0x1803; -constexpr unsigned int mmAZALIA_INPUT_CRC1_RESULT__VI = 0x1804; -constexpr unsigned int mmAZALIA_INPUT_PAYLOAD_CAPABILITY__VI = 0x17F8; -constexpr unsigned int mmAZALIA_MEM_PWR_CTRL__VI = 0x1810; -constexpr unsigned int mmAZALIA_MEM_PWR_STATUS__VI = 0x1811; -constexpr unsigned int mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY__VI = 0x17F6; -constexpr unsigned int mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL__VI = 0x17F7; -constexpr unsigned int mmAZALIA_RIRB_AND_DP_CONTROL__VI = 0x17EB; -constexpr unsigned int mmAZALIA_SCLK_CONTROL__VI = 0x17E7; -constexpr unsigned int mmAZALIA_STREAM_DATA__VI = 0x1781; -constexpr unsigned int mmAZALIA_STREAM_INDEX__VI = 0x1780; -constexpr unsigned int mmAZALIA_UNDERFLOW_FILLER_SAMPLE__VI = 0x17E8; -constexpr unsigned int mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__VI = 0x17A9; -constexpr unsigned int mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI = 0x17A8; -constexpr unsigned int mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__VI = 0x17AD; -constexpr unsigned int mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI = 0x17AC; -constexpr unsigned int mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__VI = 0x17B1; -constexpr unsigned int mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI = 0x17B0; -constexpr unsigned int mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__VI = 0x17B5; -constexpr unsigned int mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI = 0x17B4; -constexpr unsigned int mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__VI = 0x17B9; -constexpr unsigned int mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI = 0x17B8; -constexpr unsigned int mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__VI = 0x17BD; -constexpr unsigned int mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI = 0x17BC; -constexpr unsigned int mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__VI = 0x17C1; -constexpr unsigned int mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI = 0x17C0; -constexpr unsigned int mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__VI = 0x17C5; -constexpr unsigned int mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__VI = 0x17C4; -constexpr unsigned int mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI = 0x59D5; -constexpr unsigned int mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI = 0x59D4; -constexpr unsigned int mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI = 0x59D9; -constexpr unsigned int mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI = 0x59D8; -constexpr unsigned int mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI = 0x59DD; -constexpr unsigned int mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI = 0x59DC; -constexpr unsigned int mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI = 0x59E1; -constexpr unsigned int mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI = 0x59E0; -constexpr unsigned int mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI = 0x59E5; -constexpr unsigned int mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI = 0x59E4; -constexpr unsigned int mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI = 0x59E9; -constexpr unsigned int mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI = 0x59E8; -constexpr unsigned int mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI = 0x59ED; -constexpr unsigned int mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI = 0x59EC; -constexpr unsigned int mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI = 0x59F1; -constexpr unsigned int mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI = 0x59F0; -constexpr unsigned int mmAZF0STREAM0_AZALIA_STREAM_DATA__VI = 0x1781; -constexpr unsigned int mmAZF0STREAM0_AZALIA_STREAM_INDEX__VI = 0x1780; -constexpr unsigned int mmAZF0STREAM10_AZALIA_STREAM_DATA__VI = 0x59C5; -constexpr unsigned int mmAZF0STREAM10_AZALIA_STREAM_INDEX__VI = 0x59C4; -constexpr unsigned int mmAZF0STREAM11_AZALIA_STREAM_DATA__VI = 0x59C7; -constexpr unsigned int mmAZF0STREAM11_AZALIA_STREAM_INDEX__VI = 0x59C6; -constexpr unsigned int mmAZF0STREAM12_AZALIA_STREAM_DATA__VI = 0x59C9; -constexpr unsigned int mmAZF0STREAM12_AZALIA_STREAM_INDEX__VI = 0x59C8; -constexpr unsigned int mmAZF0STREAM13_AZALIA_STREAM_DATA__VI = 0x59CB; -constexpr unsigned int mmAZF0STREAM13_AZALIA_STREAM_INDEX__VI = 0x59CA; -constexpr unsigned int mmAZF0STREAM14_AZALIA_STREAM_DATA__VI = 0x59CD; -constexpr unsigned int mmAZF0STREAM14_AZALIA_STREAM_INDEX__VI = 0x59CC; -constexpr unsigned int mmAZF0STREAM15_AZALIA_STREAM_DATA__VI = 0x59CF; -constexpr unsigned int mmAZF0STREAM15_AZALIA_STREAM_INDEX__VI = 0x59CE; -constexpr unsigned int mmAZF0STREAM1_AZALIA_STREAM_DATA__VI = 0x1783; -constexpr unsigned int mmAZF0STREAM1_AZALIA_STREAM_INDEX__VI = 0x1782; -constexpr unsigned int mmAZF0STREAM2_AZALIA_STREAM_DATA__VI = 0x1785; -constexpr unsigned int mmAZF0STREAM2_AZALIA_STREAM_INDEX__VI = 0x1784; -constexpr unsigned int mmAZF0STREAM3_AZALIA_STREAM_DATA__VI = 0x1787; -constexpr unsigned int mmAZF0STREAM3_AZALIA_STREAM_INDEX__VI = 0x1786; -constexpr unsigned int mmAZF0STREAM4_AZALIA_STREAM_DATA__VI = 0x1789; -constexpr unsigned int mmAZF0STREAM4_AZALIA_STREAM_INDEX__VI = 0x1788; -constexpr unsigned int mmAZF0STREAM5_AZALIA_STREAM_DATA__VI = 0x178B; -constexpr unsigned int mmAZF0STREAM5_AZALIA_STREAM_INDEX__VI = 0x178A; -constexpr unsigned int mmAZF0STREAM6_AZALIA_STREAM_DATA__VI = 0x178D; -constexpr unsigned int mmAZF0STREAM6_AZALIA_STREAM_INDEX__VI = 0x178C; -constexpr unsigned int mmAZF0STREAM7_AZALIA_STREAM_DATA__VI = 0x178F; -constexpr unsigned int mmAZF0STREAM7_AZALIA_STREAM_INDEX__VI = 0x178E; -constexpr unsigned int mmAZF0STREAM8_AZALIA_STREAM_DATA__VI = 0x59C1; -constexpr unsigned int mmAZF0STREAM8_AZALIA_STREAM_INDEX__VI = 0x59C0; -constexpr unsigned int mmAZF0STREAM9_AZALIA_STREAM_DATA__VI = 0x59C3; -constexpr unsigned int mmAZF0STREAM9_AZALIA_STREAM_INDEX__VI = 0x59C2; -constexpr unsigned int mmAZ_TEST_DEBUG_DATA__VI = 0x1820; -constexpr unsigned int mmAZ_TEST_DEBUG_INDEX__VI = 0x181F; -constexpr unsigned int mmBF_ANA_ISO_CNTL__VI = 0x14C7; -constexpr unsigned int mmBIF_ATOMIC_ERR_LOG__VI = 0x1512; -constexpr unsigned int mmBIF_BME_STATUS__VI = 0x1511; -constexpr unsigned int mmBIF_CLK_CTRL__VI = 0x14C5; -constexpr unsigned int mmBIF_DOORBELL_APER_EN__VI = 0x1501; -constexpr unsigned int mmBIF_DOORBELL_GBLAPER1_LOWER__VI = 0x14FC; -constexpr unsigned int mmBIF_DOORBELL_GBLAPER1_UPPER__VI = 0x14FD; -constexpr unsigned int mmBIF_DOORBELL_GBLAPER2_LOWER__VI = 0x14FE; -constexpr unsigned int mmBIF_DOORBELL_GBLAPER2_UPPER__VI = 0x14FF; -constexpr unsigned int mmBIF_GPUIOV_FB_TOTAL_FB_INFO__VI = 0x14D8; -constexpr unsigned int mmBIF_GPUIOV_RESET_NOTIFICATION__VI = 0x14D5; -constexpr unsigned int mmBIF_GPUIOV_VM_INIT_STATUS__VI = 0x14D6; -constexpr unsigned int mmBIF_IOV_FUNC_IDENTIFIER__VI = 0x1503; -constexpr unsigned int mmBIF_MM_INDACCESS_CNTL__VI = 0x1500; -constexpr unsigned int mmBIF_MST_TRANS_PENDING__VI = 0x14EA; -constexpr unsigned int mmBIF_RB_BASE__VI = 0x1531; -constexpr unsigned int mmBIF_RB_CNTL__VI = 0x1530; -constexpr unsigned int mmBIF_RB_RPTR__VI = 0x1532; -constexpr unsigned int mmBIF_RB_WPTR__VI = 0x1533; -constexpr unsigned int mmBIF_RB_WPTR_ADDR_HI__VI = 0x1534; -constexpr unsigned int mmBIF_RB_WPTR_ADDR_LO__VI = 0x1535; -constexpr unsigned int mmBIF_RFE_MST_BX_CMDSTATUS__VI = 0x1449; -constexpr unsigned int mmBIF_RFE_MST_SMBUS_CMDSTATUS__VI = 0x1448; -constexpr unsigned int mmBIF_RFE_WARMRST_CNTL__VI = 0x1459; -constexpr unsigned int mmBIF_RLC_INTR_CNTL__VI = 0x1510; -constexpr unsigned int mmBIF_SLV_TRANS_PENDING__VI = 0x14E9; -constexpr unsigned int mmBIF_SMU_DATA__VI = 0x143E; -constexpr unsigned int mmBIF_SMU_INDEX__VI = 0x143D; -constexpr unsigned int mmBIF_VDDGFX_FB_CMP__VI = 0x143C; -constexpr unsigned int mmBIF_VDDGFX_GFX0_LOWER__VI = 0x1428; -constexpr unsigned int mmBIF_VDDGFX_GFX0_UPPER__VI = 0x1429; -constexpr unsigned int mmBIF_VDDGFX_GFX1_LOWER__VI = 0x142A; -constexpr unsigned int mmBIF_VDDGFX_GFX1_UPPER__VI = 0x142B; -constexpr unsigned int mmBIF_VDDGFX_GFX2_LOWER__VI = 0x142C; -constexpr unsigned int mmBIF_VDDGFX_GFX2_UPPER__VI = 0x142D; -constexpr unsigned int mmBIF_VDDGFX_GFX3_LOWER__VI = 0x142E; -constexpr unsigned int mmBIF_VDDGFX_GFX3_UPPER__VI = 0x142F; -constexpr unsigned int mmBIF_VDDGFX_GFX4_LOWER__VI = 0x1430; -constexpr unsigned int mmBIF_VDDGFX_GFX4_UPPER__VI = 0x1431; -constexpr unsigned int mmBIF_VDDGFX_GFX5_LOWER__VI = 0x1432; -constexpr unsigned int mmBIF_VDDGFX_GFX5_UPPER__VI = 0x1433; -constexpr unsigned int mmBIF_VDDGFX_RSV1_LOWER__VI = 0x1434; -constexpr unsigned int mmBIF_VDDGFX_RSV1_UPPER__VI = 0x1435; -constexpr unsigned int mmBIF_VDDGFX_RSV2_LOWER__VI = 0x1436; -constexpr unsigned int mmBIF_VDDGFX_RSV2_UPPER__VI = 0x1437; -constexpr unsigned int mmBIF_VDDGFX_RSV3_LOWER__VI = 0x1438; -constexpr unsigned int mmBIF_VDDGFX_RSV3_UPPER__VI = 0x1439; -constexpr unsigned int mmBIF_VDDGFX_RSV4_LOWER__VI = 0x143A; -constexpr unsigned int mmBIF_VDDGFX_RSV4_UPPER__VI = 0x143B; -constexpr unsigned int mmBIF_VIRT_RESET_REQ__VI = 0x14D2; -constexpr unsigned int mmBLND0_BLND_CONTROL__VI = 0x1B6D; -constexpr unsigned int mmBLND0_BLND_CONTROL2__VI = 0x1B6F; -constexpr unsigned int mmBLND0_BLND_DEBUG__VI = 0x1B74; -constexpr unsigned int mmBLND0_BLND_REG_UPDATE_STATUS__VI = 0x1B77; -constexpr unsigned int mmBLND0_BLND_TEST_DEBUG_DATA__VI = 0x1B76; -constexpr unsigned int mmBLND0_BLND_TEST_DEBUG_INDEX__VI = 0x1B75; -constexpr unsigned int mmBLND0_BLND_UNDERFLOW_INTERRUPT__VI = 0x1B71; -constexpr unsigned int mmBLND0_BLND_UPDATE__VI = 0x1B70; -constexpr unsigned int mmBLND0_BLND_V_UPDATE_LOCK__VI = 0x1B73; -constexpr unsigned int mmBLND0_SM_CONTROL2__VI = 0x1B6E; -constexpr unsigned int mmBLND1_BLND_CONTROL__VI = 0x1D6D; -constexpr unsigned int mmBLND1_BLND_CONTROL2__VI = 0x1D6F; -constexpr unsigned int mmBLND1_BLND_DEBUG__VI = 0x1D74; -constexpr unsigned int mmBLND1_BLND_REG_UPDATE_STATUS__VI = 0x1D77; -constexpr unsigned int mmBLND1_BLND_TEST_DEBUG_DATA__VI = 0x1D76; -constexpr unsigned int mmBLND1_BLND_TEST_DEBUG_INDEX__VI = 0x1D75; -constexpr unsigned int mmBLND1_BLND_UNDERFLOW_INTERRUPT__VI = 0x1D71; -constexpr unsigned int mmBLND1_BLND_UPDATE__VI = 0x1D70; -constexpr unsigned int mmBLND1_BLND_V_UPDATE_LOCK__VI = 0x1D73; -constexpr unsigned int mmBLND1_SM_CONTROL2__VI = 0x1D6E; -constexpr unsigned int mmBLND2_BLND_CONTROL__VI = 0x1F6D; -constexpr unsigned int mmBLND2_BLND_CONTROL2__VI = 0x1F6F; -constexpr unsigned int mmBLND2_BLND_DEBUG__VI = 0x1F74; -constexpr unsigned int mmBLND2_BLND_REG_UPDATE_STATUS__VI = 0x1F77; -constexpr unsigned int mmBLND2_BLND_TEST_DEBUG_DATA__VI = 0x1F76; -constexpr unsigned int mmBLND2_BLND_TEST_DEBUG_INDEX__VI = 0x1F75; -constexpr unsigned int mmBLND2_BLND_UNDERFLOW_INTERRUPT__VI = 0x1F71; -constexpr unsigned int mmBLND2_BLND_UPDATE__VI = 0x1F70; -constexpr unsigned int mmBLND2_BLND_V_UPDATE_LOCK__VI = 0x1F73; -constexpr unsigned int mmBLND2_SM_CONTROL2__VI = 0x1F6E; -constexpr unsigned int mmBLND3_BLND_CONTROL__VI = 0x416D; -constexpr unsigned int mmBLND3_BLND_CONTROL2__VI = 0x416F; -constexpr unsigned int mmBLND3_BLND_DEBUG__VI = 0x4174; -constexpr unsigned int mmBLND3_BLND_REG_UPDATE_STATUS__VI = 0x4177; -constexpr unsigned int mmBLND3_BLND_TEST_DEBUG_DATA__VI = 0x4176; -constexpr unsigned int mmBLND3_BLND_TEST_DEBUG_INDEX__VI = 0x4175; -constexpr unsigned int mmBLND3_BLND_UNDERFLOW_INTERRUPT__VI = 0x4171; -constexpr unsigned int mmBLND3_BLND_UPDATE__VI = 0x4170; -constexpr unsigned int mmBLND3_BLND_V_UPDATE_LOCK__VI = 0x4173; -constexpr unsigned int mmBLND3_SM_CONTROL2__VI = 0x416E; -constexpr unsigned int mmBLND4_BLND_CONTROL__VI = 0x436D; -constexpr unsigned int mmBLND4_BLND_CONTROL2__VI = 0x436F; -constexpr unsigned int mmBLND4_BLND_DEBUG__VI = 0x4374; -constexpr unsigned int mmBLND4_BLND_REG_UPDATE_STATUS__VI = 0x4377; -constexpr unsigned int mmBLND4_BLND_TEST_DEBUG_DATA__VI = 0x4376; -constexpr unsigned int mmBLND4_BLND_TEST_DEBUG_INDEX__VI = 0x4375; -constexpr unsigned int mmBLND4_BLND_UNDERFLOW_INTERRUPT__VI = 0x4371; -constexpr unsigned int mmBLND4_BLND_UPDATE__VI = 0x4370; -constexpr unsigned int mmBLND4_BLND_V_UPDATE_LOCK__VI = 0x4373; -constexpr unsigned int mmBLND4_SM_CONTROL2__VI = 0x436E; -constexpr unsigned int mmBLND5_BLND_CONTROL__VI = 0x456D; -constexpr unsigned int mmBLND5_BLND_CONTROL2__VI = 0x456F; -constexpr unsigned int mmBLND5_BLND_DEBUG__VI = 0x4574; -constexpr unsigned int mmBLND5_BLND_REG_UPDATE_STATUS__VI = 0x4577; -constexpr unsigned int mmBLND5_BLND_TEST_DEBUG_DATA__VI = 0x4576; -constexpr unsigned int mmBLND5_BLND_TEST_DEBUG_INDEX__VI = 0x4575; -constexpr unsigned int mmBLND5_BLND_UNDERFLOW_INTERRUPT__VI = 0x4571; -constexpr unsigned int mmBLND5_BLND_UPDATE__VI = 0x4570; -constexpr unsigned int mmBLND5_BLND_V_UPDATE_LOCK__VI = 0x4573; -constexpr unsigned int mmBLND5_SM_CONTROL2__VI = 0x456E; -constexpr unsigned int mmBLND6_BLND_CONTROL__VI = 0x476D; -constexpr unsigned int mmBLND6_BLND_CONTROL2__VI = 0x476F; -constexpr unsigned int mmBLND6_BLND_DEBUG__VI = 0x4774; -constexpr unsigned int mmBLND6_BLND_REG_UPDATE_STATUS__VI = 0x4777; -constexpr unsigned int mmBLND6_BLND_TEST_DEBUG_DATA__VI = 0x4776; -constexpr unsigned int mmBLND6_BLND_TEST_DEBUG_INDEX__VI = 0x4775; -constexpr unsigned int mmBLND6_BLND_UNDERFLOW_INTERRUPT__VI = 0x4771; -constexpr unsigned int mmBLND6_BLND_UPDATE__VI = 0x4770; -constexpr unsigned int mmBLND6_BLND_V_UPDATE_LOCK__VI = 0x4773; -constexpr unsigned int mmBLND6_SM_CONTROL2__VI = 0x476E; -constexpr unsigned int mmBLND_CONTROL__VI = 0x1B6D; -constexpr unsigned int mmBLND_CONTROL2__VI = 0x1B6F; -constexpr unsigned int mmBLND_DEBUG__VI = 0x1B74; -constexpr unsigned int mmBLND_REG_UPDATE_STATUS__VI = 0x1B77; -constexpr unsigned int mmBLND_TEST_DEBUG_DATA__VI = 0x1B76; -constexpr unsigned int mmBLND_TEST_DEBUG_INDEX__VI = 0x1B75; -constexpr unsigned int mmBLND_UNDERFLOW_INTERRUPT__VI = 0x1B71; -constexpr unsigned int mmBLND_UPDATE__VI = 0x1B70; -constexpr unsigned int mmBLND_V_UPDATE_LOCK__VI = 0x1B73; -constexpr unsigned int mmBL_PWM_CNTL__VI = 0x4820; -constexpr unsigned int mmBL_PWM_CNTL2__VI = 0x4821; -constexpr unsigned int mmBL_PWM_GRP1_REG_LOCK__VI = 0x4823; -constexpr unsigned int mmBL_PWM_PERIOD_CNTL__VI = 0x4822; -constexpr unsigned int mmBPHYC_DAC_AUTO_CALIB_CONTROL__VI = 0x48BA; -constexpr unsigned int mmBPHYC_DAC_MACRO_CNTL__VI = 0x48B9; -constexpr unsigned int mmBPHYC_PLL0_DISPPLL_BG_CNTL__VI = 0x171E; -constexpr unsigned int mmBPHYC_PLL0_PLL_ANALOG__VI = 0x1708; -constexpr unsigned int mmBPHYC_PLL0_PLL_ANALOG_CNTL__VI = 0x1711; -constexpr unsigned int mmBPHYC_PLL0_PLL_CNTL__VI = 0x1707; -constexpr unsigned int mmBPHYC_PLL0_PLL_DEBUG_CNTL__VI = 0x170B; -constexpr unsigned int mmBPHYC_PLL0_PLL_DS_CNTL__VI = 0x1705; -constexpr unsigned int mmBPHYC_PLL0_PLL_FB_DIV__VI = 0x1701; -constexpr unsigned int mmBPHYC_PLL0_PLL_IDCLK_CNTL__VI = 0x1706; -constexpr unsigned int mmBPHYC_PLL0_PLL_POST_DIV__VI = 0x1702; -constexpr unsigned int mmBPHYC_PLL0_PLL_REF_DIV__VI = 0x1700; -constexpr unsigned int mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC__VI = 0x1703; -constexpr unsigned int mmBPHYC_PLL0_PLL_SS_CNTL__VI = 0x1704; -constexpr unsigned int mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL__VI = 0x170A; -constexpr unsigned int mmBPHYC_PLL0_PLL_UPDATE_CNTL__VI = 0x170D; -constexpr unsigned int mmBPHYC_PLL0_PLL_UPDATE_LOCK__VI = 0x170C; -constexpr unsigned int mmBPHYC_PLL0_PLL_VREG_CNTL__VI = 0x1709; -constexpr unsigned int mmBPHYC_PLL0_PLL_XOR_LOCK__VI = 0x1710; -constexpr unsigned int mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL__VI = 0x1721; -constexpr unsigned int mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG__VI = 0x171F; -constexpr unsigned int mmBPHYC_PLL0_PPLL_SPARE0__VI = 0x1722; -constexpr unsigned int mmBPHYC_PLL0_PPLL_SPARE1__VI = 0x1723; -constexpr unsigned int mmBPHYC_PLL0_PPLL_STATUS_DEBUG__VI = 0x1720; -constexpr unsigned int mmBPHYC_PLL0_VGA25_PPLL_ANALOG__VI = 0x171B; -constexpr unsigned int mmBPHYC_PLL0_VGA25_PPLL_FB_DIV__VI = 0x1715; -constexpr unsigned int mmBPHYC_PLL0_VGA25_PPLL_POST_DIV__VI = 0x1718; -constexpr unsigned int mmBPHYC_PLL0_VGA25_PPLL_REF_DIV__VI = 0x1712; -constexpr unsigned int mmBPHYC_PLL0_VGA28_PPLL_ANALOG__VI = 0x171C; -constexpr unsigned int mmBPHYC_PLL0_VGA28_PPLL_FB_DIV__VI = 0x1716; -constexpr unsigned int mmBPHYC_PLL0_VGA28_PPLL_POST_DIV__VI = 0x1719; -constexpr unsigned int mmBPHYC_PLL0_VGA28_PPLL_REF_DIV__VI = 0x1713; -constexpr unsigned int mmBPHYC_PLL0_VGA41_PPLL_ANALOG__VI = 0x171D; -constexpr unsigned int mmBPHYC_PLL0_VGA41_PPLL_FB_DIV__VI = 0x1717; -constexpr unsigned int mmBPHYC_PLL0_VGA41_PPLL_POST_DIV__VI = 0x171A; -constexpr unsigned int mmBPHYC_PLL0_VGA41_PPLL_REF_DIV__VI = 0x1714; -constexpr unsigned int mmBPHYC_PLL1_DISPPLL_BG_CNTL__VI = 0x1748; -constexpr unsigned int mmBPHYC_PLL1_PLL_ANALOG__VI = 0x1732; -constexpr unsigned int mmBPHYC_PLL1_PLL_ANALOG_CNTL__VI = 0x173B; -constexpr unsigned int mmBPHYC_PLL1_PLL_CNTL__VI = 0x1731; -constexpr unsigned int mmBPHYC_PLL1_PLL_DEBUG_CNTL__VI = 0x1735; -constexpr unsigned int mmBPHYC_PLL1_PLL_DS_CNTL__VI = 0x172F; -constexpr unsigned int mmBPHYC_PLL1_PLL_FB_DIV__VI = 0x172B; -constexpr unsigned int mmBPHYC_PLL1_PLL_IDCLK_CNTL__VI = 0x1730; -constexpr unsigned int mmBPHYC_PLL1_PLL_POST_DIV__VI = 0x172C; -constexpr unsigned int mmBPHYC_PLL1_PLL_REF_DIV__VI = 0x172A; -constexpr unsigned int mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC__VI = 0x172D; -constexpr unsigned int mmBPHYC_PLL1_PLL_SS_CNTL__VI = 0x172E; -constexpr unsigned int mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL__VI = 0x1734; -constexpr unsigned int mmBPHYC_PLL1_PLL_UPDATE_CNTL__VI = 0x1737; -constexpr unsigned int mmBPHYC_PLL1_PLL_UPDATE_LOCK__VI = 0x1736; -constexpr unsigned int mmBPHYC_PLL1_PLL_VREG_CNTL__VI = 0x1733; -constexpr unsigned int mmBPHYC_PLL1_PLL_XOR_LOCK__VI = 0x173A; -constexpr unsigned int mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL__VI = 0x174B; -constexpr unsigned int mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG__VI = 0x1749; -constexpr unsigned int mmBPHYC_PLL1_PPLL_SPARE0__VI = 0x174C; -constexpr unsigned int mmBPHYC_PLL1_PPLL_SPARE1__VI = 0x174D; -constexpr unsigned int mmBPHYC_PLL1_PPLL_STATUS_DEBUG__VI = 0x174A; -constexpr unsigned int mmBPHYC_PLL1_VGA25_PPLL_ANALOG__VI = 0x1745; -constexpr unsigned int mmBPHYC_PLL1_VGA25_PPLL_FB_DIV__VI = 0x173F; -constexpr unsigned int mmBPHYC_PLL1_VGA25_PPLL_POST_DIV__VI = 0x1742; -constexpr unsigned int mmBPHYC_PLL1_VGA25_PPLL_REF_DIV__VI = 0x173C; -constexpr unsigned int mmBPHYC_PLL1_VGA28_PPLL_ANALOG__VI = 0x1746; -constexpr unsigned int mmBPHYC_PLL1_VGA28_PPLL_FB_DIV__VI = 0x1740; -constexpr unsigned int mmBPHYC_PLL1_VGA28_PPLL_POST_DIV__VI = 0x1743; -constexpr unsigned int mmBPHYC_PLL1_VGA28_PPLL_REF_DIV__VI = 0x173D; -constexpr unsigned int mmBPHYC_PLL1_VGA41_PPLL_ANALOG__VI = 0x1747; -constexpr unsigned int mmBPHYC_PLL1_VGA41_PPLL_FB_DIV__VI = 0x1741; -constexpr unsigned int mmBPHYC_PLL1_VGA41_PPLL_POST_DIV__VI = 0x1744; -constexpr unsigned int mmBPHYC_PLL1_VGA41_PPLL_REF_DIV__VI = 0x173E; -constexpr unsigned int mmBPHYC_PLL2_DISPPLL_BG_CNTL__VI = 0x1772; -constexpr unsigned int mmBPHYC_PLL2_PLL_ANALOG__VI = 0x175C; -constexpr unsigned int mmBPHYC_PLL2_PLL_ANALOG_CNTL__VI = 0x1765; -constexpr unsigned int mmBPHYC_PLL2_PLL_CNTL__VI = 0x175B; -constexpr unsigned int mmBPHYC_PLL2_PLL_DEBUG_CNTL__VI = 0x175F; -constexpr unsigned int mmBPHYC_PLL2_PLL_DS_CNTL__VI = 0x1759; -constexpr unsigned int mmBPHYC_PLL2_PLL_FB_DIV__VI = 0x1755; -constexpr unsigned int mmBPHYC_PLL2_PLL_IDCLK_CNTL__VI = 0x175A; -constexpr unsigned int mmBPHYC_PLL2_PLL_POST_DIV__VI = 0x1756; -constexpr unsigned int mmBPHYC_PLL2_PLL_REF_DIV__VI = 0x1754; -constexpr unsigned int mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC__VI = 0x1757; -constexpr unsigned int mmBPHYC_PLL2_PLL_SS_CNTL__VI = 0x1758; -constexpr unsigned int mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL__VI = 0x175E; -constexpr unsigned int mmBPHYC_PLL2_PLL_UPDATE_CNTL__VI = 0x1761; -constexpr unsigned int mmBPHYC_PLL2_PLL_UPDATE_LOCK__VI = 0x1760; -constexpr unsigned int mmBPHYC_PLL2_PLL_VREG_CNTL__VI = 0x175D; -constexpr unsigned int mmBPHYC_PLL2_PLL_XOR_LOCK__VI = 0x1764; -constexpr unsigned int mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL__VI = 0x1775; -constexpr unsigned int mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG__VI = 0x1773; -constexpr unsigned int mmBPHYC_PLL2_PPLL_SPARE0__VI = 0x1776; -constexpr unsigned int mmBPHYC_PLL2_PPLL_SPARE1__VI = 0x1777; -constexpr unsigned int mmBPHYC_PLL2_PPLL_STATUS_DEBUG__VI = 0x1774; -constexpr unsigned int mmBPHYC_PLL2_VGA25_PPLL_ANALOG__VI = 0x176F; -constexpr unsigned int mmBPHYC_PLL2_VGA25_PPLL_FB_DIV__VI = 0x1769; -constexpr unsigned int mmBPHYC_PLL2_VGA25_PPLL_POST_DIV__VI = 0x176C; -constexpr unsigned int mmBPHYC_PLL2_VGA25_PPLL_REF_DIV__VI = 0x1766; -constexpr unsigned int mmBPHYC_PLL2_VGA28_PPLL_ANALOG__VI = 0x1770; -constexpr unsigned int mmBPHYC_PLL2_VGA28_PPLL_FB_DIV__VI = 0x176A; -constexpr unsigned int mmBPHYC_PLL2_VGA28_PPLL_POST_DIV__VI = 0x176D; -constexpr unsigned int mmBPHYC_PLL2_VGA28_PPLL_REF_DIV__VI = 0x1767; -constexpr unsigned int mmBPHYC_PLL2_VGA41_PPLL_ANALOG__VI = 0x1771; -constexpr unsigned int mmBPHYC_PLL2_VGA41_PPLL_FB_DIV__VI = 0x176B; -constexpr unsigned int mmBPHYC_PLL2_VGA41_PPLL_POST_DIV__VI = 0x176E; -constexpr unsigned int mmBPHYC_PLL2_VGA41_PPLL_REF_DIV__VI = 0x1768; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL__VI = 0x48CC; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION__VI = 0x48CA; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_DEBUG__VI = 0x48D6; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1__VI = 0x48C6; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2__VI = 0x48C7; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV__VI = 0x48C5; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL__VI = 0x48C9; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE__VI = 0x48C8; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL__VI = 0x48C4; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT__VI = 0x48CB; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2__VI = 0x48CD; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL__VI = 0x48D4; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED__VI = 0x48D5; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1__VI = 0x48C0; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2__VI = 0x48C1; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3__VI = 0x48C2; -constexpr unsigned int mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4__VI = 0x48C3; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL__VI = 0x48EC; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION__VI = 0x48EA; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_DEBUG__VI = 0x48F6; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1__VI = 0x48E6; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2__VI = 0x48E7; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV__VI = 0x48E5; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL__VI = 0x48E9; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE__VI = 0x48E8; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL__VI = 0x48E4; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT__VI = 0x48EB; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2__VI = 0x48ED; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL__VI = 0x48F4; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED__VI = 0x48F5; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1__VI = 0x48E0; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2__VI = 0x48E1; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3__VI = 0x48E2; -constexpr unsigned int mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4__VI = 0x48E3; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL__VI = 0x490C; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION__VI = 0x490A; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_DEBUG__VI = 0x4916; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1__VI = 0x4906; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2__VI = 0x4907; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV__VI = 0x4905; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL__VI = 0x4909; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE__VI = 0x4908; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL__VI = 0x4904; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT__VI = 0x490B; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2__VI = 0x490D; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL__VI = 0x4914; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED__VI = 0x4915; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1__VI = 0x4900; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2__VI = 0x4901; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3__VI = 0x4902; -constexpr unsigned int mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4__VI = 0x4903; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL__VI = 0x492C; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION__VI = 0x492A; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_DEBUG__VI = 0x4936; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1__VI = 0x4926; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2__VI = 0x4927; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV__VI = 0x4925; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL__VI = 0x4929; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE__VI = 0x4928; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL__VI = 0x4924; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT__VI = 0x492B; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2__VI = 0x492D; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL__VI = 0x4934; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED__VI = 0x4935; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1__VI = 0x4920; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2__VI = 0x4921; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3__VI = 0x4922; -constexpr unsigned int mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4__VI = 0x4923; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL__VI = 0x494C; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION__VI = 0x494A; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_DEBUG__VI = 0x4956; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1__VI = 0x4946; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2__VI = 0x4947; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV__VI = 0x4945; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL__VI = 0x4949; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE__VI = 0x4948; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL__VI = 0x4944; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT__VI = 0x494B; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2__VI = 0x494D; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL__VI = 0x4954; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED__VI = 0x4955; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1__VI = 0x4940; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2__VI = 0x4941; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3__VI = 0x4942; -constexpr unsigned int mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4__VI = 0x4943; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL__VI = 0x496C; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION__VI = 0x496A; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_DEBUG__VI = 0x4976; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1__VI = 0x4966; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2__VI = 0x4967; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV__VI = 0x4965; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL__VI = 0x4969; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE__VI = 0x4968; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL__VI = 0x4964; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT__VI = 0x496B; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2__VI = 0x496D; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL__VI = 0x4974; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED__VI = 0x4975; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1__VI = 0x4960; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2__VI = 0x4961; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3__VI = 0x4962; -constexpr unsigned int mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4__VI = 0x4963; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL__VI = 0x498C; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION__VI = 0x498A; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_DEBUG__VI = 0x4996; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1__VI = 0x4986; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2__VI = 0x4987; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV__VI = 0x4985; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL__VI = 0x4989; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE__VI = 0x4988; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL__VI = 0x4984; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT__VI = 0x498B; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2__VI = 0x498D; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL__VI = 0x4994; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED__VI = 0x4995; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1__VI = 0x4980; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2__VI = 0x4981; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3__VI = 0x4982; -constexpr unsigned int mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4__VI = 0x4983; -constexpr unsigned int mmBX_RESET_CNTL__VI = 0x1518; -constexpr unsigned int mmCB_COLOR0_DCC_BASE__VI = 0xA325; -constexpr unsigned int mmCB_COLOR0_DCC_CONTROL__VI = 0xA31E; -constexpr unsigned int mmCB_COLOR1_DCC_BASE__VI = 0xA334; -constexpr unsigned int mmCB_COLOR1_DCC_CONTROL__VI = 0xA32D; -constexpr unsigned int mmCB_COLOR2_DCC_BASE__VI = 0xA343; -constexpr unsigned int mmCB_COLOR2_DCC_CONTROL__VI = 0xA33C; -constexpr unsigned int mmCB_COLOR3_DCC_BASE__VI = 0xA352; -constexpr unsigned int mmCB_COLOR3_DCC_CONTROL__VI = 0xA34B; -constexpr unsigned int mmCB_COLOR4_DCC_BASE__VI = 0xA361; -constexpr unsigned int mmCB_COLOR4_DCC_CONTROL__VI = 0xA35A; -constexpr unsigned int mmCB_COLOR5_DCC_BASE__VI = 0xA370; -constexpr unsigned int mmCB_COLOR5_DCC_CONTROL__VI = 0xA369; -constexpr unsigned int mmCB_COLOR6_DCC_BASE__VI = 0xA37F; -constexpr unsigned int mmCB_COLOR6_DCC_CONTROL__VI = 0xA378; -constexpr unsigned int mmCB_COLOR7_DCC_BASE__VI = 0xA38E; -constexpr unsigned int mmCB_COLOR7_DCC_CONTROL__VI = 0xA387; -constexpr unsigned int mmCB_DCC_CONFIG__VI = 0x2687; -constexpr unsigned int mmCB_DCC_CONTROL__VI = 0xA109; -constexpr unsigned int mmCB_DEBUG_BUS_19__VI = 0x26AB; -constexpr unsigned int mmCB_DEBUG_BUS_20__VI = 0x26AC; -constexpr unsigned int mmCB_DEBUG_BUS_21__VI = 0x26AD; -constexpr unsigned int mmCB_DEBUG_BUS_22__VI = 0x26AE; -constexpr unsigned int mmCC_DC_PIPE_DIS__VI = 0x0312; -constexpr unsigned int mmCC_GC_SHADER_RATE_CONFIG__VI = 0x2312; -constexpr unsigned int mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__VI = 0x1835; -constexpr unsigned int mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY__VI = 0x1834; -constexpr unsigned int mmCG_FPS_CNT__VI = 0x01B6; -constexpr unsigned int mmCLKREQB_PERF_COUNTER__VI = 0x1522; -constexpr unsigned int mmCNV_CSC_C11_C12__VI = 0x5E20; -constexpr unsigned int mmCNV_CSC_C13_C14__VI = 0x5E21; -constexpr unsigned int mmCNV_CSC_C21_C22__VI = 0x5E22; -constexpr unsigned int mmCNV_CSC_C23_C24__VI = 0x5E23; -constexpr unsigned int mmCNV_CSC_C31_C32__VI = 0x5E24; -constexpr unsigned int mmCNV_CSC_C33_C34__VI = 0x5E25; -constexpr unsigned int mmCNV_CSC_CLAMP_B__VI = 0x5E2B; -constexpr unsigned int mmCNV_CSC_CLAMP_G__VI = 0x5E2A; -constexpr unsigned int mmCNV_CSC_CLAMP_R__VI = 0x5E29; -constexpr unsigned int mmCNV_CSC_CONTROL__VI = 0x5E1F; -constexpr unsigned int mmCNV_CSC_ROUND_OFFSET_B__VI = 0x5E28; -constexpr unsigned int mmCNV_CSC_ROUND_OFFSET_G__VI = 0x5E27; -constexpr unsigned int mmCNV_CSC_ROUND_OFFSET_R__VI = 0x5E26; -constexpr unsigned int mmCNV_INPUT_SELECT__VI = 0x5E33; -constexpr unsigned int mmCNV_MODE__VI = 0x5E1A; -constexpr unsigned int mmCNV_SOURCE_SIZE__VI = 0x5E1E; -constexpr unsigned int mmCNV_TEST_CNTL__VI = 0x5E2C; -constexpr unsigned int mmCNV_TEST_CRC_BLUE__VI = 0x5E2F; -constexpr unsigned int mmCNV_TEST_CRC_GREEN__VI = 0x5E2E; -constexpr unsigned int mmCNV_TEST_CRC_RED__VI = 0x5E2D; -constexpr unsigned int mmCNV_TEST_DEBUG_DATA__VI = 0x5E35; -constexpr unsigned int mmCNV_TEST_DEBUG_INDEX__VI = 0x5E34; -constexpr unsigned int mmCNV_UPDATE__VI = 0x5E1D; -constexpr unsigned int mmCNV_WINDOW_SIZE__VI = 0x5E1C; -constexpr unsigned int mmCNV_WINDOW_START__VI = 0x5E1B; -constexpr unsigned int mmCOL_MAN_DEBUG_CONTROL__VI = 0x46E6; -constexpr unsigned int mmCOL_MAN_FP_CONVERTED_FIELD__VI = 0x46C7; -constexpr unsigned int mmCOL_MAN_INPUT_CSC_CONTROL__VI = 0x46A5; -constexpr unsigned int mmCOL_MAN_OUTPUT_CSC_CONTROL__VI = 0x46B6; -constexpr unsigned int mmCOL_MAN_TEST_DEBUG_DATA__VI = 0x46E5; -constexpr unsigned int mmCOL_MAN_TEST_DEBUG_INDEX__VI = 0x46E4; -constexpr unsigned int mmCOL_MAN_UPDATE__VI = 0x46A4; -constexpr unsigned int mmCOMM_MATRIXA_TRANS_C11_C12__VI = 0x1A43; -constexpr unsigned int mmCOMM_MATRIXA_TRANS_C13_C14__VI = 0x1A44; -constexpr unsigned int mmCOMM_MATRIXA_TRANS_C21_C22__VI = 0x1A45; -constexpr unsigned int mmCOMM_MATRIXA_TRANS_C23_C24__VI = 0x1A46; -constexpr unsigned int mmCOMM_MATRIXA_TRANS_C31_C32__VI = 0x1A47; -constexpr unsigned int mmCOMM_MATRIXA_TRANS_C33_C34__VI = 0x1A48; -constexpr unsigned int mmCOMM_MATRIXB_TRANS_C11_C12__VI = 0x1A49; -constexpr unsigned int mmCOMM_MATRIXB_TRANS_C13_C14__VI = 0x1A4A; -constexpr unsigned int mmCOMM_MATRIXB_TRANS_C21_C22__VI = 0x1A4B; -constexpr unsigned int mmCOMM_MATRIXB_TRANS_C23_C24__VI = 0x1A4C; -constexpr unsigned int mmCOMM_MATRIXB_TRANS_C31_C32__VI = 0x1A4D; -constexpr unsigned int mmCOMM_MATRIXB_TRANS_C33_C34__VI = 0x1A4E; -constexpr unsigned int mmCOMPUTE_DISPATCH_ID__VI = 0x2E20; -constexpr unsigned int mmCOMPUTE_NOWHERE__VI = 0x2E7F; -constexpr unsigned int mmCOMPUTE_RELAUNCH__VI = 0x2E22; -constexpr unsigned int mmCOMPUTE_THREADGROUP_ID__VI = 0x2E21; -constexpr unsigned int mmCOMPUTE_WAVE_RESTORE_ADDR_HI__VI = 0x2E24; -constexpr unsigned int mmCOMPUTE_WAVE_RESTORE_ADDR_LO__VI = 0x2E23; -constexpr unsigned int mmCOMPUTE_WAVE_RESTORE_CONTROL__VI = 0x2E25; -constexpr unsigned int mmCONFIG_RESERVED__VI = 0x1502; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED0__VI = 0x5FD0; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED1__VI = 0x5FD1; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED10__VI = 0x5FDA; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED11__VI = 0x5FDB; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED2__VI = 0x5FD2; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED3__VI = 0x5FD3; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED4__VI = 0x5FD4; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED5__VI = 0x5FD5; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED6__VI = 0x5FD6; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED7__VI = 0x5FD7; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED8__VI = 0x5FD8; -constexpr unsigned int mmCPLL_MACRO_CNTL_RESERVED9__VI = 0x5FD9; -constexpr unsigned int mmCPM_CONTROL__VI = 0x14B8; -constexpr unsigned int mmCP_CE_COMPLETION_STATUS__VI = 0xC0ED; -constexpr unsigned int mmCP_CE_METADATA_BASE_ADDR__VI = 0xC0F2; -constexpr unsigned int mmCP_CE_METADATA_BASE_ADDR_HI__VI = 0xC0F3; -constexpr unsigned int mmCP_CE_RB_OFFSET__VI = 0xC09B; -constexpr unsigned int mmCP_CE_UCODE_ADDR__SI__CI = 0x305A; -constexpr unsigned int mmCP_CE_UCODE_ADDR__VI = 0xF818; -constexpr unsigned int mmCP_CE_UCODE_DATA__SI__CI = 0x305B; -constexpr unsigned int mmCP_CE_UCODE_DATA__VI = 0xF819; -constexpr unsigned int mmCP_CONFIG__VI = 0x0F96; -constexpr unsigned int mmCP_CPC_IC_BASE_CNTL__VI = 0x30BB; -constexpr unsigned int mmCP_CPC_IC_BASE_HI__VI = 0x30BA; -constexpr unsigned int mmCP_CPC_IC_BASE_LO__VI = 0x30B9; -constexpr unsigned int mmCP_CPC_IC_OP_CNTL__VI = 0x30BC; -constexpr unsigned int mmCP_CPC_MGCG_SYNC_CNTL__VI = 0x3036; -constexpr unsigned int mmCP_DFY_CMD__VI = 0x3034; -constexpr unsigned int mmCP_DISPATCH_INDR_ADDR__VI = 0xC0F6; -constexpr unsigned int mmCP_DISPATCH_INDR_ADDR_HI__VI = 0xC0F7; -constexpr unsigned int mmCP_DRAW_INDX_INDR_ADDR__VI = 0xC0F4; -constexpr unsigned int mmCP_DRAW_INDX_INDR_ADDR_HI__VI = 0xC0F5; -constexpr unsigned int mmCP_DRAW_OBJECT__VI = 0xD810; -constexpr unsigned int mmCP_DRAW_OBJECT_COUNTER__VI = 0xD811; -constexpr unsigned int mmCP_DRAW_WINDOW_CNTL__VI = 0xD815; -constexpr unsigned int mmCP_DRAW_WINDOW_HI__VI = 0xD813; -constexpr unsigned int mmCP_DRAW_WINDOW_LO__VI = 0xD814; -constexpr unsigned int mmCP_DRAW_WINDOW_MASK_HI__VI = 0xD812; -constexpr unsigned int mmCP_EOP_DONE_CNTX_ID__VI = 0xC0D7; -constexpr unsigned int mmCP_GDS_BKUP_ADDR__VI = 0xC0FB; -constexpr unsigned int mmCP_GDS_BKUP_ADDR_HI__VI = 0xC0FC; -constexpr unsigned int mmCP_HPD_STATUS0__VI = 0x3241; -constexpr unsigned int mmCP_HQD_CNTL_STACK_OFFSET__VI = 0x3273; -constexpr unsigned int mmCP_HQD_CNTL_STACK_SIZE__VI = 0x3274; -constexpr unsigned int mmCP_HQD_CTX_SAVE_BASE_ADDR_HI__VI = 0x3271; -constexpr unsigned int mmCP_HQD_CTX_SAVE_BASE_ADDR_LO__VI = 0x3270; -constexpr unsigned int mmCP_HQD_CTX_SAVE_CONTROL__VI = 0x3272; -constexpr unsigned int mmCP_HQD_CTX_SAVE_SIZE__VI = 0x3276; -constexpr unsigned int mmCP_HQD_EOP_BASE_ADDR__VI = 0x326A; -constexpr unsigned int mmCP_HQD_EOP_BASE_ADDR_HI__VI = 0x326B; -constexpr unsigned int mmCP_HQD_EOP_CONTROL__VI = 0x326C; -constexpr unsigned int mmCP_HQD_EOP_DONES__VI = 0x327A; -constexpr unsigned int mmCP_HQD_EOP_EVENTS__VI = 0x326F; -constexpr unsigned int mmCP_HQD_EOP_RPTR__VI = 0x326D; -constexpr unsigned int mmCP_HQD_EOP_WPTR__VI = 0x326E; -constexpr unsigned int mmCP_HQD_EOP_WPTR_MEM__VI = 0x3279; -constexpr unsigned int mmCP_HQD_ERROR__VI = 0x3278; -constexpr unsigned int mmCP_HQD_GDS_RESOURCE_STATE__VI = 0x3277; -constexpr unsigned int mmCP_HQD_HQ_CONTROL0__VI = 0x3266; -constexpr unsigned int mmCP_HQD_HQ_CONTROL1__VI = 0x3269; -constexpr unsigned int mmCP_HQD_HQ_STATUS0__VI = 0x3265; -constexpr unsigned int mmCP_HQD_HQ_STATUS1__VI = 0x3268; -constexpr unsigned int mmCP_HQD_OFFLOAD__VI = 0x325E; -constexpr unsigned int mmCP_HQD_WG_STATE_OFFSET__VI = 0x3275; -constexpr unsigned int mmCP_INDEX_BASE_ADDR__VI = 0xC0F8; -constexpr unsigned int mmCP_INDEX_BASE_ADDR_HI__VI = 0xC0F9; -constexpr unsigned int mmCP_INDEX_TYPE__VI = 0xC0FA; -constexpr unsigned int mmCP_MEC1_F32_INT_DIS__VI = 0x30BD; -constexpr unsigned int mmCP_MEC2_F32_INT_DIS__VI = 0x30BE; -constexpr unsigned int mmCP_MEC_DOORBELL_RANGE_LOWER__VI = 0x305C; -constexpr unsigned int mmCP_MEC_DOORBELL_RANGE_UPPER__VI = 0x305D; -constexpr unsigned int mmCP_MEC_ME1_UCODE_ADDR__VI = 0xF81A; -constexpr unsigned int mmCP_MEC_ME1_UCODE_DATA__VI = 0xF81B; -constexpr unsigned int mmCP_MEC_ME2_UCODE_ADDR__VI = 0xF81C; -constexpr unsigned int mmCP_MEC_ME2_UCODE_DATA__VI = 0xF81D; -constexpr unsigned int mmCP_ME_RAM_DATA__SI__CI = 0x3058; -constexpr unsigned int mmCP_ME_RAM_DATA__VI = 0xF817; -constexpr unsigned int mmCP_ME_RAM_RADDR__SI__CI = 0x3056; -constexpr unsigned int mmCP_ME_RAM_RADDR__VI = 0xF816; -constexpr unsigned int mmCP_ME_RAM_WADDR__SI__CI = 0x3057; -constexpr unsigned int mmCP_ME_RAM_WADDR__VI = 0xF816; -constexpr unsigned int mmCP_PFP_COMPLETION_STATUS__VI = 0xC0EC; -constexpr unsigned int mmCP_PFP_METADATA_BASE_ADDR__VI = 0xC0F0; -constexpr unsigned int mmCP_PFP_METADATA_BASE_ADDR_HI__VI = 0xC0F1; -constexpr unsigned int mmCP_PFP_UCODE_ADDR__SI__CI = 0x3054; -constexpr unsigned int mmCP_PFP_UCODE_ADDR__VI = 0xF814; -constexpr unsigned int mmCP_PFP_UCODE_DATA__SI__CI = 0x3055; -constexpr unsigned int mmCP_PFP_UCODE_DATA__VI = 0xF815; -constexpr unsigned int mmCP_PIPE_STATS_CONTROL__VI = 0xC03D; -constexpr unsigned int mmCP_PQ_STATUS__VI = 0x30B8; -constexpr unsigned int mmCP_PRED_NOT_VISIBLE__VI = 0xC0EE; -constexpr unsigned int mmCP_RB_DOORBELL_CONTROL__VI = 0x3059; -constexpr unsigned int mmCP_RB_DOORBELL_RANGE_LOWER__VI = 0x305A; -constexpr unsigned int mmCP_RB_DOORBELL_RANGE_UPPER__VI = 0x305B; -constexpr unsigned int mmCP_SAMPLE_STATUS__VI = 0xC0FD; -constexpr unsigned int mmCP_STREAM_OUT_CONTROL__VI = 0xC03E; -constexpr unsigned int mmCP_VIRT_STATUS__VI = 0x3038; -constexpr unsigned int mmCP_VMID_STATUS__VI = 0x30BF; -constexpr unsigned int mmCRTC0_CRTC_3D_STRUCTURE_CONTROL__VI = 0x1B78; -constexpr unsigned int mmCRTC0_CRTC_AVSYNC_COUNTER__VI = 0x1B9B; -constexpr unsigned int mmCRTC0_CRTC_BLACK_COLOR__VI = 0x1BCC; -constexpr unsigned int mmCRTC0_CRTC_BLACK_COLOR_EXT__VI = 0x1BCD; -constexpr unsigned int mmCRTC0_CRTC_BLANK_DATA_COLOR__VI = 0x1BCA; -constexpr unsigned int mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT__VI = 0x1BCB; -constexpr unsigned int mmCRTC0_CRTC_CRC0_DATA_B__VI = 0x1BDA; -constexpr unsigned int mmCRTC0_CRTC_CRC0_DATA_RG__VI = 0x1BD9; -constexpr unsigned int mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL__VI = 0x1BD5; -constexpr unsigned int mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL__VI = 0x1BD6; -constexpr unsigned int mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL__VI = 0x1BD7; -constexpr unsigned int mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL__VI = 0x1BD8; -constexpr unsigned int mmCRTC0_CRTC_CRC1_DATA_B__VI = 0x1BE0; -constexpr unsigned int mmCRTC0_CRTC_CRC1_DATA_RG__VI = 0x1BDF; -constexpr unsigned int mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL__VI = 0x1BDB; -constexpr unsigned int mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL__VI = 0x1BDC; -constexpr unsigned int mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL__VI = 0x1BDD; -constexpr unsigned int mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL__VI = 0x1BDE; -constexpr unsigned int mmCRTC0_CRTC_CRC_CNTL__VI = 0x1BD4; -constexpr unsigned int mmCRTC0_CRTC_DCFE_CLOCK_CONTROL__VI = 0x1B7C; -constexpr unsigned int mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL__VI = 0x1BE1; -constexpr unsigned int mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI = 0x1BE5; -constexpr unsigned int mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI = 0x1BE4; -constexpr unsigned int mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI = 0x1BE6; -constexpr unsigned int mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI = 0x1BE3; -constexpr unsigned int mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI = 0x1BE2; -constexpr unsigned int mmCRTC0_CRTC_FIELD_INDICATION_CONTROL__VI = 0x1BA0; -constexpr unsigned int mmCRTC0_CRTC_GSL_CONTROL__VI = 0x1B7B; -constexpr unsigned int mmCRTC0_CRTC_GSL_VSYNC_GAP__VI = 0x1B79; -constexpr unsigned int mmCRTC0_CRTC_GSL_WINDOW__VI = 0x1B7A; -constexpr unsigned int mmCRTC0_CRTC_H_BLANK_EARLY_NUM__VI = 0x1B7D; -constexpr unsigned int mmCRTC0_CRTC_OVERSCAN_COLOR__VI = 0x1BC8; -constexpr unsigned int mmCRTC0_CRTC_OVERSCAN_COLOR_EXT__VI = 0x1BC9; -constexpr unsigned int mmCRTC0_CRTC_PIXEL_DATA_READBACK0__VI = 0x1BA1; -constexpr unsigned int mmCRTC0_CRTC_PIXEL_DATA_READBACK1__VI = 0x1BA2; -constexpr unsigned int mmCRTC0_CRTC_STATIC_SCREEN_CONTROL__VI = 0x1BE7; -constexpr unsigned int mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE__VI = 0x1B9A; -constexpr unsigned int mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI = 0x1BCF; -constexpr unsigned int mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION__VI = 0x1BCE; -constexpr unsigned int mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI = 0x1BD1; -constexpr unsigned int mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION__VI = 0x1BD0; -constexpr unsigned int mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI = 0x1BD3; -constexpr unsigned int mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION__VI = 0x1BD2; -constexpr unsigned int mmCRTC0_DCFE_DBG_SEL__VI = 0x1B7E; -constexpr unsigned int mmCRTC0_DCFE_MEM_PWR_CTRL__VI = 0x1B7F; -constexpr unsigned int mmCRTC0_DCFE_MEM_PWR_CTRL2__VI = 0x1BB8; -constexpr unsigned int mmCRTC0_DCFE_MEM_PWR_STATUS__VI = 0x1BB9; -constexpr unsigned int mmCRTC0_PIXEL_RATE_CNTL__VI = 0x0140; -constexpr unsigned int mmCRTC1_CRTC_3D_STRUCTURE_CONTROL__VI = 0x1D78; -constexpr unsigned int mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT__VI = 0x1DC3; -constexpr unsigned int mmCRTC1_CRTC_AVSYNC_COUNTER__VI = 0x1D9B; -constexpr unsigned int mmCRTC1_CRTC_BLACK_COLOR__VI = 0x1DCC; -constexpr unsigned int mmCRTC1_CRTC_BLACK_COLOR_EXT__VI = 0x1DCD; -constexpr unsigned int mmCRTC1_CRTC_BLANK_CONTROL__SI__CI = 0x1E9D; -constexpr unsigned int mmCRTC1_CRTC_BLANK_CONTROL__VI = 0x1D9D; -constexpr unsigned int mmCRTC1_CRTC_BLANK_DATA_COLOR__VI = 0x1DCA; -constexpr unsigned int mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT__VI = 0x1DCB; -constexpr unsigned int mmCRTC1_CRTC_CONTROL__VI = 0x1D9C; -constexpr unsigned int mmCRTC1_CRTC_COUNT_CONTROL__VI = 0x1DA9; -constexpr unsigned int mmCRTC1_CRTC_COUNT_RESET__VI = 0x1DAA; -constexpr unsigned int mmCRTC1_CRTC_CRC0_DATA_B__VI = 0x1DDA; -constexpr unsigned int mmCRTC1_CRTC_CRC0_DATA_RG__VI = 0x1DD9; -constexpr unsigned int mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL__VI = 0x1DD5; -constexpr unsigned int mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL__VI = 0x1DD6; -constexpr unsigned int mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL__VI = 0x1DD7; -constexpr unsigned int mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL__VI = 0x1DD8; -constexpr unsigned int mmCRTC1_CRTC_CRC1_DATA_B__VI = 0x1DE0; -constexpr unsigned int mmCRTC1_CRTC_CRC1_DATA_RG__VI = 0x1DDF; -constexpr unsigned int mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL__VI = 0x1DDB; -constexpr unsigned int mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL__VI = 0x1DDC; -constexpr unsigned int mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL__VI = 0x1DDD; -constexpr unsigned int mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL__VI = 0x1DDE; -constexpr unsigned int mmCRTC1_CRTC_CRC_CNTL__VI = 0x1DD4; -constexpr unsigned int mmCRTC1_CRTC_DCFE_CLOCK_CONTROL__VI = 0x1D7C; -constexpr unsigned int mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL__VI = 0x1DB6; -constexpr unsigned int mmCRTC1_CRTC_DTMTEST_CNTL__VI = 0x1D92; -constexpr unsigned int mmCRTC1_CRTC_DTMTEST_STATUS_POSITION__VI = 0x1D93; -constexpr unsigned int mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL__VI = 0x1DE1; -constexpr unsigned int mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI = 0x1DE5; -constexpr unsigned int mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI = 0x1DE4; -constexpr unsigned int mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI = 0x1DE6; -constexpr unsigned int mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI = 0x1DE3; -constexpr unsigned int mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI = 0x1DE2; -constexpr unsigned int mmCRTC1_CRTC_FIELD_INDICATION_CONTROL__VI = 0x1DA0; -constexpr unsigned int mmCRTC1_CRTC_FLOW_CONTROL__VI = 0x1D99; -constexpr unsigned int mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL__VI = 0x1D98; -constexpr unsigned int mmCRTC1_CRTC_GSL_CONTROL__VI = 0x1D7B; -constexpr unsigned int mmCRTC1_CRTC_GSL_VSYNC_GAP__VI = 0x1D79; -constexpr unsigned int mmCRTC1_CRTC_GSL_WINDOW__VI = 0x1D7A; -constexpr unsigned int mmCRTC1_CRTC_H_BLANK_EARLY_NUM__VI = 0x1D7D; -constexpr unsigned int mmCRTC1_CRTC_H_BLANK_START_END__VI = 0x1D81; -constexpr unsigned int mmCRTC1_CRTC_H_SYNC_A__VI = 0x1D82; -constexpr unsigned int mmCRTC1_CRTC_H_SYNC_A_CNTL__VI = 0x1D83; -constexpr unsigned int mmCRTC1_CRTC_H_SYNC_B__VI = 0x1D84; -constexpr unsigned int mmCRTC1_CRTC_H_SYNC_B_CNTL__VI = 0x1D85; -constexpr unsigned int mmCRTC1_CRTC_H_TOTAL__VI = 0x1D80; -constexpr unsigned int mmCRTC1_CRTC_INTERLACE_CONTROL__VI = 0x1D9E; -constexpr unsigned int mmCRTC1_CRTC_INTERLACE_STATUS__VI = 0x1D9F; -constexpr unsigned int mmCRTC1_CRTC_INTERRUPT_CONTROL__VI = 0x1DB4; -constexpr unsigned int mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI = 0x1DAB; -constexpr unsigned int mmCRTC1_CRTC_MASTER_EN__VI = 0x1DC2; -constexpr unsigned int mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT__VI = 0x1DBF; -constexpr unsigned int mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI = 0x1DC0; -constexpr unsigned int mmCRTC1_CRTC_MVP_STATUS__VI = 0x1DC1; -constexpr unsigned int mmCRTC1_CRTC_NOM_VERT_POSITION__VI = 0x1DA5; -constexpr unsigned int mmCRTC1_CRTC_OVERSCAN_COLOR__VI = 0x1DC8; -constexpr unsigned int mmCRTC1_CRTC_OVERSCAN_COLOR_EXT__VI = 0x1DC9; -constexpr unsigned int mmCRTC1_CRTC_PIXEL_DATA_READBACK0__VI = 0x1DA1; -constexpr unsigned int mmCRTC1_CRTC_PIXEL_DATA_READBACK1__VI = 0x1DA2; -constexpr unsigned int mmCRTC1_CRTC_SNAPSHOT_CONTROL__VI = 0x1DB0; -constexpr unsigned int mmCRTC1_CRTC_SNAPSHOT_FRAME__VI = 0x1DB2; -constexpr unsigned int mmCRTC1_CRTC_SNAPSHOT_POSITION__VI = 0x1DB1; -constexpr unsigned int mmCRTC1_CRTC_SNAPSHOT_STATUS__VI = 0x1DAF; -constexpr unsigned int mmCRTC1_CRTC_START_LINE_CONTROL__VI = 0x1DB3; -constexpr unsigned int mmCRTC1_CRTC_STATIC_SCREEN_CONTROL__VI = 0x1DE7; -constexpr unsigned int mmCRTC1_CRTC_STATUS__SI__CI = 0x1EA3; -constexpr unsigned int mmCRTC1_CRTC_STATUS__VI = 0x1DA3; -constexpr unsigned int mmCRTC1_CRTC_STATUS_FRAME_COUNT__VI = 0x1DA6; -constexpr unsigned int mmCRTC1_CRTC_STATUS_HV_COUNT__VI = 0x1DA8; -constexpr unsigned int mmCRTC1_CRTC_STATUS_POSITION__SI__CI = 0x1EA4; -constexpr unsigned int mmCRTC1_CRTC_STATUS_POSITION__VI = 0x1DA4; -constexpr unsigned int mmCRTC1_CRTC_STATUS_VF_COUNT__VI = 0x1DA7; -constexpr unsigned int mmCRTC1_CRTC_STEREO_CONTROL__VI = 0x1DAE; -constexpr unsigned int mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE__VI = 0x1D9A; -constexpr unsigned int mmCRTC1_CRTC_STEREO_STATUS__VI = 0x1DAD; -constexpr unsigned int mmCRTC1_CRTC_TEST_DEBUG_DATA__VI = 0x1DC7; -constexpr unsigned int mmCRTC1_CRTC_TEST_DEBUG_INDEX__VI = 0x1DC6; -constexpr unsigned int mmCRTC1_CRTC_TEST_PATTERN_COLOR__VI = 0x1DBC; -constexpr unsigned int mmCRTC1_CRTC_TEST_PATTERN_CONTROL__VI = 0x1DBA; -constexpr unsigned int mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS__VI = 0x1DBB; -constexpr unsigned int mmCRTC1_CRTC_TRIGA_CNTL__VI = 0x1D94; -constexpr unsigned int mmCRTC1_CRTC_TRIGA_MANUAL_TRIG__VI = 0x1D95; -constexpr unsigned int mmCRTC1_CRTC_TRIGB_CNTL__VI = 0x1D96; -constexpr unsigned int mmCRTC1_CRTC_TRIGB_MANUAL_TRIG__VI = 0x1D97; -constexpr unsigned int mmCRTC1_CRTC_UPDATE_LOCK__VI = 0x1DB5; -constexpr unsigned int mmCRTC1_CRTC_VBI_END__VI = 0x1D86; -constexpr unsigned int mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI = 0x1DCF; -constexpr unsigned int mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION__VI = 0x1DCE; -constexpr unsigned int mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI = 0x1DD1; -constexpr unsigned int mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION__VI = 0x1DD0; -constexpr unsigned int mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI = 0x1DD3; -constexpr unsigned int mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION__VI = 0x1DD2; -constexpr unsigned int mmCRTC1_CRTC_VERT_SYNC_CONTROL__VI = 0x1DAC; -constexpr unsigned int mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI = 0x1DB7; -constexpr unsigned int mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS__VI = 0x1D8C; -constexpr unsigned int mmCRTC1_CRTC_V_BLANK_START_END__VI = 0x1D8D; -constexpr unsigned int mmCRTC1_CRTC_V_SYNC_A__VI = 0x1D8E; -constexpr unsigned int mmCRTC1_CRTC_V_SYNC_A_CNTL__VI = 0x1D8F; -constexpr unsigned int mmCRTC1_CRTC_V_SYNC_B__VI = 0x1D90; -constexpr unsigned int mmCRTC1_CRTC_V_SYNC_B_CNTL__VI = 0x1D91; -constexpr unsigned int mmCRTC1_CRTC_V_TOTAL__VI = 0x1D87; -constexpr unsigned int mmCRTC1_CRTC_V_TOTAL_CONTROL__VI = 0x1D8A; -constexpr unsigned int mmCRTC1_CRTC_V_TOTAL_INT_STATUS__VI = 0x1D8B; -constexpr unsigned int mmCRTC1_CRTC_V_TOTAL_MAX__VI = 0x1D89; -constexpr unsigned int mmCRTC1_CRTC_V_TOTAL_MIN__VI = 0x1D88; -constexpr unsigned int mmCRTC1_CRTC_V_UPDATE_INT_STATUS__VI = 0x1DC4; -constexpr unsigned int mmCRTC1_DCFE_DBG_SEL__VI = 0x1D7E; -constexpr unsigned int mmCRTC1_DCFE_MEM_PWR_CTRL__VI = 0x1D7F; -constexpr unsigned int mmCRTC1_DCFE_MEM_PWR_CTRL2__VI = 0x1DB8; -constexpr unsigned int mmCRTC1_DCFE_MEM_PWR_STATUS__VI = 0x1DB9; -constexpr unsigned int mmCRTC1_MASTER_UPDATE_LOCK__VI = 0x1DBD; -constexpr unsigned int mmCRTC1_MASTER_UPDATE_MODE__SI__CI = 0x1EBE; -constexpr unsigned int mmCRTC1_MASTER_UPDATE_MODE__VI = 0x1DBE; -constexpr unsigned int mmCRTC1_PIXEL_RATE_CNTL__VI = 0x0144; -constexpr unsigned int mmCRTC2_CRTC_3D_STRUCTURE_CONTROL__VI = 0x1F78; -constexpr unsigned int mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT__VI = 0x1FC3; -constexpr unsigned int mmCRTC2_CRTC_AVSYNC_COUNTER__VI = 0x1F9B; -constexpr unsigned int mmCRTC2_CRTC_BLACK_COLOR__VI = 0x1FCC; -constexpr unsigned int mmCRTC2_CRTC_BLACK_COLOR_EXT__VI = 0x1FCD; -constexpr unsigned int mmCRTC2_CRTC_BLANK_CONTROL__SI__CI = 0x419D; -constexpr unsigned int mmCRTC2_CRTC_BLANK_CONTROL__VI = 0x1F9D; -constexpr unsigned int mmCRTC2_CRTC_BLANK_DATA_COLOR__VI = 0x1FCA; -constexpr unsigned int mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT__VI = 0x1FCB; -constexpr unsigned int mmCRTC2_CRTC_CONTROL__VI = 0x1F9C; -constexpr unsigned int mmCRTC2_CRTC_COUNT_CONTROL__VI = 0x1FA9; -constexpr unsigned int mmCRTC2_CRTC_COUNT_RESET__VI = 0x1FAA; -constexpr unsigned int mmCRTC2_CRTC_CRC0_DATA_B__VI = 0x1FDA; -constexpr unsigned int mmCRTC2_CRTC_CRC0_DATA_RG__VI = 0x1FD9; -constexpr unsigned int mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL__VI = 0x1FD5; -constexpr unsigned int mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL__VI = 0x1FD6; -constexpr unsigned int mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL__VI = 0x1FD7; -constexpr unsigned int mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL__VI = 0x1FD8; -constexpr unsigned int mmCRTC2_CRTC_CRC1_DATA_B__VI = 0x1FE0; -constexpr unsigned int mmCRTC2_CRTC_CRC1_DATA_RG__VI = 0x1FDF; -constexpr unsigned int mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL__VI = 0x1FDB; -constexpr unsigned int mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL__VI = 0x1FDC; -constexpr unsigned int mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL__VI = 0x1FDD; -constexpr unsigned int mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL__VI = 0x1FDE; -constexpr unsigned int mmCRTC2_CRTC_CRC_CNTL__VI = 0x1FD4; -constexpr unsigned int mmCRTC2_CRTC_DCFE_CLOCK_CONTROL__VI = 0x1F7C; -constexpr unsigned int mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL__VI = 0x1FB6; -constexpr unsigned int mmCRTC2_CRTC_DTMTEST_CNTL__VI = 0x1F92; -constexpr unsigned int mmCRTC2_CRTC_DTMTEST_STATUS_POSITION__VI = 0x1F93; -constexpr unsigned int mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL__VI = 0x1FE1; -constexpr unsigned int mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI = 0x1FE5; -constexpr unsigned int mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI = 0x1FE4; -constexpr unsigned int mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI = 0x1FE6; -constexpr unsigned int mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI = 0x1FE3; -constexpr unsigned int mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI = 0x1FE2; -constexpr unsigned int mmCRTC2_CRTC_FIELD_INDICATION_CONTROL__VI = 0x1FA0; -constexpr unsigned int mmCRTC2_CRTC_FLOW_CONTROL__VI = 0x1F99; -constexpr unsigned int mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL__VI = 0x1F98; -constexpr unsigned int mmCRTC2_CRTC_GSL_CONTROL__VI = 0x1F7B; -constexpr unsigned int mmCRTC2_CRTC_GSL_VSYNC_GAP__VI = 0x1F79; -constexpr unsigned int mmCRTC2_CRTC_GSL_WINDOW__VI = 0x1F7A; -constexpr unsigned int mmCRTC2_CRTC_H_BLANK_EARLY_NUM__VI = 0x1F7D; -constexpr unsigned int mmCRTC2_CRTC_H_BLANK_START_END__VI = 0x1F81; -constexpr unsigned int mmCRTC2_CRTC_H_SYNC_A__VI = 0x1F82; -constexpr unsigned int mmCRTC2_CRTC_H_SYNC_A_CNTL__VI = 0x1F83; -constexpr unsigned int mmCRTC2_CRTC_H_SYNC_B__VI = 0x1F84; -constexpr unsigned int mmCRTC2_CRTC_H_SYNC_B_CNTL__VI = 0x1F85; -constexpr unsigned int mmCRTC2_CRTC_H_TOTAL__VI = 0x1F80; -constexpr unsigned int mmCRTC2_CRTC_INTERLACE_CONTROL__VI = 0x1F9E; -constexpr unsigned int mmCRTC2_CRTC_INTERLACE_STATUS__VI = 0x1F9F; -constexpr unsigned int mmCRTC2_CRTC_INTERRUPT_CONTROL__VI = 0x1FB4; -constexpr unsigned int mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI = 0x1FAB; -constexpr unsigned int mmCRTC2_CRTC_MASTER_EN__VI = 0x1FC2; -constexpr unsigned int mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT__VI = 0x1FBF; -constexpr unsigned int mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI = 0x1FC0; -constexpr unsigned int mmCRTC2_CRTC_MVP_STATUS__VI = 0x1FC1; -constexpr unsigned int mmCRTC2_CRTC_NOM_VERT_POSITION__VI = 0x1FA5; -constexpr unsigned int mmCRTC2_CRTC_OVERSCAN_COLOR__VI = 0x1FC8; -constexpr unsigned int mmCRTC2_CRTC_OVERSCAN_COLOR_EXT__VI = 0x1FC9; -constexpr unsigned int mmCRTC2_CRTC_PIXEL_DATA_READBACK0__VI = 0x1FA1; -constexpr unsigned int mmCRTC2_CRTC_PIXEL_DATA_READBACK1__VI = 0x1FA2; -constexpr unsigned int mmCRTC2_CRTC_SNAPSHOT_CONTROL__VI = 0x1FB0; -constexpr unsigned int mmCRTC2_CRTC_SNAPSHOT_FRAME__VI = 0x1FB2; -constexpr unsigned int mmCRTC2_CRTC_SNAPSHOT_POSITION__VI = 0x1FB1; -constexpr unsigned int mmCRTC2_CRTC_SNAPSHOT_STATUS__VI = 0x1FAF; -constexpr unsigned int mmCRTC2_CRTC_START_LINE_CONTROL__VI = 0x1FB3; -constexpr unsigned int mmCRTC2_CRTC_STATIC_SCREEN_CONTROL__VI = 0x1FE7; -constexpr unsigned int mmCRTC2_CRTC_STATUS__SI__CI = 0x41A3; -constexpr unsigned int mmCRTC2_CRTC_STATUS__VI = 0x1FA3; -constexpr unsigned int mmCRTC2_CRTC_STATUS_FRAME_COUNT__VI = 0x1FA6; -constexpr unsigned int mmCRTC2_CRTC_STATUS_HV_COUNT__VI = 0x1FA8; -constexpr unsigned int mmCRTC2_CRTC_STATUS_POSITION__SI__CI = 0x41A4; -constexpr unsigned int mmCRTC2_CRTC_STATUS_POSITION__VI = 0x1FA4; -constexpr unsigned int mmCRTC2_CRTC_STATUS_VF_COUNT__VI = 0x1FA7; -constexpr unsigned int mmCRTC2_CRTC_STEREO_CONTROL__VI = 0x1FAE; -constexpr unsigned int mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE__VI = 0x1F9A; -constexpr unsigned int mmCRTC2_CRTC_STEREO_STATUS__VI = 0x1FAD; -constexpr unsigned int mmCRTC2_CRTC_TEST_DEBUG_DATA__VI = 0x1FC7; -constexpr unsigned int mmCRTC2_CRTC_TEST_DEBUG_INDEX__VI = 0x1FC6; -constexpr unsigned int mmCRTC2_CRTC_TEST_PATTERN_COLOR__VI = 0x1FBC; -constexpr unsigned int mmCRTC2_CRTC_TEST_PATTERN_CONTROL__VI = 0x1FBA; -constexpr unsigned int mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS__VI = 0x1FBB; -constexpr unsigned int mmCRTC2_CRTC_TRIGA_CNTL__VI = 0x1F94; -constexpr unsigned int mmCRTC2_CRTC_TRIGA_MANUAL_TRIG__VI = 0x1F95; -constexpr unsigned int mmCRTC2_CRTC_TRIGB_CNTL__VI = 0x1F96; -constexpr unsigned int mmCRTC2_CRTC_TRIGB_MANUAL_TRIG__VI = 0x1F97; -constexpr unsigned int mmCRTC2_CRTC_UPDATE_LOCK__VI = 0x1FB5; -constexpr unsigned int mmCRTC2_CRTC_VBI_END__VI = 0x1F86; -constexpr unsigned int mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI = 0x1FCF; -constexpr unsigned int mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION__VI = 0x1FCE; -constexpr unsigned int mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI = 0x1FD1; -constexpr unsigned int mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION__VI = 0x1FD0; -constexpr unsigned int mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI = 0x1FD3; -constexpr unsigned int mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION__VI = 0x1FD2; -constexpr unsigned int mmCRTC2_CRTC_VERT_SYNC_CONTROL__VI = 0x1FAC; -constexpr unsigned int mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI = 0x1FB7; -constexpr unsigned int mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS__VI = 0x1F8C; -constexpr unsigned int mmCRTC2_CRTC_V_BLANK_START_END__VI = 0x1F8D; -constexpr unsigned int mmCRTC2_CRTC_V_SYNC_A__VI = 0x1F8E; -constexpr unsigned int mmCRTC2_CRTC_V_SYNC_A_CNTL__VI = 0x1F8F; -constexpr unsigned int mmCRTC2_CRTC_V_SYNC_B__VI = 0x1F90; -constexpr unsigned int mmCRTC2_CRTC_V_SYNC_B_CNTL__VI = 0x1F91; -constexpr unsigned int mmCRTC2_CRTC_V_TOTAL__VI = 0x1F87; -constexpr unsigned int mmCRTC2_CRTC_V_TOTAL_CONTROL__VI = 0x1F8A; -constexpr unsigned int mmCRTC2_CRTC_V_TOTAL_INT_STATUS__VI = 0x1F8B; -constexpr unsigned int mmCRTC2_CRTC_V_TOTAL_MAX__VI = 0x1F89; -constexpr unsigned int mmCRTC2_CRTC_V_TOTAL_MIN__VI = 0x1F88; -constexpr unsigned int mmCRTC2_CRTC_V_UPDATE_INT_STATUS__VI = 0x1FC4; -constexpr unsigned int mmCRTC2_DCFE_DBG_SEL__VI = 0x1F7E; -constexpr unsigned int mmCRTC2_DCFE_MEM_PWR_CTRL__VI = 0x1F7F; -constexpr unsigned int mmCRTC2_DCFE_MEM_PWR_CTRL2__VI = 0x1FB8; -constexpr unsigned int mmCRTC2_DCFE_MEM_PWR_STATUS__VI = 0x1FB9; -constexpr unsigned int mmCRTC2_MASTER_UPDATE_LOCK__VI = 0x1FBD; -constexpr unsigned int mmCRTC2_MASTER_UPDATE_MODE__SI__CI = 0x41BE; -constexpr unsigned int mmCRTC2_MASTER_UPDATE_MODE__VI = 0x1FBE; -constexpr unsigned int mmCRTC2_PIXEL_RATE_CNTL__VI = 0x0148; -constexpr unsigned int mmCRTC3_CRTC_3D_STRUCTURE_CONTROL__VI = 0x4178; -constexpr unsigned int mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT__VI = 0x41C3; -constexpr unsigned int mmCRTC3_CRTC_AVSYNC_COUNTER__VI = 0x419B; -constexpr unsigned int mmCRTC3_CRTC_BLACK_COLOR__VI = 0x41CC; -constexpr unsigned int mmCRTC3_CRTC_BLACK_COLOR_EXT__VI = 0x41CD; -constexpr unsigned int mmCRTC3_CRTC_BLANK_CONTROL__SI__CI = 0x449D; -constexpr unsigned int mmCRTC3_CRTC_BLANK_CONTROL__VI = 0x419D; -constexpr unsigned int mmCRTC3_CRTC_BLANK_DATA_COLOR__VI = 0x41CA; -constexpr unsigned int mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT__VI = 0x41CB; -constexpr unsigned int mmCRTC3_CRTC_CONTROL__VI = 0x419C; -constexpr unsigned int mmCRTC3_CRTC_COUNT_CONTROL__VI = 0x41A9; -constexpr unsigned int mmCRTC3_CRTC_COUNT_RESET__VI = 0x41AA; -constexpr unsigned int mmCRTC3_CRTC_CRC0_DATA_B__VI = 0x41DA; -constexpr unsigned int mmCRTC3_CRTC_CRC0_DATA_RG__VI = 0x41D9; -constexpr unsigned int mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL__VI = 0x41D5; -constexpr unsigned int mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL__VI = 0x41D6; -constexpr unsigned int mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL__VI = 0x41D7; -constexpr unsigned int mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL__VI = 0x41D8; -constexpr unsigned int mmCRTC3_CRTC_CRC1_DATA_B__VI = 0x41E0; -constexpr unsigned int mmCRTC3_CRTC_CRC1_DATA_RG__VI = 0x41DF; -constexpr unsigned int mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL__VI = 0x41DB; -constexpr unsigned int mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL__VI = 0x41DC; -constexpr unsigned int mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL__VI = 0x41DD; -constexpr unsigned int mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL__VI = 0x41DE; -constexpr unsigned int mmCRTC3_CRTC_CRC_CNTL__VI = 0x41D4; -constexpr unsigned int mmCRTC3_CRTC_DCFE_CLOCK_CONTROL__VI = 0x417C; -constexpr unsigned int mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL__VI = 0x41B6; -constexpr unsigned int mmCRTC3_CRTC_DTMTEST_CNTL__VI = 0x4192; -constexpr unsigned int mmCRTC3_CRTC_DTMTEST_STATUS_POSITION__VI = 0x4193; -constexpr unsigned int mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL__VI = 0x41E1; -constexpr unsigned int mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI = 0x41E5; -constexpr unsigned int mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI = 0x41E4; -constexpr unsigned int mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI = 0x41E6; -constexpr unsigned int mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI = 0x41E3; -constexpr unsigned int mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI = 0x41E2; -constexpr unsigned int mmCRTC3_CRTC_FIELD_INDICATION_CONTROL__VI = 0x41A0; -constexpr unsigned int mmCRTC3_CRTC_FLOW_CONTROL__VI = 0x4199; -constexpr unsigned int mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL__VI = 0x4198; -constexpr unsigned int mmCRTC3_CRTC_GSL_CONTROL__VI = 0x417B; -constexpr unsigned int mmCRTC3_CRTC_GSL_VSYNC_GAP__VI = 0x4179; -constexpr unsigned int mmCRTC3_CRTC_GSL_WINDOW__VI = 0x417A; -constexpr unsigned int mmCRTC3_CRTC_H_BLANK_EARLY_NUM__VI = 0x417D; -constexpr unsigned int mmCRTC3_CRTC_H_BLANK_START_END__VI = 0x4181; -constexpr unsigned int mmCRTC3_CRTC_H_SYNC_A__VI = 0x4182; -constexpr unsigned int mmCRTC3_CRTC_H_SYNC_A_CNTL__VI = 0x4183; -constexpr unsigned int mmCRTC3_CRTC_H_SYNC_B__VI = 0x4184; -constexpr unsigned int mmCRTC3_CRTC_H_SYNC_B_CNTL__VI = 0x4185; -constexpr unsigned int mmCRTC3_CRTC_H_TOTAL__VI = 0x4180; -constexpr unsigned int mmCRTC3_CRTC_INTERLACE_CONTROL__VI = 0x419E; -constexpr unsigned int mmCRTC3_CRTC_INTERLACE_STATUS__VI = 0x419F; -constexpr unsigned int mmCRTC3_CRTC_INTERRUPT_CONTROL__VI = 0x41B4; -constexpr unsigned int mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI = 0x41AB; -constexpr unsigned int mmCRTC3_CRTC_MASTER_EN__VI = 0x41C2; -constexpr unsigned int mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT__VI = 0x41BF; -constexpr unsigned int mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI = 0x41C0; -constexpr unsigned int mmCRTC3_CRTC_MVP_STATUS__VI = 0x41C1; -constexpr unsigned int mmCRTC3_CRTC_NOM_VERT_POSITION__VI = 0x41A5; -constexpr unsigned int mmCRTC3_CRTC_OVERSCAN_COLOR__VI = 0x41C8; -constexpr unsigned int mmCRTC3_CRTC_OVERSCAN_COLOR_EXT__VI = 0x41C9; -constexpr unsigned int mmCRTC3_CRTC_PIXEL_DATA_READBACK0__VI = 0x41A1; -constexpr unsigned int mmCRTC3_CRTC_PIXEL_DATA_READBACK1__VI = 0x41A2; -constexpr unsigned int mmCRTC3_CRTC_SNAPSHOT_CONTROL__VI = 0x41B0; -constexpr unsigned int mmCRTC3_CRTC_SNAPSHOT_FRAME__VI = 0x41B2; -constexpr unsigned int mmCRTC3_CRTC_SNAPSHOT_POSITION__VI = 0x41B1; -constexpr unsigned int mmCRTC3_CRTC_SNAPSHOT_STATUS__VI = 0x41AF; -constexpr unsigned int mmCRTC3_CRTC_START_LINE_CONTROL__VI = 0x41B3; -constexpr unsigned int mmCRTC3_CRTC_STATIC_SCREEN_CONTROL__VI = 0x41E7; -constexpr unsigned int mmCRTC3_CRTC_STATUS__SI__CI = 0x44A3; -constexpr unsigned int mmCRTC3_CRTC_STATUS__VI = 0x41A3; -constexpr unsigned int mmCRTC3_CRTC_STATUS_FRAME_COUNT__VI = 0x41A6; -constexpr unsigned int mmCRTC3_CRTC_STATUS_HV_COUNT__VI = 0x41A8; -constexpr unsigned int mmCRTC3_CRTC_STATUS_POSITION__SI__CI = 0x44A4; -constexpr unsigned int mmCRTC3_CRTC_STATUS_POSITION__VI = 0x41A4; -constexpr unsigned int mmCRTC3_CRTC_STATUS_VF_COUNT__VI = 0x41A7; -constexpr unsigned int mmCRTC3_CRTC_STEREO_CONTROL__VI = 0x41AE; -constexpr unsigned int mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE__VI = 0x419A; -constexpr unsigned int mmCRTC3_CRTC_STEREO_STATUS__VI = 0x41AD; -constexpr unsigned int mmCRTC3_CRTC_TEST_DEBUG_DATA__VI = 0x41C7; -constexpr unsigned int mmCRTC3_CRTC_TEST_DEBUG_INDEX__VI = 0x41C6; -constexpr unsigned int mmCRTC3_CRTC_TEST_PATTERN_COLOR__VI = 0x41BC; -constexpr unsigned int mmCRTC3_CRTC_TEST_PATTERN_CONTROL__VI = 0x41BA; -constexpr unsigned int mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS__VI = 0x41BB; -constexpr unsigned int mmCRTC3_CRTC_TRIGA_CNTL__VI = 0x4194; -constexpr unsigned int mmCRTC3_CRTC_TRIGA_MANUAL_TRIG__VI = 0x4195; -constexpr unsigned int mmCRTC3_CRTC_TRIGB_CNTL__VI = 0x4196; -constexpr unsigned int mmCRTC3_CRTC_TRIGB_MANUAL_TRIG__VI = 0x4197; -constexpr unsigned int mmCRTC3_CRTC_UPDATE_LOCK__VI = 0x41B5; -constexpr unsigned int mmCRTC3_CRTC_VBI_END__VI = 0x4186; -constexpr unsigned int mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI = 0x41CF; -constexpr unsigned int mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION__VI = 0x41CE; -constexpr unsigned int mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI = 0x41D1; -constexpr unsigned int mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION__VI = 0x41D0; -constexpr unsigned int mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI = 0x41D3; -constexpr unsigned int mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION__VI = 0x41D2; -constexpr unsigned int mmCRTC3_CRTC_VERT_SYNC_CONTROL__VI = 0x41AC; -constexpr unsigned int mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI = 0x41B7; -constexpr unsigned int mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS__VI = 0x418C; -constexpr unsigned int mmCRTC3_CRTC_V_BLANK_START_END__VI = 0x418D; -constexpr unsigned int mmCRTC3_CRTC_V_SYNC_A__VI = 0x418E; -constexpr unsigned int mmCRTC3_CRTC_V_SYNC_A_CNTL__VI = 0x418F; -constexpr unsigned int mmCRTC3_CRTC_V_SYNC_B__VI = 0x4190; -constexpr unsigned int mmCRTC3_CRTC_V_SYNC_B_CNTL__VI = 0x4191; -constexpr unsigned int mmCRTC3_CRTC_V_TOTAL__VI = 0x4187; -constexpr unsigned int mmCRTC3_CRTC_V_TOTAL_CONTROL__VI = 0x418A; -constexpr unsigned int mmCRTC3_CRTC_V_TOTAL_INT_STATUS__VI = 0x418B; -constexpr unsigned int mmCRTC3_CRTC_V_TOTAL_MAX__VI = 0x4189; -constexpr unsigned int mmCRTC3_CRTC_V_TOTAL_MIN__VI = 0x4188; -constexpr unsigned int mmCRTC3_CRTC_V_UPDATE_INT_STATUS__VI = 0x41C4; -constexpr unsigned int mmCRTC3_DCFE_DBG_SEL__VI = 0x417E; -constexpr unsigned int mmCRTC3_DCFE_MEM_PWR_CTRL__VI = 0x417F; -constexpr unsigned int mmCRTC3_DCFE_MEM_PWR_CTRL2__VI = 0x41B8; -constexpr unsigned int mmCRTC3_DCFE_MEM_PWR_STATUS__VI = 0x41B9; -constexpr unsigned int mmCRTC3_MASTER_UPDATE_LOCK__VI = 0x41BD; -constexpr unsigned int mmCRTC3_MASTER_UPDATE_MODE__SI__CI = 0x44BE; -constexpr unsigned int mmCRTC3_MASTER_UPDATE_MODE__VI = 0x41BE; -constexpr unsigned int mmCRTC3_PIXEL_RATE_CNTL__VI = 0x014C; -constexpr unsigned int mmCRTC4_CRTC_3D_STRUCTURE_CONTROL__VI = 0x4378; -constexpr unsigned int mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT__VI = 0x43C3; -constexpr unsigned int mmCRTC4_CRTC_AVSYNC_COUNTER__VI = 0x439B; -constexpr unsigned int mmCRTC4_CRTC_BLACK_COLOR__VI = 0x43CC; -constexpr unsigned int mmCRTC4_CRTC_BLACK_COLOR_EXT__VI = 0x43CD; -constexpr unsigned int mmCRTC4_CRTC_BLANK_CONTROL__SI__CI = 0x479D; -constexpr unsigned int mmCRTC4_CRTC_BLANK_CONTROL__VI = 0x439D; -constexpr unsigned int mmCRTC4_CRTC_BLANK_DATA_COLOR__VI = 0x43CA; -constexpr unsigned int mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT__VI = 0x43CB; -constexpr unsigned int mmCRTC4_CRTC_CONTROL__VI = 0x439C; -constexpr unsigned int mmCRTC4_CRTC_COUNT_CONTROL__VI = 0x43A9; -constexpr unsigned int mmCRTC4_CRTC_COUNT_RESET__VI = 0x43AA; -constexpr unsigned int mmCRTC4_CRTC_CRC0_DATA_B__VI = 0x43DA; -constexpr unsigned int mmCRTC4_CRTC_CRC0_DATA_RG__VI = 0x43D9; -constexpr unsigned int mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL__VI = 0x43D5; -constexpr unsigned int mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL__VI = 0x43D6; -constexpr unsigned int mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL__VI = 0x43D7; -constexpr unsigned int mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL__VI = 0x43D8; -constexpr unsigned int mmCRTC4_CRTC_CRC1_DATA_B__VI = 0x43E0; -constexpr unsigned int mmCRTC4_CRTC_CRC1_DATA_RG__VI = 0x43DF; -constexpr unsigned int mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL__VI = 0x43DB; -constexpr unsigned int mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL__VI = 0x43DC; -constexpr unsigned int mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL__VI = 0x43DD; -constexpr unsigned int mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL__VI = 0x43DE; -constexpr unsigned int mmCRTC4_CRTC_CRC_CNTL__VI = 0x43D4; -constexpr unsigned int mmCRTC4_CRTC_DCFE_CLOCK_CONTROL__VI = 0x437C; -constexpr unsigned int mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL__VI = 0x43B6; -constexpr unsigned int mmCRTC4_CRTC_DTMTEST_CNTL__VI = 0x4392; -constexpr unsigned int mmCRTC4_CRTC_DTMTEST_STATUS_POSITION__VI = 0x4393; -constexpr unsigned int mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL__VI = 0x43E1; -constexpr unsigned int mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI = 0x43E5; -constexpr unsigned int mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI = 0x43E4; -constexpr unsigned int mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI = 0x43E6; -constexpr unsigned int mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI = 0x43E3; -constexpr unsigned int mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI = 0x43E2; -constexpr unsigned int mmCRTC4_CRTC_FIELD_INDICATION_CONTROL__VI = 0x43A0; -constexpr unsigned int mmCRTC4_CRTC_FLOW_CONTROL__VI = 0x4399; -constexpr unsigned int mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL__VI = 0x4398; -constexpr unsigned int mmCRTC4_CRTC_GSL_CONTROL__VI = 0x437B; -constexpr unsigned int mmCRTC4_CRTC_GSL_VSYNC_GAP__VI = 0x4379; -constexpr unsigned int mmCRTC4_CRTC_GSL_WINDOW__VI = 0x437A; -constexpr unsigned int mmCRTC4_CRTC_H_BLANK_EARLY_NUM__VI = 0x437D; -constexpr unsigned int mmCRTC4_CRTC_H_BLANK_START_END__VI = 0x4381; -constexpr unsigned int mmCRTC4_CRTC_H_SYNC_A__VI = 0x4382; -constexpr unsigned int mmCRTC4_CRTC_H_SYNC_A_CNTL__VI = 0x4383; -constexpr unsigned int mmCRTC4_CRTC_H_SYNC_B__VI = 0x4384; -constexpr unsigned int mmCRTC4_CRTC_H_SYNC_B_CNTL__VI = 0x4385; -constexpr unsigned int mmCRTC4_CRTC_H_TOTAL__VI = 0x4380; -constexpr unsigned int mmCRTC4_CRTC_INTERLACE_CONTROL__VI = 0x439E; -constexpr unsigned int mmCRTC4_CRTC_INTERLACE_STATUS__VI = 0x439F; -constexpr unsigned int mmCRTC4_CRTC_INTERRUPT_CONTROL__VI = 0x43B4; -constexpr unsigned int mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI = 0x43AB; -constexpr unsigned int mmCRTC4_CRTC_MASTER_EN__VI = 0x43C2; -constexpr unsigned int mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT__VI = 0x43BF; -constexpr unsigned int mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI = 0x43C0; -constexpr unsigned int mmCRTC4_CRTC_MVP_STATUS__VI = 0x43C1; -constexpr unsigned int mmCRTC4_CRTC_NOM_VERT_POSITION__VI = 0x43A5; -constexpr unsigned int mmCRTC4_CRTC_OVERSCAN_COLOR__VI = 0x43C8; -constexpr unsigned int mmCRTC4_CRTC_OVERSCAN_COLOR_EXT__VI = 0x43C9; -constexpr unsigned int mmCRTC4_CRTC_PIXEL_DATA_READBACK0__VI = 0x43A1; -constexpr unsigned int mmCRTC4_CRTC_PIXEL_DATA_READBACK1__VI = 0x43A2; -constexpr unsigned int mmCRTC4_CRTC_SNAPSHOT_CONTROL__VI = 0x43B0; -constexpr unsigned int mmCRTC4_CRTC_SNAPSHOT_FRAME__VI = 0x43B2; -constexpr unsigned int mmCRTC4_CRTC_SNAPSHOT_POSITION__VI = 0x43B1; -constexpr unsigned int mmCRTC4_CRTC_SNAPSHOT_STATUS__VI = 0x43AF; -constexpr unsigned int mmCRTC4_CRTC_START_LINE_CONTROL__VI = 0x43B3; -constexpr unsigned int mmCRTC4_CRTC_STATIC_SCREEN_CONTROL__VI = 0x43E7; -constexpr unsigned int mmCRTC4_CRTC_STATUS__SI__CI = 0x47A3; -constexpr unsigned int mmCRTC4_CRTC_STATUS__VI = 0x43A3; -constexpr unsigned int mmCRTC4_CRTC_STATUS_FRAME_COUNT__VI = 0x43A6; -constexpr unsigned int mmCRTC4_CRTC_STATUS_HV_COUNT__VI = 0x43A8; -constexpr unsigned int mmCRTC4_CRTC_STATUS_POSITION__SI__CI = 0x47A4; -constexpr unsigned int mmCRTC4_CRTC_STATUS_POSITION__VI = 0x43A4; -constexpr unsigned int mmCRTC4_CRTC_STATUS_VF_COUNT__VI = 0x43A7; -constexpr unsigned int mmCRTC4_CRTC_STEREO_CONTROL__VI = 0x43AE; -constexpr unsigned int mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE__VI = 0x439A; -constexpr unsigned int mmCRTC4_CRTC_STEREO_STATUS__VI = 0x43AD; -constexpr unsigned int mmCRTC4_CRTC_TEST_DEBUG_DATA__VI = 0x43C7; -constexpr unsigned int mmCRTC4_CRTC_TEST_DEBUG_INDEX__VI = 0x43C6; -constexpr unsigned int mmCRTC4_CRTC_TEST_PATTERN_COLOR__VI = 0x43BC; -constexpr unsigned int mmCRTC4_CRTC_TEST_PATTERN_CONTROL__VI = 0x43BA; -constexpr unsigned int mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS__VI = 0x43BB; -constexpr unsigned int mmCRTC4_CRTC_TRIGA_CNTL__VI = 0x4394; -constexpr unsigned int mmCRTC4_CRTC_TRIGA_MANUAL_TRIG__VI = 0x4395; -constexpr unsigned int mmCRTC4_CRTC_TRIGB_CNTL__VI = 0x4396; -constexpr unsigned int mmCRTC4_CRTC_TRIGB_MANUAL_TRIG__VI = 0x4397; -constexpr unsigned int mmCRTC4_CRTC_UPDATE_LOCK__VI = 0x43B5; -constexpr unsigned int mmCRTC4_CRTC_VBI_END__VI = 0x4386; -constexpr unsigned int mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI = 0x43CF; -constexpr unsigned int mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION__VI = 0x43CE; -constexpr unsigned int mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI = 0x43D1; -constexpr unsigned int mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION__VI = 0x43D0; -constexpr unsigned int mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI = 0x43D3; -constexpr unsigned int mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION__VI = 0x43D2; -constexpr unsigned int mmCRTC4_CRTC_VERT_SYNC_CONTROL__VI = 0x43AC; -constexpr unsigned int mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI = 0x43B7; -constexpr unsigned int mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS__VI = 0x438C; -constexpr unsigned int mmCRTC4_CRTC_V_BLANK_START_END__VI = 0x438D; -constexpr unsigned int mmCRTC4_CRTC_V_SYNC_A__VI = 0x438E; -constexpr unsigned int mmCRTC4_CRTC_V_SYNC_A_CNTL__VI = 0x438F; -constexpr unsigned int mmCRTC4_CRTC_V_SYNC_B__VI = 0x4390; -constexpr unsigned int mmCRTC4_CRTC_V_SYNC_B_CNTL__VI = 0x4391; -constexpr unsigned int mmCRTC4_CRTC_V_TOTAL__VI = 0x4387; -constexpr unsigned int mmCRTC4_CRTC_V_TOTAL_CONTROL__VI = 0x438A; -constexpr unsigned int mmCRTC4_CRTC_V_TOTAL_INT_STATUS__VI = 0x438B; -constexpr unsigned int mmCRTC4_CRTC_V_TOTAL_MAX__VI = 0x4389; -constexpr unsigned int mmCRTC4_CRTC_V_TOTAL_MIN__VI = 0x4388; -constexpr unsigned int mmCRTC4_CRTC_V_UPDATE_INT_STATUS__VI = 0x43C4; -constexpr unsigned int mmCRTC4_DCFE_DBG_SEL__VI = 0x437E; -constexpr unsigned int mmCRTC4_DCFE_MEM_PWR_CTRL__VI = 0x437F; -constexpr unsigned int mmCRTC4_DCFE_MEM_PWR_CTRL2__VI = 0x43B8; -constexpr unsigned int mmCRTC4_DCFE_MEM_PWR_STATUS__VI = 0x43B9; -constexpr unsigned int mmCRTC4_MASTER_UPDATE_LOCK__VI = 0x43BD; -constexpr unsigned int mmCRTC4_MASTER_UPDATE_MODE__SI__CI = 0x47BE; -constexpr unsigned int mmCRTC4_MASTER_UPDATE_MODE__VI = 0x43BE; -constexpr unsigned int mmCRTC4_PIXEL_RATE_CNTL__VI = 0x0150; -constexpr unsigned int mmCRTC5_CRTC_3D_STRUCTURE_CONTROL__VI = 0x4578; -constexpr unsigned int mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT__VI = 0x45C3; -constexpr unsigned int mmCRTC5_CRTC_AVSYNC_COUNTER__VI = 0x459B; -constexpr unsigned int mmCRTC5_CRTC_BLACK_COLOR__VI = 0x45CC; -constexpr unsigned int mmCRTC5_CRTC_BLACK_COLOR_EXT__VI = 0x45CD; -constexpr unsigned int mmCRTC5_CRTC_BLANK_CONTROL__SI__CI = 0x4A9D; -constexpr unsigned int mmCRTC5_CRTC_BLANK_CONTROL__VI = 0x459D; -constexpr unsigned int mmCRTC5_CRTC_BLANK_DATA_COLOR__VI = 0x45CA; -constexpr unsigned int mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT__VI = 0x45CB; -constexpr unsigned int mmCRTC5_CRTC_CONTROL__VI = 0x459C; -constexpr unsigned int mmCRTC5_CRTC_COUNT_CONTROL__VI = 0x45A9; -constexpr unsigned int mmCRTC5_CRTC_COUNT_RESET__VI = 0x45AA; -constexpr unsigned int mmCRTC5_CRTC_CRC0_DATA_B__VI = 0x45DA; -constexpr unsigned int mmCRTC5_CRTC_CRC0_DATA_RG__VI = 0x45D9; -constexpr unsigned int mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL__VI = 0x45D5; -constexpr unsigned int mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL__VI = 0x45D6; -constexpr unsigned int mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL__VI = 0x45D7; -constexpr unsigned int mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL__VI = 0x45D8; -constexpr unsigned int mmCRTC5_CRTC_CRC1_DATA_B__VI = 0x45E0; -constexpr unsigned int mmCRTC5_CRTC_CRC1_DATA_RG__VI = 0x45DF; -constexpr unsigned int mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL__VI = 0x45DB; -constexpr unsigned int mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL__VI = 0x45DC; -constexpr unsigned int mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL__VI = 0x45DD; -constexpr unsigned int mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL__VI = 0x45DE; -constexpr unsigned int mmCRTC5_CRTC_CRC_CNTL__VI = 0x45D4; -constexpr unsigned int mmCRTC5_CRTC_DCFE_CLOCK_CONTROL__VI = 0x457C; -constexpr unsigned int mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL__VI = 0x45B6; -constexpr unsigned int mmCRTC5_CRTC_DTMTEST_CNTL__VI = 0x4592; -constexpr unsigned int mmCRTC5_CRTC_DTMTEST_STATUS_POSITION__VI = 0x4593; -constexpr unsigned int mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL__VI = 0x45E1; -constexpr unsigned int mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI = 0x45E5; -constexpr unsigned int mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI = 0x45E4; -constexpr unsigned int mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI = 0x45E6; -constexpr unsigned int mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI = 0x45E3; -constexpr unsigned int mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI = 0x45E2; -constexpr unsigned int mmCRTC5_CRTC_FIELD_INDICATION_CONTROL__VI = 0x45A0; -constexpr unsigned int mmCRTC5_CRTC_FLOW_CONTROL__VI = 0x4599; -constexpr unsigned int mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL__VI = 0x4598; -constexpr unsigned int mmCRTC5_CRTC_GSL_CONTROL__VI = 0x457B; -constexpr unsigned int mmCRTC5_CRTC_GSL_VSYNC_GAP__VI = 0x4579; -constexpr unsigned int mmCRTC5_CRTC_GSL_WINDOW__VI = 0x457A; -constexpr unsigned int mmCRTC5_CRTC_H_BLANK_EARLY_NUM__VI = 0x457D; -constexpr unsigned int mmCRTC5_CRTC_H_BLANK_START_END__VI = 0x4581; -constexpr unsigned int mmCRTC5_CRTC_H_SYNC_A__VI = 0x4582; -constexpr unsigned int mmCRTC5_CRTC_H_SYNC_A_CNTL__VI = 0x4583; -constexpr unsigned int mmCRTC5_CRTC_H_SYNC_B__VI = 0x4584; -constexpr unsigned int mmCRTC5_CRTC_H_SYNC_B_CNTL__VI = 0x4585; -constexpr unsigned int mmCRTC5_CRTC_H_TOTAL__VI = 0x4580; -constexpr unsigned int mmCRTC5_CRTC_INTERLACE_CONTROL__VI = 0x459E; -constexpr unsigned int mmCRTC5_CRTC_INTERLACE_STATUS__VI = 0x459F; -constexpr unsigned int mmCRTC5_CRTC_INTERRUPT_CONTROL__VI = 0x45B4; -constexpr unsigned int mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI = 0x45AB; -constexpr unsigned int mmCRTC5_CRTC_MASTER_EN__VI = 0x45C2; -constexpr unsigned int mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT__VI = 0x45BF; -constexpr unsigned int mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI = 0x45C0; -constexpr unsigned int mmCRTC5_CRTC_MVP_STATUS__VI = 0x45C1; -constexpr unsigned int mmCRTC5_CRTC_NOM_VERT_POSITION__VI = 0x45A5; -constexpr unsigned int mmCRTC5_CRTC_OVERSCAN_COLOR__VI = 0x45C8; -constexpr unsigned int mmCRTC5_CRTC_OVERSCAN_COLOR_EXT__VI = 0x45C9; -constexpr unsigned int mmCRTC5_CRTC_PIXEL_DATA_READBACK0__VI = 0x45A1; -constexpr unsigned int mmCRTC5_CRTC_PIXEL_DATA_READBACK1__VI = 0x45A2; -constexpr unsigned int mmCRTC5_CRTC_SNAPSHOT_CONTROL__VI = 0x45B0; -constexpr unsigned int mmCRTC5_CRTC_SNAPSHOT_FRAME__VI = 0x45B2; -constexpr unsigned int mmCRTC5_CRTC_SNAPSHOT_POSITION__VI = 0x45B1; -constexpr unsigned int mmCRTC5_CRTC_SNAPSHOT_STATUS__VI = 0x45AF; -constexpr unsigned int mmCRTC5_CRTC_START_LINE_CONTROL__VI = 0x45B3; -constexpr unsigned int mmCRTC5_CRTC_STATIC_SCREEN_CONTROL__VI = 0x45E7; -constexpr unsigned int mmCRTC5_CRTC_STATUS__SI__CI = 0x4AA3; -constexpr unsigned int mmCRTC5_CRTC_STATUS__VI = 0x45A3; -constexpr unsigned int mmCRTC5_CRTC_STATUS_FRAME_COUNT__VI = 0x45A6; -constexpr unsigned int mmCRTC5_CRTC_STATUS_HV_COUNT__VI = 0x45A8; -constexpr unsigned int mmCRTC5_CRTC_STATUS_POSITION__SI__CI = 0x4AA4; -constexpr unsigned int mmCRTC5_CRTC_STATUS_POSITION__VI = 0x45A4; -constexpr unsigned int mmCRTC5_CRTC_STATUS_VF_COUNT__VI = 0x45A7; -constexpr unsigned int mmCRTC5_CRTC_STEREO_CONTROL__VI = 0x45AE; -constexpr unsigned int mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE__VI = 0x459A; -constexpr unsigned int mmCRTC5_CRTC_STEREO_STATUS__VI = 0x45AD; -constexpr unsigned int mmCRTC5_CRTC_TEST_DEBUG_DATA__VI = 0x45C7; -constexpr unsigned int mmCRTC5_CRTC_TEST_DEBUG_INDEX__VI = 0x45C6; -constexpr unsigned int mmCRTC5_CRTC_TEST_PATTERN_COLOR__VI = 0x45BC; -constexpr unsigned int mmCRTC5_CRTC_TEST_PATTERN_CONTROL__VI = 0x45BA; -constexpr unsigned int mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS__VI = 0x45BB; -constexpr unsigned int mmCRTC5_CRTC_TRIGA_CNTL__VI = 0x4594; -constexpr unsigned int mmCRTC5_CRTC_TRIGA_MANUAL_TRIG__VI = 0x4595; -constexpr unsigned int mmCRTC5_CRTC_TRIGB_CNTL__VI = 0x4596; -constexpr unsigned int mmCRTC5_CRTC_TRIGB_MANUAL_TRIG__VI = 0x4597; -constexpr unsigned int mmCRTC5_CRTC_UPDATE_LOCK__VI = 0x45B5; -constexpr unsigned int mmCRTC5_CRTC_VBI_END__VI = 0x4586; -constexpr unsigned int mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI = 0x45CF; -constexpr unsigned int mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION__VI = 0x45CE; -constexpr unsigned int mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI = 0x45D1; -constexpr unsigned int mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION__VI = 0x45D0; -constexpr unsigned int mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI = 0x45D3; -constexpr unsigned int mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION__VI = 0x45D2; -constexpr unsigned int mmCRTC5_CRTC_VERT_SYNC_CONTROL__VI = 0x45AC; -constexpr unsigned int mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI = 0x45B7; -constexpr unsigned int mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS__VI = 0x458C; -constexpr unsigned int mmCRTC5_CRTC_V_BLANK_START_END__VI = 0x458D; -constexpr unsigned int mmCRTC5_CRTC_V_SYNC_A__VI = 0x458E; -constexpr unsigned int mmCRTC5_CRTC_V_SYNC_A_CNTL__VI = 0x458F; -constexpr unsigned int mmCRTC5_CRTC_V_SYNC_B__VI = 0x4590; -constexpr unsigned int mmCRTC5_CRTC_V_SYNC_B_CNTL__VI = 0x4591; -constexpr unsigned int mmCRTC5_CRTC_V_TOTAL__VI = 0x4587; -constexpr unsigned int mmCRTC5_CRTC_V_TOTAL_CONTROL__VI = 0x458A; -constexpr unsigned int mmCRTC5_CRTC_V_TOTAL_INT_STATUS__VI = 0x458B; -constexpr unsigned int mmCRTC5_CRTC_V_TOTAL_MAX__VI = 0x4589; -constexpr unsigned int mmCRTC5_CRTC_V_TOTAL_MIN__VI = 0x4588; -constexpr unsigned int mmCRTC5_CRTC_V_UPDATE_INT_STATUS__VI = 0x45C4; -constexpr unsigned int mmCRTC5_DCFE_DBG_SEL__VI = 0x457E; -constexpr unsigned int mmCRTC5_DCFE_MEM_PWR_CTRL__VI = 0x457F; -constexpr unsigned int mmCRTC5_DCFE_MEM_PWR_CTRL2__VI = 0x45B8; -constexpr unsigned int mmCRTC5_DCFE_MEM_PWR_STATUS__VI = 0x45B9; -constexpr unsigned int mmCRTC5_MASTER_UPDATE_LOCK__VI = 0x45BD; -constexpr unsigned int mmCRTC5_MASTER_UPDATE_MODE__SI__CI = 0x4ABE; -constexpr unsigned int mmCRTC5_MASTER_UPDATE_MODE__VI = 0x45BE; -constexpr unsigned int mmCRTC5_PIXEL_RATE_CNTL__VI = 0x0154; -constexpr unsigned int mmCRTC6_CRTC_3D_STRUCTURE_CONTROL__VI = 0x4778; -constexpr unsigned int mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT__VI = 0x47C3; -constexpr unsigned int mmCRTC6_CRTC_AVSYNC_COUNTER__VI = 0x479B; -constexpr unsigned int mmCRTC6_CRTC_BLACK_COLOR__VI = 0x47CC; -constexpr unsigned int mmCRTC6_CRTC_BLACK_COLOR_EXT__VI = 0x47CD; -constexpr unsigned int mmCRTC6_CRTC_BLANK_CONTROL__VI = 0x479D; -constexpr unsigned int mmCRTC6_CRTC_BLANK_DATA_COLOR__VI = 0x47CA; -constexpr unsigned int mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT__VI = 0x47CB; -constexpr unsigned int mmCRTC6_CRTC_CONTROL__VI = 0x479C; -constexpr unsigned int mmCRTC6_CRTC_COUNT_CONTROL__VI = 0x47A9; -constexpr unsigned int mmCRTC6_CRTC_COUNT_RESET__VI = 0x47AA; -constexpr unsigned int mmCRTC6_CRTC_CRC0_DATA_B__VI = 0x47DA; -constexpr unsigned int mmCRTC6_CRTC_CRC0_DATA_RG__VI = 0x47D9; -constexpr unsigned int mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL__VI = 0x47D5; -constexpr unsigned int mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL__VI = 0x47D6; -constexpr unsigned int mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL__VI = 0x47D7; -constexpr unsigned int mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL__VI = 0x47D8; -constexpr unsigned int mmCRTC6_CRTC_CRC1_DATA_B__VI = 0x47E0; -constexpr unsigned int mmCRTC6_CRTC_CRC1_DATA_RG__VI = 0x47DF; -constexpr unsigned int mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL__VI = 0x47DB; -constexpr unsigned int mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL__VI = 0x47DC; -constexpr unsigned int mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL__VI = 0x47DD; -constexpr unsigned int mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL__VI = 0x47DE; -constexpr unsigned int mmCRTC6_CRTC_CRC_CNTL__VI = 0x47D4; -constexpr unsigned int mmCRTC6_CRTC_DCFE_CLOCK_CONTROL__VI = 0x477C; -constexpr unsigned int mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL__VI = 0x47B6; -constexpr unsigned int mmCRTC6_CRTC_DTMTEST_CNTL__VI = 0x4792; -constexpr unsigned int mmCRTC6_CRTC_DTMTEST_STATUS_POSITION__VI = 0x4793; -constexpr unsigned int mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL__VI = 0x47E1; -constexpr unsigned int mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI = 0x47E5; -constexpr unsigned int mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI = 0x47E4; -constexpr unsigned int mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI = 0x47E6; -constexpr unsigned int mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END__VI = 0x47E3; -constexpr unsigned int mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START__VI = 0x47E2; -constexpr unsigned int mmCRTC6_CRTC_FIELD_INDICATION_CONTROL__VI = 0x47A0; -constexpr unsigned int mmCRTC6_CRTC_FLOW_CONTROL__VI = 0x4799; -constexpr unsigned int mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL__VI = 0x4798; -constexpr unsigned int mmCRTC6_CRTC_GSL_CONTROL__VI = 0x477B; -constexpr unsigned int mmCRTC6_CRTC_GSL_VSYNC_GAP__VI = 0x4779; -constexpr unsigned int mmCRTC6_CRTC_GSL_WINDOW__VI = 0x477A; -constexpr unsigned int mmCRTC6_CRTC_H_BLANK_EARLY_NUM__VI = 0x477D; -constexpr unsigned int mmCRTC6_CRTC_H_BLANK_START_END__VI = 0x4781; -constexpr unsigned int mmCRTC6_CRTC_H_SYNC_A__VI = 0x4782; -constexpr unsigned int mmCRTC6_CRTC_H_SYNC_A_CNTL__VI = 0x4783; -constexpr unsigned int mmCRTC6_CRTC_H_SYNC_B__VI = 0x4784; -constexpr unsigned int mmCRTC6_CRTC_H_SYNC_B_CNTL__VI = 0x4785; -constexpr unsigned int mmCRTC6_CRTC_H_TOTAL__VI = 0x4780; -constexpr unsigned int mmCRTC6_CRTC_INTERLACE_CONTROL__VI = 0x479E; -constexpr unsigned int mmCRTC6_CRTC_INTERLACE_STATUS__VI = 0x479F; -constexpr unsigned int mmCRTC6_CRTC_INTERRUPT_CONTROL__VI = 0x47B4; -constexpr unsigned int mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__VI = 0x47AB; -constexpr unsigned int mmCRTC6_CRTC_MASTER_EN__VI = 0x47C2; -constexpr unsigned int mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT__VI = 0x47BF; -constexpr unsigned int mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER__VI = 0x47C0; -constexpr unsigned int mmCRTC6_CRTC_MVP_STATUS__VI = 0x47C1; -constexpr unsigned int mmCRTC6_CRTC_NOM_VERT_POSITION__VI = 0x47A5; -constexpr unsigned int mmCRTC6_CRTC_OVERSCAN_COLOR__VI = 0x47C8; -constexpr unsigned int mmCRTC6_CRTC_OVERSCAN_COLOR_EXT__VI = 0x47C9; -constexpr unsigned int mmCRTC6_CRTC_PIXEL_DATA_READBACK0__VI = 0x47A1; -constexpr unsigned int mmCRTC6_CRTC_PIXEL_DATA_READBACK1__VI = 0x47A2; -constexpr unsigned int mmCRTC6_CRTC_SNAPSHOT_CONTROL__VI = 0x47B0; -constexpr unsigned int mmCRTC6_CRTC_SNAPSHOT_FRAME__VI = 0x47B2; -constexpr unsigned int mmCRTC6_CRTC_SNAPSHOT_POSITION__VI = 0x47B1; -constexpr unsigned int mmCRTC6_CRTC_SNAPSHOT_STATUS__VI = 0x47AF; -constexpr unsigned int mmCRTC6_CRTC_START_LINE_CONTROL__VI = 0x47B3; -constexpr unsigned int mmCRTC6_CRTC_STATIC_SCREEN_CONTROL__VI = 0x47E7; -constexpr unsigned int mmCRTC6_CRTC_STATUS__VI = 0x47A3; -constexpr unsigned int mmCRTC6_CRTC_STATUS_FRAME_COUNT__VI = 0x47A6; -constexpr unsigned int mmCRTC6_CRTC_STATUS_HV_COUNT__VI = 0x47A8; -constexpr unsigned int mmCRTC6_CRTC_STATUS_POSITION__VI = 0x47A4; -constexpr unsigned int mmCRTC6_CRTC_STATUS_VF_COUNT__VI = 0x47A7; -constexpr unsigned int mmCRTC6_CRTC_STEREO_CONTROL__VI = 0x47AE; -constexpr unsigned int mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE__VI = 0x479A; -constexpr unsigned int mmCRTC6_CRTC_STEREO_STATUS__VI = 0x47AD; -constexpr unsigned int mmCRTC6_CRTC_TEST_DEBUG_DATA__VI = 0x47C7; -constexpr unsigned int mmCRTC6_CRTC_TEST_DEBUG_INDEX__VI = 0x47C6; -constexpr unsigned int mmCRTC6_CRTC_TEST_PATTERN_COLOR__VI = 0x47BC; -constexpr unsigned int mmCRTC6_CRTC_TEST_PATTERN_CONTROL__VI = 0x47BA; -constexpr unsigned int mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS__VI = 0x47BB; -constexpr unsigned int mmCRTC6_CRTC_TRIGA_CNTL__VI = 0x4794; -constexpr unsigned int mmCRTC6_CRTC_TRIGA_MANUAL_TRIG__VI = 0x4795; -constexpr unsigned int mmCRTC6_CRTC_TRIGB_CNTL__VI = 0x4796; -constexpr unsigned int mmCRTC6_CRTC_TRIGB_MANUAL_TRIG__VI = 0x4797; -constexpr unsigned int mmCRTC6_CRTC_UPDATE_LOCK__VI = 0x47B5; -constexpr unsigned int mmCRTC6_CRTC_VBI_END__VI = 0x4786; -constexpr unsigned int mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL__VI = 0x47CF; -constexpr unsigned int mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION__VI = 0x47CE; -constexpr unsigned int mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL__VI = 0x47D1; -constexpr unsigned int mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION__VI = 0x47D0; -constexpr unsigned int mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL__VI = 0x47D3; -constexpr unsigned int mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION__VI = 0x47D2; -constexpr unsigned int mmCRTC6_CRTC_VERT_SYNC_CONTROL__VI = 0x47AC; -constexpr unsigned int mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE__VI = 0x47B7; -constexpr unsigned int mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS__VI = 0x478C; -constexpr unsigned int mmCRTC6_CRTC_V_BLANK_START_END__VI = 0x478D; -constexpr unsigned int mmCRTC6_CRTC_V_SYNC_A__VI = 0x478E; -constexpr unsigned int mmCRTC6_CRTC_V_SYNC_A_CNTL__VI = 0x478F; -constexpr unsigned int mmCRTC6_CRTC_V_SYNC_B__VI = 0x4790; -constexpr unsigned int mmCRTC6_CRTC_V_SYNC_B_CNTL__VI = 0x4791; -constexpr unsigned int mmCRTC6_CRTC_V_TOTAL__VI = 0x4787; -constexpr unsigned int mmCRTC6_CRTC_V_TOTAL_CONTROL__VI = 0x478A; -constexpr unsigned int mmCRTC6_CRTC_V_TOTAL_INT_STATUS__VI = 0x478B; -constexpr unsigned int mmCRTC6_CRTC_V_TOTAL_MAX__VI = 0x4789; -constexpr unsigned int mmCRTC6_CRTC_V_TOTAL_MIN__VI = 0x4788; -constexpr unsigned int mmCRTC6_CRTC_V_UPDATE_INT_STATUS__VI = 0x47C4; -constexpr unsigned int mmCRTC6_DCFE_DBG_SEL__VI = 0x477E; -constexpr unsigned int mmCRTC6_DCFE_MEM_PWR_CTRL__VI = 0x477F; -constexpr unsigned int mmCRTC6_DCFE_MEM_PWR_CTRL2__VI = 0x47B8; -constexpr unsigned int mmCRTC6_DCFE_MEM_PWR_STATUS__VI = 0x47B9; -constexpr unsigned int mmCRTC6_MASTER_UPDATE_LOCK__VI = 0x47BD; -constexpr unsigned int mmCRTC6_MASTER_UPDATE_MODE__VI = 0x47BE; -constexpr unsigned int mmCRTC_3D_STRUCTURE_CONTROL__VI = 0x1B78; -constexpr unsigned int mmCRTC_AVSYNC_COUNTER__VI = 0x1B9B; -constexpr unsigned int mmCRTC_BLACK_COLOR__VI = 0x1BCC; -constexpr unsigned int mmCRTC_BLACK_COLOR_EXT__VI = 0x1BCD; -constexpr unsigned int mmCRTC_BLANK_DATA_COLOR__VI = 0x1BCA; -constexpr unsigned int mmCRTC_BLANK_DATA_COLOR_EXT__VI = 0x1BCB; -constexpr unsigned int mmCRTC_CRC0_DATA_B__VI = 0x1BDA; -constexpr unsigned int mmCRTC_CRC0_DATA_RG__VI = 0x1BD9; -constexpr unsigned int mmCRTC_CRC0_WINDOWA_X_CONTROL__VI = 0x1BD5; -constexpr unsigned int mmCRTC_CRC0_WINDOWA_Y_CONTROL__VI = 0x1BD6; -constexpr unsigned int mmCRTC_CRC0_WINDOWB_X_CONTROL__VI = 0x1BD7; -constexpr unsigned int mmCRTC_CRC0_WINDOWB_Y_CONTROL__VI = 0x1BD8; -constexpr unsigned int mmCRTC_CRC1_DATA_B__VI = 0x1BE0; -constexpr unsigned int mmCRTC_CRC1_DATA_RG__VI = 0x1BDF; -constexpr unsigned int mmCRTC_CRC1_WINDOWA_X_CONTROL__VI = 0x1BDB; -constexpr unsigned int mmCRTC_CRC1_WINDOWA_Y_CONTROL__VI = 0x1BDC; -constexpr unsigned int mmCRTC_CRC1_WINDOWB_X_CONTROL__VI = 0x1BDD; -constexpr unsigned int mmCRTC_CRC1_WINDOWB_Y_CONTROL__VI = 0x1BDE; -constexpr unsigned int mmCRTC_CRC_CNTL__VI = 0x1BD4; -constexpr unsigned int mmCRTC_DCFE_CLOCK_CONTROL__VI = 0x1B7C; -constexpr unsigned int mmCRTC_EXT_TIMING_SYNC_CONTROL__VI = 0x1BE1; -constexpr unsigned int mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI = 0x1BE5; -constexpr unsigned int mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI = 0x1BE4; -constexpr unsigned int mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI = 0x1BE6; -constexpr unsigned int mmCRTC_EXT_TIMING_SYNC_WINDOW_END__VI = 0x1BE3; -constexpr unsigned int mmCRTC_EXT_TIMING_SYNC_WINDOW_START__VI = 0x1BE2; -constexpr unsigned int mmCRTC_FIELD_INDICATION_CONTROL__VI = 0x1BA0; -constexpr unsigned int mmCRTC_GSL_CONTROL__VI = 0x1B7B; -constexpr unsigned int mmCRTC_GSL_VSYNC_GAP__VI = 0x1B79; -constexpr unsigned int mmCRTC_GSL_WINDOW__VI = 0x1B7A; -constexpr unsigned int mmCRTC_H_BLANK_EARLY_NUM__VI = 0x1B7D; -constexpr unsigned int mmCRTC_OVERSCAN_COLOR__VI = 0x1BC8; -constexpr unsigned int mmCRTC_OVERSCAN_COLOR_EXT__VI = 0x1BC9; -constexpr unsigned int mmCRTC_PIXEL_DATA_READBACK0__VI = 0x1BA1; -constexpr unsigned int mmCRTC_PIXEL_DATA_READBACK1__VI = 0x1BA2; -constexpr unsigned int mmCRTC_STATIC_SCREEN_CONTROL__VI = 0x1BE7; -constexpr unsigned int mmCRTC_STEREO_FORCE_NEXT_EYE__VI = 0x1B9A; -constexpr unsigned int mmCRTC_VERTICAL_INTERRUPT0_CONTROL__VI = 0x1BCF; -constexpr unsigned int mmCRTC_VERTICAL_INTERRUPT0_POSITION__VI = 0x1BCE; -constexpr unsigned int mmCRTC_VERTICAL_INTERRUPT1_CONTROL__VI = 0x1BD1; -constexpr unsigned int mmCRTC_VERTICAL_INTERRUPT1_POSITION__VI = 0x1BD0; -constexpr unsigned int mmCRTC_VERTICAL_INTERRUPT2_CONTROL__VI = 0x1BD3; -constexpr unsigned int mmCRTC_VERTICAL_INTERRUPT2_POSITION__VI = 0x1BD2; -constexpr unsigned int mmCUR2_COLOR1__VI = 0x1A75; -constexpr unsigned int mmCUR2_COLOR2__VI = 0x1A76; -constexpr unsigned int mmCUR2_CONTROL__VI = 0x1A6F; -constexpr unsigned int mmCUR2_HOT_SPOT__VI = 0x1A74; -constexpr unsigned int mmCUR2_POSITION__VI = 0x1A73; -constexpr unsigned int mmCUR2_SIZE__VI = 0x1A71; -constexpr unsigned int mmCUR2_STEREO_CONTROL__VI = 0x1A9B; -constexpr unsigned int mmCUR2_SURFACE_ADDRESS__VI = 0x1A70; -constexpr unsigned int mmCUR2_SURFACE_ADDRESS_HIGH__VI = 0x1A72; -constexpr unsigned int mmCUR2_UPDATE__VI = 0x1A77; -constexpr unsigned int mmCUR_REQUEST_FILTER_CNTL__VI = 0x1A99; -constexpr unsigned int mmCUR_STEREO_CONTROL__VI = 0x1A9A; -constexpr unsigned int mmDAC_AUTODETECT_CONTROL__VI = 0x16B4; -constexpr unsigned int mmDAC_AUTODETECT_CONTROL2__VI = 0x16B5; -constexpr unsigned int mmDAC_AUTODETECT_CONTROL3__VI = 0x16B6; -constexpr unsigned int mmDAC_AUTODETECT_INT_CONTROL__VI = 0x16B8; -constexpr unsigned int mmDAC_AUTODETECT_STATUS__VI = 0x16B7; -constexpr unsigned int mmDAC_CLK_ENABLE__VI = 0x0128; -constexpr unsigned int mmDAC_COMPARATOR_ENABLE__VI = 0x16BD; -constexpr unsigned int mmDAC_COMPARATOR_OUTPUT__VI = 0x16BE; -constexpr unsigned int mmDAC_CONTROL__VI = 0x16BC; -constexpr unsigned int mmDAC_CRC_CONTROL__VI = 0x16AD; -constexpr unsigned int mmDAC_CRC_EN__VI = 0x16AC; -constexpr unsigned int mmDAC_CRC_SIG_CONTROL__VI = 0x16B1; -constexpr unsigned int mmDAC_CRC_SIG_CONTROL_MASK__VI = 0x16AF; -constexpr unsigned int mmDAC_CRC_SIG_RGB__VI = 0x16B0; -constexpr unsigned int mmDAC_CRC_SIG_RGB_MASK__VI = 0x16AE; -constexpr unsigned int mmDAC_DFT_CONFIG__VI = 0x16C0; -constexpr unsigned int mmDAC_ENABLE__VI = 0x16AA; -constexpr unsigned int mmDAC_FIFO_STATUS__VI = 0x16C1; -constexpr unsigned int mmDAC_FORCE_DATA__VI = 0x16BA; -constexpr unsigned int mmDAC_FORCE_OUTPUT_CNTL__VI = 0x16B9; -constexpr unsigned int mmDAC_MACRO_CNTL_RESERVED0__VI = 0x48B8; -constexpr unsigned int mmDAC_MACRO_CNTL_RESERVED1__VI = 0x48B9; -constexpr unsigned int mmDAC_MACRO_CNTL_RESERVED2__VI = 0x48BA; -constexpr unsigned int mmDAC_MACRO_CNTL_RESERVED3__VI = 0x48BB; -constexpr unsigned int mmDAC_POWERDOWN__VI = 0x16BB; -constexpr unsigned int mmDAC_PWR_CNTL__VI = 0x16BF; -constexpr unsigned int mmDAC_SOURCE_SELECT__VI = 0x16AB; -constexpr unsigned int mmDAC_STEREOSYNC_SELECT__VI = 0x16B3; -constexpr unsigned int mmDAC_SYNC_TRISTATE_CONTROL__VI = 0x16B2; -constexpr unsigned int mmDAC_TEST_DEBUG_DATA__VI = 0x16C3; -constexpr unsigned int mmDAC_TEST_DEBUG_INDEX__VI = 0x16C2; -constexpr unsigned int mmDBG_OUT_CNTL__VI = 0x4834; -constexpr unsigned int mmDBG_SMB_BYPASS_SRBM_ACCESS__VI = 0x14EB; -constexpr unsigned int mmDCCG_AUDIO_DTO0_MODULE__VI = 0x016D; -constexpr unsigned int mmDCCG_AUDIO_DTO0_PHASE__VI = 0x016C; -constexpr unsigned int mmDCCG_AUDIO_DTO1_MODULE__VI = 0x016F; -constexpr unsigned int mmDCCG_AUDIO_DTO1_PHASE__VI = 0x016E; -constexpr unsigned int mmDCCG_AUDIO_DTO_SOURCE__VI = 0x016B; -constexpr unsigned int mmDCCG_CAC_STATUS__VI = 0x0137; -constexpr unsigned int mmDCCG_CBUS_WRCMD_DELAY__VI = 0x0110; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0__VI = 0x5FD0; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1__VI = 0x5FD1; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10__VI = 0x5FDA; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11__VI = 0x5FDB; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2__VI = 0x5FD2; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3__VI = 0x5FD3; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4__VI = 0x5FD4; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5__VI = 0x5FD5; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6__VI = 0x5FD6; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7__VI = 0x5FD7; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8__VI = 0x5FD8; -constexpr unsigned int mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9__VI = 0x5FD9; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0__VI = 0x5FDC; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1__VI = 0x5FDD; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10__VI = 0x5FE6; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11__VI = 0x5FE7; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2__VI = 0x5FDE; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3__VI = 0x5FDF; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4__VI = 0x5FE0; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5__VI = 0x5FE1; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6__VI = 0x5FE2; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7__VI = 0x5FE3; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8__VI = 0x5FE4; -constexpr unsigned int mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9__VI = 0x5FE5; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0__VI = 0x5FE8; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1__VI = 0x5FE9; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10__VI = 0x5FF2; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11__VI = 0x5FF3; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2__VI = 0x5FEA; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3__VI = 0x5FEB; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4__VI = 0x5FEC; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5__VI = 0x5FED; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6__VI = 0x5FEE; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7__VI = 0x5FEF; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8__VI = 0x5FF0; -constexpr unsigned int mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9__VI = 0x5FF1; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0__VI = 0x5FF4; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1__VI = 0x5FF5; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10__VI = 0x5FFE; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11__VI = 0x5FFF; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2__VI = 0x5FF6; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3__VI = 0x5FF7; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4__VI = 0x5FF8; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5__VI = 0x5FF9; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6__VI = 0x5FFA; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7__VI = 0x5FFB; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8__VI = 0x5FFC; -constexpr unsigned int mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9__VI = 0x5FFD; -constexpr unsigned int mmDCCG_DISP_CNTL_REG__VI = 0x013F; -constexpr unsigned int mmDCCG_DS_CNTL__VI = 0x0115; -constexpr unsigned int mmDCCG_DS_DEBUG_CNTL__VI = 0x0112; -constexpr unsigned int mmDCCG_DS_DTO_INCR__VI = 0x0113; -constexpr unsigned int mmDCCG_DS_DTO_MODULO__VI = 0x0114; -constexpr unsigned int mmDCCG_DS_HW_CAL_INTERVAL__VI = 0x0116; -constexpr unsigned int mmDCCG_GATE_DISABLE_CNTL__VI = 0x0134; -constexpr unsigned int mmDCCG_GTC_CNTL__VI = 0x0120; -constexpr unsigned int mmDCCG_GTC_CURRENT__VI = 0x0123; -constexpr unsigned int mmDCCG_GTC_DTO_INCR__VI = 0x0121; -constexpr unsigned int mmDCCG_GTC_DTO_MODULO__VI = 0x0122; -constexpr unsigned int mmDCCG_PERFMON_CNTL__VI = 0x0133; -constexpr unsigned int mmDCCG_PERFMON_CNTL2__VI = 0x010E; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0__VI = 0x1700; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1__VI = 0x1701; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10__VI = 0x170A; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11__VI = 0x170B; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12__VI = 0x170C; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13__VI = 0x170D; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14__VI = 0x170E; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15__VI = 0x170F; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16__VI = 0x1710; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17__VI = 0x1711; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18__VI = 0x1712; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19__VI = 0x1713; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2__VI = 0x1702; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20__VI = 0x1714; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21__VI = 0x1715; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22__VI = 0x1716; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23__VI = 0x1717; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24__VI = 0x1718; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25__VI = 0x1719; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26__VI = 0x171A; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27__VI = 0x171B; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28__VI = 0x171C; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29__VI = 0x171D; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3__VI = 0x1703; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30__VI = 0x171E; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31__VI = 0x171F; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32__VI = 0x1720; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33__VI = 0x1721; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34__VI = 0x1722; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35__VI = 0x1723; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36__VI = 0x1724; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37__VI = 0x1725; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38__VI = 0x1726; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39__VI = 0x1727; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4__VI = 0x1704; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40__VI = 0x1728; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41__VI = 0x1729; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5__VI = 0x1705; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6__VI = 0x1706; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7__VI = 0x1707; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8__VI = 0x1708; -constexpr unsigned int mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9__VI = 0x1709; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0__VI = 0x172A; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1__VI = 0x172B; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10__VI = 0x1734; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11__VI = 0x1735; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12__VI = 0x1736; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13__VI = 0x1737; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14__VI = 0x1738; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15__VI = 0x1739; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16__VI = 0x173A; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17__VI = 0x173B; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18__VI = 0x173C; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19__VI = 0x173D; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2__VI = 0x172C; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20__VI = 0x173E; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21__VI = 0x173F; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22__VI = 0x1740; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23__VI = 0x1741; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24__VI = 0x1742; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25__VI = 0x1743; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26__VI = 0x1744; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27__VI = 0x1745; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28__VI = 0x1746; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29__VI = 0x1747; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3__VI = 0x172D; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30__VI = 0x1748; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31__VI = 0x1749; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32__VI = 0x174A; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33__VI = 0x174B; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34__VI = 0x174C; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35__VI = 0x174D; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36__VI = 0x174E; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37__VI = 0x174F; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38__VI = 0x1750; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39__VI = 0x1751; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4__VI = 0x172E; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40__VI = 0x1752; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41__VI = 0x1753; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5__VI = 0x172F; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6__VI = 0x1730; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7__VI = 0x1731; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8__VI = 0x1732; -constexpr unsigned int mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9__VI = 0x1733; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0__VI = 0x1754; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1__VI = 0x1755; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10__VI = 0x175E; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11__VI = 0x175F; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12__VI = 0x1760; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13__VI = 0x1761; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14__VI = 0x1762; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15__VI = 0x1763; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16__VI = 0x1764; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17__VI = 0x1765; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18__VI = 0x1766; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19__VI = 0x1767; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2__VI = 0x1756; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20__VI = 0x1768; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21__VI = 0x1769; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22__VI = 0x176A; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23__VI = 0x176B; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24__VI = 0x176C; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25__VI = 0x176D; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26__VI = 0x176E; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27__VI = 0x176F; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28__VI = 0x1770; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29__VI = 0x1771; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3__VI = 0x1757; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30__VI = 0x1772; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31__VI = 0x1773; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32__VI = 0x1774; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33__VI = 0x1775; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34__VI = 0x1776; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35__VI = 0x1777; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36__VI = 0x1778; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37__VI = 0x1779; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38__VI = 0x177A; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39__VI = 0x177B; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4__VI = 0x1758; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40__VI = 0x177C; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41__VI = 0x177D; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5__VI = 0x1759; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6__VI = 0x175A; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7__VI = 0x175B; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8__VI = 0x175C; -constexpr unsigned int mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9__VI = 0x175D; -constexpr unsigned int mmDCCG_SOFT_RESET__VI = 0x015F; -constexpr unsigned int mmDCCG_TEST_CLK_SEL__VI = 0x017E; -constexpr unsigned int mmDCCG_TEST_DEBUG_DATA__VI = 0x017D; -constexpr unsigned int mmDCCG_TEST_DEBUG_INDEX__VI = 0x017C; -constexpr unsigned int mmDCDEBUG_BUS_CLK1_SEL__VI = 0x16C4; -constexpr unsigned int mmDCDEBUG_BUS_CLK2_SEL__VI = 0x16C5; -constexpr unsigned int mmDCDEBUG_BUS_CLK3_SEL__VI = 0x16C6; -constexpr unsigned int mmDCDEBUG_BUS_CLK4_SEL__VI = 0x16C7; -constexpr unsigned int mmDCDEBUG_BUS_CLK5_SEL__VI = 0x16C8; -constexpr unsigned int mmDCDEBUG_OUT_CNTL__VI = 0x16CA; -constexpr unsigned int mmDCDEBUG_OUT_DATA__VI = 0x16CB; -constexpr unsigned int mmDCDEBUG_OUT_PIN_OVERRIDE__VI = 0x16C9; -constexpr unsigned int mmDCE_VCE_CONTROL__VI = 0x1856; -constexpr unsigned int mmDCFE0_DCFE_CLOCK_CONTROL__VI = 0x1B00; -constexpr unsigned int mmDCFE0_DCFE_DBG_CONFIG__VI = 0x1B02; -constexpr unsigned int mmDCFE0_DCFE_SOFT_RESET__VI = 0x1B01; -constexpr unsigned int mmDCFE1_DCFE_CLOCK_CONTROL__VI = 0x1D00; -constexpr unsigned int mmDCFE1_DCFE_DBG_CONFIG__VI = 0x1D02; -constexpr unsigned int mmDCFE1_DCFE_SOFT_RESET__VI = 0x1D01; -constexpr unsigned int mmDCFE2_DCFE_CLOCK_CONTROL__VI = 0x1F00; -constexpr unsigned int mmDCFE2_DCFE_DBG_CONFIG__VI = 0x1F02; -constexpr unsigned int mmDCFE2_DCFE_SOFT_RESET__VI = 0x1F01; -constexpr unsigned int mmDCFE3_DCFE_CLOCK_CONTROL__VI = 0x4100; -constexpr unsigned int mmDCFE3_DCFE_DBG_CONFIG__VI = 0x4102; -constexpr unsigned int mmDCFE3_DCFE_SOFT_RESET__VI = 0x4101; -constexpr unsigned int mmDCFE4_DCFE_CLOCK_CONTROL__VI = 0x4300; -constexpr unsigned int mmDCFE4_DCFE_DBG_CONFIG__VI = 0x4302; -constexpr unsigned int mmDCFE4_DCFE_SOFT_RESET__VI = 0x4301; -constexpr unsigned int mmDCFE5_DCFE_CLOCK_CONTROL__VI = 0x4500; -constexpr unsigned int mmDCFE5_DCFE_DBG_CONFIG__VI = 0x4502; -constexpr unsigned int mmDCFE5_DCFE_SOFT_RESET__VI = 0x4501; -constexpr unsigned int mmDCFEV0_CRTC_PIXEL_RATE_CNTL__VI = 0x0104; -constexpr unsigned int mmDCFEV0_PG_CONFIG__VI = 0x02DB; -constexpr unsigned int mmDCFEV0_PG_ENABLE__VI = 0x02DC; -constexpr unsigned int mmDCFEV0_PG_STATUS__VI = 0x02DD; -constexpr unsigned int mmDCFEV_CLOCK_CONTROL__VI = 0x46F4; -constexpr unsigned int mmDCFEV_DBG_CONFIG__VI = 0x46F7; -constexpr unsigned int mmDCFEV_DMIFV_CLOCK_CONTROL__VI = 0x46F6; -constexpr unsigned int mmDCFEV_DMIFV_MEM_PWR_CTRL__VI = 0x46F8; -constexpr unsigned int mmDCFEV_DMIFV_MEM_PWR_STATUS__VI = 0x46F9; -constexpr unsigned int mmDCFEV_SOFT_RESET__VI = 0x46F5; -constexpr unsigned int mmDCFE_CLOCK_CONTROL__VI = 0x1B00; -constexpr unsigned int mmDCFE_DBG_CONFIG__VI = 0x1B02; -constexpr unsigned int mmDCFE_DBG_SEL__VI = 0x1B7E; -constexpr unsigned int mmDCFE_MEM_PWR_CTRL__VI = 0x1B7F; -constexpr unsigned int mmDCFE_MEM_PWR_CTRL2__VI = 0x1BB8; -constexpr unsigned int mmDCFE_MEM_PWR_STATUS__VI = 0x1BB9; -constexpr unsigned int mmDCFE_SOFT_RESET__VI = 0x1B01; -constexpr unsigned int mmDCIO_CLOCK_CNTL__VI = 0x482D; -constexpr unsigned int mmDCIO_DEBUG__VI = 0x482F; -constexpr unsigned int mmDCIO_DEBUG_CONFIG__VI = 0x4835; -constexpr unsigned int mmDCIO_DPHY_SEL__VI = 0x4837; -constexpr unsigned int mmDCIO_GSL0_CNTL__VI = 0x4826; -constexpr unsigned int mmDCIO_GSL1_CNTL__VI = 0x4827; -constexpr unsigned int mmDCIO_GSL2_CNTL__VI = 0x4828; -constexpr unsigned int mmDCIO_GSL_GENLK_PAD_CNTL__VI = 0x4824; -constexpr unsigned int mmDCIO_GSL_SWAPLOCK_PAD_CNTL__VI = 0x4825; -constexpr unsigned int mmDCIO_IMPCAL_CNTL__VI = 0x483D; -constexpr unsigned int mmDCIO_IMPCAL_CNTL_CD__VI = 0x4841; -constexpr unsigned int mmDCIO_IMPCAL_CNTL_EF__VI = 0x4845; -constexpr unsigned int mmDCIO_SOFT_RESET__VI = 0x4836; -constexpr unsigned int mmDCIO_TEST_DEBUG_DATA__VI = 0x4832; -constexpr unsigned int mmDCIO_TEST_DEBUG_INDEX__VI = 0x4831; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__VI = 0x48C0; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__VI = 0x48C1; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__VI = 0x48CA; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__VI = 0x48CB; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__VI = 0x48CC; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__VI = 0x48CD; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__VI = 0x48CE; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__VI = 0x48CF; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__VI = 0x48D0; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__VI = 0x48D1; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__VI = 0x48D2; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__VI = 0x48D3; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__VI = 0x48C2; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__VI = 0x48D4; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__VI = 0x48D5; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__VI = 0x48D6; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__VI = 0x48D7; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__VI = 0x48D8; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__VI = 0x48D9; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__VI = 0x48DA; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__VI = 0x48DB; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__VI = 0x48DC; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__VI = 0x48DD; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__VI = 0x48C3; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__VI = 0x48DE; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__VI = 0x48DF; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__VI = 0x48C4; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__VI = 0x48C5; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__VI = 0x48C6; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__VI = 0x48C7; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__VI = 0x48C8; -constexpr unsigned int mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__VI = 0x48C9; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__VI = 0x48E0; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__VI = 0x48E1; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__VI = 0x48EA; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__VI = 0x48EB; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__VI = 0x48EC; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__VI = 0x48ED; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__VI = 0x48EE; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__VI = 0x48EF; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__VI = 0x48F0; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__VI = 0x48F1; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__VI = 0x48F2; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__VI = 0x48F3; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__VI = 0x48E2; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__VI = 0x48F4; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__VI = 0x48F5; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__VI = 0x48F6; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__VI = 0x48F7; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__VI = 0x48F8; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__VI = 0x48F9; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__VI = 0x48FA; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__VI = 0x48FB; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__VI = 0x48FC; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__VI = 0x48FD; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__VI = 0x48E3; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__VI = 0x48FE; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__VI = 0x48FF; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__VI = 0x48E4; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__VI = 0x48E5; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__VI = 0x48E6; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__VI = 0x48E7; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__VI = 0x48E8; -constexpr unsigned int mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__VI = 0x48E9; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__VI = 0x4900; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__VI = 0x4901; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__VI = 0x490A; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__VI = 0x490B; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__VI = 0x490C; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__VI = 0x490D; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__VI = 0x490E; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__VI = 0x490F; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__VI = 0x4910; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__VI = 0x4911; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__VI = 0x4912; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__VI = 0x4913; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__VI = 0x4902; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__VI = 0x4914; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__VI = 0x4915; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__VI = 0x4916; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__VI = 0x4917; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__VI = 0x4918; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__VI = 0x4919; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__VI = 0x491A; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__VI = 0x491B; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__VI = 0x491C; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__VI = 0x491D; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__VI = 0x4903; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__VI = 0x491E; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__VI = 0x491F; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__VI = 0x4904; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__VI = 0x4905; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__VI = 0x4906; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__VI = 0x4907; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__VI = 0x4908; -constexpr unsigned int mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__VI = 0x4909; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__VI = 0x4920; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__VI = 0x4921; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__VI = 0x492A; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__VI = 0x492B; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__VI = 0x492C; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__VI = 0x492D; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__VI = 0x492E; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__VI = 0x492F; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__VI = 0x4930; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__VI = 0x4931; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__VI = 0x4932; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__VI = 0x4933; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__VI = 0x4922; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__VI = 0x4934; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__VI = 0x4935; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__VI = 0x4936; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__VI = 0x4937; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__VI = 0x4938; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__VI = 0x4939; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__VI = 0x493A; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__VI = 0x493B; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__VI = 0x493C; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__VI = 0x493D; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__VI = 0x4923; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__VI = 0x493E; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__VI = 0x493F; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__VI = 0x4924; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__VI = 0x4925; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__VI = 0x4926; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__VI = 0x4927; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__VI = 0x4928; -constexpr unsigned int mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__VI = 0x4929; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__VI = 0x4940; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__VI = 0x4941; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__VI = 0x494A; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__VI = 0x494B; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__VI = 0x494C; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__VI = 0x494D; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__VI = 0x494E; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__VI = 0x494F; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__VI = 0x4950; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__VI = 0x4951; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__VI = 0x4952; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__VI = 0x4953; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__VI = 0x4942; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__VI = 0x4954; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__VI = 0x4955; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__VI = 0x4956; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__VI = 0x4957; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__VI = 0x4958; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__VI = 0x4959; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__VI = 0x495A; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__VI = 0x495B; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__VI = 0x495C; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__VI = 0x495D; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__VI = 0x4943; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__VI = 0x495E; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__VI = 0x495F; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__VI = 0x4944; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__VI = 0x4945; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__VI = 0x4946; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__VI = 0x4947; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__VI = 0x4948; -constexpr unsigned int mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__VI = 0x4949; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__VI = 0x4960; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__VI = 0x4961; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__VI = 0x496A; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__VI = 0x496B; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__VI = 0x496C; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__VI = 0x496D; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__VI = 0x496E; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__VI = 0x496F; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__VI = 0x4970; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__VI = 0x4971; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__VI = 0x4972; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__VI = 0x4973; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__VI = 0x4962; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__VI = 0x4974; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__VI = 0x4975; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__VI = 0x4976; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__VI = 0x4977; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__VI = 0x4978; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__VI = 0x4979; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__VI = 0x497A; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__VI = 0x497B; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__VI = 0x497C; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__VI = 0x497D; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__VI = 0x4963; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__VI = 0x497E; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__VI = 0x497F; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__VI = 0x4964; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__VI = 0x4965; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__VI = 0x4966; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__VI = 0x4967; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__VI = 0x4968; -constexpr unsigned int mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__VI = 0x4969; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__VI = 0x4980; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__VI = 0x4981; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__VI = 0x498A; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__VI = 0x498B; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__VI = 0x498C; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__VI = 0x498D; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__VI = 0x498E; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__VI = 0x498F; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__VI = 0x4990; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__VI = 0x4991; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__VI = 0x4992; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__VI = 0x4993; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__VI = 0x4982; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__VI = 0x4994; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__VI = 0x4995; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__VI = 0x4996; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__VI = 0x4997; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__VI = 0x4998; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__VI = 0x4999; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__VI = 0x499A; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__VI = 0x499B; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__VI = 0x499C; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__VI = 0x499D; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__VI = 0x4983; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__VI = 0x499E; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__VI = 0x499F; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__VI = 0x4984; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__VI = 0x4985; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__VI = 0x4986; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__VI = 0x4987; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__VI = 0x4988; -constexpr unsigned int mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__VI = 0x4989; -constexpr unsigned int mmDCIO_WRCMD_DELAY__VI = 0x4816; -constexpr unsigned int mmDCI_CLK_CNTL__VI = 0x0319; -constexpr unsigned int mmDCI_CLK_RAMP_CNTL__VI = 0x031A; -constexpr unsigned int mmDCI_DEBUG_CONFIG__VI = 0x0320; -constexpr unsigned int mmDCI_MEM_PWR_CNTL__VI = 0x031B; -constexpr unsigned int mmDCI_MEM_PWR_CNTL2__VI = 0x031C; -constexpr unsigned int mmDCI_MEM_PWR_CNTL3__VI = 0x031D; -constexpr unsigned int mmDCI_MEM_PWR_STATUS__VI = 0x0317; -constexpr unsigned int mmDCI_MEM_PWR_STATUS2__VI = 0x0318; -constexpr unsigned int mmDCI_PG_DEBUG_CONFIG__VI = 0x1812; -constexpr unsigned int mmDCI_SOFT_RESET__VI = 0x0328; -constexpr unsigned int mmDCI_TEST_DEBUG_DATA__VI = 0x031F; -constexpr unsigned int mmDCI_TEST_DEBUG_INDEX__VI = 0x031E; -constexpr unsigned int mmDCO_CLK_CNTL__VI = 0x1864; -constexpr unsigned int mmDCO_CLK_RAMP_CNTL__VI = 0x1865; -constexpr unsigned int mmDCO_DCFE_EXT_VSYNC_CNTL__VI = 0x4830; -constexpr unsigned int mmDCO_MEM_PWR_CTRL__VI = 0x1862; -constexpr unsigned int mmDCO_MEM_PWR_CTRL2__VI = 0x1863; -constexpr unsigned int mmDCO_MEM_PWR_STATUS__VI = 0x1861; -constexpr unsigned int mmDCO_POWER_MANAGEMENT_CNTL__VI = 0x1868; -constexpr unsigned int mmDCO_SCRATCH0__VI = 0x184E; -constexpr unsigned int mmDCO_SCRATCH1__VI = 0x184F; -constexpr unsigned int mmDCO_SCRATCH2__VI = 0x1850; -constexpr unsigned int mmDCO_SCRATCH3__VI = 0x1851; -constexpr unsigned int mmDCO_SCRATCH4__VI = 0x1852; -constexpr unsigned int mmDCO_SCRATCH5__VI = 0x1853; -constexpr unsigned int mmDCO_SCRATCH6__VI = 0x1854; -constexpr unsigned int mmDCO_SCRATCH7__VI = 0x1855; -constexpr unsigned int mmDCO_SOFT_RESET__VI = 0x1871; -constexpr unsigned int mmDCO_STEREOSYNC_SEL__VI = 0x186E; -constexpr unsigned int mmDCO_TEST_DEBUG_DATA__VI = 0x1870; -constexpr unsigned int mmDCO_TEST_DEBUG_INDEX__VI = 0x186F; -constexpr unsigned int mmDCP0_ALPHA_CONTROL__VI = 0x1ABC; -constexpr unsigned int mmDCP0_COMM_MATRIXA_TRANS_C11_C12__VI = 0x1A43; -constexpr unsigned int mmDCP0_COMM_MATRIXA_TRANS_C13_C14__VI = 0x1A44; -constexpr unsigned int mmDCP0_COMM_MATRIXA_TRANS_C21_C22__VI = 0x1A45; -constexpr unsigned int mmDCP0_COMM_MATRIXA_TRANS_C23_C24__VI = 0x1A46; -constexpr unsigned int mmDCP0_COMM_MATRIXA_TRANS_C31_C32__VI = 0x1A47; -constexpr unsigned int mmDCP0_COMM_MATRIXA_TRANS_C33_C34__VI = 0x1A48; -constexpr unsigned int mmDCP0_COMM_MATRIXB_TRANS_C11_C12__VI = 0x1A49; -constexpr unsigned int mmDCP0_COMM_MATRIXB_TRANS_C13_C14__VI = 0x1A4A; -constexpr unsigned int mmDCP0_COMM_MATRIXB_TRANS_C21_C22__VI = 0x1A4B; -constexpr unsigned int mmDCP0_COMM_MATRIXB_TRANS_C23_C24__VI = 0x1A4C; -constexpr unsigned int mmDCP0_COMM_MATRIXB_TRANS_C31_C32__VI = 0x1A4D; -constexpr unsigned int mmDCP0_COMM_MATRIXB_TRANS_C33_C34__VI = 0x1A4E; -constexpr unsigned int mmDCP0_CUR2_COLOR1__VI = 0x1A75; -constexpr unsigned int mmDCP0_CUR2_COLOR2__VI = 0x1A76; -constexpr unsigned int mmDCP0_CUR2_CONTROL__VI = 0x1A6F; -constexpr unsigned int mmDCP0_CUR2_HOT_SPOT__VI = 0x1A74; -constexpr unsigned int mmDCP0_CUR2_POSITION__VI = 0x1A73; -constexpr unsigned int mmDCP0_CUR2_SIZE__VI = 0x1A71; -constexpr unsigned int mmDCP0_CUR2_STEREO_CONTROL__VI = 0x1A9B; -constexpr unsigned int mmDCP0_CUR2_SURFACE_ADDRESS__VI = 0x1A70; -constexpr unsigned int mmDCP0_CUR2_SURFACE_ADDRESS_HIGH__VI = 0x1A72; -constexpr unsigned int mmDCP0_CUR2_UPDATE__VI = 0x1A77; -constexpr unsigned int mmDCP0_CUR_REQUEST_FILTER_CNTL__VI = 0x1A99; -constexpr unsigned int mmDCP0_CUR_STEREO_CONTROL__VI = 0x1A9A; -constexpr unsigned int mmDCP0_DCP_DEBUG2__VI = 0x1A98; -constexpr unsigned int mmDCP0_DCP_FP_CONVERTED_FIELD__VI = 0x1A65; -constexpr unsigned int mmDCP0_DCP_GSL_CONTROL__VI = 0x1A90; -constexpr unsigned int mmDCP0_DCP_RANDOM_SEEDS__VI = 0x1A61; -constexpr unsigned int mmDCP0_DCP_SPATIAL_DITHER_CNTL__VI = 0x1A60; -constexpr unsigned int mmDCP0_DC_LUT_VGA_ACCESS_ENABLE__VI = 0x1A7D; -constexpr unsigned int mmDCP0_DEGAMMA_CONTROL__VI = 0x1A58; -constexpr unsigned int mmDCP0_DENORM_CONTROL__VI = 0x1A50; -constexpr unsigned int mmDCP0_GAMUT_REMAP_C11_C12__VI = 0x1A5A; -constexpr unsigned int mmDCP0_GAMUT_REMAP_C13_C14__VI = 0x1A5B; -constexpr unsigned int mmDCP0_GAMUT_REMAP_C21_C22__VI = 0x1A5C; -constexpr unsigned int mmDCP0_GAMUT_REMAP_C23_C24__VI = 0x1A5D; -constexpr unsigned int mmDCP0_GAMUT_REMAP_C31_C32__VI = 0x1A5E; -constexpr unsigned int mmDCP0_GAMUT_REMAP_C33_C34__VI = 0x1A5F; -constexpr unsigned int mmDCP0_GAMUT_REMAP_CONTROL__VI = 0x1A59; -constexpr unsigned int mmDCP0_GRPH_FLIP_RATE_CNTL__VI = 0x1A8E; -constexpr unsigned int mmDCP0_GRPH_STEREOSYNC_FLIP__VI = 0x1A97; -constexpr unsigned int mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI = 0x1A9F; -constexpr unsigned int mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI = 0x1ABF; -constexpr unsigned int mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI = 0x1ABD; -constexpr unsigned int mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI = 0x1ABE; -constexpr unsigned int mmDCP0_HW_ROTATION__VI = 0x1A9E; -constexpr unsigned int mmDCP0_INPUT_CSC_C11_C12__VI = 0x1A36; -constexpr unsigned int mmDCP0_INPUT_CSC_C13_C14__VI = 0x1A37; -constexpr unsigned int mmDCP0_INPUT_CSC_C21_C22__VI = 0x1A38; -constexpr unsigned int mmDCP0_INPUT_CSC_C23_C24__VI = 0x1A39; -constexpr unsigned int mmDCP0_INPUT_CSC_C31_C32__VI = 0x1A3A; -constexpr unsigned int mmDCP0_INPUT_CSC_C33_C34__VI = 0x1A3B; -constexpr unsigned int mmDCP0_INPUT_CSC_CONTROL__VI = 0x1A35; -constexpr unsigned int mmDCP0_INPUT_GAMMA_CONTROL__VI = 0x1A10; -constexpr unsigned int mmDCP0_KEY_CONTROL__VI = 0x1A53; -constexpr unsigned int mmDCP0_KEY_RANGE_ALPHA__VI = 0x1A54; -constexpr unsigned int mmDCP0_KEY_RANGE_BLUE__VI = 0x1A57; -constexpr unsigned int mmDCP0_KEY_RANGE_GREEN__VI = 0x1A56; -constexpr unsigned int mmDCP0_KEY_RANGE_RED__VI = 0x1A55; -constexpr unsigned int mmDCP0_OUTPUT_CSC_C11_C12__VI = 0x1A3D; -constexpr unsigned int mmDCP0_OUTPUT_CSC_C13_C14__VI = 0x1A3E; -constexpr unsigned int mmDCP0_OUTPUT_CSC_C21_C22__VI = 0x1A3F; -constexpr unsigned int mmDCP0_OUTPUT_CSC_C23_C24__VI = 0x1A40; -constexpr unsigned int mmDCP0_OUTPUT_CSC_C31_C32__VI = 0x1A41; -constexpr unsigned int mmDCP0_OUTPUT_CSC_C33_C34__VI = 0x1A42; -constexpr unsigned int mmDCP0_OUTPUT_CSC_CONTROL__VI = 0x1A3C; -constexpr unsigned int mmDCP0_OUT_CLAMP_CONTROL_B_CB__VI = 0x1A9D; -constexpr unsigned int mmDCP0_OUT_CLAMP_CONTROL_G_Y__VI = 0x1A9C; -constexpr unsigned int mmDCP0_OUT_CLAMP_CONTROL_R_CR__VI = 0x1A52; -constexpr unsigned int mmDCP0_OUT_ROUND_CONTROL__VI = 0x1A51; -constexpr unsigned int mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS__VI = 0x1A92; -constexpr unsigned int mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x1A94; -constexpr unsigned int mmDCP0_OVL_STEREOSYNC_FLIP__VI = 0x1A93; -constexpr unsigned int mmDCP0_PRESCALE_GRPH_CONTROL__VI = 0x1A2D; -constexpr unsigned int mmDCP0_PRESCALE_OVL_CONTROL__VI = 0x1A31; -constexpr unsigned int mmDCP0_PRESCALE_VALUES_GRPH_B__VI = 0x1A30; -constexpr unsigned int mmDCP0_PRESCALE_VALUES_GRPH_G__VI = 0x1A2F; -constexpr unsigned int mmDCP0_PRESCALE_VALUES_GRPH_R__VI = 0x1A2E; -constexpr unsigned int mmDCP0_PRESCALE_VALUES_OVL_CB__VI = 0x1A32; -constexpr unsigned int mmDCP0_PRESCALE_VALUES_OVL_CR__VI = 0x1A34; -constexpr unsigned int mmDCP0_PRESCALE_VALUES_OVL_Y__VI = 0x1A33; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_END_CNTL1__VI = 0x1AA6; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_END_CNTL2__VI = 0x1AA7; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_REGION_0_1__VI = 0x1AA8; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_REGION_10_11__VI = 0x1AAD; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_REGION_12_13__VI = 0x1AAE; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_REGION_14_15__VI = 0x1AAF; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_REGION_2_3__VI = 0x1AA9; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_REGION_4_5__VI = 0x1AAA; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_REGION_6_7__VI = 0x1AAB; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_REGION_8_9__VI = 0x1AAC; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL__VI = 0x1AA5; -constexpr unsigned int mmDCP0_REGAMMA_CNTLA_START_CNTL__VI = 0x1AA4; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_END_CNTL1__VI = 0x1AB2; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_END_CNTL2__VI = 0x1AB3; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_REGION_0_1__VI = 0x1AB4; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_REGION_10_11__VI = 0x1AB9; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_REGION_12_13__VI = 0x1ABA; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_REGION_14_15__VI = 0x1ABB; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_REGION_2_3__VI = 0x1AB5; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_REGION_4_5__VI = 0x1AB6; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_REGION_6_7__VI = 0x1AB7; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_REGION_8_9__VI = 0x1AB8; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL__VI = 0x1AB1; -constexpr unsigned int mmDCP0_REGAMMA_CNTLB_START_CNTL__VI = 0x1AB0; -constexpr unsigned int mmDCP0_REGAMMA_CONTROL__VI = 0x1AA0; -constexpr unsigned int mmDCP0_REGAMMA_LUT_DATA__VI = 0x1AA2; -constexpr unsigned int mmDCP0_REGAMMA_LUT_INDEX__VI = 0x1AA1; -constexpr unsigned int mmDCP0_REGAMMA_LUT_WRITE_EN_MASK__VI = 0x1AA3; -constexpr unsigned int mmDCP1_ALPHA_CONTROL__VI = 0x1CBC; -constexpr unsigned int mmDCP1_COMM_MATRIXA_TRANS_C11_C12__VI = 0x1C43; -constexpr unsigned int mmDCP1_COMM_MATRIXA_TRANS_C13_C14__VI = 0x1C44; -constexpr unsigned int mmDCP1_COMM_MATRIXA_TRANS_C21_C22__VI = 0x1C45; -constexpr unsigned int mmDCP1_COMM_MATRIXA_TRANS_C23_C24__VI = 0x1C46; -constexpr unsigned int mmDCP1_COMM_MATRIXA_TRANS_C31_C32__VI = 0x1C47; -constexpr unsigned int mmDCP1_COMM_MATRIXA_TRANS_C33_C34__VI = 0x1C48; -constexpr unsigned int mmDCP1_COMM_MATRIXB_TRANS_C11_C12__VI = 0x1C49; -constexpr unsigned int mmDCP1_COMM_MATRIXB_TRANS_C13_C14__VI = 0x1C4A; -constexpr unsigned int mmDCP1_COMM_MATRIXB_TRANS_C21_C22__VI = 0x1C4B; -constexpr unsigned int mmDCP1_COMM_MATRIXB_TRANS_C23_C24__VI = 0x1C4C; -constexpr unsigned int mmDCP1_COMM_MATRIXB_TRANS_C31_C32__VI = 0x1C4D; -constexpr unsigned int mmDCP1_COMM_MATRIXB_TRANS_C33_C34__VI = 0x1C4E; -constexpr unsigned int mmDCP1_CUR2_COLOR1__VI = 0x1C75; -constexpr unsigned int mmDCP1_CUR2_COLOR2__VI = 0x1C76; -constexpr unsigned int mmDCP1_CUR2_CONTROL__VI = 0x1C6F; -constexpr unsigned int mmDCP1_CUR2_HOT_SPOT__VI = 0x1C74; -constexpr unsigned int mmDCP1_CUR2_POSITION__VI = 0x1C73; -constexpr unsigned int mmDCP1_CUR2_SIZE__VI = 0x1C71; -constexpr unsigned int mmDCP1_CUR2_STEREO_CONTROL__VI = 0x1C9B; -constexpr unsigned int mmDCP1_CUR2_SURFACE_ADDRESS__VI = 0x1C70; -constexpr unsigned int mmDCP1_CUR2_SURFACE_ADDRESS_HIGH__VI = 0x1C72; -constexpr unsigned int mmDCP1_CUR2_UPDATE__VI = 0x1C77; -constexpr unsigned int mmDCP1_CUR_COLOR1__VI = 0x1C6C; -constexpr unsigned int mmDCP1_CUR_COLOR2__VI = 0x1C6D; -constexpr unsigned int mmDCP1_CUR_CONTROL__VI = 0x1C66; -constexpr unsigned int mmDCP1_CUR_HOT_SPOT__VI = 0x1C6B; -constexpr unsigned int mmDCP1_CUR_POSITION__VI = 0x1C6A; -constexpr unsigned int mmDCP1_CUR_REQUEST_FILTER_CNTL__VI = 0x1C99; -constexpr unsigned int mmDCP1_CUR_SIZE__VI = 0x1C68; -constexpr unsigned int mmDCP1_CUR_STEREO_CONTROL__VI = 0x1C9A; -constexpr unsigned int mmDCP1_CUR_SURFACE_ADDRESS__VI = 0x1C67; -constexpr unsigned int mmDCP1_CUR_SURFACE_ADDRESS_HIGH__VI = 0x1C69; -constexpr unsigned int mmDCP1_CUR_UPDATE__VI = 0x1C6E; -constexpr unsigned int mmDCP1_DCP_CRC_CONTROL__VI = 0x1C87; -constexpr unsigned int mmDCP1_DCP_CRC_CURRENT__VI = 0x1C89; -constexpr unsigned int mmDCP1_DCP_CRC_LAST__VI = 0x1C8B; -constexpr unsigned int mmDCP1_DCP_CRC_MASK__VI = 0x1C88; -constexpr unsigned int mmDCP1_DCP_DEBUG__VI = 0x1C8D; -constexpr unsigned int mmDCP1_DCP_DEBUG2__VI = 0x1C98; -constexpr unsigned int mmDCP1_DCP_FP_CONVERTED_FIELD__VI = 0x1C65; -constexpr unsigned int mmDCP1_DCP_GSL_CONTROL__VI = 0x1C90; -constexpr unsigned int mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK__VI = 0x1C91; -constexpr unsigned int mmDCP1_DCP_RANDOM_SEEDS__VI = 0x1C61; -constexpr unsigned int mmDCP1_DCP_SPATIAL_DITHER_CNTL__VI = 0x1C60; -constexpr unsigned int mmDCP1_DCP_TEST_DEBUG_DATA__VI = 0x1C96; -constexpr unsigned int mmDCP1_DCP_TEST_DEBUG_INDEX__VI = 0x1C95; -constexpr unsigned int mmDCP1_DC_LUT_30_COLOR__VI = 0x1C7C; -constexpr unsigned int mmDCP1_DC_LUT_AUTOFILL__VI = 0x1C7F; -constexpr unsigned int mmDCP1_DC_LUT_BLACK_OFFSET_BLUE__VI = 0x1C81; -constexpr unsigned int mmDCP1_DC_LUT_BLACK_OFFSET_GREEN__VI = 0x1C82; -constexpr unsigned int mmDCP1_DC_LUT_BLACK_OFFSET_RED__VI = 0x1C83; -constexpr unsigned int mmDCP1_DC_LUT_CONTROL__VI = 0x1C80; -constexpr unsigned int mmDCP1_DC_LUT_PWL_DATA__VI = 0x1C7B; -constexpr unsigned int mmDCP1_DC_LUT_RW_INDEX__VI = 0x1C79; -constexpr unsigned int mmDCP1_DC_LUT_RW_MODE__VI = 0x1C78; -constexpr unsigned int mmDCP1_DC_LUT_SEQ_COLOR__VI = 0x1C7A; -constexpr unsigned int mmDCP1_DC_LUT_VGA_ACCESS_ENABLE__VI = 0x1C7D; -constexpr unsigned int mmDCP1_DC_LUT_WHITE_OFFSET_BLUE__VI = 0x1C84; -constexpr unsigned int mmDCP1_DC_LUT_WHITE_OFFSET_GREEN__VI = 0x1C85; -constexpr unsigned int mmDCP1_DC_LUT_WHITE_OFFSET_RED__VI = 0x1C86; -constexpr unsigned int mmDCP1_DC_LUT_WRITE_EN_MASK__VI = 0x1C7E; -constexpr unsigned int mmDCP1_DEGAMMA_CONTROL__VI = 0x1C58; -constexpr unsigned int mmDCP1_DENORM_CONTROL__VI = 0x1C50; -constexpr unsigned int mmDCP1_GAMUT_REMAP_C11_C12__VI = 0x1C5A; -constexpr unsigned int mmDCP1_GAMUT_REMAP_C13_C14__VI = 0x1C5B; -constexpr unsigned int mmDCP1_GAMUT_REMAP_C21_C22__VI = 0x1C5C; -constexpr unsigned int mmDCP1_GAMUT_REMAP_C23_C24__VI = 0x1C5D; -constexpr unsigned int mmDCP1_GAMUT_REMAP_C31_C32__VI = 0x1C5E; -constexpr unsigned int mmDCP1_GAMUT_REMAP_C33_C34__VI = 0x1C5F; -constexpr unsigned int mmDCP1_GAMUT_REMAP_CONTROL__VI = 0x1C59; -constexpr unsigned int mmDCP1_GRPH_COMPRESS_PITCH__VI = 0x1C1A; -constexpr unsigned int mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS__VI = 0x1C19; -constexpr unsigned int mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__VI = 0x1C1B; -constexpr unsigned int mmDCP1_GRPH_CONTROL__SI__CI = 0x1D01; -constexpr unsigned int mmDCP1_GRPH_CONTROL__VI = 0x1C01; -constexpr unsigned int mmDCP1_GRPH_DFQ_CONTROL__VI = 0x1C14; -constexpr unsigned int mmDCP1_GRPH_DFQ_STATUS__VI = 0x1C15; -constexpr unsigned int mmDCP1_GRPH_ENABLE__VI = 0x1C00; -constexpr unsigned int mmDCP1_GRPH_FLIP_CONTROL__SI__CI = 0x1D12; -constexpr unsigned int mmDCP1_GRPH_FLIP_CONTROL__VI = 0x1C12; -constexpr unsigned int mmDCP1_GRPH_FLIP_RATE_CNTL__VI = 0x1C8E; -constexpr unsigned int mmDCP1_GRPH_INTERRUPT_CONTROL__VI = 0x1C17; -constexpr unsigned int mmDCP1_GRPH_INTERRUPT_STATUS__VI = 0x1C16; -constexpr unsigned int mmDCP1_GRPH_LUT_10BIT_BYPASS__VI = 0x1C02; -constexpr unsigned int mmDCP1_GRPH_PITCH__SI__CI = 0x1D06; -constexpr unsigned int mmDCP1_GRPH_PITCH__VI = 0x1C06; -constexpr unsigned int mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS__SI__CI = 0x1D04; -constexpr unsigned int mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS__VI = 0x1C04; -constexpr unsigned int mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI = 0x1C07; -constexpr unsigned int mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS__VI = 0x1C05; -constexpr unsigned int mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x1C08; -constexpr unsigned int mmDCP1_GRPH_STEREOSYNC_FLIP__VI = 0x1C97; -constexpr unsigned int mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE__VI = 0x1C18; -constexpr unsigned int mmDCP1_GRPH_SURFACE_ADDRESS_INUSE__VI = 0x1C13; -constexpr unsigned int mmDCP1_GRPH_SURFACE_OFFSET_X__VI = 0x1C09; -constexpr unsigned int mmDCP1_GRPH_SURFACE_OFFSET_Y__VI = 0x1C0A; -constexpr unsigned int mmDCP1_GRPH_SWAP_CNTL__VI = 0x1C03; -constexpr unsigned int mmDCP1_GRPH_UPDATE__SI__CI = 0x1D11; -constexpr unsigned int mmDCP1_GRPH_UPDATE__VI = 0x1C11; -constexpr unsigned int mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI = 0x1C9F; -constexpr unsigned int mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI = 0x1CBF; -constexpr unsigned int mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI = 0x1CBD; -constexpr unsigned int mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI = 0x1CBE; -constexpr unsigned int mmDCP1_GRPH_X_END__VI = 0x1C0D; -constexpr unsigned int mmDCP1_GRPH_X_START__VI = 0x1C0B; -constexpr unsigned int mmDCP1_GRPH_Y_END__VI = 0x1C0E; -constexpr unsigned int mmDCP1_GRPH_Y_START__VI = 0x1C0C; -constexpr unsigned int mmDCP1_HW_ROTATION__VI = 0x1C9E; -constexpr unsigned int mmDCP1_INPUT_CSC_C11_C12__VI = 0x1C36; -constexpr unsigned int mmDCP1_INPUT_CSC_C13_C14__VI = 0x1C37; -constexpr unsigned int mmDCP1_INPUT_CSC_C21_C22__VI = 0x1C38; -constexpr unsigned int mmDCP1_INPUT_CSC_C23_C24__VI = 0x1C39; -constexpr unsigned int mmDCP1_INPUT_CSC_C31_C32__VI = 0x1C3A; -constexpr unsigned int mmDCP1_INPUT_CSC_C33_C34__VI = 0x1C3B; -constexpr unsigned int mmDCP1_INPUT_CSC_CONTROL__VI = 0x1C35; -constexpr unsigned int mmDCP1_INPUT_GAMMA_CONTROL__VI = 0x1C10; -constexpr unsigned int mmDCP1_KEY_CONTROL__VI = 0x1C53; -constexpr unsigned int mmDCP1_KEY_RANGE_ALPHA__VI = 0x1C54; -constexpr unsigned int mmDCP1_KEY_RANGE_BLUE__VI = 0x1C57; -constexpr unsigned int mmDCP1_KEY_RANGE_GREEN__VI = 0x1C56; -constexpr unsigned int mmDCP1_KEY_RANGE_RED__VI = 0x1C55; -constexpr unsigned int mmDCP1_OUTPUT_CSC_C11_C12__VI = 0x1C3D; -constexpr unsigned int mmDCP1_OUTPUT_CSC_C13_C14__VI = 0x1C3E; -constexpr unsigned int mmDCP1_OUTPUT_CSC_C21_C22__VI = 0x1C3F; -constexpr unsigned int mmDCP1_OUTPUT_CSC_C23_C24__VI = 0x1C40; -constexpr unsigned int mmDCP1_OUTPUT_CSC_C31_C32__VI = 0x1C41; -constexpr unsigned int mmDCP1_OUTPUT_CSC_C33_C34__VI = 0x1C42; -constexpr unsigned int mmDCP1_OUTPUT_CSC_CONTROL__VI = 0x1C3C; -constexpr unsigned int mmDCP1_OUT_CLAMP_CONTROL_B_CB__VI = 0x1C9D; -constexpr unsigned int mmDCP1_OUT_CLAMP_CONTROL_G_Y__VI = 0x1C9C; -constexpr unsigned int mmDCP1_OUT_CLAMP_CONTROL_R_CR__VI = 0x1C52; -constexpr unsigned int mmDCP1_OUT_ROUND_CONTROL__VI = 0x1C51; -constexpr unsigned int mmDCP1_OVLSCL_EDGE_PIXEL_CNTL__VI = 0x1C2C; -constexpr unsigned int mmDCP1_OVL_CONTROL1__VI = 0x1C1D; -constexpr unsigned int mmDCP1_OVL_CONTROL2__VI = 0x1C1E; -constexpr unsigned int mmDCP1_OVL_DFQ_CONTROL__VI = 0x1C29; -constexpr unsigned int mmDCP1_OVL_DFQ_STATUS__VI = 0x1C2A; -constexpr unsigned int mmDCP1_OVL_ENABLE__VI = 0x1C1C; -constexpr unsigned int mmDCP1_OVL_END__VI = 0x1C26; -constexpr unsigned int mmDCP1_OVL_PITCH__VI = 0x1C21; -constexpr unsigned int mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS__VI = 0x1C92; -constexpr unsigned int mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x1C94; -constexpr unsigned int mmDCP1_OVL_START__VI = 0x1C25; -constexpr unsigned int mmDCP1_OVL_STEREOSYNC_FLIP__VI = 0x1C93; -constexpr unsigned int mmDCP1_OVL_SURFACE_ADDRESS__SI__CI = 0x1D20; -constexpr unsigned int mmDCP1_OVL_SURFACE_ADDRESS__VI = 0x1C20; -constexpr unsigned int mmDCP1_OVL_SURFACE_ADDRESS_HIGH__VI = 0x1C22; -constexpr unsigned int mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE__VI = 0x1C2B; -constexpr unsigned int mmDCP1_OVL_SURFACE_ADDRESS_INUSE__VI = 0x1C28; -constexpr unsigned int mmDCP1_OVL_SURFACE_OFFSET_X__VI = 0x1C23; -constexpr unsigned int mmDCP1_OVL_SURFACE_OFFSET_Y__VI = 0x1C24; -constexpr unsigned int mmDCP1_OVL_SWAP_CNTL__VI = 0x1C1F; -constexpr unsigned int mmDCP1_OVL_UPDATE__VI = 0x1C27; -constexpr unsigned int mmDCP1_PRESCALE_GRPH_CONTROL__VI = 0x1C2D; -constexpr unsigned int mmDCP1_PRESCALE_OVL_CONTROL__VI = 0x1C31; -constexpr unsigned int mmDCP1_PRESCALE_VALUES_GRPH_B__VI = 0x1C30; -constexpr unsigned int mmDCP1_PRESCALE_VALUES_GRPH_G__VI = 0x1C2F; -constexpr unsigned int mmDCP1_PRESCALE_VALUES_GRPH_R__VI = 0x1C2E; -constexpr unsigned int mmDCP1_PRESCALE_VALUES_OVL_CB__VI = 0x1C32; -constexpr unsigned int mmDCP1_PRESCALE_VALUES_OVL_CR__VI = 0x1C34; -constexpr unsigned int mmDCP1_PRESCALE_VALUES_OVL_Y__VI = 0x1C33; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_END_CNTL1__VI = 0x1CA6; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_END_CNTL2__VI = 0x1CA7; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_REGION_0_1__VI = 0x1CA8; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_REGION_10_11__VI = 0x1CAD; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_REGION_12_13__VI = 0x1CAE; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_REGION_14_15__VI = 0x1CAF; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_REGION_2_3__VI = 0x1CA9; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_REGION_4_5__VI = 0x1CAA; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_REGION_6_7__VI = 0x1CAB; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_REGION_8_9__VI = 0x1CAC; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL__VI = 0x1CA5; -constexpr unsigned int mmDCP1_REGAMMA_CNTLA_START_CNTL__VI = 0x1CA4; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_END_CNTL1__VI = 0x1CB2; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_END_CNTL2__VI = 0x1CB3; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_REGION_0_1__VI = 0x1CB4; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_REGION_10_11__VI = 0x1CB9; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_REGION_12_13__VI = 0x1CBA; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_REGION_14_15__VI = 0x1CBB; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_REGION_2_3__VI = 0x1CB5; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_REGION_4_5__VI = 0x1CB6; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_REGION_6_7__VI = 0x1CB7; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_REGION_8_9__VI = 0x1CB8; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL__VI = 0x1CB1; -constexpr unsigned int mmDCP1_REGAMMA_CNTLB_START_CNTL__VI = 0x1CB0; -constexpr unsigned int mmDCP1_REGAMMA_CONTROL__VI = 0x1CA0; -constexpr unsigned int mmDCP1_REGAMMA_LUT_DATA__VI = 0x1CA2; -constexpr unsigned int mmDCP1_REGAMMA_LUT_INDEX__VI = 0x1CA1; -constexpr unsigned int mmDCP1_REGAMMA_LUT_WRITE_EN_MASK__VI = 0x1CA3; -constexpr unsigned int mmDCP2_ALPHA_CONTROL__VI = 0x1EBC; -constexpr unsigned int mmDCP2_COMM_MATRIXA_TRANS_C11_C12__VI = 0x1E43; -constexpr unsigned int mmDCP2_COMM_MATRIXA_TRANS_C13_C14__VI = 0x1E44; -constexpr unsigned int mmDCP2_COMM_MATRIXA_TRANS_C21_C22__VI = 0x1E45; -constexpr unsigned int mmDCP2_COMM_MATRIXA_TRANS_C23_C24__VI = 0x1E46; -constexpr unsigned int mmDCP2_COMM_MATRIXA_TRANS_C31_C32__VI = 0x1E47; -constexpr unsigned int mmDCP2_COMM_MATRIXA_TRANS_C33_C34__VI = 0x1E48; -constexpr unsigned int mmDCP2_COMM_MATRIXB_TRANS_C11_C12__VI = 0x1E49; -constexpr unsigned int mmDCP2_COMM_MATRIXB_TRANS_C13_C14__VI = 0x1E4A; -constexpr unsigned int mmDCP2_COMM_MATRIXB_TRANS_C21_C22__VI = 0x1E4B; -constexpr unsigned int mmDCP2_COMM_MATRIXB_TRANS_C23_C24__VI = 0x1E4C; -constexpr unsigned int mmDCP2_COMM_MATRIXB_TRANS_C31_C32__VI = 0x1E4D; -constexpr unsigned int mmDCP2_COMM_MATRIXB_TRANS_C33_C34__VI = 0x1E4E; -constexpr unsigned int mmDCP2_CUR2_COLOR1__VI = 0x1E75; -constexpr unsigned int mmDCP2_CUR2_COLOR2__VI = 0x1E76; -constexpr unsigned int mmDCP2_CUR2_CONTROL__VI = 0x1E6F; -constexpr unsigned int mmDCP2_CUR2_HOT_SPOT__VI = 0x1E74; -constexpr unsigned int mmDCP2_CUR2_POSITION__VI = 0x1E73; -constexpr unsigned int mmDCP2_CUR2_SIZE__VI = 0x1E71; -constexpr unsigned int mmDCP2_CUR2_STEREO_CONTROL__VI = 0x1E9B; -constexpr unsigned int mmDCP2_CUR2_SURFACE_ADDRESS__VI = 0x1E70; -constexpr unsigned int mmDCP2_CUR2_SURFACE_ADDRESS_HIGH__VI = 0x1E72; -constexpr unsigned int mmDCP2_CUR2_UPDATE__VI = 0x1E77; -constexpr unsigned int mmDCP2_CUR_COLOR1__VI = 0x1E6C; -constexpr unsigned int mmDCP2_CUR_COLOR2__VI = 0x1E6D; -constexpr unsigned int mmDCP2_CUR_CONTROL__VI = 0x1E66; -constexpr unsigned int mmDCP2_CUR_HOT_SPOT__VI = 0x1E6B; -constexpr unsigned int mmDCP2_CUR_POSITION__VI = 0x1E6A; -constexpr unsigned int mmDCP2_CUR_REQUEST_FILTER_CNTL__VI = 0x1E99; -constexpr unsigned int mmDCP2_CUR_SIZE__VI = 0x1E68; -constexpr unsigned int mmDCP2_CUR_STEREO_CONTROL__VI = 0x1E9A; -constexpr unsigned int mmDCP2_CUR_SURFACE_ADDRESS__VI = 0x1E67; -constexpr unsigned int mmDCP2_CUR_SURFACE_ADDRESS_HIGH__VI = 0x1E69; -constexpr unsigned int mmDCP2_CUR_UPDATE__VI = 0x1E6E; -constexpr unsigned int mmDCP2_DCP_CRC_CONTROL__VI = 0x1E87; -constexpr unsigned int mmDCP2_DCP_CRC_CURRENT__VI = 0x1E89; -constexpr unsigned int mmDCP2_DCP_CRC_LAST__VI = 0x1E8B; -constexpr unsigned int mmDCP2_DCP_CRC_MASK__VI = 0x1E88; -constexpr unsigned int mmDCP2_DCP_DEBUG__VI = 0x1E8D; -constexpr unsigned int mmDCP2_DCP_DEBUG2__VI = 0x1E98; -constexpr unsigned int mmDCP2_DCP_FP_CONVERTED_FIELD__VI = 0x1E65; -constexpr unsigned int mmDCP2_DCP_GSL_CONTROL__VI = 0x1E90; -constexpr unsigned int mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK__VI = 0x1E91; -constexpr unsigned int mmDCP2_DCP_RANDOM_SEEDS__VI = 0x1E61; -constexpr unsigned int mmDCP2_DCP_SPATIAL_DITHER_CNTL__VI = 0x1E60; -constexpr unsigned int mmDCP2_DCP_TEST_DEBUG_DATA__VI = 0x1E96; -constexpr unsigned int mmDCP2_DCP_TEST_DEBUG_INDEX__VI = 0x1E95; -constexpr unsigned int mmDCP2_DC_LUT_30_COLOR__VI = 0x1E7C; -constexpr unsigned int mmDCP2_DC_LUT_AUTOFILL__VI = 0x1E7F; -constexpr unsigned int mmDCP2_DC_LUT_BLACK_OFFSET_BLUE__VI = 0x1E81; -constexpr unsigned int mmDCP2_DC_LUT_BLACK_OFFSET_GREEN__VI = 0x1E82; -constexpr unsigned int mmDCP2_DC_LUT_BLACK_OFFSET_RED__VI = 0x1E83; -constexpr unsigned int mmDCP2_DC_LUT_CONTROL__VI = 0x1E80; -constexpr unsigned int mmDCP2_DC_LUT_PWL_DATA__VI = 0x1E7B; -constexpr unsigned int mmDCP2_DC_LUT_RW_INDEX__VI = 0x1E79; -constexpr unsigned int mmDCP2_DC_LUT_RW_MODE__VI = 0x1E78; -constexpr unsigned int mmDCP2_DC_LUT_SEQ_COLOR__VI = 0x1E7A; -constexpr unsigned int mmDCP2_DC_LUT_VGA_ACCESS_ENABLE__VI = 0x1E7D; -constexpr unsigned int mmDCP2_DC_LUT_WHITE_OFFSET_BLUE__VI = 0x1E84; -constexpr unsigned int mmDCP2_DC_LUT_WHITE_OFFSET_GREEN__VI = 0x1E85; -constexpr unsigned int mmDCP2_DC_LUT_WHITE_OFFSET_RED__VI = 0x1E86; -constexpr unsigned int mmDCP2_DC_LUT_WRITE_EN_MASK__VI = 0x1E7E; -constexpr unsigned int mmDCP2_DEGAMMA_CONTROL__VI = 0x1E58; -constexpr unsigned int mmDCP2_DENORM_CONTROL__VI = 0x1E50; -constexpr unsigned int mmDCP2_GAMUT_REMAP_C11_C12__VI = 0x1E5A; -constexpr unsigned int mmDCP2_GAMUT_REMAP_C13_C14__VI = 0x1E5B; -constexpr unsigned int mmDCP2_GAMUT_REMAP_C21_C22__VI = 0x1E5C; -constexpr unsigned int mmDCP2_GAMUT_REMAP_C23_C24__VI = 0x1E5D; -constexpr unsigned int mmDCP2_GAMUT_REMAP_C31_C32__VI = 0x1E5E; -constexpr unsigned int mmDCP2_GAMUT_REMAP_C33_C34__VI = 0x1E5F; -constexpr unsigned int mmDCP2_GAMUT_REMAP_CONTROL__VI = 0x1E59; -constexpr unsigned int mmDCP2_GRPH_COMPRESS_PITCH__VI = 0x1E1A; -constexpr unsigned int mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS__VI = 0x1E19; -constexpr unsigned int mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__VI = 0x1E1B; -constexpr unsigned int mmDCP2_GRPH_CONTROL__SI__CI = 0x4001; -constexpr unsigned int mmDCP2_GRPH_CONTROL__VI = 0x1E01; -constexpr unsigned int mmDCP2_GRPH_DFQ_CONTROL__VI = 0x1E14; -constexpr unsigned int mmDCP2_GRPH_DFQ_STATUS__VI = 0x1E15; -constexpr unsigned int mmDCP2_GRPH_ENABLE__VI = 0x1E00; -constexpr unsigned int mmDCP2_GRPH_FLIP_CONTROL__SI__CI = 0x4012; -constexpr unsigned int mmDCP2_GRPH_FLIP_CONTROL__VI = 0x1E12; -constexpr unsigned int mmDCP2_GRPH_FLIP_RATE_CNTL__VI = 0x1E8E; -constexpr unsigned int mmDCP2_GRPH_INTERRUPT_CONTROL__VI = 0x1E17; -constexpr unsigned int mmDCP2_GRPH_INTERRUPT_STATUS__VI = 0x1E16; -constexpr unsigned int mmDCP2_GRPH_LUT_10BIT_BYPASS__VI = 0x1E02; -constexpr unsigned int mmDCP2_GRPH_PITCH__SI__CI = 0x4006; -constexpr unsigned int mmDCP2_GRPH_PITCH__VI = 0x1E06; -constexpr unsigned int mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS__SI__CI = 0x4004; -constexpr unsigned int mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS__VI = 0x1E04; -constexpr unsigned int mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI = 0x1E07; -constexpr unsigned int mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS__VI = 0x1E05; -constexpr unsigned int mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x1E08; -constexpr unsigned int mmDCP2_GRPH_STEREOSYNC_FLIP__VI = 0x1E97; -constexpr unsigned int mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE__VI = 0x1E18; -constexpr unsigned int mmDCP2_GRPH_SURFACE_ADDRESS_INUSE__VI = 0x1E13; -constexpr unsigned int mmDCP2_GRPH_SURFACE_OFFSET_X__VI = 0x1E09; -constexpr unsigned int mmDCP2_GRPH_SURFACE_OFFSET_Y__VI = 0x1E0A; -constexpr unsigned int mmDCP2_GRPH_SWAP_CNTL__VI = 0x1E03; -constexpr unsigned int mmDCP2_GRPH_UPDATE__SI__CI = 0x4011; -constexpr unsigned int mmDCP2_GRPH_UPDATE__VI = 0x1E11; -constexpr unsigned int mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI = 0x1E9F; -constexpr unsigned int mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI = 0x1EBF; -constexpr unsigned int mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI = 0x1EBD; -constexpr unsigned int mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI = 0x1EBE; -constexpr unsigned int mmDCP2_GRPH_X_END__VI = 0x1E0D; -constexpr unsigned int mmDCP2_GRPH_X_START__VI = 0x1E0B; -constexpr unsigned int mmDCP2_GRPH_Y_END__VI = 0x1E0E; -constexpr unsigned int mmDCP2_GRPH_Y_START__VI = 0x1E0C; -constexpr unsigned int mmDCP2_HW_ROTATION__VI = 0x1E9E; -constexpr unsigned int mmDCP2_INPUT_CSC_C11_C12__VI = 0x1E36; -constexpr unsigned int mmDCP2_INPUT_CSC_C13_C14__VI = 0x1E37; -constexpr unsigned int mmDCP2_INPUT_CSC_C21_C22__VI = 0x1E38; -constexpr unsigned int mmDCP2_INPUT_CSC_C23_C24__VI = 0x1E39; -constexpr unsigned int mmDCP2_INPUT_CSC_C31_C32__VI = 0x1E3A; -constexpr unsigned int mmDCP2_INPUT_CSC_C33_C34__VI = 0x1E3B; -constexpr unsigned int mmDCP2_INPUT_CSC_CONTROL__VI = 0x1E35; -constexpr unsigned int mmDCP2_INPUT_GAMMA_CONTROL__VI = 0x1E10; -constexpr unsigned int mmDCP2_KEY_CONTROL__VI = 0x1E53; -constexpr unsigned int mmDCP2_KEY_RANGE_ALPHA__VI = 0x1E54; -constexpr unsigned int mmDCP2_KEY_RANGE_BLUE__VI = 0x1E57; -constexpr unsigned int mmDCP2_KEY_RANGE_GREEN__VI = 0x1E56; -constexpr unsigned int mmDCP2_KEY_RANGE_RED__VI = 0x1E55; -constexpr unsigned int mmDCP2_OUTPUT_CSC_C11_C12__VI = 0x1E3D; -constexpr unsigned int mmDCP2_OUTPUT_CSC_C13_C14__VI = 0x1E3E; -constexpr unsigned int mmDCP2_OUTPUT_CSC_C21_C22__VI = 0x1E3F; -constexpr unsigned int mmDCP2_OUTPUT_CSC_C23_C24__VI = 0x1E40; -constexpr unsigned int mmDCP2_OUTPUT_CSC_C31_C32__VI = 0x1E41; -constexpr unsigned int mmDCP2_OUTPUT_CSC_C33_C34__VI = 0x1E42; -constexpr unsigned int mmDCP2_OUTPUT_CSC_CONTROL__VI = 0x1E3C; -constexpr unsigned int mmDCP2_OUT_CLAMP_CONTROL_B_CB__VI = 0x1E9D; -constexpr unsigned int mmDCP2_OUT_CLAMP_CONTROL_G_Y__VI = 0x1E9C; -constexpr unsigned int mmDCP2_OUT_CLAMP_CONTROL_R_CR__VI = 0x1E52; -constexpr unsigned int mmDCP2_OUT_ROUND_CONTROL__VI = 0x1E51; -constexpr unsigned int mmDCP2_OVLSCL_EDGE_PIXEL_CNTL__VI = 0x1E2C; -constexpr unsigned int mmDCP2_OVL_CONTROL1__VI = 0x1E1D; -constexpr unsigned int mmDCP2_OVL_CONTROL2__VI = 0x1E1E; -constexpr unsigned int mmDCP2_OVL_DFQ_CONTROL__VI = 0x1E29; -constexpr unsigned int mmDCP2_OVL_DFQ_STATUS__VI = 0x1E2A; -constexpr unsigned int mmDCP2_OVL_ENABLE__VI = 0x1E1C; -constexpr unsigned int mmDCP2_OVL_END__VI = 0x1E26; -constexpr unsigned int mmDCP2_OVL_PITCH__VI = 0x1E21; -constexpr unsigned int mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS__VI = 0x1E92; -constexpr unsigned int mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x1E94; -constexpr unsigned int mmDCP2_OVL_START__VI = 0x1E25; -constexpr unsigned int mmDCP2_OVL_STEREOSYNC_FLIP__VI = 0x1E93; -constexpr unsigned int mmDCP2_OVL_SURFACE_ADDRESS__SI__CI = 0x4020; -constexpr unsigned int mmDCP2_OVL_SURFACE_ADDRESS__VI = 0x1E20; -constexpr unsigned int mmDCP2_OVL_SURFACE_ADDRESS_HIGH__VI = 0x1E22; -constexpr unsigned int mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE__VI = 0x1E2B; -constexpr unsigned int mmDCP2_OVL_SURFACE_ADDRESS_INUSE__VI = 0x1E28; -constexpr unsigned int mmDCP2_OVL_SURFACE_OFFSET_X__VI = 0x1E23; -constexpr unsigned int mmDCP2_OVL_SURFACE_OFFSET_Y__VI = 0x1E24; -constexpr unsigned int mmDCP2_OVL_SWAP_CNTL__VI = 0x1E1F; -constexpr unsigned int mmDCP2_OVL_UPDATE__VI = 0x1E27; -constexpr unsigned int mmDCP2_PRESCALE_GRPH_CONTROL__VI = 0x1E2D; -constexpr unsigned int mmDCP2_PRESCALE_OVL_CONTROL__VI = 0x1E31; -constexpr unsigned int mmDCP2_PRESCALE_VALUES_GRPH_B__VI = 0x1E30; -constexpr unsigned int mmDCP2_PRESCALE_VALUES_GRPH_G__VI = 0x1E2F; -constexpr unsigned int mmDCP2_PRESCALE_VALUES_GRPH_R__VI = 0x1E2E; -constexpr unsigned int mmDCP2_PRESCALE_VALUES_OVL_CB__VI = 0x1E32; -constexpr unsigned int mmDCP2_PRESCALE_VALUES_OVL_CR__VI = 0x1E34; -constexpr unsigned int mmDCP2_PRESCALE_VALUES_OVL_Y__VI = 0x1E33; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_END_CNTL1__VI = 0x1EA6; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_END_CNTL2__VI = 0x1EA7; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_REGION_0_1__VI = 0x1EA8; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_REGION_10_11__VI = 0x1EAD; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_REGION_12_13__VI = 0x1EAE; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_REGION_14_15__VI = 0x1EAF; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_REGION_2_3__VI = 0x1EA9; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_REGION_4_5__VI = 0x1EAA; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_REGION_6_7__VI = 0x1EAB; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_REGION_8_9__VI = 0x1EAC; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL__VI = 0x1EA5; -constexpr unsigned int mmDCP2_REGAMMA_CNTLA_START_CNTL__VI = 0x1EA4; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_END_CNTL1__VI = 0x1EB2; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_END_CNTL2__VI = 0x1EB3; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_REGION_0_1__VI = 0x1EB4; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_REGION_10_11__VI = 0x1EB9; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_REGION_12_13__VI = 0x1EBA; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_REGION_14_15__VI = 0x1EBB; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_REGION_2_3__VI = 0x1EB5; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_REGION_4_5__VI = 0x1EB6; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_REGION_6_7__VI = 0x1EB7; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_REGION_8_9__VI = 0x1EB8; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL__VI = 0x1EB1; -constexpr unsigned int mmDCP2_REGAMMA_CNTLB_START_CNTL__VI = 0x1EB0; -constexpr unsigned int mmDCP2_REGAMMA_CONTROL__VI = 0x1EA0; -constexpr unsigned int mmDCP2_REGAMMA_LUT_DATA__VI = 0x1EA2; -constexpr unsigned int mmDCP2_REGAMMA_LUT_INDEX__VI = 0x1EA1; -constexpr unsigned int mmDCP2_REGAMMA_LUT_WRITE_EN_MASK__VI = 0x1EA3; -constexpr unsigned int mmDCP3_ALPHA_CONTROL__VI = 0x40BC; -constexpr unsigned int mmDCP3_COMM_MATRIXA_TRANS_C11_C12__VI = 0x4043; -constexpr unsigned int mmDCP3_COMM_MATRIXA_TRANS_C13_C14__VI = 0x4044; -constexpr unsigned int mmDCP3_COMM_MATRIXA_TRANS_C21_C22__VI = 0x4045; -constexpr unsigned int mmDCP3_COMM_MATRIXA_TRANS_C23_C24__VI = 0x4046; -constexpr unsigned int mmDCP3_COMM_MATRIXA_TRANS_C31_C32__VI = 0x4047; -constexpr unsigned int mmDCP3_COMM_MATRIXA_TRANS_C33_C34__VI = 0x4048; -constexpr unsigned int mmDCP3_COMM_MATRIXB_TRANS_C11_C12__VI = 0x4049; -constexpr unsigned int mmDCP3_COMM_MATRIXB_TRANS_C13_C14__VI = 0x404A; -constexpr unsigned int mmDCP3_COMM_MATRIXB_TRANS_C21_C22__VI = 0x404B; -constexpr unsigned int mmDCP3_COMM_MATRIXB_TRANS_C23_C24__VI = 0x404C; -constexpr unsigned int mmDCP3_COMM_MATRIXB_TRANS_C31_C32__VI = 0x404D; -constexpr unsigned int mmDCP3_COMM_MATRIXB_TRANS_C33_C34__VI = 0x404E; -constexpr unsigned int mmDCP3_CUR2_COLOR1__VI = 0x4075; -constexpr unsigned int mmDCP3_CUR2_COLOR2__VI = 0x4076; -constexpr unsigned int mmDCP3_CUR2_CONTROL__VI = 0x406F; -constexpr unsigned int mmDCP3_CUR2_HOT_SPOT__VI = 0x4074; -constexpr unsigned int mmDCP3_CUR2_POSITION__VI = 0x4073; -constexpr unsigned int mmDCP3_CUR2_SIZE__VI = 0x4071; -constexpr unsigned int mmDCP3_CUR2_STEREO_CONTROL__VI = 0x409B; -constexpr unsigned int mmDCP3_CUR2_SURFACE_ADDRESS__VI = 0x4070; -constexpr unsigned int mmDCP3_CUR2_SURFACE_ADDRESS_HIGH__VI = 0x4072; -constexpr unsigned int mmDCP3_CUR2_UPDATE__VI = 0x4077; -constexpr unsigned int mmDCP3_CUR_COLOR1__VI = 0x406C; -constexpr unsigned int mmDCP3_CUR_COLOR2__VI = 0x406D; -constexpr unsigned int mmDCP3_CUR_CONTROL__VI = 0x4066; -constexpr unsigned int mmDCP3_CUR_HOT_SPOT__VI = 0x406B; -constexpr unsigned int mmDCP3_CUR_POSITION__VI = 0x406A; -constexpr unsigned int mmDCP3_CUR_REQUEST_FILTER_CNTL__VI = 0x4099; -constexpr unsigned int mmDCP3_CUR_SIZE__VI = 0x4068; -constexpr unsigned int mmDCP3_CUR_STEREO_CONTROL__VI = 0x409A; -constexpr unsigned int mmDCP3_CUR_SURFACE_ADDRESS__VI = 0x4067; -constexpr unsigned int mmDCP3_CUR_SURFACE_ADDRESS_HIGH__VI = 0x4069; -constexpr unsigned int mmDCP3_CUR_UPDATE__VI = 0x406E; -constexpr unsigned int mmDCP3_DCP_CRC_CONTROL__VI = 0x4087; -constexpr unsigned int mmDCP3_DCP_CRC_CURRENT__VI = 0x4089; -constexpr unsigned int mmDCP3_DCP_CRC_LAST__VI = 0x408B; -constexpr unsigned int mmDCP3_DCP_CRC_MASK__VI = 0x4088; -constexpr unsigned int mmDCP3_DCP_DEBUG__VI = 0x408D; -constexpr unsigned int mmDCP3_DCP_DEBUG2__VI = 0x4098; -constexpr unsigned int mmDCP3_DCP_FP_CONVERTED_FIELD__VI = 0x4065; -constexpr unsigned int mmDCP3_DCP_GSL_CONTROL__VI = 0x4090; -constexpr unsigned int mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK__VI = 0x4091; -constexpr unsigned int mmDCP3_DCP_RANDOM_SEEDS__VI = 0x4061; -constexpr unsigned int mmDCP3_DCP_SPATIAL_DITHER_CNTL__VI = 0x4060; -constexpr unsigned int mmDCP3_DCP_TEST_DEBUG_DATA__VI = 0x4096; -constexpr unsigned int mmDCP3_DCP_TEST_DEBUG_INDEX__VI = 0x4095; -constexpr unsigned int mmDCP3_DC_LUT_30_COLOR__VI = 0x407C; -constexpr unsigned int mmDCP3_DC_LUT_AUTOFILL__VI = 0x407F; -constexpr unsigned int mmDCP3_DC_LUT_BLACK_OFFSET_BLUE__VI = 0x4081; -constexpr unsigned int mmDCP3_DC_LUT_BLACK_OFFSET_GREEN__VI = 0x4082; -constexpr unsigned int mmDCP3_DC_LUT_BLACK_OFFSET_RED__VI = 0x4083; -constexpr unsigned int mmDCP3_DC_LUT_CONTROL__VI = 0x4080; -constexpr unsigned int mmDCP3_DC_LUT_PWL_DATA__VI = 0x407B; -constexpr unsigned int mmDCP3_DC_LUT_RW_INDEX__VI = 0x4079; -constexpr unsigned int mmDCP3_DC_LUT_RW_MODE__VI = 0x4078; -constexpr unsigned int mmDCP3_DC_LUT_SEQ_COLOR__VI = 0x407A; -constexpr unsigned int mmDCP3_DC_LUT_VGA_ACCESS_ENABLE__VI = 0x407D; -constexpr unsigned int mmDCP3_DC_LUT_WHITE_OFFSET_BLUE__VI = 0x4084; -constexpr unsigned int mmDCP3_DC_LUT_WHITE_OFFSET_GREEN__VI = 0x4085; -constexpr unsigned int mmDCP3_DC_LUT_WHITE_OFFSET_RED__VI = 0x4086; -constexpr unsigned int mmDCP3_DC_LUT_WRITE_EN_MASK__VI = 0x407E; -constexpr unsigned int mmDCP3_DEGAMMA_CONTROL__VI = 0x4058; -constexpr unsigned int mmDCP3_DENORM_CONTROL__VI = 0x4050; -constexpr unsigned int mmDCP3_GAMUT_REMAP_C11_C12__VI = 0x405A; -constexpr unsigned int mmDCP3_GAMUT_REMAP_C13_C14__VI = 0x405B; -constexpr unsigned int mmDCP3_GAMUT_REMAP_C21_C22__VI = 0x405C; -constexpr unsigned int mmDCP3_GAMUT_REMAP_C23_C24__VI = 0x405D; -constexpr unsigned int mmDCP3_GAMUT_REMAP_C31_C32__VI = 0x405E; -constexpr unsigned int mmDCP3_GAMUT_REMAP_C33_C34__VI = 0x405F; -constexpr unsigned int mmDCP3_GAMUT_REMAP_CONTROL__VI = 0x4059; -constexpr unsigned int mmDCP3_GRPH_COMPRESS_PITCH__VI = 0x401A; -constexpr unsigned int mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS__VI = 0x4019; -constexpr unsigned int mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__VI = 0x401B; -constexpr unsigned int mmDCP3_GRPH_CONTROL__SI__CI = 0x4301; -constexpr unsigned int mmDCP3_GRPH_CONTROL__VI = 0x4001; -constexpr unsigned int mmDCP3_GRPH_DFQ_CONTROL__VI = 0x4014; -constexpr unsigned int mmDCP3_GRPH_DFQ_STATUS__VI = 0x4015; -constexpr unsigned int mmDCP3_GRPH_ENABLE__VI = 0x4000; -constexpr unsigned int mmDCP3_GRPH_FLIP_CONTROL__SI__CI = 0x4312; -constexpr unsigned int mmDCP3_GRPH_FLIP_CONTROL__VI = 0x4012; -constexpr unsigned int mmDCP3_GRPH_FLIP_RATE_CNTL__VI = 0x408E; -constexpr unsigned int mmDCP3_GRPH_INTERRUPT_CONTROL__VI = 0x4017; -constexpr unsigned int mmDCP3_GRPH_INTERRUPT_STATUS__VI = 0x4016; -constexpr unsigned int mmDCP3_GRPH_LUT_10BIT_BYPASS__VI = 0x4002; -constexpr unsigned int mmDCP3_GRPH_PITCH__SI__CI = 0x4306; -constexpr unsigned int mmDCP3_GRPH_PITCH__VI = 0x4006; -constexpr unsigned int mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS__SI__CI = 0x4304; -constexpr unsigned int mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS__VI = 0x4004; -constexpr unsigned int mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI = 0x4007; -constexpr unsigned int mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS__VI = 0x4005; -constexpr unsigned int mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x4008; -constexpr unsigned int mmDCP3_GRPH_STEREOSYNC_FLIP__VI = 0x4097; -constexpr unsigned int mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE__VI = 0x4018; -constexpr unsigned int mmDCP3_GRPH_SURFACE_ADDRESS_INUSE__VI = 0x4013; -constexpr unsigned int mmDCP3_GRPH_SURFACE_OFFSET_X__VI = 0x4009; -constexpr unsigned int mmDCP3_GRPH_SURFACE_OFFSET_Y__VI = 0x400A; -constexpr unsigned int mmDCP3_GRPH_SWAP_CNTL__VI = 0x4003; -constexpr unsigned int mmDCP3_GRPH_UPDATE__SI__CI = 0x4311; -constexpr unsigned int mmDCP3_GRPH_UPDATE__VI = 0x4011; -constexpr unsigned int mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI = 0x409F; -constexpr unsigned int mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI = 0x40BF; -constexpr unsigned int mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI = 0x40BD; -constexpr unsigned int mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI = 0x40BE; -constexpr unsigned int mmDCP3_GRPH_X_END__VI = 0x400D; -constexpr unsigned int mmDCP3_GRPH_X_START__VI = 0x400B; -constexpr unsigned int mmDCP3_GRPH_Y_END__VI = 0x400E; -constexpr unsigned int mmDCP3_GRPH_Y_START__VI = 0x400C; -constexpr unsigned int mmDCP3_HW_ROTATION__VI = 0x409E; -constexpr unsigned int mmDCP3_INPUT_CSC_C11_C12__VI = 0x4036; -constexpr unsigned int mmDCP3_INPUT_CSC_C13_C14__VI = 0x4037; -constexpr unsigned int mmDCP3_INPUT_CSC_C21_C22__VI = 0x4038; -constexpr unsigned int mmDCP3_INPUT_CSC_C23_C24__VI = 0x4039; -constexpr unsigned int mmDCP3_INPUT_CSC_C31_C32__VI = 0x403A; -constexpr unsigned int mmDCP3_INPUT_CSC_C33_C34__VI = 0x403B; -constexpr unsigned int mmDCP3_INPUT_CSC_CONTROL__VI = 0x4035; -constexpr unsigned int mmDCP3_INPUT_GAMMA_CONTROL__VI = 0x4010; -constexpr unsigned int mmDCP3_KEY_CONTROL__VI = 0x4053; -constexpr unsigned int mmDCP3_KEY_RANGE_ALPHA__VI = 0x4054; -constexpr unsigned int mmDCP3_KEY_RANGE_BLUE__VI = 0x4057; -constexpr unsigned int mmDCP3_KEY_RANGE_GREEN__VI = 0x4056; -constexpr unsigned int mmDCP3_KEY_RANGE_RED__VI = 0x4055; -constexpr unsigned int mmDCP3_OUTPUT_CSC_C11_C12__VI = 0x403D; -constexpr unsigned int mmDCP3_OUTPUT_CSC_C13_C14__VI = 0x403E; -constexpr unsigned int mmDCP3_OUTPUT_CSC_C21_C22__VI = 0x403F; -constexpr unsigned int mmDCP3_OUTPUT_CSC_C23_C24__VI = 0x4040; -constexpr unsigned int mmDCP3_OUTPUT_CSC_C31_C32__VI = 0x4041; -constexpr unsigned int mmDCP3_OUTPUT_CSC_C33_C34__VI = 0x4042; -constexpr unsigned int mmDCP3_OUTPUT_CSC_CONTROL__VI = 0x403C; -constexpr unsigned int mmDCP3_OUT_CLAMP_CONTROL_B_CB__VI = 0x409D; -constexpr unsigned int mmDCP3_OUT_CLAMP_CONTROL_G_Y__VI = 0x409C; -constexpr unsigned int mmDCP3_OUT_CLAMP_CONTROL_R_CR__VI = 0x4052; -constexpr unsigned int mmDCP3_OUT_ROUND_CONTROL__VI = 0x4051; -constexpr unsigned int mmDCP3_OVLSCL_EDGE_PIXEL_CNTL__VI = 0x402C; -constexpr unsigned int mmDCP3_OVL_CONTROL1__VI = 0x401D; -constexpr unsigned int mmDCP3_OVL_CONTROL2__VI = 0x401E; -constexpr unsigned int mmDCP3_OVL_DFQ_CONTROL__VI = 0x4029; -constexpr unsigned int mmDCP3_OVL_DFQ_STATUS__VI = 0x402A; -constexpr unsigned int mmDCP3_OVL_ENABLE__VI = 0x401C; -constexpr unsigned int mmDCP3_OVL_END__VI = 0x4026; -constexpr unsigned int mmDCP3_OVL_PITCH__VI = 0x4021; -constexpr unsigned int mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS__VI = 0x4092; -constexpr unsigned int mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x4094; -constexpr unsigned int mmDCP3_OVL_START__VI = 0x4025; -constexpr unsigned int mmDCP3_OVL_STEREOSYNC_FLIP__VI = 0x4093; -constexpr unsigned int mmDCP3_OVL_SURFACE_ADDRESS__SI__CI = 0x4320; -constexpr unsigned int mmDCP3_OVL_SURFACE_ADDRESS__VI = 0x4020; -constexpr unsigned int mmDCP3_OVL_SURFACE_ADDRESS_HIGH__VI = 0x4022; -constexpr unsigned int mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE__VI = 0x402B; -constexpr unsigned int mmDCP3_OVL_SURFACE_ADDRESS_INUSE__VI = 0x4028; -constexpr unsigned int mmDCP3_OVL_SURFACE_OFFSET_X__VI = 0x4023; -constexpr unsigned int mmDCP3_OVL_SURFACE_OFFSET_Y__VI = 0x4024; -constexpr unsigned int mmDCP3_OVL_SWAP_CNTL__VI = 0x401F; -constexpr unsigned int mmDCP3_OVL_UPDATE__VI = 0x4027; -constexpr unsigned int mmDCP3_PRESCALE_GRPH_CONTROL__VI = 0x402D; -constexpr unsigned int mmDCP3_PRESCALE_OVL_CONTROL__VI = 0x4031; -constexpr unsigned int mmDCP3_PRESCALE_VALUES_GRPH_B__VI = 0x4030; -constexpr unsigned int mmDCP3_PRESCALE_VALUES_GRPH_G__VI = 0x402F; -constexpr unsigned int mmDCP3_PRESCALE_VALUES_GRPH_R__VI = 0x402E; -constexpr unsigned int mmDCP3_PRESCALE_VALUES_OVL_CB__VI = 0x4032; -constexpr unsigned int mmDCP3_PRESCALE_VALUES_OVL_CR__VI = 0x4034; -constexpr unsigned int mmDCP3_PRESCALE_VALUES_OVL_Y__VI = 0x4033; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_END_CNTL1__VI = 0x40A6; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_END_CNTL2__VI = 0x40A7; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_REGION_0_1__VI = 0x40A8; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_REGION_10_11__VI = 0x40AD; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_REGION_12_13__VI = 0x40AE; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_REGION_14_15__VI = 0x40AF; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_REGION_2_3__VI = 0x40A9; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_REGION_4_5__VI = 0x40AA; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_REGION_6_7__VI = 0x40AB; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_REGION_8_9__VI = 0x40AC; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL__VI = 0x40A5; -constexpr unsigned int mmDCP3_REGAMMA_CNTLA_START_CNTL__VI = 0x40A4; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_END_CNTL1__VI = 0x40B2; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_END_CNTL2__VI = 0x40B3; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_REGION_0_1__VI = 0x40B4; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_REGION_10_11__VI = 0x40B9; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_REGION_12_13__VI = 0x40BA; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_REGION_14_15__VI = 0x40BB; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_REGION_2_3__VI = 0x40B5; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_REGION_4_5__VI = 0x40B6; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_REGION_6_7__VI = 0x40B7; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_REGION_8_9__VI = 0x40B8; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL__VI = 0x40B1; -constexpr unsigned int mmDCP3_REGAMMA_CNTLB_START_CNTL__VI = 0x40B0; -constexpr unsigned int mmDCP3_REGAMMA_CONTROL__VI = 0x40A0; -constexpr unsigned int mmDCP3_REGAMMA_LUT_DATA__VI = 0x40A2; -constexpr unsigned int mmDCP3_REGAMMA_LUT_INDEX__VI = 0x40A1; -constexpr unsigned int mmDCP3_REGAMMA_LUT_WRITE_EN_MASK__VI = 0x40A3; -constexpr unsigned int mmDCP4_ALPHA_CONTROL__VI = 0x42BC; -constexpr unsigned int mmDCP4_COMM_MATRIXA_TRANS_C11_C12__VI = 0x4243; -constexpr unsigned int mmDCP4_COMM_MATRIXA_TRANS_C13_C14__VI = 0x4244; -constexpr unsigned int mmDCP4_COMM_MATRIXA_TRANS_C21_C22__VI = 0x4245; -constexpr unsigned int mmDCP4_COMM_MATRIXA_TRANS_C23_C24__VI = 0x4246; -constexpr unsigned int mmDCP4_COMM_MATRIXA_TRANS_C31_C32__VI = 0x4247; -constexpr unsigned int mmDCP4_COMM_MATRIXA_TRANS_C33_C34__VI = 0x4248; -constexpr unsigned int mmDCP4_COMM_MATRIXB_TRANS_C11_C12__VI = 0x4249; -constexpr unsigned int mmDCP4_COMM_MATRIXB_TRANS_C13_C14__VI = 0x424A; -constexpr unsigned int mmDCP4_COMM_MATRIXB_TRANS_C21_C22__VI = 0x424B; -constexpr unsigned int mmDCP4_COMM_MATRIXB_TRANS_C23_C24__VI = 0x424C; -constexpr unsigned int mmDCP4_COMM_MATRIXB_TRANS_C31_C32__VI = 0x424D; -constexpr unsigned int mmDCP4_COMM_MATRIXB_TRANS_C33_C34__VI = 0x424E; -constexpr unsigned int mmDCP4_CUR2_COLOR1__VI = 0x4275; -constexpr unsigned int mmDCP4_CUR2_COLOR2__VI = 0x4276; -constexpr unsigned int mmDCP4_CUR2_CONTROL__VI = 0x426F; -constexpr unsigned int mmDCP4_CUR2_HOT_SPOT__VI = 0x4274; -constexpr unsigned int mmDCP4_CUR2_POSITION__VI = 0x4273; -constexpr unsigned int mmDCP4_CUR2_SIZE__VI = 0x4271; -constexpr unsigned int mmDCP4_CUR2_STEREO_CONTROL__VI = 0x429B; -constexpr unsigned int mmDCP4_CUR2_SURFACE_ADDRESS__VI = 0x4270; -constexpr unsigned int mmDCP4_CUR2_SURFACE_ADDRESS_HIGH__VI = 0x4272; -constexpr unsigned int mmDCP4_CUR2_UPDATE__VI = 0x4277; -constexpr unsigned int mmDCP4_CUR_COLOR1__VI = 0x426C; -constexpr unsigned int mmDCP4_CUR_COLOR2__VI = 0x426D; -constexpr unsigned int mmDCP4_CUR_CONTROL__VI = 0x4266; -constexpr unsigned int mmDCP4_CUR_HOT_SPOT__VI = 0x426B; -constexpr unsigned int mmDCP4_CUR_POSITION__VI = 0x426A; -constexpr unsigned int mmDCP4_CUR_REQUEST_FILTER_CNTL__VI = 0x4299; -constexpr unsigned int mmDCP4_CUR_SIZE__VI = 0x4268; -constexpr unsigned int mmDCP4_CUR_STEREO_CONTROL__VI = 0x429A; -constexpr unsigned int mmDCP4_CUR_SURFACE_ADDRESS__VI = 0x4267; -constexpr unsigned int mmDCP4_CUR_SURFACE_ADDRESS_HIGH__VI = 0x4269; -constexpr unsigned int mmDCP4_CUR_UPDATE__VI = 0x426E; -constexpr unsigned int mmDCP4_DCP_CRC_CONTROL__VI = 0x4287; -constexpr unsigned int mmDCP4_DCP_CRC_CURRENT__VI = 0x4289; -constexpr unsigned int mmDCP4_DCP_CRC_LAST__VI = 0x428B; -constexpr unsigned int mmDCP4_DCP_CRC_MASK__VI = 0x4288; -constexpr unsigned int mmDCP4_DCP_DEBUG__VI = 0x428D; -constexpr unsigned int mmDCP4_DCP_DEBUG2__VI = 0x4298; -constexpr unsigned int mmDCP4_DCP_FP_CONVERTED_FIELD__VI = 0x4265; -constexpr unsigned int mmDCP4_DCP_GSL_CONTROL__VI = 0x4290; -constexpr unsigned int mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK__VI = 0x4291; -constexpr unsigned int mmDCP4_DCP_RANDOM_SEEDS__VI = 0x4261; -constexpr unsigned int mmDCP4_DCP_SPATIAL_DITHER_CNTL__VI = 0x4260; -constexpr unsigned int mmDCP4_DCP_TEST_DEBUG_DATA__VI = 0x4296; -constexpr unsigned int mmDCP4_DCP_TEST_DEBUG_INDEX__VI = 0x4295; -constexpr unsigned int mmDCP4_DC_LUT_30_COLOR__VI = 0x427C; -constexpr unsigned int mmDCP4_DC_LUT_AUTOFILL__VI = 0x427F; -constexpr unsigned int mmDCP4_DC_LUT_BLACK_OFFSET_BLUE__VI = 0x4281; -constexpr unsigned int mmDCP4_DC_LUT_BLACK_OFFSET_GREEN__VI = 0x4282; -constexpr unsigned int mmDCP4_DC_LUT_BLACK_OFFSET_RED__VI = 0x4283; -constexpr unsigned int mmDCP4_DC_LUT_CONTROL__VI = 0x4280; -constexpr unsigned int mmDCP4_DC_LUT_PWL_DATA__VI = 0x427B; -constexpr unsigned int mmDCP4_DC_LUT_RW_INDEX__VI = 0x4279; -constexpr unsigned int mmDCP4_DC_LUT_RW_MODE__VI = 0x4278; -constexpr unsigned int mmDCP4_DC_LUT_SEQ_COLOR__VI = 0x427A; -constexpr unsigned int mmDCP4_DC_LUT_VGA_ACCESS_ENABLE__VI = 0x427D; -constexpr unsigned int mmDCP4_DC_LUT_WHITE_OFFSET_BLUE__VI = 0x4284; -constexpr unsigned int mmDCP4_DC_LUT_WHITE_OFFSET_GREEN__VI = 0x4285; -constexpr unsigned int mmDCP4_DC_LUT_WHITE_OFFSET_RED__VI = 0x4286; -constexpr unsigned int mmDCP4_DC_LUT_WRITE_EN_MASK__VI = 0x427E; -constexpr unsigned int mmDCP4_DEGAMMA_CONTROL__VI = 0x4258; -constexpr unsigned int mmDCP4_DENORM_CONTROL__VI = 0x4250; -constexpr unsigned int mmDCP4_GAMUT_REMAP_C11_C12__VI = 0x425A; -constexpr unsigned int mmDCP4_GAMUT_REMAP_C13_C14__VI = 0x425B; -constexpr unsigned int mmDCP4_GAMUT_REMAP_C21_C22__VI = 0x425C; -constexpr unsigned int mmDCP4_GAMUT_REMAP_C23_C24__VI = 0x425D; -constexpr unsigned int mmDCP4_GAMUT_REMAP_C31_C32__VI = 0x425E; -constexpr unsigned int mmDCP4_GAMUT_REMAP_C33_C34__VI = 0x425F; -constexpr unsigned int mmDCP4_GAMUT_REMAP_CONTROL__VI = 0x4259; -constexpr unsigned int mmDCP4_GRPH_COMPRESS_PITCH__VI = 0x421A; -constexpr unsigned int mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS__VI = 0x4219; -constexpr unsigned int mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__VI = 0x421B; -constexpr unsigned int mmDCP4_GRPH_CONTROL__SI__CI = 0x4601; -constexpr unsigned int mmDCP4_GRPH_CONTROL__VI = 0x4201; -constexpr unsigned int mmDCP4_GRPH_DFQ_CONTROL__VI = 0x4214; -constexpr unsigned int mmDCP4_GRPH_DFQ_STATUS__VI = 0x4215; -constexpr unsigned int mmDCP4_GRPH_ENABLE__VI = 0x4200; -constexpr unsigned int mmDCP4_GRPH_FLIP_CONTROL__SI__CI = 0x4612; -constexpr unsigned int mmDCP4_GRPH_FLIP_CONTROL__VI = 0x4212; -constexpr unsigned int mmDCP4_GRPH_FLIP_RATE_CNTL__VI = 0x428E; -constexpr unsigned int mmDCP4_GRPH_INTERRUPT_CONTROL__VI = 0x4217; -constexpr unsigned int mmDCP4_GRPH_INTERRUPT_STATUS__VI = 0x4216; -constexpr unsigned int mmDCP4_GRPH_LUT_10BIT_BYPASS__VI = 0x4202; -constexpr unsigned int mmDCP4_GRPH_PITCH__SI__CI = 0x4606; -constexpr unsigned int mmDCP4_GRPH_PITCH__VI = 0x4206; -constexpr unsigned int mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS__SI__CI = 0x4604; -constexpr unsigned int mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS__VI = 0x4204; -constexpr unsigned int mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI = 0x4207; -constexpr unsigned int mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS__VI = 0x4205; -constexpr unsigned int mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x4208; -constexpr unsigned int mmDCP4_GRPH_STEREOSYNC_FLIP__VI = 0x4297; -constexpr unsigned int mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE__VI = 0x4218; -constexpr unsigned int mmDCP4_GRPH_SURFACE_ADDRESS_INUSE__VI = 0x4213; -constexpr unsigned int mmDCP4_GRPH_SURFACE_OFFSET_X__VI = 0x4209; -constexpr unsigned int mmDCP4_GRPH_SURFACE_OFFSET_Y__VI = 0x420A; -constexpr unsigned int mmDCP4_GRPH_SWAP_CNTL__VI = 0x4203; -constexpr unsigned int mmDCP4_GRPH_UPDATE__SI__CI = 0x4611; -constexpr unsigned int mmDCP4_GRPH_UPDATE__VI = 0x4211; -constexpr unsigned int mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI = 0x429F; -constexpr unsigned int mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI = 0x42BF; -constexpr unsigned int mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI = 0x42BD; -constexpr unsigned int mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI = 0x42BE; -constexpr unsigned int mmDCP4_GRPH_X_END__VI = 0x420D; -constexpr unsigned int mmDCP4_GRPH_X_START__VI = 0x420B; -constexpr unsigned int mmDCP4_GRPH_Y_END__VI = 0x420E; -constexpr unsigned int mmDCP4_GRPH_Y_START__VI = 0x420C; -constexpr unsigned int mmDCP4_HW_ROTATION__VI = 0x429E; -constexpr unsigned int mmDCP4_INPUT_CSC_C11_C12__VI = 0x4236; -constexpr unsigned int mmDCP4_INPUT_CSC_C13_C14__VI = 0x4237; -constexpr unsigned int mmDCP4_INPUT_CSC_C21_C22__VI = 0x4238; -constexpr unsigned int mmDCP4_INPUT_CSC_C23_C24__VI = 0x4239; -constexpr unsigned int mmDCP4_INPUT_CSC_C31_C32__VI = 0x423A; -constexpr unsigned int mmDCP4_INPUT_CSC_C33_C34__VI = 0x423B; -constexpr unsigned int mmDCP4_INPUT_CSC_CONTROL__VI = 0x4235; -constexpr unsigned int mmDCP4_INPUT_GAMMA_CONTROL__VI = 0x4210; -constexpr unsigned int mmDCP4_KEY_CONTROL__VI = 0x4253; -constexpr unsigned int mmDCP4_KEY_RANGE_ALPHA__VI = 0x4254; -constexpr unsigned int mmDCP4_KEY_RANGE_BLUE__VI = 0x4257; -constexpr unsigned int mmDCP4_KEY_RANGE_GREEN__VI = 0x4256; -constexpr unsigned int mmDCP4_KEY_RANGE_RED__VI = 0x4255; -constexpr unsigned int mmDCP4_OUTPUT_CSC_C11_C12__VI = 0x423D; -constexpr unsigned int mmDCP4_OUTPUT_CSC_C13_C14__VI = 0x423E; -constexpr unsigned int mmDCP4_OUTPUT_CSC_C21_C22__VI = 0x423F; -constexpr unsigned int mmDCP4_OUTPUT_CSC_C23_C24__VI = 0x4240; -constexpr unsigned int mmDCP4_OUTPUT_CSC_C31_C32__VI = 0x4241; -constexpr unsigned int mmDCP4_OUTPUT_CSC_C33_C34__VI = 0x4242; -constexpr unsigned int mmDCP4_OUTPUT_CSC_CONTROL__VI = 0x423C; -constexpr unsigned int mmDCP4_OUT_CLAMP_CONTROL_B_CB__VI = 0x429D; -constexpr unsigned int mmDCP4_OUT_CLAMP_CONTROL_G_Y__VI = 0x429C; -constexpr unsigned int mmDCP4_OUT_CLAMP_CONTROL_R_CR__VI = 0x4252; -constexpr unsigned int mmDCP4_OUT_ROUND_CONTROL__VI = 0x4251; -constexpr unsigned int mmDCP4_OVLSCL_EDGE_PIXEL_CNTL__VI = 0x422C; -constexpr unsigned int mmDCP4_OVL_CONTROL1__VI = 0x421D; -constexpr unsigned int mmDCP4_OVL_CONTROL2__VI = 0x421E; -constexpr unsigned int mmDCP4_OVL_DFQ_CONTROL__VI = 0x4229; -constexpr unsigned int mmDCP4_OVL_DFQ_STATUS__VI = 0x422A; -constexpr unsigned int mmDCP4_OVL_ENABLE__VI = 0x421C; -constexpr unsigned int mmDCP4_OVL_END__VI = 0x4226; -constexpr unsigned int mmDCP4_OVL_PITCH__VI = 0x4221; -constexpr unsigned int mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS__VI = 0x4292; -constexpr unsigned int mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x4294; -constexpr unsigned int mmDCP4_OVL_START__VI = 0x4225; -constexpr unsigned int mmDCP4_OVL_STEREOSYNC_FLIP__VI = 0x4293; -constexpr unsigned int mmDCP4_OVL_SURFACE_ADDRESS__SI__CI = 0x4620; -constexpr unsigned int mmDCP4_OVL_SURFACE_ADDRESS__VI = 0x4220; -constexpr unsigned int mmDCP4_OVL_SURFACE_ADDRESS_HIGH__VI = 0x4222; -constexpr unsigned int mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE__VI = 0x422B; -constexpr unsigned int mmDCP4_OVL_SURFACE_ADDRESS_INUSE__VI = 0x4228; -constexpr unsigned int mmDCP4_OVL_SURFACE_OFFSET_X__VI = 0x4223; -constexpr unsigned int mmDCP4_OVL_SURFACE_OFFSET_Y__VI = 0x4224; -constexpr unsigned int mmDCP4_OVL_SWAP_CNTL__VI = 0x421F; -constexpr unsigned int mmDCP4_OVL_UPDATE__VI = 0x4227; -constexpr unsigned int mmDCP4_PRESCALE_GRPH_CONTROL__VI = 0x422D; -constexpr unsigned int mmDCP4_PRESCALE_OVL_CONTROL__VI = 0x4231; -constexpr unsigned int mmDCP4_PRESCALE_VALUES_GRPH_B__VI = 0x4230; -constexpr unsigned int mmDCP4_PRESCALE_VALUES_GRPH_G__VI = 0x422F; -constexpr unsigned int mmDCP4_PRESCALE_VALUES_GRPH_R__VI = 0x422E; -constexpr unsigned int mmDCP4_PRESCALE_VALUES_OVL_CB__VI = 0x4232; -constexpr unsigned int mmDCP4_PRESCALE_VALUES_OVL_CR__VI = 0x4234; -constexpr unsigned int mmDCP4_PRESCALE_VALUES_OVL_Y__VI = 0x4233; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_END_CNTL1__VI = 0x42A6; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_END_CNTL2__VI = 0x42A7; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_REGION_0_1__VI = 0x42A8; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_REGION_10_11__VI = 0x42AD; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_REGION_12_13__VI = 0x42AE; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_REGION_14_15__VI = 0x42AF; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_REGION_2_3__VI = 0x42A9; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_REGION_4_5__VI = 0x42AA; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_REGION_6_7__VI = 0x42AB; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_REGION_8_9__VI = 0x42AC; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL__VI = 0x42A5; -constexpr unsigned int mmDCP4_REGAMMA_CNTLA_START_CNTL__VI = 0x42A4; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_END_CNTL1__VI = 0x42B2; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_END_CNTL2__VI = 0x42B3; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_REGION_0_1__VI = 0x42B4; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_REGION_10_11__VI = 0x42B9; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_REGION_12_13__VI = 0x42BA; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_REGION_14_15__VI = 0x42BB; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_REGION_2_3__VI = 0x42B5; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_REGION_4_5__VI = 0x42B6; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_REGION_6_7__VI = 0x42B7; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_REGION_8_9__VI = 0x42B8; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL__VI = 0x42B1; -constexpr unsigned int mmDCP4_REGAMMA_CNTLB_START_CNTL__VI = 0x42B0; -constexpr unsigned int mmDCP4_REGAMMA_CONTROL__VI = 0x42A0; -constexpr unsigned int mmDCP4_REGAMMA_LUT_DATA__VI = 0x42A2; -constexpr unsigned int mmDCP4_REGAMMA_LUT_INDEX__VI = 0x42A1; -constexpr unsigned int mmDCP4_REGAMMA_LUT_WRITE_EN_MASK__VI = 0x42A3; -constexpr unsigned int mmDCP5_ALPHA_CONTROL__VI = 0x44BC; -constexpr unsigned int mmDCP5_COMM_MATRIXA_TRANS_C11_C12__VI = 0x4443; -constexpr unsigned int mmDCP5_COMM_MATRIXA_TRANS_C13_C14__VI = 0x4444; -constexpr unsigned int mmDCP5_COMM_MATRIXA_TRANS_C21_C22__VI = 0x4445; -constexpr unsigned int mmDCP5_COMM_MATRIXA_TRANS_C23_C24__VI = 0x4446; -constexpr unsigned int mmDCP5_COMM_MATRIXA_TRANS_C31_C32__VI = 0x4447; -constexpr unsigned int mmDCP5_COMM_MATRIXA_TRANS_C33_C34__VI = 0x4448; -constexpr unsigned int mmDCP5_COMM_MATRIXB_TRANS_C11_C12__VI = 0x4449; -constexpr unsigned int mmDCP5_COMM_MATRIXB_TRANS_C13_C14__VI = 0x444A; -constexpr unsigned int mmDCP5_COMM_MATRIXB_TRANS_C21_C22__VI = 0x444B; -constexpr unsigned int mmDCP5_COMM_MATRIXB_TRANS_C23_C24__VI = 0x444C; -constexpr unsigned int mmDCP5_COMM_MATRIXB_TRANS_C31_C32__VI = 0x444D; -constexpr unsigned int mmDCP5_COMM_MATRIXB_TRANS_C33_C34__VI = 0x444E; -constexpr unsigned int mmDCP5_CUR2_COLOR1__VI = 0x4475; -constexpr unsigned int mmDCP5_CUR2_COLOR2__VI = 0x4476; -constexpr unsigned int mmDCP5_CUR2_CONTROL__VI = 0x446F; -constexpr unsigned int mmDCP5_CUR2_HOT_SPOT__VI = 0x4474; -constexpr unsigned int mmDCP5_CUR2_POSITION__VI = 0x4473; -constexpr unsigned int mmDCP5_CUR2_SIZE__VI = 0x4471; -constexpr unsigned int mmDCP5_CUR2_STEREO_CONTROL__VI = 0x449B; -constexpr unsigned int mmDCP5_CUR2_SURFACE_ADDRESS__VI = 0x4470; -constexpr unsigned int mmDCP5_CUR2_SURFACE_ADDRESS_HIGH__VI = 0x4472; -constexpr unsigned int mmDCP5_CUR2_UPDATE__VI = 0x4477; -constexpr unsigned int mmDCP5_CUR_COLOR1__VI = 0x446C; -constexpr unsigned int mmDCP5_CUR_COLOR2__VI = 0x446D; -constexpr unsigned int mmDCP5_CUR_CONTROL__VI = 0x4466; -constexpr unsigned int mmDCP5_CUR_HOT_SPOT__VI = 0x446B; -constexpr unsigned int mmDCP5_CUR_POSITION__VI = 0x446A; -constexpr unsigned int mmDCP5_CUR_REQUEST_FILTER_CNTL__VI = 0x4499; -constexpr unsigned int mmDCP5_CUR_SIZE__VI = 0x4468; -constexpr unsigned int mmDCP5_CUR_STEREO_CONTROL__VI = 0x449A; -constexpr unsigned int mmDCP5_CUR_SURFACE_ADDRESS__VI = 0x4467; -constexpr unsigned int mmDCP5_CUR_SURFACE_ADDRESS_HIGH__VI = 0x4469; -constexpr unsigned int mmDCP5_CUR_UPDATE__VI = 0x446E; -constexpr unsigned int mmDCP5_DCP_CRC_CONTROL__VI = 0x4487; -constexpr unsigned int mmDCP5_DCP_CRC_CURRENT__VI = 0x4489; -constexpr unsigned int mmDCP5_DCP_CRC_LAST__VI = 0x448B; -constexpr unsigned int mmDCP5_DCP_CRC_MASK__VI = 0x4488; -constexpr unsigned int mmDCP5_DCP_DEBUG__VI = 0x448D; -constexpr unsigned int mmDCP5_DCP_DEBUG2__VI = 0x4498; -constexpr unsigned int mmDCP5_DCP_FP_CONVERTED_FIELD__VI = 0x4465; -constexpr unsigned int mmDCP5_DCP_GSL_CONTROL__VI = 0x4490; -constexpr unsigned int mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK__VI = 0x4491; -constexpr unsigned int mmDCP5_DCP_RANDOM_SEEDS__VI = 0x4461; -constexpr unsigned int mmDCP5_DCP_SPATIAL_DITHER_CNTL__VI = 0x4460; -constexpr unsigned int mmDCP5_DCP_TEST_DEBUG_DATA__VI = 0x4496; -constexpr unsigned int mmDCP5_DCP_TEST_DEBUG_INDEX__VI = 0x4495; -constexpr unsigned int mmDCP5_DC_LUT_30_COLOR__VI = 0x447C; -constexpr unsigned int mmDCP5_DC_LUT_AUTOFILL__VI = 0x447F; -constexpr unsigned int mmDCP5_DC_LUT_BLACK_OFFSET_BLUE__VI = 0x4481; -constexpr unsigned int mmDCP5_DC_LUT_BLACK_OFFSET_GREEN__VI = 0x4482; -constexpr unsigned int mmDCP5_DC_LUT_BLACK_OFFSET_RED__VI = 0x4483; -constexpr unsigned int mmDCP5_DC_LUT_CONTROL__VI = 0x4480; -constexpr unsigned int mmDCP5_DC_LUT_PWL_DATA__VI = 0x447B; -constexpr unsigned int mmDCP5_DC_LUT_RW_INDEX__VI = 0x4479; -constexpr unsigned int mmDCP5_DC_LUT_RW_MODE__VI = 0x4478; -constexpr unsigned int mmDCP5_DC_LUT_SEQ_COLOR__VI = 0x447A; -constexpr unsigned int mmDCP5_DC_LUT_VGA_ACCESS_ENABLE__VI = 0x447D; -constexpr unsigned int mmDCP5_DC_LUT_WHITE_OFFSET_BLUE__VI = 0x4484; -constexpr unsigned int mmDCP5_DC_LUT_WHITE_OFFSET_GREEN__VI = 0x4485; -constexpr unsigned int mmDCP5_DC_LUT_WHITE_OFFSET_RED__VI = 0x4486; -constexpr unsigned int mmDCP5_DC_LUT_WRITE_EN_MASK__VI = 0x447E; -constexpr unsigned int mmDCP5_DEGAMMA_CONTROL__VI = 0x4458; -constexpr unsigned int mmDCP5_DENORM_CONTROL__VI = 0x4450; -constexpr unsigned int mmDCP5_GAMUT_REMAP_C11_C12__VI = 0x445A; -constexpr unsigned int mmDCP5_GAMUT_REMAP_C13_C14__VI = 0x445B; -constexpr unsigned int mmDCP5_GAMUT_REMAP_C21_C22__VI = 0x445C; -constexpr unsigned int mmDCP5_GAMUT_REMAP_C23_C24__VI = 0x445D; -constexpr unsigned int mmDCP5_GAMUT_REMAP_C31_C32__VI = 0x445E; -constexpr unsigned int mmDCP5_GAMUT_REMAP_C33_C34__VI = 0x445F; -constexpr unsigned int mmDCP5_GAMUT_REMAP_CONTROL__VI = 0x4459; -constexpr unsigned int mmDCP5_GRPH_COMPRESS_PITCH__VI = 0x441A; -constexpr unsigned int mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS__VI = 0x4419; -constexpr unsigned int mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__VI = 0x441B; -constexpr unsigned int mmDCP5_GRPH_CONTROL__SI__CI = 0x4901; -constexpr unsigned int mmDCP5_GRPH_CONTROL__VI = 0x4401; -constexpr unsigned int mmDCP5_GRPH_DFQ_CONTROL__VI = 0x4414; -constexpr unsigned int mmDCP5_GRPH_DFQ_STATUS__VI = 0x4415; -constexpr unsigned int mmDCP5_GRPH_ENABLE__VI = 0x4400; -constexpr unsigned int mmDCP5_GRPH_FLIP_CONTROL__SI__CI = 0x4912; -constexpr unsigned int mmDCP5_GRPH_FLIP_CONTROL__VI = 0x4412; -constexpr unsigned int mmDCP5_GRPH_FLIP_RATE_CNTL__VI = 0x448E; -constexpr unsigned int mmDCP5_GRPH_INTERRUPT_CONTROL__VI = 0x4417; -constexpr unsigned int mmDCP5_GRPH_INTERRUPT_STATUS__VI = 0x4416; -constexpr unsigned int mmDCP5_GRPH_LUT_10BIT_BYPASS__VI = 0x4402; -constexpr unsigned int mmDCP5_GRPH_PITCH__SI__CI = 0x4906; -constexpr unsigned int mmDCP5_GRPH_PITCH__VI = 0x4406; -constexpr unsigned int mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS__SI__CI = 0x4904; -constexpr unsigned int mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS__VI = 0x4404; -constexpr unsigned int mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__VI = 0x4407; -constexpr unsigned int mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS__VI = 0x4405; -constexpr unsigned int mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x4408; -constexpr unsigned int mmDCP5_GRPH_STEREOSYNC_FLIP__VI = 0x4497; -constexpr unsigned int mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE__VI = 0x4418; -constexpr unsigned int mmDCP5_GRPH_SURFACE_ADDRESS_INUSE__VI = 0x4413; -constexpr unsigned int mmDCP5_GRPH_SURFACE_OFFSET_X__VI = 0x4409; -constexpr unsigned int mmDCP5_GRPH_SURFACE_OFFSET_Y__VI = 0x440A; -constexpr unsigned int mmDCP5_GRPH_SWAP_CNTL__VI = 0x4403; -constexpr unsigned int mmDCP5_GRPH_UPDATE__SI__CI = 0x4911; -constexpr unsigned int mmDCP5_GRPH_UPDATE__VI = 0x4411; -constexpr unsigned int mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI = 0x449F; -constexpr unsigned int mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI = 0x44BF; -constexpr unsigned int mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI = 0x44BD; -constexpr unsigned int mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI = 0x44BE; -constexpr unsigned int mmDCP5_GRPH_X_END__VI = 0x440D; -constexpr unsigned int mmDCP5_GRPH_X_START__VI = 0x440B; -constexpr unsigned int mmDCP5_GRPH_Y_END__VI = 0x440E; -constexpr unsigned int mmDCP5_GRPH_Y_START__VI = 0x440C; -constexpr unsigned int mmDCP5_HW_ROTATION__VI = 0x449E; -constexpr unsigned int mmDCP5_INPUT_CSC_C11_C12__VI = 0x4436; -constexpr unsigned int mmDCP5_INPUT_CSC_C13_C14__VI = 0x4437; -constexpr unsigned int mmDCP5_INPUT_CSC_C21_C22__VI = 0x4438; -constexpr unsigned int mmDCP5_INPUT_CSC_C23_C24__VI = 0x4439; -constexpr unsigned int mmDCP5_INPUT_CSC_C31_C32__VI = 0x443A; -constexpr unsigned int mmDCP5_INPUT_CSC_C33_C34__VI = 0x443B; -constexpr unsigned int mmDCP5_INPUT_CSC_CONTROL__VI = 0x4435; -constexpr unsigned int mmDCP5_INPUT_GAMMA_CONTROL__VI = 0x4410; -constexpr unsigned int mmDCP5_KEY_CONTROL__VI = 0x4453; -constexpr unsigned int mmDCP5_KEY_RANGE_ALPHA__VI = 0x4454; -constexpr unsigned int mmDCP5_KEY_RANGE_BLUE__VI = 0x4457; -constexpr unsigned int mmDCP5_KEY_RANGE_GREEN__VI = 0x4456; -constexpr unsigned int mmDCP5_KEY_RANGE_RED__VI = 0x4455; -constexpr unsigned int mmDCP5_OUTPUT_CSC_C11_C12__VI = 0x443D; -constexpr unsigned int mmDCP5_OUTPUT_CSC_C13_C14__VI = 0x443E; -constexpr unsigned int mmDCP5_OUTPUT_CSC_C21_C22__VI = 0x443F; -constexpr unsigned int mmDCP5_OUTPUT_CSC_C23_C24__VI = 0x4440; -constexpr unsigned int mmDCP5_OUTPUT_CSC_C31_C32__VI = 0x4441; -constexpr unsigned int mmDCP5_OUTPUT_CSC_C33_C34__VI = 0x4442; -constexpr unsigned int mmDCP5_OUTPUT_CSC_CONTROL__VI = 0x443C; -constexpr unsigned int mmDCP5_OUT_CLAMP_CONTROL_B_CB__VI = 0x449D; -constexpr unsigned int mmDCP5_OUT_CLAMP_CONTROL_G_Y__VI = 0x449C; -constexpr unsigned int mmDCP5_OUT_CLAMP_CONTROL_R_CR__VI = 0x4452; -constexpr unsigned int mmDCP5_OUT_ROUND_CONTROL__VI = 0x4451; -constexpr unsigned int mmDCP5_OVLSCL_EDGE_PIXEL_CNTL__VI = 0x442C; -constexpr unsigned int mmDCP5_OVL_CONTROL1__VI = 0x441D; -constexpr unsigned int mmDCP5_OVL_CONTROL2__VI = 0x441E; -constexpr unsigned int mmDCP5_OVL_DFQ_CONTROL__VI = 0x4429; -constexpr unsigned int mmDCP5_OVL_DFQ_STATUS__VI = 0x442A; -constexpr unsigned int mmDCP5_OVL_ENABLE__VI = 0x441C; -constexpr unsigned int mmDCP5_OVL_END__VI = 0x4426; -constexpr unsigned int mmDCP5_OVL_PITCH__VI = 0x4421; -constexpr unsigned int mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS__VI = 0x4492; -constexpr unsigned int mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x4494; -constexpr unsigned int mmDCP5_OVL_START__VI = 0x4425; -constexpr unsigned int mmDCP5_OVL_STEREOSYNC_FLIP__VI = 0x4493; -constexpr unsigned int mmDCP5_OVL_SURFACE_ADDRESS__SI__CI = 0x4920; -constexpr unsigned int mmDCP5_OVL_SURFACE_ADDRESS__VI = 0x4420; -constexpr unsigned int mmDCP5_OVL_SURFACE_ADDRESS_HIGH__VI = 0x4422; -constexpr unsigned int mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE__VI = 0x442B; -constexpr unsigned int mmDCP5_OVL_SURFACE_ADDRESS_INUSE__VI = 0x4428; -constexpr unsigned int mmDCP5_OVL_SURFACE_OFFSET_X__VI = 0x4423; -constexpr unsigned int mmDCP5_OVL_SURFACE_OFFSET_Y__VI = 0x4424; -constexpr unsigned int mmDCP5_OVL_SWAP_CNTL__VI = 0x441F; -constexpr unsigned int mmDCP5_OVL_UPDATE__VI = 0x4427; -constexpr unsigned int mmDCP5_PRESCALE_GRPH_CONTROL__VI = 0x442D; -constexpr unsigned int mmDCP5_PRESCALE_OVL_CONTROL__VI = 0x4431; -constexpr unsigned int mmDCP5_PRESCALE_VALUES_GRPH_B__VI = 0x4430; -constexpr unsigned int mmDCP5_PRESCALE_VALUES_GRPH_G__VI = 0x442F; -constexpr unsigned int mmDCP5_PRESCALE_VALUES_GRPH_R__VI = 0x442E; -constexpr unsigned int mmDCP5_PRESCALE_VALUES_OVL_CB__VI = 0x4432; -constexpr unsigned int mmDCP5_PRESCALE_VALUES_OVL_CR__VI = 0x4434; -constexpr unsigned int mmDCP5_PRESCALE_VALUES_OVL_Y__VI = 0x4433; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_END_CNTL1__VI = 0x44A6; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_END_CNTL2__VI = 0x44A7; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_REGION_0_1__VI = 0x44A8; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_REGION_10_11__VI = 0x44AD; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_REGION_12_13__VI = 0x44AE; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_REGION_14_15__VI = 0x44AF; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_REGION_2_3__VI = 0x44A9; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_REGION_4_5__VI = 0x44AA; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_REGION_6_7__VI = 0x44AB; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_REGION_8_9__VI = 0x44AC; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL__VI = 0x44A5; -constexpr unsigned int mmDCP5_REGAMMA_CNTLA_START_CNTL__VI = 0x44A4; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_END_CNTL1__VI = 0x44B2; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_END_CNTL2__VI = 0x44B3; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_REGION_0_1__VI = 0x44B4; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_REGION_10_11__VI = 0x44B9; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_REGION_12_13__VI = 0x44BA; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_REGION_14_15__VI = 0x44BB; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_REGION_2_3__VI = 0x44B5; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_REGION_4_5__VI = 0x44B6; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_REGION_6_7__VI = 0x44B7; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_REGION_8_9__VI = 0x44B8; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL__VI = 0x44B1; -constexpr unsigned int mmDCP5_REGAMMA_CNTLB_START_CNTL__VI = 0x44B0; -constexpr unsigned int mmDCP5_REGAMMA_CONTROL__VI = 0x44A0; -constexpr unsigned int mmDCP5_REGAMMA_LUT_DATA__VI = 0x44A2; -constexpr unsigned int mmDCP5_REGAMMA_LUT_INDEX__VI = 0x44A1; -constexpr unsigned int mmDCP5_REGAMMA_LUT_WRITE_EN_MASK__VI = 0x44A3; -constexpr unsigned int mmDCPG_TEST_DEBUG_DATA__VI = 0x02D7; -constexpr unsigned int mmDCPG_TEST_DEBUG_INDEX__VI = 0x02D6; -constexpr unsigned int mmDCP_DEBUG2__VI = 0x1A98; -constexpr unsigned int mmDCP_FP_CONVERTED_FIELD__VI = 0x1A65; -constexpr unsigned int mmDCP_GSL_CONTROL__VI = 0x1A90; -constexpr unsigned int mmDCP_RANDOM_SEEDS__VI = 0x1A61; -constexpr unsigned int mmDCP_SPATIAL_DITHER_CNTL__VI = 0x1A60; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED0__VI = 0x5A84; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED1__VI = 0x5A85; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED10__VI = 0x5A8E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED100__VI = 0x5AE8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED101__VI = 0x5AE9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED102__VI = 0x5AEA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED103__VI = 0x5AEB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED104__VI = 0x5AEC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED105__VI = 0x5AED; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED106__VI = 0x5AEE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED107__VI = 0x5AEF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED108__VI = 0x5AF0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED109__VI = 0x5AF1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED11__VI = 0x5A8F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED110__VI = 0x5AF2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED111__VI = 0x5AF3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED112__VI = 0x5AF4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED113__VI = 0x5AF5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED114__VI = 0x5AF6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED115__VI = 0x5AF7; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED116__VI = 0x5AF8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED117__VI = 0x5AF9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED118__VI = 0x5AFA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED119__VI = 0x5AFB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED12__VI = 0x5A90; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED120__VI = 0x5AFC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED121__VI = 0x5AFD; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED122__VI = 0x5AFE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED123__VI = 0x5AFF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED124__VI = 0x5B00; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED125__VI = 0x5B01; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED126__VI = 0x5B02; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED127__VI = 0x5B03; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED128__VI = 0x5B04; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED129__VI = 0x5B05; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED13__VI = 0x5A91; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED130__VI = 0x5B06; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED131__VI = 0x5B07; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED132__VI = 0x5B08; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED133__VI = 0x5B09; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED134__VI = 0x5B0A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED135__VI = 0x5B0B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED136__VI = 0x5B0C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED137__VI = 0x5B0D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED138__VI = 0x5B0E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED139__VI = 0x5B0F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED14__VI = 0x5A92; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED140__VI = 0x5B10; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED141__VI = 0x5B11; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED142__VI = 0x5B12; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED143__VI = 0x5B13; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED144__VI = 0x5B14; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED145__VI = 0x5B15; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED146__VI = 0x5B16; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED147__VI = 0x5B17; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED148__VI = 0x5B18; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED149__VI = 0x5B19; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED15__VI = 0x5A93; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED150__VI = 0x5B1A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED151__VI = 0x5B1B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED152__VI = 0x5B1C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED153__VI = 0x5B1D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED154__VI = 0x5B1E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED155__VI = 0x5B1F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED156__VI = 0x5B20; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED157__VI = 0x5B21; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED158__VI = 0x5B22; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED159__VI = 0x5B23; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED16__VI = 0x5A94; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED160__VI = 0x5B24; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED161__VI = 0x5B25; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED162__VI = 0x5B26; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED163__VI = 0x5B27; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED164__VI = 0x5B28; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED165__VI = 0x5B29; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED166__VI = 0x5B2A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED167__VI = 0x5B2B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED168__VI = 0x5B2C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED169__VI = 0x5B2D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED17__VI = 0x5A95; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED170__VI = 0x5B2E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED171__VI = 0x5B2F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED172__VI = 0x5B30; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED173__VI = 0x5B31; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED174__VI = 0x5B32; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED175__VI = 0x5B33; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED176__VI = 0x5B34; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED177__VI = 0x5B35; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED178__VI = 0x5B36; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED179__VI = 0x5B37; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED18__VI = 0x5A96; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED180__VI = 0x5B38; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED181__VI = 0x5B39; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED182__VI = 0x5B3A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED183__VI = 0x5B3B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED184__VI = 0x5B3C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED185__VI = 0x5B3D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED186__VI = 0x5B3E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED187__VI = 0x5B3F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED188__VI = 0x5B40; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED189__VI = 0x5B41; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED19__VI = 0x5A97; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED190__VI = 0x5B42; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED191__VI = 0x5B43; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED192__VI = 0x5B44; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED193__VI = 0x5B45; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED194__VI = 0x5B46; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED195__VI = 0x5B47; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED196__VI = 0x5B48; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED197__VI = 0x5B49; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED198__VI = 0x5B4A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED199__VI = 0x5B4B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED2__VI = 0x5A86; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED20__VI = 0x5A98; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED200__VI = 0x5B4C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED201__VI = 0x5B4D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED202__VI = 0x5B4E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED203__VI = 0x5B4F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED204__VI = 0x5B50; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED205__VI = 0x5B51; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED206__VI = 0x5B52; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED207__VI = 0x5B53; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED208__VI = 0x5B54; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED209__VI = 0x5B55; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED21__VI = 0x5A99; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED210__VI = 0x5B56; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED211__VI = 0x5B57; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED212__VI = 0x5B58; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED213__VI = 0x5B59; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED214__VI = 0x5B5A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED215__VI = 0x5B5B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED216__VI = 0x5B5C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED217__VI = 0x5B5D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED218__VI = 0x5B5E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED219__VI = 0x5B5F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED22__VI = 0x5A9A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED220__VI = 0x5B60; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED221__VI = 0x5B61; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED222__VI = 0x5B62; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED223__VI = 0x5B63; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED224__VI = 0x5B64; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED225__VI = 0x5B65; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED226__VI = 0x5B66; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED227__VI = 0x5B67; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED228__VI = 0x5B68; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED229__VI = 0x5B69; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED23__VI = 0x5A9B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED230__VI = 0x5B6A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED231__VI = 0x5B6B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED232__VI = 0x5B6C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED233__VI = 0x5B6D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED234__VI = 0x5B6E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED235__VI = 0x5B6F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED236__VI = 0x5B70; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED237__VI = 0x5B71; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED238__VI = 0x5B72; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED239__VI = 0x5B73; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED24__VI = 0x5A9C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED240__VI = 0x5B74; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED241__VI = 0x5B75; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED242__VI = 0x5B76; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED243__VI = 0x5B77; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED244__VI = 0x5B78; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED245__VI = 0x5B79; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED246__VI = 0x5B7A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED247__VI = 0x5B7B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED248__VI = 0x5B7C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED249__VI = 0x5B7D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED25__VI = 0x5A9D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED250__VI = 0x5B7E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED251__VI = 0x5B7F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED252__VI = 0x5B80; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED253__VI = 0x5B81; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED254__VI = 0x5B82; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED255__VI = 0x5B83; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED256__VI = 0x5B84; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED257__VI = 0x5B85; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED258__VI = 0x5B86; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED259__VI = 0x5B87; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED26__VI = 0x5A9E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED260__VI = 0x5B88; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED261__VI = 0x5B89; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED262__VI = 0x5B8A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED263__VI = 0x5B8B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED264__VI = 0x5B8C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED265__VI = 0x5B8D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED266__VI = 0x5B8E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED267__VI = 0x5B8F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED268__VI = 0x5B90; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED269__VI = 0x5B91; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED27__VI = 0x5A9F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED270__VI = 0x5B92; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED271__VI = 0x5B93; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED272__VI = 0x5B94; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED273__VI = 0x5B95; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED274__VI = 0x5B96; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED275__VI = 0x5B97; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED276__VI = 0x5B98; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED277__VI = 0x5B99; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED278__VI = 0x5B9A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED279__VI = 0x5B9B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED28__VI = 0x5AA0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED280__VI = 0x5B9C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED281__VI = 0x5B9D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED282__VI = 0x5B9E; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED283__VI = 0x5B9F; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED284__VI = 0x5BA0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED285__VI = 0x5BA1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED286__VI = 0x5BA2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED287__VI = 0x5BA3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED288__VI = 0x5BA4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED289__VI = 0x5BA5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED29__VI = 0x5AA1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED290__VI = 0x5BA6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED291__VI = 0x5BA7; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED292__VI = 0x5BA8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED293__VI = 0x5BA9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED294__VI = 0x5BAA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED295__VI = 0x5BAB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED296__VI = 0x5BAC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED297__VI = 0x5BAD; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED298__VI = 0x5BAE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED299__VI = 0x5BAF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED3__VI = 0x5A87; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED30__VI = 0x5AA2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED300__VI = 0x5BB0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED301__VI = 0x5BB1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED302__VI = 0x5BB2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED303__VI = 0x5BB3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED304__VI = 0x5BB4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED305__VI = 0x5BB5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED306__VI = 0x5BB6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED307__VI = 0x5BB7; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED308__VI = 0x5BB8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED309__VI = 0x5BB9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED31__VI = 0x5AA3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED310__VI = 0x5BBA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED311__VI = 0x5BBB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED312__VI = 0x5BBC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED313__VI = 0x5BBD; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED314__VI = 0x5BBE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED315__VI = 0x5BBF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED316__VI = 0x5BC0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED317__VI = 0x5BC1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED318__VI = 0x5BC2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED319__VI = 0x5BC3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED32__VI = 0x5AA4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED320__VI = 0x5BC4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED321__VI = 0x5BC5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED322__VI = 0x5BC6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED323__VI = 0x5BC7; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED324__VI = 0x5BC8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED325__VI = 0x5BC9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED326__VI = 0x5BCA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED327__VI = 0x5BCB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED328__VI = 0x5BCC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED329__VI = 0x5BCD; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED33__VI = 0x5AA5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED330__VI = 0x5BCE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED331__VI = 0x5BCF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED332__VI = 0x5BD0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED333__VI = 0x5BD1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED334__VI = 0x5BD2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED335__VI = 0x5BD3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED336__VI = 0x5BD4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED337__VI = 0x5BD5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED338__VI = 0x5BD6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED339__VI = 0x5BD7; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED34__VI = 0x5AA6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED340__VI = 0x5BD8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED341__VI = 0x5BD9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED342__VI = 0x5BDA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED343__VI = 0x5BDB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED344__VI = 0x5BDC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED345__VI = 0x5BDD; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED346__VI = 0x5BDE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED347__VI = 0x5BDF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED348__VI = 0x5BE0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED349__VI = 0x5BE1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED35__VI = 0x5AA7; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED350__VI = 0x5BE2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED351__VI = 0x5BE3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED352__VI = 0x5BE4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED353__VI = 0x5BE5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED354__VI = 0x5BE6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED355__VI = 0x5BE7; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED356__VI = 0x5BE8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED357__VI = 0x5BE9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED358__VI = 0x5BEA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED359__VI = 0x5BEB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED36__VI = 0x5AA8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED360__VI = 0x5BEC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED361__VI = 0x5BED; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED362__VI = 0x5BEE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED363__VI = 0x5BEF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED364__VI = 0x5BF0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED365__VI = 0x5BF1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED366__VI = 0x5BF2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED367__VI = 0x5BF3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED368__VI = 0x5BF4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED369__VI = 0x5BF5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED37__VI = 0x5AA9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED370__VI = 0x5BF6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED371__VI = 0x5BF7; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED372__VI = 0x5BF8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED373__VI = 0x5BF9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED374__VI = 0x5BFA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED375__VI = 0x5BFB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED376__VI = 0x5BFC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED377__VI = 0x5BFD; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED378__VI = 0x5BFE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED379__VI = 0x5BFF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED38__VI = 0x5AAA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED39__VI = 0x5AAB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED4__VI = 0x5A88; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED40__VI = 0x5AAC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED41__VI = 0x5AAD; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED42__VI = 0x5AAE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED43__VI = 0x5AAF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED44__VI = 0x5AB0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED45__VI = 0x5AB1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED46__VI = 0x5AB2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED47__VI = 0x5AB3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED48__VI = 0x5AB4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED49__VI = 0x5AB5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED5__VI = 0x5A89; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED50__VI = 0x5AB6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED51__VI = 0x5AB7; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED52__VI = 0x5AB8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED53__VI = 0x5AB9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED54__VI = 0x5ABA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED55__VI = 0x5ABB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED56__VI = 0x5ABC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED57__VI = 0x5ABD; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED58__VI = 0x5ABE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED59__VI = 0x5ABF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED6__VI = 0x5A8A; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED60__VI = 0x5AC0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED61__VI = 0x5AC1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED62__VI = 0x5AC2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED63__VI = 0x5AC3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED64__VI = 0x5AC4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED65__VI = 0x5AC5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED66__VI = 0x5AC6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED67__VI = 0x5AC7; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED68__VI = 0x5AC8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED69__VI = 0x5AC9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED7__VI = 0x5A8B; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED70__VI = 0x5ACA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED71__VI = 0x5ACB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED72__VI = 0x5ACC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED73__VI = 0x5ACD; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED74__VI = 0x5ACE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED75__VI = 0x5ACF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED76__VI = 0x5AD0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED77__VI = 0x5AD1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED78__VI = 0x5AD2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED79__VI = 0x5AD3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED8__VI = 0x5A8C; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED80__VI = 0x5AD4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED81__VI = 0x5AD5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED82__VI = 0x5AD6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED83__VI = 0x5AD7; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED84__VI = 0x5AD8; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED85__VI = 0x5AD9; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED86__VI = 0x5ADA; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED87__VI = 0x5ADB; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED88__VI = 0x5ADC; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED89__VI = 0x5ADD; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED9__VI = 0x5A8D; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED90__VI = 0x5ADE; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED91__VI = 0x5ADF; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED92__VI = 0x5AE0; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED93__VI = 0x5AE1; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED94__VI = 0x5AE2; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED95__VI = 0x5AE3; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED96__VI = 0x5AE4; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED97__VI = 0x5AE5; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED98__VI = 0x5AE6; -constexpr unsigned int mmDCRX_PHY_MACRO_CNTL_RESERVED99__VI = 0x5AE7; -constexpr unsigned int mmDC_ABM1_OVERSCAN_PIXEL_VALUE__VI = 0x169B; -constexpr unsigned int mmDC_DVODATA_CONFIG__VI = 0x481A; -constexpr unsigned int mmDC_GENERICA__VI = 0x4800; -constexpr unsigned int mmDC_GENERICB__VI = 0x4801; -constexpr unsigned int mmDC_GPIO_DDC1_A__VI = 0x4869; -constexpr unsigned int mmDC_GPIO_DDC1_EN__VI = 0x486A; -constexpr unsigned int mmDC_GPIO_DDC1_MASK__VI = 0x4868; -constexpr unsigned int mmDC_GPIO_DDC1_Y__VI = 0x486B; -constexpr unsigned int mmDC_GPIO_DDC2_A__VI = 0x486D; -constexpr unsigned int mmDC_GPIO_DDC2_EN__VI = 0x486E; -constexpr unsigned int mmDC_GPIO_DDC2_MASK__VI = 0x486C; -constexpr unsigned int mmDC_GPIO_DDC2_Y__VI = 0x486F; -constexpr unsigned int mmDC_GPIO_DDC3_A__VI = 0x4871; -constexpr unsigned int mmDC_GPIO_DDC3_EN__VI = 0x4872; -constexpr unsigned int mmDC_GPIO_DDC3_MASK__VI = 0x4870; -constexpr unsigned int mmDC_GPIO_DDC3_Y__VI = 0x4873; -constexpr unsigned int mmDC_GPIO_DDC4_A__VI = 0x4875; -constexpr unsigned int mmDC_GPIO_DDC4_EN__VI = 0x4876; -constexpr unsigned int mmDC_GPIO_DDC4_MASK__VI = 0x4874; -constexpr unsigned int mmDC_GPIO_DDC4_Y__VI = 0x4877; -constexpr unsigned int mmDC_GPIO_DDC5_A__VI = 0x4879; -constexpr unsigned int mmDC_GPIO_DDC5_EN__VI = 0x487A; -constexpr unsigned int mmDC_GPIO_DDC5_MASK__VI = 0x4878; -constexpr unsigned int mmDC_GPIO_DDC5_Y__VI = 0x487B; -constexpr unsigned int mmDC_GPIO_DDC6_A__VI = 0x487D; -constexpr unsigned int mmDC_GPIO_DDC6_EN__VI = 0x487E; -constexpr unsigned int mmDC_GPIO_DDC6_MASK__VI = 0x487C; -constexpr unsigned int mmDC_GPIO_DDC6_Y__VI = 0x487F; -constexpr unsigned int mmDC_GPIO_DDCVGA_A__VI = 0x4881; -constexpr unsigned int mmDC_GPIO_DDCVGA_EN__VI = 0x4882; -constexpr unsigned int mmDC_GPIO_DDCVGA_MASK__VI = 0x4880; -constexpr unsigned int mmDC_GPIO_DDCVGA_Y__VI = 0x4883; -constexpr unsigned int mmDC_GPIO_DEBUG__VI = 0x4804; -constexpr unsigned int mmDC_GPIO_DVODATA_A__VI = 0x4865; -constexpr unsigned int mmDC_GPIO_DVODATA_EN__VI = 0x4866; -constexpr unsigned int mmDC_GPIO_DVODATA_MASK__VI = 0x4864; -constexpr unsigned int mmDC_GPIO_DVODATA_Y__VI = 0x4867; -constexpr unsigned int mmDC_GPIO_GENERIC_A__VI = 0x4861; -constexpr unsigned int mmDC_GPIO_GENERIC_EN__VI = 0x4862; -constexpr unsigned int mmDC_GPIO_GENERIC_MASK__VI = 0x4860; -constexpr unsigned int mmDC_GPIO_GENERIC_Y__VI = 0x4863; -constexpr unsigned int mmDC_GPIO_GENLK_A__VI = 0x4889; -constexpr unsigned int mmDC_GPIO_GENLK_EN__VI = 0x488A; -constexpr unsigned int mmDC_GPIO_GENLK_MASK__VI = 0x4888; -constexpr unsigned int mmDC_GPIO_GENLK_Y__VI = 0x488B; -constexpr unsigned int mmDC_GPIO_HPD_A__VI = 0x488D; -constexpr unsigned int mmDC_GPIO_HPD_EN__VI = 0x488E; -constexpr unsigned int mmDC_GPIO_HPD_MASK__VI = 0x488C; -constexpr unsigned int mmDC_GPIO_HPD_Y__VI = 0x488F; -constexpr unsigned int mmDC_GPIO_I2CPAD_A__VI = 0x4899; -constexpr unsigned int mmDC_GPIO_I2CPAD_EN__VI = 0x489A; -constexpr unsigned int mmDC_GPIO_I2CPAD_MASK__VI = 0x4898; -constexpr unsigned int mmDC_GPIO_I2CPAD_STRENGTH__VI = 0x489C; -constexpr unsigned int mmDC_GPIO_I2CPAD_Y__VI = 0x489B; -constexpr unsigned int mmDC_GPIO_PAD_STRENGTH_1__VI = 0x4894; -constexpr unsigned int mmDC_GPIO_PAD_STRENGTH_2__VI = 0x4895; -constexpr unsigned int mmDC_GPIO_PWRSEQ_A__VI = 0x4891; -constexpr unsigned int mmDC_GPIO_PWRSEQ_EN__VI = 0x4892; -constexpr unsigned int mmDC_GPIO_PWRSEQ_MASK__VI = 0x4890; -constexpr unsigned int mmDC_GPIO_PWRSEQ_Y__VI = 0x4893; -constexpr unsigned int mmDC_GPIO_SYNCA_A__VI = 0x4885; -constexpr unsigned int mmDC_GPIO_SYNCA_EN__VI = 0x4886; -constexpr unsigned int mmDC_GPIO_SYNCA_MASK__VI = 0x4884; -constexpr unsigned int mmDC_GPIO_SYNCA_Y__VI = 0x4887; -constexpr unsigned int mmDC_GPU_TIMER_READ__VI = 0x482B; -constexpr unsigned int mmDC_GPU_TIMER_READ_CNTL__VI = 0x482C; -constexpr unsigned int mmDC_GPU_TIMER_START_POSITION_P_FLIP__VI = 0x482A; -constexpr unsigned int mmDC_GPU_TIMER_START_POSITION_V_UPDATE__VI = 0x4829; -constexpr unsigned int mmDC_HPD_CONTROL__VI = 0x189A; -constexpr unsigned int mmDC_HPD_FAST_TRAIN_CNTL__VI = 0x189B; -constexpr unsigned int mmDC_HPD_INT_CONTROL__VI = 0x1899; -constexpr unsigned int mmDC_HPD_INT_STATUS__VI = 0x1898; -constexpr unsigned int mmDC_HPD_TOGGLE_FILT_CNTL__VI = 0x189C; -constexpr unsigned int mmDC_I2C_ARBITRATION__VI = 0x16D5; -constexpr unsigned int mmDC_I2C_CONTROL__VI = 0x16D4; -constexpr unsigned int mmDC_I2C_DATA__VI = 0x16EE; -constexpr unsigned int mmDC_I2C_DDC1_HW_STATUS__VI = 0x16D8; -constexpr unsigned int mmDC_I2C_DDC1_SETUP__VI = 0x16DF; -constexpr unsigned int mmDC_I2C_DDC1_SPEED__VI = 0x16DE; -constexpr unsigned int mmDC_I2C_DDC2_HW_STATUS__VI = 0x16D9; -constexpr unsigned int mmDC_I2C_DDC2_SETUP__VI = 0x16E1; -constexpr unsigned int mmDC_I2C_DDC2_SPEED__VI = 0x16E0; -constexpr unsigned int mmDC_I2C_DDC3_HW_STATUS__VI = 0x16DA; -constexpr unsigned int mmDC_I2C_DDC3_SETUP__VI = 0x16E3; -constexpr unsigned int mmDC_I2C_DDC3_SPEED__VI = 0x16E2; -constexpr unsigned int mmDC_I2C_DDC4_HW_STATUS__VI = 0x16DB; -constexpr unsigned int mmDC_I2C_DDC4_SETUP__VI = 0x16E5; -constexpr unsigned int mmDC_I2C_DDC4_SPEED__VI = 0x16E4; -constexpr unsigned int mmDC_I2C_DDC5_HW_STATUS__VI = 0x16DC; -constexpr unsigned int mmDC_I2C_DDC5_SETUP__VI = 0x16E7; -constexpr unsigned int mmDC_I2C_DDC5_SPEED__VI = 0x16E6; -constexpr unsigned int mmDC_I2C_DDC6_HW_STATUS__VI = 0x16DD; -constexpr unsigned int mmDC_I2C_DDC6_SETUP__VI = 0x16E9; -constexpr unsigned int mmDC_I2C_DDC6_SPEED__VI = 0x16E8; -constexpr unsigned int mmDC_I2C_DDCVGA_HW_STATUS__VI = 0x16EF; -constexpr unsigned int mmDC_I2C_DDCVGA_SETUP__VI = 0x16F1; -constexpr unsigned int mmDC_I2C_DDCVGA_SPEED__VI = 0x16F0; -constexpr unsigned int mmDC_I2C_EDID_DETECT_CTRL__VI = 0x16F2; -constexpr unsigned int mmDC_I2C_INTERRUPT_CONTROL__VI = 0x16D6; -constexpr unsigned int mmDC_I2C_SW_STATUS__VI = 0x16D7; -constexpr unsigned int mmDC_I2C_TRANSACTION0__VI = 0x16EA; -constexpr unsigned int mmDC_I2C_TRANSACTION1__VI = 0x16EB; -constexpr unsigned int mmDC_I2C_TRANSACTION2__VI = 0x16EC; -constexpr unsigned int mmDC_I2C_TRANSACTION3__VI = 0x16ED; -constexpr unsigned int mmDC_IP_REQUEST_CNTL__VI = 0x02D2; -constexpr unsigned int mmDC_LUT_VGA_ACCESS_ENABLE__VI = 0x1A7D; -constexpr unsigned int mmDC_MEM_GLOBAL_PWR_REQ_CNTL__VI = 0x0132; -constexpr unsigned int mmDC_MVP_LB_CONTROL__VI = 0x1AE3; -constexpr unsigned int mmDC_PAD_EXTERN_SIG__VI = 0x4802; -constexpr unsigned int mmDC_PERFMON0_PERFCOUNTER_CNTL__VI = 0x0170; -constexpr unsigned int mmDC_PERFMON0_PERFCOUNTER_STATE__VI = 0x0171; -constexpr unsigned int mmDC_PERFMON0_PERFMON_CNTL__VI = 0x0173; -constexpr unsigned int mmDC_PERFMON0_PERFMON_CNTL2__VI = 0x017A; -constexpr unsigned int mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC__VI = 0x0172; -constexpr unsigned int mmDC_PERFMON0_PERFMON_CVALUE_LOW__VI = 0x0174; -constexpr unsigned int mmDC_PERFMON0_PERFMON_HI__VI = 0x0175; -constexpr unsigned int mmDC_PERFMON0_PERFMON_LOW__VI = 0x0176; -constexpr unsigned int mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA__VI = 0x0178; -constexpr unsigned int mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX__VI = 0x0177; -constexpr unsigned int mmDC_PERFMON10_PERFCOUNTER_CNTL__VI = 0x59A0; -constexpr unsigned int mmDC_PERFMON10_PERFCOUNTER_STATE__VI = 0x59A1; -constexpr unsigned int mmDC_PERFMON10_PERFMON_CNTL__VI = 0x59A3; -constexpr unsigned int mmDC_PERFMON10_PERFMON_CNTL2__VI = 0x59AA; -constexpr unsigned int mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC__VI = 0x59A2; -constexpr unsigned int mmDC_PERFMON10_PERFMON_CVALUE_LOW__VI = 0x59A4; -constexpr unsigned int mmDC_PERFMON10_PERFMON_HI__VI = 0x59A5; -constexpr unsigned int mmDC_PERFMON10_PERFMON_LOW__VI = 0x59A6; -constexpr unsigned int mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA__VI = 0x59A8; -constexpr unsigned int mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX__VI = 0x59A7; -constexpr unsigned int mmDC_PERFMON11_PERFCOUNTER_CNTL__VI = 0x4724; -constexpr unsigned int mmDC_PERFMON11_PERFCOUNTER_STATE__VI = 0x4725; -constexpr unsigned int mmDC_PERFMON11_PERFMON_CNTL__VI = 0x4727; -constexpr unsigned int mmDC_PERFMON11_PERFMON_CNTL2__VI = 0x472E; -constexpr unsigned int mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC__VI = 0x4726; -constexpr unsigned int mmDC_PERFMON11_PERFMON_CVALUE_LOW__VI = 0x4728; -constexpr unsigned int mmDC_PERFMON11_PERFMON_HI__VI = 0x4729; -constexpr unsigned int mmDC_PERFMON11_PERFMON_LOW__VI = 0x472A; -constexpr unsigned int mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA__VI = 0x472C; -constexpr unsigned int mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX__VI = 0x472B; -constexpr unsigned int mmDC_PERFMON1_PERFCOUNTER_CNTL__VI = 0x0364; -constexpr unsigned int mmDC_PERFMON1_PERFCOUNTER_STATE__VI = 0x0365; -constexpr unsigned int mmDC_PERFMON1_PERFMON_CNTL__VI = 0x0367; -constexpr unsigned int mmDC_PERFMON1_PERFMON_CNTL2__VI = 0x036E; -constexpr unsigned int mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC__VI = 0x0366; -constexpr unsigned int mmDC_PERFMON1_PERFMON_CVALUE_LOW__VI = 0x0368; -constexpr unsigned int mmDC_PERFMON1_PERFMON_HI__VI = 0x0369; -constexpr unsigned int mmDC_PERFMON1_PERFMON_LOW__VI = 0x036A; -constexpr unsigned int mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA__VI = 0x036C; -constexpr unsigned int mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX__VI = 0x036B; -constexpr unsigned int mmDC_PERFMON2_PERFCOUNTER_CNTL__VI = 0x18C8; -constexpr unsigned int mmDC_PERFMON2_PERFCOUNTER_STATE__VI = 0x18C9; -constexpr unsigned int mmDC_PERFMON2_PERFMON_CNTL__VI = 0x18CB; -constexpr unsigned int mmDC_PERFMON2_PERFMON_CNTL2__VI = 0x18D2; -constexpr unsigned int mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC__VI = 0x18CA; -constexpr unsigned int mmDC_PERFMON2_PERFMON_CVALUE_LOW__VI = 0x18CC; -constexpr unsigned int mmDC_PERFMON2_PERFMON_HI__VI = 0x18CD; -constexpr unsigned int mmDC_PERFMON2_PERFMON_LOW__VI = 0x18CE; -constexpr unsigned int mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA__VI = 0x18D0; -constexpr unsigned int mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX__VI = 0x18CF; -constexpr unsigned int mmDC_PERFMON3_PERFCOUNTER_CNTL__VI = 0x1B24; -constexpr unsigned int mmDC_PERFMON3_PERFCOUNTER_STATE__VI = 0x1B25; -constexpr unsigned int mmDC_PERFMON3_PERFMON_CNTL__VI = 0x1B27; -constexpr unsigned int mmDC_PERFMON3_PERFMON_CNTL2__VI = 0x1B2E; -constexpr unsigned int mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC__VI = 0x1B26; -constexpr unsigned int mmDC_PERFMON3_PERFMON_CVALUE_LOW__VI = 0x1B28; -constexpr unsigned int mmDC_PERFMON3_PERFMON_HI__VI = 0x1B29; -constexpr unsigned int mmDC_PERFMON3_PERFMON_LOW__VI = 0x1B2A; -constexpr unsigned int mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA__VI = 0x1B2C; -constexpr unsigned int mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX__VI = 0x1B2B; -constexpr unsigned int mmDC_PERFMON4_PERFCOUNTER_CNTL__VI = 0x1D24; -constexpr unsigned int mmDC_PERFMON4_PERFCOUNTER_STATE__VI = 0x1D25; -constexpr unsigned int mmDC_PERFMON4_PERFMON_CNTL__VI = 0x1D27; -constexpr unsigned int mmDC_PERFMON4_PERFMON_CNTL2__VI = 0x1D2E; -constexpr unsigned int mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC__VI = 0x1D26; -constexpr unsigned int mmDC_PERFMON4_PERFMON_CVALUE_LOW__VI = 0x1D28; -constexpr unsigned int mmDC_PERFMON4_PERFMON_HI__VI = 0x1D29; -constexpr unsigned int mmDC_PERFMON4_PERFMON_LOW__VI = 0x1D2A; -constexpr unsigned int mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA__VI = 0x1D2C; -constexpr unsigned int mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX__VI = 0x1D2B; -constexpr unsigned int mmDC_PERFMON5_PERFCOUNTER_CNTL__VI = 0x1F24; -constexpr unsigned int mmDC_PERFMON5_PERFCOUNTER_STATE__VI = 0x1F25; -constexpr unsigned int mmDC_PERFMON5_PERFMON_CNTL__VI = 0x1F27; -constexpr unsigned int mmDC_PERFMON5_PERFMON_CNTL2__VI = 0x1F2E; -constexpr unsigned int mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC__VI = 0x1F26; -constexpr unsigned int mmDC_PERFMON5_PERFMON_CVALUE_LOW__VI = 0x1F28; -constexpr unsigned int mmDC_PERFMON5_PERFMON_HI__VI = 0x1F29; -constexpr unsigned int mmDC_PERFMON5_PERFMON_LOW__VI = 0x1F2A; -constexpr unsigned int mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA__VI = 0x1F2C; -constexpr unsigned int mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX__VI = 0x1F2B; -constexpr unsigned int mmDC_PERFMON6_PERFCOUNTER_CNTL__VI = 0x4124; -constexpr unsigned int mmDC_PERFMON6_PERFCOUNTER_STATE__VI = 0x4125; -constexpr unsigned int mmDC_PERFMON6_PERFMON_CNTL__VI = 0x4127; -constexpr unsigned int mmDC_PERFMON6_PERFMON_CNTL2__VI = 0x412E; -constexpr unsigned int mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC__VI = 0x4126; -constexpr unsigned int mmDC_PERFMON6_PERFMON_CVALUE_LOW__VI = 0x4128; -constexpr unsigned int mmDC_PERFMON6_PERFMON_HI__VI = 0x4129; -constexpr unsigned int mmDC_PERFMON6_PERFMON_LOW__VI = 0x412A; -constexpr unsigned int mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA__VI = 0x412C; -constexpr unsigned int mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX__VI = 0x412B; -constexpr unsigned int mmDC_PERFMON7_PERFCOUNTER_CNTL__VI = 0x4324; -constexpr unsigned int mmDC_PERFMON7_PERFCOUNTER_STATE__VI = 0x4325; -constexpr unsigned int mmDC_PERFMON7_PERFMON_CNTL__VI = 0x4327; -constexpr unsigned int mmDC_PERFMON7_PERFMON_CNTL2__VI = 0x432E; -constexpr unsigned int mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC__VI = 0x4326; -constexpr unsigned int mmDC_PERFMON7_PERFMON_CVALUE_LOW__VI = 0x4328; -constexpr unsigned int mmDC_PERFMON7_PERFMON_HI__VI = 0x4329; -constexpr unsigned int mmDC_PERFMON7_PERFMON_LOW__VI = 0x432A; -constexpr unsigned int mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA__VI = 0x432C; -constexpr unsigned int mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX__VI = 0x432B; -constexpr unsigned int mmDC_PERFMON8_PERFCOUNTER_CNTL__VI = 0x4524; -constexpr unsigned int mmDC_PERFMON8_PERFCOUNTER_STATE__VI = 0x4525; -constexpr unsigned int mmDC_PERFMON8_PERFMON_CNTL__VI = 0x4527; -constexpr unsigned int mmDC_PERFMON8_PERFMON_CNTL2__VI = 0x452E; -constexpr unsigned int mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC__VI = 0x4526; -constexpr unsigned int mmDC_PERFMON8_PERFMON_CVALUE_LOW__VI = 0x4528; -constexpr unsigned int mmDC_PERFMON8_PERFMON_HI__VI = 0x4529; -constexpr unsigned int mmDC_PERFMON8_PERFMON_LOW__VI = 0x452A; -constexpr unsigned int mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA__VI = 0x452C; -constexpr unsigned int mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX__VI = 0x452B; -constexpr unsigned int mmDC_PERFMON9_PERFCOUNTER_CNTL__VI = 0x5F68; -constexpr unsigned int mmDC_PERFMON9_PERFCOUNTER_STATE__VI = 0x5F69; -constexpr unsigned int mmDC_PERFMON9_PERFMON_CNTL__VI = 0x5F6B; -constexpr unsigned int mmDC_PERFMON9_PERFMON_CNTL2__VI = 0x5F72; -constexpr unsigned int mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC__VI = 0x5F6A; -constexpr unsigned int mmDC_PERFMON9_PERFMON_CVALUE_LOW__VI = 0x5F6C; -constexpr unsigned int mmDC_PERFMON9_PERFMON_HI__VI = 0x5F6D; -constexpr unsigned int mmDC_PERFMON9_PERFMON_LOW__VI = 0x5F6E; -constexpr unsigned int mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA__VI = 0x5F70; -constexpr unsigned int mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX__VI = 0x5F6F; -constexpr unsigned int mmDC_PGCNTL_STATUS_REG__VI = 0x02D5; -constexpr unsigned int mmDC_PGFSM_CONFIG_REG__VI = 0x02D3; -constexpr unsigned int mmDC_PGFSM_WRITE_REG__VI = 0x02D4; -constexpr unsigned int mmDC_PINSTRAPS__VI = 0x4818; -constexpr unsigned int mmDC_REF_CLK_CNTL__VI = 0x4803; -constexpr unsigned int mmDC_TEST_DEBUG_DATA__VI = 0x157D; -constexpr unsigned int mmDC_TEST_DEBUG_INDEX__VI = 0x157C; -constexpr unsigned int mmDEGAMMA_CONTROL__VI = 0x1A58; -constexpr unsigned int mmDENORM_CLAMP_CONTROL__VI = 0x46C3; -constexpr unsigned int mmDENORM_CLAMP_RANGE_B_CB__VI = 0x46C6; -constexpr unsigned int mmDENORM_CLAMP_RANGE_G_Y__VI = 0x46C5; -constexpr unsigned int mmDENORM_CLAMP_RANGE_R_CR__VI = 0x46C4; -constexpr unsigned int mmDENORM_CONTROL__VI = 0x1A50; -constexpr unsigned int mmDENTIST_DISPCLK_CNTL__VI = 0x0124; -constexpr unsigned int mmDIG0_AFMT_60958_0__VI = 0x4A38; -constexpr unsigned int mmDIG0_AFMT_60958_1__VI = 0x4A39; -constexpr unsigned int mmDIG0_AFMT_60958_2__VI = 0x4A3F; -constexpr unsigned int mmDIG0_AFMT_AUDIO_CRC_CONTROL__VI = 0x4A3A; -constexpr unsigned int mmDIG0_AFMT_AUDIO_CRC_RESULT__VI = 0x4A40; -constexpr unsigned int mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL__VI = 0x4A46; -constexpr unsigned int mmDIG0_AFMT_AUDIO_INFO0__VI = 0x4A36; -constexpr unsigned int mmDIG0_AFMT_AUDIO_INFO1__VI = 0x4A37; -constexpr unsigned int mmDIG0_AFMT_AUDIO_PACKET_CONTROL__VI = 0x4A42; -constexpr unsigned int mmDIG0_AFMT_AUDIO_PACKET_CONTROL2__VI = 0x4A14; -constexpr unsigned int mmDIG0_AFMT_AUDIO_SRC_CONTROL__VI = 0x4A45; -constexpr unsigned int mmDIG0_AFMT_AVI_INFO0__VI = 0x4A1E; -constexpr unsigned int mmDIG0_AFMT_AVI_INFO1__VI = 0x4A1F; -constexpr unsigned int mmDIG0_AFMT_AVI_INFO2__VI = 0x4A20; -constexpr unsigned int mmDIG0_AFMT_AVI_INFO3__VI = 0x4A21; -constexpr unsigned int mmDIG0_AFMT_GENERIC_0__VI = 0x4A25; -constexpr unsigned int mmDIG0_AFMT_GENERIC_1__VI = 0x4A26; -constexpr unsigned int mmDIG0_AFMT_GENERIC_2__VI = 0x4A27; -constexpr unsigned int mmDIG0_AFMT_GENERIC_3__VI = 0x4A28; -constexpr unsigned int mmDIG0_AFMT_GENERIC_4__VI = 0x4A29; -constexpr unsigned int mmDIG0_AFMT_GENERIC_5__VI = 0x4A2A; -constexpr unsigned int mmDIG0_AFMT_GENERIC_6__VI = 0x4A2B; -constexpr unsigned int mmDIG0_AFMT_GENERIC_7__VI = 0x4A2C; -constexpr unsigned int mmDIG0_AFMT_GENERIC_HDR__VI = 0x4A24; -constexpr unsigned int mmDIG0_AFMT_INFOFRAME_CONTROL0__VI = 0x4A44; -constexpr unsigned int mmDIG0_AFMT_ISRC1_0__VI = 0x4A15; -constexpr unsigned int mmDIG0_AFMT_ISRC1_1__VI = 0x4A16; -constexpr unsigned int mmDIG0_AFMT_ISRC1_2__VI = 0x4A17; -constexpr unsigned int mmDIG0_AFMT_ISRC1_3__VI = 0x4A18; -constexpr unsigned int mmDIG0_AFMT_ISRC1_4__VI = 0x4A19; -constexpr unsigned int mmDIG0_AFMT_ISRC2_0__VI = 0x4A1A; -constexpr unsigned int mmDIG0_AFMT_ISRC2_1__VI = 0x4A1B; -constexpr unsigned int mmDIG0_AFMT_ISRC2_2__VI = 0x4A1C; -constexpr unsigned int mmDIG0_AFMT_ISRC2_3__VI = 0x4A1D; -constexpr unsigned int mmDIG0_AFMT_MPEG_INFO0__VI = 0x4A22; -constexpr unsigned int mmDIG0_AFMT_MPEG_INFO1__VI = 0x4A23; -constexpr unsigned int mmDIG0_AFMT_RAMP_CONTROL0__VI = 0x4A3B; -constexpr unsigned int mmDIG0_AFMT_RAMP_CONTROL1__VI = 0x4A3C; -constexpr unsigned int mmDIG0_AFMT_RAMP_CONTROL2__VI = 0x4A3D; -constexpr unsigned int mmDIG0_AFMT_RAMP_CONTROL3__VI = 0x4A3E; -constexpr unsigned int mmDIG0_AFMT_STATUS__VI = 0x4A41; -constexpr unsigned int mmDIG0_AFMT_VBI_PACKET_CONTROL__VI = 0x4A43; -constexpr unsigned int mmDIG0_DIG_BE_CNTL__VI = 0x4A47; -constexpr unsigned int mmDIG0_DIG_BE_EN_CNTL__VI = 0x4A48; -constexpr unsigned int mmDIG0_DIG_CLOCK_PATTERN__VI = 0x4A03; -constexpr unsigned int mmDIG0_DIG_DISPCLK_SWITCH_CNTL__VI = 0x4A07; -constexpr unsigned int mmDIG0_DIG_DISPCLK_SWITCH_STATUS__VI = 0x4A08; -constexpr unsigned int mmDIG0_DIG_FE_CNTL__VI = 0x4A00; -constexpr unsigned int mmDIG0_DIG_FE_TEST_DEBUG_DATA__VI = 0x4A7D; -constexpr unsigned int mmDIG0_DIG_FE_TEST_DEBUG_INDEX__VI = 0x4A7C; -constexpr unsigned int mmDIG0_DIG_FIFO_STATUS__VI = 0x4A06; -constexpr unsigned int mmDIG0_DIG_LANE_ENABLE__VI = 0x4A79; -constexpr unsigned int mmDIG0_DIG_OUTPUT_CRC_CNTL__VI = 0x4A01; -constexpr unsigned int mmDIG0_DIG_OUTPUT_CRC_RESULT__VI = 0x4A02; -constexpr unsigned int mmDIG0_DIG_RANDOM_PATTERN_SEED__VI = 0x4A05; -constexpr unsigned int mmDIG0_DIG_TEST_DEBUG_DATA__VI = 0x4A7B; -constexpr unsigned int mmDIG0_DIG_TEST_DEBUG_INDEX__VI = 0x4A7A; -constexpr unsigned int mmDIG0_DIG_TEST_PATTERN__VI = 0x4A04; -constexpr unsigned int mmDIG0_HDMI_ACR_32_0__VI = 0x4A2E; -constexpr unsigned int mmDIG0_HDMI_ACR_32_1__VI = 0x4A2F; -constexpr unsigned int mmDIG0_HDMI_ACR_44_0__VI = 0x4A30; -constexpr unsigned int mmDIG0_HDMI_ACR_44_1__VI = 0x4A31; -constexpr unsigned int mmDIG0_HDMI_ACR_48_0__VI = 0x4A32; -constexpr unsigned int mmDIG0_HDMI_ACR_48_1__VI = 0x4A33; -constexpr unsigned int mmDIG0_HDMI_ACR_PACKET_CONTROL__VI = 0x4A0C; -constexpr unsigned int mmDIG0_HDMI_ACR_STATUS_0__VI = 0x4A34; -constexpr unsigned int mmDIG0_HDMI_ACR_STATUS_1__VI = 0x4A35; -constexpr unsigned int mmDIG0_HDMI_AUDIO_PACKET_CONTROL__VI = 0x4A0B; -constexpr unsigned int mmDIG0_HDMI_CONTROL__VI = 0x4A09; -constexpr unsigned int mmDIG0_HDMI_GC__VI = 0x4A13; -constexpr unsigned int mmDIG0_HDMI_GENERIC_PACKET_CONTROL0__VI = 0x4A10; -constexpr unsigned int mmDIG0_HDMI_GENERIC_PACKET_CONTROL1__VI = 0x4A2D; -constexpr unsigned int mmDIG0_HDMI_INFOFRAME_CONTROL0__VI = 0x4A0E; -constexpr unsigned int mmDIG0_HDMI_INFOFRAME_CONTROL1__VI = 0x4A0F; -constexpr unsigned int mmDIG0_HDMI_STATUS__VI = 0x4A0A; -constexpr unsigned int mmDIG0_HDMI_VBI_PACKET_CONTROL__VI = 0x4A0D; -constexpr unsigned int mmDIG0_LVDS_DATA_CNTL__VI = 0x4A78; -constexpr unsigned int mmDIG0_TMDS_CNTL__VI = 0x4A6B; -constexpr unsigned int mmDIG0_TMDS_CONTROL0_FEEDBACK__VI = 0x4A6D; -constexpr unsigned int mmDIG0_TMDS_CONTROL_CHAR__VI = 0x4A6C; -constexpr unsigned int mmDIG0_TMDS_CTL0_1_GEN_CNTL__VI = 0x4A75; -constexpr unsigned int mmDIG0_TMDS_CTL2_3_GEN_CNTL__VI = 0x4A76; -constexpr unsigned int mmDIG0_TMDS_CTL_BITS__VI = 0x4A72; -constexpr unsigned int mmDIG0_TMDS_DCBALANCER_CONTROL__VI = 0x4A73; -constexpr unsigned int mmDIG0_TMDS_DEBUG__VI = 0x4A71; -constexpr unsigned int mmDIG0_TMDS_STEREOSYNC_CTL_SEL__VI = 0x4A6E; -constexpr unsigned int mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1__VI = 0x4A6F; -constexpr unsigned int mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3__VI = 0x4A70; -constexpr unsigned int mmDIG1_AFMT_60958_0__VI = 0x4B38; -constexpr unsigned int mmDIG1_AFMT_60958_1__VI = 0x4B39; -constexpr unsigned int mmDIG1_AFMT_60958_2__VI = 0x4B3F; -constexpr unsigned int mmDIG1_AFMT_AUDIO_CRC_CONTROL__VI = 0x4B3A; -constexpr unsigned int mmDIG1_AFMT_AUDIO_CRC_RESULT__VI = 0x4B40; -constexpr unsigned int mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL__VI = 0x4B46; -constexpr unsigned int mmDIG1_AFMT_AUDIO_INFO0__VI = 0x4B36; -constexpr unsigned int mmDIG1_AFMT_AUDIO_INFO1__VI = 0x4B37; -constexpr unsigned int mmDIG1_AFMT_AUDIO_PACKET_CONTROL__VI = 0x4B42; -constexpr unsigned int mmDIG1_AFMT_AUDIO_PACKET_CONTROL2__VI = 0x4B14; -constexpr unsigned int mmDIG1_AFMT_AUDIO_SRC_CONTROL__VI = 0x4B45; -constexpr unsigned int mmDIG1_AFMT_AVI_INFO0__VI = 0x4B1E; -constexpr unsigned int mmDIG1_AFMT_AVI_INFO1__VI = 0x4B1F; -constexpr unsigned int mmDIG1_AFMT_AVI_INFO2__VI = 0x4B20; -constexpr unsigned int mmDIG1_AFMT_AVI_INFO3__VI = 0x4B21; -constexpr unsigned int mmDIG1_AFMT_GENERIC_0__VI = 0x4B25; -constexpr unsigned int mmDIG1_AFMT_GENERIC_1__VI = 0x4B26; -constexpr unsigned int mmDIG1_AFMT_GENERIC_2__VI = 0x4B27; -constexpr unsigned int mmDIG1_AFMT_GENERIC_3__VI = 0x4B28; -constexpr unsigned int mmDIG1_AFMT_GENERIC_4__VI = 0x4B29; -constexpr unsigned int mmDIG1_AFMT_GENERIC_5__VI = 0x4B2A; -constexpr unsigned int mmDIG1_AFMT_GENERIC_6__VI = 0x4B2B; -constexpr unsigned int mmDIG1_AFMT_GENERIC_7__VI = 0x4B2C; -constexpr unsigned int mmDIG1_AFMT_GENERIC_HDR__VI = 0x4B24; -constexpr unsigned int mmDIG1_AFMT_INFOFRAME_CONTROL0__VI = 0x4B44; -constexpr unsigned int mmDIG1_AFMT_ISRC1_0__VI = 0x4B15; -constexpr unsigned int mmDIG1_AFMT_ISRC1_1__VI = 0x4B16; -constexpr unsigned int mmDIG1_AFMT_ISRC1_2__VI = 0x4B17; -constexpr unsigned int mmDIG1_AFMT_ISRC1_3__VI = 0x4B18; -constexpr unsigned int mmDIG1_AFMT_ISRC1_4__VI = 0x4B19; -constexpr unsigned int mmDIG1_AFMT_ISRC2_0__VI = 0x4B1A; -constexpr unsigned int mmDIG1_AFMT_ISRC2_1__VI = 0x4B1B; -constexpr unsigned int mmDIG1_AFMT_ISRC2_2__VI = 0x4B1C; -constexpr unsigned int mmDIG1_AFMT_ISRC2_3__VI = 0x4B1D; -constexpr unsigned int mmDIG1_AFMT_MPEG_INFO0__VI = 0x4B22; -constexpr unsigned int mmDIG1_AFMT_MPEG_INFO1__VI = 0x4B23; -constexpr unsigned int mmDIG1_AFMT_RAMP_CONTROL0__VI = 0x4B3B; -constexpr unsigned int mmDIG1_AFMT_RAMP_CONTROL1__VI = 0x4B3C; -constexpr unsigned int mmDIG1_AFMT_RAMP_CONTROL2__VI = 0x4B3D; -constexpr unsigned int mmDIG1_AFMT_RAMP_CONTROL3__VI = 0x4B3E; -constexpr unsigned int mmDIG1_AFMT_STATUS__VI = 0x4B41; -constexpr unsigned int mmDIG1_AFMT_VBI_PACKET_CONTROL__VI = 0x4B43; -constexpr unsigned int mmDIG1_DIG_BE_CNTL__VI = 0x4B47; -constexpr unsigned int mmDIG1_DIG_BE_EN_CNTL__VI = 0x4B48; -constexpr unsigned int mmDIG1_DIG_CLOCK_PATTERN__VI = 0x4B03; -constexpr unsigned int mmDIG1_DIG_DISPCLK_SWITCH_CNTL__VI = 0x4B07; -constexpr unsigned int mmDIG1_DIG_DISPCLK_SWITCH_STATUS__VI = 0x4B08; -constexpr unsigned int mmDIG1_DIG_FE_CNTL__VI = 0x4B00; -constexpr unsigned int mmDIG1_DIG_FE_TEST_DEBUG_DATA__VI = 0x4B7D; -constexpr unsigned int mmDIG1_DIG_FE_TEST_DEBUG_INDEX__VI = 0x4B7C; -constexpr unsigned int mmDIG1_DIG_FIFO_STATUS__VI = 0x4B06; -constexpr unsigned int mmDIG1_DIG_LANE_ENABLE__VI = 0x4B79; -constexpr unsigned int mmDIG1_DIG_OUTPUT_CRC_CNTL__VI = 0x4B01; -constexpr unsigned int mmDIG1_DIG_OUTPUT_CRC_RESULT__VI = 0x4B02; -constexpr unsigned int mmDIG1_DIG_RANDOM_PATTERN_SEED__VI = 0x4B05; -constexpr unsigned int mmDIG1_DIG_TEST_DEBUG_DATA__VI = 0x4B7B; -constexpr unsigned int mmDIG1_DIG_TEST_DEBUG_INDEX__VI = 0x4B7A; -constexpr unsigned int mmDIG1_DIG_TEST_PATTERN__VI = 0x4B04; -constexpr unsigned int mmDIG1_HDMI_ACR_32_0__VI = 0x4B2E; -constexpr unsigned int mmDIG1_HDMI_ACR_32_1__VI = 0x4B2F; -constexpr unsigned int mmDIG1_HDMI_ACR_44_0__VI = 0x4B30; -constexpr unsigned int mmDIG1_HDMI_ACR_44_1__VI = 0x4B31; -constexpr unsigned int mmDIG1_HDMI_ACR_48_0__VI = 0x4B32; -constexpr unsigned int mmDIG1_HDMI_ACR_48_1__VI = 0x4B33; -constexpr unsigned int mmDIG1_HDMI_ACR_PACKET_CONTROL__VI = 0x4B0C; -constexpr unsigned int mmDIG1_HDMI_ACR_STATUS_0__VI = 0x4B34; -constexpr unsigned int mmDIG1_HDMI_ACR_STATUS_1__VI = 0x4B35; -constexpr unsigned int mmDIG1_HDMI_AUDIO_PACKET_CONTROL__VI = 0x4B0B; -constexpr unsigned int mmDIG1_HDMI_CONTROL__VI = 0x4B09; -constexpr unsigned int mmDIG1_HDMI_GC__VI = 0x4B13; -constexpr unsigned int mmDIG1_HDMI_GENERIC_PACKET_CONTROL0__VI = 0x4B10; -constexpr unsigned int mmDIG1_HDMI_GENERIC_PACKET_CONTROL1__VI = 0x4B2D; -constexpr unsigned int mmDIG1_HDMI_INFOFRAME_CONTROL0__VI = 0x4B0E; -constexpr unsigned int mmDIG1_HDMI_INFOFRAME_CONTROL1__VI = 0x4B0F; -constexpr unsigned int mmDIG1_HDMI_STATUS__VI = 0x4B0A; -constexpr unsigned int mmDIG1_HDMI_VBI_PACKET_CONTROL__VI = 0x4B0D; -constexpr unsigned int mmDIG1_LVDS_DATA_CNTL__VI = 0x4B78; -constexpr unsigned int mmDIG1_TMDS_CNTL__VI = 0x4B6B; -constexpr unsigned int mmDIG1_TMDS_CONTROL0_FEEDBACK__VI = 0x4B6D; -constexpr unsigned int mmDIG1_TMDS_CONTROL_CHAR__VI = 0x4B6C; -constexpr unsigned int mmDIG1_TMDS_CTL0_1_GEN_CNTL__VI = 0x4B75; -constexpr unsigned int mmDIG1_TMDS_CTL2_3_GEN_CNTL__VI = 0x4B76; -constexpr unsigned int mmDIG1_TMDS_CTL_BITS__VI = 0x4B72; -constexpr unsigned int mmDIG1_TMDS_DCBALANCER_CONTROL__VI = 0x4B73; -constexpr unsigned int mmDIG1_TMDS_DEBUG__VI = 0x4B71; -constexpr unsigned int mmDIG1_TMDS_STEREOSYNC_CTL_SEL__VI = 0x4B6E; -constexpr unsigned int mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1__VI = 0x4B6F; -constexpr unsigned int mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3__VI = 0x4B70; -constexpr unsigned int mmDIG2_AFMT_60958_0__VI = 0x4C38; -constexpr unsigned int mmDIG2_AFMT_60958_1__VI = 0x4C39; -constexpr unsigned int mmDIG2_AFMT_60958_2__VI = 0x4C3F; -constexpr unsigned int mmDIG2_AFMT_AUDIO_CRC_CONTROL__VI = 0x4C3A; -constexpr unsigned int mmDIG2_AFMT_AUDIO_CRC_RESULT__VI = 0x4C40; -constexpr unsigned int mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL__VI = 0x4C46; -constexpr unsigned int mmDIG2_AFMT_AUDIO_INFO0__VI = 0x4C36; -constexpr unsigned int mmDIG2_AFMT_AUDIO_INFO1__VI = 0x4C37; -constexpr unsigned int mmDIG2_AFMT_AUDIO_PACKET_CONTROL__VI = 0x4C42; -constexpr unsigned int mmDIG2_AFMT_AUDIO_PACKET_CONTROL2__VI = 0x4C14; -constexpr unsigned int mmDIG2_AFMT_AUDIO_SRC_CONTROL__VI = 0x4C45; -constexpr unsigned int mmDIG2_AFMT_AVI_INFO0__VI = 0x4C1E; -constexpr unsigned int mmDIG2_AFMT_AVI_INFO1__VI = 0x4C1F; -constexpr unsigned int mmDIG2_AFMT_AVI_INFO2__VI = 0x4C20; -constexpr unsigned int mmDIG2_AFMT_AVI_INFO3__VI = 0x4C21; -constexpr unsigned int mmDIG2_AFMT_GENERIC_0__VI = 0x4C25; -constexpr unsigned int mmDIG2_AFMT_GENERIC_1__VI = 0x4C26; -constexpr unsigned int mmDIG2_AFMT_GENERIC_2__VI = 0x4C27; -constexpr unsigned int mmDIG2_AFMT_GENERIC_3__VI = 0x4C28; -constexpr unsigned int mmDIG2_AFMT_GENERIC_4__VI = 0x4C29; -constexpr unsigned int mmDIG2_AFMT_GENERIC_5__VI = 0x4C2A; -constexpr unsigned int mmDIG2_AFMT_GENERIC_6__VI = 0x4C2B; -constexpr unsigned int mmDIG2_AFMT_GENERIC_7__VI = 0x4C2C; -constexpr unsigned int mmDIG2_AFMT_GENERIC_HDR__VI = 0x4C24; -constexpr unsigned int mmDIG2_AFMT_INFOFRAME_CONTROL0__VI = 0x4C44; -constexpr unsigned int mmDIG2_AFMT_ISRC1_0__VI = 0x4C15; -constexpr unsigned int mmDIG2_AFMT_ISRC1_1__VI = 0x4C16; -constexpr unsigned int mmDIG2_AFMT_ISRC1_2__VI = 0x4C17; -constexpr unsigned int mmDIG2_AFMT_ISRC1_3__VI = 0x4C18; -constexpr unsigned int mmDIG2_AFMT_ISRC1_4__VI = 0x4C19; -constexpr unsigned int mmDIG2_AFMT_ISRC2_0__VI = 0x4C1A; -constexpr unsigned int mmDIG2_AFMT_ISRC2_1__VI = 0x4C1B; -constexpr unsigned int mmDIG2_AFMT_ISRC2_2__VI = 0x4C1C; -constexpr unsigned int mmDIG2_AFMT_ISRC2_3__VI = 0x4C1D; -constexpr unsigned int mmDIG2_AFMT_MPEG_INFO0__VI = 0x4C22; -constexpr unsigned int mmDIG2_AFMT_MPEG_INFO1__VI = 0x4C23; -constexpr unsigned int mmDIG2_AFMT_RAMP_CONTROL0__VI = 0x4C3B; -constexpr unsigned int mmDIG2_AFMT_RAMP_CONTROL1__VI = 0x4C3C; -constexpr unsigned int mmDIG2_AFMT_RAMP_CONTROL2__VI = 0x4C3D; -constexpr unsigned int mmDIG2_AFMT_RAMP_CONTROL3__VI = 0x4C3E; -constexpr unsigned int mmDIG2_AFMT_STATUS__VI = 0x4C41; -constexpr unsigned int mmDIG2_AFMT_VBI_PACKET_CONTROL__VI = 0x4C43; -constexpr unsigned int mmDIG2_DIG_BE_CNTL__VI = 0x4C47; -constexpr unsigned int mmDIG2_DIG_BE_EN_CNTL__VI = 0x4C48; -constexpr unsigned int mmDIG2_DIG_CLOCK_PATTERN__VI = 0x4C03; -constexpr unsigned int mmDIG2_DIG_DISPCLK_SWITCH_CNTL__VI = 0x4C07; -constexpr unsigned int mmDIG2_DIG_DISPCLK_SWITCH_STATUS__VI = 0x4C08; -constexpr unsigned int mmDIG2_DIG_FE_CNTL__VI = 0x4C00; -constexpr unsigned int mmDIG2_DIG_FE_TEST_DEBUG_DATA__VI = 0x4C7D; -constexpr unsigned int mmDIG2_DIG_FE_TEST_DEBUG_INDEX__VI = 0x4C7C; -constexpr unsigned int mmDIG2_DIG_FIFO_STATUS__VI = 0x4C06; -constexpr unsigned int mmDIG2_DIG_LANE_ENABLE__VI = 0x4C79; -constexpr unsigned int mmDIG2_DIG_OUTPUT_CRC_CNTL__VI = 0x4C01; -constexpr unsigned int mmDIG2_DIG_OUTPUT_CRC_RESULT__VI = 0x4C02; -constexpr unsigned int mmDIG2_DIG_RANDOM_PATTERN_SEED__VI = 0x4C05; -constexpr unsigned int mmDIG2_DIG_TEST_DEBUG_DATA__VI = 0x4C7B; -constexpr unsigned int mmDIG2_DIG_TEST_DEBUG_INDEX__VI = 0x4C7A; -constexpr unsigned int mmDIG2_DIG_TEST_PATTERN__VI = 0x4C04; -constexpr unsigned int mmDIG2_HDMI_ACR_32_0__VI = 0x4C2E; -constexpr unsigned int mmDIG2_HDMI_ACR_32_1__VI = 0x4C2F; -constexpr unsigned int mmDIG2_HDMI_ACR_44_0__VI = 0x4C30; -constexpr unsigned int mmDIG2_HDMI_ACR_44_1__VI = 0x4C31; -constexpr unsigned int mmDIG2_HDMI_ACR_48_0__VI = 0x4C32; -constexpr unsigned int mmDIG2_HDMI_ACR_48_1__VI = 0x4C33; -constexpr unsigned int mmDIG2_HDMI_ACR_PACKET_CONTROL__VI = 0x4C0C; -constexpr unsigned int mmDIG2_HDMI_ACR_STATUS_0__VI = 0x4C34; -constexpr unsigned int mmDIG2_HDMI_ACR_STATUS_1__VI = 0x4C35; -constexpr unsigned int mmDIG2_HDMI_AUDIO_PACKET_CONTROL__VI = 0x4C0B; -constexpr unsigned int mmDIG2_HDMI_CONTROL__VI = 0x4C09; -constexpr unsigned int mmDIG2_HDMI_GC__VI = 0x4C13; -constexpr unsigned int mmDIG2_HDMI_GENERIC_PACKET_CONTROL0__VI = 0x4C10; -constexpr unsigned int mmDIG2_HDMI_GENERIC_PACKET_CONTROL1__VI = 0x4C2D; -constexpr unsigned int mmDIG2_HDMI_INFOFRAME_CONTROL0__VI = 0x4C0E; -constexpr unsigned int mmDIG2_HDMI_INFOFRAME_CONTROL1__VI = 0x4C0F; -constexpr unsigned int mmDIG2_HDMI_STATUS__VI = 0x4C0A; -constexpr unsigned int mmDIG2_HDMI_VBI_PACKET_CONTROL__VI = 0x4C0D; -constexpr unsigned int mmDIG2_LVDS_DATA_CNTL__VI = 0x4C78; -constexpr unsigned int mmDIG2_TMDS_CNTL__VI = 0x4C6B; -constexpr unsigned int mmDIG2_TMDS_CONTROL0_FEEDBACK__VI = 0x4C6D; -constexpr unsigned int mmDIG2_TMDS_CONTROL_CHAR__VI = 0x4C6C; -constexpr unsigned int mmDIG2_TMDS_CTL0_1_GEN_CNTL__VI = 0x4C75; -constexpr unsigned int mmDIG2_TMDS_CTL2_3_GEN_CNTL__VI = 0x4C76; -constexpr unsigned int mmDIG2_TMDS_CTL_BITS__VI = 0x4C72; -constexpr unsigned int mmDIG2_TMDS_DCBALANCER_CONTROL__VI = 0x4C73; -constexpr unsigned int mmDIG2_TMDS_DEBUG__VI = 0x4C71; -constexpr unsigned int mmDIG2_TMDS_STEREOSYNC_CTL_SEL__VI = 0x4C6E; -constexpr unsigned int mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1__VI = 0x4C6F; -constexpr unsigned int mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3__VI = 0x4C70; -constexpr unsigned int mmDIG3_AFMT_60958_0__VI = 0x4D38; -constexpr unsigned int mmDIG3_AFMT_60958_1__VI = 0x4D39; -constexpr unsigned int mmDIG3_AFMT_60958_2__VI = 0x4D3F; -constexpr unsigned int mmDIG3_AFMT_AUDIO_CRC_CONTROL__VI = 0x4D3A; -constexpr unsigned int mmDIG3_AFMT_AUDIO_CRC_RESULT__VI = 0x4D40; -constexpr unsigned int mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL__VI = 0x4D46; -constexpr unsigned int mmDIG3_AFMT_AUDIO_INFO0__VI = 0x4D36; -constexpr unsigned int mmDIG3_AFMT_AUDIO_INFO1__VI = 0x4D37; -constexpr unsigned int mmDIG3_AFMT_AUDIO_PACKET_CONTROL__VI = 0x4D42; -constexpr unsigned int mmDIG3_AFMT_AUDIO_PACKET_CONTROL2__VI = 0x4D14; -constexpr unsigned int mmDIG3_AFMT_AUDIO_SRC_CONTROL__VI = 0x4D45; -constexpr unsigned int mmDIG3_AFMT_AVI_INFO0__VI = 0x4D1E; -constexpr unsigned int mmDIG3_AFMT_AVI_INFO1__VI = 0x4D1F; -constexpr unsigned int mmDIG3_AFMT_AVI_INFO2__VI = 0x4D20; -constexpr unsigned int mmDIG3_AFMT_AVI_INFO3__VI = 0x4D21; -constexpr unsigned int mmDIG3_AFMT_GENERIC_0__VI = 0x4D25; -constexpr unsigned int mmDIG3_AFMT_GENERIC_1__VI = 0x4D26; -constexpr unsigned int mmDIG3_AFMT_GENERIC_2__VI = 0x4D27; -constexpr unsigned int mmDIG3_AFMT_GENERIC_3__VI = 0x4D28; -constexpr unsigned int mmDIG3_AFMT_GENERIC_4__VI = 0x4D29; -constexpr unsigned int mmDIG3_AFMT_GENERIC_5__VI = 0x4D2A; -constexpr unsigned int mmDIG3_AFMT_GENERIC_6__VI = 0x4D2B; -constexpr unsigned int mmDIG3_AFMT_GENERIC_7__VI = 0x4D2C; -constexpr unsigned int mmDIG3_AFMT_GENERIC_HDR__VI = 0x4D24; -constexpr unsigned int mmDIG3_AFMT_INFOFRAME_CONTROL0__VI = 0x4D44; -constexpr unsigned int mmDIG3_AFMT_ISRC1_0__VI = 0x4D15; -constexpr unsigned int mmDIG3_AFMT_ISRC1_1__VI = 0x4D16; -constexpr unsigned int mmDIG3_AFMT_ISRC1_2__VI = 0x4D17; -constexpr unsigned int mmDIG3_AFMT_ISRC1_3__VI = 0x4D18; -constexpr unsigned int mmDIG3_AFMT_ISRC1_4__VI = 0x4D19; -constexpr unsigned int mmDIG3_AFMT_ISRC2_0__VI = 0x4D1A; -constexpr unsigned int mmDIG3_AFMT_ISRC2_1__VI = 0x4D1B; -constexpr unsigned int mmDIG3_AFMT_ISRC2_2__VI = 0x4D1C; -constexpr unsigned int mmDIG3_AFMT_ISRC2_3__VI = 0x4D1D; -constexpr unsigned int mmDIG3_AFMT_MPEG_INFO0__VI = 0x4D22; -constexpr unsigned int mmDIG3_AFMT_MPEG_INFO1__VI = 0x4D23; -constexpr unsigned int mmDIG3_AFMT_RAMP_CONTROL0__VI = 0x4D3B; -constexpr unsigned int mmDIG3_AFMT_RAMP_CONTROL1__VI = 0x4D3C; -constexpr unsigned int mmDIG3_AFMT_RAMP_CONTROL2__VI = 0x4D3D; -constexpr unsigned int mmDIG3_AFMT_RAMP_CONTROL3__VI = 0x4D3E; -constexpr unsigned int mmDIG3_AFMT_STATUS__VI = 0x4D41; -constexpr unsigned int mmDIG3_AFMT_VBI_PACKET_CONTROL__VI = 0x4D43; -constexpr unsigned int mmDIG3_DIG_BE_CNTL__VI = 0x4D47; -constexpr unsigned int mmDIG3_DIG_BE_EN_CNTL__VI = 0x4D48; -constexpr unsigned int mmDIG3_DIG_CLOCK_PATTERN__VI = 0x4D03; -constexpr unsigned int mmDIG3_DIG_DISPCLK_SWITCH_CNTL__VI = 0x4D07; -constexpr unsigned int mmDIG3_DIG_DISPCLK_SWITCH_STATUS__VI = 0x4D08; -constexpr unsigned int mmDIG3_DIG_FE_CNTL__VI = 0x4D00; -constexpr unsigned int mmDIG3_DIG_FE_TEST_DEBUG_DATA__VI = 0x4D7D; -constexpr unsigned int mmDIG3_DIG_FE_TEST_DEBUG_INDEX__VI = 0x4D7C; -constexpr unsigned int mmDIG3_DIG_FIFO_STATUS__VI = 0x4D06; -constexpr unsigned int mmDIG3_DIG_LANE_ENABLE__VI = 0x4D79; -constexpr unsigned int mmDIG3_DIG_OUTPUT_CRC_CNTL__VI = 0x4D01; -constexpr unsigned int mmDIG3_DIG_OUTPUT_CRC_RESULT__VI = 0x4D02; -constexpr unsigned int mmDIG3_DIG_RANDOM_PATTERN_SEED__VI = 0x4D05; -constexpr unsigned int mmDIG3_DIG_TEST_DEBUG_DATA__VI = 0x4D7B; -constexpr unsigned int mmDIG3_DIG_TEST_DEBUG_INDEX__VI = 0x4D7A; -constexpr unsigned int mmDIG3_DIG_TEST_PATTERN__VI = 0x4D04; -constexpr unsigned int mmDIG3_HDMI_ACR_32_0__VI = 0x4D2E; -constexpr unsigned int mmDIG3_HDMI_ACR_32_1__VI = 0x4D2F; -constexpr unsigned int mmDIG3_HDMI_ACR_44_0__VI = 0x4D30; -constexpr unsigned int mmDIG3_HDMI_ACR_44_1__VI = 0x4D31; -constexpr unsigned int mmDIG3_HDMI_ACR_48_0__VI = 0x4D32; -constexpr unsigned int mmDIG3_HDMI_ACR_48_1__VI = 0x4D33; -constexpr unsigned int mmDIG3_HDMI_ACR_PACKET_CONTROL__VI = 0x4D0C; -constexpr unsigned int mmDIG3_HDMI_ACR_STATUS_0__VI = 0x4D34; -constexpr unsigned int mmDIG3_HDMI_ACR_STATUS_1__VI = 0x4D35; -constexpr unsigned int mmDIG3_HDMI_AUDIO_PACKET_CONTROL__VI = 0x4D0B; -constexpr unsigned int mmDIG3_HDMI_CONTROL__VI = 0x4D09; -constexpr unsigned int mmDIG3_HDMI_GC__VI = 0x4D13; -constexpr unsigned int mmDIG3_HDMI_GENERIC_PACKET_CONTROL0__VI = 0x4D10; -constexpr unsigned int mmDIG3_HDMI_GENERIC_PACKET_CONTROL1__VI = 0x4D2D; -constexpr unsigned int mmDIG3_HDMI_INFOFRAME_CONTROL0__VI = 0x4D0E; -constexpr unsigned int mmDIG3_HDMI_INFOFRAME_CONTROL1__VI = 0x4D0F; -constexpr unsigned int mmDIG3_HDMI_STATUS__VI = 0x4D0A; -constexpr unsigned int mmDIG3_HDMI_VBI_PACKET_CONTROL__VI = 0x4D0D; -constexpr unsigned int mmDIG3_LVDS_DATA_CNTL__VI = 0x4D78; -constexpr unsigned int mmDIG3_TMDS_CNTL__VI = 0x4D6B; -constexpr unsigned int mmDIG3_TMDS_CONTROL0_FEEDBACK__VI = 0x4D6D; -constexpr unsigned int mmDIG3_TMDS_CONTROL_CHAR__VI = 0x4D6C; -constexpr unsigned int mmDIG3_TMDS_CTL0_1_GEN_CNTL__VI = 0x4D75; -constexpr unsigned int mmDIG3_TMDS_CTL2_3_GEN_CNTL__VI = 0x4D76; -constexpr unsigned int mmDIG3_TMDS_CTL_BITS__VI = 0x4D72; -constexpr unsigned int mmDIG3_TMDS_DCBALANCER_CONTROL__VI = 0x4D73; -constexpr unsigned int mmDIG3_TMDS_DEBUG__VI = 0x4D71; -constexpr unsigned int mmDIG3_TMDS_STEREOSYNC_CTL_SEL__VI = 0x4D6E; -constexpr unsigned int mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1__VI = 0x4D6F; -constexpr unsigned int mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3__VI = 0x4D70; -constexpr unsigned int mmDIG4_AFMT_60958_0__VI = 0x4E38; -constexpr unsigned int mmDIG4_AFMT_60958_1__VI = 0x4E39; -constexpr unsigned int mmDIG4_AFMT_60958_2__VI = 0x4E3F; -constexpr unsigned int mmDIG4_AFMT_AUDIO_CRC_CONTROL__VI = 0x4E3A; -constexpr unsigned int mmDIG4_AFMT_AUDIO_CRC_RESULT__VI = 0x4E40; -constexpr unsigned int mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL__VI = 0x4E46; -constexpr unsigned int mmDIG4_AFMT_AUDIO_INFO0__VI = 0x4E36; -constexpr unsigned int mmDIG4_AFMT_AUDIO_INFO1__VI = 0x4E37; -constexpr unsigned int mmDIG4_AFMT_AUDIO_PACKET_CONTROL__VI = 0x4E42; -constexpr unsigned int mmDIG4_AFMT_AUDIO_PACKET_CONTROL2__VI = 0x4E14; -constexpr unsigned int mmDIG4_AFMT_AUDIO_SRC_CONTROL__VI = 0x4E45; -constexpr unsigned int mmDIG4_AFMT_AVI_INFO0__VI = 0x4E1E; -constexpr unsigned int mmDIG4_AFMT_AVI_INFO1__VI = 0x4E1F; -constexpr unsigned int mmDIG4_AFMT_AVI_INFO2__VI = 0x4E20; -constexpr unsigned int mmDIG4_AFMT_AVI_INFO3__VI = 0x4E21; -constexpr unsigned int mmDIG4_AFMT_GENERIC_0__VI = 0x4E25; -constexpr unsigned int mmDIG4_AFMT_GENERIC_1__VI = 0x4E26; -constexpr unsigned int mmDIG4_AFMT_GENERIC_2__VI = 0x4E27; -constexpr unsigned int mmDIG4_AFMT_GENERIC_3__VI = 0x4E28; -constexpr unsigned int mmDIG4_AFMT_GENERIC_4__VI = 0x4E29; -constexpr unsigned int mmDIG4_AFMT_GENERIC_5__VI = 0x4E2A; -constexpr unsigned int mmDIG4_AFMT_GENERIC_6__VI = 0x4E2B; -constexpr unsigned int mmDIG4_AFMT_GENERIC_7__VI = 0x4E2C; -constexpr unsigned int mmDIG4_AFMT_GENERIC_HDR__VI = 0x4E24; -constexpr unsigned int mmDIG4_AFMT_INFOFRAME_CONTROL0__VI = 0x4E44; -constexpr unsigned int mmDIG4_AFMT_ISRC1_0__VI = 0x4E15; -constexpr unsigned int mmDIG4_AFMT_ISRC1_1__VI = 0x4E16; -constexpr unsigned int mmDIG4_AFMT_ISRC1_2__VI = 0x4E17; -constexpr unsigned int mmDIG4_AFMT_ISRC1_3__VI = 0x4E18; -constexpr unsigned int mmDIG4_AFMT_ISRC1_4__VI = 0x4E19; -constexpr unsigned int mmDIG4_AFMT_ISRC2_0__VI = 0x4E1A; -constexpr unsigned int mmDIG4_AFMT_ISRC2_1__VI = 0x4E1B; -constexpr unsigned int mmDIG4_AFMT_ISRC2_2__VI = 0x4E1C; -constexpr unsigned int mmDIG4_AFMT_ISRC2_3__VI = 0x4E1D; -constexpr unsigned int mmDIG4_AFMT_MPEG_INFO0__VI = 0x4E22; -constexpr unsigned int mmDIG4_AFMT_MPEG_INFO1__VI = 0x4E23; -constexpr unsigned int mmDIG4_AFMT_RAMP_CONTROL0__VI = 0x4E3B; -constexpr unsigned int mmDIG4_AFMT_RAMP_CONTROL1__VI = 0x4E3C; -constexpr unsigned int mmDIG4_AFMT_RAMP_CONTROL2__VI = 0x4E3D; -constexpr unsigned int mmDIG4_AFMT_RAMP_CONTROL3__VI = 0x4E3E; -constexpr unsigned int mmDIG4_AFMT_STATUS__VI = 0x4E41; -constexpr unsigned int mmDIG4_AFMT_VBI_PACKET_CONTROL__VI = 0x4E43; -constexpr unsigned int mmDIG4_DIG_BE_CNTL__VI = 0x4E47; -constexpr unsigned int mmDIG4_DIG_BE_EN_CNTL__VI = 0x4E48; -constexpr unsigned int mmDIG4_DIG_CLOCK_PATTERN__VI = 0x4E03; -constexpr unsigned int mmDIG4_DIG_DISPCLK_SWITCH_CNTL__VI = 0x4E07; -constexpr unsigned int mmDIG4_DIG_DISPCLK_SWITCH_STATUS__VI = 0x4E08; -constexpr unsigned int mmDIG4_DIG_FE_CNTL__VI = 0x4E00; -constexpr unsigned int mmDIG4_DIG_FE_TEST_DEBUG_DATA__VI = 0x4E7D; -constexpr unsigned int mmDIG4_DIG_FE_TEST_DEBUG_INDEX__VI = 0x4E7C; -constexpr unsigned int mmDIG4_DIG_FIFO_STATUS__VI = 0x4E06; -constexpr unsigned int mmDIG4_DIG_LANE_ENABLE__VI = 0x4E79; -constexpr unsigned int mmDIG4_DIG_OUTPUT_CRC_CNTL__VI = 0x4E01; -constexpr unsigned int mmDIG4_DIG_OUTPUT_CRC_RESULT__VI = 0x4E02; -constexpr unsigned int mmDIG4_DIG_RANDOM_PATTERN_SEED__VI = 0x4E05; -constexpr unsigned int mmDIG4_DIG_TEST_DEBUG_DATA__VI = 0x4E7B; -constexpr unsigned int mmDIG4_DIG_TEST_DEBUG_INDEX__VI = 0x4E7A; -constexpr unsigned int mmDIG4_DIG_TEST_PATTERN__VI = 0x4E04; -constexpr unsigned int mmDIG4_HDMI_ACR_32_0__VI = 0x4E2E; -constexpr unsigned int mmDIG4_HDMI_ACR_32_1__VI = 0x4E2F; -constexpr unsigned int mmDIG4_HDMI_ACR_44_0__VI = 0x4E30; -constexpr unsigned int mmDIG4_HDMI_ACR_44_1__VI = 0x4E31; -constexpr unsigned int mmDIG4_HDMI_ACR_48_0__VI = 0x4E32; -constexpr unsigned int mmDIG4_HDMI_ACR_48_1__VI = 0x4E33; -constexpr unsigned int mmDIG4_HDMI_ACR_PACKET_CONTROL__VI = 0x4E0C; -constexpr unsigned int mmDIG4_HDMI_ACR_STATUS_0__VI = 0x4E34; -constexpr unsigned int mmDIG4_HDMI_ACR_STATUS_1__VI = 0x4E35; -constexpr unsigned int mmDIG4_HDMI_AUDIO_PACKET_CONTROL__VI = 0x4E0B; -constexpr unsigned int mmDIG4_HDMI_CONTROL__VI = 0x4E09; -constexpr unsigned int mmDIG4_HDMI_GC__VI = 0x4E13; -constexpr unsigned int mmDIG4_HDMI_GENERIC_PACKET_CONTROL0__VI = 0x4E10; -constexpr unsigned int mmDIG4_HDMI_GENERIC_PACKET_CONTROL1__VI = 0x4E2D; -constexpr unsigned int mmDIG4_HDMI_INFOFRAME_CONTROL0__VI = 0x4E0E; -constexpr unsigned int mmDIG4_HDMI_INFOFRAME_CONTROL1__VI = 0x4E0F; -constexpr unsigned int mmDIG4_HDMI_STATUS__VI = 0x4E0A; -constexpr unsigned int mmDIG4_HDMI_VBI_PACKET_CONTROL__VI = 0x4E0D; -constexpr unsigned int mmDIG4_LVDS_DATA_CNTL__VI = 0x4E78; -constexpr unsigned int mmDIG4_TMDS_CNTL__VI = 0x4E6B; -constexpr unsigned int mmDIG4_TMDS_CONTROL0_FEEDBACK__VI = 0x4E6D; -constexpr unsigned int mmDIG4_TMDS_CONTROL_CHAR__VI = 0x4E6C; -constexpr unsigned int mmDIG4_TMDS_CTL0_1_GEN_CNTL__VI = 0x4E75; -constexpr unsigned int mmDIG4_TMDS_CTL2_3_GEN_CNTL__VI = 0x4E76; -constexpr unsigned int mmDIG4_TMDS_CTL_BITS__VI = 0x4E72; -constexpr unsigned int mmDIG4_TMDS_DCBALANCER_CONTROL__VI = 0x4E73; -constexpr unsigned int mmDIG4_TMDS_DEBUG__VI = 0x4E71; -constexpr unsigned int mmDIG4_TMDS_STEREOSYNC_CTL_SEL__VI = 0x4E6E; -constexpr unsigned int mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1__VI = 0x4E6F; -constexpr unsigned int mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3__VI = 0x4E70; -constexpr unsigned int mmDIG5_AFMT_60958_0__VI = 0x4F38; -constexpr unsigned int mmDIG5_AFMT_60958_1__VI = 0x4F39; -constexpr unsigned int mmDIG5_AFMT_60958_2__VI = 0x4F3F; -constexpr unsigned int mmDIG5_AFMT_AUDIO_CRC_CONTROL__VI = 0x4F3A; -constexpr unsigned int mmDIG5_AFMT_AUDIO_CRC_RESULT__VI = 0x4F40; -constexpr unsigned int mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL__VI = 0x4F46; -constexpr unsigned int mmDIG5_AFMT_AUDIO_INFO0__VI = 0x4F36; -constexpr unsigned int mmDIG5_AFMT_AUDIO_INFO1__VI = 0x4F37; -constexpr unsigned int mmDIG5_AFMT_AUDIO_PACKET_CONTROL__VI = 0x4F42; -constexpr unsigned int mmDIG5_AFMT_AUDIO_PACKET_CONTROL2__VI = 0x4F14; -constexpr unsigned int mmDIG5_AFMT_AUDIO_SRC_CONTROL__VI = 0x4F45; -constexpr unsigned int mmDIG5_AFMT_AVI_INFO0__VI = 0x4F1E; -constexpr unsigned int mmDIG5_AFMT_AVI_INFO1__VI = 0x4F1F; -constexpr unsigned int mmDIG5_AFMT_AVI_INFO2__VI = 0x4F20; -constexpr unsigned int mmDIG5_AFMT_AVI_INFO3__VI = 0x4F21; -constexpr unsigned int mmDIG5_AFMT_GENERIC_0__VI = 0x4F25; -constexpr unsigned int mmDIG5_AFMT_GENERIC_1__VI = 0x4F26; -constexpr unsigned int mmDIG5_AFMT_GENERIC_2__VI = 0x4F27; -constexpr unsigned int mmDIG5_AFMT_GENERIC_3__VI = 0x4F28; -constexpr unsigned int mmDIG5_AFMT_GENERIC_4__VI = 0x4F29; -constexpr unsigned int mmDIG5_AFMT_GENERIC_5__VI = 0x4F2A; -constexpr unsigned int mmDIG5_AFMT_GENERIC_6__VI = 0x4F2B; -constexpr unsigned int mmDIG5_AFMT_GENERIC_7__VI = 0x4F2C; -constexpr unsigned int mmDIG5_AFMT_GENERIC_HDR__VI = 0x4F24; -constexpr unsigned int mmDIG5_AFMT_INFOFRAME_CONTROL0__VI = 0x4F44; -constexpr unsigned int mmDIG5_AFMT_ISRC1_0__VI = 0x4F15; -constexpr unsigned int mmDIG5_AFMT_ISRC1_1__VI = 0x4F16; -constexpr unsigned int mmDIG5_AFMT_ISRC1_2__VI = 0x4F17; -constexpr unsigned int mmDIG5_AFMT_ISRC1_3__VI = 0x4F18; -constexpr unsigned int mmDIG5_AFMT_ISRC1_4__VI = 0x4F19; -constexpr unsigned int mmDIG5_AFMT_ISRC2_0__VI = 0x4F1A; -constexpr unsigned int mmDIG5_AFMT_ISRC2_1__VI = 0x4F1B; -constexpr unsigned int mmDIG5_AFMT_ISRC2_2__VI = 0x4F1C; -constexpr unsigned int mmDIG5_AFMT_ISRC2_3__VI = 0x4F1D; -constexpr unsigned int mmDIG5_AFMT_MPEG_INFO0__VI = 0x4F22; -constexpr unsigned int mmDIG5_AFMT_MPEG_INFO1__VI = 0x4F23; -constexpr unsigned int mmDIG5_AFMT_RAMP_CONTROL0__VI = 0x4F3B; -constexpr unsigned int mmDIG5_AFMT_RAMP_CONTROL1__VI = 0x4F3C; -constexpr unsigned int mmDIG5_AFMT_RAMP_CONTROL2__VI = 0x4F3D; -constexpr unsigned int mmDIG5_AFMT_RAMP_CONTROL3__VI = 0x4F3E; -constexpr unsigned int mmDIG5_AFMT_STATUS__VI = 0x4F41; -constexpr unsigned int mmDIG5_AFMT_VBI_PACKET_CONTROL__VI = 0x4F43; -constexpr unsigned int mmDIG5_DIG_BE_CNTL__VI = 0x4F47; -constexpr unsigned int mmDIG5_DIG_BE_EN_CNTL__VI = 0x4F48; -constexpr unsigned int mmDIG5_DIG_CLOCK_PATTERN__VI = 0x4F03; -constexpr unsigned int mmDIG5_DIG_DISPCLK_SWITCH_CNTL__VI = 0x4F07; -constexpr unsigned int mmDIG5_DIG_DISPCLK_SWITCH_STATUS__VI = 0x4F08; -constexpr unsigned int mmDIG5_DIG_FE_CNTL__VI = 0x4F00; -constexpr unsigned int mmDIG5_DIG_FE_TEST_DEBUG_DATA__VI = 0x4F7D; -constexpr unsigned int mmDIG5_DIG_FE_TEST_DEBUG_INDEX__VI = 0x4F7C; -constexpr unsigned int mmDIG5_DIG_FIFO_STATUS__VI = 0x4F06; -constexpr unsigned int mmDIG5_DIG_LANE_ENABLE__VI = 0x4F79; -constexpr unsigned int mmDIG5_DIG_OUTPUT_CRC_CNTL__VI = 0x4F01; -constexpr unsigned int mmDIG5_DIG_OUTPUT_CRC_RESULT__VI = 0x4F02; -constexpr unsigned int mmDIG5_DIG_RANDOM_PATTERN_SEED__VI = 0x4F05; -constexpr unsigned int mmDIG5_DIG_TEST_DEBUG_DATA__VI = 0x4F7B; -constexpr unsigned int mmDIG5_DIG_TEST_DEBUG_INDEX__VI = 0x4F7A; -constexpr unsigned int mmDIG5_DIG_TEST_PATTERN__VI = 0x4F04; -constexpr unsigned int mmDIG5_HDMI_ACR_32_0__VI = 0x4F2E; -constexpr unsigned int mmDIG5_HDMI_ACR_32_1__VI = 0x4F2F; -constexpr unsigned int mmDIG5_HDMI_ACR_44_0__VI = 0x4F30; -constexpr unsigned int mmDIG5_HDMI_ACR_44_1__VI = 0x4F31; -constexpr unsigned int mmDIG5_HDMI_ACR_48_0__VI = 0x4F32; -constexpr unsigned int mmDIG5_HDMI_ACR_48_1__VI = 0x4F33; -constexpr unsigned int mmDIG5_HDMI_ACR_PACKET_CONTROL__VI = 0x4F0C; -constexpr unsigned int mmDIG5_HDMI_ACR_STATUS_0__VI = 0x4F34; -constexpr unsigned int mmDIG5_HDMI_ACR_STATUS_1__VI = 0x4F35; -constexpr unsigned int mmDIG5_HDMI_AUDIO_PACKET_CONTROL__VI = 0x4F0B; -constexpr unsigned int mmDIG5_HDMI_CONTROL__VI = 0x4F09; -constexpr unsigned int mmDIG5_HDMI_GC__VI = 0x4F13; -constexpr unsigned int mmDIG5_HDMI_GENERIC_PACKET_CONTROL0__VI = 0x4F10; -constexpr unsigned int mmDIG5_HDMI_GENERIC_PACKET_CONTROL1__VI = 0x4F2D; -constexpr unsigned int mmDIG5_HDMI_INFOFRAME_CONTROL0__VI = 0x4F0E; -constexpr unsigned int mmDIG5_HDMI_INFOFRAME_CONTROL1__VI = 0x4F0F; -constexpr unsigned int mmDIG5_HDMI_STATUS__VI = 0x4F0A; -constexpr unsigned int mmDIG5_HDMI_VBI_PACKET_CONTROL__VI = 0x4F0D; -constexpr unsigned int mmDIG5_LVDS_DATA_CNTL__VI = 0x4F78; -constexpr unsigned int mmDIG5_TMDS_CNTL__VI = 0x4F6B; -constexpr unsigned int mmDIG5_TMDS_CONTROL0_FEEDBACK__VI = 0x4F6D; -constexpr unsigned int mmDIG5_TMDS_CONTROL_CHAR__VI = 0x4F6C; -constexpr unsigned int mmDIG5_TMDS_CTL0_1_GEN_CNTL__VI = 0x4F75; -constexpr unsigned int mmDIG5_TMDS_CTL2_3_GEN_CNTL__VI = 0x4F76; -constexpr unsigned int mmDIG5_TMDS_CTL_BITS__VI = 0x4F72; -constexpr unsigned int mmDIG5_TMDS_DCBALANCER_CONTROL__VI = 0x4F73; -constexpr unsigned int mmDIG5_TMDS_DEBUG__VI = 0x4F71; -constexpr unsigned int mmDIG5_TMDS_STEREOSYNC_CTL_SEL__VI = 0x4F6E; -constexpr unsigned int mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1__VI = 0x4F6F; -constexpr unsigned int mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3__VI = 0x4F70; -constexpr unsigned int mmDIG6_AFMT_60958_0__VI = 0x5438; -constexpr unsigned int mmDIG6_AFMT_60958_1__VI = 0x5439; -constexpr unsigned int mmDIG6_AFMT_60958_2__VI = 0x543F; -constexpr unsigned int mmDIG6_AFMT_AUDIO_CRC_CONTROL__VI = 0x543A; -constexpr unsigned int mmDIG6_AFMT_AUDIO_CRC_RESULT__VI = 0x5440; -constexpr unsigned int mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL__VI = 0x5446; -constexpr unsigned int mmDIG6_AFMT_AUDIO_INFO0__VI = 0x5436; -constexpr unsigned int mmDIG6_AFMT_AUDIO_INFO1__VI = 0x5437; -constexpr unsigned int mmDIG6_AFMT_AUDIO_PACKET_CONTROL__VI = 0x5442; -constexpr unsigned int mmDIG6_AFMT_AUDIO_PACKET_CONTROL2__VI = 0x5414; -constexpr unsigned int mmDIG6_AFMT_AUDIO_SRC_CONTROL__VI = 0x5445; -constexpr unsigned int mmDIG6_AFMT_AVI_INFO0__VI = 0x541E; -constexpr unsigned int mmDIG6_AFMT_AVI_INFO1__VI = 0x541F; -constexpr unsigned int mmDIG6_AFMT_AVI_INFO2__VI = 0x5420; -constexpr unsigned int mmDIG6_AFMT_AVI_INFO3__VI = 0x5421; -constexpr unsigned int mmDIG6_AFMT_GENERIC_0__VI = 0x5425; -constexpr unsigned int mmDIG6_AFMT_GENERIC_1__VI = 0x5426; -constexpr unsigned int mmDIG6_AFMT_GENERIC_2__VI = 0x5427; -constexpr unsigned int mmDIG6_AFMT_GENERIC_3__VI = 0x5428; -constexpr unsigned int mmDIG6_AFMT_GENERIC_4__VI = 0x5429; -constexpr unsigned int mmDIG6_AFMT_GENERIC_5__VI = 0x542A; -constexpr unsigned int mmDIG6_AFMT_GENERIC_6__VI = 0x542B; -constexpr unsigned int mmDIG6_AFMT_GENERIC_7__VI = 0x542C; -constexpr unsigned int mmDIG6_AFMT_GENERIC_HDR__VI = 0x5424; -constexpr unsigned int mmDIG6_AFMT_INFOFRAME_CONTROL0__VI = 0x5444; -constexpr unsigned int mmDIG6_AFMT_ISRC1_0__VI = 0x5415; -constexpr unsigned int mmDIG6_AFMT_ISRC1_1__VI = 0x5416; -constexpr unsigned int mmDIG6_AFMT_ISRC1_2__VI = 0x5417; -constexpr unsigned int mmDIG6_AFMT_ISRC1_3__VI = 0x5418; -constexpr unsigned int mmDIG6_AFMT_ISRC1_4__VI = 0x5419; -constexpr unsigned int mmDIG6_AFMT_ISRC2_0__VI = 0x541A; -constexpr unsigned int mmDIG6_AFMT_ISRC2_1__VI = 0x541B; -constexpr unsigned int mmDIG6_AFMT_ISRC2_2__VI = 0x541C; -constexpr unsigned int mmDIG6_AFMT_ISRC2_3__VI = 0x541D; -constexpr unsigned int mmDIG6_AFMT_MPEG_INFO0__VI = 0x5422; -constexpr unsigned int mmDIG6_AFMT_MPEG_INFO1__VI = 0x5423; -constexpr unsigned int mmDIG6_AFMT_RAMP_CONTROL0__VI = 0x543B; -constexpr unsigned int mmDIG6_AFMT_RAMP_CONTROL1__VI = 0x543C; -constexpr unsigned int mmDIG6_AFMT_RAMP_CONTROL2__VI = 0x543D; -constexpr unsigned int mmDIG6_AFMT_RAMP_CONTROL3__VI = 0x543E; -constexpr unsigned int mmDIG6_AFMT_STATUS__VI = 0x5441; -constexpr unsigned int mmDIG6_AFMT_VBI_PACKET_CONTROL__VI = 0x5443; -constexpr unsigned int mmDIG6_DIG_BE_CNTL__VI = 0x5447; -constexpr unsigned int mmDIG6_DIG_BE_EN_CNTL__VI = 0x5448; -constexpr unsigned int mmDIG6_DIG_CLOCK_PATTERN__VI = 0x5403; -constexpr unsigned int mmDIG6_DIG_DISPCLK_SWITCH_CNTL__VI = 0x5407; -constexpr unsigned int mmDIG6_DIG_DISPCLK_SWITCH_STATUS__VI = 0x5408; -constexpr unsigned int mmDIG6_DIG_FE_CNTL__VI = 0x5400; -constexpr unsigned int mmDIG6_DIG_FE_TEST_DEBUG_DATA__VI = 0x547D; -constexpr unsigned int mmDIG6_DIG_FE_TEST_DEBUG_INDEX__VI = 0x547C; -constexpr unsigned int mmDIG6_DIG_FIFO_STATUS__VI = 0x5406; -constexpr unsigned int mmDIG6_DIG_LANE_ENABLE__VI = 0x5479; -constexpr unsigned int mmDIG6_DIG_OUTPUT_CRC_CNTL__VI = 0x5401; -constexpr unsigned int mmDIG6_DIG_OUTPUT_CRC_RESULT__VI = 0x5402; -constexpr unsigned int mmDIG6_DIG_RANDOM_PATTERN_SEED__VI = 0x5405; -constexpr unsigned int mmDIG6_DIG_TEST_DEBUG_DATA__VI = 0x547B; -constexpr unsigned int mmDIG6_DIG_TEST_DEBUG_INDEX__VI = 0x547A; -constexpr unsigned int mmDIG6_DIG_TEST_PATTERN__VI = 0x5404; -constexpr unsigned int mmDIG6_HDMI_ACR_32_0__VI = 0x542E; -constexpr unsigned int mmDIG6_HDMI_ACR_32_1__VI = 0x542F; -constexpr unsigned int mmDIG6_HDMI_ACR_44_0__VI = 0x5430; -constexpr unsigned int mmDIG6_HDMI_ACR_44_1__VI = 0x5431; -constexpr unsigned int mmDIG6_HDMI_ACR_48_0__VI = 0x5432; -constexpr unsigned int mmDIG6_HDMI_ACR_48_1__VI = 0x5433; -constexpr unsigned int mmDIG6_HDMI_ACR_PACKET_CONTROL__VI = 0x540C; -constexpr unsigned int mmDIG6_HDMI_ACR_STATUS_0__VI = 0x5434; -constexpr unsigned int mmDIG6_HDMI_ACR_STATUS_1__VI = 0x5435; -constexpr unsigned int mmDIG6_HDMI_AUDIO_PACKET_CONTROL__VI = 0x540B; -constexpr unsigned int mmDIG6_HDMI_CONTROL__VI = 0x5409; -constexpr unsigned int mmDIG6_HDMI_GC__VI = 0x5413; -constexpr unsigned int mmDIG6_HDMI_GENERIC_PACKET_CONTROL0__VI = 0x5410; -constexpr unsigned int mmDIG6_HDMI_GENERIC_PACKET_CONTROL1__VI = 0x542D; -constexpr unsigned int mmDIG6_HDMI_INFOFRAME_CONTROL0__VI = 0x540E; -constexpr unsigned int mmDIG6_HDMI_INFOFRAME_CONTROL1__VI = 0x540F; -constexpr unsigned int mmDIG6_HDMI_STATUS__VI = 0x540A; -constexpr unsigned int mmDIG6_HDMI_VBI_PACKET_CONTROL__VI = 0x540D; -constexpr unsigned int mmDIG6_LVDS_DATA_CNTL__VI = 0x5478; -constexpr unsigned int mmDIG6_TMDS_CNTL__VI = 0x546B; -constexpr unsigned int mmDIG6_TMDS_CONTROL0_FEEDBACK__VI = 0x546D; -constexpr unsigned int mmDIG6_TMDS_CONTROL_CHAR__VI = 0x546C; -constexpr unsigned int mmDIG6_TMDS_CTL0_1_GEN_CNTL__VI = 0x5475; -constexpr unsigned int mmDIG6_TMDS_CTL2_3_GEN_CNTL__VI = 0x5476; -constexpr unsigned int mmDIG6_TMDS_CTL_BITS__VI = 0x5472; -constexpr unsigned int mmDIG6_TMDS_DCBALANCER_CONTROL__VI = 0x5473; -constexpr unsigned int mmDIG6_TMDS_DEBUG__VI = 0x5471; -constexpr unsigned int mmDIG6_TMDS_STEREOSYNC_CTL_SEL__VI = 0x546E; -constexpr unsigned int mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1__VI = 0x546F; -constexpr unsigned int mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3__VI = 0x5470; -constexpr unsigned int mmDIG_BE_CNTL__VI = 0x4A47; -constexpr unsigned int mmDIG_BE_EN_CNTL__VI = 0x4A48; -constexpr unsigned int mmDIG_CLOCK_PATTERN__VI = 0x4A03; -constexpr unsigned int mmDIG_DISPCLK_SWITCH_CNTL__VI = 0x4A07; -constexpr unsigned int mmDIG_DISPCLK_SWITCH_STATUS__VI = 0x4A08; -constexpr unsigned int mmDIG_FE_CNTL__VI = 0x4A00; -constexpr unsigned int mmDIG_FE_TEST_DEBUG_DATA__VI = 0x4A7D; -constexpr unsigned int mmDIG_FE_TEST_DEBUG_INDEX__VI = 0x4A7C; -constexpr unsigned int mmDIG_FIFO_STATUS__VI = 0x4A06; -constexpr unsigned int mmDIG_LANE_ENABLE__VI = 0x4A79; -constexpr unsigned int mmDIG_OUTPUT_CRC_CNTL__VI = 0x4A01; -constexpr unsigned int mmDIG_OUTPUT_CRC_RESULT__VI = 0x4A02; -constexpr unsigned int mmDIG_RANDOM_PATTERN_SEED__VI = 0x4A05; -constexpr unsigned int mmDIG_SOFT_RESET__VI = 0x1872; -constexpr unsigned int mmDIG_TEST_DEBUG_DATA__VI = 0x4A7B; -constexpr unsigned int mmDIG_TEST_DEBUG_INDEX__VI = 0x4A7A; -constexpr unsigned int mmDIG_TEST_PATTERN__VI = 0x4A04; -constexpr unsigned int mmDISPCLK_CGTT_BLK_CTRL_REG__VI = 0x0135; -constexpr unsigned int mmDISPCLK_FREQ_CHANGE_CNTL__VI = 0x0131; -constexpr unsigned int mmDISPPLL_BG_CNTL__VI = 0x171E; -constexpr unsigned int mmDISP_INTERRUPT_STATUS__VI = 0x1857; -constexpr unsigned int mmDISP_INTERRUPT_STATUS_CONTINUE__VI = 0x1858; -constexpr unsigned int mmDISP_INTERRUPT_STATUS_CONTINUE2__VI = 0x1859; -constexpr unsigned int mmDISP_INTERRUPT_STATUS_CONTINUE3__VI = 0x185A; -constexpr unsigned int mmDISP_INTERRUPT_STATUS_CONTINUE4__VI = 0x185B; -constexpr unsigned int mmDISP_INTERRUPT_STATUS_CONTINUE5__VI = 0x185C; -constexpr unsigned int mmDISP_INTERRUPT_STATUS_CONTINUE6__VI = 0x185D; -constexpr unsigned int mmDISP_INTERRUPT_STATUS_CONTINUE7__VI = 0x185E; -constexpr unsigned int mmDISP_INTERRUPT_STATUS_CONTINUE8__VI = 0x185F; -constexpr unsigned int mmDISP_INTERRUPT_STATUS_CONTINUE9__VI = 0x1860; -constexpr unsigned int mmDMCU_DPRX_INTERRUPT_STATUS1__VI = 0x1634; -constexpr unsigned int mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__VI = 0x1635; -constexpr unsigned int mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI = 0x1636; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_STATUS1__VI = 0x1644; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_STATUS2__VI = 0x1645; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_STATUS3__VI = 0x1646; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_STATUS4__VI = 0x1647; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_STATUS5__VI = 0x1642; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__VI = 0x167C; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__VI = 0x167D; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__VI = 0x167E; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__VI = 0x167F; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__VI = 0x1633; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__VI = 0x1674; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__VI = 0x1675; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__VI = 0x1676; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__VI = 0x1677; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__VI = 0x1643; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI = 0x1678; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__VI = 0x1679; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__VI = 0x167A; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__VI = 0x167B; -constexpr unsigned int mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__VI = 0x1673; -constexpr unsigned int mmDMCU_SMU_INTERRUPT_CNTL__VI = 0x012C; -constexpr unsigned int mmDMCU_SS_INTERRUPT_CNTL_STATUS__VI = 0x1613; -constexpr unsigned int mmDMCU_UC_CLK_GATING_CNTL__VI = 0x161B; -constexpr unsigned int mmDMIF_ADDR_CALC__VI = 0x0303; -constexpr unsigned int mmDMIF_ADDR_CONFIG__VI = 0x02F5; -constexpr unsigned int mmDMIF_PG0_DPG_HW_DEBUG_11__VI = 0x1B3D; -constexpr unsigned int mmDMIF_PG0_DPG_HW_DEBUG_A__VI = 0x1B3B; -constexpr unsigned int mmDMIF_PG0_DPG_HW_DEBUG_B__VI = 0x1B3C; -constexpr unsigned int mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1__VI = 0x1B30; -constexpr unsigned int mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2__VI = 0x1B31; -constexpr unsigned int mmDMIF_PG0_DPG_PIPE_DPM_CONTROL__VI = 0x1B34; -constexpr unsigned int mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI = 0x1B36; -constexpr unsigned int mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL__VI = 0x1B35; -constexpr unsigned int mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI = 0x1B37; -constexpr unsigned int mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL__VI = 0x1B33; -constexpr unsigned int mmDMIF_PG0_DPG_REPEATER_PROGRAM__VI = 0x1B3A; -constexpr unsigned int mmDMIF_PG0_DPG_TEST_DEBUG_DATA__VI = 0x1B39; -constexpr unsigned int mmDMIF_PG0_DPG_TEST_DEBUG_INDEX__VI = 0x1B38; -constexpr unsigned int mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL__VI = 0x1B32; -constexpr unsigned int mmDMIF_PG1_DPG_HW_DEBUG_11__VI = 0x1D3D; -constexpr unsigned int mmDMIF_PG1_DPG_HW_DEBUG_A__VI = 0x1D3B; -constexpr unsigned int mmDMIF_PG1_DPG_HW_DEBUG_B__VI = 0x1D3C; -constexpr unsigned int mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1__VI = 0x1D30; -constexpr unsigned int mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2__VI = 0x1D31; -constexpr unsigned int mmDMIF_PG1_DPG_PIPE_DPM_CONTROL__VI = 0x1D34; -constexpr unsigned int mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI = 0x1D36; -constexpr unsigned int mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL__VI = 0x1D35; -constexpr unsigned int mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI = 0x1D37; -constexpr unsigned int mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL__VI = 0x1D33; -constexpr unsigned int mmDMIF_PG1_DPG_REPEATER_PROGRAM__VI = 0x1D3A; -constexpr unsigned int mmDMIF_PG1_DPG_TEST_DEBUG_DATA__VI = 0x1D39; -constexpr unsigned int mmDMIF_PG1_DPG_TEST_DEBUG_INDEX__VI = 0x1D38; -constexpr unsigned int mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL__VI = 0x1D32; -constexpr unsigned int mmDMIF_PG2_DPG_HW_DEBUG_11__VI = 0x1F3D; -constexpr unsigned int mmDMIF_PG2_DPG_HW_DEBUG_A__VI = 0x1F3B; -constexpr unsigned int mmDMIF_PG2_DPG_HW_DEBUG_B__VI = 0x1F3C; -constexpr unsigned int mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1__VI = 0x1F30; -constexpr unsigned int mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2__VI = 0x1F31; -constexpr unsigned int mmDMIF_PG2_DPG_PIPE_DPM_CONTROL__VI = 0x1F34; -constexpr unsigned int mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI = 0x1F36; -constexpr unsigned int mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL__VI = 0x1F35; -constexpr unsigned int mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI = 0x1F37; -constexpr unsigned int mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL__VI = 0x1F33; -constexpr unsigned int mmDMIF_PG2_DPG_REPEATER_PROGRAM__VI = 0x1F3A; -constexpr unsigned int mmDMIF_PG2_DPG_TEST_DEBUG_DATA__VI = 0x1F39; -constexpr unsigned int mmDMIF_PG2_DPG_TEST_DEBUG_INDEX__VI = 0x1F38; -constexpr unsigned int mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL__VI = 0x1F32; -constexpr unsigned int mmDMIF_PG3_DPG_HW_DEBUG_11__VI = 0x413D; -constexpr unsigned int mmDMIF_PG3_DPG_HW_DEBUG_A__VI = 0x413B; -constexpr unsigned int mmDMIF_PG3_DPG_HW_DEBUG_B__VI = 0x413C; -constexpr unsigned int mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1__VI = 0x4130; -constexpr unsigned int mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2__VI = 0x4131; -constexpr unsigned int mmDMIF_PG3_DPG_PIPE_DPM_CONTROL__VI = 0x4134; -constexpr unsigned int mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI = 0x4136; -constexpr unsigned int mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL__VI = 0x4135; -constexpr unsigned int mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI = 0x4137; -constexpr unsigned int mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL__VI = 0x4133; -constexpr unsigned int mmDMIF_PG3_DPG_REPEATER_PROGRAM__VI = 0x413A; -constexpr unsigned int mmDMIF_PG3_DPG_TEST_DEBUG_DATA__VI = 0x4139; -constexpr unsigned int mmDMIF_PG3_DPG_TEST_DEBUG_INDEX__VI = 0x4138; -constexpr unsigned int mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL__VI = 0x4132; -constexpr unsigned int mmDMIF_PG4_DPG_HW_DEBUG_11__VI = 0x433D; -constexpr unsigned int mmDMIF_PG4_DPG_HW_DEBUG_A__VI = 0x433B; -constexpr unsigned int mmDMIF_PG4_DPG_HW_DEBUG_B__VI = 0x433C; -constexpr unsigned int mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1__VI = 0x4330; -constexpr unsigned int mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2__VI = 0x4331; -constexpr unsigned int mmDMIF_PG4_DPG_PIPE_DPM_CONTROL__VI = 0x4334; -constexpr unsigned int mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI = 0x4336; -constexpr unsigned int mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL__VI = 0x4335; -constexpr unsigned int mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI = 0x4337; -constexpr unsigned int mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL__VI = 0x4333; -constexpr unsigned int mmDMIF_PG4_DPG_REPEATER_PROGRAM__VI = 0x433A; -constexpr unsigned int mmDMIF_PG4_DPG_TEST_DEBUG_DATA__VI = 0x4339; -constexpr unsigned int mmDMIF_PG4_DPG_TEST_DEBUG_INDEX__VI = 0x4338; -constexpr unsigned int mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL__VI = 0x4332; -constexpr unsigned int mmDMIF_PG5_DPG_HW_DEBUG_11__VI = 0x453D; -constexpr unsigned int mmDMIF_PG5_DPG_HW_DEBUG_A__VI = 0x453B; -constexpr unsigned int mmDMIF_PG5_DPG_HW_DEBUG_B__VI = 0x453C; -constexpr unsigned int mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1__VI = 0x4530; -constexpr unsigned int mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2__VI = 0x4531; -constexpr unsigned int mmDMIF_PG5_DPG_PIPE_DPM_CONTROL__VI = 0x4534; -constexpr unsigned int mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI = 0x4536; -constexpr unsigned int mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL__VI = 0x4535; -constexpr unsigned int mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI = 0x4537; -constexpr unsigned int mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL__VI = 0x4533; -constexpr unsigned int mmDMIF_PG5_DPG_REPEATER_PROGRAM__VI = 0x453A; -constexpr unsigned int mmDMIF_PG5_DPG_TEST_DEBUG_DATA__VI = 0x4539; -constexpr unsigned int mmDMIF_PG5_DPG_TEST_DEBUG_INDEX__VI = 0x4538; -constexpr unsigned int mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL__VI = 0x4532; -constexpr unsigned int mmDMIF_PG6_DPG_HW_DEBUG_11__VI = 0x473D; -constexpr unsigned int mmDMIF_PG6_DPG_HW_DEBUG_A__VI = 0x473B; -constexpr unsigned int mmDMIF_PG6_DPG_HW_DEBUG_B__VI = 0x473C; -constexpr unsigned int mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1__VI = 0x4730; -constexpr unsigned int mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2__VI = 0x4731; -constexpr unsigned int mmDMIF_PG6_DPG_PIPE_DPM_CONTROL__VI = 0x4734; -constexpr unsigned int mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI = 0x4736; -constexpr unsigned int mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL__VI = 0x4735; -constexpr unsigned int mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI = 0x4737; -constexpr unsigned int mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL__VI = 0x4733; -constexpr unsigned int mmDMIF_PG6_DPG_REPEATER_PROGRAM__VI = 0x473A; -constexpr unsigned int mmDMIF_PG6_DPG_TEST_DEBUG_DATA__VI = 0x4739; -constexpr unsigned int mmDMIF_PG6_DPG_TEST_DEBUG_INDEX__VI = 0x4738; -constexpr unsigned int mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL__VI = 0x4732; -constexpr unsigned int mmDMIF_P_VMID__VI = 0x0300; -constexpr unsigned int mmDMIF_STATUS2__VI = 0x0304; -constexpr unsigned int mmDMIF_TEST_DEBUG_DATA__VI = 0x0302; -constexpr unsigned int mmDMIF_TEST_DEBUG_INDEX__VI = 0x0301; -constexpr unsigned int mmDMIF_URG_OVERRIDE__VI = 0x0329; -constexpr unsigned int mmDP0_DP_CONFIG__VI = 0x4AA3; -constexpr unsigned int mmDP0_DP_DPHY_8B10B_CNTL__VI = 0x4AB4; -constexpr unsigned int mmDP0_DP_DPHY_CNTL__VI = 0x4AAF; -constexpr unsigned int mmDP0_DP_DPHY_CRC_CNTL__VI = 0x4AB8; -constexpr unsigned int mmDP0_DP_DPHY_CRC_EN__VI = 0x4AB7; -constexpr unsigned int mmDP0_DP_DPHY_CRC_MST_CNTL__VI = 0x4ABA; -constexpr unsigned int mmDP0_DP_DPHY_CRC_MST_STATUS__VI = 0x4ABB; -constexpr unsigned int mmDP0_DP_DPHY_CRC_RESULT__VI = 0x4AB9; -constexpr unsigned int mmDP0_DP_DPHY_FAST_TRAINING__VI = 0x4ABC; -constexpr unsigned int mmDP0_DP_DPHY_FAST_TRAINING_STATUS__VI = 0x4ABD; -constexpr unsigned int mmDP0_DP_DPHY_PRBS_CNTL__VI = 0x4AB5; -constexpr unsigned int mmDP0_DP_DPHY_SYM0__VI = 0x4AB1; -constexpr unsigned int mmDP0_DP_DPHY_SYM1__VI = 0x4AB2; -constexpr unsigned int mmDP0_DP_DPHY_SYM2__VI = 0x4AB3; -constexpr unsigned int mmDP0_DP_DPHY_TRAINING_PATTERN_SEL__VI = 0x4AB0; -constexpr unsigned int mmDP0_DP_FE_TEST_DEBUG_DATA__VI = 0x4ADB; -constexpr unsigned int mmDP0_DP_FE_TEST_DEBUG_INDEX__VI = 0x4ADA; -constexpr unsigned int mmDP0_DP_HBR2_EYE_PATTERN__VI = 0x4AAC; -constexpr unsigned int mmDP0_DP_LINK_CNTL__VI = 0x4AA0; -constexpr unsigned int mmDP0_DP_LINK_FRAMING_CNTL__VI = 0x4AAB; -constexpr unsigned int mmDP0_DP_MSA_COLORIMETRY__VI = 0x4AA2; -constexpr unsigned int mmDP0_DP_MSA_MISC__VI = 0x4AA6; -constexpr unsigned int mmDP0_DP_MSA_V_TIMING_OVERRIDE1__VI = 0x4ABE; -constexpr unsigned int mmDP0_DP_MSA_V_TIMING_OVERRIDE2__VI = 0x4ABF; -constexpr unsigned int mmDP0_DP_MSE_LINK_TIMING__VI = 0x4AD6; -constexpr unsigned int mmDP0_DP_MSE_MISC_CNTL__VI = 0x4AD7; -constexpr unsigned int mmDP0_DP_MSE_RATE_CNTL__VI = 0x4ACF; -constexpr unsigned int mmDP0_DP_MSE_RATE_UPDATE__VI = 0x4AD1; -constexpr unsigned int mmDP0_DP_MSE_SAT0__VI = 0x4AD2; -constexpr unsigned int mmDP0_DP_MSE_SAT1__VI = 0x4AD3; -constexpr unsigned int mmDP0_DP_MSE_SAT2__VI = 0x4AD4; -constexpr unsigned int mmDP0_DP_MSE_SAT_UPDATE__VI = 0x4AD5; -constexpr unsigned int mmDP0_DP_PIXEL_FORMAT__VI = 0x4AA1; -constexpr unsigned int mmDP0_DP_SEC_AUD_M__VI = 0x4ACB; -constexpr unsigned int mmDP0_DP_SEC_AUD_M_READBACK__VI = 0x4ACC; -constexpr unsigned int mmDP0_DP_SEC_AUD_N__VI = 0x4AC9; -constexpr unsigned int mmDP0_DP_SEC_AUD_N_READBACK__VI = 0x4ACA; -constexpr unsigned int mmDP0_DP_SEC_CNTL__VI = 0x4AC3; -constexpr unsigned int mmDP0_DP_SEC_CNTL1__VI = 0x4AC4; -constexpr unsigned int mmDP0_DP_SEC_FRAMING1__VI = 0x4AC5; -constexpr unsigned int mmDP0_DP_SEC_FRAMING2__VI = 0x4AC6; -constexpr unsigned int mmDP0_DP_SEC_FRAMING3__VI = 0x4AC7; -constexpr unsigned int mmDP0_DP_SEC_FRAMING4__VI = 0x4AC8; -constexpr unsigned int mmDP0_DP_SEC_PACKET_CNTL__VI = 0x4ACE; -constexpr unsigned int mmDP0_DP_SEC_TIMESTAMP__VI = 0x4ACD; -constexpr unsigned int mmDP0_DP_STEER_FIFO__VI = 0x4AA5; -constexpr unsigned int mmDP0_DP_TEST_DEBUG_DATA__VI = 0x4AD9; -constexpr unsigned int mmDP0_DP_TEST_DEBUG_INDEX__VI = 0x4AD8; -constexpr unsigned int mmDP0_DP_VID_INTERRUPT_CNTL__VI = 0x4AAE; -constexpr unsigned int mmDP0_DP_VID_M__VI = 0x4AAA; -constexpr unsigned int mmDP0_DP_VID_MSA_VBID__VI = 0x4AAD; -constexpr unsigned int mmDP0_DP_VID_N__VI = 0x4AA9; -constexpr unsigned int mmDP0_DP_VID_STREAM_CNTL__VI = 0x4AA4; -constexpr unsigned int mmDP0_DP_VID_TIMING__VI = 0x4AA8; -constexpr unsigned int mmDP1_DP_CONFIG__VI = 0x4BA3; -constexpr unsigned int mmDP1_DP_DPHY_8B10B_CNTL__VI = 0x4BB4; -constexpr unsigned int mmDP1_DP_DPHY_CNTL__VI = 0x4BAF; -constexpr unsigned int mmDP1_DP_DPHY_CRC_CNTL__VI = 0x4BB8; -constexpr unsigned int mmDP1_DP_DPHY_CRC_EN__VI = 0x4BB7; -constexpr unsigned int mmDP1_DP_DPHY_CRC_MST_CNTL__VI = 0x4BBA; -constexpr unsigned int mmDP1_DP_DPHY_CRC_MST_STATUS__VI = 0x4BBB; -constexpr unsigned int mmDP1_DP_DPHY_CRC_RESULT__VI = 0x4BB9; -constexpr unsigned int mmDP1_DP_DPHY_FAST_TRAINING__VI = 0x4BBC; -constexpr unsigned int mmDP1_DP_DPHY_FAST_TRAINING_STATUS__VI = 0x4BBD; -constexpr unsigned int mmDP1_DP_DPHY_PRBS_CNTL__VI = 0x4BB5; -constexpr unsigned int mmDP1_DP_DPHY_SYM0__VI = 0x4BB1; -constexpr unsigned int mmDP1_DP_DPHY_SYM1__VI = 0x4BB2; -constexpr unsigned int mmDP1_DP_DPHY_SYM2__VI = 0x4BB3; -constexpr unsigned int mmDP1_DP_DPHY_TRAINING_PATTERN_SEL__VI = 0x4BB0; -constexpr unsigned int mmDP1_DP_FE_TEST_DEBUG_DATA__VI = 0x4BDB; -constexpr unsigned int mmDP1_DP_FE_TEST_DEBUG_INDEX__VI = 0x4BDA; -constexpr unsigned int mmDP1_DP_HBR2_EYE_PATTERN__VI = 0x4BAC; -constexpr unsigned int mmDP1_DP_LINK_CNTL__VI = 0x4BA0; -constexpr unsigned int mmDP1_DP_LINK_FRAMING_CNTL__VI = 0x4BAB; -constexpr unsigned int mmDP1_DP_MSA_COLORIMETRY__VI = 0x4BA2; -constexpr unsigned int mmDP1_DP_MSA_MISC__VI = 0x4BA6; -constexpr unsigned int mmDP1_DP_MSA_V_TIMING_OVERRIDE1__VI = 0x4BBE; -constexpr unsigned int mmDP1_DP_MSA_V_TIMING_OVERRIDE2__VI = 0x4BBF; -constexpr unsigned int mmDP1_DP_MSE_LINK_TIMING__VI = 0x4BD6; -constexpr unsigned int mmDP1_DP_MSE_MISC_CNTL__VI = 0x4BD7; -constexpr unsigned int mmDP1_DP_MSE_RATE_CNTL__VI = 0x4BCF; -constexpr unsigned int mmDP1_DP_MSE_RATE_UPDATE__VI = 0x4BD1; -constexpr unsigned int mmDP1_DP_MSE_SAT0__VI = 0x4BD2; -constexpr unsigned int mmDP1_DP_MSE_SAT1__VI = 0x4BD3; -constexpr unsigned int mmDP1_DP_MSE_SAT2__VI = 0x4BD4; -constexpr unsigned int mmDP1_DP_MSE_SAT_UPDATE__VI = 0x4BD5; -constexpr unsigned int mmDP1_DP_PIXEL_FORMAT__VI = 0x4BA1; -constexpr unsigned int mmDP1_DP_SEC_AUD_M__VI = 0x4BCB; -constexpr unsigned int mmDP1_DP_SEC_AUD_M_READBACK__VI = 0x4BCC; -constexpr unsigned int mmDP1_DP_SEC_AUD_N__VI = 0x4BC9; -constexpr unsigned int mmDP1_DP_SEC_AUD_N_READBACK__VI = 0x4BCA; -constexpr unsigned int mmDP1_DP_SEC_CNTL__VI = 0x4BC3; -constexpr unsigned int mmDP1_DP_SEC_CNTL1__VI = 0x4BC4; -constexpr unsigned int mmDP1_DP_SEC_FRAMING1__VI = 0x4BC5; -constexpr unsigned int mmDP1_DP_SEC_FRAMING2__VI = 0x4BC6; -constexpr unsigned int mmDP1_DP_SEC_FRAMING3__VI = 0x4BC7; -constexpr unsigned int mmDP1_DP_SEC_FRAMING4__VI = 0x4BC8; -constexpr unsigned int mmDP1_DP_SEC_PACKET_CNTL__VI = 0x4BCE; -constexpr unsigned int mmDP1_DP_SEC_TIMESTAMP__VI = 0x4BCD; -constexpr unsigned int mmDP1_DP_STEER_FIFO__VI = 0x4BA5; -constexpr unsigned int mmDP1_DP_TEST_DEBUG_DATA__VI = 0x4BD9; -constexpr unsigned int mmDP1_DP_TEST_DEBUG_INDEX__VI = 0x4BD8; -constexpr unsigned int mmDP1_DP_VID_INTERRUPT_CNTL__VI = 0x4BAE; -constexpr unsigned int mmDP1_DP_VID_M__VI = 0x4BAA; -constexpr unsigned int mmDP1_DP_VID_MSA_VBID__VI = 0x4BAD; -constexpr unsigned int mmDP1_DP_VID_N__VI = 0x4BA9; -constexpr unsigned int mmDP1_DP_VID_STREAM_CNTL__VI = 0x4BA4; -constexpr unsigned int mmDP1_DP_VID_TIMING__VI = 0x4BA8; -constexpr unsigned int mmDP2_DP_CONFIG__VI = 0x4CA3; -constexpr unsigned int mmDP2_DP_DPHY_8B10B_CNTL__VI = 0x4CB4; -constexpr unsigned int mmDP2_DP_DPHY_CNTL__VI = 0x4CAF; -constexpr unsigned int mmDP2_DP_DPHY_CRC_CNTL__VI = 0x4CB8; -constexpr unsigned int mmDP2_DP_DPHY_CRC_EN__VI = 0x4CB7; -constexpr unsigned int mmDP2_DP_DPHY_CRC_MST_CNTL__VI = 0x4CBA; -constexpr unsigned int mmDP2_DP_DPHY_CRC_MST_STATUS__VI = 0x4CBB; -constexpr unsigned int mmDP2_DP_DPHY_CRC_RESULT__VI = 0x4CB9; -constexpr unsigned int mmDP2_DP_DPHY_FAST_TRAINING__VI = 0x4CBC; -constexpr unsigned int mmDP2_DP_DPHY_FAST_TRAINING_STATUS__VI = 0x4CBD; -constexpr unsigned int mmDP2_DP_DPHY_PRBS_CNTL__VI = 0x4CB5; -constexpr unsigned int mmDP2_DP_DPHY_SYM0__VI = 0x4CB1; -constexpr unsigned int mmDP2_DP_DPHY_SYM1__VI = 0x4CB2; -constexpr unsigned int mmDP2_DP_DPHY_SYM2__VI = 0x4CB3; -constexpr unsigned int mmDP2_DP_DPHY_TRAINING_PATTERN_SEL__VI = 0x4CB0; -constexpr unsigned int mmDP2_DP_FE_TEST_DEBUG_DATA__VI = 0x4CDB; -constexpr unsigned int mmDP2_DP_FE_TEST_DEBUG_INDEX__VI = 0x4CDA; -constexpr unsigned int mmDP2_DP_HBR2_EYE_PATTERN__VI = 0x4CAC; -constexpr unsigned int mmDP2_DP_LINK_CNTL__VI = 0x4CA0; -constexpr unsigned int mmDP2_DP_LINK_FRAMING_CNTL__VI = 0x4CAB; -constexpr unsigned int mmDP2_DP_MSA_COLORIMETRY__VI = 0x4CA2; -constexpr unsigned int mmDP2_DP_MSA_MISC__VI = 0x4CA6; -constexpr unsigned int mmDP2_DP_MSA_V_TIMING_OVERRIDE1__VI = 0x4CBE; -constexpr unsigned int mmDP2_DP_MSA_V_TIMING_OVERRIDE2__VI = 0x4CBF; -constexpr unsigned int mmDP2_DP_MSE_LINK_TIMING__VI = 0x4CD6; -constexpr unsigned int mmDP2_DP_MSE_MISC_CNTL__VI = 0x4CD7; -constexpr unsigned int mmDP2_DP_MSE_RATE_CNTL__VI = 0x4CCF; -constexpr unsigned int mmDP2_DP_MSE_RATE_UPDATE__VI = 0x4CD1; -constexpr unsigned int mmDP2_DP_MSE_SAT0__VI = 0x4CD2; -constexpr unsigned int mmDP2_DP_MSE_SAT1__VI = 0x4CD3; -constexpr unsigned int mmDP2_DP_MSE_SAT2__VI = 0x4CD4; -constexpr unsigned int mmDP2_DP_MSE_SAT_UPDATE__VI = 0x4CD5; -constexpr unsigned int mmDP2_DP_PIXEL_FORMAT__VI = 0x4CA1; -constexpr unsigned int mmDP2_DP_SEC_AUD_M__VI = 0x4CCB; -constexpr unsigned int mmDP2_DP_SEC_AUD_M_READBACK__VI = 0x4CCC; -constexpr unsigned int mmDP2_DP_SEC_AUD_N__VI = 0x4CC9; -constexpr unsigned int mmDP2_DP_SEC_AUD_N_READBACK__VI = 0x4CCA; -constexpr unsigned int mmDP2_DP_SEC_CNTL__VI = 0x4CC3; -constexpr unsigned int mmDP2_DP_SEC_CNTL1__VI = 0x4CC4; -constexpr unsigned int mmDP2_DP_SEC_FRAMING1__VI = 0x4CC5; -constexpr unsigned int mmDP2_DP_SEC_FRAMING2__VI = 0x4CC6; -constexpr unsigned int mmDP2_DP_SEC_FRAMING3__VI = 0x4CC7; -constexpr unsigned int mmDP2_DP_SEC_FRAMING4__VI = 0x4CC8; -constexpr unsigned int mmDP2_DP_SEC_PACKET_CNTL__VI = 0x4CCE; -constexpr unsigned int mmDP2_DP_SEC_TIMESTAMP__VI = 0x4CCD; -constexpr unsigned int mmDP2_DP_STEER_FIFO__VI = 0x4CA5; -constexpr unsigned int mmDP2_DP_TEST_DEBUG_DATA__VI = 0x4CD9; -constexpr unsigned int mmDP2_DP_TEST_DEBUG_INDEX__VI = 0x4CD8; -constexpr unsigned int mmDP2_DP_VID_INTERRUPT_CNTL__VI = 0x4CAE; -constexpr unsigned int mmDP2_DP_VID_M__VI = 0x4CAA; -constexpr unsigned int mmDP2_DP_VID_MSA_VBID__VI = 0x4CAD; -constexpr unsigned int mmDP2_DP_VID_N__VI = 0x4CA9; -constexpr unsigned int mmDP2_DP_VID_STREAM_CNTL__VI = 0x4CA4; -constexpr unsigned int mmDP2_DP_VID_TIMING__VI = 0x4CA8; -constexpr unsigned int mmDP3_DP_CONFIG__VI = 0x4DA3; -constexpr unsigned int mmDP3_DP_DPHY_8B10B_CNTL__VI = 0x4DB4; -constexpr unsigned int mmDP3_DP_DPHY_CNTL__VI = 0x4DAF; -constexpr unsigned int mmDP3_DP_DPHY_CRC_CNTL__VI = 0x4DB8; -constexpr unsigned int mmDP3_DP_DPHY_CRC_EN__VI = 0x4DB7; -constexpr unsigned int mmDP3_DP_DPHY_CRC_MST_CNTL__VI = 0x4DBA; -constexpr unsigned int mmDP3_DP_DPHY_CRC_MST_STATUS__VI = 0x4DBB; -constexpr unsigned int mmDP3_DP_DPHY_CRC_RESULT__VI = 0x4DB9; -constexpr unsigned int mmDP3_DP_DPHY_FAST_TRAINING__VI = 0x4DBC; -constexpr unsigned int mmDP3_DP_DPHY_FAST_TRAINING_STATUS__VI = 0x4DBD; -constexpr unsigned int mmDP3_DP_DPHY_PRBS_CNTL__VI = 0x4DB5; -constexpr unsigned int mmDP3_DP_DPHY_SYM0__VI = 0x4DB1; -constexpr unsigned int mmDP3_DP_DPHY_SYM1__VI = 0x4DB2; -constexpr unsigned int mmDP3_DP_DPHY_SYM2__VI = 0x4DB3; -constexpr unsigned int mmDP3_DP_DPHY_TRAINING_PATTERN_SEL__VI = 0x4DB0; -constexpr unsigned int mmDP3_DP_FE_TEST_DEBUG_DATA__VI = 0x4DDB; -constexpr unsigned int mmDP3_DP_FE_TEST_DEBUG_INDEX__VI = 0x4DDA; -constexpr unsigned int mmDP3_DP_HBR2_EYE_PATTERN__VI = 0x4DAC; -constexpr unsigned int mmDP3_DP_LINK_CNTL__VI = 0x4DA0; -constexpr unsigned int mmDP3_DP_LINK_FRAMING_CNTL__VI = 0x4DAB; -constexpr unsigned int mmDP3_DP_MSA_COLORIMETRY__VI = 0x4DA2; -constexpr unsigned int mmDP3_DP_MSA_MISC__VI = 0x4DA6; -constexpr unsigned int mmDP3_DP_MSA_V_TIMING_OVERRIDE1__VI = 0x4DBE; -constexpr unsigned int mmDP3_DP_MSA_V_TIMING_OVERRIDE2__VI = 0x4DBF; -constexpr unsigned int mmDP3_DP_MSE_LINK_TIMING__VI = 0x4DD6; -constexpr unsigned int mmDP3_DP_MSE_MISC_CNTL__VI = 0x4DD7; -constexpr unsigned int mmDP3_DP_MSE_RATE_CNTL__VI = 0x4DCF; -constexpr unsigned int mmDP3_DP_MSE_RATE_UPDATE__VI = 0x4DD1; -constexpr unsigned int mmDP3_DP_MSE_SAT0__VI = 0x4DD2; -constexpr unsigned int mmDP3_DP_MSE_SAT1__VI = 0x4DD3; -constexpr unsigned int mmDP3_DP_MSE_SAT2__VI = 0x4DD4; -constexpr unsigned int mmDP3_DP_MSE_SAT_UPDATE__VI = 0x4DD5; -constexpr unsigned int mmDP3_DP_PIXEL_FORMAT__VI = 0x4DA1; -constexpr unsigned int mmDP3_DP_SEC_AUD_M__VI = 0x4DCB; -constexpr unsigned int mmDP3_DP_SEC_AUD_M_READBACK__VI = 0x4DCC; -constexpr unsigned int mmDP3_DP_SEC_AUD_N__VI = 0x4DC9; -constexpr unsigned int mmDP3_DP_SEC_AUD_N_READBACK__VI = 0x4DCA; -constexpr unsigned int mmDP3_DP_SEC_CNTL__VI = 0x4DC3; -constexpr unsigned int mmDP3_DP_SEC_CNTL1__VI = 0x4DC4; -constexpr unsigned int mmDP3_DP_SEC_FRAMING1__VI = 0x4DC5; -constexpr unsigned int mmDP3_DP_SEC_FRAMING2__VI = 0x4DC6; -constexpr unsigned int mmDP3_DP_SEC_FRAMING3__VI = 0x4DC7; -constexpr unsigned int mmDP3_DP_SEC_FRAMING4__VI = 0x4DC8; -constexpr unsigned int mmDP3_DP_SEC_PACKET_CNTL__VI = 0x4DCE; -constexpr unsigned int mmDP3_DP_SEC_TIMESTAMP__VI = 0x4DCD; -constexpr unsigned int mmDP3_DP_STEER_FIFO__VI = 0x4DA5; -constexpr unsigned int mmDP3_DP_TEST_DEBUG_DATA__VI = 0x4DD9; -constexpr unsigned int mmDP3_DP_TEST_DEBUG_INDEX__VI = 0x4DD8; -constexpr unsigned int mmDP3_DP_VID_INTERRUPT_CNTL__VI = 0x4DAE; -constexpr unsigned int mmDP3_DP_VID_M__VI = 0x4DAA; -constexpr unsigned int mmDP3_DP_VID_MSA_VBID__VI = 0x4DAD; -constexpr unsigned int mmDP3_DP_VID_N__VI = 0x4DA9; -constexpr unsigned int mmDP3_DP_VID_STREAM_CNTL__VI = 0x4DA4; -constexpr unsigned int mmDP3_DP_VID_TIMING__VI = 0x4DA8; -constexpr unsigned int mmDP4_DP_CONFIG__VI = 0x4EA3; -constexpr unsigned int mmDP4_DP_DPHY_8B10B_CNTL__VI = 0x4EB4; -constexpr unsigned int mmDP4_DP_DPHY_CNTL__VI = 0x4EAF; -constexpr unsigned int mmDP4_DP_DPHY_CRC_CNTL__VI = 0x4EB8; -constexpr unsigned int mmDP4_DP_DPHY_CRC_EN__VI = 0x4EB7; -constexpr unsigned int mmDP4_DP_DPHY_CRC_MST_CNTL__VI = 0x4EBA; -constexpr unsigned int mmDP4_DP_DPHY_CRC_MST_STATUS__VI = 0x4EBB; -constexpr unsigned int mmDP4_DP_DPHY_CRC_RESULT__VI = 0x4EB9; -constexpr unsigned int mmDP4_DP_DPHY_FAST_TRAINING__VI = 0x4EBC; -constexpr unsigned int mmDP4_DP_DPHY_FAST_TRAINING_STATUS__VI = 0x4EBD; -constexpr unsigned int mmDP4_DP_DPHY_PRBS_CNTL__VI = 0x4EB5; -constexpr unsigned int mmDP4_DP_DPHY_SYM0__VI = 0x4EB1; -constexpr unsigned int mmDP4_DP_DPHY_SYM1__VI = 0x4EB2; -constexpr unsigned int mmDP4_DP_DPHY_SYM2__VI = 0x4EB3; -constexpr unsigned int mmDP4_DP_DPHY_TRAINING_PATTERN_SEL__VI = 0x4EB0; -constexpr unsigned int mmDP4_DP_FE_TEST_DEBUG_DATA__VI = 0x4EDB; -constexpr unsigned int mmDP4_DP_FE_TEST_DEBUG_INDEX__VI = 0x4EDA; -constexpr unsigned int mmDP4_DP_HBR2_EYE_PATTERN__VI = 0x4EAC; -constexpr unsigned int mmDP4_DP_LINK_CNTL__VI = 0x4EA0; -constexpr unsigned int mmDP4_DP_LINK_FRAMING_CNTL__VI = 0x4EAB; -constexpr unsigned int mmDP4_DP_MSA_COLORIMETRY__VI = 0x4EA2; -constexpr unsigned int mmDP4_DP_MSA_MISC__VI = 0x4EA6; -constexpr unsigned int mmDP4_DP_MSA_V_TIMING_OVERRIDE1__VI = 0x4EBE; -constexpr unsigned int mmDP4_DP_MSA_V_TIMING_OVERRIDE2__VI = 0x4EBF; -constexpr unsigned int mmDP4_DP_MSE_LINK_TIMING__VI = 0x4ED6; -constexpr unsigned int mmDP4_DP_MSE_MISC_CNTL__VI = 0x4ED7; -constexpr unsigned int mmDP4_DP_MSE_RATE_CNTL__VI = 0x4ECF; -constexpr unsigned int mmDP4_DP_MSE_RATE_UPDATE__VI = 0x4ED1; -constexpr unsigned int mmDP4_DP_MSE_SAT0__VI = 0x4ED2; -constexpr unsigned int mmDP4_DP_MSE_SAT1__VI = 0x4ED3; -constexpr unsigned int mmDP4_DP_MSE_SAT2__VI = 0x4ED4; -constexpr unsigned int mmDP4_DP_MSE_SAT_UPDATE__VI = 0x4ED5; -constexpr unsigned int mmDP4_DP_PIXEL_FORMAT__VI = 0x4EA1; -constexpr unsigned int mmDP4_DP_SEC_AUD_M__VI = 0x4ECB; -constexpr unsigned int mmDP4_DP_SEC_AUD_M_READBACK__VI = 0x4ECC; -constexpr unsigned int mmDP4_DP_SEC_AUD_N__VI = 0x4EC9; -constexpr unsigned int mmDP4_DP_SEC_AUD_N_READBACK__VI = 0x4ECA; -constexpr unsigned int mmDP4_DP_SEC_CNTL__VI = 0x4EC3; -constexpr unsigned int mmDP4_DP_SEC_CNTL1__VI = 0x4EC4; -constexpr unsigned int mmDP4_DP_SEC_FRAMING1__VI = 0x4EC5; -constexpr unsigned int mmDP4_DP_SEC_FRAMING2__VI = 0x4EC6; -constexpr unsigned int mmDP4_DP_SEC_FRAMING3__VI = 0x4EC7; -constexpr unsigned int mmDP4_DP_SEC_FRAMING4__VI = 0x4EC8; -constexpr unsigned int mmDP4_DP_SEC_PACKET_CNTL__VI = 0x4ECE; -constexpr unsigned int mmDP4_DP_SEC_TIMESTAMP__VI = 0x4ECD; -constexpr unsigned int mmDP4_DP_STEER_FIFO__VI = 0x4EA5; -constexpr unsigned int mmDP4_DP_TEST_DEBUG_DATA__VI = 0x4ED9; -constexpr unsigned int mmDP4_DP_TEST_DEBUG_INDEX__VI = 0x4ED8; -constexpr unsigned int mmDP4_DP_VID_INTERRUPT_CNTL__VI = 0x4EAE; -constexpr unsigned int mmDP4_DP_VID_M__VI = 0x4EAA; -constexpr unsigned int mmDP4_DP_VID_MSA_VBID__VI = 0x4EAD; -constexpr unsigned int mmDP4_DP_VID_N__VI = 0x4EA9; -constexpr unsigned int mmDP4_DP_VID_STREAM_CNTL__VI = 0x4EA4; -constexpr unsigned int mmDP4_DP_VID_TIMING__VI = 0x4EA8; -constexpr unsigned int mmDP5_DP_CONFIG__VI = 0x4FA3; -constexpr unsigned int mmDP5_DP_DPHY_8B10B_CNTL__VI = 0x4FB4; -constexpr unsigned int mmDP5_DP_DPHY_CNTL__VI = 0x4FAF; -constexpr unsigned int mmDP5_DP_DPHY_CRC_CNTL__VI = 0x4FB8; -constexpr unsigned int mmDP5_DP_DPHY_CRC_EN__VI = 0x4FB7; -constexpr unsigned int mmDP5_DP_DPHY_CRC_MST_CNTL__VI = 0x4FBA; -constexpr unsigned int mmDP5_DP_DPHY_CRC_MST_STATUS__VI = 0x4FBB; -constexpr unsigned int mmDP5_DP_DPHY_CRC_RESULT__VI = 0x4FB9; -constexpr unsigned int mmDP5_DP_DPHY_FAST_TRAINING__VI = 0x4FBC; -constexpr unsigned int mmDP5_DP_DPHY_FAST_TRAINING_STATUS__VI = 0x4FBD; -constexpr unsigned int mmDP5_DP_DPHY_PRBS_CNTL__VI = 0x4FB5; -constexpr unsigned int mmDP5_DP_DPHY_SYM0__VI = 0x4FB1; -constexpr unsigned int mmDP5_DP_DPHY_SYM1__VI = 0x4FB2; -constexpr unsigned int mmDP5_DP_DPHY_SYM2__VI = 0x4FB3; -constexpr unsigned int mmDP5_DP_DPHY_TRAINING_PATTERN_SEL__VI = 0x4FB0; -constexpr unsigned int mmDP5_DP_FE_TEST_DEBUG_DATA__VI = 0x4FDB; -constexpr unsigned int mmDP5_DP_FE_TEST_DEBUG_INDEX__VI = 0x4FDA; -constexpr unsigned int mmDP5_DP_HBR2_EYE_PATTERN__VI = 0x4FAC; -constexpr unsigned int mmDP5_DP_LINK_CNTL__VI = 0x4FA0; -constexpr unsigned int mmDP5_DP_LINK_FRAMING_CNTL__VI = 0x4FAB; -constexpr unsigned int mmDP5_DP_MSA_COLORIMETRY__VI = 0x4FA2; -constexpr unsigned int mmDP5_DP_MSA_MISC__VI = 0x4FA6; -constexpr unsigned int mmDP5_DP_MSA_V_TIMING_OVERRIDE1__VI = 0x4FBE; -constexpr unsigned int mmDP5_DP_MSA_V_TIMING_OVERRIDE2__VI = 0x4FBF; -constexpr unsigned int mmDP5_DP_MSE_LINK_TIMING__VI = 0x4FD6; -constexpr unsigned int mmDP5_DP_MSE_MISC_CNTL__VI = 0x4FD7; -constexpr unsigned int mmDP5_DP_MSE_RATE_CNTL__VI = 0x4FCF; -constexpr unsigned int mmDP5_DP_MSE_RATE_UPDATE__VI = 0x4FD1; -constexpr unsigned int mmDP5_DP_MSE_SAT0__VI = 0x4FD2; -constexpr unsigned int mmDP5_DP_MSE_SAT1__VI = 0x4FD3; -constexpr unsigned int mmDP5_DP_MSE_SAT2__VI = 0x4FD4; -constexpr unsigned int mmDP5_DP_MSE_SAT_UPDATE__VI = 0x4FD5; -constexpr unsigned int mmDP5_DP_PIXEL_FORMAT__VI = 0x4FA1; -constexpr unsigned int mmDP5_DP_SEC_AUD_M__VI = 0x4FCB; -constexpr unsigned int mmDP5_DP_SEC_AUD_M_READBACK__VI = 0x4FCC; -constexpr unsigned int mmDP5_DP_SEC_AUD_N__VI = 0x4FC9; -constexpr unsigned int mmDP5_DP_SEC_AUD_N_READBACK__VI = 0x4FCA; -constexpr unsigned int mmDP5_DP_SEC_CNTL__VI = 0x4FC3; -constexpr unsigned int mmDP5_DP_SEC_CNTL1__VI = 0x4FC4; -constexpr unsigned int mmDP5_DP_SEC_FRAMING1__VI = 0x4FC5; -constexpr unsigned int mmDP5_DP_SEC_FRAMING2__VI = 0x4FC6; -constexpr unsigned int mmDP5_DP_SEC_FRAMING3__VI = 0x4FC7; -constexpr unsigned int mmDP5_DP_SEC_FRAMING4__VI = 0x4FC8; -constexpr unsigned int mmDP5_DP_SEC_PACKET_CNTL__VI = 0x4FCE; -constexpr unsigned int mmDP5_DP_SEC_TIMESTAMP__VI = 0x4FCD; -constexpr unsigned int mmDP5_DP_STEER_FIFO__VI = 0x4FA5; -constexpr unsigned int mmDP5_DP_TEST_DEBUG_DATA__VI = 0x4FD9; -constexpr unsigned int mmDP5_DP_TEST_DEBUG_INDEX__VI = 0x4FD8; -constexpr unsigned int mmDP5_DP_VID_INTERRUPT_CNTL__VI = 0x4FAE; -constexpr unsigned int mmDP5_DP_VID_M__VI = 0x4FAA; -constexpr unsigned int mmDP5_DP_VID_MSA_VBID__VI = 0x4FAD; -constexpr unsigned int mmDP5_DP_VID_N__VI = 0x4FA9; -constexpr unsigned int mmDP5_DP_VID_STREAM_CNTL__VI = 0x4FA4; -constexpr unsigned int mmDP5_DP_VID_TIMING__VI = 0x4FA8; -constexpr unsigned int mmDP6_DP_CONFIG__VI = 0x54A3; -constexpr unsigned int mmDP6_DP_DPHY_8B10B_CNTL__VI = 0x54B4; -constexpr unsigned int mmDP6_DP_DPHY_CNTL__VI = 0x54AF; -constexpr unsigned int mmDP6_DP_DPHY_CRC_CNTL__VI = 0x54B8; -constexpr unsigned int mmDP6_DP_DPHY_CRC_EN__VI = 0x54B7; -constexpr unsigned int mmDP6_DP_DPHY_CRC_MST_CNTL__VI = 0x54BA; -constexpr unsigned int mmDP6_DP_DPHY_CRC_MST_STATUS__VI = 0x54BB; -constexpr unsigned int mmDP6_DP_DPHY_CRC_RESULT__VI = 0x54B9; -constexpr unsigned int mmDP6_DP_DPHY_FAST_TRAINING__VI = 0x54BC; -constexpr unsigned int mmDP6_DP_DPHY_FAST_TRAINING_STATUS__VI = 0x54BD; -constexpr unsigned int mmDP6_DP_DPHY_PRBS_CNTL__VI = 0x54B5; -constexpr unsigned int mmDP6_DP_DPHY_SYM0__VI = 0x54B1; -constexpr unsigned int mmDP6_DP_DPHY_SYM1__VI = 0x54B2; -constexpr unsigned int mmDP6_DP_DPHY_SYM2__VI = 0x54B3; -constexpr unsigned int mmDP6_DP_DPHY_TRAINING_PATTERN_SEL__VI = 0x54B0; -constexpr unsigned int mmDP6_DP_FE_TEST_DEBUG_DATA__VI = 0x54DB; -constexpr unsigned int mmDP6_DP_FE_TEST_DEBUG_INDEX__VI = 0x54DA; -constexpr unsigned int mmDP6_DP_HBR2_EYE_PATTERN__VI = 0x54AC; -constexpr unsigned int mmDP6_DP_LINK_CNTL__VI = 0x54A0; -constexpr unsigned int mmDP6_DP_LINK_FRAMING_CNTL__VI = 0x54AB; -constexpr unsigned int mmDP6_DP_MSA_COLORIMETRY__VI = 0x54A2; -constexpr unsigned int mmDP6_DP_MSA_MISC__VI = 0x54A6; -constexpr unsigned int mmDP6_DP_MSA_V_TIMING_OVERRIDE1__VI = 0x54BE; -constexpr unsigned int mmDP6_DP_MSA_V_TIMING_OVERRIDE2__VI = 0x54BF; -constexpr unsigned int mmDP6_DP_MSE_LINK_TIMING__VI = 0x54D6; -constexpr unsigned int mmDP6_DP_MSE_MISC_CNTL__VI = 0x54D7; -constexpr unsigned int mmDP6_DP_MSE_RATE_CNTL__VI = 0x54CF; -constexpr unsigned int mmDP6_DP_MSE_RATE_UPDATE__VI = 0x54D1; -constexpr unsigned int mmDP6_DP_MSE_SAT0__VI = 0x54D2; -constexpr unsigned int mmDP6_DP_MSE_SAT1__VI = 0x54D3; -constexpr unsigned int mmDP6_DP_MSE_SAT2__VI = 0x54D4; -constexpr unsigned int mmDP6_DP_MSE_SAT_UPDATE__VI = 0x54D5; -constexpr unsigned int mmDP6_DP_PIXEL_FORMAT__VI = 0x54A1; -constexpr unsigned int mmDP6_DP_SEC_AUD_M__VI = 0x54CB; -constexpr unsigned int mmDP6_DP_SEC_AUD_M_READBACK__VI = 0x54CC; -constexpr unsigned int mmDP6_DP_SEC_AUD_N__VI = 0x54C9; -constexpr unsigned int mmDP6_DP_SEC_AUD_N_READBACK__VI = 0x54CA; -constexpr unsigned int mmDP6_DP_SEC_CNTL__VI = 0x54C3; -constexpr unsigned int mmDP6_DP_SEC_CNTL1__VI = 0x54C4; -constexpr unsigned int mmDP6_DP_SEC_FRAMING1__VI = 0x54C5; -constexpr unsigned int mmDP6_DP_SEC_FRAMING2__VI = 0x54C6; -constexpr unsigned int mmDP6_DP_SEC_FRAMING3__VI = 0x54C7; -constexpr unsigned int mmDP6_DP_SEC_FRAMING4__VI = 0x54C8; -constexpr unsigned int mmDP6_DP_SEC_PACKET_CNTL__VI = 0x54CE; -constexpr unsigned int mmDP6_DP_SEC_TIMESTAMP__VI = 0x54CD; -constexpr unsigned int mmDP6_DP_STEER_FIFO__VI = 0x54A5; -constexpr unsigned int mmDP6_DP_TEST_DEBUG_DATA__VI = 0x54D9; -constexpr unsigned int mmDP6_DP_TEST_DEBUG_INDEX__VI = 0x54D8; -constexpr unsigned int mmDP6_DP_VID_INTERRUPT_CNTL__VI = 0x54AE; -constexpr unsigned int mmDP6_DP_VID_M__VI = 0x54AA; -constexpr unsigned int mmDP6_DP_VID_MSA_VBID__VI = 0x54AD; -constexpr unsigned int mmDP6_DP_VID_N__VI = 0x54A9; -constexpr unsigned int mmDP6_DP_VID_STREAM_CNTL__VI = 0x54A4; -constexpr unsigned int mmDP6_DP_VID_TIMING__VI = 0x54A8; -constexpr unsigned int mmDPDBG_CLK_FORCE_CONTROL__VI = 0x010D; -constexpr unsigned int mmDPDBG_CNTL__VI = 0x1866; -constexpr unsigned int mmDPDBG_INTERRUPT__VI = 0x1867; -constexpr unsigned int mmDPG_HW_DEBUG_11__VI = 0x1B3D; -constexpr unsigned int mmDPG_HW_DEBUG_A__VI = 0x1B3B; -constexpr unsigned int mmDPG_HW_DEBUG_B__VI = 0x1B3C; -constexpr unsigned int mmDPG_PIPE_ARBITRATION_CONTROL1__VI = 0x1B30; -constexpr unsigned int mmDPG_PIPE_ARBITRATION_CONTROL2__VI = 0x1B31; -constexpr unsigned int mmDPG_PIPE_DPM_CONTROL__VI = 0x1B34; -constexpr unsigned int mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI = 0x1B36; -constexpr unsigned int mmDPG_PIPE_STUTTER_CONTROL__VI = 0x1B35; -constexpr unsigned int mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI = 0x1B37; -constexpr unsigned int mmDPG_PIPE_URGENCY_CONTROL__VI = 0x1B33; -constexpr unsigned int mmDPG_REPEATER_PROGRAM__VI = 0x1B3A; -constexpr unsigned int mmDPG_TEST_DEBUG_DATA__VI = 0x1B39; -constexpr unsigned int mmDPG_TEST_DEBUG_INDEX__VI = 0x1B38; -constexpr unsigned int mmDPG_WATERMARK_MASK_CONTROL__VI = 0x1B32; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED0__VI = 0x5D98; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED1__VI = 0x5D99; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED10__VI = 0x5DA2; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED11__VI = 0x5DA3; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED12__VI = 0x5DA4; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED13__VI = 0x5DA5; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED14__VI = 0x5DA6; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED15__VI = 0x5DA7; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED16__VI = 0x5DA8; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED17__VI = 0x5DA9; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED18__VI = 0x5DAA; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED19__VI = 0x5DAB; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED2__VI = 0x5D9A; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED20__VI = 0x5DAC; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED21__VI = 0x5DAD; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED22__VI = 0x5DAE; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED23__VI = 0x5DAF; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED24__VI = 0x5DB0; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED25__VI = 0x5DB1; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED26__VI = 0x5DB2; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED27__VI = 0x5DB3; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED28__VI = 0x5DB4; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED29__VI = 0x5DB5; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED3__VI = 0x5D9B; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED30__VI = 0x5DB6; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED31__VI = 0x5DB7; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED32__VI = 0x5DB8; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED33__VI = 0x5DB9; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED34__VI = 0x5DBA; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED35__VI = 0x5DBB; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED36__VI = 0x5DBC; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED37__VI = 0x5DBD; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED38__VI = 0x5DBE; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED39__VI = 0x5DBF; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED4__VI = 0x5D9C; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED40__VI = 0x5DC0; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED41__VI = 0x5DC1; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED42__VI = 0x5DC2; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED43__VI = 0x5DC3; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED44__VI = 0x5DC4; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED45__VI = 0x5DC5; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED46__VI = 0x5DC6; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED47__VI = 0x5DC7; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED48__VI = 0x5DC8; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED49__VI = 0x5DC9; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED5__VI = 0x5D9D; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED50__VI = 0x5DCA; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED51__VI = 0x5DCB; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED52__VI = 0x5DCC; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED53__VI = 0x5DCD; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED54__VI = 0x5DCE; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED55__VI = 0x5DCF; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED56__VI = 0x5DD0; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED57__VI = 0x5DD1; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED58__VI = 0x5DD2; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED59__VI = 0x5DD3; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED6__VI = 0x5D9E; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED60__VI = 0x5DD4; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED61__VI = 0x5DD5; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED62__VI = 0x5DD6; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED63__VI = 0x5DD7; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED7__VI = 0x5D9F; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED8__VI = 0x5DA0; -constexpr unsigned int mmDPHY_MACRO_CNTL_RESERVED9__VI = 0x5DA1; -constexpr unsigned int mmDPREFCLK_CGTT_BLK_CTRL_REG__VI = 0x0108; -constexpr unsigned int mmDPREFCLK_CNTL__VI = 0x0118; -constexpr unsigned int mmDP_AUX0_AUX_ARB_CONTROL__VI = 0x5C02; -constexpr unsigned int mmDP_AUX0_AUX_CONTROL__VI = 0x5C00; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_RX_CONTROL0__VI = 0x5C0A; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_RX_CONTROL1__VI = 0x5C0B; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_RX_STATUS__VI = 0x5C0D; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_TX_CONTROL__VI = 0x5C09; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL__VI = 0x5C08; -constexpr unsigned int mmDP_AUX0_AUX_DPHY_TX_STATUS__VI = 0x5C0C; -constexpr unsigned int mmDP_AUX0_AUX_GTC_SYNC_CONTROL__VI = 0x5C0E; -constexpr unsigned int mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__VI = 0x5C10; -constexpr unsigned int mmDP_AUX0_AUX_GTC_SYNC_DATA__VI = 0x5C12; -constexpr unsigned int mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__VI = 0x5C0F; -constexpr unsigned int mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI = 0x5C13; -constexpr unsigned int mmDP_AUX0_AUX_GTC_SYNC_STATUS__VI = 0x5C11; -constexpr unsigned int mmDP_AUX0_AUX_INTERRUPT_CONTROL__VI = 0x5C03; -constexpr unsigned int mmDP_AUX0_AUX_LS_DATA__VI = 0x5C07; -constexpr unsigned int mmDP_AUX0_AUX_LS_STATUS__VI = 0x5C05; -constexpr unsigned int mmDP_AUX0_AUX_SW_CONTROL__VI = 0x5C01; -constexpr unsigned int mmDP_AUX0_AUX_SW_DATA__VI = 0x5C06; -constexpr unsigned int mmDP_AUX0_AUX_SW_STATUS__VI = 0x5C04; -constexpr unsigned int mmDP_AUX0_AUX_TEST_DEBUG_DATA__VI = 0x5C15; -constexpr unsigned int mmDP_AUX0_AUX_TEST_DEBUG_INDEX__VI = 0x5C14; -constexpr unsigned int mmDP_AUX1_AUX_ARB_CONTROL__VI = 0x5C1E; -constexpr unsigned int mmDP_AUX1_AUX_CONTROL__VI = 0x5C1C; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_RX_CONTROL0__VI = 0x5C26; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_RX_CONTROL1__VI = 0x5C27; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_RX_STATUS__VI = 0x5C29; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_TX_CONTROL__VI = 0x5C25; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL__VI = 0x5C24; -constexpr unsigned int mmDP_AUX1_AUX_DPHY_TX_STATUS__VI = 0x5C28; -constexpr unsigned int mmDP_AUX1_AUX_GTC_SYNC_CONTROL__VI = 0x5C2A; -constexpr unsigned int mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__VI = 0x5C2C; -constexpr unsigned int mmDP_AUX1_AUX_GTC_SYNC_DATA__VI = 0x5C2E; -constexpr unsigned int mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__VI = 0x5C2B; -constexpr unsigned int mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI = 0x5C2F; -constexpr unsigned int mmDP_AUX1_AUX_GTC_SYNC_STATUS__VI = 0x5C2D; -constexpr unsigned int mmDP_AUX1_AUX_INTERRUPT_CONTROL__VI = 0x5C1F; -constexpr unsigned int mmDP_AUX1_AUX_LS_DATA__VI = 0x5C23; -constexpr unsigned int mmDP_AUX1_AUX_LS_STATUS__VI = 0x5C21; -constexpr unsigned int mmDP_AUX1_AUX_SW_CONTROL__VI = 0x5C1D; -constexpr unsigned int mmDP_AUX1_AUX_SW_DATA__VI = 0x5C22; -constexpr unsigned int mmDP_AUX1_AUX_SW_STATUS__VI = 0x5C20; -constexpr unsigned int mmDP_AUX1_AUX_TEST_DEBUG_DATA__VI = 0x5C31; -constexpr unsigned int mmDP_AUX1_AUX_TEST_DEBUG_INDEX__VI = 0x5C30; -constexpr unsigned int mmDP_AUX2_AUX_ARB_CONTROL__VI = 0x5C3A; -constexpr unsigned int mmDP_AUX2_AUX_CONTROL__VI = 0x5C38; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_RX_CONTROL0__VI = 0x5C42; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_RX_CONTROL1__VI = 0x5C43; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_RX_STATUS__VI = 0x5C45; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_TX_CONTROL__VI = 0x5C41; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL__VI = 0x5C40; -constexpr unsigned int mmDP_AUX2_AUX_DPHY_TX_STATUS__VI = 0x5C44; -constexpr unsigned int mmDP_AUX2_AUX_GTC_SYNC_CONTROL__VI = 0x5C46; -constexpr unsigned int mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__VI = 0x5C48; -constexpr unsigned int mmDP_AUX2_AUX_GTC_SYNC_DATA__VI = 0x5C4A; -constexpr unsigned int mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__VI = 0x5C47; -constexpr unsigned int mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI = 0x5C4B; -constexpr unsigned int mmDP_AUX2_AUX_GTC_SYNC_STATUS__VI = 0x5C49; -constexpr unsigned int mmDP_AUX2_AUX_INTERRUPT_CONTROL__VI = 0x5C3B; -constexpr unsigned int mmDP_AUX2_AUX_LS_DATA__VI = 0x5C3F; -constexpr unsigned int mmDP_AUX2_AUX_LS_STATUS__VI = 0x5C3D; -constexpr unsigned int mmDP_AUX2_AUX_SW_CONTROL__VI = 0x5C39; -constexpr unsigned int mmDP_AUX2_AUX_SW_DATA__VI = 0x5C3E; -constexpr unsigned int mmDP_AUX2_AUX_SW_STATUS__VI = 0x5C3C; -constexpr unsigned int mmDP_AUX2_AUX_TEST_DEBUG_DATA__VI = 0x5C4D; -constexpr unsigned int mmDP_AUX2_AUX_TEST_DEBUG_INDEX__VI = 0x5C4C; -constexpr unsigned int mmDP_AUX3_AUX_ARB_CONTROL__VI = 0x5C56; -constexpr unsigned int mmDP_AUX3_AUX_CONTROL__VI = 0x5C54; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_RX_CONTROL0__VI = 0x5C5E; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_RX_CONTROL1__VI = 0x5C5F; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_RX_STATUS__VI = 0x5C61; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_TX_CONTROL__VI = 0x5C5D; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL__VI = 0x5C5C; -constexpr unsigned int mmDP_AUX3_AUX_DPHY_TX_STATUS__VI = 0x5C60; -constexpr unsigned int mmDP_AUX3_AUX_GTC_SYNC_CONTROL__VI = 0x5C62; -constexpr unsigned int mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__VI = 0x5C64; -constexpr unsigned int mmDP_AUX3_AUX_GTC_SYNC_DATA__VI = 0x5C66; -constexpr unsigned int mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__VI = 0x5C63; -constexpr unsigned int mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI = 0x5C67; -constexpr unsigned int mmDP_AUX3_AUX_GTC_SYNC_STATUS__VI = 0x5C65; -constexpr unsigned int mmDP_AUX3_AUX_INTERRUPT_CONTROL__VI = 0x5C57; -constexpr unsigned int mmDP_AUX3_AUX_LS_DATA__VI = 0x5C5B; -constexpr unsigned int mmDP_AUX3_AUX_LS_STATUS__VI = 0x5C59; -constexpr unsigned int mmDP_AUX3_AUX_SW_CONTROL__VI = 0x5C55; -constexpr unsigned int mmDP_AUX3_AUX_SW_DATA__VI = 0x5C5A; -constexpr unsigned int mmDP_AUX3_AUX_SW_STATUS__VI = 0x5C58; -constexpr unsigned int mmDP_AUX3_AUX_TEST_DEBUG_DATA__VI = 0x5C69; -constexpr unsigned int mmDP_AUX3_AUX_TEST_DEBUG_INDEX__VI = 0x5C68; -constexpr unsigned int mmDP_AUX4_AUX_ARB_CONTROL__VI = 0x5C72; -constexpr unsigned int mmDP_AUX4_AUX_CONTROL__VI = 0x5C70; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_RX_CONTROL0__VI = 0x5C7A; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_RX_CONTROL1__VI = 0x5C7B; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_RX_STATUS__VI = 0x5C7D; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_TX_CONTROL__VI = 0x5C79; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL__VI = 0x5C78; -constexpr unsigned int mmDP_AUX4_AUX_DPHY_TX_STATUS__VI = 0x5C7C; -constexpr unsigned int mmDP_AUX4_AUX_GTC_SYNC_CONTROL__VI = 0x5C7E; -constexpr unsigned int mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__VI = 0x5C80; -constexpr unsigned int mmDP_AUX4_AUX_GTC_SYNC_DATA__VI = 0x5C82; -constexpr unsigned int mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__VI = 0x5C7F; -constexpr unsigned int mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI = 0x5C83; -constexpr unsigned int mmDP_AUX4_AUX_GTC_SYNC_STATUS__VI = 0x5C81; -constexpr unsigned int mmDP_AUX4_AUX_INTERRUPT_CONTROL__VI = 0x5C73; -constexpr unsigned int mmDP_AUX4_AUX_LS_DATA__VI = 0x5C77; -constexpr unsigned int mmDP_AUX4_AUX_LS_STATUS__VI = 0x5C75; -constexpr unsigned int mmDP_AUX4_AUX_SW_CONTROL__VI = 0x5C71; -constexpr unsigned int mmDP_AUX4_AUX_SW_DATA__VI = 0x5C76; -constexpr unsigned int mmDP_AUX4_AUX_SW_STATUS__VI = 0x5C74; -constexpr unsigned int mmDP_AUX4_AUX_TEST_DEBUG_DATA__VI = 0x5C85; -constexpr unsigned int mmDP_AUX4_AUX_TEST_DEBUG_INDEX__VI = 0x5C84; -constexpr unsigned int mmDP_AUX5_AUX_ARB_CONTROL__VI = 0x5C8E; -constexpr unsigned int mmDP_AUX5_AUX_CONTROL__VI = 0x5C8C; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_RX_CONTROL0__VI = 0x5C96; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_RX_CONTROL1__VI = 0x5C97; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_RX_STATUS__VI = 0x5C99; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_TX_CONTROL__VI = 0x5C95; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL__VI = 0x5C94; -constexpr unsigned int mmDP_AUX5_AUX_DPHY_TX_STATUS__VI = 0x5C98; -constexpr unsigned int mmDP_AUX5_AUX_GTC_SYNC_CONTROL__VI = 0x5C9A; -constexpr unsigned int mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__VI = 0x5C9C; -constexpr unsigned int mmDP_AUX5_AUX_GTC_SYNC_DATA__VI = 0x5C9E; -constexpr unsigned int mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__VI = 0x5C9B; -constexpr unsigned int mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI = 0x5C9F; -constexpr unsigned int mmDP_AUX5_AUX_GTC_SYNC_STATUS__VI = 0x5C9D; -constexpr unsigned int mmDP_AUX5_AUX_INTERRUPT_CONTROL__VI = 0x5C8F; -constexpr unsigned int mmDP_AUX5_AUX_LS_DATA__VI = 0x5C93; -constexpr unsigned int mmDP_AUX5_AUX_LS_STATUS__VI = 0x5C91; -constexpr unsigned int mmDP_AUX5_AUX_SW_CONTROL__VI = 0x5C8D; -constexpr unsigned int mmDP_AUX5_AUX_SW_DATA__VI = 0x5C92; -constexpr unsigned int mmDP_AUX5_AUX_SW_STATUS__VI = 0x5C90; -constexpr unsigned int mmDP_AUX5_AUX_TEST_DEBUG_DATA__VI = 0x5CA1; -constexpr unsigned int mmDP_AUX5_AUX_TEST_DEBUG_INDEX__VI = 0x5CA0; -constexpr unsigned int mmDP_CONFIG__VI = 0x4AA3; -constexpr unsigned int mmDP_DPHY_8B10B_CNTL__VI = 0x4AB4; -constexpr unsigned int mmDP_DPHY_CNTL__VI = 0x4AAF; -constexpr unsigned int mmDP_DPHY_CRC_CNTL__VI = 0x4AB8; -constexpr unsigned int mmDP_DPHY_CRC_EN__VI = 0x4AB7; -constexpr unsigned int mmDP_DPHY_CRC_MST_CNTL__VI = 0x4ABA; -constexpr unsigned int mmDP_DPHY_CRC_MST_STATUS__VI = 0x4ABB; -constexpr unsigned int mmDP_DPHY_CRC_RESULT__VI = 0x4AB9; -constexpr unsigned int mmDP_DPHY_FAST_TRAINING__VI = 0x4ABC; -constexpr unsigned int mmDP_DPHY_FAST_TRAINING_STATUS__VI = 0x4ABD; -constexpr unsigned int mmDP_DPHY_PRBS_CNTL__VI = 0x4AB5; -constexpr unsigned int mmDP_DPHY_SYM0__VI = 0x4AB1; -constexpr unsigned int mmDP_DPHY_SYM1__VI = 0x4AB2; -constexpr unsigned int mmDP_DPHY_SYM2__VI = 0x4AB3; -constexpr unsigned int mmDP_DPHY_TRAINING_PATTERN_SEL__VI = 0x4AB0; -constexpr unsigned int mmDP_DTO0_MODULO__VI = 0x0142; -constexpr unsigned int mmDP_DTO0_PHASE__VI = 0x0141; -constexpr unsigned int mmDP_DTO1_MODULO__VI = 0x0146; -constexpr unsigned int mmDP_DTO1_PHASE__VI = 0x0145; -constexpr unsigned int mmDP_DTO2_MODULO__VI = 0x014A; -constexpr unsigned int mmDP_DTO2_PHASE__VI = 0x0149; -constexpr unsigned int mmDP_DTO3_MODULO__VI = 0x014E; -constexpr unsigned int mmDP_DTO3_PHASE__VI = 0x014D; -constexpr unsigned int mmDP_DTO4_MODULO__VI = 0x0152; -constexpr unsigned int mmDP_DTO4_PHASE__VI = 0x0151; -constexpr unsigned int mmDP_DTO5_MODULO__VI = 0x0156; -constexpr unsigned int mmDP_DTO5_PHASE__VI = 0x0155; -constexpr unsigned int mmDP_FE_TEST_DEBUG_DATA__VI = 0x4ADB; -constexpr unsigned int mmDP_FE_TEST_DEBUG_INDEX__VI = 0x4ADA; -constexpr unsigned int mmDP_HBR2_EYE_PATTERN__VI = 0x4AAC; -constexpr unsigned int mmDP_LINK_CNTL__VI = 0x4AA0; -constexpr unsigned int mmDP_LINK_FRAMING_CNTL__VI = 0x4AAB; -constexpr unsigned int mmDP_MSA_COLORIMETRY__VI = 0x4AA2; -constexpr unsigned int mmDP_MSA_MISC__VI = 0x4AA6; -constexpr unsigned int mmDP_MSA_V_TIMING_OVERRIDE1__VI = 0x4ABE; -constexpr unsigned int mmDP_MSA_V_TIMING_OVERRIDE2__VI = 0x4ABF; -constexpr unsigned int mmDP_MSE_LINK_TIMING__VI = 0x4AD6; -constexpr unsigned int mmDP_MSE_MISC_CNTL__VI = 0x4AD7; -constexpr unsigned int mmDP_MSE_RATE_CNTL__VI = 0x4ACF; -constexpr unsigned int mmDP_MSE_RATE_UPDATE__VI = 0x4AD1; -constexpr unsigned int mmDP_MSE_SAT0__VI = 0x4AD2; -constexpr unsigned int mmDP_MSE_SAT1__VI = 0x4AD3; -constexpr unsigned int mmDP_MSE_SAT2__VI = 0x4AD4; -constexpr unsigned int mmDP_MSE_SAT_UPDATE__VI = 0x4AD5; -constexpr unsigned int mmDP_PIXEL_FORMAT__VI = 0x4AA1; -constexpr unsigned int mmDP_SEC_AUD_M__VI = 0x4ACB; -constexpr unsigned int mmDP_SEC_AUD_M_READBACK__VI = 0x4ACC; -constexpr unsigned int mmDP_SEC_AUD_N__VI = 0x4AC9; -constexpr unsigned int mmDP_SEC_AUD_N_READBACK__VI = 0x4ACA; -constexpr unsigned int mmDP_SEC_CNTL__VI = 0x4AC3; -constexpr unsigned int mmDP_SEC_CNTL1__VI = 0x4AC4; -constexpr unsigned int mmDP_SEC_FRAMING1__VI = 0x4AC5; -constexpr unsigned int mmDP_SEC_FRAMING2__VI = 0x4AC6; -constexpr unsigned int mmDP_SEC_FRAMING3__VI = 0x4AC7; -constexpr unsigned int mmDP_SEC_FRAMING4__VI = 0x4AC8; -constexpr unsigned int mmDP_SEC_PACKET_CNTL__VI = 0x4ACE; -constexpr unsigned int mmDP_SEC_TIMESTAMP__VI = 0x4ACD; -constexpr unsigned int mmDP_STEER_FIFO__VI = 0x4AA5; -constexpr unsigned int mmDP_TEST_DEBUG_DATA__VI = 0x4AD9; -constexpr unsigned int mmDP_TEST_DEBUG_INDEX__VI = 0x4AD8; -constexpr unsigned int mmDP_VID_INTERRUPT_CNTL__VI = 0x4AAE; -constexpr unsigned int mmDP_VID_M__VI = 0x4AAA; -constexpr unsigned int mmDP_VID_MSA_VBID__VI = 0x4AAD; -constexpr unsigned int mmDP_VID_N__VI = 0x4AA9; -constexpr unsigned int mmDP_VID_STREAM_CNTL__VI = 0x4AA4; -constexpr unsigned int mmDP_VID_TIMING__VI = 0x4AA8; -constexpr unsigned int mmDVOACLKC_CNTL__VI = 0x016A; -constexpr unsigned int mmDVOACLKC_MVP_CNTL__VI = 0x0169; -constexpr unsigned int mmDVOACLKD_CNTL__VI = 0x0168; -constexpr unsigned int mmDVO_CLK_ENABLE__VI = 0x0129; -constexpr unsigned int mmDVO_CONTROL__VI = 0x16A3; -constexpr unsigned int mmDVO_CRC2_SIG_MASK__VI = 0x16A5; -constexpr unsigned int mmDVO_CRC2_SIG_RESULT__VI = 0x16A6; -constexpr unsigned int mmDVO_CRC_EN__VI = 0x16A4; -constexpr unsigned int mmDVO_ENABLE__VI = 0x16A0; -constexpr unsigned int mmDVO_FIFO_ERROR_STATUS__VI = 0x16A7; -constexpr unsigned int mmDVO_OUTPUT__VI = 0x16A2; -constexpr unsigned int mmDVO_SKEW_ADJUST__VI = 0x489F; -constexpr unsigned int mmDVO_SOURCE_SELECT__VI = 0x16A1; -constexpr unsigned int mmDVO_STRENGTH_CONTROL__VI = 0x489D; -constexpr unsigned int mmDVO_TEST_DEBUG_DATA__VI = 0x16A9; -constexpr unsigned int mmDVO_TEST_DEBUG_INDEX__VI = 0x16A8; -constexpr unsigned int mmDVO_VREF_CONTROL__VI = 0x489E; -constexpr unsigned int mmFBC_CLIENT_REGION_MASK__VI = 0x029B; -constexpr unsigned int mmFBC_CNTL__VI = 0x0280; -constexpr unsigned int mmFBC_COMP_CNTL__VI = 0x0284; -constexpr unsigned int mmFBC_COMP_MODE__VI = 0x0285; -constexpr unsigned int mmFBC_CSM_REGION_OFFSET_01__VI = 0x0299; -constexpr unsigned int mmFBC_CSM_REGION_OFFSET_23__VI = 0x029A; -constexpr unsigned int mmFBC_DEBUG0__VI = 0x0286; -constexpr unsigned int mmFBC_DEBUG1__VI = 0x0287; -constexpr unsigned int mmFBC_DEBUG2__VI = 0x0288; -constexpr unsigned int mmFBC_DEBUG_COMP__VI = 0x029C; -constexpr unsigned int mmFBC_DEBUG_CSR__VI = 0x029D; -constexpr unsigned int mmFBC_DEBUG_CSR_RDATA__VI = 0x029E; -constexpr unsigned int mmFBC_DEBUG_CSR_RDATA_HI__VI = 0x02A0; -constexpr unsigned int mmFBC_DEBUG_CSR_WDATA__VI = 0x029F; -constexpr unsigned int mmFBC_DEBUG_CSR_WDATA_HI__VI = 0x02A1; -constexpr unsigned int mmFBC_IDLE_FORCE_CLEAR_MASK__VI = 0x0282; -constexpr unsigned int mmFBC_IDLE_MASK__VI = 0x0281; -constexpr unsigned int mmFBC_IND_LUT0__VI = 0x0289; -constexpr unsigned int mmFBC_IND_LUT1__VI = 0x028A; -constexpr unsigned int mmFBC_IND_LUT10__VI = 0x0293; -constexpr unsigned int mmFBC_IND_LUT11__VI = 0x0294; -constexpr unsigned int mmFBC_IND_LUT12__VI = 0x0295; -constexpr unsigned int mmFBC_IND_LUT13__VI = 0x0296; -constexpr unsigned int mmFBC_IND_LUT14__VI = 0x0297; -constexpr unsigned int mmFBC_IND_LUT15__VI = 0x0298; -constexpr unsigned int mmFBC_IND_LUT2__VI = 0x028B; -constexpr unsigned int mmFBC_IND_LUT3__VI = 0x028C; -constexpr unsigned int mmFBC_IND_LUT4__VI = 0x028D; -constexpr unsigned int mmFBC_IND_LUT5__VI = 0x028E; -constexpr unsigned int mmFBC_IND_LUT6__VI = 0x028F; -constexpr unsigned int mmFBC_IND_LUT7__VI = 0x0290; -constexpr unsigned int mmFBC_IND_LUT8__VI = 0x0291; -constexpr unsigned int mmFBC_IND_LUT9__VI = 0x0292; -constexpr unsigned int mmFBC_MISC__VI = 0x02A2; -constexpr unsigned int mmFBC_START_STOP_DELAY__VI = 0x0283; -constexpr unsigned int mmFBC_STATUS__VI = 0x02A3; -constexpr unsigned int mmFBC_TEST_DEBUG_DATA__VI = 0x02A5; -constexpr unsigned int mmFBC_TEST_DEBUG_INDEX__VI = 0x02A4; -constexpr unsigned int mmFMT0_FMT_CLAMP_COMPONENT_B__VI = 0x1BEA; -constexpr unsigned int mmFMT0_FMT_CLAMP_COMPONENT_G__VI = 0x1BE9; -constexpr unsigned int mmFMT0_FMT_CLAMP_COMPONENT_R__VI = 0x1BE8; -constexpr unsigned int mmFMT0_FMT_TEST_DEBUG_DATA__VI = 0x1BEC; -constexpr unsigned int mmFMT0_FMT_TEST_DEBUG_INDEX__VI = 0x1BEB; -constexpr unsigned int mmFMT1_FMT_BIT_DEPTH_CONTROL__VI = 0x1DF2; -constexpr unsigned int mmFMT1_FMT_CLAMP_CNTL__VI = 0x1DF9; -constexpr unsigned int mmFMT1_FMT_CLAMP_COMPONENT_B__VI = 0x1DEA; -constexpr unsigned int mmFMT1_FMT_CLAMP_COMPONENT_G__VI = 0x1DE9; -constexpr unsigned int mmFMT1_FMT_CLAMP_COMPONENT_R__VI = 0x1DE8; -constexpr unsigned int mmFMT1_FMT_CONTROL__VI = 0x1DEE; -constexpr unsigned int mmFMT1_FMT_CRC_CNTL__VI = 0x1DFA; -constexpr unsigned int mmFMT1_FMT_CRC_SIG_BLUE_CONTROL__VI = 0x1DFE; -constexpr unsigned int mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK__VI = 0x1DFC; -constexpr unsigned int mmFMT1_FMT_CRC_SIG_RED_GREEN__VI = 0x1DFD; -constexpr unsigned int mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK__VI = 0x1DFB; -constexpr unsigned int mmFMT1_FMT_DEBUG_CNTL__VI = 0x1DFF; -constexpr unsigned int mmFMT1_FMT_DITHER_RAND_B_SEED__VI = 0x1DF5; -constexpr unsigned int mmFMT1_FMT_DITHER_RAND_G_SEED__VI = 0x1DF4; -constexpr unsigned int mmFMT1_FMT_DITHER_RAND_R_SEED__VI = 0x1DF3; -constexpr unsigned int mmFMT1_FMT_DYNAMIC_EXP_CNTL__VI = 0x1DED; -constexpr unsigned int mmFMT1_FMT_FORCE_DATA_0_1__VI = 0x1DF0; -constexpr unsigned int mmFMT1_FMT_FORCE_DATA_2_3__VI = 0x1DF1; -constexpr unsigned int mmFMT1_FMT_FORCE_OUTPUT_CNTL__VI = 0x1DEF; -constexpr unsigned int mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__VI = 0x1DF6; -constexpr unsigned int mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__VI = 0x1DF7; -constexpr unsigned int mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__VI = 0x1DF8; -constexpr unsigned int mmFMT1_FMT_TEST_DEBUG_DATA__VI = 0x1DEC; -constexpr unsigned int mmFMT1_FMT_TEST_DEBUG_INDEX__VI = 0x1DEB; -constexpr unsigned int mmFMT2_FMT_BIT_DEPTH_CONTROL__VI = 0x1FF2; -constexpr unsigned int mmFMT2_FMT_CLAMP_CNTL__VI = 0x1FF9; -constexpr unsigned int mmFMT2_FMT_CLAMP_COMPONENT_B__VI = 0x1FEA; -constexpr unsigned int mmFMT2_FMT_CLAMP_COMPONENT_G__VI = 0x1FE9; -constexpr unsigned int mmFMT2_FMT_CLAMP_COMPONENT_R__VI = 0x1FE8; -constexpr unsigned int mmFMT2_FMT_CONTROL__VI = 0x1FEE; -constexpr unsigned int mmFMT2_FMT_CRC_CNTL__VI = 0x1FFA; -constexpr unsigned int mmFMT2_FMT_CRC_SIG_BLUE_CONTROL__VI = 0x1FFE; -constexpr unsigned int mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK__VI = 0x1FFC; -constexpr unsigned int mmFMT2_FMT_CRC_SIG_RED_GREEN__VI = 0x1FFD; -constexpr unsigned int mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK__VI = 0x1FFB; -constexpr unsigned int mmFMT2_FMT_DEBUG_CNTL__VI = 0x1FFF; -constexpr unsigned int mmFMT2_FMT_DITHER_RAND_B_SEED__VI = 0x1FF5; -constexpr unsigned int mmFMT2_FMT_DITHER_RAND_G_SEED__VI = 0x1FF4; -constexpr unsigned int mmFMT2_FMT_DITHER_RAND_R_SEED__VI = 0x1FF3; -constexpr unsigned int mmFMT2_FMT_DYNAMIC_EXP_CNTL__VI = 0x1FED; -constexpr unsigned int mmFMT2_FMT_FORCE_DATA_0_1__VI = 0x1FF0; -constexpr unsigned int mmFMT2_FMT_FORCE_DATA_2_3__VI = 0x1FF1; -constexpr unsigned int mmFMT2_FMT_FORCE_OUTPUT_CNTL__VI = 0x1FEF; -constexpr unsigned int mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__VI = 0x1FF6; -constexpr unsigned int mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__VI = 0x1FF7; -constexpr unsigned int mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__VI = 0x1FF8; -constexpr unsigned int mmFMT2_FMT_TEST_DEBUG_DATA__VI = 0x1FEC; -constexpr unsigned int mmFMT2_FMT_TEST_DEBUG_INDEX__VI = 0x1FEB; -constexpr unsigned int mmFMT3_FMT_BIT_DEPTH_CONTROL__VI = 0x41F2; -constexpr unsigned int mmFMT3_FMT_CLAMP_CNTL__VI = 0x41F9; -constexpr unsigned int mmFMT3_FMT_CLAMP_COMPONENT_B__VI = 0x41EA; -constexpr unsigned int mmFMT3_FMT_CLAMP_COMPONENT_G__VI = 0x41E9; -constexpr unsigned int mmFMT3_FMT_CLAMP_COMPONENT_R__VI = 0x41E8; -constexpr unsigned int mmFMT3_FMT_CONTROL__VI = 0x41EE; -constexpr unsigned int mmFMT3_FMT_CRC_CNTL__VI = 0x41FA; -constexpr unsigned int mmFMT3_FMT_CRC_SIG_BLUE_CONTROL__VI = 0x41FE; -constexpr unsigned int mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK__VI = 0x41FC; -constexpr unsigned int mmFMT3_FMT_CRC_SIG_RED_GREEN__VI = 0x41FD; -constexpr unsigned int mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK__VI = 0x41FB; -constexpr unsigned int mmFMT3_FMT_DEBUG_CNTL__VI = 0x41FF; -constexpr unsigned int mmFMT3_FMT_DITHER_RAND_B_SEED__VI = 0x41F5; -constexpr unsigned int mmFMT3_FMT_DITHER_RAND_G_SEED__VI = 0x41F4; -constexpr unsigned int mmFMT3_FMT_DITHER_RAND_R_SEED__VI = 0x41F3; -constexpr unsigned int mmFMT3_FMT_DYNAMIC_EXP_CNTL__VI = 0x41ED; -constexpr unsigned int mmFMT3_FMT_FORCE_DATA_0_1__VI = 0x41F0; -constexpr unsigned int mmFMT3_FMT_FORCE_DATA_2_3__VI = 0x41F1; -constexpr unsigned int mmFMT3_FMT_FORCE_OUTPUT_CNTL__VI = 0x41EF; -constexpr unsigned int mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__VI = 0x41F6; -constexpr unsigned int mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__VI = 0x41F7; -constexpr unsigned int mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__VI = 0x41F8; -constexpr unsigned int mmFMT3_FMT_TEST_DEBUG_DATA__VI = 0x41EC; -constexpr unsigned int mmFMT3_FMT_TEST_DEBUG_INDEX__VI = 0x41EB; -constexpr unsigned int mmFMT4_FMT_BIT_DEPTH_CONTROL__VI = 0x43F2; -constexpr unsigned int mmFMT4_FMT_CLAMP_CNTL__VI = 0x43F9; -constexpr unsigned int mmFMT4_FMT_CLAMP_COMPONENT_B__VI = 0x43EA; -constexpr unsigned int mmFMT4_FMT_CLAMP_COMPONENT_G__VI = 0x43E9; -constexpr unsigned int mmFMT4_FMT_CLAMP_COMPONENT_R__VI = 0x43E8; -constexpr unsigned int mmFMT4_FMT_CONTROL__VI = 0x43EE; -constexpr unsigned int mmFMT4_FMT_CRC_CNTL__VI = 0x43FA; -constexpr unsigned int mmFMT4_FMT_CRC_SIG_BLUE_CONTROL__VI = 0x43FE; -constexpr unsigned int mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK__VI = 0x43FC; -constexpr unsigned int mmFMT4_FMT_CRC_SIG_RED_GREEN__VI = 0x43FD; -constexpr unsigned int mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK__VI = 0x43FB; -constexpr unsigned int mmFMT4_FMT_DEBUG_CNTL__VI = 0x43FF; -constexpr unsigned int mmFMT4_FMT_DITHER_RAND_B_SEED__VI = 0x43F5; -constexpr unsigned int mmFMT4_FMT_DITHER_RAND_G_SEED__VI = 0x43F4; -constexpr unsigned int mmFMT4_FMT_DITHER_RAND_R_SEED__VI = 0x43F3; -constexpr unsigned int mmFMT4_FMT_DYNAMIC_EXP_CNTL__VI = 0x43ED; -constexpr unsigned int mmFMT4_FMT_FORCE_DATA_0_1__VI = 0x43F0; -constexpr unsigned int mmFMT4_FMT_FORCE_DATA_2_3__VI = 0x43F1; -constexpr unsigned int mmFMT4_FMT_FORCE_OUTPUT_CNTL__VI = 0x43EF; -constexpr unsigned int mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__VI = 0x43F6; -constexpr unsigned int mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__VI = 0x43F7; -constexpr unsigned int mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__VI = 0x43F8; -constexpr unsigned int mmFMT4_FMT_TEST_DEBUG_DATA__VI = 0x43EC; -constexpr unsigned int mmFMT4_FMT_TEST_DEBUG_INDEX__VI = 0x43EB; -constexpr unsigned int mmFMT5_FMT_BIT_DEPTH_CONTROL__VI = 0x45F2; -constexpr unsigned int mmFMT5_FMT_CLAMP_CNTL__VI = 0x45F9; -constexpr unsigned int mmFMT5_FMT_CLAMP_COMPONENT_B__VI = 0x45EA; -constexpr unsigned int mmFMT5_FMT_CLAMP_COMPONENT_G__VI = 0x45E9; -constexpr unsigned int mmFMT5_FMT_CLAMP_COMPONENT_R__VI = 0x45E8; -constexpr unsigned int mmFMT5_FMT_CONTROL__VI = 0x45EE; -constexpr unsigned int mmFMT5_FMT_CRC_CNTL__VI = 0x45FA; -constexpr unsigned int mmFMT5_FMT_CRC_SIG_BLUE_CONTROL__VI = 0x45FE; -constexpr unsigned int mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK__VI = 0x45FC; -constexpr unsigned int mmFMT5_FMT_CRC_SIG_RED_GREEN__VI = 0x45FD; -constexpr unsigned int mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK__VI = 0x45FB; -constexpr unsigned int mmFMT5_FMT_DEBUG_CNTL__VI = 0x45FF; -constexpr unsigned int mmFMT5_FMT_DITHER_RAND_B_SEED__VI = 0x45F5; -constexpr unsigned int mmFMT5_FMT_DITHER_RAND_G_SEED__VI = 0x45F4; -constexpr unsigned int mmFMT5_FMT_DITHER_RAND_R_SEED__VI = 0x45F3; -constexpr unsigned int mmFMT5_FMT_DYNAMIC_EXP_CNTL__VI = 0x45ED; -constexpr unsigned int mmFMT5_FMT_FORCE_DATA_0_1__VI = 0x45F0; -constexpr unsigned int mmFMT5_FMT_FORCE_DATA_2_3__VI = 0x45F1; -constexpr unsigned int mmFMT5_FMT_FORCE_OUTPUT_CNTL__VI = 0x45EF; -constexpr unsigned int mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL__VI = 0x45F6; -constexpr unsigned int mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__VI = 0x45F7; -constexpr unsigned int mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__VI = 0x45F8; -constexpr unsigned int mmFMT5_FMT_TEST_DEBUG_DATA__VI = 0x45EC; -constexpr unsigned int mmFMT5_FMT_TEST_DEBUG_INDEX__VI = 0x45EB; -constexpr unsigned int mmFMT_CLAMP_COMPONENT_B__VI = 0x1BEA; -constexpr unsigned int mmFMT_CLAMP_COMPONENT_G__VI = 0x1BE9; -constexpr unsigned int mmFMT_CLAMP_COMPONENT_R__VI = 0x1BE8; -constexpr unsigned int mmFMT_TEST_DEBUG_DATA__VI = 0x1BEC; -constexpr unsigned int mmFMT_TEST_DEBUG_INDEX__VI = 0x1BEB; -constexpr unsigned int mmGAMMA_CORR_CNTLA_END_CNTL1__VI = 0x46CE; -constexpr unsigned int mmGAMMA_CORR_CNTLA_END_CNTL2__VI = 0x46CF; -constexpr unsigned int mmGAMMA_CORR_CNTLA_REGION_0_1__VI = 0x46D0; -constexpr unsigned int mmGAMMA_CORR_CNTLA_REGION_10_11__VI = 0x46D5; -constexpr unsigned int mmGAMMA_CORR_CNTLA_REGION_12_13__VI = 0x46D6; -constexpr unsigned int mmGAMMA_CORR_CNTLA_REGION_14_15__VI = 0x46D7; -constexpr unsigned int mmGAMMA_CORR_CNTLA_REGION_2_3__VI = 0x46D1; -constexpr unsigned int mmGAMMA_CORR_CNTLA_REGION_4_5__VI = 0x46D2; -constexpr unsigned int mmGAMMA_CORR_CNTLA_REGION_6_7__VI = 0x46D3; -constexpr unsigned int mmGAMMA_CORR_CNTLA_REGION_8_9__VI = 0x46D4; -constexpr unsigned int mmGAMMA_CORR_CNTLA_SLOPE_CNTL__VI = 0x46CD; -constexpr unsigned int mmGAMMA_CORR_CNTLA_START_CNTL__VI = 0x46CC; -constexpr unsigned int mmGAMMA_CORR_CNTLB_END_CNTL1__VI = 0x46DA; -constexpr unsigned int mmGAMMA_CORR_CNTLB_END_CNTL2__VI = 0x46DB; -constexpr unsigned int mmGAMMA_CORR_CNTLB_REGION_0_1__VI = 0x46DC; -constexpr unsigned int mmGAMMA_CORR_CNTLB_REGION_10_11__VI = 0x46E1; -constexpr unsigned int mmGAMMA_CORR_CNTLB_REGION_12_13__VI = 0x46E2; -constexpr unsigned int mmGAMMA_CORR_CNTLB_REGION_14_15__VI = 0x46E3; -constexpr unsigned int mmGAMMA_CORR_CNTLB_REGION_2_3__VI = 0x46DD; -constexpr unsigned int mmGAMMA_CORR_CNTLB_REGION_4_5__VI = 0x46DE; -constexpr unsigned int mmGAMMA_CORR_CNTLB_REGION_6_7__VI = 0x46DF; -constexpr unsigned int mmGAMMA_CORR_CNTLB_REGION_8_9__VI = 0x46E0; -constexpr unsigned int mmGAMMA_CORR_CNTLB_SLOPE_CNTL__VI = 0x46D9; -constexpr unsigned int mmGAMMA_CORR_CNTLB_START_CNTL__VI = 0x46D8; -constexpr unsigned int mmGAMMA_CORR_CONTROL__VI = 0x46C8; -constexpr unsigned int mmGAMMA_CORR_LUT_DATA__VI = 0x46CA; -constexpr unsigned int mmGAMMA_CORR_LUT_INDEX__VI = 0x46C9; -constexpr unsigned int mmGAMMA_CORR_LUT_WRITE_EN_MASK__VI = 0x46CB; -constexpr unsigned int mmGAMUT_REMAP_C11_C12__VI = 0x1A5A; -constexpr unsigned int mmGAMUT_REMAP_C13_C14__VI = 0x1A5B; -constexpr unsigned int mmGAMUT_REMAP_C21_C22__VI = 0x1A5C; -constexpr unsigned int mmGAMUT_REMAP_C23_C24__VI = 0x1A5D; -constexpr unsigned int mmGAMUT_REMAP_C31_C32__VI = 0x1A5E; -constexpr unsigned int mmGAMUT_REMAP_C33_C34__VI = 0x1A5F; -constexpr unsigned int mmGAMUT_REMAP_CONTROL__VI = 0x1A59; -constexpr unsigned int mmGARLIC_COHE_CP_DMA_ME_COMMAND__VI = 0x141B; -constexpr unsigned int mmGARLIC_COHE_CP_DMA_PFP_COMMAND__VI = 0x141C; -constexpr unsigned int mmGARLIC_COHE_CP_DMA_PIO_COMMAND__VI = 0x1424; -constexpr unsigned int mmGARLIC_COHE_CP_RB0_WPTR__VI = 0x1415; -constexpr unsigned int mmGARLIC_COHE_CP_RB1_WPTR__VI = 0x1416; -constexpr unsigned int mmGARLIC_COHE_CP_RB2_WPTR__VI = 0x1417; -constexpr unsigned int mmGARLIC_COHE_GARLIC_FLUSH_REQ__VI = 0x1425; -constexpr unsigned int mmGARLIC_COHE_SAM_SAB_RBI_WPTR__VI = 0x141D; -constexpr unsigned int mmGARLIC_COHE_SAM_SAB_RBO_WPTR__VI = 0x141E; -constexpr unsigned int mmGARLIC_COHE_SDMA0_GFX_RB_WPTR__VI = 0x1419; -constexpr unsigned int mmGARLIC_COHE_SDMA1_GFX_RB_WPTR__VI = 0x141A; -constexpr unsigned int mmGARLIC_COHE_SDMA2_GFX_RB_WPTR__VI = 0x1422; -constexpr unsigned int mmGARLIC_COHE_SDMA3_GFX_RB_WPTR__VI = 0x1423; -constexpr unsigned int mmGARLIC_COHE_UVD_RBC_RB_WPTR__VI = 0x1418; -constexpr unsigned int mmGARLIC_COHE_VCE_OUT_RB_WPTR__VI = 0x141F; -constexpr unsigned int mmGARLIC_COHE_VCE_RB_WPTR__VI = 0x1421; -constexpr unsigned int mmGARLIC_COHE_VCE_RB_WPTR2__VI = 0x1420; -constexpr unsigned int mmGC_CAC_CGTT_CLK_CTRL__VI = 0x3292; -constexpr unsigned int mmGC_CAC_LKG_AGGR_LOWER__VI = 0x3296; -constexpr unsigned int mmGC_CAC_LKG_AGGR_UPPER__VI = 0x3297; -constexpr unsigned int mmGC_USER_SHADER_RATE_CONFIG__VI = 0x2313; -constexpr unsigned int mmGDS_CS_CTXSW_CNT0__VI = 0x334E; -constexpr unsigned int mmGDS_CS_CTXSW_CNT1__VI = 0x334F; -constexpr unsigned int mmGDS_CS_CTXSW_CNT2__VI = 0x3350; -constexpr unsigned int mmGDS_CS_CTXSW_CNT3__VI = 0x3351; -constexpr unsigned int mmGDS_CS_CTXSW_STATUS__VI = 0x334D; -constexpr unsigned int mmGDS_DSM_CNTL__VI = 0x25CA; -constexpr unsigned int mmGDS_EDC_CNT__VI = 0x25C5; -constexpr unsigned int mmGDS_EDC_GRBM_CNT__VI = 0x25C6; -constexpr unsigned int mmGDS_EDC_OA_DED__VI = 0x25C7; -constexpr unsigned int mmGDS_GFX_CTXSW_STATUS__VI = 0x3352; -constexpr unsigned int mmGDS_PS0_CTXSW_CNT0__VI = 0x3357; -constexpr unsigned int mmGDS_PS0_CTXSW_CNT1__VI = 0x3358; -constexpr unsigned int mmGDS_PS0_CTXSW_CNT2__VI = 0x3359; -constexpr unsigned int mmGDS_PS0_CTXSW_CNT3__VI = 0x335A; -constexpr unsigned int mmGDS_PS1_CTXSW_CNT0__VI = 0x335B; -constexpr unsigned int mmGDS_PS1_CTXSW_CNT1__VI = 0x335C; -constexpr unsigned int mmGDS_PS1_CTXSW_CNT2__VI = 0x335D; -constexpr unsigned int mmGDS_PS1_CTXSW_CNT3__VI = 0x335E; -constexpr unsigned int mmGDS_PS2_CTXSW_CNT0__VI = 0x335F; -constexpr unsigned int mmGDS_PS2_CTXSW_CNT1__VI = 0x3360; -constexpr unsigned int mmGDS_PS2_CTXSW_CNT2__VI = 0x3361; -constexpr unsigned int mmGDS_PS2_CTXSW_CNT3__VI = 0x3362; -constexpr unsigned int mmGDS_PS3_CTXSW_CNT0__VI = 0x3363; -constexpr unsigned int mmGDS_PS3_CTXSW_CNT1__VI = 0x3364; -constexpr unsigned int mmGDS_PS3_CTXSW_CNT2__VI = 0x3365; -constexpr unsigned int mmGDS_PS3_CTXSW_CNT3__VI = 0x3366; -constexpr unsigned int mmGDS_PS4_CTXSW_CNT0__VI = 0x3367; -constexpr unsigned int mmGDS_PS4_CTXSW_CNT1__VI = 0x3368; -constexpr unsigned int mmGDS_PS4_CTXSW_CNT2__VI = 0x3369; -constexpr unsigned int mmGDS_PS4_CTXSW_CNT3__VI = 0x336A; -constexpr unsigned int mmGDS_PS5_CTXSW_CNT0__VI = 0x336B; -constexpr unsigned int mmGDS_PS5_CTXSW_CNT1__VI = 0x336C; -constexpr unsigned int mmGDS_PS5_CTXSW_CNT2__VI = 0x336D; -constexpr unsigned int mmGDS_PS5_CTXSW_CNT3__VI = 0x336E; -constexpr unsigned int mmGDS_PS6_CTXSW_CNT0__VI = 0x336F; -constexpr unsigned int mmGDS_PS6_CTXSW_CNT1__VI = 0x3370; -constexpr unsigned int mmGDS_PS6_CTXSW_CNT2__VI = 0x3371; -constexpr unsigned int mmGDS_PS6_CTXSW_CNT3__VI = 0x3372; -constexpr unsigned int mmGDS_PS7_CTXSW_CNT0__VI = 0x3373; -constexpr unsigned int mmGDS_PS7_CTXSW_CNT1__VI = 0x3374; -constexpr unsigned int mmGDS_PS7_CTXSW_CNT2__VI = 0x3375; -constexpr unsigned int mmGDS_PS7_CTXSW_CNT3__VI = 0x3376; -constexpr unsigned int mmGDS_VS_CTXSW_CNT0__VI = 0x3353; -constexpr unsigned int mmGDS_VS_CTXSW_CNT1__VI = 0x3354; -constexpr unsigned int mmGDS_VS_CTXSW_CNT2__VI = 0x3355; -constexpr unsigned int mmGDS_VS_CTXSW_CNT3__VI = 0x3356; -constexpr unsigned int mmGENERIC_I2C_CONTROL__VI = 0x16F4; -constexpr unsigned int mmGENERIC_I2C_DATA__VI = 0x16FA; -constexpr unsigned int mmGENERIC_I2C_INTERRUPT_CONTROL__VI = 0x16F5; -constexpr unsigned int mmGENERIC_I2C_PIN_DEBUG__VI = 0x16FC; -constexpr unsigned int mmGENERIC_I2C_PIN_SELECTION__VI = 0x16FB; -constexpr unsigned int mmGENERIC_I2C_SETUP__VI = 0x16F8; -constexpr unsigned int mmGENERIC_I2C_SPEED__VI = 0x16F7; -constexpr unsigned int mmGENERIC_I2C_STATUS__VI = 0x16F6; -constexpr unsigned int mmGENERIC_I2C_TRANSACTION__VI = 0x16F9; -constexpr unsigned int mmGMCON_LPT_TARGET__VI = 0x0D53; -constexpr unsigned int mmGPU_BIST_CONTROL__VI = 0xF835; -constexpr unsigned int mmGRBM_CAM_DATA__SI__CI = 0x3001; -constexpr unsigned int mmGRBM_CAM_DATA__VI = 0xF83F; -constexpr unsigned int mmGRBM_CAM_INDEX__SI__CI = 0x3000; -constexpr unsigned int mmGRBM_CAM_INDEX__VI = 0xF83E; -constexpr unsigned int mmGRBM_DSM_BYPASS__VI = 0x201E; -constexpr unsigned int mmGRBM_HYP_CAM_DATA__VI = 0xF83F; -constexpr unsigned int mmGRBM_HYP_CAM_INDEX__VI = 0xF83E; -constexpr unsigned int mmGRBM_TRAP_ADDR__VI = 0x201A; -constexpr unsigned int mmGRBM_TRAP_ADDR_MSK__VI = 0x201B; -constexpr unsigned int mmGRBM_TRAP_OP__VI = 0x2019; -constexpr unsigned int mmGRBM_TRAP_WD__VI = 0x201C; -constexpr unsigned int mmGRBM_TRAP_WD_MSK__VI = 0x201D; -constexpr unsigned int mmGRBM_WRITE_ERROR__VI = 0x201F; -constexpr unsigned int mmGRPH_FLIP_RATE_CNTL__VI = 0x1A8E; -constexpr unsigned int mmGRPH_STEREOSYNC_FLIP__VI = 0x1A97; -constexpr unsigned int mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI = 0x1A9F; -constexpr unsigned int mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI = 0x1ABF; -constexpr unsigned int mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI = 0x1ABD; -constexpr unsigned int mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI = 0x1ABE; -constexpr unsigned int mmGSKT_CONTROL__VI = 0x14BF; -constexpr unsigned int mmHDMI_ACR_32_0__VI = 0x4A2E; -constexpr unsigned int mmHDMI_ACR_32_1__VI = 0x4A2F; -constexpr unsigned int mmHDMI_ACR_44_0__VI = 0x4A30; -constexpr unsigned int mmHDMI_ACR_44_1__VI = 0x4A31; -constexpr unsigned int mmHDMI_ACR_48_0__VI = 0x4A32; -constexpr unsigned int mmHDMI_ACR_48_1__VI = 0x4A33; -constexpr unsigned int mmHDMI_ACR_PACKET_CONTROL__VI = 0x4A0C; -constexpr unsigned int mmHDMI_ACR_STATUS_0__VI = 0x4A34; -constexpr unsigned int mmHDMI_ACR_STATUS_1__VI = 0x4A35; -constexpr unsigned int mmHDMI_AUDIO_PACKET_CONTROL__VI = 0x4A0B; -constexpr unsigned int mmHDMI_CONTROL__VI = 0x4A09; -constexpr unsigned int mmHDMI_GC__VI = 0x4A13; -constexpr unsigned int mmHDMI_GENERIC_PACKET_CONTROL0__VI = 0x4A10; -constexpr unsigned int mmHDMI_GENERIC_PACKET_CONTROL1__VI = 0x4A2D; -constexpr unsigned int mmHDMI_INFOFRAME_CONTROL0__VI = 0x4A0E; -constexpr unsigned int mmHDMI_INFOFRAME_CONTROL1__VI = 0x4A0F; -constexpr unsigned int mmHDMI_STATUS__VI = 0x4A0A; -constexpr unsigned int mmHDMI_VBI_PACKET_CONTROL__VI = 0x4A0D; -constexpr unsigned int mmHDP_ADDR_CONFIG__VI = 0x0BD2; -constexpr unsigned int mmHDP_MEMIO_ADDR__VI = 0x0BF7; -constexpr unsigned int mmHDP_MEMIO_CNTL__VI = 0x0BF6; -constexpr unsigned int mmHDP_MEMIO_RD_DATA__VI = 0x0BFA; -constexpr unsigned int mmHDP_MEMIO_STATUS__VI = 0x0BF8; -constexpr unsigned int mmHDP_MEMIO_WR_DATA__VI = 0x0BF9; -constexpr unsigned int mmHDP_MEM_POWER_LS__VI = 0x0BD4; -constexpr unsigned int mmHDP_MISC_CNTL__VI = 0x0BD3; -constexpr unsigned int mmHDP_NONSURFACE_PREFETCH__VI = 0x0BD5; -constexpr unsigned int mmHDP_VF_ENABLE__VI = 0x0BFB; -constexpr unsigned int mmHDP_XDP_BARS_ADDR_39_36__VI = 0x0C44; -constexpr unsigned int mmHPD0_DC_HPD_CONTROL__VI = 0x189A; -constexpr unsigned int mmHPD0_DC_HPD_FAST_TRAIN_CNTL__VI = 0x189B; -constexpr unsigned int mmHPD0_DC_HPD_INT_CONTROL__VI = 0x1899; -constexpr unsigned int mmHPD0_DC_HPD_INT_STATUS__VI = 0x1898; -constexpr unsigned int mmHPD0_DC_HPD_TOGGLE_FILT_CNTL__VI = 0x189C; -constexpr unsigned int mmHPD1_DC_HPD_CONTROL__VI = 0x18A2; -constexpr unsigned int mmHPD1_DC_HPD_FAST_TRAIN_CNTL__VI = 0x18A3; -constexpr unsigned int mmHPD1_DC_HPD_INT_CONTROL__VI = 0x18A1; -constexpr unsigned int mmHPD1_DC_HPD_INT_STATUS__VI = 0x18A0; -constexpr unsigned int mmHPD1_DC_HPD_TOGGLE_FILT_CNTL__VI = 0x18A4; -constexpr unsigned int mmHPD2_DC_HPD_CONTROL__VI = 0x18AA; -constexpr unsigned int mmHPD2_DC_HPD_FAST_TRAIN_CNTL__VI = 0x18AB; -constexpr unsigned int mmHPD2_DC_HPD_INT_CONTROL__VI = 0x18A9; -constexpr unsigned int mmHPD2_DC_HPD_INT_STATUS__VI = 0x18A8; -constexpr unsigned int mmHPD2_DC_HPD_TOGGLE_FILT_CNTL__VI = 0x18AC; -constexpr unsigned int mmHPD3_DC_HPD_CONTROL__VI = 0x18B2; -constexpr unsigned int mmHPD3_DC_HPD_FAST_TRAIN_CNTL__VI = 0x18B3; -constexpr unsigned int mmHPD3_DC_HPD_INT_CONTROL__VI = 0x18B1; -constexpr unsigned int mmHPD3_DC_HPD_INT_STATUS__VI = 0x18B0; -constexpr unsigned int mmHPD3_DC_HPD_TOGGLE_FILT_CNTL__VI = 0x18B4; -constexpr unsigned int mmHPD4_DC_HPD_CONTROL__VI = 0x18BA; -constexpr unsigned int mmHPD4_DC_HPD_FAST_TRAIN_CNTL__VI = 0x18BB; -constexpr unsigned int mmHPD4_DC_HPD_INT_CONTROL__VI = 0x18B9; -constexpr unsigned int mmHPD4_DC_HPD_INT_STATUS__VI = 0x18B8; -constexpr unsigned int mmHPD4_DC_HPD_TOGGLE_FILT_CNTL__VI = 0x18BC; -constexpr unsigned int mmHPD5_DC_HPD_CONTROL__VI = 0x18C2; -constexpr unsigned int mmHPD5_DC_HPD_FAST_TRAIN_CNTL__VI = 0x18C3; -constexpr unsigned int mmHPD5_DC_HPD_INT_CONTROL__VI = 0x18C1; -constexpr unsigned int mmHPD5_DC_HPD_INT_STATUS__VI = 0x18C0; -constexpr unsigned int mmHPD5_DC_HPD_TOGGLE_FILT_CNTL__VI = 0x18C4; -constexpr unsigned int mmHW_ROTATION__VI = 0x1A9E; -constexpr unsigned int mmIH_ACTIVE_FCN_ID__VI = 0x0E43; -constexpr unsigned int mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT__VI = 0x0E4B; -constexpr unsigned int mmIH_CNTL__SI__CI = 0x0F86; -constexpr unsigned int mmIH_CNTL__VI = 0x0E36; -constexpr unsigned int mmIH_DEBUG__VI = 0x0E3C; -constexpr unsigned int mmIH_DOORBELL_RPTR__VI = 0x0E42; -constexpr unsigned int mmIH_DSM_MATCH_DATA_CONTROL__VI = 0x0E41; -constexpr unsigned int mmIH_DSM_MATCH_FIELD_CONTROL__VI = 0x0E40; -constexpr unsigned int mmIH_DSM_MATCH_VALUE_BIT_31_0__VI = 0x0E3D; -constexpr unsigned int mmIH_DSM_MATCH_VALUE_BIT_63_32__VI = 0x0E3E; -constexpr unsigned int mmIH_DSM_MATCH_VALUE_BIT_95_64__VI = 0x0E3F; -constexpr unsigned int mmIH_LEVEL_INTR_MASK__VI = 0x0E49; -constexpr unsigned int mmIH_LEVEL_STATUS__SI__CI = 0x0F87; -constexpr unsigned int mmIH_LEVEL_STATUS__VI = 0x0E37; -constexpr unsigned int mmIH_PERFCOUNTER0_RESULT__VI = 0x0E3A; -constexpr unsigned int mmIH_PERFCOUNTER1_RESULT__VI = 0x0E3B; -constexpr unsigned int mmIH_PERFMON_CNTL__VI = 0x0E39; -constexpr unsigned int mmIH_RB_BASE__SI__CI = 0x0F81; -constexpr unsigned int mmIH_RB_BASE__VI = 0x0E31; -constexpr unsigned int mmIH_RB_CNTL__SI__CI = 0x0F80; -constexpr unsigned int mmIH_RB_CNTL__VI = 0x0E30; -constexpr unsigned int mmIH_RB_RPTR__SI__CI = 0x0F82; -constexpr unsigned int mmIH_RB_RPTR__VI = 0x0E32; -constexpr unsigned int mmIH_RB_WPTR__SI__CI = 0x0F83; -constexpr unsigned int mmIH_RB_WPTR__VI = 0x0E33; -constexpr unsigned int mmIH_RB_WPTR_ADDR_HI__SI__CI = 0x0F84; -constexpr unsigned int mmIH_RB_WPTR_ADDR_HI__VI = 0x0E34; -constexpr unsigned int mmIH_RB_WPTR_ADDR_LO__SI__CI = 0x0F85; -constexpr unsigned int mmIH_RB_WPTR_ADDR_LO__VI = 0x0E35; -constexpr unsigned int mmIH_RESET_INCOMPLETE_INT_CNTL__VI = 0x0E4A; -constexpr unsigned int mmIH_STATUS__SI__CI = 0x0F88; -constexpr unsigned int mmIH_STATUS__VI = 0x0E38; -constexpr unsigned int mmIH_VERSION__VI = 0x0E48; -constexpr unsigned int mmIH_VF_ENABLE__VI = 0x0E45; -constexpr unsigned int mmIH_VF_RB_BIF_STATUS__VI = 0x0E47; -constexpr unsigned int mmIH_VF_RB_STATUS__VI = 0x0E44; -constexpr unsigned int mmIH_VIRT_RESET_REQ__VI = 0x0E46; -constexpr unsigned int mmIH_VMID_0_LUT__VI = 0x0E00; -constexpr unsigned int mmIH_VMID_10_LUT__VI = 0x0E0A; -constexpr unsigned int mmIH_VMID_11_LUT__VI = 0x0E0B; -constexpr unsigned int mmIH_VMID_12_LUT__VI = 0x0E0C; -constexpr unsigned int mmIH_VMID_13_LUT__VI = 0x0E0D; -constexpr unsigned int mmIH_VMID_14_LUT__VI = 0x0E0E; -constexpr unsigned int mmIH_VMID_15_LUT__VI = 0x0E0F; -constexpr unsigned int mmIH_VMID_1_LUT__VI = 0x0E01; -constexpr unsigned int mmIH_VMID_2_LUT__VI = 0x0E02; -constexpr unsigned int mmIH_VMID_3_LUT__VI = 0x0E03; -constexpr unsigned int mmIH_VMID_4_LUT__VI = 0x0E04; -constexpr unsigned int mmIH_VMID_5_LUT__VI = 0x0E05; -constexpr unsigned int mmIH_VMID_6_LUT__VI = 0x0E06; -constexpr unsigned int mmIH_VMID_7_LUT__VI = 0x0E07; -constexpr unsigned int mmIH_VMID_8_LUT__VI = 0x0E08; -constexpr unsigned int mmIH_VMID_9_LUT__VI = 0x0E09; -constexpr unsigned int mmINPUT_CSC_C11_C12__VI = 0x1A36; -constexpr unsigned int mmINPUT_CSC_C11_C12_A__VI = 0x46A6; -constexpr unsigned int mmINPUT_CSC_C11_C12_B__VI = 0x46AC; -constexpr unsigned int mmINPUT_CSC_C13_C14__VI = 0x1A37; -constexpr unsigned int mmINPUT_CSC_C13_C14_A__VI = 0x46A7; -constexpr unsigned int mmINPUT_CSC_C13_C14_B__VI = 0x46AD; -constexpr unsigned int mmINPUT_CSC_C21_C22__VI = 0x1A38; -constexpr unsigned int mmINPUT_CSC_C21_C22_A__VI = 0x46A8; -constexpr unsigned int mmINPUT_CSC_C21_C22_B__VI = 0x46AE; -constexpr unsigned int mmINPUT_CSC_C23_C24__VI = 0x1A39; -constexpr unsigned int mmINPUT_CSC_C23_C24_A__VI = 0x46A9; -constexpr unsigned int mmINPUT_CSC_C23_C24_B__VI = 0x46AF; -constexpr unsigned int mmINPUT_CSC_C31_C32__VI = 0x1A3A; -constexpr unsigned int mmINPUT_CSC_C31_C32_A__VI = 0x46AA; -constexpr unsigned int mmINPUT_CSC_C31_C32_B__VI = 0x46B0; -constexpr unsigned int mmINPUT_CSC_C33_C34__VI = 0x1A3B; -constexpr unsigned int mmINPUT_CSC_C33_C34_A__VI = 0x46AB; -constexpr unsigned int mmINPUT_CSC_C33_C34_B__VI = 0x46B1; -constexpr unsigned int mmINPUT_CSC_CONTROL__VI = 0x1A35; -constexpr unsigned int mmINPUT_GAMMA_CONTROL__VI = 0x1A10; -constexpr unsigned int mmKEY_CONTROL__VI = 0x1A53; -constexpr unsigned int mmKEY_RANGE_ALPHA__VI = 0x1A54; -constexpr unsigned int mmKEY_RANGE_BLUE__VI = 0x1A57; -constexpr unsigned int mmKEY_RANGE_GREEN__VI = 0x1A56; -constexpr unsigned int mmKEY_RANGE_RED__VI = 0x1A55; -constexpr unsigned int mmLB0_DC_MVP_LB_CONTROL__VI = 0x1AE3; -constexpr unsigned int mmLB0_LB_BLACK_KEYER_B_CB__VI = 0x1ACF; -constexpr unsigned int mmLB0_LB_BLACK_KEYER_G_Y__VI = 0x1ACE; -constexpr unsigned int mmLB0_LB_BLACK_KEYER_R_CR__VI = 0x1ACD; -constexpr unsigned int mmLB0_LB_BUFFER_LEVEL_STATUS__VI = 0x1AD7; -constexpr unsigned int mmLB0_LB_BUFFER_STATUS__VI = 0x1ADA; -constexpr unsigned int mmLB0_LB_BUFFER_URGENCY_CTRL__VI = 0x1AD8; -constexpr unsigned int mmLB0_LB_BUFFER_URGENCY_STATUS__VI = 0x1AD9; -constexpr unsigned int mmLB0_LB_DATA_FORMAT__VI = 0x1AC0; -constexpr unsigned int mmLB0_LB_DEBUG__VI = 0x1AE4; -constexpr unsigned int mmLB0_LB_DEBUG2__VI = 0x1AE5; -constexpr unsigned int mmLB0_LB_DEBUG3__VI = 0x1AE6; -constexpr unsigned int mmLB0_LB_DESKTOP_HEIGHT__VI = 0x1AC3; -constexpr unsigned int mmLB0_LB_INTERRUPT_MASK__VI = 0x1AC8; -constexpr unsigned int mmLB0_LB_KEYER_COLOR_B_CB__VI = 0x1AD3; -constexpr unsigned int mmLB0_LB_KEYER_COLOR_CTRL__VI = 0x1AD0; -constexpr unsigned int mmLB0_LB_KEYER_COLOR_G_Y__VI = 0x1AD2; -constexpr unsigned int mmLB0_LB_KEYER_COLOR_REP_B_CB__VI = 0x1AD6; -constexpr unsigned int mmLB0_LB_KEYER_COLOR_REP_G_Y__VI = 0x1AD5; -constexpr unsigned int mmLB0_LB_KEYER_COLOR_REP_R_CR__VI = 0x1AD4; -constexpr unsigned int mmLB0_LB_KEYER_COLOR_R_CR__VI = 0x1AD1; -constexpr unsigned int mmLB0_LB_MEMORY_CTRL__VI = 0x1AC1; -constexpr unsigned int mmLB0_LB_MEMORY_SIZE_STATUS__VI = 0x1AC2; -constexpr unsigned int mmLB0_LB_NO_OUTSTANDING_REQ_STATUS__VI = 0x1ADC; -constexpr unsigned int mmLB0_LB_SNAPSHOT_V_COUNTER__VI = 0x1AC7; -constexpr unsigned int mmLB0_LB_SYNC_RESET_SEL__VI = 0x1ACC; -constexpr unsigned int mmLB0_LB_VBLANK_STATUS__VI = 0x1ACB; -constexpr unsigned int mmLB0_LB_VLINE2_START_END__VI = 0x1AC5; -constexpr unsigned int mmLB0_LB_VLINE2_STATUS__VI = 0x1ACA; -constexpr unsigned int mmLB0_LB_VLINE_START_END__VI = 0x1AC4; -constexpr unsigned int mmLB0_LB_VLINE_STATUS__VI = 0x1AC9; -constexpr unsigned int mmLB0_LB_V_COUNTER__VI = 0x1AC6; -constexpr unsigned int mmLB0_MVP_AFR_FLIP_FIFO_CNTL__VI = 0x1AE1; -constexpr unsigned int mmLB0_MVP_AFR_FLIP_MODE__VI = 0x1AE0; -constexpr unsigned int mmLB0_MVP_FLIP_LINE_NUM_INSERT__VI = 0x1AE2; -constexpr unsigned int mmLB1_DC_MVP_LB_CONTROL__VI = 0x1CE3; -constexpr unsigned int mmLB1_LB_BLACK_KEYER_B_CB__VI = 0x1CCF; -constexpr unsigned int mmLB1_LB_BLACK_KEYER_G_Y__VI = 0x1CCE; -constexpr unsigned int mmLB1_LB_BLACK_KEYER_R_CR__VI = 0x1CCD; -constexpr unsigned int mmLB1_LB_BUFFER_LEVEL_STATUS__VI = 0x1CD7; -constexpr unsigned int mmLB1_LB_BUFFER_STATUS__VI = 0x1CDA; -constexpr unsigned int mmLB1_LB_BUFFER_URGENCY_CTRL__VI = 0x1CD8; -constexpr unsigned int mmLB1_LB_BUFFER_URGENCY_STATUS__VI = 0x1CD9; -constexpr unsigned int mmLB1_LB_DATA_FORMAT__VI = 0x1CC0; -constexpr unsigned int mmLB1_LB_DEBUG__VI = 0x1CE4; -constexpr unsigned int mmLB1_LB_DEBUG2__VI = 0x1CE5; -constexpr unsigned int mmLB1_LB_DEBUG3__VI = 0x1CE6; -constexpr unsigned int mmLB1_LB_DESKTOP_HEIGHT__VI = 0x1CC3; -constexpr unsigned int mmLB1_LB_INTERRUPT_MASK__VI = 0x1CC8; -constexpr unsigned int mmLB1_LB_KEYER_COLOR_B_CB__VI = 0x1CD3; -constexpr unsigned int mmLB1_LB_KEYER_COLOR_CTRL__VI = 0x1CD0; -constexpr unsigned int mmLB1_LB_KEYER_COLOR_G_Y__VI = 0x1CD2; -constexpr unsigned int mmLB1_LB_KEYER_COLOR_REP_B_CB__VI = 0x1CD6; -constexpr unsigned int mmLB1_LB_KEYER_COLOR_REP_G_Y__VI = 0x1CD5; -constexpr unsigned int mmLB1_LB_KEYER_COLOR_REP_R_CR__VI = 0x1CD4; -constexpr unsigned int mmLB1_LB_KEYER_COLOR_R_CR__VI = 0x1CD1; -constexpr unsigned int mmLB1_LB_MEMORY_CTRL__VI = 0x1CC1; -constexpr unsigned int mmLB1_LB_MEMORY_SIZE_STATUS__VI = 0x1CC2; -constexpr unsigned int mmLB1_LB_NO_OUTSTANDING_REQ_STATUS__VI = 0x1CDC; -constexpr unsigned int mmLB1_LB_SNAPSHOT_V_COUNTER__VI = 0x1CC7; -constexpr unsigned int mmLB1_LB_SYNC_RESET_SEL__VI = 0x1CCC; -constexpr unsigned int mmLB1_LB_TEST_DEBUG_DATA__VI = 0x1CFF; -constexpr unsigned int mmLB1_LB_TEST_DEBUG_INDEX__VI = 0x1CFE; -constexpr unsigned int mmLB1_LB_VBLANK_STATUS__VI = 0x1CCB; -constexpr unsigned int mmLB1_LB_VLINE2_START_END__VI = 0x1CC5; -constexpr unsigned int mmLB1_LB_VLINE2_STATUS__VI = 0x1CCA; -constexpr unsigned int mmLB1_LB_VLINE_START_END__VI = 0x1CC4; -constexpr unsigned int mmLB1_LB_VLINE_STATUS__VI = 0x1CC9; -constexpr unsigned int mmLB1_LB_V_COUNTER__VI = 0x1CC6; -constexpr unsigned int mmLB1_MVP_AFR_FLIP_FIFO_CNTL__VI = 0x1CE1; -constexpr unsigned int mmLB1_MVP_AFR_FLIP_MODE__VI = 0x1CE0; -constexpr unsigned int mmLB1_MVP_FLIP_LINE_NUM_INSERT__VI = 0x1CE2; -constexpr unsigned int mmLB2_DC_MVP_LB_CONTROL__VI = 0x1EE3; -constexpr unsigned int mmLB2_LB_BLACK_KEYER_B_CB__VI = 0x1ECF; -constexpr unsigned int mmLB2_LB_BLACK_KEYER_G_Y__VI = 0x1ECE; -constexpr unsigned int mmLB2_LB_BLACK_KEYER_R_CR__VI = 0x1ECD; -constexpr unsigned int mmLB2_LB_BUFFER_LEVEL_STATUS__VI = 0x1ED7; -constexpr unsigned int mmLB2_LB_BUFFER_STATUS__VI = 0x1EDA; -constexpr unsigned int mmLB2_LB_BUFFER_URGENCY_CTRL__VI = 0x1ED8; -constexpr unsigned int mmLB2_LB_BUFFER_URGENCY_STATUS__VI = 0x1ED9; -constexpr unsigned int mmLB2_LB_DATA_FORMAT__VI = 0x1EC0; -constexpr unsigned int mmLB2_LB_DEBUG__VI = 0x1EE4; -constexpr unsigned int mmLB2_LB_DEBUG2__VI = 0x1EE5; -constexpr unsigned int mmLB2_LB_DEBUG3__VI = 0x1EE6; -constexpr unsigned int mmLB2_LB_DESKTOP_HEIGHT__VI = 0x1EC3; -constexpr unsigned int mmLB2_LB_INTERRUPT_MASK__VI = 0x1EC8; -constexpr unsigned int mmLB2_LB_KEYER_COLOR_B_CB__VI = 0x1ED3; -constexpr unsigned int mmLB2_LB_KEYER_COLOR_CTRL__VI = 0x1ED0; -constexpr unsigned int mmLB2_LB_KEYER_COLOR_G_Y__VI = 0x1ED2; -constexpr unsigned int mmLB2_LB_KEYER_COLOR_REP_B_CB__VI = 0x1ED6; -constexpr unsigned int mmLB2_LB_KEYER_COLOR_REP_G_Y__VI = 0x1ED5; -constexpr unsigned int mmLB2_LB_KEYER_COLOR_REP_R_CR__VI = 0x1ED4; -constexpr unsigned int mmLB2_LB_KEYER_COLOR_R_CR__VI = 0x1ED1; -constexpr unsigned int mmLB2_LB_MEMORY_CTRL__VI = 0x1EC1; -constexpr unsigned int mmLB2_LB_MEMORY_SIZE_STATUS__VI = 0x1EC2; -constexpr unsigned int mmLB2_LB_NO_OUTSTANDING_REQ_STATUS__VI = 0x1EDC; -constexpr unsigned int mmLB2_LB_SNAPSHOT_V_COUNTER__VI = 0x1EC7; -constexpr unsigned int mmLB2_LB_SYNC_RESET_SEL__VI = 0x1ECC; -constexpr unsigned int mmLB2_LB_TEST_DEBUG_DATA__VI = 0x1EFF; -constexpr unsigned int mmLB2_LB_TEST_DEBUG_INDEX__VI = 0x1EFE; -constexpr unsigned int mmLB2_LB_VBLANK_STATUS__VI = 0x1ECB; -constexpr unsigned int mmLB2_LB_VLINE2_START_END__VI = 0x1EC5; -constexpr unsigned int mmLB2_LB_VLINE2_STATUS__VI = 0x1ECA; -constexpr unsigned int mmLB2_LB_VLINE_START_END__VI = 0x1EC4; -constexpr unsigned int mmLB2_LB_VLINE_STATUS__VI = 0x1EC9; -constexpr unsigned int mmLB2_LB_V_COUNTER__VI = 0x1EC6; -constexpr unsigned int mmLB2_MVP_AFR_FLIP_FIFO_CNTL__VI = 0x1EE1; -constexpr unsigned int mmLB2_MVP_AFR_FLIP_MODE__VI = 0x1EE0; -constexpr unsigned int mmLB2_MVP_FLIP_LINE_NUM_INSERT__VI = 0x1EE2; -constexpr unsigned int mmLB3_DC_MVP_LB_CONTROL__VI = 0x40E3; -constexpr unsigned int mmLB3_LB_BLACK_KEYER_B_CB__VI = 0x40CF; -constexpr unsigned int mmLB3_LB_BLACK_KEYER_G_Y__VI = 0x40CE; -constexpr unsigned int mmLB3_LB_BLACK_KEYER_R_CR__VI = 0x40CD; -constexpr unsigned int mmLB3_LB_BUFFER_LEVEL_STATUS__VI = 0x40D7; -constexpr unsigned int mmLB3_LB_BUFFER_STATUS__VI = 0x40DA; -constexpr unsigned int mmLB3_LB_BUFFER_URGENCY_CTRL__VI = 0x40D8; -constexpr unsigned int mmLB3_LB_BUFFER_URGENCY_STATUS__VI = 0x40D9; -constexpr unsigned int mmLB3_LB_DATA_FORMAT__VI = 0x40C0; -constexpr unsigned int mmLB3_LB_DEBUG__VI = 0x40E4; -constexpr unsigned int mmLB3_LB_DEBUG2__VI = 0x40E5; -constexpr unsigned int mmLB3_LB_DEBUG3__VI = 0x40E6; -constexpr unsigned int mmLB3_LB_DESKTOP_HEIGHT__VI = 0x40C3; -constexpr unsigned int mmLB3_LB_INTERRUPT_MASK__VI = 0x40C8; -constexpr unsigned int mmLB3_LB_KEYER_COLOR_B_CB__VI = 0x40D3; -constexpr unsigned int mmLB3_LB_KEYER_COLOR_CTRL__VI = 0x40D0; -constexpr unsigned int mmLB3_LB_KEYER_COLOR_G_Y__VI = 0x40D2; -constexpr unsigned int mmLB3_LB_KEYER_COLOR_REP_B_CB__VI = 0x40D6; -constexpr unsigned int mmLB3_LB_KEYER_COLOR_REP_G_Y__VI = 0x40D5; -constexpr unsigned int mmLB3_LB_KEYER_COLOR_REP_R_CR__VI = 0x40D4; -constexpr unsigned int mmLB3_LB_KEYER_COLOR_R_CR__VI = 0x40D1; -constexpr unsigned int mmLB3_LB_MEMORY_CTRL__VI = 0x40C1; -constexpr unsigned int mmLB3_LB_MEMORY_SIZE_STATUS__VI = 0x40C2; -constexpr unsigned int mmLB3_LB_NO_OUTSTANDING_REQ_STATUS__VI = 0x40DC; -constexpr unsigned int mmLB3_LB_SNAPSHOT_V_COUNTER__VI = 0x40C7; -constexpr unsigned int mmLB3_LB_SYNC_RESET_SEL__VI = 0x40CC; -constexpr unsigned int mmLB3_LB_TEST_DEBUG_DATA__VI = 0x40FF; -constexpr unsigned int mmLB3_LB_TEST_DEBUG_INDEX__VI = 0x40FE; -constexpr unsigned int mmLB3_LB_VBLANK_STATUS__VI = 0x40CB; -constexpr unsigned int mmLB3_LB_VLINE2_START_END__VI = 0x40C5; -constexpr unsigned int mmLB3_LB_VLINE2_STATUS__VI = 0x40CA; -constexpr unsigned int mmLB3_LB_VLINE_START_END__VI = 0x40C4; -constexpr unsigned int mmLB3_LB_VLINE_STATUS__VI = 0x40C9; -constexpr unsigned int mmLB3_LB_V_COUNTER__VI = 0x40C6; -constexpr unsigned int mmLB3_MVP_AFR_FLIP_FIFO_CNTL__VI = 0x40E1; -constexpr unsigned int mmLB3_MVP_AFR_FLIP_MODE__VI = 0x40E0; -constexpr unsigned int mmLB3_MVP_FLIP_LINE_NUM_INSERT__VI = 0x40E2; -constexpr unsigned int mmLB4_DC_MVP_LB_CONTROL__VI = 0x42E3; -constexpr unsigned int mmLB4_LB_BLACK_KEYER_B_CB__VI = 0x42CF; -constexpr unsigned int mmLB4_LB_BLACK_KEYER_G_Y__VI = 0x42CE; -constexpr unsigned int mmLB4_LB_BLACK_KEYER_R_CR__VI = 0x42CD; -constexpr unsigned int mmLB4_LB_BUFFER_LEVEL_STATUS__VI = 0x42D7; -constexpr unsigned int mmLB4_LB_BUFFER_STATUS__VI = 0x42DA; -constexpr unsigned int mmLB4_LB_BUFFER_URGENCY_CTRL__VI = 0x42D8; -constexpr unsigned int mmLB4_LB_BUFFER_URGENCY_STATUS__VI = 0x42D9; -constexpr unsigned int mmLB4_LB_DATA_FORMAT__VI = 0x42C0; -constexpr unsigned int mmLB4_LB_DEBUG__VI = 0x42E4; -constexpr unsigned int mmLB4_LB_DEBUG2__VI = 0x42E5; -constexpr unsigned int mmLB4_LB_DEBUG3__VI = 0x42E6; -constexpr unsigned int mmLB4_LB_DESKTOP_HEIGHT__VI = 0x42C3; -constexpr unsigned int mmLB4_LB_INTERRUPT_MASK__VI = 0x42C8; -constexpr unsigned int mmLB4_LB_KEYER_COLOR_B_CB__VI = 0x42D3; -constexpr unsigned int mmLB4_LB_KEYER_COLOR_CTRL__VI = 0x42D0; -constexpr unsigned int mmLB4_LB_KEYER_COLOR_G_Y__VI = 0x42D2; -constexpr unsigned int mmLB4_LB_KEYER_COLOR_REP_B_CB__VI = 0x42D6; -constexpr unsigned int mmLB4_LB_KEYER_COLOR_REP_G_Y__VI = 0x42D5; -constexpr unsigned int mmLB4_LB_KEYER_COLOR_REP_R_CR__VI = 0x42D4; -constexpr unsigned int mmLB4_LB_KEYER_COLOR_R_CR__VI = 0x42D1; -constexpr unsigned int mmLB4_LB_MEMORY_CTRL__VI = 0x42C1; -constexpr unsigned int mmLB4_LB_MEMORY_SIZE_STATUS__VI = 0x42C2; -constexpr unsigned int mmLB4_LB_NO_OUTSTANDING_REQ_STATUS__VI = 0x42DC; -constexpr unsigned int mmLB4_LB_SNAPSHOT_V_COUNTER__VI = 0x42C7; -constexpr unsigned int mmLB4_LB_SYNC_RESET_SEL__VI = 0x42CC; -constexpr unsigned int mmLB4_LB_TEST_DEBUG_DATA__VI = 0x42FF; -constexpr unsigned int mmLB4_LB_TEST_DEBUG_INDEX__VI = 0x42FE; -constexpr unsigned int mmLB4_LB_VBLANK_STATUS__VI = 0x42CB; -constexpr unsigned int mmLB4_LB_VLINE2_START_END__VI = 0x42C5; -constexpr unsigned int mmLB4_LB_VLINE2_STATUS__VI = 0x42CA; -constexpr unsigned int mmLB4_LB_VLINE_START_END__VI = 0x42C4; -constexpr unsigned int mmLB4_LB_VLINE_STATUS__VI = 0x42C9; -constexpr unsigned int mmLB4_LB_V_COUNTER__VI = 0x42C6; -constexpr unsigned int mmLB4_MVP_AFR_FLIP_FIFO_CNTL__VI = 0x42E1; -constexpr unsigned int mmLB4_MVP_AFR_FLIP_MODE__VI = 0x42E0; -constexpr unsigned int mmLB4_MVP_FLIP_LINE_NUM_INSERT__VI = 0x42E2; -constexpr unsigned int mmLB5_DC_MVP_LB_CONTROL__VI = 0x44E3; -constexpr unsigned int mmLB5_LB_BLACK_KEYER_B_CB__VI = 0x44CF; -constexpr unsigned int mmLB5_LB_BLACK_KEYER_G_Y__VI = 0x44CE; -constexpr unsigned int mmLB5_LB_BLACK_KEYER_R_CR__VI = 0x44CD; -constexpr unsigned int mmLB5_LB_BUFFER_LEVEL_STATUS__VI = 0x44D7; -constexpr unsigned int mmLB5_LB_BUFFER_STATUS__VI = 0x44DA; -constexpr unsigned int mmLB5_LB_BUFFER_URGENCY_CTRL__VI = 0x44D8; -constexpr unsigned int mmLB5_LB_BUFFER_URGENCY_STATUS__VI = 0x44D9; -constexpr unsigned int mmLB5_LB_DATA_FORMAT__VI = 0x44C0; -constexpr unsigned int mmLB5_LB_DEBUG__VI = 0x44E4; -constexpr unsigned int mmLB5_LB_DEBUG2__VI = 0x44E5; -constexpr unsigned int mmLB5_LB_DEBUG3__VI = 0x44E6; -constexpr unsigned int mmLB5_LB_DESKTOP_HEIGHT__VI = 0x44C3; -constexpr unsigned int mmLB5_LB_INTERRUPT_MASK__VI = 0x44C8; -constexpr unsigned int mmLB5_LB_KEYER_COLOR_B_CB__VI = 0x44D3; -constexpr unsigned int mmLB5_LB_KEYER_COLOR_CTRL__VI = 0x44D0; -constexpr unsigned int mmLB5_LB_KEYER_COLOR_G_Y__VI = 0x44D2; -constexpr unsigned int mmLB5_LB_KEYER_COLOR_REP_B_CB__VI = 0x44D6; -constexpr unsigned int mmLB5_LB_KEYER_COLOR_REP_G_Y__VI = 0x44D5; -constexpr unsigned int mmLB5_LB_KEYER_COLOR_REP_R_CR__VI = 0x44D4; -constexpr unsigned int mmLB5_LB_KEYER_COLOR_R_CR__VI = 0x44D1; -constexpr unsigned int mmLB5_LB_MEMORY_CTRL__VI = 0x44C1; -constexpr unsigned int mmLB5_LB_MEMORY_SIZE_STATUS__VI = 0x44C2; -constexpr unsigned int mmLB5_LB_NO_OUTSTANDING_REQ_STATUS__VI = 0x44DC; -constexpr unsigned int mmLB5_LB_SNAPSHOT_V_COUNTER__VI = 0x44C7; -constexpr unsigned int mmLB5_LB_SYNC_RESET_SEL__VI = 0x44CC; -constexpr unsigned int mmLB5_LB_TEST_DEBUG_DATA__VI = 0x44FF; -constexpr unsigned int mmLB5_LB_TEST_DEBUG_INDEX__VI = 0x44FE; -constexpr unsigned int mmLB5_LB_VBLANK_STATUS__VI = 0x44CB; -constexpr unsigned int mmLB5_LB_VLINE2_START_END__VI = 0x44C5; -constexpr unsigned int mmLB5_LB_VLINE2_STATUS__VI = 0x44CA; -constexpr unsigned int mmLB5_LB_VLINE_START_END__VI = 0x44C4; -constexpr unsigned int mmLB5_LB_VLINE_STATUS__VI = 0x44C9; -constexpr unsigned int mmLB5_LB_V_COUNTER__VI = 0x44C6; -constexpr unsigned int mmLB5_MVP_AFR_FLIP_FIFO_CNTL__VI = 0x44E1; -constexpr unsigned int mmLB5_MVP_AFR_FLIP_MODE__VI = 0x44E0; -constexpr unsigned int mmLB5_MVP_FLIP_LINE_NUM_INSERT__VI = 0x44E2; -constexpr unsigned int mmLBV_BLACK_KEYER_B_CB__VI = 0x464D; -constexpr unsigned int mmLBV_BLACK_KEYER_G_Y__VI = 0x464C; -constexpr unsigned int mmLBV_BLACK_KEYER_R_CR__VI = 0x464B; -constexpr unsigned int mmLBV_BUFFER_LEVEL_STATUS__VI = 0x4655; -constexpr unsigned int mmLBV_BUFFER_STATUS__VI = 0x4658; -constexpr unsigned int mmLBV_BUFFER_URGENCY_CTRL__VI = 0x4656; -constexpr unsigned int mmLBV_BUFFER_URGENCY_STATUS__VI = 0x4657; -constexpr unsigned int mmLBV_DATA_FORMAT__VI = 0x463C; -constexpr unsigned int mmLBV_DEBUG__VI = 0x465A; -constexpr unsigned int mmLBV_DEBUG2__VI = 0x465B; -constexpr unsigned int mmLBV_DEBUG3__VI = 0x465C; -constexpr unsigned int mmLBV_DESKTOP_HEIGHT__VI = 0x463F; -constexpr unsigned int mmLBV_INTERRUPT_MASK__VI = 0x4646; -constexpr unsigned int mmLBV_KEYER_COLOR_B_CB__VI = 0x4651; -constexpr unsigned int mmLBV_KEYER_COLOR_CTRL__VI = 0x464E; -constexpr unsigned int mmLBV_KEYER_COLOR_G_Y__VI = 0x4650; -constexpr unsigned int mmLBV_KEYER_COLOR_REP_B_CB__VI = 0x4654; -constexpr unsigned int mmLBV_KEYER_COLOR_REP_G_Y__VI = 0x4653; -constexpr unsigned int mmLBV_KEYER_COLOR_REP_R_CR__VI = 0x4652; -constexpr unsigned int mmLBV_KEYER_COLOR_R_CR__VI = 0x464F; -constexpr unsigned int mmLBV_MEMORY_CTRL__VI = 0x463D; -constexpr unsigned int mmLBV_MEMORY_SIZE_STATUS__VI = 0x463E; -constexpr unsigned int mmLBV_NO_OUTSTANDING_REQ_STATUS__VI = 0x4659; -constexpr unsigned int mmLBV_SNAPSHOT_V_COUNTER__VI = 0x4643; -constexpr unsigned int mmLBV_SNAPSHOT_V_COUNTER_CHROMA__VI = 0x4645; -constexpr unsigned int mmLBV_SYNC_RESET_SEL__VI = 0x464A; -constexpr unsigned int mmLBV_TEST_DEBUG_DATA__VI = 0x4667; -constexpr unsigned int mmLBV_TEST_DEBUG_INDEX__VI = 0x4666; -constexpr unsigned int mmLBV_VBLANK_STATUS__VI = 0x4649; -constexpr unsigned int mmLBV_VLINE2_START_END__VI = 0x4641; -constexpr unsigned int mmLBV_VLINE2_STATUS__VI = 0x4648; -constexpr unsigned int mmLBV_VLINE_START_END__VI = 0x4640; -constexpr unsigned int mmLBV_VLINE_STATUS__VI = 0x4647; -constexpr unsigned int mmLBV_V_COUNTER__VI = 0x4642; -constexpr unsigned int mmLBV_V_COUNTER_CHROMA__VI = 0x4644; -constexpr unsigned int mmLB_BLACK_KEYER_B_CB__VI = 0x1ACF; -constexpr unsigned int mmLB_BLACK_KEYER_G_Y__VI = 0x1ACE; -constexpr unsigned int mmLB_BLACK_KEYER_R_CR__VI = 0x1ACD; -constexpr unsigned int mmLB_BUFFER_LEVEL_STATUS__VI = 0x1AD7; -constexpr unsigned int mmLB_BUFFER_STATUS__VI = 0x1ADA; -constexpr unsigned int mmLB_BUFFER_URGENCY_CTRL__VI = 0x1AD8; -constexpr unsigned int mmLB_BUFFER_URGENCY_STATUS__VI = 0x1AD9; -constexpr unsigned int mmLB_DATA_FORMAT__VI = 0x1AC0; -constexpr unsigned int mmLB_DEBUG__VI = 0x1AE4; -constexpr unsigned int mmLB_DEBUG2__VI = 0x1AE5; -constexpr unsigned int mmLB_DEBUG3__VI = 0x1AE6; -constexpr unsigned int mmLB_DESKTOP_HEIGHT__VI = 0x1AC3; -constexpr unsigned int mmLB_INTERRUPT_MASK__VI = 0x1AC8; -constexpr unsigned int mmLB_KEYER_COLOR_B_CB__VI = 0x1AD3; -constexpr unsigned int mmLB_KEYER_COLOR_CTRL__VI = 0x1AD0; -constexpr unsigned int mmLB_KEYER_COLOR_G_Y__VI = 0x1AD2; -constexpr unsigned int mmLB_KEYER_COLOR_REP_B_CB__VI = 0x1AD6; -constexpr unsigned int mmLB_KEYER_COLOR_REP_G_Y__VI = 0x1AD5; -constexpr unsigned int mmLB_KEYER_COLOR_REP_R_CR__VI = 0x1AD4; -constexpr unsigned int mmLB_KEYER_COLOR_R_CR__VI = 0x1AD1; -constexpr unsigned int mmLB_MEMORY_CTRL__VI = 0x1AC1; -constexpr unsigned int mmLB_MEMORY_SIZE_STATUS__VI = 0x1AC2; -constexpr unsigned int mmLB_NO_OUTSTANDING_REQ_STATUS__VI = 0x1ADC; -constexpr unsigned int mmLB_SNAPSHOT_V_COUNTER__VI = 0x1AC7; -constexpr unsigned int mmLB_SYNC_RESET_SEL__VI = 0x1ACC; -constexpr unsigned int mmLB_VBLANK_STATUS__VI = 0x1ACB; -constexpr unsigned int mmLB_VLINE2_START_END__VI = 0x1AC5; -constexpr unsigned int mmLB_VLINE2_STATUS__VI = 0x1ACA; -constexpr unsigned int mmLB_VLINE_START_END__VI = 0x1AC4; -constexpr unsigned int mmLB_VLINE_STATUS__VI = 0x1AC9; -constexpr unsigned int mmLB_V_COUNTER__VI = 0x1AC6; -constexpr unsigned int mmLOW_POWER_TILING_CONTROL__VI = 0x030B; -constexpr unsigned int mmLVDS_DATA_CNTL__VI = 0x4A78; -constexpr unsigned int mmLVTMA_PWRSEQ_CNTL__VI = 0x481B; -constexpr unsigned int mmLVTMA_PWRSEQ_DELAY1__VI = 0x481E; -constexpr unsigned int mmLVTMA_PWRSEQ_DELAY2__VI = 0x481F; -constexpr unsigned int mmLVTMA_PWRSEQ_REF_DIV__VI = 0x481D; -constexpr unsigned int mmLVTMA_PWRSEQ_STATE__VI = 0x481C; -constexpr unsigned int mmMAILBOX_CONTROL__VI = 0x14D0; -constexpr unsigned int mmMAILBOX_INDEX__VI = 0x14C6; -constexpr unsigned int mmMAILBOX_INT_CNTL__VI = 0x14D1; -constexpr unsigned int mmMAILBOX_MSGBUF_RCV_DW0__VI = 0x14CC; -constexpr unsigned int mmMAILBOX_MSGBUF_RCV_DW1__VI = 0x14CD; -constexpr unsigned int mmMAILBOX_MSGBUF_RCV_DW2__VI = 0x14CE; -constexpr unsigned int mmMAILBOX_MSGBUF_RCV_DW3__VI = 0x14CF; -constexpr unsigned int mmMAILBOX_MSGBUF_TRN_DW0__VI = 0x14C8; -constexpr unsigned int mmMAILBOX_MSGBUF_TRN_DW1__VI = 0x14C9; -constexpr unsigned int mmMAILBOX_MSGBUF_TRN_DW2__VI = 0x14CA; -constexpr unsigned int mmMAILBOX_MSGBUF_TRN_DW3__VI = 0x14CB; -constexpr unsigned int mmMCIF_CONTROL__VI = 0x030C; -constexpr unsigned int mmMCIF_MEM_CONTROL__VI = 0x0311; -constexpr unsigned int mmMCIF_TEST_DEBUG_DATA__VI = 0x030F; -constexpr unsigned int mmMCIF_TEST_DEBUG_INDEX__VI = 0x030E; -constexpr unsigned int mmMCIF_VMID__VI = 0x0310; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__VI = 0x5E84; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__VI = 0x5E79; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS__VI = 0x5E7A; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__VI = 0x5E78; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__VI = 0x5E98; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C__VI = 0x5E8A; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__VI = 0x5E8B; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__VI = 0x5E88; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__VI = 0x5E89; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_1_STATUS__VI = 0x5E7C; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2__VI = 0x5E7D; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C__VI = 0x5E8E; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__VI = 0x5E8F; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__VI = 0x5E8C; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__VI = 0x5E8D; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_2_STATUS__VI = 0x5E7E; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2__VI = 0x5E7F; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C__VI = 0x5E92; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__VI = 0x5E93; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__VI = 0x5E90; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__VI = 0x5E91; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_3_STATUS__VI = 0x5E80; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2__VI = 0x5E81; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C__VI = 0x5E96; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__VI = 0x5E97; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__VI = 0x5E94; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__VI = 0x5E95; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_4_STATUS__VI = 0x5E82; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2__VI = 0x5E83; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_BUF_PITCH__VI = 0x5E7B; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL__VI = 0x5E99; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__VI = 0x5E87; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__VI = 0x5E86; -constexpr unsigned int mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK__VI = 0x5E85; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__VI = 0x5EC4; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__VI = 0x5EB9; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS__VI = 0x5EBA; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__VI = 0x5EB8; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__VI = 0x5ED8; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C__VI = 0x5ECA; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__VI = 0x5ECB; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__VI = 0x5EC8; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__VI = 0x5EC9; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_1_STATUS__VI = 0x5EBC; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2__VI = 0x5EBD; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C__VI = 0x5ECE; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__VI = 0x5ECF; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__VI = 0x5ECC; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__VI = 0x5ECD; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_2_STATUS__VI = 0x5EBE; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2__VI = 0x5EBF; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C__VI = 0x5ED2; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__VI = 0x5ED3; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__VI = 0x5ED0; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__VI = 0x5ED1; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_3_STATUS__VI = 0x5EC0; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2__VI = 0x5EC1; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C__VI = 0x5ED6; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__VI = 0x5ED7; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__VI = 0x5ED4; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__VI = 0x5ED5; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_4_STATUS__VI = 0x5EC2; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2__VI = 0x5EC3; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_BUF_PITCH__VI = 0x5EBB; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL__VI = 0x5ED9; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__VI = 0x5EC7; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__VI = 0x5EC6; -constexpr unsigned int mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK__VI = 0x5EC5; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__VI = 0x5F04; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__VI = 0x5EF9; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS__VI = 0x5EFA; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__VI = 0x5EF8; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__VI = 0x5F18; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C__VI = 0x5F0A; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__VI = 0x5F0B; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__VI = 0x5F08; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__VI = 0x5F09; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_1_STATUS__VI = 0x5EFC; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2__VI = 0x5EFD; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C__VI = 0x5F0E; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__VI = 0x5F0F; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__VI = 0x5F0C; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__VI = 0x5F0D; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_2_STATUS__VI = 0x5EFE; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2__VI = 0x5EFF; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C__VI = 0x5F12; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__VI = 0x5F13; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__VI = 0x5F10; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__VI = 0x5F11; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_3_STATUS__VI = 0x5F00; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2__VI = 0x5F01; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C__VI = 0x5F16; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__VI = 0x5F17; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__VI = 0x5F14; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__VI = 0x5F15; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_4_STATUS__VI = 0x5F02; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2__VI = 0x5F03; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_BUF_PITCH__VI = 0x5EFB; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL__VI = 0x5F19; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__VI = 0x5F07; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__VI = 0x5F06; -constexpr unsigned int mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK__VI = 0x5F05; -constexpr unsigned int mmMCIF_WB_ARBITRATION_CONTROL__VI = 0x5E84; -constexpr unsigned int mmMCIF_WB_BUFMGR_CUR_LINE_R__VI = 0x5E79; -constexpr unsigned int mmMCIF_WB_BUFMGR_STATUS__VI = 0x5E7A; -constexpr unsigned int mmMCIF_WB_BUFMGR_SW_CONTROL__VI = 0x5E78; -constexpr unsigned int mmMCIF_WB_BUFMGR_VCE_CONTROL__VI = 0x5E98; -constexpr unsigned int mmMCIF_WB_BUF_1_ADDR_C__VI = 0x5E8A; -constexpr unsigned int mmMCIF_WB_BUF_1_ADDR_C_OFFSET__VI = 0x5E8B; -constexpr unsigned int mmMCIF_WB_BUF_1_ADDR_Y__VI = 0x5E88; -constexpr unsigned int mmMCIF_WB_BUF_1_ADDR_Y_OFFSET__VI = 0x5E89; -constexpr unsigned int mmMCIF_WB_BUF_1_STATUS__VI = 0x5E7C; -constexpr unsigned int mmMCIF_WB_BUF_1_STATUS2__VI = 0x5E7D; -constexpr unsigned int mmMCIF_WB_BUF_2_ADDR_C__VI = 0x5E8E; -constexpr unsigned int mmMCIF_WB_BUF_2_ADDR_C_OFFSET__VI = 0x5E8F; -constexpr unsigned int mmMCIF_WB_BUF_2_ADDR_Y__VI = 0x5E8C; -constexpr unsigned int mmMCIF_WB_BUF_2_ADDR_Y_OFFSET__VI = 0x5E8D; -constexpr unsigned int mmMCIF_WB_BUF_2_STATUS__VI = 0x5E7E; -constexpr unsigned int mmMCIF_WB_BUF_2_STATUS2__VI = 0x5E7F; -constexpr unsigned int mmMCIF_WB_BUF_3_ADDR_C__VI = 0x5E92; -constexpr unsigned int mmMCIF_WB_BUF_3_ADDR_C_OFFSET__VI = 0x5E93; -constexpr unsigned int mmMCIF_WB_BUF_3_ADDR_Y__VI = 0x5E90; -constexpr unsigned int mmMCIF_WB_BUF_3_ADDR_Y_OFFSET__VI = 0x5E91; -constexpr unsigned int mmMCIF_WB_BUF_3_STATUS__VI = 0x5E80; -constexpr unsigned int mmMCIF_WB_BUF_3_STATUS2__VI = 0x5E81; -constexpr unsigned int mmMCIF_WB_BUF_4_ADDR_C__VI = 0x5E96; -constexpr unsigned int mmMCIF_WB_BUF_4_ADDR_C_OFFSET__VI = 0x5E97; -constexpr unsigned int mmMCIF_WB_BUF_4_ADDR_Y__VI = 0x5E94; -constexpr unsigned int mmMCIF_WB_BUF_4_ADDR_Y_OFFSET__VI = 0x5E95; -constexpr unsigned int mmMCIF_WB_BUF_4_STATUS__VI = 0x5E82; -constexpr unsigned int mmMCIF_WB_BUF_4_STATUS2__VI = 0x5E83; -constexpr unsigned int mmMCIF_WB_BUF_PITCH__VI = 0x5E7B; -constexpr unsigned int mmMCIF_WB_HVVMID_CONTROL__VI = 0x5E99; -constexpr unsigned int mmMCIF_WB_TEST_DEBUG_DATA__VI = 0x5E87; -constexpr unsigned int mmMCIF_WB_TEST_DEBUG_INDEX__VI = 0x5E86; -constexpr unsigned int mmMCIF_WB_URGENCY_WATERMARK__VI = 0x5E85; -constexpr unsigned int mmMCIF_WRITE_COMBINE_CONTROL__VI = 0x030D; -constexpr unsigned int mmMC_ARB_ATOMIC__VI = 0x09BE; -constexpr unsigned int mmMC_ARB_GRUB__VI = 0x09C8; -constexpr unsigned int mmMC_ARB_GRUB2__VI = 0x0A01; -constexpr unsigned int mmMC_ARB_GRUB_PRIORITY1_RD__VI = 0x0DD8; -constexpr unsigned int mmMC_ARB_GRUB_PRIORITY1_WR__VI = 0x0DD9; -constexpr unsigned int mmMC_ARB_GRUB_PRIORITY2_RD__VI = 0x0DDA; -constexpr unsigned int mmMC_ARB_GRUB_PRIORITY2_WR__VI = 0x0DDB; -constexpr unsigned int mmMC_ARB_GRUB_PROMOTE__VI = 0x09CE; -constexpr unsigned int mmMC_ARB_GRUB_REALTIME_RD__VI = 0x09F9; -constexpr unsigned int mmMC_ARB_GRUB_REALTIME_WR__VI = 0x09FB; -constexpr unsigned int mmMC_ARB_PERF_CID__VI = 0x09C6; -constexpr unsigned int mmMC_ARB_SNOOP__VI = 0x09C7; -constexpr unsigned int mmMC_BIST_CMD__VI = 0x0A85; -constexpr unsigned int mmMC_BIST_CNTL__SI__CI = 0x0A05; -constexpr unsigned int mmMC_BIST_CNTL__VI = 0x0A84; -constexpr unsigned int mmMC_BIST_DAT__VI = 0x0A86; -constexpr unsigned int mmMC_BIST_DATA_WORD0__SI__CI = 0x0A0A; -constexpr unsigned int mmMC_BIST_DATA_WORD0__VI = 0x0A8A; -constexpr unsigned int mmMC_BIST_DATA_WORD1__SI__CI = 0x0A0B; -constexpr unsigned int mmMC_BIST_DATA_WORD1__VI = 0x0A8B; -constexpr unsigned int mmMC_BIST_DATA_WORD2__SI__CI = 0x0A0C; -constexpr unsigned int mmMC_BIST_DATA_WORD2__VI = 0x0A8C; -constexpr unsigned int mmMC_BIST_DATA_WORD3__SI__CI = 0x0A0D; -constexpr unsigned int mmMC_BIST_DATA_WORD3__VI = 0x0A8D; -constexpr unsigned int mmMC_BIST_DATA_WORD4__SI__CI = 0x0A0E; -constexpr unsigned int mmMC_BIST_DATA_WORD4__VI = 0x0A8E; -constexpr unsigned int mmMC_BIST_DATA_WORD5__SI__CI = 0x0A0F; -constexpr unsigned int mmMC_BIST_DATA_WORD5__VI = 0x0A8F; -constexpr unsigned int mmMC_BIST_DATA_WORD6__SI__CI = 0x0A10; -constexpr unsigned int mmMC_BIST_DATA_WORD6__VI = 0x0A90; -constexpr unsigned int mmMC_BIST_DATA_WORD7__SI__CI = 0x0A11; -constexpr unsigned int mmMC_BIST_DATA_WORD7__VI = 0x0A91; -constexpr unsigned int mmMC_BIST_MISMATCH_ADDR__SI__CI = 0x0A13; -constexpr unsigned int mmMC_BIST_MISMATCH_ADDR__VI = 0x0A93; -constexpr unsigned int mmMC_BIST_RDATA_WORD0__SI__CI = 0x0A14; -constexpr unsigned int mmMC_BIST_RDATA_WORD0__VI = 0x0A94; -constexpr unsigned int mmMC_BIST_RDATA_WORD1__SI__CI = 0x0A15; -constexpr unsigned int mmMC_BIST_RDATA_WORD1__VI = 0x0A95; -constexpr unsigned int mmMC_BIST_RDATA_WORD2__SI__CI = 0x0A16; -constexpr unsigned int mmMC_BIST_RDATA_WORD2__VI = 0x0A96; -constexpr unsigned int mmMC_BIST_RDATA_WORD3__SI__CI = 0x0A17; -constexpr unsigned int mmMC_BIST_RDATA_WORD3__VI = 0x0A97; -constexpr unsigned int mmMC_BIST_RDATA_WORD4__SI__CI = 0x0A18; -constexpr unsigned int mmMC_BIST_RDATA_WORD4__VI = 0x0A98; -constexpr unsigned int mmMC_BIST_RDATA_WORD5__SI__CI = 0x0A19; -constexpr unsigned int mmMC_BIST_RDATA_WORD5__VI = 0x0A99; -constexpr unsigned int mmMC_BIST_RDATA_WORD6__SI__CI = 0x0A1A; -constexpr unsigned int mmMC_BIST_RDATA_WORD6__VI = 0x0A9A; -constexpr unsigned int mmMC_BIST_RDATA_WORD7__SI__CI = 0x0A1B; -constexpr unsigned int mmMC_BIST_RDATA_WORD7__VI = 0x0A9B; -constexpr unsigned int mmMC_CG_DATAPORT__SI__CI = 0x0A21; -constexpr unsigned int mmMC_CG_DATAPORT__VI = 0x0A32; -constexpr unsigned int mmMC_CITF_CREDITS_ARB_RD2__VI = 0x097E; -constexpr unsigned int mmMC_DC_INTERFACE_NACK_STATUS__VI = 0x0313; -constexpr unsigned int mmMC_FUS_ARB_GARLIC_CNTL__VI = 0x0A20; -constexpr unsigned int mmMC_FUS_ARB_GARLIC_ISOC_PRI__VI = 0x0A1F; -constexpr unsigned int mmMC_FUS_ARB_GARLIC_WR_PRI__VI = 0x0A21; -constexpr unsigned int mmMC_FUS_ARB_GARLIC_WR_PRI2__VI = 0x0A22; -constexpr unsigned int mmMC_FUS_DRAM0_BANK_ADDR_MAPPING__VI = 0x0A11; -constexpr unsigned int mmMC_FUS_DRAM0_CS0_BASE__VI = 0x0A05; -constexpr unsigned int mmMC_FUS_DRAM0_CS1_BASE__VI = 0x0A07; -constexpr unsigned int mmMC_FUS_DRAM0_CS2_BASE__VI = 0x0A09; -constexpr unsigned int mmMC_FUS_DRAM0_CS3_BASE__VI = 0x0A0B; -constexpr unsigned int mmMC_FUS_DRAM0_CTL_BASE__VI = 0x0A13; -constexpr unsigned int mmMC_FUS_DRAM0_CTL_LIMIT__VI = 0x0A15; -constexpr unsigned int mmMC_FUS_DRAM1_BANK_ADDR_MAPPING__VI = 0x0A12; -constexpr unsigned int mmMC_FUS_DRAM1_CS0_BASE__VI = 0x0A06; -constexpr unsigned int mmMC_FUS_DRAM1_CS1_BASE__VI = 0x0A08; -constexpr unsigned int mmMC_FUS_DRAM1_CS2_BASE__VI = 0x0A0A; -constexpr unsigned int mmMC_FUS_DRAM1_CS3_BASE__VI = 0x0A0C; -constexpr unsigned int mmMC_FUS_DRAM1_CTL_BASE__VI = 0x0A14; -constexpr unsigned int mmMC_FUS_DRAM1_CTL_LIMIT__VI = 0x0A16; -constexpr unsigned int mmMC_FUS_DRAM_APER_BASE__VI = 0x0A1A; -constexpr unsigned int mmMC_FUS_DRAM_APER_DEF__VI = 0x0A1E; -constexpr unsigned int mmMC_FUS_DRAM_APER_TOP__VI = 0x0A1B; -constexpr unsigned int mmMC_FUS_DRAM_CTL_HIGH_01__VI = 0x0A17; -constexpr unsigned int mmMC_FUS_DRAM_CTL_HIGH_23__VI = 0x0A18; -constexpr unsigned int mmMC_FUS_DRAM_MODE__VI = 0x0A19; -constexpr unsigned int mmMC_GRUB_FEATURES__VI = 0x0A36; -constexpr unsigned int mmMC_GRUB_PERFCOUNTER0_CFG__VI = 0x07E6; -constexpr unsigned int mmMC_GRUB_PERFCOUNTER1_CFG__VI = 0x07E7; -constexpr unsigned int mmMC_GRUB_PERFCOUNTER_HI__VI = 0x07E5; -constexpr unsigned int mmMC_GRUB_PERFCOUNTER_LO__VI = 0x07E4; -constexpr unsigned int mmMC_GRUB_PERFCOUNTER_RSLT_CNTL__VI = 0x07E8; -constexpr unsigned int mmMC_GRUB_POST_PROBE_DELAY__VI = 0x0A34; -constexpr unsigned int mmMC_GRUB_PROBE_CREDITS__VI = 0x0A35; -constexpr unsigned int mmMC_GRUB_PROBE_MAP__VI = 0x0A33; -constexpr unsigned int mmMC_GRUB_TCB_DATA_HI__VI = 0x0A3A; -constexpr unsigned int mmMC_GRUB_TCB_DATA_LO__VI = 0x0A39; -constexpr unsigned int mmMC_GRUB_TCB_INDEX__VI = 0x0A38; -constexpr unsigned int mmMC_GRUB_TX_CREDITS__VI = 0x0A37; -constexpr unsigned int mmMC_HUB_MISC_ATOMIC_IDLE_STATUS__VI = 0x084F; -constexpr unsigned int mmMC_HUB_RDREQ_ACPG__VI = 0x0881; -constexpr unsigned int mmMC_HUB_RDREQ_ACPO__VI = 0x0882; -constexpr unsigned int mmMC_HUB_RDREQ_BYPASS_GBL0__VI = 0x084C; -constexpr unsigned int mmMC_HUB_RDREQ_DMIF__VI = 0x0862; -constexpr unsigned int mmMC_HUB_RDREQ_HDP__VI = 0x085A; -constexpr unsigned int mmMC_HUB_RDREQ_ISP_CCPU__VI = 0x0DE2; -constexpr unsigned int mmMC_HUB_RDREQ_ISP_MPM__VI = 0x0DE1; -constexpr unsigned int mmMC_HUB_RDREQ_ISP_SPM__VI = 0x0DE0; -constexpr unsigned int mmMC_HUB_RDREQ_MCDS__VI = 0x0DE7; -constexpr unsigned int mmMC_HUB_RDREQ_MCDT__VI = 0x0DE8; -constexpr unsigned int mmMC_HUB_RDREQ_MCDU__VI = 0x0DE9; -constexpr unsigned int mmMC_HUB_RDREQ_MCDV__VI = 0x0DEA; -constexpr unsigned int mmMC_HUB_RDREQ_MCIF__VI = 0x0863; -constexpr unsigned int mmMC_HUB_RDREQ_RLC__VI = 0x085C; -constexpr unsigned int mmMC_HUB_RDREQ_SAMMSP__VI = 0x0883; -constexpr unsigned int mmMC_HUB_RDREQ_SDMA0__VI = 0x0859; -constexpr unsigned int mmMC_HUB_RDREQ_SDMA1__VI = 0x085B; -constexpr unsigned int mmMC_HUB_RDREQ_SEM__VI = 0x085D; -constexpr unsigned int mmMC_HUB_RDREQ_TLS__VI = 0x0861; -constexpr unsigned int mmMC_HUB_RDREQ_UMC__VI = 0x085F; -constexpr unsigned int mmMC_HUB_RDREQ_UVD__VI = 0x0860; -constexpr unsigned int mmMC_HUB_RDREQ_VCE0__VI = 0x085E; -constexpr unsigned int mmMC_HUB_RDREQ_VCE1__VI = 0x0DFC; -constexpr unsigned int mmMC_HUB_RDREQ_VCEU0__VI = 0x0865; -constexpr unsigned int mmMC_HUB_RDREQ_VCEU1__VI = 0x0DFD; -constexpr unsigned int mmMC_HUB_RDREQ_VMC__VI = 0x0864; -constexpr unsigned int mmMC_HUB_RDREQ_VP8__VI = 0x0884; -constexpr unsigned int mmMC_HUB_RDREQ_VP8U__VI = 0x0885; -constexpr unsigned int mmMC_HUB_RDREQ_XDMAM__VI = 0x0880; -constexpr unsigned int mmMC_HUB_WDP_ACPG__VI = 0x0885; -constexpr unsigned int mmMC_HUB_WDP_ACPO__VI = 0x0886; -constexpr unsigned int mmMC_HUB_WDP_BP2__VI = 0x0DFB; -constexpr unsigned int mmMC_HUB_WDP_BYPASS_GBL0__VI = 0x084A; -constexpr unsigned int mmMC_HUB_WDP_BYPASS_GBL1__VI = 0x084B; -constexpr unsigned int mmMC_HUB_WDP_CREDITS2__VI = 0x0840; -constexpr unsigned int mmMC_HUB_WDP_CREDITS3__VI = 0x0843; -constexpr unsigned int mmMC_HUB_WDP_CREDITS_MCDS__VI = 0x0DF7; -constexpr unsigned int mmMC_HUB_WDP_CREDITS_MCDT__VI = 0x0DF8; -constexpr unsigned int mmMC_HUB_WDP_CREDITS_MCDU__VI = 0x0DF9; -constexpr unsigned int mmMC_HUB_WDP_CREDITS_MCDV__VI = 0x0DFA; -constexpr unsigned int mmMC_HUB_WDP_CREDITS_MCDW__VI = 0x0DF3; -constexpr unsigned int mmMC_HUB_WDP_CREDITS_MCDX__VI = 0x0DF4; -constexpr unsigned int mmMC_HUB_WDP_CREDITS_MCDY__VI = 0x0DF5; -constexpr unsigned int mmMC_HUB_WDP_CREDITS_MCDZ__VI = 0x0DF6; -constexpr unsigned int mmMC_HUB_WDP_HDP__VI = 0x0877; -constexpr unsigned int mmMC_HUB_WDP_IH__VI = 0x0870; -constexpr unsigned int mmMC_HUB_WDP_ISP_CCPU__VI = 0x0DE6; -constexpr unsigned int mmMC_HUB_WDP_ISP_MPM__VI = 0x0DE5; -constexpr unsigned int mmMC_HUB_WDP_ISP_MPS__VI = 0x0DE4; -constexpr unsigned int mmMC_HUB_WDP_ISP_SPM__VI = 0x0DE3; -constexpr unsigned int mmMC_HUB_WDP_MCDS__VI = 0x0DEB; -constexpr unsigned int mmMC_HUB_WDP_MCDT__VI = 0x0DEC; -constexpr unsigned int mmMC_HUB_WDP_MCDU__VI = 0x0DED; -constexpr unsigned int mmMC_HUB_WDP_MCDV__VI = 0x0DEE; -constexpr unsigned int mmMC_HUB_WDP_MCDW__VI = 0x0866; -constexpr unsigned int mmMC_HUB_WDP_MCDX__VI = 0x0867; -constexpr unsigned int mmMC_HUB_WDP_MCDY__VI = 0x0868; -constexpr unsigned int mmMC_HUB_WDP_MCDZ__VI = 0x0869; -constexpr unsigned int mmMC_HUB_WDP_MCIF__VI = 0x086D; -constexpr unsigned int mmMC_HUB_WDP_RLC__VI = 0x0871; -constexpr unsigned int mmMC_HUB_WDP_SAMMSP__VI = 0x0887; -constexpr unsigned int mmMC_HUB_WDP_SDMA0__VI = 0x0878; -constexpr unsigned int mmMC_HUB_WDP_SDMA1__VI = 0x086B; -constexpr unsigned int mmMC_HUB_WDP_SEM__VI = 0x0872; -constexpr unsigned int mmMC_HUB_WDP_SH0__VI = 0x086C; -constexpr unsigned int mmMC_HUB_WDP_SH1__VI = 0x0874; -constexpr unsigned int mmMC_HUB_WDP_SIP__VI = 0x086A; -constexpr unsigned int mmMC_HUB_WDP_SMU__VI = 0x0873; -constexpr unsigned int mmMC_HUB_WDP_UMC__VI = 0x0875; -constexpr unsigned int mmMC_HUB_WDP_UVD__VI = 0x0876; -constexpr unsigned int mmMC_HUB_WDP_VCE0__VI = 0x086E; -constexpr unsigned int mmMC_HUB_WDP_VCE1__VI = 0x0DFE; -constexpr unsigned int mmMC_HUB_WDP_VCEU0__VI = 0x087D; -constexpr unsigned int mmMC_HUB_WDP_VCEU1__VI = 0x0DFF; -constexpr unsigned int mmMC_HUB_WDP_VIN0__VI = 0x0850; -constexpr unsigned int mmMC_HUB_WDP_VP8__VI = 0x0888; -constexpr unsigned int mmMC_HUB_WDP_VP8U__VI = 0x088A; -constexpr unsigned int mmMC_HUB_WDP_XDMA__VI = 0x087F; -constexpr unsigned int mmMC_HUB_WDP_XDMAM__VI = 0x087E; -constexpr unsigned int mmMC_HUB_WDP_XDP__VI = 0x086F; -constexpr unsigned int mmMC_HUB_WRRET_MCDS__VI = 0x0DEF; -constexpr unsigned int mmMC_HUB_WRRET_MCDT__VI = 0x0DF0; -constexpr unsigned int mmMC_HUB_WRRET_MCDU__VI = 0x0DF1; -constexpr unsigned int mmMC_HUB_WRRET_MCDV__VI = 0x0DF2; -constexpr unsigned int mmMC_HUB_WRRET_MCDW__VI = 0x0879; -constexpr unsigned int mmMC_HUB_WRRET_MCDX__VI = 0x087A; -constexpr unsigned int mmMC_HUB_WRRET_MCDY__VI = 0x087B; -constexpr unsigned int mmMC_HUB_WRRET_MCDZ__VI = 0x087C; -constexpr unsigned int mmMC_PMG_CFG__SI__CI = 0x0A84; -constexpr unsigned int mmMC_PMG_CFG__VI = 0x0A54; -constexpr unsigned int mmMC_PMG_CMD_EMRS__SI__CI = 0x0A83; -constexpr unsigned int mmMC_PMG_CMD_EMRS__VI = 0x0A4A; -constexpr unsigned int mmMC_PMG_CMD_MRS__SI__CI = 0x0AAB; -constexpr unsigned int mmMC_PMG_CMD_MRS__VI = 0x0A4C; -constexpr unsigned int mmMC_PMG_CMD_MRS1__SI__CI = 0x0AD1; -constexpr unsigned int mmMC_PMG_CMD_MRS1__VI = 0x0A4E; -constexpr unsigned int mmMC_PMG_CMD_MRS2__SI__CI = 0x0AD7; -constexpr unsigned int mmMC_PMG_CMD_MRS2__VI = 0x0A50; -constexpr unsigned int mmMC_RPB_TCI_CNTL__VI = 0x095C; -constexpr unsigned int mmMC_RPB_TCI_CNTL2__VI = 0x095D; -constexpr unsigned int mmMC_SEQ_CAS_TIMING__SI__CI = 0x0A29; -constexpr unsigned int mmMC_SEQ_CAS_TIMING__VI = 0x0A2B; -constexpr unsigned int mmMC_SEQ_CAS_TIMING_LP__SI__CI = 0x0A9C; -constexpr unsigned int mmMC_SEQ_CAS_TIMING_LP__VI = 0x0A2C; -constexpr unsigned int mmMC_SEQ_CG__SI__CI = 0x0A9A; -constexpr unsigned int mmMC_SEQ_CG__VI = 0x0A7B; -constexpr unsigned int mmMC_SEQ_CMD__SI__CI = 0x0A31; -constexpr unsigned int mmMC_SEQ_CMD__VI = 0x0A47; -constexpr unsigned int mmMC_SEQ_CNTL__SI__CI = 0x0A25; -constexpr unsigned int mmMC_SEQ_CNTL__VI = 0x0A24; -constexpr unsigned int mmMC_SEQ_CNTL_2__SI__CI = 0x0AD4; -constexpr unsigned int mmMC_SEQ_CNTL_2__VI = 0x0A25; -constexpr unsigned int mmMC_SEQ_CNTL_3__VI = 0x0A26; -constexpr unsigned int mmMC_SEQ_DRAM__SI__CI = 0x0A26; -constexpr unsigned int mmMC_SEQ_DRAM__VI = 0x0A27; -constexpr unsigned int mmMC_SEQ_DRAM_2__SI__CI = 0x0A27; -constexpr unsigned int mmMC_SEQ_DRAM_2__VI = 0x0A28; -constexpr unsigned int mmMC_SEQ_FIFO_CTL__SI__CI = 0x0A57; -constexpr unsigned int mmMC_SEQ_FIFO_CTL__VI = 0x0A5D; -constexpr unsigned int mmMC_SEQ_IO_DEBUG_DATA__SI__CI = 0x0A92; -constexpr unsigned int mmMC_SEQ_IO_DEBUG_DATA__VI = 0x0ABD; -constexpr unsigned int mmMC_SEQ_IO_DEBUG_INDEX__SI__CI = 0x0A91; -constexpr unsigned int mmMC_SEQ_IO_DEBUG_INDEX__VI = 0x0ABC; -constexpr unsigned int mmMC_SEQ_IO_RESERVE__VI = 0x0A61; -constexpr unsigned int mmMC_SEQ_MISC0__SI__CI = 0x0A80; -constexpr unsigned int mmMC_SEQ_MISC0__VI = 0x0A71; -constexpr unsigned int mmMC_SEQ_MISC1__SI__CI = 0x0A81; -constexpr unsigned int mmMC_SEQ_MISC1__VI = 0x0A72; -constexpr unsigned int mmMC_SEQ_MISC3__SI__CI = 0x0A8B; -constexpr unsigned int mmMC_SEQ_MISC3__VI = 0x0A74; -constexpr unsigned int mmMC_SEQ_MISC4__SI__CI = 0x0A8C; -constexpr unsigned int mmMC_SEQ_MISC4__VI = 0x0A75; -constexpr unsigned int mmMC_SEQ_MISC5__SI__CI = 0x0A95; -constexpr unsigned int mmMC_SEQ_MISC5__VI = 0x0A76; -constexpr unsigned int mmMC_SEQ_MISC6__SI__CI = 0x0A96; -constexpr unsigned int mmMC_SEQ_MISC6__VI = 0x0A77; -constexpr unsigned int mmMC_SEQ_MISC7__SI__CI = 0x0A99; -constexpr unsigned int mmMC_SEQ_MISC7__VI = 0x0A78; -constexpr unsigned int mmMC_SEQ_MISC8__SI__CI = 0x0A5F; -constexpr unsigned int mmMC_SEQ_MISC8__VI = 0x0A79; -constexpr unsigned int mmMC_SEQ_MISC9__SI__CI = 0x0AE7; -constexpr unsigned int mmMC_SEQ_MISC9__VI = 0x0A7A; -constexpr unsigned int mmMC_SEQ_MISC_TIMING__SI__CI = 0x0A2A; -constexpr unsigned int mmMC_SEQ_MISC_TIMING__VI = 0x0A2D; -constexpr unsigned int mmMC_SEQ_MISC_TIMING2__SI__CI = 0x0A2B; -constexpr unsigned int mmMC_SEQ_MISC_TIMING2__VI = 0x0A2F; -constexpr unsigned int mmMC_SEQ_MISC_TIMING2_LP__SI__CI = 0x0A9E; -constexpr unsigned int mmMC_SEQ_MISC_TIMING2_LP__VI = 0x0A30; -constexpr unsigned int mmMC_SEQ_MISC_TIMING_LP__SI__CI = 0x0A9D; -constexpr unsigned int mmMC_SEQ_MISC_TIMING_LP__VI = 0x0A2E; -constexpr unsigned int mmMC_SEQ_PMG_TIMING__SI__CI = 0x0A2C; -constexpr unsigned int mmMC_SEQ_PMG_TIMING__VI = 0x0A31; -constexpr unsigned int mmMC_SEQ_PMG_TIMING_LP__SI__CI = 0x0AD3; -constexpr unsigned int mmMC_SEQ_PMG_TIMING_LP__VI = 0x0A32; -constexpr unsigned int mmMC_SEQ_RAS_TIMING__SI__CI = 0x0A28; -constexpr unsigned int mmMC_SEQ_RAS_TIMING__VI = 0x0A29; -constexpr unsigned int mmMC_SEQ_RAS_TIMING_LP__SI__CI = 0x0A9B; -constexpr unsigned int mmMC_SEQ_RAS_TIMING_LP__VI = 0x0A2A; -constexpr unsigned int mmMC_SEQ_RD_CTL_D0__SI__CI = 0x0A2D; -constexpr unsigned int mmMC_SEQ_RD_CTL_D0__VI = 0x0A33; -constexpr unsigned int mmMC_SEQ_RD_CTL_D0_LP__SI__CI = 0x0AC7; -constexpr unsigned int mmMC_SEQ_RD_CTL_D0_LP__VI = 0x0A34; -constexpr unsigned int mmMC_SEQ_RD_CTL_D1__SI__CI = 0x0A2E; -constexpr unsigned int mmMC_SEQ_RD_CTL_D1__VI = 0x0A35; -constexpr unsigned int mmMC_SEQ_RD_CTL_D1_LP__SI__CI = 0x0AC8; -constexpr unsigned int mmMC_SEQ_RD_CTL_D1_LP__VI = 0x0A36; -constexpr unsigned int mmMC_SEQ_RESERVE_0_S__SI__CI = 0x0A1E; -constexpr unsigned int mmMC_SEQ_RESERVE_0_S__VI = 0x0A07; -constexpr unsigned int mmMC_SEQ_RESERVE_1_S__SI__CI = 0x0A1F; -constexpr unsigned int mmMC_SEQ_RESERVE_1_S__VI = 0x0A08; -constexpr unsigned int mmMC_SEQ_RESERVE_M__SI__CI = 0x0A82; -constexpr unsigned int mmMC_SEQ_RESERVE_M__VI = 0x0A60; -constexpr unsigned int mmMC_SEQ_SREG_READ__VI = 0x0A7F; -constexpr unsigned int mmMC_SEQ_SREG_STATUS__VI = 0x0A80; -constexpr unsigned int mmMC_SEQ_STATUS_M__SI__CI = 0x0A7D; -constexpr unsigned int mmMC_SEQ_STATUS_M__VI = 0x0A5E; -constexpr unsigned int mmMC_SEQ_STATUS_S__SI__CI = 0x0A20; -constexpr unsigned int mmMC_SEQ_STATUS_S__VI = 0x0A05; -constexpr unsigned int mmMC_SEQ_SUP_CNTL__SI__CI = 0x0A32; -constexpr unsigned int mmMC_SEQ_SUP_CNTL__VI = 0x0A63; -constexpr unsigned int mmMC_SEQ_SUP_DEC_STAT__SI__CI = 0x0A88; -constexpr unsigned int mmMC_SEQ_SUP_DEC_STAT__VI = 0x0A6A; -constexpr unsigned int mmMC_SEQ_SUP_GP0_STAT__SI__CI = 0x0A8F; -constexpr unsigned int mmMC_SEQ_SUP_GP0_STAT__VI = 0x0A65; -constexpr unsigned int mmMC_SEQ_SUP_GP1_STAT__SI__CI = 0x0A90; -constexpr unsigned int mmMC_SEQ_SUP_GP1_STAT__VI = 0x0A66; -constexpr unsigned int mmMC_SEQ_SUP_GP2_STAT__SI__CI = 0x0A85; -constexpr unsigned int mmMC_SEQ_SUP_GP2_STAT__VI = 0x0A67; -constexpr unsigned int mmMC_SEQ_SUP_GP3_STAT__SI__CI = 0x0A86; -constexpr unsigned int mmMC_SEQ_SUP_GP3_STAT__VI = 0x0A68; -constexpr unsigned int mmMC_SEQ_SUP_IR_STAT__SI__CI = 0x0A87; -constexpr unsigned int mmMC_SEQ_SUP_IR_STAT__VI = 0x0A69; -constexpr unsigned int mmMC_SEQ_SUP_PGM__SI__CI = 0x0A33; -constexpr unsigned int mmMC_SEQ_SUP_PGM__VI = 0x0A64; -constexpr unsigned int mmMC_SEQ_SUP_PGM_STAT__SI__CI = 0x0A89; -constexpr unsigned int mmMC_SEQ_SUP_PGM_STAT__VI = 0x0A6B; -constexpr unsigned int mmMC_SEQ_SUP_R_PGM__SI__CI = 0x0A8A; -constexpr unsigned int mmMC_SEQ_SUP_R_PGM__VI = 0x0A6C; -constexpr unsigned int mmMC_SEQ_TIMER_RD__SI__CI = 0x0ACA; -constexpr unsigned int mmMC_SEQ_TIMER_RD__VI = 0x0A7D; -constexpr unsigned int mmMC_SEQ_TIMER_WR__SI__CI = 0x0AC9; -constexpr unsigned int mmMC_SEQ_TIMER_WR__VI = 0x0A7C; -constexpr unsigned int mmMC_SEQ_TRAIN_CAPTURE__SI__CI = 0x0A3E; -constexpr unsigned int mmMC_SEQ_TRAIN_CAPTURE__VI = 0x0A5B; -constexpr unsigned int mmMC_SEQ_TRAIN_WAKEUP_CLEAR__SI__CI = 0x0A3F; -constexpr unsigned int mmMC_SEQ_TRAIN_WAKEUP_CLEAR__VI = 0x0A5C; -constexpr unsigned int mmMC_SEQ_TRAIN_WAKEUP_CNTL__SI__CI = 0x0A3A; -constexpr unsigned int mmMC_SEQ_TRAIN_WAKEUP_CNTL__VI = 0x0A57; -constexpr unsigned int mmMC_SEQ_TRAIN_WAKEUP_EDGE__SI__CI = 0x0A3C; -constexpr unsigned int mmMC_SEQ_TRAIN_WAKEUP_EDGE__VI = 0x0A58; -constexpr unsigned int mmMC_SEQ_TRAIN_WAKEUP_MASK__SI__CI = 0x0A3D; -constexpr unsigned int mmMC_SEQ_TRAIN_WAKEUP_MASK__VI = 0x0A59; -constexpr unsigned int mmMC_SEQ_WR_CTL_D0__SI__CI = 0x0A2F; -constexpr unsigned int mmMC_SEQ_WR_CTL_D0__VI = 0x0A3B; -constexpr unsigned int mmMC_SEQ_WR_CTL_D0_LP__SI__CI = 0x0A9F; -constexpr unsigned int mmMC_SEQ_WR_CTL_D0_LP__VI = 0x0A3C; -constexpr unsigned int mmMC_SEQ_WR_CTL_D1__SI__CI = 0x0A30; -constexpr unsigned int mmMC_SEQ_WR_CTL_D1__VI = 0x0A3D; -constexpr unsigned int mmMC_SEQ_WR_CTL_D1_LP__SI__CI = 0x0AA0; -constexpr unsigned int mmMC_SEQ_WR_CTL_D1_LP__VI = 0x0A3E; -constexpr unsigned int mmMC_SHARED_ACTIVE_FCN_ID__VI = 0x081F; -constexpr unsigned int mmMC_SHARED_CHREMAP2__VI = 0x081C; -constexpr unsigned int mmMC_SHARED_VF_ENABLE__VI = 0x081D; -constexpr unsigned int mmMC_SHARED_VIRT_RESET_REQ__VI = 0x081E; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF0__VI = 0xF980; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF1__VI = 0xF981; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF10__VI = 0xF98A; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF11__VI = 0xF98B; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF12__VI = 0xF98C; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF13__VI = 0xF98D; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF14__VI = 0xF98E; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF15__VI = 0xF98F; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF2__VI = 0xF982; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF3__VI = 0xF983; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF4__VI = 0xF984; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF5__VI = 0xF985; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF6__VI = 0xF986; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF7__VI = 0xF987; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF8__VI = 0xF988; -constexpr unsigned int mmMC_VM_FB_SIZE_OFFSET_VF9__VI = 0xF989; -constexpr unsigned int mmMC_VM_MARC_BASE_HI_0__VI = 0xF999; -constexpr unsigned int mmMC_VM_MARC_BASE_HI_1__VI = 0xF99F; -constexpr unsigned int mmMC_VM_MARC_BASE_HI_2__VI = 0xF9A5; -constexpr unsigned int mmMC_VM_MARC_BASE_HI_3__VI = 0xF9AB; -constexpr unsigned int mmMC_VM_MARC_BASE_LO_0__VI = 0xF998; -constexpr unsigned int mmMC_VM_MARC_BASE_LO_1__VI = 0xF99E; -constexpr unsigned int mmMC_VM_MARC_BASE_LO_2__VI = 0xF9A4; -constexpr unsigned int mmMC_VM_MARC_BASE_LO_3__VI = 0xF9AA; -constexpr unsigned int mmMC_VM_MARC_CNTL__VI = 0xF9B0; -constexpr unsigned int mmMC_VM_MARC_LEN_HI_0__VI = 0xF99D; -constexpr unsigned int mmMC_VM_MARC_LEN_HI_1__VI = 0xF9A3; -constexpr unsigned int mmMC_VM_MARC_LEN_HI_2__VI = 0xF9A9; -constexpr unsigned int mmMC_VM_MARC_LEN_HI_3__VI = 0xF9AF; -constexpr unsigned int mmMC_VM_MARC_LEN_LO_0__VI = 0xF99C; -constexpr unsigned int mmMC_VM_MARC_LEN_LO_1__VI = 0xF9A2; -constexpr unsigned int mmMC_VM_MARC_LEN_LO_2__VI = 0xF9A8; -constexpr unsigned int mmMC_VM_MARC_LEN_LO_3__VI = 0xF9AE; -constexpr unsigned int mmMC_VM_MARC_RELOC_HI_0__VI = 0xF99B; -constexpr unsigned int mmMC_VM_MARC_RELOC_HI_1__VI = 0xF9A1; -constexpr unsigned int mmMC_VM_MARC_RELOC_HI_2__VI = 0xF9A7; -constexpr unsigned int mmMC_VM_MARC_RELOC_HI_3__VI = 0xF9AD; -constexpr unsigned int mmMC_VM_MARC_RELOC_LO_0__VI = 0xF99A; -constexpr unsigned int mmMC_VM_MARC_RELOC_LO_1__VI = 0xF9A0; -constexpr unsigned int mmMC_VM_MARC_RELOC_LO_2__VI = 0xF9A6; -constexpr unsigned int mmMC_VM_MARC_RELOC_LO_3__VI = 0xF9AC; -constexpr unsigned int mmMC_VM_MB_L1_TLB1_DEBUG__VI = 0x0892; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_CNTL0__VI = 0xF9B1; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_CNTL1__VI = 0xF9B4; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_CNTL2__VI = 0xF9B7; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_CNTL3__VI = 0xF9BA; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_CNTL4__VI = 0xF9BD; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_CNTL5__VI = 0xF9C0; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_CNTL6__VI = 0xF9C3; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_CNTL7__VI = 0xF9C6; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_CNTL8__VI = 0xF9C9; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_END_ADDR0__VI = 0xF9B3; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_END_ADDR1__VI = 0xF9B6; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_END_ADDR2__VI = 0xF9B9; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_END_ADDR3__VI = 0xF9BC; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_END_ADDR4__VI = 0xF9BF; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_END_ADDR5__VI = 0xF9C2; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_END_ADDR6__VI = 0xF9C5; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_END_ADDR7__VI = 0xF9C8; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_END_ADDR8__VI = 0xF9CB; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__VI = 0xF9CD; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VI = 0xF9CC; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_START_ADDR0__VI = 0xF9B2; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_START_ADDR1__VI = 0xF9B5; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_START_ADDR2__VI = 0xF9B8; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_START_ADDR3__VI = 0xF9BB; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_START_ADDR4__VI = 0xF9BE; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_START_ADDR5__VI = 0xF9C1; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_START_ADDR6__VI = 0xF9C4; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_START_ADDR7__VI = 0xF9C7; -constexpr unsigned int mmMC_VM_MB_L1_TLS0_START_ADDR8__VI = 0xF9CA; -constexpr unsigned int mmMC_VM_NB_LOWER_TOP_OF_DRAM2__VI = 0xF995; -constexpr unsigned int mmMC_VM_NB_MMIOBASE__VI = 0xF990; -constexpr unsigned int mmMC_VM_NB_MMIOLIMIT__VI = 0xF991; -constexpr unsigned int mmMC_VM_NB_PCI_ARB__VI = 0xF993; -constexpr unsigned int mmMC_VM_NB_PCI_CTRL__VI = 0xF992; -constexpr unsigned int mmMC_VM_NB_TOP_OF_DRAM3__VI = 0xF997; -constexpr unsigned int mmMC_VM_NB_TOP_OF_DRAM_SLOT1__VI = 0xF994; -constexpr unsigned int mmMC_VM_NB_UPPER_TOP_OF_DRAM2__VI = 0xF996; -constexpr unsigned int mmMC_XBAR_FIFO_MON_CNTL0__VI = 0x0C8F; -constexpr unsigned int mmMC_XBAR_FIFO_MON_CNTL1__VI = 0x0C90; -constexpr unsigned int mmMC_XBAR_FIFO_MON_CNTL2__VI = 0x0C91; -constexpr unsigned int mmMC_XBAR_FIFO_MON_MAX_THSH__VI = 0x0C96; -constexpr unsigned int mmMC_XBAR_FIFO_MON_RSLT0__VI = 0x0C92; -constexpr unsigned int mmMC_XBAR_FIFO_MON_RSLT1__VI = 0x0C93; -constexpr unsigned int mmMC_XBAR_FIFO_MON_RSLT2__VI = 0x0C94; -constexpr unsigned int mmMC_XBAR_FIFO_MON_RSLT3__VI = 0x0C95; -constexpr unsigned int mmMICROSECOND_TIME_BASE_DIV__VI = 0x013B; -constexpr unsigned int mmMILLISECOND_TIME_BASE_DIV__VI = 0x0130; -constexpr unsigned int mmMP_FPS_CNT__VI = 0x0235; -constexpr unsigned int mmMVP_AFR_FLIP_FIFO_CNTL__VI = 0x1AE1; -constexpr unsigned int mmMVP_AFR_FLIP_MODE__VI = 0x1AE0; -constexpr unsigned int mmMVP_BLACK_KEYER__VI = 0x02B2; -constexpr unsigned int mmMVP_CONTROL1__VI = 0x02AC; -constexpr unsigned int mmMVP_CONTROL2__VI = 0x02AD; -constexpr unsigned int mmMVP_CONTROL3__VI = 0x02B6; -constexpr unsigned int mmMVP_CRC_CNTL__VI = 0x02B3; -constexpr unsigned int mmMVP_CRC_RESULT_BLUE_GREEN__VI = 0x02B4; -constexpr unsigned int mmMVP_CRC_RESULT_RED__VI = 0x02B5; -constexpr unsigned int mmMVP_DEBUG__VI = 0x02BB; -constexpr unsigned int mmMVP_FIFO_CONTROL__VI = 0x02AE; -constexpr unsigned int mmMVP_FIFO_STATUS__VI = 0x02AF; -constexpr unsigned int mmMVP_FLIP_LINE_NUM_INSERT__VI = 0x1AE2; -constexpr unsigned int mmMVP_INBAND_CNTL_CAP__VI = 0x02B1; -constexpr unsigned int mmMVP_RECEIVE_CNT_CNTL1__VI = 0x02B7; -constexpr unsigned int mmMVP_RECEIVE_CNT_CNTL2__VI = 0x02B8; -constexpr unsigned int mmMVP_SLAVE_STATUS__VI = 0x02B0; -constexpr unsigned int mmMVP_TEST_DEBUG_DATA__VI = 0x02BA; -constexpr unsigned int mmMVP_TEST_DEBUG_INDEX__VI = 0x02B9; -constexpr unsigned int mmOUTPUT_CSC_C11_C12__VI = 0x1A3D; -constexpr unsigned int mmOUTPUT_CSC_C11_C12_A__VI = 0x46B7; -constexpr unsigned int mmOUTPUT_CSC_C11_C12_B__VI = 0x46BD; -constexpr unsigned int mmOUTPUT_CSC_C13_C14__VI = 0x1A3E; -constexpr unsigned int mmOUTPUT_CSC_C13_C14_A__VI = 0x46B8; -constexpr unsigned int mmOUTPUT_CSC_C13_C14_B__VI = 0x46BE; -constexpr unsigned int mmOUTPUT_CSC_C21_C22__VI = 0x1A3F; -constexpr unsigned int mmOUTPUT_CSC_C21_C22_A__VI = 0x46B9; -constexpr unsigned int mmOUTPUT_CSC_C21_C22_B__VI = 0x46BF; -constexpr unsigned int mmOUTPUT_CSC_C23_C24__VI = 0x1A40; -constexpr unsigned int mmOUTPUT_CSC_C23_C24_A__VI = 0x46BA; -constexpr unsigned int mmOUTPUT_CSC_C23_C24_B__VI = 0x46C0; -constexpr unsigned int mmOUTPUT_CSC_C31_C32__VI = 0x1A41; -constexpr unsigned int mmOUTPUT_CSC_C31_C32_A__VI = 0x46BB; -constexpr unsigned int mmOUTPUT_CSC_C31_C32_B__VI = 0x46C1; -constexpr unsigned int mmOUTPUT_CSC_C33_C34__VI = 0x1A42; -constexpr unsigned int mmOUTPUT_CSC_C33_C34_A__VI = 0x46BC; -constexpr unsigned int mmOUTPUT_CSC_C33_C34_B__VI = 0x46C2; -constexpr unsigned int mmOUTPUT_CSC_CONTROL__VI = 0x1A3C; -constexpr unsigned int mmOUT_CLAMP_CONTROL_B_CB__VI = 0x1A9D; -constexpr unsigned int mmOUT_CLAMP_CONTROL_G_Y__VI = 0x1A9C; -constexpr unsigned int mmOUT_CLAMP_CONTROL_R_CR__VI = 0x1A52; -constexpr unsigned int mmOUT_ROUND_CONTROL__VI = 0x1A51; -constexpr unsigned int mmOVL_SECONDARY_SURFACE_ADDRESS__VI = 0x1A92; -constexpr unsigned int mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI = 0x1A94; -constexpr unsigned int mmOVL_STEREOSYNC_FLIP__VI = 0x1A93; -constexpr unsigned int mmPCIE_EFUSE__VI = 0x0FC0; -constexpr unsigned int mmPCIE_EFUSE2__VI = 0x0FC1; -constexpr unsigned int mmPCIE_EFUSE3__VI = 0x0FC2; -constexpr unsigned int mmPCIE_EFUSE4__VI = 0x0FC3; -constexpr unsigned int mmPCIE_EFUSE5__VI = 0x0FC4; -constexpr unsigned int mmPCIE_EFUSE6__VI = 0x0FC5; -constexpr unsigned int mmPCIE_EFUSE7__VI = 0x0FC6; -constexpr unsigned int mmPERFCOUNTER_CNTL__VI = 0x0170; -constexpr unsigned int mmPERFCOUNTER_STATE__VI = 0x0171; -constexpr unsigned int mmPERFMON_CNTL__VI = 0x0173; -constexpr unsigned int mmPERFMON_CNTL2__VI = 0x017A; -constexpr unsigned int mmPERFMON_CVALUE_INT_MISC__VI = 0x0172; -constexpr unsigned int mmPERFMON_CVALUE_LOW__VI = 0x0174; -constexpr unsigned int mmPERFMON_HI__VI = 0x0175; -constexpr unsigned int mmPERFMON_LOW__VI = 0x0176; -constexpr unsigned int mmPERFMON_TEST_DEBUG_DATA__VI = 0x0178; -constexpr unsigned int mmPERFMON_TEST_DEBUG_INDEX__VI = 0x0177; -constexpr unsigned int mmPHY_AUX_CNTL__VI = 0x4897; -constexpr unsigned int mmPIPE0_ARBITRATION_CONTROL3__VI = 0x02FA; -constexpr unsigned int mmPIPE0_DMIF_BUFFER_CONTROL__VI = 0x0321; -constexpr unsigned int mmPIPE0_MAX_REQUESTS__VI = 0x0305; -constexpr unsigned int mmPIPE0_PG_CONFIG__VI = 0x02C0; -constexpr unsigned int mmPIPE0_PG_ENABLE__VI = 0x02C1; -constexpr unsigned int mmPIPE0_PG_STATUS__VI = 0x02C2; -constexpr unsigned int mmPIPE1_ARBITRATION_CONTROL3__VI = 0x02FB; -constexpr unsigned int mmPIPE1_DMIF_BUFFER_CONTROL__VI = 0x0322; -constexpr unsigned int mmPIPE1_MAX_REQUESTS__VI = 0x0306; -constexpr unsigned int mmPIPE1_PG_CONFIG__VI = 0x02C3; -constexpr unsigned int mmPIPE1_PG_ENABLE__VI = 0x02C4; -constexpr unsigned int mmPIPE1_PG_STATUS__VI = 0x02C5; -constexpr unsigned int mmPIPE2_ARBITRATION_CONTROL3__VI = 0x02FC; -constexpr unsigned int mmPIPE2_DMIF_BUFFER_CONTROL__VI = 0x0323; -constexpr unsigned int mmPIPE2_MAX_REQUESTS__VI = 0x0307; -constexpr unsigned int mmPIPE2_PG_CONFIG__VI = 0x02C6; -constexpr unsigned int mmPIPE2_PG_ENABLE__VI = 0x02C7; -constexpr unsigned int mmPIPE2_PG_STATUS__VI = 0x02C8; -constexpr unsigned int mmPIPE3_ARBITRATION_CONTROL3__VI = 0x02FD; -constexpr unsigned int mmPIPE3_DMIF_BUFFER_CONTROL__VI = 0x0324; -constexpr unsigned int mmPIPE3_MAX_REQUESTS__VI = 0x0308; -constexpr unsigned int mmPIPE3_PG_CONFIG__VI = 0x02C9; -constexpr unsigned int mmPIPE3_PG_ENABLE__VI = 0x02CA; -constexpr unsigned int mmPIPE3_PG_STATUS__VI = 0x02CB; -constexpr unsigned int mmPIPE4_ARBITRATION_CONTROL3__VI = 0x02FE; -constexpr unsigned int mmPIPE4_DMIF_BUFFER_CONTROL__VI = 0x0325; -constexpr unsigned int mmPIPE4_MAX_REQUESTS__VI = 0x0309; -constexpr unsigned int mmPIPE4_PG_CONFIG__VI = 0x02CC; -constexpr unsigned int mmPIPE4_PG_ENABLE__VI = 0x02CD; -constexpr unsigned int mmPIPE4_PG_STATUS__VI = 0x02CE; -constexpr unsigned int mmPIPE5_ARBITRATION_CONTROL3__VI = 0x02FF; -constexpr unsigned int mmPIPE5_DMIF_BUFFER_CONTROL__VI = 0x0326; -constexpr unsigned int mmPIPE5_MAX_REQUESTS__VI = 0x030A; -constexpr unsigned int mmPIPE5_PG_CONFIG__VI = 0x02CF; -constexpr unsigned int mmPIPE5_PG_ENABLE__VI = 0x02D0; -constexpr unsigned int mmPIPE5_PG_STATUS__VI = 0x02D1; -constexpr unsigned int mmPIPE6_ARBITRATION_CONTROL3__VI = 0x032A; -constexpr unsigned int mmPIPE6_MAX_REQUESTS__VI = 0x032C; -constexpr unsigned int mmPIPE7_ARBITRATION_CONTROL3__VI = 0x032B; -constexpr unsigned int mmPIPE7_MAX_REQUESTS__VI = 0x032D; -constexpr unsigned int mmPIXCLK0_RESYNC_CNTL__VI = 0x013A; -constexpr unsigned int mmPIXCLK1_RESYNC_CNTL__VI = 0x0138; -constexpr unsigned int mmPIXCLK2_RESYNC_CNTL__VI = 0x0139; -constexpr unsigned int mmPLL_ANALOG__VI = 0x1708; -constexpr unsigned int mmPLL_ANALOG_CNTL__VI = 0x1711; -constexpr unsigned int mmPLL_CNTL__VI = 0x1707; -constexpr unsigned int mmPLL_DEBUG_CNTL__VI = 0x170B; -constexpr unsigned int mmPLL_DS_CNTL__VI = 0x1705; -constexpr unsigned int mmPLL_FB_DIV__VI = 0x1701; -constexpr unsigned int mmPLL_IDCLK_CNTL__VI = 0x1706; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED0__VI = 0x1700; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED1__VI = 0x1701; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED10__VI = 0x170A; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED11__VI = 0x170B; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED12__VI = 0x170C; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED13__VI = 0x170D; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED14__VI = 0x170E; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED15__VI = 0x170F; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED16__VI = 0x1710; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED17__VI = 0x1711; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED18__VI = 0x1712; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED19__VI = 0x1713; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED2__VI = 0x1702; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED20__VI = 0x1714; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED21__VI = 0x1715; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED22__VI = 0x1716; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED23__VI = 0x1717; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED24__VI = 0x1718; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED25__VI = 0x1719; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED26__VI = 0x171A; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED27__VI = 0x171B; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED28__VI = 0x171C; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED29__VI = 0x171D; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED3__VI = 0x1703; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED30__VI = 0x171E; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED31__VI = 0x171F; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED32__VI = 0x1720; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED33__VI = 0x1721; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED34__VI = 0x1722; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED35__VI = 0x1723; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED36__VI = 0x1724; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED37__VI = 0x1725; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED38__VI = 0x1726; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED39__VI = 0x1727; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED4__VI = 0x1704; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED40__VI = 0x1728; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED41__VI = 0x1729; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED5__VI = 0x1705; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED6__VI = 0x1706; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED7__VI = 0x1707; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED8__VI = 0x1708; -constexpr unsigned int mmPLL_MACRO_CNTL_RESERVED9__VI = 0x1709; -constexpr unsigned int mmPLL_POST_DIV__VI = 0x1702; -constexpr unsigned int mmPLL_REF_DIV__VI = 0x1700; -constexpr unsigned int mmPLL_SS_AMOUNT_DSFRAC__VI = 0x1703; -constexpr unsigned int mmPLL_SS_CNTL__VI = 0x1704; -constexpr unsigned int mmPLL_UNLOCK_DETECT_CNTL__VI = 0x170A; -constexpr unsigned int mmPLL_UPDATE_CNTL__VI = 0x170D; -constexpr unsigned int mmPLL_UPDATE_LOCK__VI = 0x170C; -constexpr unsigned int mmPLL_VREG_CNTL__VI = 0x1709; -constexpr unsigned int mmPLL_XOR_LOCK__VI = 0x1710; -constexpr unsigned int mmPPLL_DEBUG_MUX_CNTL__VI = 0x1721; -constexpr unsigned int mmPPLL_DIV_UPDATE_DEBUG__VI = 0x171F; -constexpr unsigned int mmPPLL_SPARE0__VI = 0x1722; -constexpr unsigned int mmPPLL_SPARE1__VI = 0x1723; -constexpr unsigned int mmPPLL_STATUS_DEBUG__VI = 0x1720; -constexpr unsigned int mmPRESCALE_CONTROL__VI = 0x46B2; -constexpr unsigned int mmPRESCALE_GRPH_CONTROL__VI = 0x1A2D; -constexpr unsigned int mmPRESCALE_OVL_CONTROL__VI = 0x1A31; -constexpr unsigned int mmPRESCALE_VALUES_B__VI = 0x46B5; -constexpr unsigned int mmPRESCALE_VALUES_G__VI = 0x46B4; -constexpr unsigned int mmPRESCALE_VALUES_GRPH_B__VI = 0x1A30; -constexpr unsigned int mmPRESCALE_VALUES_GRPH_G__VI = 0x1A2F; -constexpr unsigned int mmPRESCALE_VALUES_GRPH_R__VI = 0x1A2E; -constexpr unsigned int mmPRESCALE_VALUES_OVL_CB__VI = 0x1A32; -constexpr unsigned int mmPRESCALE_VALUES_OVL_CR__VI = 0x1A34; -constexpr unsigned int mmPRESCALE_VALUES_OVL_Y__VI = 0x1A33; -constexpr unsigned int mmPRESCALE_VALUES_R__VI = 0x46B3; -constexpr unsigned int mmRAS_TA_SIGNATURE1__VI = 0x33A0; -constexpr unsigned int mmRBBMIF_STATUS__VI = 0x0315; -constexpr unsigned int mmRBBMIF_STATUS_FLAG__VI = 0x0327; -constexpr unsigned int mmRBBMIF_TIMEOUT__VI = 0x0314; -constexpr unsigned int mmRBBMIF_TIMEOUT_DIS__VI = 0x0316; -constexpr unsigned int mmREFCLK_CGTT_BLK_CTRL_REG__VI = 0x010B; -constexpr unsigned int mmREFCLK_CNTL__VI = 0x0109; -constexpr unsigned int mmREGAMMA_CNTLA_END_CNTL1__VI = 0x1AA6; -constexpr unsigned int mmREGAMMA_CNTLA_END_CNTL2__VI = 0x1AA7; -constexpr unsigned int mmREGAMMA_CNTLA_REGION_0_1__VI = 0x1AA8; -constexpr unsigned int mmREGAMMA_CNTLA_REGION_10_11__VI = 0x1AAD; -constexpr unsigned int mmREGAMMA_CNTLA_REGION_12_13__VI = 0x1AAE; -constexpr unsigned int mmREGAMMA_CNTLA_REGION_14_15__VI = 0x1AAF; -constexpr unsigned int mmREGAMMA_CNTLA_REGION_2_3__VI = 0x1AA9; -constexpr unsigned int mmREGAMMA_CNTLA_REGION_4_5__VI = 0x1AAA; -constexpr unsigned int mmREGAMMA_CNTLA_REGION_6_7__VI = 0x1AAB; -constexpr unsigned int mmREGAMMA_CNTLA_REGION_8_9__VI = 0x1AAC; -constexpr unsigned int mmREGAMMA_CNTLA_SLOPE_CNTL__VI = 0x1AA5; -constexpr unsigned int mmREGAMMA_CNTLA_START_CNTL__VI = 0x1AA4; -constexpr unsigned int mmREGAMMA_CNTLB_END_CNTL1__VI = 0x1AB2; -constexpr unsigned int mmREGAMMA_CNTLB_END_CNTL2__VI = 0x1AB3; -constexpr unsigned int mmREGAMMA_CNTLB_REGION_0_1__VI = 0x1AB4; -constexpr unsigned int mmREGAMMA_CNTLB_REGION_10_11__VI = 0x1AB9; -constexpr unsigned int mmREGAMMA_CNTLB_REGION_12_13__VI = 0x1ABA; -constexpr unsigned int mmREGAMMA_CNTLB_REGION_14_15__VI = 0x1ABB; -constexpr unsigned int mmREGAMMA_CNTLB_REGION_2_3__VI = 0x1AB5; -constexpr unsigned int mmREGAMMA_CNTLB_REGION_4_5__VI = 0x1AB6; -constexpr unsigned int mmREGAMMA_CNTLB_REGION_6_7__VI = 0x1AB7; -constexpr unsigned int mmREGAMMA_CNTLB_REGION_8_9__VI = 0x1AB8; -constexpr unsigned int mmREGAMMA_CNTLB_SLOPE_CNTL__VI = 0x1AB1; -constexpr unsigned int mmREGAMMA_CNTLB_START_CNTL__VI = 0x1AB0; -constexpr unsigned int mmREGAMMA_CONTROL__VI = 0x1AA0; -constexpr unsigned int mmREGAMMA_LUT_DATA__VI = 0x1AA2; -constexpr unsigned int mmREGAMMA_LUT_INDEX__VI = 0x1AA1; -constexpr unsigned int mmREGAMMA_LUT_WRITE_EN_MASK__VI = 0x1AA3; -constexpr unsigned int mmREMAP_HDP_MEM_FLUSH_CNTL__VI = 0x1426; -constexpr unsigned int mmREMAP_HDP_REG_FLUSH_CNTL__VI = 0x1427; -constexpr unsigned int mmRLC_AUTO_PG_CTRL__VI = 0xEC55; -constexpr unsigned int mmRLC_CAPTURE_GPU_CLOCK_COUNT__VI = 0xEC26; -constexpr unsigned int mmRLC_CGCG_CGLS_CTRL__VI = 0xEC49; -constexpr unsigned int mmRLC_CGCG_RAMP_CTRL__VI = 0xEC4A; -constexpr unsigned int mmRLC_CGTT_MGCG_OVERRIDE__VI = 0xEC48; -constexpr unsigned int mmRLC_CNTL__SI__CI = 0x30C0; -constexpr unsigned int mmRLC_CNTL__VI = 0xEC00; -constexpr unsigned int mmRLC_CP_RESPONSE0__VI = 0xECA5; -constexpr unsigned int mmRLC_CP_RESPONSE1__VI = 0xECA6; -constexpr unsigned int mmRLC_CP_RESPONSE2__VI = 0xECA7; -constexpr unsigned int mmRLC_CP_RESPONSE3__VI = 0xECA8; -constexpr unsigned int mmRLC_CP_SCHEDULERS__VI = 0xECAA; -constexpr unsigned int mmRLC_CSIB_ADDR_HI__VI = 0xECA3; -constexpr unsigned int mmRLC_CSIB_ADDR_LO__VI = 0xECA2; -constexpr unsigned int mmRLC_CSIB_LENGTH__VI = 0xECA4; -constexpr unsigned int mmRLC_CU_STATUS__VI = 0xEC4E; -constexpr unsigned int mmRLC_DEBUG__VI = 0xEC02; -constexpr unsigned int mmRLC_DEBUG_SELECT__VI = 0xEC01; -constexpr unsigned int mmRLC_DRIVER_CPDMA_STATUS__VI = 0xEC1E; -constexpr unsigned int mmRLC_DYN_PG_REQUEST__VI = 0xEC4C; -constexpr unsigned int mmRLC_DYN_PG_STATUS__VI = 0xEC4B; -constexpr unsigned int mmRLC_GPM_CU_PD_TIMEOUT__VI = 0xEC6B; -constexpr unsigned int mmRLC_GPM_DEBUG__VI = 0xEC21; -constexpr unsigned int mmRLC_GPM_DEBUG_SELECT__VI = 0xEC20; -constexpr unsigned int mmRLC_GPM_GENERAL_0__VI = 0xEC63; -constexpr unsigned int mmRLC_GPM_GENERAL_1__VI = 0xEC64; -constexpr unsigned int mmRLC_GPM_GENERAL_2__VI = 0xEC65; -constexpr unsigned int mmRLC_GPM_GENERAL_3__VI = 0xEC66; -constexpr unsigned int mmRLC_GPM_GENERAL_4__VI = 0xEC67; -constexpr unsigned int mmRLC_GPM_GENERAL_5__VI = 0xEC68; -constexpr unsigned int mmRLC_GPM_GENERAL_6__VI = 0xEC69; -constexpr unsigned int mmRLC_GPM_GENERAL_7__VI = 0xEC6A; -constexpr unsigned int mmRLC_GPM_INT_DISABLE_TH0__VI = 0xEC7C; -constexpr unsigned int mmRLC_GPM_INT_DISABLE_TH1__VI = 0xEC7D; -constexpr unsigned int mmRLC_GPM_INT_FORCE_TH0__VI = 0xEC7E; -constexpr unsigned int mmRLC_GPM_INT_FORCE_TH1__VI = 0xEC7F; -constexpr unsigned int mmRLC_GPM_LOG_ADDR__VI = 0xEC76; -constexpr unsigned int mmRLC_GPM_LOG_CONT__VI = 0xEC7B; -constexpr unsigned int mmRLC_GPM_LOG_SIZE__VI = 0xEC77; -constexpr unsigned int mmRLC_GPM_PERF_COUNT_0__VI = 0xEC6F; -constexpr unsigned int mmRLC_GPM_PERF_COUNT_1__VI = 0xEC70; -constexpr unsigned int mmRLC_GPM_SCRATCH_ADDR__VI = 0xEC6C; -constexpr unsigned int mmRLC_GPM_SCRATCH_DATA__VI = 0xEC6D; -constexpr unsigned int mmRLC_GPM_STAT__VI = 0xEC40; -constexpr unsigned int mmRLC_GPM_THREAD_ENABLE__VI = 0xEC45; -constexpr unsigned int mmRLC_GPM_THREAD_PRIORITY__VI = 0xEC44; -constexpr unsigned int mmRLC_GPM_THREAD_RESET__VI = 0xEC28; -constexpr unsigned int mmRLC_GPM_UCODE_ADDR__VI = 0xF83C; -constexpr unsigned int mmRLC_GPM_UCODE_DATA__VI = 0xF83D; -constexpr unsigned int mmRLC_GPM_VMID_THREAD0__VI = 0xEC46; -constexpr unsigned int mmRLC_GPM_VMID_THREAD1__VI = 0xEC47; -constexpr unsigned int mmRLC_GPM_VMID_THREAD2__VI = 0xFB41; -constexpr unsigned int mmRLC_GPR_REG1__VI = 0xEC79; -constexpr unsigned int mmRLC_GPR_REG2__VI = 0xEC7A; -constexpr unsigned int mmRLC_GPU_CLOCK_32__VI = 0xEC42; -constexpr unsigned int mmRLC_GPU_CLOCK_32_RES_SEL__VI = 0xEC41; -constexpr unsigned int mmRLC_GPU_CLOCK_COUNT_LSB__VI = 0xEC24; -constexpr unsigned int mmRLC_GPU_CLOCK_COUNT_MSB__VI = 0xEC25; -constexpr unsigned int mmRLC_GPU_IOV_ACTIVE_FCN_ID__VI = 0xFB40; -constexpr unsigned int mmRLC_GPU_IOV_CFG_REG1__VI = 0xFB01; -constexpr unsigned int mmRLC_GPU_IOV_CFG_REG10__VI = 0xFB22; -constexpr unsigned int mmRLC_GPU_IOV_CFG_REG11__VI = 0xFB23; -constexpr unsigned int mmRLC_GPU_IOV_CFG_REG12__VI = 0xFB24; -constexpr unsigned int mmRLC_GPU_IOV_CFG_REG13__VI = 0xFB25; -constexpr unsigned int mmRLC_GPU_IOV_CFG_REG14__VI = 0xFB26; -constexpr unsigned int mmRLC_GPU_IOV_CFG_REG15__VI = 0xFB27; -constexpr unsigned int mmRLC_GPU_IOV_CFG_REG2__VI = 0xFB02; -constexpr unsigned int mmRLC_GPU_IOV_CFG_REG6__VI = 0xFB06; -constexpr unsigned int mmRLC_GPU_IOV_CFG_REG8__VI = 0xFB08; -constexpr unsigned int mmRLC_GPU_IOV_CFG_REG9__VI = 0xFB21; -constexpr unsigned int mmRLC_GPU_IOV_F32_CNTL__VI = 0xFB46; -constexpr unsigned int mmRLC_GPU_IOV_F32_RESET__VI = 0xFB47; -constexpr unsigned int mmRLC_GPU_IOV_INT_DISABLE__VI = 0xFB4E; -constexpr unsigned int mmRLC_GPU_IOV_INT_FORCE__VI = 0xFB4F; -constexpr unsigned int mmRLC_GPU_IOV_RLC_RESPONSE__VI = 0xFB4D; -constexpr unsigned int mmRLC_GPU_IOV_SCH_0__VI = 0xFB52; -constexpr unsigned int mmRLC_GPU_IOV_SCH_1__VI = 0xFB53; -constexpr unsigned int mmRLC_GPU_IOV_SCH_2__VI = 0xFB54; -constexpr unsigned int mmRLC_GPU_IOV_SCH_3__VI = 0xFB55; -constexpr unsigned int mmRLC_GPU_IOV_SCH_INT__VI = 0xFB56; -constexpr unsigned int mmRLC_GPU_IOV_SCRATCH_ADDR__VI = 0xFB44; -constexpr unsigned int mmRLC_GPU_IOV_SCRATCH_DATA__VI = 0xFB45; -constexpr unsigned int mmRLC_GPU_IOV_SDMA0_BUSY_STATUS__VI = 0xFB50; -constexpr unsigned int mmRLC_GPU_IOV_SDMA0_STATUS__VI = 0xFB48; -constexpr unsigned int mmRLC_GPU_IOV_SDMA1_BUSY_STATUS__VI = 0xFB51; -constexpr unsigned int mmRLC_GPU_IOV_SDMA1_STATUS__VI = 0xFB49; -constexpr unsigned int mmRLC_GPU_IOV_SMU_RESPONSE__VI = 0xFB4A; -constexpr unsigned int mmRLC_GPU_IOV_UCODE_ADDR__VI = 0xFB42; -constexpr unsigned int mmRLC_GPU_IOV_UCODE_DATA__VI = 0xFB43; -constexpr unsigned int mmRLC_GPU_IOV_VF_ENABLE__VI = 0xFB00; -constexpr unsigned int mmRLC_GPU_IOV_VIRT_RESET_REQ__VI = 0xFB4C; -constexpr unsigned int mmRLC_HYP_GPM_UCODE_ADDR__VI = 0xF83C; -constexpr unsigned int mmRLC_HYP_GPM_UCODE_DATA__VI = 0xF83D; -constexpr unsigned int mmRLC_JUMP_TABLE_RESTORE__VI = 0xEC1E; -constexpr unsigned int mmRLC_LB_ALWAYS_ACTIVE_CU_MASK__VI = 0xEC50; -constexpr unsigned int mmRLC_LB_CNTL__VI = 0xEC19; -constexpr unsigned int mmRLC_LB_CNTR_INIT__VI = 0xEC1B; -constexpr unsigned int mmRLC_LB_CNTR_MAX__VI = 0xEC12; -constexpr unsigned int mmRLC_LB_INIT_CU_MASK__VI = 0xEC4F; -constexpr unsigned int mmRLC_LB_PARAMS__VI = 0xEC51; -constexpr unsigned int mmRLC_LOAD_BALANCE_CNTR__VI = 0xEC1C; -constexpr unsigned int mmRLC_MAX_PG_CU__VI = 0xEC54; -constexpr unsigned int mmRLC_MC_CNTL__VI = 0xEC03; -constexpr unsigned int mmRLC_MEM_SLP_CNTL__VI = 0xEC06; -constexpr unsigned int mmRLC_MGCG_CTRL__VI = 0xEC1A; -constexpr unsigned int mmRLC_PERFMON_CLK_CNTL__VI = 0xDCBF; -constexpr unsigned int mmRLC_PG_ALWAYS_ON_CU_MASK__VI = 0xEC53; -constexpr unsigned int mmRLC_PG_CNTL__VI = 0xEC43; -constexpr unsigned int mmRLC_PG_DELAY__VI = 0xEC4D; -constexpr unsigned int mmRLC_PG_DELAY_2__VI = 0xEC1F; -constexpr unsigned int mmRLC_PG_DELAY_3__VI = 0xEC78; -constexpr unsigned int mmRLC_RLCV_COMMAND__VI = 0xEC0A; -constexpr unsigned int mmRLC_RLCV_SAFE_MODE__VI = 0xEC08; -constexpr unsigned int mmRLC_ROM_CNTL__VI = 0xF836; -constexpr unsigned int mmRLC_SAFE_MODE__VI = 0xEC05; -constexpr unsigned int mmRLC_SAVE_AND_RESTORE_BASE__VI = 0xEC1D; -constexpr unsigned int mmRLC_SERDES_CU_MASTER_BUSY__VI = 0xEC61; -constexpr unsigned int mmRLC_SERDES_NONCU_MASTER_BUSY__VI = 0xEC62; -constexpr unsigned int mmRLC_SERDES_RD_DATA_0__VI = 0xEC5A; -constexpr unsigned int mmRLC_SERDES_RD_DATA_1__VI = 0xEC5B; -constexpr unsigned int mmRLC_SERDES_RD_DATA_2__VI = 0xEC5C; -constexpr unsigned int mmRLC_SERDES_RD_MASTER_INDEX__VI = 0xEC59; -constexpr unsigned int mmRLC_SERDES_WR_CTRL__VI = 0xEC5F; -constexpr unsigned int mmRLC_SERDES_WR_CU_MASTER_MASK__VI = 0xEC5D; -constexpr unsigned int mmRLC_SERDES_WR_DATA__VI = 0xEC60; -constexpr unsigned int mmRLC_SERDES_WR_NONCU_MASTER_MASK__VI = 0xEC5E; -constexpr unsigned int mmRLC_SMU_COMMAND__VI = 0xECA9; -constexpr unsigned int mmRLC_SMU_GRBM_REG_SAVE_CTRL__VI = 0xEC56; -constexpr unsigned int mmRLC_SMU_MESSAGE__VI = 0xEC76; -constexpr unsigned int mmRLC_SMU_PG_CTRL__VI = 0xEC57; -constexpr unsigned int mmRLC_SMU_PG_WAKE_UP_CTRL__VI = 0xEC58; -constexpr unsigned int mmRLC_SMU_SAFE_MODE__VI = 0xEC09; -constexpr unsigned int mmRLC_SOFT_RESET_GPU__VI = 0xEC05; -constexpr unsigned int mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__VI = 0xDCA1; -constexpr unsigned int mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__VI = 0xDCA2; -constexpr unsigned int mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__VI = 0xDC9F; -constexpr unsigned int mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__VI = 0xDCA0; -constexpr unsigned int mmRLC_SPM_DEBUG__VI = 0xEC75; -constexpr unsigned int mmRLC_SPM_DEBUG_SELECT__VI = 0xEC74; -constexpr unsigned int mmRLC_SPM_INT_CNTL__VI = 0xEC72; -constexpr unsigned int mmRLC_SPM_INT_STATUS__VI = 0xEC73; -constexpr unsigned int mmRLC_SPM_VMID__VI = 0xEC71; -constexpr unsigned int mmRLC_SRM_ARAM_ADDR__VI = 0xEC83; -constexpr unsigned int mmRLC_SRM_ARAM_DATA__VI = 0xEC84; -constexpr unsigned int mmRLC_SRM_CNTL__VI = 0xEC80; -constexpr unsigned int mmRLC_SRM_DEBUG__VI = 0xEC82; -constexpr unsigned int mmRLC_SRM_DEBUG_SELECT__VI = 0xEC81; -constexpr unsigned int mmRLC_SRM_DRAM_ADDR__VI = 0xEC85; -constexpr unsigned int mmRLC_SRM_DRAM_DATA__VI = 0xEC86; -constexpr unsigned int mmRLC_SRM_GPM_ABORT__VI = 0xEC9C; -constexpr unsigned int mmRLC_SRM_GPM_COMMAND__VI = 0xEC87; -constexpr unsigned int mmRLC_SRM_GPM_COMMAND_STATUS__VI = 0xEC88; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_ADDR_0__VI = 0xEC8B; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_ADDR_1__VI = 0xEC8C; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_ADDR_2__VI = 0xEC8D; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_ADDR_3__VI = 0xEC8E; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_ADDR_4__VI = 0xEC8F; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_ADDR_5__VI = 0xEC90; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_ADDR_6__VI = 0xEC91; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_ADDR_7__VI = 0xEC92; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_DATA_0__VI = 0xEC93; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_DATA_1__VI = 0xEC94; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_DATA_2__VI = 0xEC95; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_DATA_3__VI = 0xEC96; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_DATA_4__VI = 0xEC97; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_DATA_5__VI = 0xEC98; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_DATA_6__VI = 0xEC99; -constexpr unsigned int mmRLC_SRM_INDEX_CNTL_DATA_7__VI = 0xEC9A; -constexpr unsigned int mmRLC_SRM_RLCV_COMMAND__VI = 0xEC89; -constexpr unsigned int mmRLC_SRM_RLCV_COMMAND_STATUS__VI = 0xEC8A; -constexpr unsigned int mmRLC_SRM_STAT__VI = 0xEC9B; -constexpr unsigned int mmRLC_STAT__VI = 0xEC04; -constexpr unsigned int mmRLC_STATIC_PG_STATUS__VI = 0xEC6E; -constexpr unsigned int mmRLC_THREAD1_DELAY__VI = 0xEC52; -constexpr unsigned int mmRLC_UCODE_CNTL__VI = 0xEC27; -constexpr unsigned int mmSAM_IH_EXT_ERR_INTR__VI = 0x8810; -constexpr unsigned int mmSAM_IH_EXT_ERR_INTR_STATUS__VI = 0x8812; -constexpr unsigned int mmSCL0_SCL_DEBUG2__VI = 0x1B69; -constexpr unsigned int mmSCL0_SCL_HORZ_FILTER_CONTROL__VI = 0x1B48; -constexpr unsigned int mmSCL0_SCL_HORZ_FILTER_INIT__VI = 0x1B4A; -constexpr unsigned int mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO__VI = 0x1B49; -constexpr unsigned int mmSCL0_SCL_MODE__VI = 0x1B42; -constexpr unsigned int mmSCL0_SCL_ROUND_OFFSET__VI = 0x1B4F; -constexpr unsigned int mmSCL0_SCL_VERT_FILTER_CONTROL__VI = 0x1B4B; -constexpr unsigned int mmSCL0_SCL_VERT_FILTER_INIT__VI = 0x1B4D; -constexpr unsigned int mmSCL0_SCL_VERT_FILTER_INIT_BOT__VI = 0x1B4E; -constexpr unsigned int mmSCL0_SCL_VERT_FILTER_SCALE_RATIO__VI = 0x1B4C; -constexpr unsigned int mmSCL0_VIEWPORT_START_SECONDARY__VI = 0x1B5B; -constexpr unsigned int mmSCL1_EXT_OVERSCAN_LEFT_RIGHT__VI = 0x1D5E; -constexpr unsigned int mmSCL1_EXT_OVERSCAN_TOP_BOTTOM__VI = 0x1D5F; -constexpr unsigned int mmSCL1_SCL_ALU_CONTROL__VI = 0x1D54; -constexpr unsigned int mmSCL1_SCL_AUTOMATIC_MODE_CONTROL__VI = 0x1D47; -constexpr unsigned int mmSCL1_SCL_BYPASS_CONTROL__VI = 0x1D45; -constexpr unsigned int mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS__VI = 0x1D55; -constexpr unsigned int mmSCL1_SCL_COEF_RAM_SELECT__VI = 0x1D40; -constexpr unsigned int mmSCL1_SCL_COEF_RAM_TAP_DATA__VI = 0x1D41; -constexpr unsigned int mmSCL1_SCL_CONTROL__VI = 0x1D44; -constexpr unsigned int mmSCL1_SCL_DEBUG__VI = 0x1D6A; -constexpr unsigned int mmSCL1_SCL_DEBUG2__VI = 0x1D69; -constexpr unsigned int mmSCL1_SCL_F_SHARP_CONTROL__VI = 0x1D53; -constexpr unsigned int mmSCL1_SCL_HORZ_FILTER_CONTROL__VI = 0x1D48; -constexpr unsigned int mmSCL1_SCL_HORZ_FILTER_INIT__VI = 0x1D4A; -constexpr unsigned int mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO__VI = 0x1D49; -constexpr unsigned int mmSCL1_SCL_MANUAL_REPLICATE_CONTROL__VI = 0x1D46; -constexpr unsigned int mmSCL1_SCL_MODE__VI = 0x1D42; -constexpr unsigned int mmSCL1_SCL_MODE_CHANGE_DET1__VI = 0x1D60; -constexpr unsigned int mmSCL1_SCL_MODE_CHANGE_DET2__VI = 0x1D61; -constexpr unsigned int mmSCL1_SCL_MODE_CHANGE_DET3__VI = 0x1D62; -constexpr unsigned int mmSCL1_SCL_MODE_CHANGE_MASK__VI = 0x1D63; -constexpr unsigned int mmSCL1_SCL_ROUND_OFFSET__VI = 0x1D4F; -constexpr unsigned int mmSCL1_SCL_TAP_CONTROL__VI = 0x1D43; -constexpr unsigned int mmSCL1_SCL_TEST_DEBUG_DATA__VI = 0x1D6C; -constexpr unsigned int mmSCL1_SCL_TEST_DEBUG_INDEX__VI = 0x1D6B; -constexpr unsigned int mmSCL1_SCL_UPDATE__VI = 0x1D51; -constexpr unsigned int mmSCL1_SCL_VERT_FILTER_CONTROL__VI = 0x1D4B; -constexpr unsigned int mmSCL1_SCL_VERT_FILTER_INIT__VI = 0x1D4D; -constexpr unsigned int mmSCL1_SCL_VERT_FILTER_INIT_BOT__VI = 0x1D4E; -constexpr unsigned int mmSCL1_SCL_VERT_FILTER_SCALE_RATIO__VI = 0x1D4C; -constexpr unsigned int mmSCL1_VIEWPORT_SIZE__VI = 0x1D5D; -constexpr unsigned int mmSCL1_VIEWPORT_START__VI = 0x1D5C; -constexpr unsigned int mmSCL1_VIEWPORT_START_SECONDARY__VI = 0x1D5B; -constexpr unsigned int mmSCL2_EXT_OVERSCAN_LEFT_RIGHT__VI = 0x1F5E; -constexpr unsigned int mmSCL2_EXT_OVERSCAN_TOP_BOTTOM__VI = 0x1F5F; -constexpr unsigned int mmSCL2_SCL_ALU_CONTROL__VI = 0x1F54; -constexpr unsigned int mmSCL2_SCL_AUTOMATIC_MODE_CONTROL__VI = 0x1F47; -constexpr unsigned int mmSCL2_SCL_BYPASS_CONTROL__VI = 0x1F45; -constexpr unsigned int mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS__VI = 0x1F55; -constexpr unsigned int mmSCL2_SCL_COEF_RAM_SELECT__VI = 0x1F40; -constexpr unsigned int mmSCL2_SCL_COEF_RAM_TAP_DATA__VI = 0x1F41; -constexpr unsigned int mmSCL2_SCL_CONTROL__VI = 0x1F44; -constexpr unsigned int mmSCL2_SCL_DEBUG__VI = 0x1F6A; -constexpr unsigned int mmSCL2_SCL_DEBUG2__VI = 0x1F69; -constexpr unsigned int mmSCL2_SCL_F_SHARP_CONTROL__VI = 0x1F53; -constexpr unsigned int mmSCL2_SCL_HORZ_FILTER_CONTROL__VI = 0x1F48; -constexpr unsigned int mmSCL2_SCL_HORZ_FILTER_INIT__VI = 0x1F4A; -constexpr unsigned int mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO__VI = 0x1F49; -constexpr unsigned int mmSCL2_SCL_MANUAL_REPLICATE_CONTROL__VI = 0x1F46; -constexpr unsigned int mmSCL2_SCL_MODE__VI = 0x1F42; -constexpr unsigned int mmSCL2_SCL_MODE_CHANGE_DET1__VI = 0x1F60; -constexpr unsigned int mmSCL2_SCL_MODE_CHANGE_DET2__VI = 0x1F61; -constexpr unsigned int mmSCL2_SCL_MODE_CHANGE_DET3__VI = 0x1F62; -constexpr unsigned int mmSCL2_SCL_MODE_CHANGE_MASK__VI = 0x1F63; -constexpr unsigned int mmSCL2_SCL_ROUND_OFFSET__VI = 0x1F4F; -constexpr unsigned int mmSCL2_SCL_TAP_CONTROL__VI = 0x1F43; -constexpr unsigned int mmSCL2_SCL_TEST_DEBUG_DATA__VI = 0x1F6C; -constexpr unsigned int mmSCL2_SCL_TEST_DEBUG_INDEX__VI = 0x1F6B; -constexpr unsigned int mmSCL2_SCL_UPDATE__VI = 0x1F51; -constexpr unsigned int mmSCL2_SCL_VERT_FILTER_CONTROL__VI = 0x1F4B; -constexpr unsigned int mmSCL2_SCL_VERT_FILTER_INIT__VI = 0x1F4D; -constexpr unsigned int mmSCL2_SCL_VERT_FILTER_INIT_BOT__VI = 0x1F4E; -constexpr unsigned int mmSCL2_SCL_VERT_FILTER_SCALE_RATIO__VI = 0x1F4C; -constexpr unsigned int mmSCL2_VIEWPORT_SIZE__VI = 0x1F5D; -constexpr unsigned int mmSCL2_VIEWPORT_START__VI = 0x1F5C; -constexpr unsigned int mmSCL2_VIEWPORT_START_SECONDARY__VI = 0x1F5B; -constexpr unsigned int mmSCL3_EXT_OVERSCAN_LEFT_RIGHT__VI = 0x415E; -constexpr unsigned int mmSCL3_EXT_OVERSCAN_TOP_BOTTOM__VI = 0x415F; -constexpr unsigned int mmSCL3_SCL_ALU_CONTROL__VI = 0x4154; -constexpr unsigned int mmSCL3_SCL_AUTOMATIC_MODE_CONTROL__VI = 0x4147; -constexpr unsigned int mmSCL3_SCL_BYPASS_CONTROL__VI = 0x4145; -constexpr unsigned int mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS__VI = 0x4155; -constexpr unsigned int mmSCL3_SCL_COEF_RAM_SELECT__VI = 0x4140; -constexpr unsigned int mmSCL3_SCL_COEF_RAM_TAP_DATA__VI = 0x4141; -constexpr unsigned int mmSCL3_SCL_CONTROL__VI = 0x4144; -constexpr unsigned int mmSCL3_SCL_DEBUG__VI = 0x416A; -constexpr unsigned int mmSCL3_SCL_DEBUG2__VI = 0x4169; -constexpr unsigned int mmSCL3_SCL_F_SHARP_CONTROL__VI = 0x4153; -constexpr unsigned int mmSCL3_SCL_HORZ_FILTER_CONTROL__VI = 0x4148; -constexpr unsigned int mmSCL3_SCL_HORZ_FILTER_INIT__VI = 0x414A; -constexpr unsigned int mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO__VI = 0x4149; -constexpr unsigned int mmSCL3_SCL_MANUAL_REPLICATE_CONTROL__VI = 0x4146; -constexpr unsigned int mmSCL3_SCL_MODE__VI = 0x4142; -constexpr unsigned int mmSCL3_SCL_MODE_CHANGE_DET1__VI = 0x4160; -constexpr unsigned int mmSCL3_SCL_MODE_CHANGE_DET2__VI = 0x4161; -constexpr unsigned int mmSCL3_SCL_MODE_CHANGE_DET3__VI = 0x4162; -constexpr unsigned int mmSCL3_SCL_MODE_CHANGE_MASK__VI = 0x4163; -constexpr unsigned int mmSCL3_SCL_ROUND_OFFSET__VI = 0x414F; -constexpr unsigned int mmSCL3_SCL_TAP_CONTROL__VI = 0x4143; -constexpr unsigned int mmSCL3_SCL_TEST_DEBUG_DATA__VI = 0x416C; -constexpr unsigned int mmSCL3_SCL_TEST_DEBUG_INDEX__VI = 0x416B; -constexpr unsigned int mmSCL3_SCL_UPDATE__VI = 0x4151; -constexpr unsigned int mmSCL3_SCL_VERT_FILTER_CONTROL__VI = 0x414B; -constexpr unsigned int mmSCL3_SCL_VERT_FILTER_INIT__VI = 0x414D; -constexpr unsigned int mmSCL3_SCL_VERT_FILTER_INIT_BOT__VI = 0x414E; -constexpr unsigned int mmSCL3_SCL_VERT_FILTER_SCALE_RATIO__VI = 0x414C; -constexpr unsigned int mmSCL3_VIEWPORT_SIZE__VI = 0x415D; -constexpr unsigned int mmSCL3_VIEWPORT_START__VI = 0x415C; -constexpr unsigned int mmSCL3_VIEWPORT_START_SECONDARY__VI = 0x415B; -constexpr unsigned int mmSCL4_EXT_OVERSCAN_LEFT_RIGHT__VI = 0x435E; -constexpr unsigned int mmSCL4_EXT_OVERSCAN_TOP_BOTTOM__VI = 0x435F; -constexpr unsigned int mmSCL4_SCL_ALU_CONTROL__VI = 0x4354; -constexpr unsigned int mmSCL4_SCL_AUTOMATIC_MODE_CONTROL__VI = 0x4347; -constexpr unsigned int mmSCL4_SCL_BYPASS_CONTROL__VI = 0x4345; -constexpr unsigned int mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS__VI = 0x4355; -constexpr unsigned int mmSCL4_SCL_COEF_RAM_SELECT__VI = 0x4340; -constexpr unsigned int mmSCL4_SCL_COEF_RAM_TAP_DATA__VI = 0x4341; -constexpr unsigned int mmSCL4_SCL_CONTROL__VI = 0x4344; -constexpr unsigned int mmSCL4_SCL_DEBUG__VI = 0x436A; -constexpr unsigned int mmSCL4_SCL_DEBUG2__VI = 0x4369; -constexpr unsigned int mmSCL4_SCL_F_SHARP_CONTROL__VI = 0x4353; -constexpr unsigned int mmSCL4_SCL_HORZ_FILTER_CONTROL__VI = 0x4348; -constexpr unsigned int mmSCL4_SCL_HORZ_FILTER_INIT__VI = 0x434A; -constexpr unsigned int mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO__VI = 0x4349; -constexpr unsigned int mmSCL4_SCL_MANUAL_REPLICATE_CONTROL__VI = 0x4346; -constexpr unsigned int mmSCL4_SCL_MODE__VI = 0x4342; -constexpr unsigned int mmSCL4_SCL_MODE_CHANGE_DET1__VI = 0x4360; -constexpr unsigned int mmSCL4_SCL_MODE_CHANGE_DET2__VI = 0x4361; -constexpr unsigned int mmSCL4_SCL_MODE_CHANGE_DET3__VI = 0x4362; -constexpr unsigned int mmSCL4_SCL_MODE_CHANGE_MASK__VI = 0x4363; -constexpr unsigned int mmSCL4_SCL_ROUND_OFFSET__VI = 0x434F; -constexpr unsigned int mmSCL4_SCL_TAP_CONTROL__VI = 0x4343; -constexpr unsigned int mmSCL4_SCL_TEST_DEBUG_DATA__VI = 0x436C; -constexpr unsigned int mmSCL4_SCL_TEST_DEBUG_INDEX__VI = 0x436B; -constexpr unsigned int mmSCL4_SCL_UPDATE__VI = 0x4351; -constexpr unsigned int mmSCL4_SCL_VERT_FILTER_CONTROL__VI = 0x434B; -constexpr unsigned int mmSCL4_SCL_VERT_FILTER_INIT__VI = 0x434D; -constexpr unsigned int mmSCL4_SCL_VERT_FILTER_INIT_BOT__VI = 0x434E; -constexpr unsigned int mmSCL4_SCL_VERT_FILTER_SCALE_RATIO__VI = 0x434C; -constexpr unsigned int mmSCL4_VIEWPORT_SIZE__VI = 0x435D; -constexpr unsigned int mmSCL4_VIEWPORT_START__VI = 0x435C; -constexpr unsigned int mmSCL4_VIEWPORT_START_SECONDARY__VI = 0x435B; -constexpr unsigned int mmSCL5_EXT_OVERSCAN_LEFT_RIGHT__VI = 0x455E; -constexpr unsigned int mmSCL5_EXT_OVERSCAN_TOP_BOTTOM__VI = 0x455F; -constexpr unsigned int mmSCL5_SCL_ALU_CONTROL__VI = 0x4554; -constexpr unsigned int mmSCL5_SCL_AUTOMATIC_MODE_CONTROL__VI = 0x4547; -constexpr unsigned int mmSCL5_SCL_BYPASS_CONTROL__VI = 0x4545; -constexpr unsigned int mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS__VI = 0x4555; -constexpr unsigned int mmSCL5_SCL_COEF_RAM_SELECT__VI = 0x4540; -constexpr unsigned int mmSCL5_SCL_COEF_RAM_TAP_DATA__VI = 0x4541; -constexpr unsigned int mmSCL5_SCL_CONTROL__VI = 0x4544; -constexpr unsigned int mmSCL5_SCL_DEBUG__VI = 0x456A; -constexpr unsigned int mmSCL5_SCL_DEBUG2__VI = 0x4569; -constexpr unsigned int mmSCL5_SCL_F_SHARP_CONTROL__VI = 0x4553; -constexpr unsigned int mmSCL5_SCL_HORZ_FILTER_CONTROL__VI = 0x4548; -constexpr unsigned int mmSCL5_SCL_HORZ_FILTER_INIT__VI = 0x454A; -constexpr unsigned int mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO__VI = 0x4549; -constexpr unsigned int mmSCL5_SCL_MANUAL_REPLICATE_CONTROL__VI = 0x4546; -constexpr unsigned int mmSCL5_SCL_MODE__VI = 0x4542; -constexpr unsigned int mmSCL5_SCL_MODE_CHANGE_DET1__VI = 0x4560; -constexpr unsigned int mmSCL5_SCL_MODE_CHANGE_DET2__VI = 0x4561; -constexpr unsigned int mmSCL5_SCL_MODE_CHANGE_DET3__VI = 0x4562; -constexpr unsigned int mmSCL5_SCL_MODE_CHANGE_MASK__VI = 0x4563; -constexpr unsigned int mmSCL5_SCL_ROUND_OFFSET__VI = 0x454F; -constexpr unsigned int mmSCL5_SCL_TAP_CONTROL__VI = 0x4543; -constexpr unsigned int mmSCL5_SCL_TEST_DEBUG_DATA__VI = 0x456C; -constexpr unsigned int mmSCL5_SCL_TEST_DEBUG_INDEX__VI = 0x456B; -constexpr unsigned int mmSCL5_SCL_UPDATE__VI = 0x4551; -constexpr unsigned int mmSCL5_SCL_VERT_FILTER_CONTROL__VI = 0x454B; -constexpr unsigned int mmSCL5_SCL_VERT_FILTER_INIT__VI = 0x454D; -constexpr unsigned int mmSCL5_SCL_VERT_FILTER_INIT_BOT__VI = 0x454E; -constexpr unsigned int mmSCL5_SCL_VERT_FILTER_SCALE_RATIO__VI = 0x454C; -constexpr unsigned int mmSCL5_VIEWPORT_SIZE__VI = 0x455D; -constexpr unsigned int mmSCL5_VIEWPORT_START__VI = 0x455C; -constexpr unsigned int mmSCL5_VIEWPORT_START_SECONDARY__VI = 0x455B; -constexpr unsigned int mmSCLK_CGTT_BLK_CTRL_REG__VI = 0x0136; -constexpr unsigned int mmSCLV_ALU_CONTROL__VI = 0x4685; -constexpr unsigned int mmSCLV_AUTOMATIC_MODE_CONTROL__VI = 0x4676; -constexpr unsigned int mmSCLV_COEF_RAM_SELECT__VI = 0x4670; -constexpr unsigned int mmSCLV_COEF_RAM_TAP_DATA__VI = 0x4671; -constexpr unsigned int mmSCLV_CONTROL__VI = 0x4674; -constexpr unsigned int mmSCLV_DEBUG__VI = 0x4693; -constexpr unsigned int mmSCLV_DEBUG2__VI = 0x4692; -constexpr unsigned int mmSCLV_EXT_OVERSCAN_LEFT_RIGHT__VI = 0x468C; -constexpr unsigned int mmSCLV_EXT_OVERSCAN_TOP_BOTTOM__VI = 0x468D; -constexpr unsigned int mmSCLV_HORZ_FILTER_CONTROL__VI = 0x4677; -constexpr unsigned int mmSCLV_HORZ_FILTER_INIT__VI = 0x4679; -constexpr unsigned int mmSCLV_HORZ_FILTER_INIT_C__VI = 0x467B; -constexpr unsigned int mmSCLV_HORZ_FILTER_SCALE_RATIO__VI = 0x4678; -constexpr unsigned int mmSCLV_HORZ_FILTER_SCALE_RATIO_C__VI = 0x467A; -constexpr unsigned int mmSCLV_MANUAL_REPLICATE_CONTROL__VI = 0x4675; -constexpr unsigned int mmSCLV_MODE__VI = 0x4672; -constexpr unsigned int mmSCLV_MODE_CHANGE_DET1__VI = 0x468E; -constexpr unsigned int mmSCLV_MODE_CHANGE_DET2__VI = 0x468F; -constexpr unsigned int mmSCLV_MODE_CHANGE_DET3__VI = 0x4690; -constexpr unsigned int mmSCLV_MODE_CHANGE_MASK__VI = 0x4691; -constexpr unsigned int mmSCLV_ROUND_OFFSET__VI = 0x4683; -constexpr unsigned int mmSCLV_TAP_CONTROL__VI = 0x4673; -constexpr unsigned int mmSCLV_TEST_DEBUG_DATA__VI = 0x4695; -constexpr unsigned int mmSCLV_TEST_DEBUG_INDEX__VI = 0x4694; -constexpr unsigned int mmSCLV_UPDATE__VI = 0x4684; -constexpr unsigned int mmSCLV_VERT_FILTER_CONTROL__VI = 0x467C; -constexpr unsigned int mmSCLV_VERT_FILTER_INIT__VI = 0x467E; -constexpr unsigned int mmSCLV_VERT_FILTER_INIT_BOT__VI = 0x467F; -constexpr unsigned int mmSCLV_VERT_FILTER_INIT_BOT_C__VI = 0x4682; -constexpr unsigned int mmSCLV_VERT_FILTER_INIT_C__VI = 0x4681; -constexpr unsigned int mmSCLV_VERT_FILTER_SCALE_RATIO__VI = 0x467D; -constexpr unsigned int mmSCLV_VERT_FILTER_SCALE_RATIO_C__VI = 0x4680; -constexpr unsigned int mmSCLV_VIEWPORT_SIZE__VI = 0x4688; -constexpr unsigned int mmSCLV_VIEWPORT_SIZE_C__VI = 0x468B; -constexpr unsigned int mmSCLV_VIEWPORT_START__VI = 0x4686; -constexpr unsigned int mmSCLV_VIEWPORT_START_C__VI = 0x4689; -constexpr unsigned int mmSCLV_VIEWPORT_START_SECONDARY__VI = 0x4687; -constexpr unsigned int mmSCLV_VIEWPORT_START_SECONDARY_C__VI = 0x468A; -constexpr unsigned int mmSCL_DEBUG2__VI = 0x1B69; -constexpr unsigned int mmSCL_HORZ_FILTER_CONTROL__VI = 0x1B48; -constexpr unsigned int mmSCL_HORZ_FILTER_INIT__VI = 0x1B4A; -constexpr unsigned int mmSCL_HORZ_FILTER_SCALE_RATIO__VI = 0x1B49; -constexpr unsigned int mmSCL_MODE__VI = 0x1B42; -constexpr unsigned int mmSCL_ROUND_OFFSET__VI = 0x1B4F; -constexpr unsigned int mmSCL_VERT_FILTER_CONTROL__VI = 0x1B4B; -constexpr unsigned int mmSCL_VERT_FILTER_INIT__VI = 0x1B4D; -constexpr unsigned int mmSCL_VERT_FILTER_INIT_BOT__VI = 0x1B4E; -constexpr unsigned int mmSCL_VERT_FILTER_SCALE_RATIO__VI = 0x1B4C; -constexpr unsigned int mmSDMA0_ACTIVE_FCN_ID__VI = 0x341F; -constexpr unsigned int mmSDMA0_ATOMIC_CNTL__VI = 0x342E; -constexpr unsigned int mmSDMA0_ATOMIC_PREOP_HI__VI = 0x3430; -constexpr unsigned int mmSDMA0_ATOMIC_PREOP_LO__VI = 0x342F; -constexpr unsigned int mmSDMA0_BA_THRESHOLD__VI = 0x342B; -constexpr unsigned int mmSDMA0_CONTEXT_REG_TYPE0__VI = 0x3478; -constexpr unsigned int mmSDMA0_CONTEXT_REG_TYPE1__VI = 0x3479; -constexpr unsigned int mmSDMA0_CONTEXT_REG_TYPE2__VI = 0x347A; -constexpr unsigned int mmSDMA0_EDC_CONFIG__VI = 0x341A; -constexpr unsigned int mmSDMA0_GFX_CSA_ADDR_HI__VI = 0x34AD; -constexpr unsigned int mmSDMA0_GFX_CSA_ADDR_LO__VI = 0x34AC; -constexpr unsigned int mmSDMA0_GFX_DOORBELL__VI = 0x3492; -constexpr unsigned int mmSDMA0_GFX_DOORBELL_LOG__VI = 0x34A9; -constexpr unsigned int mmSDMA0_GFX_DUMMY_REG__VI = 0x34B1; -constexpr unsigned int mmSDMA0_GFX_IB_SUB_REMAIN__VI = 0x34AF; -constexpr unsigned int mmSDMA0_GFX_MIDCMD_CNTL__VI = 0x34C7; -constexpr unsigned int mmSDMA0_GFX_MIDCMD_DATA0__VI = 0x34C1; -constexpr unsigned int mmSDMA0_GFX_MIDCMD_DATA1__VI = 0x34C2; -constexpr unsigned int mmSDMA0_GFX_MIDCMD_DATA2__VI = 0x34C3; -constexpr unsigned int mmSDMA0_GFX_MIDCMD_DATA3__VI = 0x34C4; -constexpr unsigned int mmSDMA0_GFX_MIDCMD_DATA4__VI = 0x34C5; -constexpr unsigned int mmSDMA0_GFX_MIDCMD_DATA5__VI = 0x34C6; -constexpr unsigned int mmSDMA0_GFX_PREEMPT__VI = 0x34B0; -constexpr unsigned int mmSDMA0_GFX_WATERMARK__VI = 0x34AA; -constexpr unsigned int mmSDMA0_ID__VI = 0x342C; -constexpr unsigned int mmSDMA0_PERFCOUNTER0_RESULT__VI = 0x9001; -constexpr unsigned int mmSDMA0_PERFCOUNTER1_RESULT__VI = 0x9002; -constexpr unsigned int mmSDMA0_PERFMON_CNTL__VI = 0x9000; -constexpr unsigned int mmSDMA0_PERF_REG_TYPE0__VI = 0x3477; -constexpr unsigned int mmSDMA0_POWER_CNTL_IDLE__VI = 0x342C; -constexpr unsigned int mmSDMA0_PUB_REG_TYPE0__VI = 0x347C; -constexpr unsigned int mmSDMA0_PUB_REG_TYPE1__VI = 0x347D; -constexpr unsigned int mmSDMA0_RD_BURST_CNTL__VI = 0x340F; -constexpr unsigned int mmSDMA0_RLC0_CSA_ADDR_HI__VI = 0x352D; -constexpr unsigned int mmSDMA0_RLC0_CSA_ADDR_LO__VI = 0x352C; -constexpr unsigned int mmSDMA0_RLC0_DUMMY_REG__VI = 0x3531; -constexpr unsigned int mmSDMA0_RLC0_IB_SUB_REMAIN__VI = 0x352F; -constexpr unsigned int mmSDMA0_RLC0_MIDCMD_CNTL__VI = 0x3547; -constexpr unsigned int mmSDMA0_RLC0_MIDCMD_DATA0__VI = 0x3541; -constexpr unsigned int mmSDMA0_RLC0_MIDCMD_DATA1__VI = 0x3542; -constexpr unsigned int mmSDMA0_RLC0_MIDCMD_DATA2__VI = 0x3543; -constexpr unsigned int mmSDMA0_RLC0_MIDCMD_DATA3__VI = 0x3544; -constexpr unsigned int mmSDMA0_RLC0_MIDCMD_DATA4__VI = 0x3545; -constexpr unsigned int mmSDMA0_RLC0_MIDCMD_DATA5__VI = 0x3546; -constexpr unsigned int mmSDMA0_RLC0_PREEMPT__VI = 0x3530; -constexpr unsigned int mmSDMA0_RLC0_WATERMARK__VI = 0x352A; -constexpr unsigned int mmSDMA0_RLC1_CSA_ADDR_HI__VI = 0x35AD; -constexpr unsigned int mmSDMA0_RLC1_CSA_ADDR_LO__VI = 0x35AC; -constexpr unsigned int mmSDMA0_RLC1_DUMMY_REG__VI = 0x35B1; -constexpr unsigned int mmSDMA0_RLC1_IB_SUB_REMAIN__VI = 0x35AF; -constexpr unsigned int mmSDMA0_RLC1_MIDCMD_CNTL__VI = 0x35C7; -constexpr unsigned int mmSDMA0_RLC1_MIDCMD_DATA0__VI = 0x35C1; -constexpr unsigned int mmSDMA0_RLC1_MIDCMD_DATA1__VI = 0x35C2; -constexpr unsigned int mmSDMA0_RLC1_MIDCMD_DATA2__VI = 0x35C3; -constexpr unsigned int mmSDMA0_RLC1_MIDCMD_DATA3__VI = 0x35C4; -constexpr unsigned int mmSDMA0_RLC1_MIDCMD_DATA4__VI = 0x35C5; -constexpr unsigned int mmSDMA0_RLC1_MIDCMD_DATA5__VI = 0x35C6; -constexpr unsigned int mmSDMA0_RLC1_PREEMPT__VI = 0x35B0; -constexpr unsigned int mmSDMA0_RLC1_WATERMARK__VI = 0x35AA; -constexpr unsigned int mmSDMA0_STATUS2_REG__VI = 0x341E; -constexpr unsigned int mmSDMA0_VERSION__VI = 0x342D; -constexpr unsigned int mmSDMA0_VF_ENABLE__VI = 0x342A; -constexpr unsigned int mmSDMA0_VIRT_RESET_REQ__VI = 0x3421; -constexpr unsigned int mmSDMA0_VM_CNTL__VI = 0x341B; -constexpr unsigned int mmSDMA0_VM_CTX_CNTL__VI = 0x3420; -constexpr unsigned int mmSDMA0_VM_CTX_HI__VI = 0x341D; -constexpr unsigned int mmSDMA0_VM_CTX_LO__VI = 0x341C; -constexpr unsigned int mmSDMA1_ACTIVE_FCN_ID__VI = 0x361F; -constexpr unsigned int mmSDMA1_ATOMIC_CNTL__VI = 0x362E; -constexpr unsigned int mmSDMA1_ATOMIC_PREOP_HI__VI = 0x3630; -constexpr unsigned int mmSDMA1_ATOMIC_PREOP_LO__VI = 0x362F; -constexpr unsigned int mmSDMA1_BA_THRESHOLD__VI = 0x362B; -constexpr unsigned int mmSDMA1_CONTEXT_REG_TYPE0__VI = 0x3678; -constexpr unsigned int mmSDMA1_CONTEXT_REG_TYPE1__VI = 0x3679; -constexpr unsigned int mmSDMA1_CONTEXT_REG_TYPE2__VI = 0x367A; -constexpr unsigned int mmSDMA1_EDC_CONFIG__VI = 0x361A; -constexpr unsigned int mmSDMA1_GFX_CSA_ADDR_HI__VI = 0x36AD; -constexpr unsigned int mmSDMA1_GFX_CSA_ADDR_LO__VI = 0x36AC; -constexpr unsigned int mmSDMA1_GFX_DOORBELL__VI = 0x3692; -constexpr unsigned int mmSDMA1_GFX_DOORBELL_LOG__VI = 0x36A9; -constexpr unsigned int mmSDMA1_GFX_DUMMY_REG__VI = 0x36B1; -constexpr unsigned int mmSDMA1_GFX_IB_SUB_REMAIN__VI = 0x36AF; -constexpr unsigned int mmSDMA1_GFX_MIDCMD_CNTL__VI = 0x36C7; -constexpr unsigned int mmSDMA1_GFX_MIDCMD_DATA0__VI = 0x36C1; -constexpr unsigned int mmSDMA1_GFX_MIDCMD_DATA1__VI = 0x36C2; -constexpr unsigned int mmSDMA1_GFX_MIDCMD_DATA2__VI = 0x36C3; -constexpr unsigned int mmSDMA1_GFX_MIDCMD_DATA3__VI = 0x36C4; -constexpr unsigned int mmSDMA1_GFX_MIDCMD_DATA4__VI = 0x36C5; -constexpr unsigned int mmSDMA1_GFX_MIDCMD_DATA5__VI = 0x36C6; -constexpr unsigned int mmSDMA1_GFX_PREEMPT__VI = 0x36B0; -constexpr unsigned int mmSDMA1_GFX_WATERMARK__VI = 0x36AA; -constexpr unsigned int mmSDMA1_ID__VI = 0x362C; -constexpr unsigned int mmSDMA1_PERFCOUNTER0_RESULT__VI = 0x9011; -constexpr unsigned int mmSDMA1_PERFCOUNTER1_RESULT__VI = 0x9012; -constexpr unsigned int mmSDMA1_PERFMON_CNTL__VI = 0x9010; -constexpr unsigned int mmSDMA1_PERF_REG_TYPE0__VI = 0x3677; -constexpr unsigned int mmSDMA1_POWER_CNTL_IDLE__VI = 0x362C; -constexpr unsigned int mmSDMA1_PUB_REG_TYPE0__VI = 0x367C; -constexpr unsigned int mmSDMA1_PUB_REG_TYPE1__VI = 0x367D; -constexpr unsigned int mmSDMA1_RD_BURST_CNTL__VI = 0x360F; -constexpr unsigned int mmSDMA1_RLC0_CSA_ADDR_HI__VI = 0x372D; -constexpr unsigned int mmSDMA1_RLC0_CSA_ADDR_LO__VI = 0x372C; -constexpr unsigned int mmSDMA1_RLC0_DUMMY_REG__VI = 0x3731; -constexpr unsigned int mmSDMA1_RLC0_IB_SUB_REMAIN__VI = 0x372F; -constexpr unsigned int mmSDMA1_RLC0_MIDCMD_CNTL__VI = 0x3747; -constexpr unsigned int mmSDMA1_RLC0_MIDCMD_DATA0__VI = 0x3741; -constexpr unsigned int mmSDMA1_RLC0_MIDCMD_DATA1__VI = 0x3742; -constexpr unsigned int mmSDMA1_RLC0_MIDCMD_DATA2__VI = 0x3743; -constexpr unsigned int mmSDMA1_RLC0_MIDCMD_DATA3__VI = 0x3744; -constexpr unsigned int mmSDMA1_RLC0_MIDCMD_DATA4__VI = 0x3745; -constexpr unsigned int mmSDMA1_RLC0_MIDCMD_DATA5__VI = 0x3746; -constexpr unsigned int mmSDMA1_RLC0_PREEMPT__VI = 0x3730; -constexpr unsigned int mmSDMA1_RLC0_WATERMARK__VI = 0x372A; -constexpr unsigned int mmSDMA1_RLC1_CSA_ADDR_HI__VI = 0x37AD; -constexpr unsigned int mmSDMA1_RLC1_CSA_ADDR_LO__VI = 0x37AC; -constexpr unsigned int mmSDMA1_RLC1_DUMMY_REG__VI = 0x37B1; -constexpr unsigned int mmSDMA1_RLC1_IB_SUB_REMAIN__VI = 0x37AF; -constexpr unsigned int mmSDMA1_RLC1_MIDCMD_CNTL__VI = 0x37C7; -constexpr unsigned int mmSDMA1_RLC1_MIDCMD_DATA0__VI = 0x37C1; -constexpr unsigned int mmSDMA1_RLC1_MIDCMD_DATA1__VI = 0x37C2; -constexpr unsigned int mmSDMA1_RLC1_MIDCMD_DATA2__VI = 0x37C3; -constexpr unsigned int mmSDMA1_RLC1_MIDCMD_DATA3__VI = 0x37C4; -constexpr unsigned int mmSDMA1_RLC1_MIDCMD_DATA4__VI = 0x37C5; -constexpr unsigned int mmSDMA1_RLC1_MIDCMD_DATA5__VI = 0x37C6; -constexpr unsigned int mmSDMA1_RLC1_PREEMPT__VI = 0x37B0; -constexpr unsigned int mmSDMA1_RLC1_WATERMARK__VI = 0x37AA; -constexpr unsigned int mmSDMA1_STATUS2_REG__VI = 0x361E; -constexpr unsigned int mmSDMA1_VERSION__VI = 0x362D; -constexpr unsigned int mmSDMA1_VF_ENABLE__VI = 0x362A; -constexpr unsigned int mmSDMA1_VIRT_RESET_REQ__VI = 0x3621; -constexpr unsigned int mmSDMA1_VM_CNTL__VI = 0x361B; -constexpr unsigned int mmSDMA1_VM_CTX_CNTL__VI = 0x3620; -constexpr unsigned int mmSDMA1_VM_CTX_HI__VI = 0x361D; -constexpr unsigned int mmSDMA1_VM_CTX_LO__VI = 0x361C; -constexpr unsigned int mmSEM_ACTIVE_FCN_ID__VI = 0x0F97; -constexpr unsigned int mmSEM_MAILBOX_CLIENTCONFIG_EXTRA__VI = 0x0F9F; -constexpr unsigned int mmSEM_PERFCOUNTER0_RESULT__VI = 0x0F92; -constexpr unsigned int mmSEM_PERFCOUNTER1_RESULT__VI = 0x0F93; -constexpr unsigned int mmSEM_PERFMON_CNTL__VI = 0x0F91; -constexpr unsigned int mmSEM_VF_ENABLE__VI = 0x0F95; -constexpr unsigned int mmSEM_VIRT_RESET_REQ__VI = 0x0F98; -constexpr unsigned int mmSE_CAC_CGTT_CLK_CTRL__VI = 0x3293; -constexpr unsigned int mmSMBCLK_PAD_CNTL__VI = 0x15ED; -constexpr unsigned int mmSMBDAT_PAD_CNTL__VI = 0x15EC; -constexpr unsigned int mmSMBUS_BACO_DUMMY__VI = 0x15EB; -constexpr unsigned int mmSMC_MSG_ARG_11__VI = 0x0093; -constexpr unsigned int mmSMU_BIF_VDDGFX_PWR_STATUS__VI = 0x14F8; -constexpr unsigned int mmSMU_CONTROL__VI = 0x012D; -constexpr unsigned int mmSMU_IND_DATA_0__VI = 0x01A7; -constexpr unsigned int mmSMU_IND_DATA_1__VI = 0x01A9; -constexpr unsigned int mmSMU_IND_DATA_2__VI = 0x01AB; -constexpr unsigned int mmSMU_IND_DATA_3__VI = 0x01AD; -constexpr unsigned int mmSMU_IND_DATA_4__VI = 0x01AF; -constexpr unsigned int mmSMU_IND_DATA_5__VI = 0x01B1; -constexpr unsigned int mmSMU_IND_DATA_6__VI = 0x01B3; -constexpr unsigned int mmSMU_IND_DATA_7__VI = 0x01B5; -constexpr unsigned int mmSMU_IND_INDEX_0__VI = 0x01A6; -constexpr unsigned int mmSMU_IND_INDEX_1__VI = 0x01A8; -constexpr unsigned int mmSMU_IND_INDEX_2__VI = 0x01AA; -constexpr unsigned int mmSMU_IND_INDEX_3__VI = 0x01AC; -constexpr unsigned int mmSMU_IND_INDEX_4__VI = 0x01AE; -constexpr unsigned int mmSMU_IND_INDEX_5__VI = 0x01B0; -constexpr unsigned int mmSMU_IND_INDEX_6__VI = 0x01B2; -constexpr unsigned int mmSMU_IND_INDEX_7__VI = 0x01B4; -constexpr unsigned int mmSMU_INTERRUPT_CONTROL__VI = 0x012E; -constexpr unsigned int mmSMU_MP1_RLC2MP_RESP__VI = 0x01F4; -constexpr unsigned int mmSMU_MP1_SRBM2P_MSG_5__VI = 0x01C5; -constexpr unsigned int mmSMU_RLC_RESPONSE__VI = 0xEC07; -constexpr unsigned int mmSM_CONTROL2__VI = 0x1B6E; -constexpr unsigned int mmSPI_COMPUTE_WF_CTX_SAVE__VI = 0x31FC; -constexpr unsigned int mmSPI_CONFIG_CNTL_2__VI = 0x2451; -constexpr unsigned int mmSPI_DSM_CNTL__VI = 0x2443; -constexpr unsigned int mmSPI_EDC_CNT__VI = 0x2444; -constexpr unsigned int mmSPI_GFX_CNTL__VI = 0x243C; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_12__VI = 0x31F4; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_13__VI = 0x31F5; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_14__VI = 0x31F6; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_CU_15__VI = 0x31F7; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_12__VI = 0x31F8; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_13__VI = 0x31F9; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_14__VI = 0x31FA; -constexpr unsigned int mmSPI_RESOURCE_RESERVE_EN_CU_15__VI = 0x31FB; -constexpr unsigned int mmSPI_START_PHASE__VI = 0x243B; -constexpr unsigned int mmSQC_ATC_EDC_GATCL1_CNT__VI = 0x23B3; -constexpr unsigned int mmSQC_DSM_CNTL__VI = 0x230F; -constexpr unsigned int mmSQC_EDC_CNT__VI = 0x23A0; -constexpr unsigned int mmSQC_GATCL1_CNTL__VI = 0x23B2; -constexpr unsigned int mmSQC_WRITEBACK__VI = 0xC349; -constexpr unsigned int mmSQ_DSM_CNTL__VI = 0x2306; -constexpr unsigned int mmSQ_EDC_DED_CNT__VI = 0x23A2; -constexpr unsigned int mmSQ_EDC_INFO__VI = 0x23A3; -constexpr unsigned int mmSQ_EDC_SEC_CNT__VI = 0x23A1; -constexpr unsigned int mmSQ_M0_GPR_IDX_WORD__VI = 0x23D2; -constexpr unsigned int mmSQ_SMEM_0__VI = 0x237F; -constexpr unsigned int mmSQ_SMEM_1__VI = 0x237F; -constexpr unsigned int mmSQ_THREAD_TRACE_BASE__SI__CI = 0x2380; -constexpr unsigned int mmSQ_THREAD_TRACE_BASE__VI = 0xC330; -constexpr unsigned int mmSQ_THREAD_TRACE_BASE2__VI = 0xC337; -constexpr unsigned int mmSQ_THREAD_TRACE_CTRL__SI__CI = 0x238F; -constexpr unsigned int mmSQ_THREAD_TRACE_CTRL__VI = 0xC335; -constexpr unsigned int mmSQ_THREAD_TRACE_HIWATER__SI__CI = 0x2392; -constexpr unsigned int mmSQ_THREAD_TRACE_HIWATER__VI = 0xC33B; -constexpr unsigned int mmSQ_THREAD_TRACE_MASK__SI__CI = 0x2382; -constexpr unsigned int mmSQ_THREAD_TRACE_MASK__VI = 0xC332; -constexpr unsigned int mmSQ_THREAD_TRACE_MODE__SI__CI = 0x238E; -constexpr unsigned int mmSQ_THREAD_TRACE_MODE__VI = 0xC336; -constexpr unsigned int mmSQ_THREAD_TRACE_PERF_MASK__SI__CI = 0x2384; -constexpr unsigned int mmSQ_THREAD_TRACE_PERF_MASK__VI = 0xC334; -constexpr unsigned int mmSQ_THREAD_TRACE_SIZE__SI__CI = 0x2381; -constexpr unsigned int mmSQ_THREAD_TRACE_SIZE__VI = 0xC331; -constexpr unsigned int mmSQ_THREAD_TRACE_STATUS__SI__CI = 0x238D; -constexpr unsigned int mmSQ_THREAD_TRACE_STATUS__VI = 0xC33A; -constexpr unsigned int mmSQ_THREAD_TRACE_TOKEN_MASK__SI__CI = 0x2383; -constexpr unsigned int mmSQ_THREAD_TRACE_TOKEN_MASK__VI = 0xC333; -constexpr unsigned int mmSQ_THREAD_TRACE_TOKEN_MASK2__VI = 0xC338; -constexpr unsigned int mmSQ_THREAD_TRACE_WPTR__SI__CI = 0x238C; -constexpr unsigned int mmSQ_THREAD_TRACE_WPTR__VI = 0xC339; -constexpr unsigned int mmSQ_VOP_DPP__VI = 0x237F; -constexpr unsigned int mmSQ_VOP_SDWA__VI = 0x237F; -constexpr unsigned int mmSQ_WREXEC_EXEC_HI__VI = 0x23B1; -constexpr unsigned int mmSQ_WREXEC_EXEC_LO__VI = 0x23B1; -constexpr unsigned int mmSRBM_CAM_DATA__SI__CI = 0x0397; -constexpr unsigned int mmSRBM_CAM_DATA__VI = 0xFE35; -constexpr unsigned int mmSRBM_CAM_INDEX__SI__CI = 0x0396; -constexpr unsigned int mmSRBM_CAM_INDEX__VI = 0xFE34; -constexpr unsigned int mmSRBM_CREDIT_RECOVER__VI = 0x039D; -constexpr unsigned int mmSRBM_CREDIT_RECOVER_CNTL__VI = 0x039C; -constexpr unsigned int mmSRBM_CREDIT_RESET__VI = 0x039E; -constexpr unsigned int mmSRBM_DEBUG_SNAPSHOT2__VI = 0x03AD; -constexpr unsigned int mmSRBM_DSM_TRIG_CNTL0__VI = 0x03AF; -constexpr unsigned int mmSRBM_DSM_TRIG_CNTL1__VI = 0x03B0; -constexpr unsigned int mmSRBM_DSM_TRIG_MASK0__VI = 0x03B1; -constexpr unsigned int mmSRBM_DSM_TRIG_MASK1__VI = 0x03B2; -constexpr unsigned int mmSRBM_FIREWALL_ERROR_ADDR__VI = 0x03AC; -constexpr unsigned int mmSRBM_FIREWALL_ERROR_SRC__VI = 0x03AB; -constexpr unsigned int mmSRBM_GFX_CNTL_DATA__VI = 0xFA2F; -constexpr unsigned int mmSRBM_GFX_CNTL_SELECT__VI = 0xFA2E; -constexpr unsigned int mmSRBM_ISP_CLKEN_CNTL__VI = 0x03B9; -constexpr unsigned int mmSRBM_ISP_DOMAIN_ADDR0__VI = 0xFA20; -constexpr unsigned int mmSRBM_ISP_DOMAIN_ADDR1__VI = 0xFA21; -constexpr unsigned int mmSRBM_ISP_DOMAIN_ADDR2__VI = 0xFA22; -constexpr unsigned int mmSRBM_MC_DOMAIN_ADDR0__VI = 0xFA00; -constexpr unsigned int mmSRBM_MC_DOMAIN_ADDR1__VI = 0xFA01; -constexpr unsigned int mmSRBM_MC_DOMAIN_ADDR2__VI = 0xFA02; -constexpr unsigned int mmSRBM_MC_DOMAIN_ADDR3__VI = 0xFA03; -constexpr unsigned int mmSRBM_MC_DOMAIN_ADDR4__VI = 0xFA04; -constexpr unsigned int mmSRBM_MC_DOMAIN_ADDR5__VI = 0xFA05; -constexpr unsigned int mmSRBM_MC_DOMAIN_ADDR6__VI = 0xFA06; -constexpr unsigned int mmSRBM_PERFCOUNTER0_HI__SI__CI = 0x0704; -constexpr unsigned int mmSRBM_PERFCOUNTER0_HI__VI = 0x7C04; -constexpr unsigned int mmSRBM_PERFCOUNTER0_LO__SI__CI = 0x0703; -constexpr unsigned int mmSRBM_PERFCOUNTER0_LO__VI = 0x7C03; -constexpr unsigned int mmSRBM_PERFCOUNTER0_SELECT__SI__CI = 0x0701; -constexpr unsigned int mmSRBM_PERFCOUNTER0_SELECT__VI = 0x7C01; -constexpr unsigned int mmSRBM_PERFCOUNTER1_HI__SI__CI = 0x0706; -constexpr unsigned int mmSRBM_PERFCOUNTER1_HI__VI = 0x7C06; -constexpr unsigned int mmSRBM_PERFCOUNTER1_LO__SI__CI = 0x0705; -constexpr unsigned int mmSRBM_PERFCOUNTER1_LO__VI = 0x7C05; -constexpr unsigned int mmSRBM_PERFCOUNTER1_SELECT__SI__CI = 0x0702; -constexpr unsigned int mmSRBM_PERFCOUNTER1_SELECT__VI = 0x7C02; -constexpr unsigned int mmSRBM_PERFMON_CNTL__SI__CI = 0x0700; -constexpr unsigned int mmSRBM_PERFMON_CNTL__VI = 0x7C00; -constexpr unsigned int mmSRBM_READ_CNTL__VI = 0x0392; -constexpr unsigned int mmSRBM_READ_ERROR2__VI = 0x03AE; -constexpr unsigned int mmSRBM_SAM_DOMAIN_ADDR0__VI = 0xFA1C; -constexpr unsigned int mmSRBM_SAM_DOMAIN_ADDR1__VI = 0xFA1D; -constexpr unsigned int mmSRBM_SAM_DOMAIN_ADDR2__VI = 0xFA1E; -constexpr unsigned int mmSRBM_SDMA_DOMAIN_ADDR0__VI = 0xFA10; -constexpr unsigned int mmSRBM_SDMA_DOMAIN_ADDR1__VI = 0xFA11; -constexpr unsigned int mmSRBM_SDMA_DOMAIN_ADDR2__VI = 0xFA12; -constexpr unsigned int mmSRBM_SDMA_DOMAIN_ADDR3__VI = 0xFA13; -constexpr unsigned int mmSRBM_STATUS3__VI = 0x0395; -constexpr unsigned int mmSRBM_SYS_DOMAIN_ADDR0__VI = 0xFA08; -constexpr unsigned int mmSRBM_SYS_DOMAIN_ADDR1__VI = 0xFA09; -constexpr unsigned int mmSRBM_SYS_DOMAIN_ADDR2__VI = 0xFA0A; -constexpr unsigned int mmSRBM_SYS_DOMAIN_ADDR3__VI = 0xFA0B; -constexpr unsigned int mmSRBM_SYS_DOMAIN_ADDR4__VI = 0xFA0C; -constexpr unsigned int mmSRBM_SYS_DOMAIN_ADDR5__VI = 0xFA0D; -constexpr unsigned int mmSRBM_SYS_DOMAIN_ADDR6__VI = 0xFA0E; -constexpr unsigned int mmSRBM_UVD_DOMAIN_ADDR0__VI = 0xFA14; -constexpr unsigned int mmSRBM_UVD_DOMAIN_ADDR1__VI = 0xFA15; -constexpr unsigned int mmSRBM_UVD_DOMAIN_ADDR2__VI = 0xFA16; -constexpr unsigned int mmSRBM_VCE_DOMAIN_ADDR0__VI = 0xFA18; -constexpr unsigned int mmSRBM_VCE_DOMAIN_ADDR1__VI = 0xFA19; -constexpr unsigned int mmSRBM_VCE_DOMAIN_ADDR2__VI = 0xFA1A; -constexpr unsigned int mmSRBM_VF_ENABLE__VI = 0xFA30; -constexpr unsigned int mmSRBM_VIRT_CNTL__VI = 0xFA31; -constexpr unsigned int mmSRBM_VIRT_RESET_REQ__VI = 0xFA32; -constexpr unsigned int mmSRBM_VP8_CLKEN_CNTL__VI = 0x03BA; -constexpr unsigned int mmSRBM_VP8_DOMAIN_ADDR0__VI = 0xFA24; -constexpr unsigned int mmSWRST_COMMAND_0__VI = 0x14A2; -constexpr unsigned int mmSWRST_COMMAND_1__VI = 0x14A3; -constexpr unsigned int mmSWRST_COMMAND_STATUS__VI = 0x14A0; -constexpr unsigned int mmSWRST_CONTROL_0__VI = 0x14A4; -constexpr unsigned int mmSWRST_CONTROL_1__VI = 0x14A5; -constexpr unsigned int mmSWRST_CONTROL_2__VI = 0x14A6; -constexpr unsigned int mmSWRST_CONTROL_3__VI = 0x14A7; -constexpr unsigned int mmSWRST_CONTROL_4__VI = 0x14A8; -constexpr unsigned int mmSWRST_CONTROL_5__VI = 0x14A9; -constexpr unsigned int mmSWRST_CONTROL_6__VI = 0x14AA; -constexpr unsigned int mmSWRST_EP_COMMAND_0__VI = 0x14AB; -constexpr unsigned int mmSWRST_EP_CONTROL_0__VI = 0x14AC; -constexpr unsigned int mmSWRST_GENERAL_CONTROL__VI = 0x14A1; -constexpr unsigned int mmSX_BLEND_OPT_CONTROL__VI = 0xA1D7; -constexpr unsigned int mmSX_BLEND_OPT_EPSILON__VI = 0xA1D6; -constexpr unsigned int mmSX_MRT0_BLEND_OPT__VI = 0xA1D8; -constexpr unsigned int mmSX_MRT1_BLEND_OPT__VI = 0xA1D9; -constexpr unsigned int mmSX_MRT2_BLEND_OPT__VI = 0xA1DA; -constexpr unsigned int mmSX_MRT3_BLEND_OPT__VI = 0xA1DB; -constexpr unsigned int mmSX_MRT4_BLEND_OPT__VI = 0xA1DC; -constexpr unsigned int mmSX_MRT5_BLEND_OPT__VI = 0xA1DD; -constexpr unsigned int mmSX_MRT6_BLEND_OPT__VI = 0xA1DE; -constexpr unsigned int mmSX_MRT7_BLEND_OPT__VI = 0xA1DF; -constexpr unsigned int mmSX_PS_DOWNCONVERT__VI = 0xA1D5; -constexpr unsigned int mmSYMCLKA_CLOCK_ENABLE__VI = 0x0160; -constexpr unsigned int mmSYMCLKB_CLOCK_ENABLE__VI = 0x0161; -constexpr unsigned int mmSYMCLKC_CLOCK_ENABLE__VI = 0x0162; -constexpr unsigned int mmSYMCLKD_CLOCK_ENABLE__VI = 0x0163; -constexpr unsigned int mmSYMCLKE_CLOCK_ENABLE__VI = 0x0164; -constexpr unsigned int mmSYMCLKF_CLOCK_ENABLE__VI = 0x0165; -constexpr unsigned int mmSYMCLKG_CLOCK_ENABLE__VI = 0x0117; -constexpr unsigned int mmSYS_GRBM_GFX_INDEX_DATA__VI = 0xFA2D; -constexpr unsigned int mmSYS_GRBM_GFX_INDEX_SELECT__VI = 0xFA2C; -constexpr unsigned int mmTCC_DSM_CNTL__VI = 0x2B85; -constexpr unsigned int mmTCC_EDC_CNT__VI = 0x2B82; -constexpr unsigned int mmTCC_EXE_DISABLE__VI = 0x2B84; -constexpr unsigned int mmTCP_ATC_EDC_GATCL1_CNT__VI = 0x32B1; -constexpr unsigned int mmTCP_CNTL2__VI = 0x32B4; -constexpr unsigned int mmTCP_DSM_CNTL__VI = 0x32B3; -constexpr unsigned int mmTCP_EDC_CNT__VI = 0x2B17; -constexpr unsigned int mmTCP_GATCL1_CNTL__VI = 0x32B0; -constexpr unsigned int mmTCP_GATCL1_DSM_CNTL__VI = 0x32B2; -constexpr unsigned int mmTD_DSM_CNTL__VI = 0x252F; -constexpr unsigned int mmTMDS_CNTL__VI = 0x4A6B; -constexpr unsigned int mmTMDS_CONTROL0_FEEDBACK__VI = 0x4A6D; -constexpr unsigned int mmTMDS_CONTROL_CHAR__VI = 0x4A6C; -constexpr unsigned int mmTMDS_CTL0_1_GEN_CNTL__VI = 0x4A75; -constexpr unsigned int mmTMDS_CTL2_3_GEN_CNTL__VI = 0x4A76; -constexpr unsigned int mmTMDS_CTL_BITS__VI = 0x4A72; -constexpr unsigned int mmTMDS_DCBALANCER_CONTROL__VI = 0x4A73; -constexpr unsigned int mmTMDS_DEBUG__VI = 0x4A71; -constexpr unsigned int mmTMDS_STEREOSYNC_CTL_SEL__VI = 0x4A6E; -constexpr unsigned int mmTMDS_SYNC_CHAR_PATTERN_0_1__VI = 0x4A6F; -constexpr unsigned int mmTMDS_SYNC_CHAR_PATTERN_2_3__VI = 0x4A70; -constexpr unsigned int mmUNIPHYA_CHANNEL_XBAR_CNTL__VI = 0x4806; -constexpr unsigned int mmUNIPHYA_LINK_CNTL__VI = 0x4805; -constexpr unsigned int mmUNIPHYB_CHANNEL_XBAR_CNTL__VI = 0x4808; -constexpr unsigned int mmUNIPHYB_LINK_CNTL__VI = 0x4807; -constexpr unsigned int mmUNIPHYC_CHANNEL_XBAR_CNTL__VI = 0x480A; -constexpr unsigned int mmUNIPHYC_LINK_CNTL__VI = 0x4809; -constexpr unsigned int mmUNIPHYD_CHANNEL_XBAR_CNTL__VI = 0x480C; -constexpr unsigned int mmUNIPHYD_LINK_CNTL__VI = 0x480B; -constexpr unsigned int mmUNIPHYE_CHANNEL_XBAR_CNTL__VI = 0x480E; -constexpr unsigned int mmUNIPHYE_LINK_CNTL__VI = 0x480D; -constexpr unsigned int mmUNIPHYF_CHANNEL_XBAR_CNTL__VI = 0x4810; -constexpr unsigned int mmUNIPHYF_LINK_CNTL__VI = 0x480F; -constexpr unsigned int mmUNIPHYG_CHANNEL_XBAR_CNTL__VI = 0x4812; -constexpr unsigned int mmUNIPHYG_LINK_CNTL__VI = 0x4811; -constexpr unsigned int mmUNIPHY_ANG_BIST_CNTL__VI = 0x48CC; -constexpr unsigned int mmUNIPHY_DATA_SYNCHRONIZATION__VI = 0x48CA; -constexpr unsigned int mmUNIPHY_DEBUG__VI = 0x48D6; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKA__VI = 0x4838; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKB__VI = 0x4839; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKC__VI = 0x483F; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKD__VI = 0x4840; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKE__VI = 0x4843; -constexpr unsigned int mmUNIPHY_IMPCAL_LINKF__VI = 0x4844; -constexpr unsigned int mmUNIPHY_IMPCAL_PERIOD__VI = 0x483A; -constexpr unsigned int mmUNIPHY_IMPCAL_PSW_AB__VI = 0x483E; -constexpr unsigned int mmUNIPHY_IMPCAL_PSW_CD__VI = 0x4842; -constexpr unsigned int mmUNIPHY_IMPCAL_PSW_EF__VI = 0x4846; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED0__VI = 0x48C0; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED1__VI = 0x48C1; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED10__VI = 0x48CA; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED11__VI = 0x48CB; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED12__VI = 0x48CC; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED13__VI = 0x48CD; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED14__VI = 0x48CE; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED15__VI = 0x48CF; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED16__VI = 0x48D0; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED17__VI = 0x48D1; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED18__VI = 0x48D2; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED19__VI = 0x48D3; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED2__VI = 0x48C2; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED20__VI = 0x48D4; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED21__VI = 0x48D5; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED22__VI = 0x48D6; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED23__VI = 0x48D7; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED24__VI = 0x48D8; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED25__VI = 0x48D9; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED26__VI = 0x48DA; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED27__VI = 0x48DB; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED28__VI = 0x48DC; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED29__VI = 0x48DD; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED3__VI = 0x48C3; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED30__VI = 0x48DE; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED31__VI = 0x48DF; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED4__VI = 0x48C4; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED5__VI = 0x48C5; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED6__VI = 0x48C6; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED7__VI = 0x48C7; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED8__VI = 0x48C8; -constexpr unsigned int mmUNIPHY_MACRO_CNTL_RESERVED9__VI = 0x48C9; -constexpr unsigned int mmUNIPHY_PLL_CONTROL1__VI = 0x48C6; -constexpr unsigned int mmUNIPHY_PLL_CONTROL2__VI = 0x48C7; -constexpr unsigned int mmUNIPHY_PLL_FBDIV__VI = 0x48C5; -constexpr unsigned int mmUNIPHY_PLL_SS_CNTL__VI = 0x48C9; -constexpr unsigned int mmUNIPHY_PLL_SS_STEP_SIZE__VI = 0x48C8; -constexpr unsigned int mmUNIPHY_POWER_CONTROL__VI = 0x48C4; -constexpr unsigned int mmUNIPHY_REG_TEST_OUTPUT__VI = 0x48CB; -constexpr unsigned int mmUNIPHY_REG_TEST_OUTPUT2__VI = 0x48CD; -constexpr unsigned int mmUNIPHY_TPG_CONTROL__VI = 0x48D4; -constexpr unsigned int mmUNIPHY_TPG_SEED__VI = 0x48D5; -constexpr unsigned int mmUNIPHY_TX_CONTROL1__VI = 0x48C0; -constexpr unsigned int mmUNIPHY_TX_CONTROL2__VI = 0x48C1; -constexpr unsigned int mmUNIPHY_TX_CONTROL3__VI = 0x48C2; -constexpr unsigned int mmUNIPHY_TX_CONTROL4__VI = 0x48C3; -constexpr unsigned int mmUNP_CRC_CONTROL__VI = 0x4630; -constexpr unsigned int mmUNP_CRC_CURRENT__VI = 0x4632; -constexpr unsigned int mmUNP_CRC_LAST__VI = 0x4633; -constexpr unsigned int mmUNP_CRC_MASK__VI = 0x4631; -constexpr unsigned int mmUNP_DEBUG__VI = 0x4636; -constexpr unsigned int mmUNP_DEBUG2__VI = 0x4637; -constexpr unsigned int mmUNP_GRPH_CONTROL__VI = 0x4601; -constexpr unsigned int mmUNP_GRPH_CONTROL_EXP__VI = 0x4603; -constexpr unsigned int mmUNP_GRPH_DFQ_CONTROL__VI = 0x4629; -constexpr unsigned int mmUNP_GRPH_DFQ_STATUS__VI = 0x462A; -constexpr unsigned int mmUNP_GRPH_ENABLE__VI = 0x4600; -constexpr unsigned int mmUNP_GRPH_FLIP_RATE_CNTL__VI = 0x462F; -constexpr unsigned int mmUNP_GRPH_INTERRUPT_CONTROL__VI = 0x462C; -constexpr unsigned int mmUNP_GRPH_INTERRUPT_STATUS__VI = 0x462B; -constexpr unsigned int mmUNP_GRPH_PITCH_C__VI = 0x4617; -constexpr unsigned int mmUNP_GRPH_PITCH_L__VI = 0x4616; -constexpr unsigned int mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__VI = 0x460B; -constexpr unsigned int mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI = 0x460D; -constexpr unsigned int mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI = 0x460C; -constexpr unsigned int mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__VI = 0x460A; -constexpr unsigned int mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__VI = 0x4607; -constexpr unsigned int mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__VI = 0x4609; -constexpr unsigned int mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__VI = 0x4608; -constexpr unsigned int mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__VI = 0x4606; -constexpr unsigned int mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__VI = 0x4613; -constexpr unsigned int mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI = 0x4615; -constexpr unsigned int mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI = 0x4614; -constexpr unsigned int mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__VI = 0x4612; -constexpr unsigned int mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__VI = 0x460F; -constexpr unsigned int mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__VI = 0x4611; -constexpr unsigned int mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__VI = 0x4610; -constexpr unsigned int mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__VI = 0x460E; -constexpr unsigned int mmUNP_GRPH_STEREOSYNC_FLIP__VI = 0x462E; -constexpr unsigned int mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__VI = 0x4628; -constexpr unsigned int mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__VI = 0x4627; -constexpr unsigned int mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C__VI = 0x4626; -constexpr unsigned int mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L__VI = 0x4625; -constexpr unsigned int mmUNP_GRPH_SURFACE_OFFSET_X_C__VI = 0x4619; -constexpr unsigned int mmUNP_GRPH_SURFACE_OFFSET_X_L__VI = 0x4618; -constexpr unsigned int mmUNP_GRPH_SURFACE_OFFSET_Y_C__VI = 0x461B; -constexpr unsigned int mmUNP_GRPH_SURFACE_OFFSET_Y_L__VI = 0x461A; -constexpr unsigned int mmUNP_GRPH_SWAP_CNTL__VI = 0x4605; -constexpr unsigned int mmUNP_GRPH_UPDATE__VI = 0x4624; -constexpr unsigned int mmUNP_GRPH_X_END_C__VI = 0x4621; -constexpr unsigned int mmUNP_GRPH_X_END_L__VI = 0x4620; -constexpr unsigned int mmUNP_GRPH_X_START_C__VI = 0x461D; -constexpr unsigned int mmUNP_GRPH_X_START_L__VI = 0x461C; -constexpr unsigned int mmUNP_GRPH_Y_END_C__VI = 0x4623; -constexpr unsigned int mmUNP_GRPH_Y_END_L__VI = 0x4622; -constexpr unsigned int mmUNP_GRPH_Y_START_C__VI = 0x461F; -constexpr unsigned int mmUNP_GRPH_Y_START_L__VI = 0x461E; -constexpr unsigned int mmUNP_HW_ROTATION__VI = 0x4635; -constexpr unsigned int mmUNP_LB_DATA_GAP_BETWEEN_CHUNK__VI = 0x4634; -constexpr unsigned int mmUNP_TEST_DEBUG_DATA__VI = 0x4639; -constexpr unsigned int mmUNP_TEST_DEBUG_INDEX__VI = 0x4638; -constexpr unsigned int mmUVD_CGC_UDEC_STATUS__VI = 0x3D2D; -constexpr unsigned int mmUVD_JPEG_ADDR_CONFIG__VI = 0x3A1F; -constexpr unsigned int mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH__VI = 0x3C66; -constexpr unsigned int mmUVD_LMI_RBC_IB_64BIT_BAR_LOW__VI = 0x3C67; -constexpr unsigned int mmUVD_LMI_RBC_IB_VMID__VI = 0x3DA1; -constexpr unsigned int mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH__VI = 0x3C68; -constexpr unsigned int mmUVD_LMI_RBC_RB_64BIT_BAR_LOW__VI = 0x3C69; -constexpr unsigned int mmUVD_LMI_RBC_RB_VMID__VI = 0x3DA3; -constexpr unsigned int mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__VI = 0x3C5E; -constexpr unsigned int mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__VI = 0x3C5F; -constexpr unsigned int mmUVD_MIF_CURR_ADDR_CONFIG__VI = 0x3992; -constexpr unsigned int mmUVD_MIF_RECON1_ADDR_CONFIG__VI = 0x39C5; -constexpr unsigned int mmUVD_MIF_REF_ADDR_CONFIG__VI = 0x3993; -constexpr unsigned int mmUVD_PGFSM_CONFIG__VI = 0x38C0; -constexpr unsigned int mmUVD_PGFSM_READ_TILE1__VI = 0x38C2; -constexpr unsigned int mmUVD_PGFSM_READ_TILE2__VI = 0x38C3; -constexpr unsigned int mmUVD_PGFSM_READ_TILE3__VI = 0x38C5; -constexpr unsigned int mmUVD_PGFSM_READ_TILE4__VI = 0x38C6; -constexpr unsigned int mmUVD_PGFSM_READ_TILE5__VI = 0x38C8; -constexpr unsigned int mmUVD_PGFSM_READ_TILE6__VI = 0x38EE; -constexpr unsigned int mmUVD_PGFSM_READ_TILE7__VI = 0x38EF; -constexpr unsigned int mmUVD_POWER_STATUS__VI = 0x38C4; -constexpr unsigned int mmUVD_SUVD_CGC_CTRL__VI = 0x3BE6; -constexpr unsigned int mmUVD_SUVD_CGC_GATE__VI = 0x3BE4; -constexpr unsigned int mmUVD_SUVD_CGC_STATUS__VI = 0x3BE5; -constexpr unsigned int mmUVD_UDEC_ADDR_CONFIG__VI = 0x3BD3; -constexpr unsigned int mmUVD_UDEC_DBW_ADDR_CONFIG__VI = 0x3BD5; -constexpr unsigned int mmUVD_UDEC_DB_ADDR_CONFIG__VI = 0x3BD4; -constexpr unsigned int mmVCE_LMI_CACHE_CTRL__VI = 0x85BD; -constexpr unsigned int mmVCE_LMI_CTRL__VI = 0x85A6; -constexpr unsigned int mmVCE_LMI_CTRL2__VI = 0x859D; -constexpr unsigned int mmVCE_LMI_SWAP_CNTL__VI = 0x85AD; -constexpr unsigned int mmVCE_LMI_SWAP_CNTL1__VI = 0x85AE; -constexpr unsigned int mmVCE_LMI_SWAP_CNTL2__VI = 0x85B3; -constexpr unsigned int mmVCE_LMI_SWAP_CNTL3__VI = 0x859E; -constexpr unsigned int mmVCE_LMI_VCPU_CACHE_40BIT_BAR__VI = 0x8597; -constexpr unsigned int mmVCE_RB_ARB_CTRL__VI = 0x809F; -constexpr unsigned int mmVCE_RB_BASE_HI__VI = 0x8061; -constexpr unsigned int mmVCE_RB_BASE_HI2__VI = 0x805C; -constexpr unsigned int mmVCE_RB_BASE_HI3__VI = 0x80D5; -constexpr unsigned int mmVCE_RB_BASE_LO__VI = 0x8060; -constexpr unsigned int mmVCE_RB_BASE_LO2__VI = 0x805B; -constexpr unsigned int mmVCE_RB_BASE_LO3__VI = 0x80D4; -constexpr unsigned int mmVCE_RB_RPTR__VI = 0x8063; -constexpr unsigned int mmVCE_RB_RPTR2__VI = 0x805E; -constexpr unsigned int mmVCE_RB_RPTR3__VI = 0x80D7; -constexpr unsigned int mmVCE_RB_SIZE__VI = 0x8062; -constexpr unsigned int mmVCE_RB_SIZE2__VI = 0x805D; -constexpr unsigned int mmVCE_RB_SIZE3__VI = 0x80D6; -constexpr unsigned int mmVCE_RB_WPTR__VI = 0x8064; -constexpr unsigned int mmVCE_RB_WPTR2__VI = 0x805F; -constexpr unsigned int mmVCE_RB_WPTR3__VI = 0x80D8; -constexpr unsigned int mmVCE_SOFT_RESET__VI = 0x8048; -constexpr unsigned int mmVCE_STATUS__VI = 0x8001; -constexpr unsigned int mmVCE_SYS_INT_ACK__VI = 0x8541; -constexpr unsigned int mmVCE_SYS_INT_EN__VI = 0x8540; -constexpr unsigned int mmVCE_SYS_INT_STATUS__VI = 0x8541; -constexpr unsigned int mmVCE_UENC_DMA_DCLK_CTRL__VI = 0x8390; -constexpr unsigned int mmVCE_VCPU_CACHE_OFFSET0__VI = 0x8009; -constexpr unsigned int mmVCE_VCPU_CACHE_OFFSET1__VI = 0x800B; -constexpr unsigned int mmVCE_VCPU_CACHE_OFFSET2__VI = 0x800D; -constexpr unsigned int mmVCE_VCPU_CACHE_SIZE0__VI = 0x800A; -constexpr unsigned int mmVCE_VCPU_CACHE_SIZE1__VI = 0x800C; -constexpr unsigned int mmVCE_VCPU_CACHE_SIZE2__VI = 0x800E; -constexpr unsigned int mmVCE_VCPU_CNTL__VI = 0x8005; -constexpr unsigned int mmVGA25_PPLL_ANALOG__VI = 0x171B; -constexpr unsigned int mmVGA25_PPLL_FB_DIV__VI = 0x1715; -constexpr unsigned int mmVGA25_PPLL_POST_DIV__VI = 0x1718; -constexpr unsigned int mmVGA25_PPLL_REF_DIV__VI = 0x1712; -constexpr unsigned int mmVGA28_PPLL_ANALOG__VI = 0x171C; -constexpr unsigned int mmVGA28_PPLL_FB_DIV__VI = 0x1716; -constexpr unsigned int mmVGA28_PPLL_POST_DIV__VI = 0x1719; -constexpr unsigned int mmVGA28_PPLL_REF_DIV__VI = 0x1713; -constexpr unsigned int mmVGA41_PPLL_ANALOG__VI = 0x171D; -constexpr unsigned int mmVGA41_PPLL_FB_DIV__VI = 0x1717; -constexpr unsigned int mmVGA41_PPLL_POST_DIV__VI = 0x171A; -constexpr unsigned int mmVGA41_PPLL_REF_DIV__VI = 0x1714; -constexpr unsigned int mmVGT_DISPATCH_DRAW_INDEX__VI = 0xA2DD; -constexpr unsigned int mmVGT_TESS_DISTRIBUTION__VI = 0xA2D4; -constexpr unsigned int mmVIEWPORT_START_SECONDARY__VI = 0x1B5B; -constexpr unsigned int mmVM_INIT_STATUS__VI = 0x14D3; -constexpr unsigned int mmVM_L2_BANK_SELECT_RESERVED_CID__VI = 0x0579; -constexpr unsigned int mmVM_L2_BANK_SELECT_RESERVED_CID2__VI = 0x057A; -constexpr unsigned int mmVM_L2_CNTL4__VI = 0x0578; -constexpr unsigned int mmWB_DBG_MODE__VI = 0x5E31; -constexpr unsigned int mmWB_DEBUG_CTRL__VI = 0x5E30; -constexpr unsigned int mmWB_EC_CONFIG__VI = 0x5E19; -constexpr unsigned int mmWB_ENABLE__VI = 0x5E18; -constexpr unsigned int mmWB_HW_DEBUG__VI = 0x5E32; -constexpr unsigned int mmWB_SOFT_RESET__VI = 0x5E36; -constexpr unsigned int mmWD_QOS__VI = 0x2242; -constexpr unsigned int mmXDMA_AON_TEST_DEBUG_DATA__VI = 0x03FD; -constexpr unsigned int mmXDMA_AON_TEST_DEBUG_INDEX__VI = 0x03FC; -constexpr unsigned int mmXDMA_CLOCK_GATING_CNTL__VI = 0x03E4; -constexpr unsigned int mmXDMA_IF_BIF_STATUS__VI = 0x03E7; -constexpr unsigned int mmXDMA_IF_STATUS__VI = 0x03E9; -constexpr unsigned int mmXDMA_INTERRUPT__VI = 0x03E3; -constexpr unsigned int mmXDMA_LOCAL_SURFACE_TILING1__VI = 0x03E1; -constexpr unsigned int mmXDMA_LOCAL_SURFACE_TILING2__VI = 0x03E2; -constexpr unsigned int mmXDMA_MC_PCIE_CLIENT_CONFIG__VI = 0x03E0; -constexpr unsigned int mmXDMA_MEM_POWER_CNTL__VI = 0x03E6; -constexpr unsigned int mmXDMA_MSTR_CACHE__VI = 0x040A; -constexpr unsigned int mmXDMA_MSTR_CACHE_BASE_ADDR__VI = 0x0408; -constexpr unsigned int mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI = 0x0409; -constexpr unsigned int mmXDMA_MSTR_CHANNEL_DIM__VI = 0x0402; -constexpr unsigned int mmXDMA_MSTR_CHANNEL_START__VI = 0x040B; -constexpr unsigned int mmXDMA_MSTR_CMD_URGENT_CNTL__VI = 0x03F2; -constexpr unsigned int mmXDMA_MSTR_CNTL__VI = 0x03EC; -constexpr unsigned int mmXDMA_MSTR_HEIGHT__VI = 0x0403; -constexpr unsigned int mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__VI = 0x03EF; -constexpr unsigned int mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__VI = 0x03F0; -constexpr unsigned int mmXDMA_MSTR_LOCAL_SURFACE_PITCH__VI = 0x03F1; -constexpr unsigned int mmXDMA_MSTR_MEM_CLIENT_CONFIG__VI = 0x03EE; -constexpr unsigned int mmXDMA_MSTR_MEM_NACK_STATUS__VI = 0x03F6; -constexpr unsigned int mmXDMA_MSTR_MEM_URGENT_CNTL__VI = 0x03F3; -constexpr unsigned int mmXDMA_MSTR_PCIE_NACK_STATUS__VI = 0x03F5; -constexpr unsigned int mmXDMA_MSTR_PERFMEAS_CNTL__VI = 0x040F; -constexpr unsigned int mmXDMA_MSTR_PERFMEAS_STATUS__VI = 0x040E; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE__VI = 0x040A; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR__VI = 0x0408; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI = 0x0409; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM__VI = 0x0402; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START__VI = 0x040B; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT__VI = 0x0403; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL__VI = 0x040F; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS__VI = 0x040E; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL__VI = 0x0400; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND__VI = 0x0401; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI = 0x0406; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI = 0x0407; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE__VI = 0x0404; -constexpr unsigned int mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI = 0x0405; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE__VI = 0x041A; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR__VI = 0x0418; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI = 0x0419; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM__VI = 0x0412; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START__VI = 0x041B; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT__VI = 0x0413; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL__VI = 0x041F; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS__VI = 0x041E; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL__VI = 0x0410; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND__VI = 0x0411; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI = 0x0416; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI = 0x0417; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE__VI = 0x0414; -constexpr unsigned int mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI = 0x0415; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE__VI = 0x042A; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR__VI = 0x0428; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI = 0x0429; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM__VI = 0x0422; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START__VI = 0x042B; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT__VI = 0x0423; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL__VI = 0x042F; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS__VI = 0x042E; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL__VI = 0x0420; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND__VI = 0x0421; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI = 0x0426; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI = 0x0427; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE__VI = 0x0424; -constexpr unsigned int mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI = 0x0425; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE__VI = 0x043A; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR__VI = 0x0438; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI = 0x0439; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM__VI = 0x0432; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START__VI = 0x043B; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT__VI = 0x0433; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL__VI = 0x043F; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS__VI = 0x043E; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL__VI = 0x0430; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND__VI = 0x0431; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI = 0x0436; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI = 0x0437; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE__VI = 0x0434; -constexpr unsigned int mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI = 0x0435; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE__VI = 0x044A; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR__VI = 0x0448; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI = 0x0449; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM__VI = 0x0442; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START__VI = 0x044B; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT__VI = 0x0443; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL__VI = 0x044F; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS__VI = 0x044E; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL__VI = 0x0440; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND__VI = 0x0441; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI = 0x0446; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI = 0x0447; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE__VI = 0x0444; -constexpr unsigned int mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI = 0x0445; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE__VI = 0x045A; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR__VI = 0x0458; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI = 0x0459; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM__VI = 0x0452; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START__VI = 0x045B; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT__VI = 0x0453; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL__VI = 0x045F; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS__VI = 0x045E; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL__VI = 0x0450; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND__VI = 0x0451; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS__VI = 0x0456; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI = 0x0457; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE__VI = 0x0454; -constexpr unsigned int mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI = 0x0455; -constexpr unsigned int mmXDMA_MSTR_PIPE_CNTL__VI = 0x0400; -constexpr unsigned int mmXDMA_MSTR_READ_COMMAND__VI = 0x0401; -constexpr unsigned int mmXDMA_MSTR_REMOTE_GPU_ADDRESS__VI = 0x0406; -constexpr unsigned int mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI = 0x0407; -constexpr unsigned int mmXDMA_MSTR_REMOTE_SURFACE_BASE__VI = 0x0404; -constexpr unsigned int mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI = 0x0405; -constexpr unsigned int mmXDMA_MSTR_STATUS__VI = 0x03ED; -constexpr unsigned int mmXDMA_MSTR_VSYNC_GSL_CHECK__VI = 0x03F7; -constexpr unsigned int mmXDMA_PERF_MEAS_STATUS__VI = 0x03E8; -constexpr unsigned int mmXDMA_PG_CONTROL__VI = 0x03F9; -constexpr unsigned int mmXDMA_PG_STATUS__VI = 0x03FB; -constexpr unsigned int mmXDMA_PG_WDATA__VI = 0x03FA; -constexpr unsigned int mmXDMA_RBBMIF_RDWR_CNTL__VI = 0x03F8; -constexpr unsigned int mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL__VI = 0x0470; -constexpr unsigned int mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS__VI = 0x0471; -constexpr unsigned int mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI = 0x0472; -constexpr unsigned int mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL__VI = 0x0478; -constexpr unsigned int mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS__VI = 0x0479; -constexpr unsigned int mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI = 0x047A; -constexpr unsigned int mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL__VI = 0x0480; -constexpr unsigned int mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS__VI = 0x0481; -constexpr unsigned int mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI = 0x0482; -constexpr unsigned int mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL__VI = 0x0488; -constexpr unsigned int mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS__VI = 0x0489; -constexpr unsigned int mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI = 0x048A; -constexpr unsigned int mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL__VI = 0x0490; -constexpr unsigned int mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS__VI = 0x0491; -constexpr unsigned int mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI = 0x0492; -constexpr unsigned int mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL__VI = 0x0498; -constexpr unsigned int mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS__VI = 0x0499; -constexpr unsigned int mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI = 0x049A; -constexpr unsigned int mmXDMA_SLV_CHANNEL_CNTL__VI = 0x0470; -constexpr unsigned int mmXDMA_SLV_CNTL__VI = 0x0460; -constexpr unsigned int mmXDMA_SLV_MEM_CLIENT_CONFIG__VI = 0x0461; -constexpr unsigned int mmXDMA_SLV_MEM_NACK_STATUS__VI = 0x0469; -constexpr unsigned int mmXDMA_SLV_PCIE_NACK_STATUS__VI = 0x0468; -constexpr unsigned int mmXDMA_SLV_RDRET_BUF_STATUS__VI = 0x046A; -constexpr unsigned int mmXDMA_SLV_READ_LATENCY_AVE__VI = 0x0467; -constexpr unsigned int mmXDMA_SLV_READ_LATENCY_MINMAX__VI = 0x0466; -constexpr unsigned int mmXDMA_SLV_READ_LATENCY_TIMER__VI = 0x046B; -constexpr unsigned int mmXDMA_SLV_READ_URGENT_CNTL__VI = 0x0463; -constexpr unsigned int mmXDMA_SLV_REMOTE_GPU_ADDRESS__VI = 0x0471; -constexpr unsigned int mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI = 0x0472; -constexpr unsigned int mmXDMA_SLV_SLS_PITCH__VI = 0x0462; -constexpr unsigned int mmXDMA_SLV_WB_RATE_CNTL__VI = 0x0465; -constexpr unsigned int mmXDMA_SLV_WRITE_URGENT_CNTL__VI = 0x0464; -constexpr unsigned int mmXDMA_TEST_DEBUG_DATA__VI = 0x03EB; -constexpr unsigned int mmXDMA_TEST_DEBUG_INDEX__VI = 0x03EA; -#define offset_HEADER__VI -constexpr unsigned int pciMSI_MASK__VI = 0x002B; -constexpr unsigned int pciMSI_MASK_64__VI = 0x002C; -constexpr unsigned int pciMSI_PENDING__VI = 0x002C; -constexpr unsigned int pciMSI_PENDING_64__VI = 0x002D; -constexpr unsigned int pciPCIE_ARI_CAP__VI = 0x00CB; -constexpr unsigned int pciPCIE_ARI_CNTL__VI = 0x00CB; -constexpr unsigned int pciPCIE_ARI_ENH_CAP_LIST__VI = 0x00CA; -constexpr unsigned int pciPCIE_LTR_CAP__VI = 0x00C9; -constexpr unsigned int pciPCIE_LTR_ENH_CAP_LIST__VI = 0x00C8; -constexpr unsigned int pciPCIE_MC_ADDR0__VI = 0x00BE; -constexpr unsigned int pciPCIE_MC_ADDR1__VI = 0x00BF; -constexpr unsigned int pciPCIE_MC_BLOCK_ALL0__VI = 0x00C2; -constexpr unsigned int pciPCIE_MC_BLOCK_ALL1__VI = 0x00C3; -constexpr unsigned int pciPCIE_MC_BLOCK_UNTRANSLATED_0__VI = 0x00C4; -constexpr unsigned int pciPCIE_MC_BLOCK_UNTRANSLATED_1__VI = 0x00C5; -constexpr unsigned int pciPCIE_MC_CAP__VI = 0x00BD; -constexpr unsigned int pciPCIE_MC_CNTL__VI = 0x00BD; -constexpr unsigned int pciPCIE_MC_ENH_CAP_LIST__VI = 0x00BC; -constexpr unsigned int pciPCIE_MC_RCV0__VI = 0x00C0; -constexpr unsigned int pciPCIE_MC_RCV1__VI = 0x00C1; -constexpr unsigned int pciPCIE_SRIOV_CAP__VI = 0x00CD; -constexpr unsigned int pciPCIE_SRIOV_CONTROL__VI = 0x00CE; -constexpr unsigned int pciPCIE_SRIOV_ENH_CAP_LIST__VI = 0x00CC; -constexpr unsigned int pciPCIE_SRIOV_FIRST_VF_OFFSET__VI = 0x00D1; -constexpr unsigned int pciPCIE_SRIOV_FUNC_DEP_LINK__VI = 0x00D0; -constexpr unsigned int pciPCIE_SRIOV_INITIAL_VFS__VI = 0x00CF; -constexpr unsigned int pciPCIE_SRIOV_NUM_VFS__VI = 0x00D0; -constexpr unsigned int pciPCIE_SRIOV_STATUS__VI = 0x00CE; -constexpr unsigned int pciPCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI = 0x00D3; -constexpr unsigned int pciPCIE_SRIOV_SYSTEM_PAGE_SIZE__VI = 0x00D4; -constexpr unsigned int pciPCIE_SRIOV_TOTAL_VFS__VI = 0x00CF; -constexpr unsigned int pciPCIE_SRIOV_VF_BASE_ADDR_0__VI = 0x00D5; -constexpr unsigned int pciPCIE_SRIOV_VF_BASE_ADDR_1__VI = 0x00D6; -constexpr unsigned int pciPCIE_SRIOV_VF_BASE_ADDR_2__VI = 0x00D7; -constexpr unsigned int pciPCIE_SRIOV_VF_BASE_ADDR_3__VI = 0x00D8; -constexpr unsigned int pciPCIE_SRIOV_VF_BASE_ADDR_4__VI = 0x00D9; -constexpr unsigned int pciPCIE_SRIOV_VF_BASE_ADDR_5__VI = 0x00DA; -constexpr unsigned int pciPCIE_SRIOV_VF_DEVICE_ID__VI = 0x00D2; -constexpr unsigned int pciPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI = 0x00DB; -constexpr unsigned int pciPCIE_SRIOV_VF_STRIDE__VI = 0x00D1; -constexpr unsigned int pciPCIE_TPH_REQR_CAP__VI = 0x00B9; -constexpr unsigned int pciPCIE_TPH_REQR_CNTL__VI = 0x00BA; -constexpr unsigned int pciPCIE_TPH_REQR_ENH_CAP_LIST__VI = 0x00B8; -constexpr unsigned int pciPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI = 0x0100; -constexpr unsigned int pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI = 0x0101; -constexpr unsigned int pciPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI = 0x0105; -} // inline namespace Chip -} // namespace Gfx6 -} // namespace Pal - -#endif diff --git a/tools/gfx6_chip/si_ci_vi_merged_pm4_it_opcodes.h b/tools/gfx6_chip/si_ci_vi_merged_pm4_it_opcodes.h deleted file mode 100644 index 0c2ac3ab..00000000 --- a/tools/gfx6_chip/si_ci_vi_merged_pm4_it_opcodes.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - *********************************************************************************************************************** - * - * Copyright (c) 2015-2021 Advanced Micro Devices, Inc. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - **********************************************************************************************************************/ - -#ifndef PM4_IT_OPCODES_H -#define PM4_IT_OPCODES_H - -enum IT_OpCodeType { - IT_NOP = 0x10, - IT_SET_BASE = 0x11, - IT_CLEAR_STATE = 0x12, - IT_INDEX_BUFFER_SIZE = 0x13, - IT_DISPATCH_DIRECT = 0x15, - IT_DISPATCH_INDIRECT = 0x16, - IT_ATOMIC_GDS = 0x1D, - IT_ATOMIC = 0x1E, - IT_OCCLUSION_QUERY = 0x1F, - IT_SET_PREDICATION = 0x20, - IT_REG_RMW = 0x21, - IT_COND_EXEC = 0x22, - IT_PRED_EXEC = 0x23, - IT_DRAW_INDIRECT = 0x24, - IT_DRAW_INDEX_INDIRECT = 0x25, - IT_INDEX_BASE = 0x26, - IT_DRAW_INDEX_2 = 0x27, - IT_CONTEXT_CONTROL = 0x28, - IT_INDEX_TYPE = 0x2A, - IT_DRAW_INDIRECT_MULTI = 0x2C, - IT_DRAW_INDEX_AUTO = 0x2D, - IT_NUM_INSTANCES = 0x2F, - IT_DRAW_INDEX_MULTI_AUTO = 0x30, - IT_INDIRECT_BUFFER_CNST = 0x33, - IT_STRMOUT_BUFFER_UPDATE = 0x34, - IT_DRAW_INDEX_OFFSET_2 = 0x35, - IT_WRITE_DATA = 0x37, - IT_DRAW_INDEX_INDIRECT_MULTI = 0x38, - IT_MEM_SEMAPHORE = 0x39, - IT_COPY_DW__SI__CI = 0x3B, - IT_WAIT_REG_MEM = 0x3C, - IT_INDIRECT_BUFFER = 0x3F, - IT_COND_INDIRECT_BUFFER = 0x3F, - IT_COPY_DATA = 0x40, - IT_CP_DMA = 0x41, - IT_PFP_SYNC_ME = 0x42, - IT_SURFACE_SYNC = 0x43, - IT_COND_WRITE = 0x45, - IT_EVENT_WRITE = 0x46, - IT_EVENT_WRITE_EOP = 0x47, - IT_EVENT_WRITE_EOS = 0x48, - IT_PREAMBLE_CNTL = 0x4A, - IT_CONTEXT_REG_RMW = 0x51, - IT_LOAD_SH_REG = 0x5F, - IT_LOAD_CONFIG_REG = 0x60, - IT_LOAD_CONTEXT_REG = 0x61, - IT_SET_CONFIG_REG = 0x68, - IT_SET_CONTEXT_REG = 0x69, - IT_SET_CONTEXT_REG_INDIRECT = 0x73, - IT_SET_SH_REG = 0x76, - IT_SET_SH_REG_OFFSET = 0x77, - IT_SCRATCH_RAM_WRITE = 0x7D, - IT_SCRATCH_RAM_READ = 0x7E, - IT_LOAD_CONST_RAM = 0x80, - IT_WRITE_CONST_RAM = 0x81, - IT_DUMP_CONST_RAM = 0x83, - IT_INCREMENT_CE_COUNTER = 0x84, - IT_INCREMENT_DE_COUNTER = 0x85, - IT_WAIT_ON_CE_COUNTER = 0x86, - IT_WAIT_ON_DE_COUNTER__SI = 0x87, - IT_WAIT_ON_DE_COUNTER_DIFF = 0x88, - IT_SWITCH_BUFFER = 0x8B, - IT_DRAW_PREAMBLE__CI__VI = 0x36, - IT_RELEASE_MEM__CI__VI = 0x49, - IT_DMA_DATA__CI__VI = 0x50, - IT_ACQUIRE_MEM__CI__VI = 0x58, - IT_REWIND__CI__VI = 0x59, - IT_LOAD_UCONFIG_REG__CI__VI = 0x5E, - IT_SET_QUEUE_REG__CI__VI = 0x78, - IT_SET_UCONFIG_REG__CI__VI = 0x79, - IT_INDEX_ATTRIBUTES_INDIRECT__CI__VI = 0x91, - IT_SET_SH_REG_INDEX__CI__VI = 0x9B, - IT_SET_RESOURCES__CI__VI = 0xA0, - IT_MAP_PROCESS__CI__VI = 0xA1, - IT_MAP_QUEUES__CI__VI = 0xA2, - IT_UNMAP_QUEUES__CI__VI = 0xA3, - IT_QUERY_STATUS__CI__VI = 0xA4, - IT_RUN_LIST__CI__VI = 0xA5, - IT_LOAD_SH_REG_INDEX__VI = 0x63, - IT_LOAD_CONTEXT_REG_INDEX__VI = 0x9F, - IT_DUMP_CONST_RAM_OFFSET__VI = 0x9E, -}; - -#define PM4_TYPE_0 0 -#define PM4_TYPE_2 2 -#define PM4_TYPE_3 3 - -#endif diff --git a/tools/gfx6_chip/si_ci_vi_merged_pm4defs.h b/tools/gfx6_chip/si_ci_vi_merged_pm4defs.h deleted file mode 100644 index 2bfbd269..00000000 --- a/tools/gfx6_chip/si_ci_vi_merged_pm4defs.h +++ /dev/null @@ -1,3628 +0,0 @@ -/* - *********************************************************************************************************************** - * - * Copyright (c) 2017-2021 Advanced Micro Devices, Inc. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - **********************************************************************************************************************/ - -#ifndef __SI_CI_VI_MERGED_PM4DEFS_HEADER -#define __SI_CI_VI_MERGED_PM4DEFS_HEADER - -#include "si_ci_vi_merged_typedef.h" - -/****************************************************************************** -* -* si_ci_vi_merged_pm4defs.h -* -* SI/CI/VI PM4 definitions, typedefs, and enumerations. -* -******************************************************************************/ - -namespace Pal -{ -namespace Gfx6 -{ -inline namespace Chip -{ - -// File version information -#define SI_CI_VI_PM4DEFS_VERSION_MAJOR 3 -#define SI_CI_VI_PM4DEFS_VERSION_MINOR 0 - -// PM4 command shifts -#define PM4_PREDICATE_SHIFT 0 -#define PM4_SHADERTYPE_SHIFT 1 -#define PM4_OP_SHIFT 8 -#define PM4_COUNT_SHIFT 16 -#define PM4_TYPE_SHIFT 30 -#define PM4_T0_ONE_REG_WR_SHIFT 15 -#define PM4_T0_INDX_SHIFT 0 - -// PM4 command control settings -#define PM4_T0_NO_INCR (1 << PM4_T0_ONE_REG_WR_SHIFT) - -// ROLL_CONTEXT defines -#define PM4_SEL_8_CP_STATE 0 -#define PM4_SEL_BLOCK_STATE 1 - -/** -*************************************************************************************************** -* @brief This enum defines the Shader types supported in PM4 type 3 header -*************************************************************************************************** -*/ -enum PM4ShaderType -{ - ShaderGraphics = 0, ///< Graphics shader - ShaderCompute = 1 ///< Compute shader -}; - -/** -*************************************************************************************************** -* @brief This enum defines the predicate value supported in PM4 type 3 header -*************************************************************************************************** -*/ -enum PM4Predicate -{ - PredDisable = 0, ///< Predicate disabled - PredEnable = 1 ///< Predicate enabled -}; - -// PM4 type 3 header macro for creating a PM4 type 3 header -#define PM4_TYPE_3_HDR(opCode, count, shaderType, predicate) \ - ((unsigned int)(predicate << PM4_PREDICATE_SHIFT) | \ - (shaderType << PM4_SHADERTYPE_SHIFT) | \ - (PM4_TYPE_3 << PM4_TYPE_SHIFT) | \ - ((count - 2) << PM4_COUNT_SHIFT) | \ - (opCode << PM4_OP_SHIFT)) - -// PM4 type 0 header macros -#define PM4_TYPE_0_HDR(Reg0, nWrites) \ - ((((unsigned int)(nWrites)-1) << PM4_COUNT_SHIFT) | \ - ((Reg0) << PM4_T0_INDX_SHIFT)) - -// RJVR: This macro needs to be modified to use Type 3 ONE_REG_WRITE. -#define PM4_TYPE_0_HDR_NO_INCR(Reg0, nWrites) \ - ((((unsigned int)(nWrites)-1) << PM4_COUNT_SHIFT) | \ - ((Reg0) << PM4_T0_INDX_SHIFT) | \ - PM4_T0_NO_INCR) - -// PM4 type 2 NOP -#define PM4_TYPE_2_NOP (PM4_TYPE_2 << PM4_TYPE_SHIFT) - -//------------------------------------------------------------------------------------------------- - -typedef union _PM4_TYPE_0_HEADER -{ - struct - { - unsigned int base : 16;///< the DWORD Memory-mapped address - unsigned int count : 14;///< count of DWORDs in the *information* body (N - 1 for N dwords) - unsigned int type : 2;///< packet identifier. It should be 0 for type 0 packets. - }; - unsigned int u32All; - -} PM4_TYPE_0_HEADER; - -//------------------------------------------------------------------------------------------------- - -typedef union PM4_TYPE_3_HEADER -{ - struct - { - unsigned int predicate : 1; ///< predicated version of packet when set - unsigned int shaderType: 1; ///< 0: Graphics, 1: Compute Shader - unsigned int reserved1 : 6; ///< reserved - unsigned int opcode : 8; ///< IT opcode - unsigned int count : 14;///< number of DWORDs - 1 in the information body. - unsigned int type : 2; ///< packet identifier. It should be 3 for type 3 packets - }; - unsigned int u32All; -} PM4_TYPE_3_HEADER; - -//------------------------------------------------------------------------------------------------- - -typedef union _CONTEXT_CONTROL_ENABLE -{ - struct - { - unsigned int enableSingleCntxConfigReg : 1; ///< single context config reg - unsigned int enableMultiCntxRenderReg : 1; ///< multi context render state reg - unsigned int reserved1 : 13; ///< reserved - unsigned int enableUserConfigReg__CI : 1; ///< User Config Reg on CI(reserved for SI) - unsigned int enableGfxSHReg : 1; ///< Gfx SH Registers - unsigned int reserved2 : 7; ///< reserved - unsigned int enableCSSHReg : 1; ///< CS SH Registers - unsigned int reserved3 : 6; ///< reserved - unsigned int enableDw : 1; ///< DW enable - }; - unsigned int u32All; -} CONTEXT_CONTROL_ENABLE; - -//------------------------------------------------------------------------------------------------- - -typedef struct _PM4CMDCONTEXTCONTROL -{ - union - { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; - union - { - CONTEXT_CONTROL_ENABLE loadControl; ///< enable bits for loading - unsigned int ordinal2; - }; - union - { - CONTEXT_CONTROL_ENABLE shadowEnable;///< enable bits for shadowing - unsigned int ordinal3; - }; - -} PM4CMDCONTEXTCONTROL, *PPM4CMDCONTEXTCONTROL; - -//------------------------------------------------------------------------------------------------- -typedef union _LOAD_ADDRESS_HIGH -{ - struct - { - unsigned int ADDR_HI : 16; ///< bits (47:32) for the block in Memory from where - ///< the CP will fetch the state - unsigned int reserved1 : 15; ///< reserved - unsigned int WAIT_IDLE : 1; ///< if set the CP will wait for the graphics pipe to - ///< be idle by writing to the GRBM Wait Until register - ///< with "Wait for 3D idle" - }; - unsigned int u32All; -} LOAD_ADDRESS_HIGH; - -//------------------------------------------------------------------------------------------------- - -// PM4CMDLOADDATA can be used with the following opcodes -// - IT_LOAD_CONFIG_REG -// - IT_LOAD_CONTEXT_REG -// - IT_LOAD_SH_REG -typedef struct _PM4CMDLOADDATA -{ - union - { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; - union - { - unsigned int addrLo; ///< low 32 address bits for the block in memory from where - ///< the CP will fetch the state - unsigned int ordinal2; - }; - union - { - LOAD_ADDRESS_HIGH addrHi; - unsigned int ordinal3; - }; - union - { - unsigned int regOffset; ///< offset in DWords from the register base address - unsigned int ordinal4; - }; - union - { - unsigned int numDwords; ///< number of DWords that the CP will fetch and write - ///< into the chip. A value of zero will fetch nothing - unsigned int ordinal5; - }; - // This is a variable length packet. So, based on size in header, the layout following this - // looks as follows (offser/numDwords pairs). - // unsigned int offset1; - // unsigned int numDwords1; - // ... - // unsigned int offsetN; - // unsigned int numDwordsN; - -} PM4CMDLOADDATA, *PPM4CMDLOADDATA; - -//------------------------------------------------------------------------------------------------- -typedef union _LOAD_ADDRESS_LOW -{ - struct - { - unsigned int index : 1; ///< 0 : ADDR_LO is direct address - ///< 1 : ARRD_LO is ignored and memory offset is in ordinal 3 - unsigned int reserved : 1; ///< reserved - unsigned int ADDR_LO : 30; ///< bits (31:2) for the block in Memory from where - ///< the CP will fetch the state. DWORD aligned - }; - unsigned int u32All; -} LOAD_ADDRESS_LOW; - -//------------------------------------------------------------------------------------------------- - -// PM4CMDLOADDATAINDEX can be used with the following opcodes (VI+) -// - IT_LOAD_CONTEXT_REG_INDEX -// - IT_LOAD_SH_REG_INDEX - -// Index values (VI+) -#define LOAD_DATA_INDEX_DIRECT_ADDR 0 // Direct load from memory address -#define LOAD_DATA_INDEX_OFFSET 1 // Load from indirect memory offset (_INDEX packets) - -#define LOAD_DATA_FORMAT_OFFSET_AND_SIZE 0 // Data is consecutive DWORDs -#define LOAD_DATA_FORMAT_OFFSET_AND_DATA 1 // Register offset and data is interleaved - -typedef struct _PM4CMDLOADDATAINDEX -{ - union - { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; - union - { - LOAD_ADDRESS_LOW addrLo; ///< low 32 address bits for the block in memory from where - ///< the CP will fetch the state - unsigned int ordinal2; - }; - union - { - unsigned int addrOffset; ///< addrLo.index = 1 Indexed mode - unsigned int ordinal3; - }; - union - { - struct - { - unsigned int regOffset : 16; ///< offset in DWords from the register base address - unsigned int reserved : 15; - unsigned int dataFormat : 1; ///< LOAD_DATA_FORMAT_* - }; - unsigned int ordinal4; - }; - union - { - unsigned int numDwords; ///< number of DWords that the CP will fetch and write - ///< into the chip. A value of zero will fetch nothing - unsigned int ordinal5; - }; - // This is a variable length packet. So, based on size in header, the layout following this - // looks as follows (offser/numDwords pairs). - // unsigned int offset1; - // unsigned int numDwords1; - // ... - // unsigned int offsetN; - // unsigned int numDwordsN; - -} PM4CMDLOADDATAINDEX, *PPM4CMDLOADDATAINDEX; - -//------------------------------------------------------------------------------------------------- - -// PM4CMDSETDATA can be used with the following opcodes: -// -// - IT_SET_CONFIG_REG -// - IT_SET_CONTEXT_REG -// - IT_SET_CONTEXT_REG_INDIRECT -// - IT_SET_SH_REG -// - IT_SET_SH_REG_INDEX -// - IT_SET_UCONFIG_REG - -// SET_CONTEXT_REG index values (CI+) -#define SET_CONTEXT_INDEX_DEFAULT 0 // Use this for all registers except the following... -#define SET_CONTEXT_INDEX_MULTI_VGT_PARAM 1 // Use this when writing IA_MULTI_VGT_PARAM -#define SET_CONTEXT_INDEX_VGT_LS_HS_CONFIG 2 // Use this when writing VGT_LS_HS_CONFIG -#define SET_CONTEXT_INDEX_PA_SC_RASTER_CONFIG 3 // Use this when writing PA_SC_RASTER_CONFIG - -#define SET_CONTEXT_INDEX_SHIFT 28 // Offset in ordinal2 of the index field. - -// SET_UCONFIG_REG index values (CI+) -#define SET_UCONFIG_INDEX_DEFAULT 0 // Use this for all registers except the following... -#define SET_UCONFIG_INDEX_PRIM_TYPE 1 // Use this when writing VGT_PRIMITIVE_TYPE -#define SET_UCONFIG_INDEX_INDEX_TYPE 2 // Use this when writing VGT_INDEX_TYPE -#define SET_UCONFIG_INDEX_NUM_INSTANCES 3 // Use this when writing VGT_NUM_INSTANCES - -// SET_SH_REG_INDEX index values (Hawaii, VI+) -// Index (0-2): reserved -#define SET_SH_REG_INDEX_CP_MODIFY_CU_MASK 3 // Use this to modify CU_EN for COMPUTE_STATIC* and SPI_SHADER_PGM_RSRC3* - // CP performs AND operation on KMD and UMD CU masks to write registers. - -typedef struct _PM4CMDSETDATA -{ - union - { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; - union - { - struct - { - unsigned int regOffset : 16; ///< offset in DWords from the register base address - unsigned int reserved1 : 12; ///< Program to zero - unsigned int index : 4; ///< Index for UCONFIG/CONTEXT on CI+ - ///< Program to zero for other opcodes and on SI - }; - unsigned int ordinal2; - }; - // This is a variable length packet. So, based on size in header, the layout following this - // looks as follows: - // Data for SET_CONTEXT_REG - // DW Offset into Patch table for SET_CONTEXT_REG_INDIRECT - // unsigned int data0; - // ... - // unsigned int dataN; - -} PM4CMDSETDATA, *PPM4CMDSETDATA; - -//------------------------------------------------------------------------------------------------- - -typedef struct _PM4CMDNOP -{ - union - { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; -} PM4CMDNOP, *PPM4CMDNOP; - -//------------------------------------------------------------------------------------------------- - -typedef struct _PM4CMDDRAWINDEXOFFSET2 -{ - union - { - PM4_TYPE_3_HEADER header; ///
) the Reference Value. - ///< 111 = Reserved. If ENGINE=PFP, only 101/Greater Than or Equal is valid, since that is all the ucode implemented in the PFP. - unsigned int operation : 2; ///< operation: - ///< 0 = Write Reference to Address0 -> Poll Address1 -> Write Reference to Address 1 - unsigned int reserved1 : 3; - unsigned int engine : 1; ///< engine, 0 = ME, 1 = PFP - unsigned int reserved2 : 23; - }; - - unsigned int ordinal2; - }; - - union - { - unsigned int addrLo; - unsigned int ordinal3; - }; - - union - { - unsigned int addrHi; - unsigned int ordinal4; - }; - - union - { - unsigned int reference; - unsigned int ordinal5; - }; - - union - { - unsigned int mask; - unsigned int ordinal6; - }; - - union - { - struct - { - unsigned int pollInterval : 16; - unsigned int reserved4 : 16; - }; - unsigned int ordinal7; - }; -} PM4WRITEDATACONFIRM, *PPM4WRITEDATACONFIRM; - -//------------------------------------------------------------------------------------------------- -typedef struct _PM4DMADATA { - union - { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; - - union - { - struct - { - unsigned int engine : 1; - unsigned int reserved1 : 11; - unsigned int srcATC : 1; - unsigned int srcCachePolicy : 2; - unsigned int srcVolatile : 1; - unsigned int reserved2 : 4; - unsigned int dstSel : 2; - unsigned int reserved3 : 2; - unsigned int dstATC : 1; - unsigned int dstCachePolicy : 2; - unsigned int dstVolatile : 1; - unsigned int reserved4 : 1; - unsigned int srcSel : 2; - unsigned int cpSync : 1; - }; - unsigned int ordinal2; - }; - - union - { - unsigned int srcAddrLo; - unsigned int data; - unsigned int ordinal3; - }; - - union - { - unsigned int srcAddrHi; - unsigned int ordinal4; - }; - - union - { - unsigned int dstAddrLo; - unsigned int ordinal5; - }; - - union - { - unsigned int dstAddrHi; - unsigned int ordinal6; - }; - - union - { - struct - { - unsigned int byteCount : 21; - unsigned int disWC : 1; - unsigned int srcSwap : 2; - unsigned int dstSwap : 2; - unsigned int sas : 1; - unsigned int das : 1; - unsigned int saic : 1; - unsigned int daic : 1; - unsigned int rawWait : 1; - unsigned int reserved5 : 1; - }; - - unsigned int command; - unsigned int ordinal7; - }; -} PM4DMADATA, *PPM4DMADATA; - -//------------------------------------------------------------------------------------------------- -typedef struct _PM4CMDRELEASEMEM -{ - union - { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; - union - { - struct - { - unsigned int eventType : 6; ///< event type written to VGT_EVENT_INITIATOR - unsigned int reserved1 : 2; ///< reserved - unsigned int eventIndex : 4; ///< event index - unsigned int tcl1VolActionEna : 1; ///< - unsigned int tcVolActionEna : 1; ///< - unsigned int reserved2 : 1; - unsigned int tcWbActionEna : 1; ///< - unsigned int tcl1ActionEna : 1; ///< - unsigned int tcActionEna : 1; - unsigned int reserved3 : 7; - unsigned int cachePolicy : 2; ///< Cache Policy setting used for writing fences and timestamps to the TCL2 - unsigned int _volatile__CI : 1; ///< Volatile setting used for writing fences and timestamps to the TCL2. - unsigned int reserved5 : 4; - }; - unsigned int ordinal2; - }; - union - { - struct - { - unsigned int reserved6 : 16; ///< reserved - unsigned int dstSel : 2; ///< destination select - unsigned int reserved7 : 6; ///< reserved - unsigned int intSel : 3; ///< selects interrupt action for end-of-pipe - unsigned int reserved8 : 2; ///< reserved - unsigned int dataSel : 3; ///< selects source of data - }; - unsigned int ordinal3; - }; - union - { - unsigned int addressLo; ///< low bits of address - unsigned int ordinal4; - }; - union - { - unsigned int addressHi; ///< high bits of address - unsigned int ordinal5; - }; - union - { - struct - { - unsigned int gdsIndex : 16; ///< Byte offset into GDS to copy from - unsigned int numDwords : 16; ///< Number of DWORDS of GDS to copy - }; - unsigned int dataLo; ///< value that will be written to memory when event occurs - unsigned int ordinal6; - }; - union - { - unsigned int dataHi; ///< value that will be written to memory when event occurs - unsigned int ordinal7; - }; -} PM4CMDRELEASEMEM, *PPM4CMDRELEASEMEM; - -// EVENT_WRITE_EOP packet definitions -#define RELEASEMEM_DST_SEL_MEMORY 0 -#define RELEASEMEM_DST_SEL_L2 1 - -#define RELEASEMEM_DATA_SEL_DISCARD 0 -#define RELEASEMEM_DATA_SEL_SEND_DATA32 1 -#define RELEASEMEM_DATA_SEL_SEND_DATA64 2 -#define RELEASEMEM_DATA_SEL_SEND_GPU_CLOCK 3 -#define RELEASEMEM_DATA_SEL_SEND_CP_PERFCOUNTER 4 -#define RELEASEMEM_DATA_SEL_STORE_GDS_DATA 5 - -#define RELEASEMEM_INT_SEL_NONE 0 -#define RELEASEMEM_INT_SEL_SEND_INT 1 -#define RELEASEMEM_INT_SEL_SEND_INT_ON_CONFIRM 2 -#define RELEASEMEM_INT_SEL_SEND_DATA_ON_CONFIRM 3 - -//------------------------------------------------------------------------------------------------- -typedef struct _PM4CMDREWIND -{ - union - { - PM4_TYPE_3_HEADER header; ///< header - unsigned int ordinal1; - }; - union - { - struct - { - unsigned int reserved0 : 24; ///< Reserved - unsigned int offloadEnable : 1; ///< Enable offload polling valid bit to IQ - unsigned int reserved1 : 6; ///< Reserved - unsigned int valid : 1; ///< Set when subsequent packets are valid - }; - unsigned int ordinal2; - }; -} PM4CMDREWIND, *PPM4CMDREWIND; - -// Rewind packet valid bit mask -#define REWIND_MASK_VALID 0x800000000 - -//------------------------------------------------------------------------------------------------- -// PM4 command template sizes -#define PM4_CMD_NOP_DWORDS \ - (sizeof(PM4CMDNOP) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_PREAMBLE_DWORDS \ - (sizeof(PM4CMDDRAWPREAMBLE) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDEX_2_DWORDS \ - (sizeof(PM4CMDDRAWINDEX2) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDEX_OFFSET_2_DWORDS \ - (sizeof(PM4CMDDRAWINDEXOFFSET2) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDEX_AUTO_DWORDS \ - (sizeof(PM4CMDDRAWINDEXAUTO) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDEX_IMMD_DWORDS \ - (sizeof(PM4CMDDRAWINDEXIMMD) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDEX_TYPE_DWORDS \ - (sizeof(PM4CMDDRAWINDEXTYPE) / sizeof(unsigned int)) - -#define PM4_CMD_INDEX_ATTRIBUTES_INDIRECT_DWORDS \ - (sizeof(PM4CMDINDEXATTRIBUTESINDIRECT) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDEX_BUFFER_SIZE_DWORDS \ - (sizeof(PM4CMDDRAWINDEXBUFFERSIZE) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_NUM_INSTANCES_DWORDS \ - (sizeof(PM4CMDDRAWNUMINSTANCES) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDEX_BASE_DWORDS \ - (sizeof(PM4CMDDRAWINDEXBASE) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_SET_BASE_DWORDS \ - (sizeof(PM4CMDDRAWSETBASE) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDIRECT_DWORDS \ - (sizeof(PM4CMDDRAWINDIRECT) / sizeof(unsigned int)) - -#define PM4_CMD_LOAD_DATA_DWORDS \ - (sizeof(PM4CMDLOADDATA) / sizeof(unsigned int)) - -#define PM4_CMD_LOAD_DATA_INDEX_DWORDS \ - (sizeof(PM4CMDLOADDATAINDEX) / sizeof(unsigned int)) - -#define PM4_CMD_SET_DATA_DWORDS \ - (sizeof(PM4CMDSETDATA) / sizeof(unsigned int)) - -#define PM4_CMD_WAIT_REG_MEM_DWORDS \ - (sizeof(PM4CMDWAITREGMEM) / sizeof(unsigned int)) - -#define PM4_CMD_WAIT_REG_MEM64_DWORDS \ - (sizeof(PM4CMDWAITREGMEM64) / sizeof(unsigned int)) - -#define PM4_CMD_WAIT_EVENT_WRITE_DWORDS \ - (sizeof(PM4CMDEVENTWRITE) / sizeof(unsigned int)) - -#define PM4_CMD_WAIT_EVENT_WRITE_QUERY_DWORDS \ - (sizeof(PM4CMDEVENTWRITEQUERY) / sizeof(unsigned int)) - -#define PM4_CMD_WAIT_EVENT_WRITE_EOP_DWORDS \ - (sizeof(PM4CMDEVENTWRITEEOP) / sizeof(unsigned int)) - -#define PM4_CMD_STRMOUT_BUFFER_UPDATE_DWORDS \ - (sizeof(PM4CMDSTRMOUTBUFFERUPDATE) / sizeof(unsigned int)) - -#define PM4_CMD_CONTEXT_CTL_DWORDS \ - (sizeof(PM4CMDCONTEXTCONTROL) / sizeof(unsigned int)) - -#define PM4_CMD_SET_PREDICATION_DWORDS \ - (sizeof(PM4CMDSETPREDICATION) / sizeof(unsigned int)) - -#define PM4_CMD_SURFACE_SYNC_DWORDS \ - (sizeof(PM4CMDSURFACESYNC) / sizeof(unsigned int)) - -#define PM4_CMD_DISPATCH_DIRECT_DWORDS \ - (sizeof(PM4CMDDISPATCHDIRECT) / sizeof(unsigned int)) - -#define PM4_CMD_DISPATCH_INDIRECT_DWORDS \ - (sizeof(PM4CMDDISPATCHINDIRECT) / sizeof(unsigned int)) - -#define PM4_CMD_DISPATCH_INDIRECT_MEC_DWORDS \ - (sizeof(PM4CMDDISPATCHINDIRECTMEC) / sizeof(unsigned int)) - -#define PM4_CMD_CLEAR_STATE_DWORDS \ - (sizeof(PM4CMDCLEARSTATE) / sizeof(unsigned int)) - -#define PM4_CMD_EVENT_WRITE_EOS_DWORDS \ - (sizeof(PM4CMDEVENTWRITEEOS) / sizeof(unsigned int)) - -#define PM4_CMD_SCRATCH_RAM_WRITE_DWORDS \ - (sizeof(PM4CMDSCRATCHRAMWRITE) / sizeof(unsigned int)) - -#define PM4_CMD_WRITE_CONST_RAM_DWORDS \ - (sizeof(PM4CMDCONSTRAMWRITE) / sizeof(unsigned int)) - -#define PM4_CMD_DUMP_CONST_RAM_DWORDS \ - (sizeof(PM4CMDCONSTRAMDUMP) / sizeof(unsigned int)) - -#define PM4_CMD_DUMP_CONST_RAM_OFFSET_DWORDS \ - (sizeof(PM4CMDCONSTRAMDUMPOFFSET) / sizeof(unsigned int)) - -#define PM4_CMD_LOAD_CONST_RAM_DWORDS \ - (sizeof(PM4CMDCONSTRAMLOAD) / sizeof(unsigned int)) - -#define PM4_CMD_INC_CE_COUNTER_DWORDS \ - (sizeof(PM4CMDINCCECOUNTER) / sizeof(unsigned int)) - -#define PM4_CMD_INC_DE_COUNTER_DWORDS \ - (sizeof(PM4CMDINCDECOUNTER) / sizeof(unsigned int)) - -#define PM4_CMD_SET_CE_DE_COUNTERS_DWORDS \ - (sizeof(PM4CMDSETCEDECOUNTERS) / sizeof(unsigned int)) - -#define PM4_CMD_WAIT_ON_AVAIL_BUFFER_DWORDS \ - (sizeof(PM4CMDWAITONAVAILBUFFER) / sizeof(unsigned int)) - -#define PM4_CMD_WAIT_ON_CE_COUNTER_DWORDS \ - (sizeof(PM4CMDWAITONCECOUNTER) / sizeof(unsigned int)) - -#define PM4_CMD_WAIT_ON_DE_COUNTER_DIFF_DWORDS \ - (sizeof(PM4CMDWAITONDECOUNTERDIFF) / sizeof(unsigned int)) - -// Miscellaneous defines -#define PM4_CMD_MAX_SIZE_DWORDS (1 << 14) - -#define PM4_SETTING_PRED_EXEC(mask, count) ((mask << 24) | count) - -//------------------------------------------------------------------------------------------------- - -#define PM4_CMD_INDIRECT_BUFFER_CONST_DWORDS \ - (sizeof(PM4CMDINDIRECTBUFFER) / sizeof(unsigned int)) - -#define PM4_CMD_INDIRECT_BUFFER_DWORDS \ - (sizeof(PM4CMDINDIRECTBUFFER) / sizeof(unsigned int)) - -#define PM4_CMD_COND_INDIRECT_BUFFER_DWORDS \ - (sizeof(PM4CMDCONDINDIRECTBUFFER) / sizeof(unsigned int)) - -#define PM4_CMD_SET_SH_REG_OFFSET_DWORDS \ - (sizeof(PM4CMDSETSHREGOFFSET) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDEX_INDIRECT_DWORDS \ - (sizeof(PM4CMDDRAWINDEXINDIRECT) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDEX_INDIRECT_MULTI_DWORDS \ - (sizeof(PM4CMDDRAWINDEXINDIRECTMULTI) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDEX_MULTI_AUTO_DWORDS \ - (sizeof(PM4CMDDRAWINDEXMULTIAUTO) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDIRECT_DWORDS \ - (sizeof(PM4CMDDRAWINDIRECT) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDIRECT_MULTI_DWORDS \ - (sizeof(PM4CMDDRAWINDIRECTMULTI) / sizeof(unsigned int)) - -#define PM4_CMD_INCREMENT_DE_COUNTER_DWORDS \ - (sizeof(PM4CMDINCREMENTCOUNTER) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_INDEX_BASE_DWORDS \ - (sizeof(PM4CMDDRAWINDEXBASE) / sizeof(unsigned int)) - -#define PM4_CMD_DRAW_MPEG_INDEX_DWORDS \ - (sizeof(PM4CMDDRAWMPEGINDEX) / sizeof(unsigned int)) - -#define PM4_CMD_COND_EXEC_DWORDS \ - (sizeof(PM4CMDCONDEXEC) / sizeof(unsigned int)) - -#define PM4_CMD_COND_EXEC_CI_DWORDS \ - (sizeof(PM4CMDCONDEXEC_CI) / sizeof(unsigned int)) - -#define PM4_CMD_COND_WRITE_DWORDS \ - (sizeof(PM4CMDCONDWRITE) / sizeof(unsigned int)) - -#define PM4_CMD_PRED_EXEC_DWORDS \ - (sizeof(PM4CMDPREDEXEC) / sizeof(unsigned int)) - -#define PM4_CMD_ATOMIC_DWORDS \ - (sizeof(PM4CMDATOMIC) / sizeof(unsigned int)) - -#define PM4_CMD_ATOMIC_GDS_DWORDS \ - (sizeof(PPM4CMDATOMICGDS) / sizeof(unsigned int)) - -#define PM4_CMD_OCCLUSION_QUERY_DWORDS \ - (sizeof(PM4CMDOCCLUSIONQUERY) / sizeof(unsigned int)) - -#define PM4_CMD_ALLOC_GDS_DWORDS \ - (sizeof(PM4CMDALLOCGDS) / sizeof(unsigned int)) - -#define PM4_CMD_CP_DMA_DWORDS \ - (sizeof(PM4CMDCPDMA) / sizeof(unsigned int)) - -#define PM4_CMD_REG_RMW_DWORDS \ - (sizeof(PM4CMDREGRMW) / sizeof(unsigned int)) - -#define PM4_CONTEXT_REG_RMW_DWORDS \ - (sizeof(PM4CONTEXTREGRMW) / sizeof(unsigned int)) - -#define PM4_CMD_WRITE_GDS_RAM_DWORDS \ - (sizeof(PM4CMDWRITEGDSRAM) / sizeof(unsigned int)) - -#define PM4_CMD_WRITE_DATA_DWORDS \ - (sizeof(PM4CMDWRITEDATA) / sizeof(unsigned int)) - -#define PM4_CMD_WRITE_CONST_RAM_OFFSET_DWORDS \ - (sizeof(PM4CMDCONSTRAMWRITE) / sizeof(unsigned int)) - -#define PM4_CMD_LOAD_CONFIG_REG_DWORDS \ - (sizeof(PM4CMDLOADDATA) / sizeof(unsigned int)) - -#define PM4_CMD_SET_CONFIG_REG_DWORDS \ - (sizeof(PM4CMDSETDATA) / sizeof(unsigned int)) - -#define PM4_CMD_PREAMBLE_CNTL_REG_DWORDS \ - (sizeof(PM4CMDPREAMBLECNTL) / sizeof(unsigned int)) - -#define PM4_CMD_SET_CONTEXT_REG_DWORDS \ - (sizeof(PM4CMDSETDATA) / sizeof(unsigned int)) - -#define PM4_CMD_SET_CONTEXT_REG_INDIRECT_DWORDS \ - (sizeof(PM4CMDSETDATA) / sizeof(unsigned int)) - -#define PM4_CMD_LOAD_CONTEXT_REG_DWORDS \ - (sizeof(PM4CMDLOADDATA) / sizeof(unsigned int)) - -#define PM4_CMD_LOAD_SH_REG_DWORDS \ - (sizeof(PM4CMDLOADDATA) / sizeof(unsigned int)) - -#define PM4_CMD_SET_SH_REG_DWORDS \ - (sizeof(PM4CMDSETDATA) / sizeof(unsigned int)) - -#define PM4_CMD_WRITE_CONST_RAM_INDIRECT_DWORDS \ - (sizeof(PM4CMDCONSTRAMWRITE) / sizeof(unsigned int)) - -#define PM4_CMD_MEM_SEMAPHORE_DWORDS \ - (sizeof(PM4CMDMEMSEMAPHORE) / sizeof(unsigned int)) - -#define PM4_CMD_PFP_SYNC_ME_DWORDS \ - (sizeof(PM4CMDPFPSYNCME) / sizeof(unsigned int)) - -#define PM4_CMD_COPY_DATA_DWORDS \ - (sizeof(PM4CMDCOPYDATA) / sizeof(unsigned int)) - -#define PM4_CMD_ACQUIRE_MEM_DWORDS \ - (sizeof(PM4ACQUIREMEM) / sizeof (unsigned int)) - -#define PM4_CMD_ATOMIC_MEM_DWORDS \ - (sizeof(PM4ATOMICMEM_CI) / sizeof (unsigned int)) - -#define PM4_CMD_WRITE_DATA_CONFIRM_DWORDS \ - (sizeof(PM4WRITEDATACONFIRM) / sizeof (unsigned int)) - -#define PM4_CMD_DMA_DATA_DWORDS \ - (sizeof(PM4DMADATA) / sizeof (unsigned int)) - -#define PM4_CMD_RELEASE_MEM_DWORDS \ - (sizeof(PM4CMDRELEASEMEM) / sizeof (unsigned int)) - -#define PM4_CMD_REWIND_DWORDS \ - (sizeof(PM4CMDREWIND) / sizeof(unsigned int)) - -} // inline namespace Chip -} // namespace Gfx6 -} // namespace Pal - -#endif - diff --git a/tools/gfx6_chip/si_ci_vi_merged_registers.h b/tools/gfx6_chip/si_ci_vi_merged_registers.h deleted file mode 100644 index 1eb1e049..00000000 --- a/tools/gfx6_chip/si_ci_vi_merged_registers.h +++ /dev/null @@ -1,141778 +0,0 @@ -/* - *********************************************************************************************************************** - * - * Copyright (c) 2014-2021 Advanced Micro Devices, Inc. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - **********************************************************************************************************************/ - -#if !defined (__SI__CI__VI_MERGED_REG_HEADER) -#define __SI__CI__VI_MERGED_REG_HEADER - -// Make sure the necessary endian defines are there. -#if defined(LITTLEENDIAN_CPU) -#else -#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" -#endif - -namespace Pal -{ -namespace Gfx6 -{ -inline namespace Chip -{ - - union ABM_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int ABM_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ABM_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int ABM_TEST_DEBUG_INDEX : 8; - unsigned int ABM_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ACP_CONFIG__CI { - struct { - unsigned int : 8; - unsigned int ACP_RDREQ_URG : 4; - unsigned int : 4; - unsigned int ACP_REQ_TRAN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ADAPTER_ID { - struct { - unsigned int SUBSYSTEM_VENDOR_ID : 16; - unsigned int SUBSYSTEM_ID : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ADAPTER_ID_W { - struct { - unsigned int SUBSYSTEM_VENDOR_ID : 16; - unsigned int SUBSYSTEM_ID : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_60958_0__SI__VI { - struct { - unsigned int AFMT_60958_CS_A : 1; - unsigned int AFMT_60958_CS_B : 1; - unsigned int AFMT_60958_CS_C : 1; - unsigned int AFMT_60958_CS_D : 3; - unsigned int AFMT_60958_CS_MODE : 2; - unsigned int AFMT_60958_CS_CATEGORY_CODE : 8; - unsigned int AFMT_60958_CS_SOURCE_NUMBER : 4; - unsigned int AFMT_60958_CS_CHANNEL_NUMBER_L : 4; - unsigned int AFMT_60958_CS_SAMPLING_FREQUENCY : 4; - unsigned int AFMT_60958_CS_CLOCK_ACCURACY : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_60958_1__SI__VI { - struct { - unsigned int AFMT_60958_CS_WORD_LENGTH : 4; - unsigned int AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY : 4; - unsigned int : 8; - unsigned int AFMT_60958_VALID_L : 1; - unsigned int : 1; - unsigned int AFMT_60958_VALID_R : 1; - unsigned int : 1; - unsigned int AFMT_60958_CS_CHANNEL_NUMBER_R : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_60958_2__SI__VI { - struct { - unsigned int AFMT_60958_CS_CHANNEL_NUMBER_2 : 4; - unsigned int AFMT_60958_CS_CHANNEL_NUMBER_3 : 4; - unsigned int AFMT_60958_CS_CHANNEL_NUMBER_4 : 4; - unsigned int AFMT_60958_CS_CHANNEL_NUMBER_5 : 4; - unsigned int AFMT_60958_CS_CHANNEL_NUMBER_6 : 4; - unsigned int AFMT_60958_CS_CHANNEL_NUMBER_7 : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AUDIO_CRC_CONTROL__SI__VI { - struct { - unsigned int AFMT_AUDIO_CRC_EN : 1; - unsigned int : 3; - unsigned int AFMT_AUDIO_CRC_CONT : 1; - unsigned int : 3; - unsigned int AFMT_AUDIO_CRC_SOURCE : 1; - unsigned int : 3; - unsigned int AFMT_AUDIO_CRC_CH_SEL : 4; - unsigned int AFMT_AUDIO_CRC_COUNT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AUDIO_CRC_RESULT__SI__VI { - struct { - unsigned int AFMT_AUDIO_CRC_DONE : 1; - unsigned int : 7; - unsigned int AFMT_AUDIO_CRC : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AUDIO_INFO0__SI__VI { - struct { - unsigned int AFMT_AUDIO_INFO_CHECKSUM : 8; - unsigned int AFMT_AUDIO_INFO_CC : 3; - unsigned int AFMT_AUDIO_INFO_CT : 4; - unsigned int : 1; - unsigned int AFMT_AUDIO_INFO_CHECKSUM_OFFSET : 8; - unsigned int AFMT_AUDIO_INFO_CXT : 5; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AUDIO_INFO1__SI__VI { - struct { - unsigned int AFMT_AUDIO_INFO_CA : 8; - unsigned int : 3; - unsigned int AFMT_AUDIO_INFO_LSV : 4; - unsigned int AFMT_AUDIO_INFO_DM_INH : 1; - unsigned int AFMT_AUDIO_INFO_LFEPBL : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AUDIO_PACKET_CONTROL2__SI { - struct { - unsigned int AFMT_AUDIO_LAYOUT_OVRD : 1; - unsigned int AFMT_AUDIO_LAYOUT_SELECT : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 3; - unsigned int AFMT_AUDIO_CHANNEL_ENABLE : 8; - unsigned int AFMT_DP_AUDIO_STREAM_ID : 8; - unsigned int AFMT_HBR_ENABLE_OVRD : 1; - unsigned int : 3; - unsigned int AFMT_60958_OSF_OVRD : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AUDIO_PACKET_CONTROL2__VI { - struct { - unsigned int AFMT_AUDIO_LAYOUT_OVRD : 1; - unsigned int AFMT_AUDIO_LAYOUT_SELECT : 1; - unsigned int : 6; - unsigned int AFMT_AUDIO_CHANNEL_ENABLE : 8; - unsigned int AFMT_DP_AUDIO_STREAM_ID : 8; - unsigned int AFMT_HBR_ENABLE_OVRD : 1; - unsigned int : 3; - unsigned int AFMT_60958_OSF_OVRD : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AUDIO_PACKET_CONTROL__SI { - struct { - unsigned int AFMT_AUDIO_SAMPLE_SEND : 1; - unsigned int : 10; - unsigned int AFMT_RESET_FIFO_WHEN_AUDIO_DIS : 1; - unsigned int AFMT_AUDIO_TEST_EN : 1; - unsigned int : 1; - unsigned int AFMT_AUDIO_TEST_MODE : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int AFMT_AUDIO_FIFO_OVERFLOW_ACK : 1; - unsigned int AFMT_AUDIO_CHANNEL_SWAP : 1; - unsigned int : 1; - unsigned int AFMT_60958_CS_UPDATE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int AFMT_AZ_AUDIO_ENABLE_CHG_ACK : 1; - unsigned int AFMT_BLANK_TEST_DATA_ON_ENC_ENB : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AUDIO_PACKET_CONTROL__VI { - struct { - unsigned int AFMT_AUDIO_SAMPLE_SEND : 1; - unsigned int : 10; - unsigned int AFMT_RESET_FIFO_WHEN_AUDIO_DIS : 1; - unsigned int AFMT_AUDIO_TEST_EN : 1; - unsigned int : 1; - unsigned int AFMT_AUDIO_TEST_MODE : 1; - unsigned int : 8; - unsigned int AFMT_AUDIO_FIFO_OVERFLOW_ACK : 1; - unsigned int AFMT_AUDIO_CHANNEL_SWAP : 1; - unsigned int : 1; - unsigned int AFMT_60958_CS_UPDATE : 1; - unsigned int : 3; - unsigned int AFMT_AZ_AUDIO_ENABLE_CHG_ACK : 1; - unsigned int AFMT_BLANK_TEST_DATA_ON_ENC_ENB : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AVI_INFO0__SI__VI { - struct { - unsigned int AFMT_AVI_INFO_CHECKSUM : 8; - unsigned int AFMT_AVI_INFO_S : 2; - unsigned int AFMT_AVI_INFO_B : 2; - unsigned int AFMT_AVI_INFO_A : 1; - unsigned int AFMT_AVI_INFO_Y : 2; - unsigned int AFMT_AVI_INFO_PB1_RSVD : 1; - unsigned int AFMT_AVI_INFO_R : 4; - unsigned int AFMT_AVI_INFO_M : 2; - unsigned int AFMT_AVI_INFO_C : 2; - unsigned int AFMT_AVI_INFO_SC : 2; - unsigned int AFMT_AVI_INFO_Q : 2; - unsigned int AFMT_AVI_INFO_EC : 3; - unsigned int AFMT_AVI_INFO_ITC : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AVI_INFO1__SI__VI { - struct { - unsigned int AFMT_AVI_INFO_VIC : 7; - unsigned int AFMT_AVI_INFO_PB4_RSVD : 1; - unsigned int AFMT_AVI_INFO_PR : 4; - unsigned int AFMT_AVI_INFO_CN : 2; - unsigned int AFMT_AVI_INFO_YQ : 2; - unsigned int AFMT_AVI_INFO_TOP : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AVI_INFO2__SI__VI { - struct { - unsigned int AFMT_AVI_INFO_BOTTOM : 16; - unsigned int AFMT_AVI_INFO_LEFT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AVI_INFO3__SI__VI { - struct { - unsigned int AFMT_AVI_INFO_RIGHT : 16; - unsigned int : 8; - unsigned int AFMT_AVI_INFO_VERSION : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_INFOFRAME_CONTROL0__SI__VI { - struct { - unsigned int : 6; - unsigned int AFMT_AUDIO_INFO_SOURCE : 1; - unsigned int AFMT_AUDIO_INFO_UPDATE : 1; - unsigned int : 2; - unsigned int AFMT_MPEG_INFO_UPDATE : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_ISRC1_0__SI__VI { - struct { - unsigned int AFMT_ISRC_STATUS : 3; - unsigned int : 3; - unsigned int AFMT_ISRC_CONTINUE : 1; - unsigned int AFMT_ISRC_VALID : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_ISRC1_1__SI__VI { - struct { - unsigned int AFMT_UPC_EAN_ISRC0 : 8; - unsigned int AFMT_UPC_EAN_ISRC1 : 8; - unsigned int AFMT_UPC_EAN_ISRC2 : 8; - unsigned int AFMT_UPC_EAN_ISRC3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_ISRC1_2__SI__VI { - struct { - unsigned int AFMT_UPC_EAN_ISRC4 : 8; - unsigned int AFMT_UPC_EAN_ISRC5 : 8; - unsigned int AFMT_UPC_EAN_ISRC6 : 8; - unsigned int AFMT_UPC_EAN_ISRC7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_ISRC1_3__SI__VI { - struct { - unsigned int AFMT_UPC_EAN_ISRC8 : 8; - unsigned int AFMT_UPC_EAN_ISRC9 : 8; - unsigned int AFMT_UPC_EAN_ISRC10 : 8; - unsigned int AFMT_UPC_EAN_ISRC11 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_ISRC1_4__SI__VI { - struct { - unsigned int AFMT_UPC_EAN_ISRC12 : 8; - unsigned int AFMT_UPC_EAN_ISRC13 : 8; - unsigned int AFMT_UPC_EAN_ISRC14 : 8; - unsigned int AFMT_UPC_EAN_ISRC15 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_ISRC2_0__SI__VI { - struct { - unsigned int AFMT_UPC_EAN_ISRC16 : 8; - unsigned int AFMT_UPC_EAN_ISRC17 : 8; - unsigned int AFMT_UPC_EAN_ISRC18 : 8; - unsigned int AFMT_UPC_EAN_ISRC19 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_ISRC2_1__SI__VI { - struct { - unsigned int AFMT_UPC_EAN_ISRC20 : 8; - unsigned int AFMT_UPC_EAN_ISRC21 : 8; - unsigned int AFMT_UPC_EAN_ISRC22 : 8; - unsigned int AFMT_UPC_EAN_ISRC23 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_ISRC2_2__SI__VI { - struct { - unsigned int AFMT_UPC_EAN_ISRC24 : 8; - unsigned int AFMT_UPC_EAN_ISRC25 : 8; - unsigned int AFMT_UPC_EAN_ISRC26 : 8; - unsigned int AFMT_UPC_EAN_ISRC27 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_ISRC2_3__SI__VI { - struct { - unsigned int AFMT_UPC_EAN_ISRC28 : 8; - unsigned int AFMT_UPC_EAN_ISRC29 : 8; - unsigned int AFMT_UPC_EAN_ISRC30 : 8; - unsigned int AFMT_UPC_EAN_ISRC31 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_MPEG_INFO0__SI__VI { - struct { - unsigned int AFMT_MPEG_INFO_CHECKSUM : 8; - unsigned int AFMT_MPEG_INFO_MB0 : 8; - unsigned int AFMT_MPEG_INFO_MB1 : 8; - unsigned int AFMT_MPEG_INFO_MB2 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_MPEG_INFO1__SI__VI { - struct { - unsigned int AFMT_MPEG_INFO_MB3 : 8; - unsigned int AFMT_MPEG_INFO_MF : 2; - unsigned int : 2; - unsigned int AFMT_MPEG_INFO_FR : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_RAMP_CONTROL0__SI__VI { - struct { - unsigned int AFMT_RAMP_MAX_COUNT : 24; - unsigned int : 7; - unsigned int AFMT_RAMP_DATA_SIGN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_RAMP_CONTROL1__SI__VI { - struct { - unsigned int AFMT_RAMP_MIN_COUNT : 24; - unsigned int AFMT_AUDIO_TEST_CH_DISABLE : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_RAMP_CONTROL2__SI__VI { - struct { - unsigned int AFMT_RAMP_INC_COUNT : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_RAMP_CONTROL3__SI__VI { - struct { - unsigned int AFMT_RAMP_DEC_COUNT : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_STATUS__SI { - struct { - unsigned int : 4; - unsigned int AFMT_AUDIO_ENABLE : 1; - unsigned int : 3; - unsigned int AFMT_AZ_HBR_ENABLE : 1; - unsigned int : 15; - unsigned int AFMT_AUDIO_FIFO_OVERFLOW : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int AFMT_AZ_AUDIO_ENABLE_CHG : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_STATUS__VI { - struct { - unsigned int : 4; - unsigned int AFMT_AUDIO_ENABLE : 1; - unsigned int : 3; - unsigned int AFMT_AZ_HBR_ENABLE : 1; - unsigned int : 15; - unsigned int AFMT_AUDIO_FIFO_OVERFLOW : 1; - unsigned int : 5; - unsigned int AFMT_AZ_AUDIO_ENABLE_CHG : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_VBI_PACKET_CONTROL__SI__VI { - struct { - unsigned int : 2; - unsigned int AFMT_GENERIC0_UPDATE : 1; - unsigned int AFMT_GENERIC2_UPDATE__VI : 1; - unsigned int : 9; - unsigned int : 1; - unsigned int : 16; - unsigned int AFMT_GENERIC_INDEX__VI : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_CNTL__CI__VI { - struct { - unsigned int DISABLE_ATC : 1; - unsigned int DISABLE_PRI : 1; - unsigned int DISABLE_PASID : 1; - unsigned int : 5; - unsigned int CREDITS_ATS_RPB : 6; - unsigned int : 2; - unsigned int DEBUG_ECO : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_DEBUG__CI__VI { - struct { - unsigned int INVALIDATE_ALL : 1; - unsigned int IDENT_RETURN : 1; - unsigned int ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS : 1; - unsigned int : 2; - unsigned int PAGE_REQUESTS_USE_RELAXED_ORDERING : 1; - unsigned int PRIV_BIT : 1; - unsigned int EXE_BIT : 1; - unsigned int PAGE_REQUEST_PERMS : 1; - unsigned int UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE : 1; - unsigned int NUM_REQUESTS_AT_ERR : 4; - unsigned int DISALLOW_ERR_TO_DONE : 1; - unsigned int IGNORE_FED : 1; - unsigned int INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED : 1; - unsigned int DEBUG_BUS_SELECT : 1; - unsigned int DISABLE_INVALIDATE_PER_DOMAIN__VI : 1; - unsigned int DISABLE_VMID0_PASID_MAPPING__VI : 1; - unsigned int DISABLE_INVALIDATION_ON_WORLD_SWITCH__VI : 1; - unsigned int ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__VI : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_DEFAULT_PAGE_CNTL__CI__VI { - struct { - unsigned int SEND_DEFAULT_PAGE : 1; - unsigned int : 1; - unsigned int DEFAULT_PAGE_HIGH : 4; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_DEFAULT_PAGE_LOW__CI { - struct { - unsigned int DEFAULT_PAGE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_DEFAULT_PAGE_LOW__VI { - struct { - unsigned int DEFAULT_PAGE : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_FAULT_CNTL__CI__VI { - struct { - unsigned int FAULT_REGISTER_LOG : 9; - unsigned int : 1; - unsigned int FAULT_INTERRUPT_TABLE : 9; - unsigned int : 1; - unsigned int FAULT_CRASH_TABLE : 9; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_FAULT_DEBUG__CI__VI { - struct { - unsigned int CREDITS_ATS_IH : 5; - unsigned int : 3; - unsigned int ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES : 1; - unsigned int : 7; - unsigned int CLEAR_FAULT_STATUS_ADDR : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_FAULT_STATUS_ADDR__CI__VI { - struct { - unsigned int PAGE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_FAULT_STATUS_INFO__CI__VI { - struct { - unsigned int FAULT_TYPE : 9; - unsigned int : 1; - unsigned int VMID : 5; - unsigned int EXTRA_INFO : 1; - unsigned int EXTRA_INFO2 : 1; - unsigned int INVALIDATION : 1; - unsigned int PAGE_REQUEST : 1; - unsigned int STATUS : 5; - unsigned int PAGE_ADDR_HIGH : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_STATUS__CI__VI { - struct { - unsigned int BUSY : 1; - unsigned int CRASHED : 1; - unsigned int DEADLOCK_DETECTION : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L1RD_DEBUG_TLB__CI__VI { - struct { - unsigned int DISABLE_FRAGMENTS : 1; - unsigned int DISABLE_INVALIDATE_BY_ADDRESS_RANGE : 1; - unsigned int : 2; - unsigned int EFFECTIVE_CAM_SIZE : 4; - unsigned int EFFECTIVE_WORK_QUEUE_SIZE : 3; - unsigned int : 1; - unsigned int CREDITS_L1_L2 : 6; - unsigned int : 2; - unsigned int CREDITS_L1_RPB : 8; - unsigned int DEBUG_ECO : 2; - unsigned int INVALIDATE_ALL : 1; - unsigned int DISABLE_CACHING_FAULT_RETURNS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L1RD_STATUS__CI__VI { - struct { - unsigned int BUSY : 1; - unsigned int DEADLOCK_DETECTION : 1; - unsigned int : 6; - unsigned int BAD_NEED_ATS : 1; - unsigned int : 3; - unsigned int CAM_PARITY_ERRORS__VI : 5; - unsigned int CAM_INDEX__VI : 5; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L1WR_DEBUG_TLB__CI__VI { - struct { - unsigned int DISABLE_FRAGMENTS : 1; - unsigned int DISABLE_INVALIDATE_BY_ADDRESS_RANGE : 1; - unsigned int : 2; - unsigned int EFFECTIVE_CAM_SIZE : 4; - unsigned int EFFECTIVE_WORK_QUEUE_SIZE : 3; - unsigned int : 1; - unsigned int CREDITS_L1_L2 : 6; - unsigned int : 2; - unsigned int CREDITS_L1_RPB : 8; - unsigned int DEBUG_ECO : 2; - unsigned int INVALIDATE_ALL : 1; - unsigned int DISABLE_CACHING_FAULT_RETURNS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L1WR_STATUS__CI__VI { - struct { - unsigned int BUSY : 1; - unsigned int DEADLOCK_DETECTION : 1; - unsigned int : 6; - unsigned int BAD_NEED_ATS : 1; - unsigned int : 3; - unsigned int CAM_PARITY_ERRORS__VI : 5; - unsigned int CAM_INDEX__VI : 5; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L1_ADDRESS_OFFSET__CI__VI { - struct { - unsigned int LOGICAL_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L1_CNTL__CI__VI { - struct { - unsigned int DONT_NEED_ATS_BEHAVIOR : 2; - unsigned int NEED_ATS_BEHAVIOR : 1; - unsigned int : 1; - unsigned int NEED_ATS_SNOOP_DEFAULT : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L2_CNTL2__CI__VI { - struct { - unsigned int BANK_SELECT : 6; - unsigned int L2_CACHE_UPDATE_MODE : 2; - unsigned int ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE : 1; - unsigned int L2_CACHE_SWAP_TAG_INDEX_LSBS : 3; - unsigned int L2_CACHE_VMID_MODE : 3; - unsigned int L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE : 6; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L2_CNTL__CI__VI { - struct { - unsigned int NUMBER_OF_TRANSLATION_READ_REQUESTS : 2; - unsigned int : 2; - unsigned int NUMBER_OF_TRANSLATION_WRITE_REQUESTS : 2; - unsigned int : 2; - unsigned int NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD : 1; - unsigned int NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L2_DEBUG2__CI { - struct { - unsigned int EFFECTIVE_CACHE_SIZE : 5; - unsigned int EFFECTIVE_WORK_QUEUE_SIZE : 3; - unsigned int FORCE_CACHE_MISS : 1; - unsigned int INVALIDATE_ALL : 1; - unsigned int DISABLE_INVALIDATE_PER_DOMAIN : 1; - unsigned int DISABLE_CACHING_SPECULATIVE_READ_RETURNS : 1; - unsigned int DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS : 1; - unsigned int : 1; - unsigned int DISABLE_CACHING_FAULT_RETURNS : 1; - unsigned int DEBUG_BUS_SELECT : 2; - unsigned int DEBUG_ECO : 2; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L2_DEBUG2__VI { - struct { - unsigned int EFFECTIVE_CACHE_SIZE : 5; - unsigned int EFFECTIVE_WORK_QUEUE_SIZE : 3; - unsigned int FORCE_CACHE_MISS : 1; - unsigned int INVALIDATE_ALL : 1; - unsigned int DISABLE_2M_CACHE : 1; - unsigned int DISABLE_CACHING_SPECULATIVE_RETURNS : 1; - unsigned int : 2; - unsigned int DISABLE_CACHING_FAULT_RETURNS : 1; - unsigned int DEBUG_BUS_SELECT : 2; - unsigned int DEBUG_ECO : 2; - unsigned int EFFECTIVE_2M_CACHE_SIZE : 4; - unsigned int CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD : 8; - unsigned int CLEAR_PARITY_ERROR_INFO : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L2_DEBUG__CI__VI { - struct { - unsigned int CREDITS_L2_ATS : 6; - unsigned int : 1; - unsigned int L2_MEM_SELECT__VI : 1; - unsigned int CACHE_INDEX__VI : 12; - unsigned int : 4; - unsigned int CACHE_SELECT__VI : 1; - unsigned int CACHE_BANK_SELECT__VI : 1; - unsigned int : 1; - unsigned int CACHE_WAY_SELECT__VI : 1; - unsigned int : 1; - unsigned int CACHE_READ__VI : 1; - unsigned int CACHE_INJECT_SOFT_PARITY_ERROR__VI : 1; - unsigned int CACHE_INJECT_HARD_PARITY_ERROR__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_MISC_CG__CI__VI { - struct { - unsigned int : 6; - unsigned int OFFDLY : 6; - unsigned int : 6; - unsigned int ENABLE : 1; - unsigned int MEM_LS_ENABLE : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_PERFCOUNTER0_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_PERFCOUNTER1_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_PERFCOUNTER2_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_PERFCOUNTER3_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_PERFCOUNTER_HI__CI__VI { - struct { - unsigned int COUNTER_HI : 16; - unsigned int COMPARE_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_PERFCOUNTER_LO__CI__VI { - struct { - unsigned int COUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_PERFCOUNTER_RSLT_CNTL__CI__VI { - struct { - unsigned int PERF_COUNTER_SELECT : 4; - unsigned int : 4; - unsigned int START_TRIGGER : 8; - unsigned int STOP_TRIGGER : 8; - unsigned int ENABLE_ANY : 1; - unsigned int CLEAR_ALL : 1; - unsigned int STOP_ALL_ON_SATURATE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID0_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID10_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID11_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID12_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID13_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID14_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID15_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID1_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID2_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID3_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID4_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID5_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID6_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID7_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID8_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID9_PASID_MAPPING__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 14; - unsigned int NO_INVALIDATION__VI : 1; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VMID_PASID_MAPPING_UPDATE_STATUS__CI__VI { - struct { - unsigned int VMID0_REMAPPING_FINISHED : 1; - unsigned int VMID1_REMAPPING_FINISHED : 1; - unsigned int VMID2_REMAPPING_FINISHED : 1; - unsigned int VMID3_REMAPPING_FINISHED : 1; - unsigned int VMID4_REMAPPING_FINISHED : 1; - unsigned int VMID5_REMAPPING_FINISHED : 1; - unsigned int VMID6_REMAPPING_FINISHED : 1; - unsigned int VMID7_REMAPPING_FINISHED : 1; - unsigned int VMID8_REMAPPING_FINISHED : 1; - unsigned int VMID9_REMAPPING_FINISHED : 1; - unsigned int VMID10_REMAPPING_FINISHED : 1; - unsigned int VMID11_REMAPPING_FINISHED : 1; - unsigned int VMID12_REMAPPING_FINISHED : 1; - unsigned int VMID13_REMAPPING_FINISHED : 1; - unsigned int VMID14_REMAPPING_FINISHED : 1; - unsigned int VMID15_REMAPPING_FINISHED : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VM_APERTURE0_CNTL2__CI__VI { - struct { - unsigned int VMIDS_USING_RANGE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VM_APERTURE0_CNTL__CI__VI { - struct { - unsigned int ATS_ACCESS_MODE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VM_APERTURE0_HIGH_ADDR__CI__VI { - struct { - unsigned int VIRTUAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VM_APERTURE0_LOW_ADDR__CI__VI { - struct { - unsigned int VIRTUAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VM_APERTURE1_CNTL2__CI__VI { - struct { - unsigned int VMIDS_USING_RANGE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VM_APERTURE1_CNTL__CI__VI { - struct { - unsigned int ATS_ACCESS_MODE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VM_APERTURE1_HIGH_ADDR__CI__VI { - struct { - unsigned int VIRTUAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_VM_APERTURE1_LOW_ADDR__CI__VI { - struct { - unsigned int VIRTUAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR00__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR01__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR02__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR03__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR04__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR05__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR06__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR07__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR08__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR09__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR0A__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR0B__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR0C__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR0D__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR0E__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR0F__SI__VI { - struct { - unsigned int ATTR_PAL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR10__SI__VI { - struct { - unsigned int ATTR_GRPH_MODE : 1; - unsigned int ATTR_MONO_EN : 1; - unsigned int ATTR_LGRPH_EN : 1; - unsigned int ATTR_BLINK_EN : 1; - unsigned int : 1; - unsigned int ATTR_PANTOPONLY : 1; - unsigned int ATTR_PCLKBY2 : 1; - unsigned int ATTR_CSEL_EN : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR11__SI__VI { - struct { - unsigned int ATTR_OVSC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR12__SI__VI { - struct { - unsigned int ATTR_MAP_EN : 4; - unsigned int ATTR_VSMUX : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR13__SI__VI { - struct { - unsigned int ATTR_PPAN : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTR14__SI__VI { - struct { - unsigned int ATTR_CSEL1 : 2; - unsigned int ATTR_CSEL2 : 2; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTRDR__SI__VI { - struct { - unsigned int ATTR_DATA : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTRDW__SI__VI { - struct { - unsigned int ATTR_DATA : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATTRX__SI__VI { - struct { - unsigned int ATTR_IDX : 5; - unsigned int ATTR_PAL_RW_ENB : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR0__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR10__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR11__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR12__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR13__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR1__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR2__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR3__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR4__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR5__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR6__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR7__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR8__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUDIO_DESCRIPTOR9__SI__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUXN_IMPCAL__SI { - struct { - unsigned int AUXN_IMPCAL_ENABLE : 1; - unsigned int : 7; - unsigned int AUXN_IMPCAL_CALOUT : 1; - unsigned int AUXN_CALOUT_ERROR : 1; - unsigned int AUXN_CALOUT_ERROR_AK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int AUXN_IMPCAL_VALUE : 4; - unsigned int AUXN_IMPCAL_STEP_DELAY : 4; - unsigned int AUXN_IMPCAL_OVERRIDE : 4; - unsigned int AUXN_IMPCAL_OVERRIDE_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUXN_IMPCAL__VI { - struct { - unsigned int AUXN_IMPCAL_ENABLE : 1; - unsigned int : 7; - unsigned int AUXN_IMPCAL_CALOUT : 1; - unsigned int AUXN_CALOUT_ERROR : 1; - unsigned int AUXN_CALOUT_ERROR_AK : 1; - unsigned int : 5; - unsigned int AUXN_IMPCAL_VALUE : 4; - unsigned int AUXN_IMPCAL_STEP_DELAY : 4; - unsigned int AUXN_IMPCAL_OVERRIDE : 4; - unsigned int AUXN_IMPCAL_OVERRIDE_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUXP_IMPCAL__SI { - struct { - unsigned int AUXP_IMPCAL_ENABLE : 1; - unsigned int : 7; - unsigned int AUXP_IMPCAL_CALOUT : 1; - unsigned int AUXP_CALOUT_ERROR : 1; - unsigned int AUXP_CALOUT_ERROR_AK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int AUXP_IMPCAL_VALUE : 4; - unsigned int AUXP_IMPCAL_STEP_DELAY : 4; - unsigned int AUXP_IMPCAL_OVERRIDE : 4; - unsigned int AUXP_IMPCAL_OVERRIDE_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUXP_IMPCAL__VI { - struct { - unsigned int AUXP_IMPCAL_ENABLE : 1; - unsigned int : 7; - unsigned int AUXP_IMPCAL_CALOUT : 1; - unsigned int AUXP_CALOUT_ERROR : 1; - unsigned int AUXP_CALOUT_ERROR_AK : 1; - unsigned int : 5; - unsigned int AUXP_IMPCAL_VALUE : 4; - unsigned int AUXP_IMPCAL_STEP_DELAY : 4; - unsigned int AUXP_IMPCAL_OVERRIDE : 4; - unsigned int AUXP_IMPCAL_OVERRIDE_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_ARB_CONTROL__SI__VI { - struct { - unsigned int AUX_ARB_PRIORITY : 2; - unsigned int AUX_REG_RW_CNTL_STATUS : 2; - unsigned int : 4; - unsigned int AUX_NO_QUEUED_SW_GO : 1; - unsigned int : 1; - unsigned int AUX_NO_QUEUED_LS_GO : 1; - unsigned int : 5; - unsigned int AUX_SW_USE_AUX_REG_REQ : 1; - unsigned int AUX_SW_DONE_USING_AUX_REG : 1; - unsigned int : 6; - unsigned int AUX_DMCU_USE_AUX_REG_REQ : 1; - unsigned int AUX_DMCU_DONE_USING_AUX_REG : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_CONTROL__SI__VI { - struct { - unsigned int AUX_EN : 1; - unsigned int : 7; - unsigned int AUX_LS_READ_EN : 1; - unsigned int : 3; - unsigned int AUX_LS_UPDATE_DISABLE : 1; - unsigned int : 3; - unsigned int AUX_IGNORE_HPD_DISCON : 1; - unsigned int : 1; - unsigned int AUX_MODE_DET_EN : 1; - unsigned int : 1; - unsigned int AUX_HPD_SEL : 3; - unsigned int : 1; - unsigned int AUX_IMPCAL_REQ_EN : 1; - unsigned int : 3; - unsigned int AUX_TEST_MODE : 1; - unsigned int AUX_DEGLITCH_EN : 1; - unsigned int SPARE_0 : 1; - unsigned int SPARE_1 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_DPHY_RX_CONTROL0__SI__VI { - struct { - unsigned int : 4; - unsigned int AUX_RX_START_WINDOW : 3; - unsigned int : 1; - unsigned int AUX_RX_RECEIVE_WINDOW : 3; - unsigned int : 1; - unsigned int AUX_RX_HALF_SYM_DETECT_LEN : 2; - unsigned int : 2; - unsigned int AUX_RX_TRANSITION_FILTER_EN : 1; - unsigned int AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT : 1; - unsigned int AUX_RX_ALLOW_BELOW_THRESHOLD_START : 1; - unsigned int AUX_RX_ALLOW_BELOW_THRESHOLD_STOP : 1; - unsigned int AUX_RX_PHASE_DETECT_LEN : 2; - unsigned int : 2; - unsigned int AUX_RX_TIMEOUT_LEN : 3; - unsigned int : 1; - unsigned int AUX_RX_DETECTION_THRESHOLD : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_DPHY_RX_CONTROL1__SI__VI { - struct { - unsigned int AUX_RX_PRECHARGE_SKIP : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_DPHY_RX_STATUS__SI__VI { - struct { - unsigned int AUX_RX_STATE : 3; - unsigned int : 5; - unsigned int AUX_RX_SYNC_VALID_COUNT : 5; - unsigned int : 3; - unsigned int AUX_RX_HALF_SYM_PERIOD_FRACT : 5; - unsigned int AUX_RX_HALF_SYM_PERIOD : 9; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_DPHY_TX_CONTROL__SI__VI { - struct { - unsigned int AUX_TX_PRECHARGE_LEN : 3; - unsigned int : 5; - unsigned int AUX_TX_PRECHARGE_SYMBOLS : 6; - unsigned int : 2; - unsigned int AUX_MODE_DET_CHECK_DELAY__VI : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_DPHY_TX_REF_CONTROL__SI__VI { - struct { - unsigned int AUX_TX_REF_SEL : 1; - unsigned int : 3; - unsigned int AUX_TX_RATE : 2; - unsigned int : 10; - unsigned int AUX_TX_REF_DIV : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_DPHY_TX_STATUS__SI__VI { - struct { - unsigned int AUX_TX_ACTIVE : 1; - unsigned int : 3; - unsigned int AUX_TX_STATE : 3; - unsigned int : 9; - unsigned int AUX_TX_HALF_SYM_PERIOD : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_INTERRUPT_CONTROL__SI__VI { - struct { - unsigned int AUX_SW_DONE_INT : 1; - unsigned int AUX_SW_DONE_ACK : 1; - unsigned int AUX_SW_DONE_MASK : 1; - unsigned int : 1; - unsigned int AUX_LS_DONE_INT : 1; - unsigned int AUX_LS_DONE_ACK : 1; - unsigned int AUX_LS_DONE_MASK : 1; - unsigned int : 1; - unsigned int AUX_GTC_SYNC_LOCK_DONE_INT__VI : 1; - unsigned int AUX_GTC_SYNC_LOCK_DONE_ACK__VI : 1; - unsigned int AUX_GTC_SYNC_LOCK_DONE_INT_MASK__VI : 1; - unsigned int : 1; - unsigned int AUX_GTC_SYNC_ERROR_INT__VI : 1; - unsigned int AUX_GTC_SYNC_ERROR_ACK__VI : 1; - unsigned int AUX_GTC_SYNC_ERROR_INT_MASK__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_LS_DATA__SI__VI { - struct { - unsigned int : 8; - unsigned int AUX_LS_DATA : 8; - unsigned int AUX_LS_INDEX : 5; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_LS_STATUS__SI__VI { - struct { - unsigned int AUX_LS_DONE : 1; - unsigned int AUX_LS_REQ : 1; - unsigned int : 2; - unsigned int AUX_LS_RX_TIMEOUT_STATE : 3; - unsigned int AUX_LS_RX_TIMEOUT : 1; - unsigned int AUX_LS_RX_OVERFLOW : 1; - unsigned int AUX_LS_HPD_DISCON : 1; - unsigned int AUX_LS_RX_PARTIAL_BYTE : 1; - unsigned int AUX_LS_NON_AUX_MODE : 1; - unsigned int AUX_LS_RX_MIN_COUNT_VIOL : 1; - unsigned int : 1; - unsigned int AUX_LS_RX_INVALID_STOP : 1; - unsigned int : 2; - unsigned int AUX_LS_RX_SYNC_INVALID_L : 1; - unsigned int AUX_LS_RX_SYNC_INVALID_H : 1; - unsigned int AUX_LS_RX_INVALID_START : 1; - unsigned int AUX_LS_RX_RECV_NO_DET : 1; - unsigned int : 1; - unsigned int AUX_LS_RX_RECV_INVALID_H : 1; - unsigned int AUX_LS_RX_RECV_INVALID_L : 1; - unsigned int AUX_LS_REPLY_BYTE_COUNT : 5; - unsigned int AUX_LS_CP_IRQ : 1; - unsigned int AUX_LS_UPDATED : 1; - unsigned int AUX_LS_UPDATED_ACK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_SW_CONTROL__SI__VI { - struct { - unsigned int AUX_SW_GO : 1; - unsigned int : 1; - unsigned int AUX_LS_READ_TRIG : 1; - unsigned int : 1; - unsigned int AUX_SW_START_DELAY : 4; - unsigned int : 8; - unsigned int AUX_SW_WR_BYTES : 5; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_SW_DATA__SI__VI { - struct { - unsigned int AUX_SW_DATA_RW : 1; - unsigned int : 7; - unsigned int AUX_SW_DATA : 8; - unsigned int AUX_SW_INDEX : 5; - unsigned int : 10; - unsigned int AUX_SW_AUTOINCREMENT_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_SW_STATUS__SI__VI { - struct { - unsigned int AUX_SW_DONE : 1; - unsigned int AUX_SW_REQ : 1; - unsigned int : 2; - unsigned int AUX_SW_RX_TIMEOUT_STATE : 3; - unsigned int AUX_SW_RX_TIMEOUT : 1; - unsigned int AUX_SW_RX_OVERFLOW : 1; - unsigned int AUX_SW_HPD_DISCON : 1; - unsigned int AUX_SW_RX_PARTIAL_BYTE : 1; - unsigned int AUX_SW_NON_AUX_MODE : 1; - unsigned int AUX_SW_RX_MIN_COUNT_VIOL : 1; - unsigned int : 1; - unsigned int AUX_SW_RX_INVALID_STOP : 1; - unsigned int : 2; - unsigned int AUX_SW_RX_SYNC_INVALID_L : 1; - unsigned int AUX_SW_RX_SYNC_INVALID_H : 1; - unsigned int AUX_SW_RX_INVALID_START : 1; - unsigned int AUX_SW_RX_RECV_NO_DET : 1; - unsigned int : 1; - unsigned int AUX_SW_RX_RECV_INVALID_H : 1; - unsigned int AUX_SW_RX_RECV_INVALID_L : 1; - unsigned int AUX_SW_REPLY_BYTE_COUNT : 5; - unsigned int : 1; - unsigned int AUX_ARB_STATUS : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__SI__VI { - struct { - unsigned int APPLICATION_POSITION_IN_CYCLIC_BUFFER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_AUDIO_DTO_CONTROL__SI { - struct { - unsigned int : 1; - unsigned int : 3; - unsigned int : 3; - unsigned int : 1; - unsigned int AZALIA_AUDIO_FORCE_DTO : 2; - unsigned int : 2; - unsigned int : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_AUDIO_DTO_CONTROL__VI { - struct { - unsigned int : 8; - unsigned int AZALIA_AUDIO_FORCE_DTO : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_AUDIO_DTO__SI__VI { - struct { - unsigned int AZALIA_AUDIO_DTO_PHASE : 16; - unsigned int AZALIA_AUDIO_DTO_MODULE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_BDL_DMA_CONTROL__SI { - struct { - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_BDL_DMA_CONTROL__VI { - struct { - unsigned int BDL_DMA_NON_SNOOP : 2; - unsigned int INPUT_BDL_DMA_NON_SNOOP : 2; - unsigned int BDL_DMA_ISOCHRONOUS : 2; - unsigned int INPUT_BDL_DMA_ISOCHRONOUS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CORB_DMA_CONTROL__SI__VI { - struct { - unsigned int CORB_DMA_NON_SNOOP : 1; - unsigned int : 3; - unsigned int CORB_DMA_ISOCHRONOUS : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CUMULATIVE_LATENCY_COUNT__SI__VI { - struct { - unsigned int AZALIA_CUMULATIVE_LATENCY_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CUMULATIVE_REQUEST_COUNT__SI__VI { - struct { - unsigned int AZALIA_CUMULATIVE_REQUEST_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CYCLIC_BUFFER_SYNC__SI__VI { - struct { - unsigned int CYCLIC_BUFFER_SYNC_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_DATA_DMA_CONTROL__SI__VI { - struct { - unsigned int DATA_DMA_NON_SNOOP : 2; - unsigned int INPUT_DATA_DMA_NON_SNOOP__VI : 2; - unsigned int DATA_DMA_ISOCHRONOUS : 2; - unsigned int INPUT_DATA_DMA_ISOCHRONOUS__VI : 2; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int AZALIA_IOC_GENERATION_METHOD : 1; - unsigned int AZALIA_UNDERFLOW_CONTROL : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_DEBUG__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__SI { - struct { - unsigned int : 4; - unsigned int : 4; - unsigned int : 4; - unsigned int : 4; - unsigned int : 4; - unsigned int : 4; - unsigned int : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI { - struct { - unsigned int CHANNEL_ID : 4; - unsigned int STREAM_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__SI__VI { - struct { - unsigned int POWER_STATE_SET : 4; - unsigned int POWER_STATE_ACT : 4; - unsigned int : 1; - unsigned int CLKSTOPOK__VI : 1; - unsigned int POWER_STATE_SETTINGS_RESET__VI : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__SI__VI { - struct { - unsigned int CODEC_RESET : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI__VI { - struct { - unsigned int SUBSYSTEM_ID_BYTE0 : 8; - unsigned int SUBSYSTEM_ID_BYTE1 : 8; - unsigned int SUBSYSTEM_ID_BYTE2 : 8; - unsigned int SUBSYSTEM_ID_BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI__VI { - struct { - unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI { - struct { - unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__VI { - struct { - unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES : 30; - unsigned int CLKSTOP : 1; - unsigned int EPSS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI__VI { - struct { - unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI__VI { - struct { - unsigned int AUDIO_RATE_CAPABILITIES : 12; - unsigned int : 4; - unsigned int AUDIO_BIT_CAPABILITIES : 5; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__SI { - struct { - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__VI { - struct { - unsigned int TAG : 6; - unsigned int : 1; - unsigned int ENABLE : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__SI { - struct { - unsigned int : 6; - unsigned int : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__VI { - struct { - unsigned int : 6; - unsigned int OUT_ENABLE : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__SI__VI { - struct { - unsigned int AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI__VI { - struct { - unsigned int AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__SI__VI { - struct { - unsigned int POWER_STATE_SET : 4; - unsigned int POWER_STATE_ACT : 4; - unsigned int : 1; - unsigned int CLKSTOPOK__VI : 1; - unsigned int POWER_STATE_SETTINGS_RESET__VI : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__SI__VI { - struct { - unsigned int CODEC_RESET : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SI__VI { - struct { - unsigned int SUBSYSTEM_ID_BYTE1 : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SI__VI { - struct { - unsigned int SUBSYSTEM_ID_BYTE2 : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SI__VI { - struct { - unsigned int SUBSYSTEM_ID_BYTE3 : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI__VI { - struct { - unsigned int SUBSYSTEM_ID_BYTE0 : 8; - unsigned int SUBSYSTEM_ID_BYTE1 : 8; - unsigned int SUBSYSTEM_ID_BYTE2 : 8; - unsigned int SUBSYSTEM_ID_BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI__VI { - struct { - unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI { - struct { - unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__VI { - struct { - unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES : 30; - unsigned int CLKSTOP : 1; - unsigned int EPSS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI__VI { - struct { - unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SI__VI { - struct { - unsigned int AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI__VI { - struct { - unsigned int AUDIO_RATE_CAPABILITIES : 12; - unsigned int : 4; - unsigned int AUDIO_BIT_CAPABILITIES : 5; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__SI__VI { - struct { - unsigned int AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SI__VI { - struct { - unsigned int AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI__VI { - struct { - unsigned int AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_LATENCY_COUNTER_CONTROL__SI__VI { - struct { - unsigned int AZALIA_LATENCY_COUNTER_RESET : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_RIRB_AND_DP_CONTROL__SI__VI { - struct { - unsigned int RIRB_NON_SNOOP : 1; - unsigned int : 3; - unsigned int DP_DMA_NON_SNOOP : 1; - unsigned int DP_UPDATE_FREQ_DIVIDER__VI : 4; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_UNDERFLOW_FILLER_SAMPLE__SI__VI { - struct { - unsigned int AZALIA_UNDERFLOW_FILLER_SAMPLE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_WORSTCASE_LATENCY_COUNT__SI__VI { - struct { - unsigned int AZALIA_WORSTCASE_LATENCY_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZ_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int AZ_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZ_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int AZ_TEST_DEBUG_INDEX : 8; - unsigned int AZ_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BACO_CNTL_MISC__CI__VI { - struct { - unsigned int BIF_ROM_REQ_DIS : 1; - unsigned int BIF_AZ_REQ_DIS : 1; - unsigned int BACO_LINK_RST_WIDTH_SEL : 2; - unsigned int BACO_REFCLK_SEL__VI : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BACO_CNTL__CI__VI { - struct { - unsigned int BACO_EN : 1; - unsigned int BACO_BCLK_OFF : 1; - unsigned int BACO_ISO_DIS : 1; - unsigned int BACO_POWER_OFF : 1; - unsigned int BACO_RESET_EN : 1; - unsigned int BACO_HANG_PROTECTION_EN : 1; - unsigned int BACO_MODE : 1; - unsigned int BACO_ANA_ISO_DIS : 1; - unsigned int RCU_BIF_CONFIG_DONE : 1; - unsigned int PWRGOOD_BF : 1; - unsigned int PWRGOOD_GPIO : 1; - unsigned int PWRGOOD_MEM : 1; - unsigned int PWRGOOD_DVO : 1; - unsigned int PWRGOOD_IDSC__VI : 1; - unsigned int : 2; - unsigned int BACO_POWER_OFF_DRAM : 1; - unsigned int BACO_BF_MEM_PHY_ISO_CNTRL : 1; - unsigned int BACO_BIF_SCLK_SWITCH__VI : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BASE_ADDR_1 { - struct { - unsigned int BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BASE_ADDR_2 { - struct { - unsigned int BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BASE_ADDR_3 { - struct { - unsigned int BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BASE_ADDR_4 { - struct { - unsigned int BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BASE_ADDR_5 { - struct { - unsigned int BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BASE_ADDR_6 { - struct { - unsigned int BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BASE_CLASS { - struct { - unsigned int BASE_CLASS : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BCI_DEBUG_READ { - struct { - unsigned int DATA : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_BACO_DEBUG_LATCH__CI__VI { - struct { - unsigned int BIF_BACO_LATCH_FLG : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_BACO_DEBUG__CI__VI { - struct { - unsigned int BIF_BACO_SCANDUMP_FLG : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_BACO_MSIC__CI { - struct { - unsigned int BIF_XTALIN_SEL : 1; - unsigned int BACO_LINK_RST_SEL : 2; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_BUSNUM_CNTL1 { - struct { - unsigned int ID_MASK : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_BUSNUM_CNTL2 { - struct { - unsigned int AUTOUPDATE_SEL : 8; - unsigned int AUTOUPDATE_EN : 1; - unsigned int : 7; - unsigned int HDPREG_CNTL : 1; - unsigned int ERROR_MULTIPLE_ID_MATCH : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_BUSNUM_LIST0 { - struct { - unsigned int ID0 : 8; - unsigned int ID1 : 8; - unsigned int ID2 : 8; - unsigned int ID3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_BUSNUM_LIST1 { - struct { - unsigned int ID4 : 8; - unsigned int ID5 : 8; - unsigned int ID6 : 8; - unsigned int ID7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_BUSY_DELAY_CNTR { - struct { - unsigned int DELAY_CNT : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_CC_RFE_IMP_OVERRIDECNTL__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_PLL_RX_IMPVAL : 4; - unsigned int STRAP_PLL_RX_IMPVAL_EN : 1; - unsigned int STRAP_PLL_TX_IMPVAL_PD : 4; - unsigned int STRAP_PLL_TX_IMPVAL_EN_PD : 1; - unsigned int STRAP_PLL_TX_IMPVAL_PU : 4; - unsigned int STRAP_PLL_TX_IMPVAL_EN_PU : 1; - unsigned int STRAP_PLL_IMP_DBG_ANALOG_EN : 1; - unsigned int STRAP_PLL_IMP_IGNORE_QUICKSIM__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_CLK_PDWN_DELAY_TIMER__SI__CI { - struct { - unsigned int TIMER : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_DEBUG_CNTL { - struct { - unsigned int DEBUG_EN : 1; - unsigned int DEBUG_MULTIBLOCKEN : 1; - unsigned int DEBUG_OUT_EN : 1; - unsigned int DEBUG_PAD_SEL : 1; - unsigned int DEBUG_BYTESEL_BLK1 : 1; - unsigned int DEBUG_BYTESEL_BLK2 : 1; - unsigned int DEBUG_SYNC_EN : 1; - unsigned int DEBUG_SWAP : 1; - unsigned int DEBUG_IDSEL_BLK1 : 5; - unsigned int : 3; - unsigned int DEBUG_IDSEL_BLK2 : 5; - unsigned int : 3; - unsigned int DEBUG_IDSEL_XSP : 1; - unsigned int : 5; - unsigned int DEBUG_SYNC_CLKSEL : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_DEBUG_MUX { - struct { - unsigned int DEBUG_MUX_BLK1 : 6; - unsigned int : 2; - unsigned int DEBUG_MUX_BLK2 : 6; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_DEBUG_OUT { - struct { - unsigned int DEBUG_OUTPUT : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_DEVFUNCNUM_LIST0__CI__VI { - struct { - unsigned int DEVFUNC_ID0 : 8; - unsigned int DEVFUNC_ID1 : 8; - unsigned int DEVFUNC_ID2 : 8; - unsigned int DEVFUNC_ID3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_DEVFUNCNUM_LIST1__CI__VI { - struct { - unsigned int DEVFUNC_ID4 : 8; - unsigned int DEVFUNC_ID5 : 8; - unsigned int DEVFUNC_ID6 : 8; - unsigned int DEVFUNC_ID7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_DOORBELL_CNTL__CI__VI { - struct { - unsigned int SELF_RING_DIS : 1; - unsigned int TRANS_CHECK_DIS : 1; - unsigned int UNTRANS_LBACK_EN : 1; - unsigned int NON_CONSECUTIVE_BE_ZERO_DIS : 1; - unsigned int DOORBELL_MONITOR_EN__VI : 1; - unsigned int DOORBELL_INTERRUPT_STATUS__VI : 1; - unsigned int : 10; - unsigned int DOORBELL_INTERRUPT_CLEAR__VI : 1; - unsigned int : 7; - unsigned int DB_MNTR_INTGEN_DIS__VI : 1; - unsigned int DB_MNTR_INTGEN_MODE_0__VI : 1; - unsigned int DB_MNTR_INTGEN_MODE_1__VI : 1; - unsigned int DB_MNTR_INTGEN_MODE_2__VI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_FB_EN { - struct { - unsigned int FB_READ_EN : 1; - unsigned int FB_WRITE_EN : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_FEATURES_CONTROL_MISC__CI__VI { - struct { - unsigned int MST_BIF_REQ_EP_DIS : 1; - unsigned int SLV_BIF_CPL_EP_DIS : 1; - unsigned int BIF_SLV_REQ_EP_DIS : 1; - unsigned int BIF_MST_CPL_EP_DIS : 1; - unsigned int UR_PSN_PKT_REPORT_POISON_DIS : 1; - unsigned int POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS : 1; - unsigned int POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS : 1; - unsigned int PLL_SWITCH_IMPCTL_CAL_DONE_DIS : 1; - unsigned int IGNORE_BE_CHECK_GASKET_COMB_DIS : 1; - unsigned int MC_BIF_REQ_ID_ROUTING_DIS__VI : 1; - unsigned int AZ_BIF_REQ_ID_ROUTING_DIS__VI : 1; - unsigned int ATC_PRG_RESP_PASID_UR_EN__VI : 1; - unsigned int BIF_RB_SET_OVERFLOW_EN__VI : 1; - unsigned int ATOMIC_ERR_INT_DIS__VI : 1; - unsigned int : 1; - unsigned int BME_HDL_NONVIR_EN__VI : 1; - unsigned int INIT_PFFLR_CRS_RET_DIS__VI : 1; - unsigned int FLR_MST_PEND_CHK_DIS__VI : 1; - unsigned int FLR_SLV_PEND_CHK_DIS__VI : 1; - unsigned int SOFT_PF_FLR_UR_CFG_EN__VI : 1; - unsigned int FLR_OSTD_UR_DIS__VI : 1; - unsigned int FLR_OSTD_HDL_DIS__VI : 1; - unsigned int FLR_NEWREQ_HDL_DIS__VI : 1; - unsigned int FLR_CRS_CFG_DIS__VI : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__CI__VI { - struct { - unsigned int UPDATE_PERIOD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_IMPCTL_RXCNTL__CI__VI { - struct { - unsigned int RX_ADJUST : 3; - unsigned int RX_BIAS_HIGH : 1; - unsigned int CONT_AFTER_RX_DECT : 1; - unsigned int : 1; - unsigned int SUSPEND : 1; - unsigned int FORCE_RST : 1; - unsigned int LOWER_RX_ADJ_THRESH : 4; - unsigned int LOWER_RX_ADJ : 1; - unsigned int UPPER_RX_ADJ_THRESH : 4; - unsigned int UPPER_RX_ADJ : 1; - unsigned int RX_IMP_LOCKED : 1; - unsigned int RX_IMP_READBACK_SEL : 1; - unsigned int RX_IMP_READBACK : 4; - unsigned int : 4; - unsigned int RX_CMP_AMBIG : 1; - unsigned int CAL_DONE : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_IMPCTL_SMPLCNTL__CI__VI { - struct { - unsigned int FORCE_DONE : 1; - unsigned int RxPDNB : 1; - unsigned int TxPDNB_pd : 1; - unsigned int TxPDNB_pu : 1; - unsigned int : 4; - unsigned int SAMPLE_PERIOD : 5; - unsigned int EXTEND_SAMPLES : 1; - unsigned int FORCE_ENABLE : 1; - unsigned int SETUP_TIME : 5; - unsigned int LOWER_SAMPLE_THRESH : 6; - unsigned int UPPER_SAMPLE_THRESH : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_IMPCTL_TXCNTL_pd__CI__VI { - struct { - unsigned int TX_ADJUST_pd : 3; - unsigned int TX_BIAS_HIGH_pd : 1; - unsigned int : 4; - unsigned int LOWER_TX_ADJ_THRESH_pd : 4; - unsigned int LOWER_TX_ADJ_pd : 1; - unsigned int UPPER_TX_ADJ_THRESH_pd : 4; - unsigned int UPPER_TX_ADJ_pd : 1; - unsigned int TX_IMP_LOCKED_pd : 1; - unsigned int TX_IMP_READBACK_SEL_pd : 1; - unsigned int TX_IMP_READBACK_pd : 4; - unsigned int : 4; - unsigned int TX_CMP_AMBIG_pd : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_IMPCTL_TXCNTL_pu__CI__VI { - struct { - unsigned int TX_ADJUST_pu : 3; - unsigned int TX_BIAS_HIGH_pu : 1; - unsigned int : 4; - unsigned int LOWER_TX_ADJ_THRESH_pu : 4; - unsigned int LOWER_TX_ADJ_pu : 1; - unsigned int UPPER_TX_ADJ_THRESH_pu : 4; - unsigned int UPPER_TX_ADJ_pu : 1; - unsigned int TX_IMP_LOCKED_pu : 1; - unsigned int TX_IMP_READBACK_SEL_pu : 1; - unsigned int TX_IMP_READBACK_pu : 4; - unsigned int : 4; - unsigned int TX_CMP_AMBIG_pu : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_LNCNT_RESET__CI { - struct { - unsigned int RESET_LNCNT_EN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_PERFCOUNTER0_RESULT__CI__VI { - struct { - unsigned int PERFCOUNTER_RESULT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_PERFCOUNTER1_RESULT__CI__VI { - struct { - unsigned int PERFCOUNTER_RESULT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_PERFMON_CNTL__CI__VI { - struct { - unsigned int PERFCOUNTER_EN : 1; - unsigned int PERFCOUNTER_RESET0 : 1; - unsigned int PERFCOUNTER_RESET1 : 1; - unsigned int : 5; - unsigned int PERF_SEL0 : 5; - unsigned int PERF_SEL1 : 5; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_PIF_TXCLK_SWITCH_TIMER__CI { - struct { - unsigned int PLL0_ACK_TIMER : 3; - unsigned int PLL1_ACK_TIMER : 3; - unsigned int PLL_SWITCH_TIMER : 4; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_PWDN_COMMAND__CI { - struct { - unsigned int REG_BU_pw_cmd : 1; - unsigned int REG_RWREG_RFEWDBIF_pw_cmd : 1; - unsigned int REG_BX_pw_cmd : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_PWDN_COMMAND__VI { - struct { - unsigned int REG_BU_pw_cmd : 1; - unsigned int REG_RWREG_RFEWDBIF_pw_cmd : 1; - unsigned int REG_SMBUS_pw_cmd : 1; - unsigned int REG_BX_pw_cmd : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_PWDN_STATUS__CI { - struct { - unsigned int BU_REG_pw_status : 1; - unsigned int RWREG_RFEWDBIF_REG_pw_status : 1; - unsigned int BX_REG_pw_status : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_PWDN_STATUS__VI { - struct { - unsigned int BU_REG_pw_status : 1; - unsigned int RWREG_RFEWDBIF_REG_pw_status : 1; - unsigned int SMBUS_REG_pw_status : 1; - unsigned int BX_REG_pw_status : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RESET_CNTL__CI { - struct { - unsigned int STRAP_EN : 1; - unsigned int RST_DONE : 1; - unsigned int LINK_TRAIN_EN : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RESET_EN__SI__CI { - struct { - unsigned int : 1; - unsigned int SOFT_RST_MODE__CI : 1; - unsigned int PHY_RESET_EN : 1; - unsigned int COR_RESET_EN : 1; - unsigned int REG_RESET_EN : 1; - unsigned int STY_RESET_EN : 1; - unsigned int CFG_RESET_EN : 1; - unsigned int DRV_RESET_EN : 1; - unsigned int RESET_CFGREG_ONLY_EN : 1; - unsigned int HOT_RESET_EN : 1; - unsigned int LINK_DISABLE_RESET_EN : 1; - unsigned int LINK_DOWN_RESET_EN : 1; - unsigned int CFG_RESET_PULSE_WIDTH : 6; - unsigned int DRV_RESET_DELAY_SEL : 2; - unsigned int PIF_RSTB_EN__CI : 1; - unsigned int PIF_STRAP_ALLVALID_EN__CI : 1; - unsigned int BIF_COR_RESET_EN__CI : 1; - unsigned int FUNC0_FLR_EN__CI : 1; - unsigned int FUNC1_FLR_EN__CI : 1; - unsigned int FUNC2_FLR_EN__CI : 1; - unsigned int FUNC0_RESET_DELAY_SEL__CI : 2; - unsigned int FUNC1_RESET_DELAY_SEL__CI : 2; - unsigned int FUNC2_RESET_DELAY_SEL__CI : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_CLIENT_SOFTRST_TRIGGER__CI__VI { - struct { - unsigned int CLIENT0_RFE_RFEWDBIF_rst : 1; - unsigned int CLIENT1_RFE_RFEWDBIF_rst : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_IMPRST_CNTL__CI__VI { - struct { - unsigned int REG_RST_impEn : 1; - unsigned int : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_MASTER_SOFTRST_TRIGGER__CI { - struct { - unsigned int BU_rst : 1; - unsigned int RWREG_RFEWDBIF_rst : 1; - unsigned int BX_rst : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_MASTER_SOFTRST_TRIGGER__VI { - struct { - unsigned int BU_rst : 1; - unsigned int RWREG_RFEWDBIF_rst : 1; - unsigned int SMBUS_rst : 1; - unsigned int BX_rst : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_MMCFG_CNTL__CI__VI { - struct { - unsigned int CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN : 1; - unsigned int CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL : 3; - unsigned int CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN : 1; - unsigned int CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL : 3; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_MST_BU_CMDSTATUS__CI__VI { - struct { - unsigned int REG_BU_clkGate_timer : 8; - unsigned int REG_BU_clkSetup_timer : 4; - unsigned int : 4; - unsigned int REG_BU_timeout_timer : 8; - unsigned int BU_RFE_mstTimeout : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_MST_BX_CMDSTATUS__CI__VI { - struct { - unsigned int REG_BX_clkGate_timer : 8; - unsigned int REG_BX_clkSetup_timer : 4; - unsigned int : 4; - unsigned int REG_BX_timeout_timer : 8; - unsigned int BX_RFE_mstTimeout : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__CI__VI { - struct { - unsigned int REG_RWREG_RFEWDBIF_clkGate_timer : 8; - unsigned int REG_RWREG_RFEWDBIF_clkSetup_timer : 4; - unsigned int : 4; - unsigned int REG_RWREG_RFEWDBIF_timeout_timer : 8; - unsigned int RWREG_RFEWDBIF_RFE_mstTimeout : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_MST_TMOUT_STATUS__CI__VI { - struct { - unsigned int MstTmoutStatus : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_SNOOP_REG__CI__VI { - struct { - unsigned int REG_SNOOP_ARBITER : 1; - unsigned int REG_SNOOP_ALLMASTER : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_SOFTRST_CNTL__CI { - struct { - unsigned int REG_RST_rstTimer : 16; - unsigned int : 13; - unsigned int : 1; - unsigned int REG_RST_softRstPropEn : 1; - unsigned int SoftRstReg : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_SOFTRST_CNTL__VI { - struct { - unsigned int REG_RST_rstTimer : 16; - unsigned int : 14; - unsigned int REG_RST_softRstPropEn : 1; - unsigned int SoftRstReg : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SCRATCH0 { - struct { - unsigned int BIF_SCRATCH0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SCRATCH1 { - struct { - unsigned int BIF_SCRATCH1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SLVARB_MODE__CI__VI { - struct { - unsigned int SLVARB_MODE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_DISP_LOWER__CI { - struct { - unsigned int : 2; - unsigned int SSA_DISP_LOWER : 16; - unsigned int : 12; - unsigned int SSA_DISP_REG_CMP_EN : 1; - unsigned int SSA_DISP_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_DISP_UPPER__CI { - struct { - unsigned int : 2; - unsigned int SSA_DISP_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_GFX0_LOWER__CI { - struct { - unsigned int : 2; - unsigned int SSA_GFX0_LOWER : 16; - unsigned int : 12; - unsigned int SSA_GFX0_REG_CMP_EN : 1; - unsigned int SSA_GFX0_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_GFX0_UPPER__CI { - struct { - unsigned int : 2; - unsigned int SSA_GFX0_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_GFX1_LOWER__CI { - struct { - unsigned int : 2; - unsigned int SSA_GFX1_LOWER : 16; - unsigned int : 12; - unsigned int SSA_GFX1_REG_CMP_EN : 1; - unsigned int SSA_GFX1_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_GFX1_UPPER__CI { - struct { - unsigned int : 2; - unsigned int SSA_GFX1_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_GFX2_LOWER__CI { - struct { - unsigned int : 2; - unsigned int SSA_GFX2_LOWER : 16; - unsigned int : 12; - unsigned int SSA_GFX2_REG_CMP_EN : 1; - unsigned int SSA_GFX2_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_GFX2_UPPER__CI { - struct { - unsigned int : 2; - unsigned int SSA_GFX2_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_GFX3_LOWER__CI { - struct { - unsigned int : 2; - unsigned int SSA_GFX3_LOWER : 16; - unsigned int : 12; - unsigned int SSA_GFX3_REG_CMP_EN : 1; - unsigned int SSA_GFX3_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_GFX3_UPPER__CI { - struct { - unsigned int : 2; - unsigned int SSA_GFX3_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_MC_LOWER__CI { - struct { - unsigned int : 2; - unsigned int SSA_MC_LOWER : 16; - unsigned int : 11; - unsigned int SSA_MC_FB_STALL_EN : 1; - unsigned int SSA_MC_REG_CMP_EN : 1; - unsigned int SSA_MC_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_MC_UPPER__CI { - struct { - unsigned int : 2; - unsigned int SSA_MC_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SSA_PWR_STATUS__CI { - struct { - unsigned int SSA_GFX_PWR_STATUS : 1; - unsigned int SSA_DISP_PWR_STATUS : 1; - unsigned int SSA_MC_PWR_STATUS : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_XDMA_HI__CI__VI { - struct { - unsigned int BIF_XDMA_UPPER_BOUND : 29; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_XDMA_LO__CI__VI { - struct { - unsigned int BIF_XDMA_LOWER_BOUND : 29; - unsigned int : 2; - unsigned int BIF_XDMA_APER_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_0 { - struct { - unsigned int BIOS_SCRATCH_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_1 { - struct { - unsigned int BIOS_SCRATCH_1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_10 { - struct { - unsigned int BIOS_SCRATCH_10 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_11 { - struct { - unsigned int BIOS_SCRATCH_11 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_12 { - struct { - unsigned int BIOS_SCRATCH_12 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_13 { - struct { - unsigned int BIOS_SCRATCH_13 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_14 { - struct { - unsigned int BIOS_SCRATCH_14 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_15 { - struct { - unsigned int BIOS_SCRATCH_15 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_2 { - struct { - unsigned int BIOS_SCRATCH_2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_3 { - struct { - unsigned int BIOS_SCRATCH_3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_4 { - struct { - unsigned int BIOS_SCRATCH_4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_5 { - struct { - unsigned int BIOS_SCRATCH_5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_6 { - struct { - unsigned int BIOS_SCRATCH_6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_7 { - struct { - unsigned int BIOS_SCRATCH_7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_8 { - struct { - unsigned int BIOS_SCRATCH_8 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIOS_SCRATCH_9 { - struct { - unsigned int BIOS_SCRATCH_9 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIST { - struct { - unsigned int BIST_COMP : 4; - unsigned int : 2; - unsigned int BIST_STRT : 1; - unsigned int BIST_CAP : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL1_PWM_ABM_CNTL__SI__VI { - struct { - unsigned int BL1_PWM_USE_ABM_EN : 1; - unsigned int BL1_PWM_USE_AMBIENT_LEVEL_EN : 1; - unsigned int BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN : 1; - unsigned int BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN : 1; - unsigned int : 12; - unsigned int BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL1_PWM_AMBIENT_LIGHT_LEVEL__SI__VI { - struct { - unsigned int BL1_PWM_AMBIENT_LIGHT_LEVEL : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL1_PWM_BL_UPDATE_SAMPLE_RATE__SI__VI { - struct { - unsigned int BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN : 1; - unsigned int BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER : 1; - unsigned int : 6; - unsigned int BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT : 8; - unsigned int BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET : 8; - unsigned int : 7; - unsigned int ABM1_HGLS_REG_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL1_PWM_CURRENT_ABM_LEVEL__SI__VI { - struct { - unsigned int BL1_PWM_CURRENT_ABM_LEVEL : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL1_PWM_FINAL_DUTY_CYCLE__SI__VI { - struct { - unsigned int BL1_PWM_FINAL_DUTY_CYCLE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL1_PWM_GRP2_REG_LOCK__SI__VI { - struct { - unsigned int BL1_PWM_GRP2_REG_LOCK : 1; - unsigned int : 7; - unsigned int BL1_PWM_GRP2_REG_UPDATE_PENDING : 1; - unsigned int : 7; - unsigned int BL1_PWM_GRP2_UPDATE_AT_FRAME_START : 1; - unsigned int BL1_PWM_GRP2_FRAME_START_DISP_SEL : 3; - unsigned int : 4; - unsigned int BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN : 1; - unsigned int : 6; - unsigned int BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL1_PWM_MINIMUM_DUTY_CYCLE__SI__VI { - struct { - unsigned int BL1_PWM_MINIMUM_DUTY_CYCLE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL1_PWM_TARGET_ABM_LEVEL__SI__VI { - struct { - unsigned int BL1_PWM_TARGET_ABM_LEVEL : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL1_PWM_USER_LEVEL__SI__VI { - struct { - unsigned int BL1_PWM_USER_LEVEL : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL_PWM_CNTL2__SI__VI { - struct { - unsigned int BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE : 16; - unsigned int : 12; - unsigned int DBG_BL_PWM_INPUT_REFCLK_SELECT : 2; - unsigned int BL_PWM_OVERRIDE_BL_OUT_ENABLE : 1; - unsigned int BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL_PWM_CNTL__SI__VI { - struct { - unsigned int BL_ACTIVE_INT_FRAC_CNT : 16; - unsigned int : 14; - unsigned int BL_PWM_FRACTIONAL_EN : 1; - unsigned int BL_PWM_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL_PWM_GRP1_REG_LOCK__SI__VI { - struct { - unsigned int BL_PWM_GRP1_REG_LOCK : 1; - unsigned int : 7; - unsigned int BL_PWM_GRP1_REG_UPDATE_PENDING : 1; - unsigned int : 7; - unsigned int BL_PWM_GRP1_UPDATE_AT_FRAME_START : 1; - unsigned int BL_PWM_GRP1_FRAME_START_DISP_SEL : 3; - unsigned int : 4; - unsigned int BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN : 1; - unsigned int : 6; - unsigned int BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BL_PWM_PERIOD_CNTL__SI__VI { - struct { - unsigned int BL_PWM_PERIOD : 16; - unsigned int BL_PWM_PERIOD_BITCNT : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BUS_CNTL { - struct { - unsigned int BIOS_ROM_WRT_EN : 1; - unsigned int BIOS_ROM_DIS : 1; - unsigned int PMI_IO_DIS : 1; - unsigned int PMI_MEM_DIS : 1; - unsigned int PMI_BM_DIS : 1; - unsigned int PMI_INT_DIS : 1; - unsigned int VGA_REG_COHERENCY_DIS : 1; - unsigned int VGA_MEM_COHERENCY_DIS : 1; - unsigned int BIF_ERR_RTR_BKPRESSURE_EN : 1; - unsigned int : 1; - unsigned int SET_AZ_TC : 3; - unsigned int SET_MC_TC : 3; - unsigned int ZERO_BE_WR_EN : 1; - unsigned int ZERO_BE_RD_EN : 1; - unsigned int RD_STALL_IO_WR__CI__VI : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BX_RESET_EN__CI__VI { - struct { - unsigned int COR_RESET_EN : 1; - unsigned int REG_RESET_EN : 1; - unsigned int STY_RESET_EN : 1; - unsigned int : 5; - unsigned int FLR_TWICE_EN__VI : 1; - unsigned int FLR_TIMER_SEL__VI : 2; - unsigned int : 4; - unsigned int DB_APER_RESET_EN__VI : 1; - unsigned int RESET_ON_VFENABLE_LOW_EN__VI : 1; - unsigned int PF_FLR_NEWHDL_EN__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CACHE_LINE { - struct { - unsigned int CACHE_LINE_SIZE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CAPTURE_HOST_BUSNUM { - struct { - unsigned int CHECK_EN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CAP_PTR { - struct { - unsigned int CAP_PTR : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND0_CONTROL { - struct { - unsigned int COLOR_SRCBLEND : 5; - unsigned int COLOR_COMB_FCN : 3; - unsigned int COLOR_DESTBLEND : 5; - unsigned int : 3; - unsigned int ALPHA_SRCBLEND : 5; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int ALPHA_DESTBLEND : 5; - unsigned int SEPARATE_ALPHA_BLEND : 1; - unsigned int ENABLE : 1; - unsigned int DISABLE_ROP3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND1_CONTROL { - struct { - unsigned int COLOR_SRCBLEND : 5; - unsigned int COLOR_COMB_FCN : 3; - unsigned int COLOR_DESTBLEND : 5; - unsigned int : 3; - unsigned int ALPHA_SRCBLEND : 5; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int ALPHA_DESTBLEND : 5; - unsigned int SEPARATE_ALPHA_BLEND : 1; - unsigned int ENABLE : 1; - unsigned int DISABLE_ROP3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND2_CONTROL { - struct { - unsigned int COLOR_SRCBLEND : 5; - unsigned int COLOR_COMB_FCN : 3; - unsigned int COLOR_DESTBLEND : 5; - unsigned int : 3; - unsigned int ALPHA_SRCBLEND : 5; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int ALPHA_DESTBLEND : 5; - unsigned int SEPARATE_ALPHA_BLEND : 1; - unsigned int ENABLE : 1; - unsigned int DISABLE_ROP3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND3_CONTROL { - struct { - unsigned int COLOR_SRCBLEND : 5; - unsigned int COLOR_COMB_FCN : 3; - unsigned int COLOR_DESTBLEND : 5; - unsigned int : 3; - unsigned int ALPHA_SRCBLEND : 5; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int ALPHA_DESTBLEND : 5; - unsigned int SEPARATE_ALPHA_BLEND : 1; - unsigned int ENABLE : 1; - unsigned int DISABLE_ROP3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND4_CONTROL { - struct { - unsigned int COLOR_SRCBLEND : 5; - unsigned int COLOR_COMB_FCN : 3; - unsigned int COLOR_DESTBLEND : 5; - unsigned int : 3; - unsigned int ALPHA_SRCBLEND : 5; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int ALPHA_DESTBLEND : 5; - unsigned int SEPARATE_ALPHA_BLEND : 1; - unsigned int ENABLE : 1; - unsigned int DISABLE_ROP3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND5_CONTROL { - struct { - unsigned int COLOR_SRCBLEND : 5; - unsigned int COLOR_COMB_FCN : 3; - unsigned int COLOR_DESTBLEND : 5; - unsigned int : 3; - unsigned int ALPHA_SRCBLEND : 5; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int ALPHA_DESTBLEND : 5; - unsigned int SEPARATE_ALPHA_BLEND : 1; - unsigned int ENABLE : 1; - unsigned int DISABLE_ROP3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND6_CONTROL { - struct { - unsigned int COLOR_SRCBLEND : 5; - unsigned int COLOR_COMB_FCN : 3; - unsigned int COLOR_DESTBLEND : 5; - unsigned int : 3; - unsigned int ALPHA_SRCBLEND : 5; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int ALPHA_DESTBLEND : 5; - unsigned int SEPARATE_ALPHA_BLEND : 1; - unsigned int ENABLE : 1; - unsigned int DISABLE_ROP3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND7_CONTROL { - struct { - unsigned int COLOR_SRCBLEND : 5; - unsigned int COLOR_COMB_FCN : 3; - unsigned int COLOR_DESTBLEND : 5; - unsigned int : 3; - unsigned int ALPHA_SRCBLEND : 5; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int ALPHA_DESTBLEND : 5; - unsigned int SEPARATE_ALPHA_BLEND : 1; - unsigned int ENABLE : 1; - unsigned int DISABLE_ROP3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND_ALPHA { - struct { - unsigned int BLEND_ALPHA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND_BLUE { - struct { - unsigned int BLEND_BLUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND_GREEN { - struct { - unsigned int BLEND_GREEN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_BLEND_RED { - struct { - unsigned int BLEND_RED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_CGTT_SCLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_ATTRIB { - struct { - unsigned int TILE_MODE_INDEX : 5; - unsigned int FMASK_TILE_MODE_INDEX : 5; - unsigned int FMASK_BANK_HEIGHT : 2; - unsigned int NUM_SAMPLES : 3; - unsigned int NUM_FRAGMENTS : 2; - unsigned int FORCE_DST_ALPHA_1 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_CLEAR_WORD0 { - struct { - unsigned int CLEAR_WORD0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_CLEAR_WORD1 { - struct { - unsigned int CLEAR_WORD1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_CMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_CMASK_SLICE { - struct { - unsigned int TILE_MAX : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_FMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_FMASK_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_INFO { - struct { - unsigned int ENDIAN : 2; - unsigned int FORMAT : 5; - unsigned int LINEAR_GENERAL : 1; - unsigned int NUMBER_TYPE : 3; - unsigned int COMP_SWAP : 2; - unsigned int FAST_CLEAR : 1; - unsigned int COMPRESSION : 1; - unsigned int BLEND_CLAMP : 1; - unsigned int BLEND_BYPASS : 1; - unsigned int SIMPLE_FLOAT : 1; - unsigned int ROUND_MODE : 1; - unsigned int CMASK_IS_LINEAR : 1; - unsigned int BLEND_OPT_DONT_RD_DST : 3; - unsigned int BLEND_OPT_DISCARD_PIXEL : 3; - unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1; - unsigned int FMASK_COMPRESS_1FRAG_ONLY__VI : 1; - unsigned int DCC_ENABLE__VI : 1; - unsigned int CMASK_ADDR_TYPE__VI : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_PITCH { - struct { - unsigned int TILE_MAX : 11; - unsigned int : 9; - unsigned int FMASK_TILE_MAX__CI__VI : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_VIEW { - struct { - unsigned int SLICE_START : 11; - unsigned int : 2; - unsigned int SLICE_MAX : 11; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_ATTRIB { - struct { - unsigned int TILE_MODE_INDEX : 5; - unsigned int FMASK_TILE_MODE_INDEX : 5; - unsigned int FMASK_BANK_HEIGHT : 2; - unsigned int NUM_SAMPLES : 3; - unsigned int NUM_FRAGMENTS : 2; - unsigned int FORCE_DST_ALPHA_1 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_CLEAR_WORD0 { - struct { - unsigned int CLEAR_WORD0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_CLEAR_WORD1 { - struct { - unsigned int CLEAR_WORD1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_CMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_CMASK_SLICE { - struct { - unsigned int TILE_MAX : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_FMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_FMASK_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_INFO { - struct { - unsigned int ENDIAN : 2; - unsigned int FORMAT : 5; - unsigned int LINEAR_GENERAL : 1; - unsigned int NUMBER_TYPE : 3; - unsigned int COMP_SWAP : 2; - unsigned int FAST_CLEAR : 1; - unsigned int COMPRESSION : 1; - unsigned int BLEND_CLAMP : 1; - unsigned int BLEND_BYPASS : 1; - unsigned int SIMPLE_FLOAT : 1; - unsigned int ROUND_MODE : 1; - unsigned int CMASK_IS_LINEAR : 1; - unsigned int BLEND_OPT_DONT_RD_DST : 3; - unsigned int BLEND_OPT_DISCARD_PIXEL : 3; - unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1; - unsigned int FMASK_COMPRESS_1FRAG_ONLY__VI : 1; - unsigned int DCC_ENABLE__VI : 1; - unsigned int CMASK_ADDR_TYPE__VI : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_PITCH { - struct { - unsigned int TILE_MAX : 11; - unsigned int : 9; - unsigned int FMASK_TILE_MAX__CI__VI : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_VIEW { - struct { - unsigned int SLICE_START : 11; - unsigned int : 2; - unsigned int SLICE_MAX : 11; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_ATTRIB { - struct { - unsigned int TILE_MODE_INDEX : 5; - unsigned int FMASK_TILE_MODE_INDEX : 5; - unsigned int FMASK_BANK_HEIGHT : 2; - unsigned int NUM_SAMPLES : 3; - unsigned int NUM_FRAGMENTS : 2; - unsigned int FORCE_DST_ALPHA_1 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_CLEAR_WORD0 { - struct { - unsigned int CLEAR_WORD0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_CLEAR_WORD1 { - struct { - unsigned int CLEAR_WORD1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_CMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_CMASK_SLICE { - struct { - unsigned int TILE_MAX : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_FMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_FMASK_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_INFO { - struct { - unsigned int ENDIAN : 2; - unsigned int FORMAT : 5; - unsigned int LINEAR_GENERAL : 1; - unsigned int NUMBER_TYPE : 3; - unsigned int COMP_SWAP : 2; - unsigned int FAST_CLEAR : 1; - unsigned int COMPRESSION : 1; - unsigned int BLEND_CLAMP : 1; - unsigned int BLEND_BYPASS : 1; - unsigned int SIMPLE_FLOAT : 1; - unsigned int ROUND_MODE : 1; - unsigned int CMASK_IS_LINEAR : 1; - unsigned int BLEND_OPT_DONT_RD_DST : 3; - unsigned int BLEND_OPT_DISCARD_PIXEL : 3; - unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1; - unsigned int FMASK_COMPRESS_1FRAG_ONLY__VI : 1; - unsigned int DCC_ENABLE__VI : 1; - unsigned int CMASK_ADDR_TYPE__VI : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_PITCH { - struct { - unsigned int TILE_MAX : 11; - unsigned int : 9; - unsigned int FMASK_TILE_MAX__CI__VI : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_VIEW { - struct { - unsigned int SLICE_START : 11; - unsigned int : 2; - unsigned int SLICE_MAX : 11; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_ATTRIB { - struct { - unsigned int TILE_MODE_INDEX : 5; - unsigned int FMASK_TILE_MODE_INDEX : 5; - unsigned int FMASK_BANK_HEIGHT : 2; - unsigned int NUM_SAMPLES : 3; - unsigned int NUM_FRAGMENTS : 2; - unsigned int FORCE_DST_ALPHA_1 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_CLEAR_WORD0 { - struct { - unsigned int CLEAR_WORD0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_CLEAR_WORD1 { - struct { - unsigned int CLEAR_WORD1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_CMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_CMASK_SLICE { - struct { - unsigned int TILE_MAX : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_FMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_FMASK_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_INFO { - struct { - unsigned int ENDIAN : 2; - unsigned int FORMAT : 5; - unsigned int LINEAR_GENERAL : 1; - unsigned int NUMBER_TYPE : 3; - unsigned int COMP_SWAP : 2; - unsigned int FAST_CLEAR : 1; - unsigned int COMPRESSION : 1; - unsigned int BLEND_CLAMP : 1; - unsigned int BLEND_BYPASS : 1; - unsigned int SIMPLE_FLOAT : 1; - unsigned int ROUND_MODE : 1; - unsigned int CMASK_IS_LINEAR : 1; - unsigned int BLEND_OPT_DONT_RD_DST : 3; - unsigned int BLEND_OPT_DISCARD_PIXEL : 3; - unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1; - unsigned int FMASK_COMPRESS_1FRAG_ONLY__VI : 1; - unsigned int DCC_ENABLE__VI : 1; - unsigned int CMASK_ADDR_TYPE__VI : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_PITCH { - struct { - unsigned int TILE_MAX : 11; - unsigned int : 9; - unsigned int FMASK_TILE_MAX__CI__VI : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_VIEW { - struct { - unsigned int SLICE_START : 11; - unsigned int : 2; - unsigned int SLICE_MAX : 11; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_ATTRIB { - struct { - unsigned int TILE_MODE_INDEX : 5; - unsigned int FMASK_TILE_MODE_INDEX : 5; - unsigned int FMASK_BANK_HEIGHT : 2; - unsigned int NUM_SAMPLES : 3; - unsigned int NUM_FRAGMENTS : 2; - unsigned int FORCE_DST_ALPHA_1 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_CLEAR_WORD0 { - struct { - unsigned int CLEAR_WORD0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_CLEAR_WORD1 { - struct { - unsigned int CLEAR_WORD1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_CMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_CMASK_SLICE { - struct { - unsigned int TILE_MAX : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_FMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_FMASK_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_INFO { - struct { - unsigned int ENDIAN : 2; - unsigned int FORMAT : 5; - unsigned int LINEAR_GENERAL : 1; - unsigned int NUMBER_TYPE : 3; - unsigned int COMP_SWAP : 2; - unsigned int FAST_CLEAR : 1; - unsigned int COMPRESSION : 1; - unsigned int BLEND_CLAMP : 1; - unsigned int BLEND_BYPASS : 1; - unsigned int SIMPLE_FLOAT : 1; - unsigned int ROUND_MODE : 1; - unsigned int CMASK_IS_LINEAR : 1; - unsigned int BLEND_OPT_DONT_RD_DST : 3; - unsigned int BLEND_OPT_DISCARD_PIXEL : 3; - unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1; - unsigned int FMASK_COMPRESS_1FRAG_ONLY__VI : 1; - unsigned int DCC_ENABLE__VI : 1; - unsigned int CMASK_ADDR_TYPE__VI : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_PITCH { - struct { - unsigned int TILE_MAX : 11; - unsigned int : 9; - unsigned int FMASK_TILE_MAX__CI__VI : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_VIEW { - struct { - unsigned int SLICE_START : 11; - unsigned int : 2; - unsigned int SLICE_MAX : 11; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_ATTRIB { - struct { - unsigned int TILE_MODE_INDEX : 5; - unsigned int FMASK_TILE_MODE_INDEX : 5; - unsigned int FMASK_BANK_HEIGHT : 2; - unsigned int NUM_SAMPLES : 3; - unsigned int NUM_FRAGMENTS : 2; - unsigned int FORCE_DST_ALPHA_1 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_CLEAR_WORD0 { - struct { - unsigned int CLEAR_WORD0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_CLEAR_WORD1 { - struct { - unsigned int CLEAR_WORD1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_CMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_CMASK_SLICE { - struct { - unsigned int TILE_MAX : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_FMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_FMASK_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_INFO { - struct { - unsigned int ENDIAN : 2; - unsigned int FORMAT : 5; - unsigned int LINEAR_GENERAL : 1; - unsigned int NUMBER_TYPE : 3; - unsigned int COMP_SWAP : 2; - unsigned int FAST_CLEAR : 1; - unsigned int COMPRESSION : 1; - unsigned int BLEND_CLAMP : 1; - unsigned int BLEND_BYPASS : 1; - unsigned int SIMPLE_FLOAT : 1; - unsigned int ROUND_MODE : 1; - unsigned int CMASK_IS_LINEAR : 1; - unsigned int BLEND_OPT_DONT_RD_DST : 3; - unsigned int BLEND_OPT_DISCARD_PIXEL : 3; - unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1; - unsigned int FMASK_COMPRESS_1FRAG_ONLY__VI : 1; - unsigned int DCC_ENABLE__VI : 1; - unsigned int CMASK_ADDR_TYPE__VI : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_PITCH { - struct { - unsigned int TILE_MAX : 11; - unsigned int : 9; - unsigned int FMASK_TILE_MAX__CI__VI : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_VIEW { - struct { - unsigned int SLICE_START : 11; - unsigned int : 2; - unsigned int SLICE_MAX : 11; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_ATTRIB { - struct { - unsigned int TILE_MODE_INDEX : 5; - unsigned int FMASK_TILE_MODE_INDEX : 5; - unsigned int FMASK_BANK_HEIGHT : 2; - unsigned int NUM_SAMPLES : 3; - unsigned int NUM_FRAGMENTS : 2; - unsigned int FORCE_DST_ALPHA_1 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_CLEAR_WORD0 { - struct { - unsigned int CLEAR_WORD0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_CLEAR_WORD1 { - struct { - unsigned int CLEAR_WORD1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_CMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_CMASK_SLICE { - struct { - unsigned int TILE_MAX : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_FMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_FMASK_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_INFO { - struct { - unsigned int ENDIAN : 2; - unsigned int FORMAT : 5; - unsigned int LINEAR_GENERAL : 1; - unsigned int NUMBER_TYPE : 3; - unsigned int COMP_SWAP : 2; - unsigned int FAST_CLEAR : 1; - unsigned int COMPRESSION : 1; - unsigned int BLEND_CLAMP : 1; - unsigned int BLEND_BYPASS : 1; - unsigned int SIMPLE_FLOAT : 1; - unsigned int ROUND_MODE : 1; - unsigned int CMASK_IS_LINEAR : 1; - unsigned int BLEND_OPT_DONT_RD_DST : 3; - unsigned int BLEND_OPT_DISCARD_PIXEL : 3; - unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1; - unsigned int FMASK_COMPRESS_1FRAG_ONLY__VI : 1; - unsigned int DCC_ENABLE__VI : 1; - unsigned int CMASK_ADDR_TYPE__VI : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_PITCH { - struct { - unsigned int TILE_MAX : 11; - unsigned int : 9; - unsigned int FMASK_TILE_MAX__CI__VI : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_VIEW { - struct { - unsigned int SLICE_START : 11; - unsigned int : 2; - unsigned int SLICE_MAX : 11; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_ATTRIB { - struct { - unsigned int TILE_MODE_INDEX : 5; - unsigned int FMASK_TILE_MODE_INDEX : 5; - unsigned int FMASK_BANK_HEIGHT : 2; - unsigned int NUM_SAMPLES : 3; - unsigned int NUM_FRAGMENTS : 2; - unsigned int FORCE_DST_ALPHA_1 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_CLEAR_WORD0 { - struct { - unsigned int CLEAR_WORD0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_CLEAR_WORD1 { - struct { - unsigned int CLEAR_WORD1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_CMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_CMASK_SLICE { - struct { - unsigned int TILE_MAX : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_FMASK { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_FMASK_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_INFO { - struct { - unsigned int ENDIAN : 2; - unsigned int FORMAT : 5; - unsigned int LINEAR_GENERAL : 1; - unsigned int NUMBER_TYPE : 3; - unsigned int COMP_SWAP : 2; - unsigned int FAST_CLEAR : 1; - unsigned int COMPRESSION : 1; - unsigned int BLEND_CLAMP : 1; - unsigned int BLEND_BYPASS : 1; - unsigned int SIMPLE_FLOAT : 1; - unsigned int ROUND_MODE : 1; - unsigned int CMASK_IS_LINEAR : 1; - unsigned int BLEND_OPT_DONT_RD_DST : 3; - unsigned int BLEND_OPT_DISCARD_PIXEL : 3; - unsigned int FMASK_COMPRESSION_DISABLE__CI__VI : 1; - unsigned int FMASK_COMPRESS_1FRAG_ONLY__VI : 1; - unsigned int DCC_ENABLE__VI : 1; - unsigned int CMASK_ADDR_TYPE__VI : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_PITCH { - struct { - unsigned int TILE_MAX : 11; - unsigned int : 9; - unsigned int FMASK_TILE_MAX__CI__VI : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_SLICE { - struct { - unsigned int TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_VIEW { - struct { - unsigned int SLICE_START : 11; - unsigned int : 2; - unsigned int SLICE_MAX : 11; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR_CONTROL { - struct { - unsigned int DISABLE_DUAL_QUAD__VI : 1; - unsigned int : 2; - unsigned int DEGAMMA_ENABLE : 1; - unsigned int MODE : 3; - unsigned int : 9; - unsigned int ROP3 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_1 { - struct { - unsigned int CB_BUSY__VI : 1; - unsigned int DB_CB_TILE_VALID_READY__VI : 1; - unsigned int DB_CB_TILE_VALID_READYB__VI : 1; - unsigned int DB_CB_TILE_VALIDB_READY__VI : 1; - unsigned int DB_CB_TILE_VALIDB_READYB__VI : 1; - unsigned int DB_CB_LQUAD_VALID_READY__VI : 1; - unsigned int DB_CB_LQUAD_VALID_READYB__VI : 1; - unsigned int DB_CB_LQUAD_VALIDB_READY__VI : 1; - unsigned int DB_CB_LQUAD_VALIDB_READYB__VI : 1; - unsigned int CB_TAP_WRREQ_VALID_READY__VI : 1; - unsigned int CB_TAP_WRREQ_VALID_READYB__VI : 1; - unsigned int CB_TAP_WRREQ_VALIDB_READY__VI : 1; - unsigned int CB_TAP_WRREQ_VALIDB_READYB__VI : 1; - unsigned int CB_TAP_RDREQ_VALID_READY__VI : 1; - unsigned int CB_TAP_RDREQ_VALID_READYB__VI : 1; - unsigned int CB_TAP_RDREQ_VALIDB_READY__VI : 1; - unsigned int CB_TAP_RDREQ_VALIDB_READYB__VI : 1; - unsigned int CM_FC_TILE_VALID_READY__VI : 1; - unsigned int CM_FC_TILE_VALID_READYB__VI : 1; - unsigned int CM_FC_TILE_VALIDB_READY__VI : 1; - unsigned int CM_FC_TILE_VALIDB_READYB__VI : 1; - unsigned int FC_CLEAR_QUAD_VALID_READY__VI : 1; - unsigned int FC_CLEAR_QUAD_VALID_READYB__VI : 1; - unsigned int FC_CLEAR_QUAD_VALIDB_READY__VI : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_13__SI__CI { - struct { - unsigned int TILE_INTFC_BUSY : 1; - unsigned int MU_BUSY : 1; - unsigned int TQ_BUSY : 1; - unsigned int AC_BUSY : 1; - unsigned int CRW_BUSY : 1; - unsigned int CACHE_CTRL_BUSY : 1; - unsigned int MC_WR_PENDING : 1; - unsigned int FC_WR_PENDING : 1; - unsigned int FC_RD_PENDING : 1; - unsigned int EVICT_PENDING : 1; - unsigned int LAST_RD_ARB_WINNER : 1; - unsigned int MU_STATE : 8; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_13__VI { - struct { - unsigned int FC_PF_FC_KEYID_RDLAT_FIFO_FULL : 1; - unsigned int FC_DOC_QTILE_CAM_MISS : 1; - unsigned int FC_DOC_QTILE_CAM_HIT : 1; - unsigned int FC_DOC_CLINE_CAM_MISS : 1; - unsigned int FC_DOC_CLINE_CAM_HIT : 1; - unsigned int FC_DOC_OVERWROTE_1_SECTOR : 1; - unsigned int FC_DOC_OVERWROTE_2_SECTORS : 1; - unsigned int FC_DOC_OVERWROTE_3_SECTORS : 1; - unsigned int FC_DOC_OVERWROTE_4_SECTORS : 1; - unsigned int FC_PF_DCC_CACHE_HIT : 1; - unsigned int FC_PF_DCC_CACHE_TAG_MISS : 1; - unsigned int FC_PF_DCC_CACHE_SECTOR_MISS : 1; - unsigned int FC_PF_DCC_CACHE_REEVICTION_STALL : 1; - unsigned int FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL : 1; - unsigned int FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL : 1; - unsigned int FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL : 1; - unsigned int FC_PF_DCC_CACHE_READ_OUTPUT_STALL : 1; - unsigned int FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL : 1; - unsigned int FC_PF_DCC_CACHE_ACK_OUTPUT_STALL : 1; - unsigned int FC_PF_DCC_CACHE_STALL : 1; - unsigned int FC_PF_DCC_CACHE_FLUSH : 1; - unsigned int FC_PF_DCC_CACHE_SECTORS_FLUSHED : 1; - unsigned int FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED : 1; - unsigned int FC_PF_DCC_CACHE_TAGS_FLUSHED : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_14__SI__CI { - struct { - unsigned int TILE_RETIREMENT_BUSY : 1; - unsigned int FOP_BUSY : 1; - unsigned int LAT_BUSY : 1; - unsigned int CACHE_CTL_BUSY : 1; - unsigned int ADDR_BUSY : 1; - unsigned int MERGE_BUSY : 1; - unsigned int QUAD_BUSY : 1; - unsigned int TILE_BUSY : 1; - unsigned int CLEAR_BUSY : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_14__VI { - struct { - unsigned int FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT : 11; - unsigned int FC_MC_DCC_READ_REQUESTS_IN_FLIGHT : 11; - unsigned int CC_PF_DCC_BEYOND_TILE_SPLIT : 1; - unsigned int CC_PF_DCC_RDREQ_STALL : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_15__SI__CI { - struct { - unsigned int SURF_SYNC_STATE : 2; - unsigned int SURF_SYNC_START : 1; - unsigned int SF_BUSY : 1; - unsigned int CS_BUSY : 1; - unsigned int RB_BUSY : 1; - unsigned int DS_BUSY : 1; - unsigned int TB_BUSY : 1; - unsigned int IB_BUSY : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_15__VI { - struct { - unsigned int CC_PF_DCC_COMPRESS_RATIO_2TO1 : 3; - unsigned int CC_PF_DCC_COMPRESS_RATIO_4TO1 : 2; - unsigned int CC_PF_DCC_COMPRESS_RATIO_4TO2 : 2; - unsigned int CC_PF_DCC_COMPRESS_RATIO_4TO3 : 2; - unsigned int CC_PF_DCC_COMPRESS_RATIO_6TO1 : 2; - unsigned int CC_PF_DCC_COMPRESS_RATIO_6TO2 : 2; - unsigned int CC_PF_DCC_COMPRESS_RATIO_6TO3 : 2; - unsigned int CC_PF_DCC_COMPRESS_RATIO_6TO4 : 2; - unsigned int CC_PF_DCC_COMPRESS_RATIO_6TO5 : 2; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_16__SI__CI { - struct { - unsigned int MC_RDREQ_CREDITS : 6; - unsigned int LAST_RD_GRANT_VEC : 4; - unsigned int MC_WRREQ_CREDITS : 6; - unsigned int LAST_WR_GRANT_VEC : 4; - unsigned int CC_WRREQ_FIFO_EMPTY : 1; - unsigned int FC_WRREQ_FIFO_EMPTY : 1; - unsigned int CM_WRREQ_FIFO_EMPTY : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_16__VI { - struct { - unsigned int CC_PF_DCC_COMPRESS_RATIO_8TO1 : 1; - unsigned int CC_PF_DCC_COMPRESS_RATIO_8TO2 : 1; - unsigned int CC_PF_DCC_COMPRESS_RATIO_8TO3 : 1; - unsigned int CC_PF_DCC_COMPRESS_RATIO_8TO4 : 1; - unsigned int CC_PF_DCC_COMPRESS_RATIO_8TO5 : 1; - unsigned int CC_PF_DCC_COMPRESS_RATIO_8TO6 : 1; - unsigned int CC_PF_DCC_COMPRESS_RATIO_8TO7 : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_17__SI__CI { - struct { - unsigned int CM_BUSY : 1; - unsigned int FC_BUSY : 1; - unsigned int CC_BUSY : 1; - unsigned int BB_BUSY : 1; - unsigned int MA_BUSY : 1; - unsigned int CORE_SCLK_VLD : 1; - unsigned int REG_SCLK1_VLD : 1; - unsigned int REG_SCLK0_VLD : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_17__VI { - struct { - unsigned int TILE_INTFC_BUSY : 1; - unsigned int MU_BUSY : 1; - unsigned int TQ_BUSY : 1; - unsigned int AC_BUSY : 1; - unsigned int CRW_BUSY : 1; - unsigned int CACHE_CTRL_BUSY : 1; - unsigned int MC_WR_PENDING : 1; - unsigned int FC_WR_PENDING : 1; - unsigned int FC_RD_PENDING : 1; - unsigned int EVICT_PENDING : 1; - unsigned int LAST_RD_ARB_WINNER : 1; - unsigned int MU_STATE : 8; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_18__SI__CI { - struct { - unsigned int NOT_USED : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_18__VI { - struct { - unsigned int TILE_RETIREMENT_BUSY : 1; - unsigned int FOP_BUSY : 1; - unsigned int CLEAR_BUSY : 1; - unsigned int LAT_BUSY : 1; - unsigned int CACHE_CTL_BUSY : 1; - unsigned int ADDR_BUSY : 1; - unsigned int MERGE_BUSY : 1; - unsigned int QUAD_BUSY : 1; - unsigned int TILE_BUSY : 1; - unsigned int DCC_BUSY : 1; - unsigned int DOC_BUSY : 1; - unsigned int DAG_BUSY : 1; - unsigned int DOC_STALL : 1; - unsigned int DOC_QT_CAM_FULL : 1; - unsigned int DOC_CL_CAM_FULL : 1; - unsigned int DOC_QUAD_PTR_FIFO_FULL : 1; - unsigned int DOC_SECTOR_MASK_FIFO_FULL : 1; - unsigned int DCS_READ_WINNER_LAST : 1; - unsigned int DCS_READ_EV_PENDING : 1; - unsigned int DCS_WRITE_CC_PENDING : 1; - unsigned int DCS_READ_CC_PENDING : 1; - unsigned int DCS_WRITE_MC_PENDING : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_2 { - struct { - unsigned int FC_CLEAR_QUAD_VALIDB_READYB__VI : 1; - unsigned int FC_QUAD_RESIDENCY_STALL__VI : 1; - unsigned int FC_CC_QUADFRAG_VALID_READY__VI : 1; - unsigned int FC_CC_QUADFRAG_VALID_READYB__VI : 1; - unsigned int FC_CC_QUADFRAG_VALIDB_READY__VI : 1; - unsigned int FC_CC_QUADFRAG_VALIDB_READYB__VI : 1; - unsigned int FOP_IN_VALID_READY__VI : 1; - unsigned int FOP_IN_VALID_READYB__VI : 1; - unsigned int FOP_IN_VALIDB_READY__VI : 1; - unsigned int FOP_IN_VALIDB_READYB__VI : 1; - unsigned int FOP_FMASK_RAW_STALL__VI : 1; - unsigned int FOP_FMASK_BYPASS_STALL__VI : 1; - unsigned int CC_IB_TB_FRAG_VALID_READY__VI : 1; - unsigned int CC_IB_TB_FRAG_VALID_READYB__VI : 1; - unsigned int CC_IB_TB_FRAG_VALIDB_READY__VI : 1; - unsigned int CC_IB_TB_FRAG_VALIDB_READYB__VI : 1; - unsigned int CC_IB_SR_FRAG_VALID_READY__VI : 1; - unsigned int CC_IB_SR_FRAG_VALID_READYB__VI : 1; - unsigned int CC_IB_SR_FRAG_VALIDB_READY__VI : 1; - unsigned int CC_IB_SR_FRAG_VALIDB_READYB__VI : 1; - unsigned int CC_RB_BC_EVENFRAG_VALID_READY__VI : 1; - unsigned int CC_RB_BC_EVENFRAG_VALID_READYB__VI : 1; - unsigned int CC_RB_BC_EVENFRAG_VALIDB_READY__VI : 1; - unsigned int CC_RB_BC_EVENFRAG_VALIDB_READYB__VI : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_HW_CONTROL { - struct { - unsigned int CM_CACHE_EVICT_POINT : 4; - unsigned int : 2; - unsigned int FC_CACHE_EVICT_POINT : 4; - unsigned int : 2; - unsigned int CC_CACHE_EVICT_POINT : 4; - unsigned int ALLOW_MRT_WITH_DUAL_SOURCE : 1; - unsigned int : 1; - unsigned int DISABLE_INTNORM_LE11BPC_CLAMPING__CI__VI : 1; - unsigned int FORCE_NEEDS_DST : 1; - unsigned int FORCE_ALWAYS_TOGGLE : 1; - unsigned int DISABLE_BLEND_OPT_RESULT_EQ_DEST__CI__VI : 1; - unsigned int DISABLE_FULL_WRITE_MASK : 1; - unsigned int DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG : 1; - unsigned int DISABLE_BLEND_OPT_DONT_RD_DST : 1; - unsigned int DISABLE_BLEND_OPT_BYPASS : 1; - unsigned int DISABLE_BLEND_OPT_DISCARD_PIXEL : 1; - unsigned int DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED : 1; - unsigned int PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT : 1; - unsigned int PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT : 1; - unsigned int DISABLE_CC_IB_SERIALIZER_STATE_OPT : 1; - unsigned int DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_HW_CONTROL_1 { - struct { - unsigned int CM_CACHE_NUM_TAGS : 5; - unsigned int FC_CACHE_NUM_TAGS : 6; - unsigned int CC_CACHE_NUM_TAGS : 6; - unsigned int CM_TILE_FIFO_DEPTH : 9; - unsigned int CHICKEN_BITS : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_HW_CONTROL_2__CI { - struct { - unsigned int CC_EVEN_ODD_FIFO_DEPTH : 8; - unsigned int FC_RDLAT_TILE_FIFO_DEPTH : 7; - unsigned int FC_RDLAT_QUAD_FIFO_DEPTH : 8; - unsigned int : 1; - unsigned int CHICKEN_BITS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_HW_CONTROL_2__VI { - struct { - unsigned int CC_EVEN_ODD_FIFO_DEPTH : 8; - unsigned int FC_RDLAT_TILE_FIFO_DEPTH : 7; - unsigned int FC_RDLAT_QUAD_FIFO_DEPTH : 8; - unsigned int : 1; - unsigned int DRR_ASSUMED_FIFO_DEPTH_DIV8 : 4; - unsigned int CHICKEN_BITS : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_HW_CONTROL_2__SI { - struct { - unsigned int CC_EVEN_ODD_FIFO_DEPTH : 8; - unsigned int FC_RDLAT_TILE_FIFO_DEPTH : 7; - unsigned int FC_RDLAT_QUAD_FIFO_DEPTH : 8; - unsigned int CHICKEN_BITS : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_HW_CONTROL_3__CI__VI { - struct { - unsigned int DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL : 1; - unsigned int RAM_ADDRESS_CONFLICTS_DISALLOWED__VI : 1; - unsigned int DISABLE_FAST_CLEAR_FETCH_OPT__VI : 1; - unsigned int DISABLE_QUAD_MARKER_DROP_STOP__VI : 1; - unsigned int DISABLE_OVERWRITE_COMBINER_CAM_CLR__VI : 1; - unsigned int DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__VI : 1; - unsigned int DISABLE_CC_CACHE_OVWR_KEY_MOD__VI : 1; - unsigned int DISABLE_CC_CACHE_PANIC_GATING__VI : 1; - unsigned int DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__VI : 1; - unsigned int SPLIT_ALL_FAST_MODE_TRANSFERS__VI : 1; - unsigned int DISABLE_SHADER_BLEND_OPTS__VI : 1; - unsigned int DISABLE_CMASK_LAST_QUAD_INSERTION__VI : 1; - unsigned int DISABLE_ROP3_FIXES_OF_BUG_511967__VI : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER0_SELECT0__SI { - struct { - unsigned int : 8; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 5; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 9; - unsigned int : 1; - unsigned int PERF_SEL3 : 9; - unsigned int : 5; - unsigned int PERF_MODE3 : 4; - unsigned int PERF_MODE2 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER0_SELECT1__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 2; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER0_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 1; - unsigned int PERF_SEL1 : 9; - unsigned int : 1; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER1_SELECT0__SI { - struct { - unsigned int : 8; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 5; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER1_SELECT1__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 2; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER1_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 19; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER2_SELECT0__SI { - struct { - unsigned int : 8; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 5; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER2_SELECT1__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 2; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER2_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 19; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER3_SELECT0__SI { - struct { - unsigned int : 8; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 5; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER3_SELECT1__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 2; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER3_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 19; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_PERFCOUNTER_FILTER__CI__VI { - struct { - unsigned int OP_FILTER_ENABLE : 1; - unsigned int OP_FILTER_SEL : 3; - unsigned int FORMAT_FILTER_ENABLE : 1; - unsigned int FORMAT_FILTER_SEL : 5; - unsigned int CLEAR_FILTER_ENABLE : 1; - unsigned int CLEAR_FILTER_SEL : 1; - unsigned int MRT_FILTER_ENABLE : 1; - unsigned int MRT_FILTER_SEL : 3; - unsigned int : 1; - unsigned int NUM_SAMPLES_FILTER_ENABLE : 1; - unsigned int NUM_SAMPLES_FILTER_SEL : 3; - unsigned int NUM_FRAGMENTS_FILTER_ENABLE : 1; - unsigned int NUM_FRAGMENTS_FILTER_SEL : 2; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_SHADER_MASK { - struct { - unsigned int OUTPUT0_ENABLE : 4; - unsigned int OUTPUT1_ENABLE : 4; - unsigned int OUTPUT2_ENABLE : 4; - unsigned int OUTPUT3_ENABLE : 4; - unsigned int OUTPUT4_ENABLE : 4; - unsigned int OUTPUT5_ENABLE : 4; - unsigned int OUTPUT6_ENABLE : 4; - unsigned int OUTPUT7_ENABLE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_TARGET_MASK { - struct { - unsigned int TARGET0_ENABLE : 4; - unsigned int TARGET1_ENABLE : 4; - unsigned int TARGET2_ENABLE : 4; - unsigned int TARGET3_ENABLE : 4; - unsigned int TARGET4_ENABLE : 4; - unsigned int TARGET5_ENABLE : 4; - unsigned int TARGET6_ENABLE : 4; - unsigned int TARGET7_ENABLE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_DRM_ID_STRAPS { - struct { - unsigned int : 1; - unsigned int : 3; - unsigned int DEVICE_ID : 16; - unsigned int MAJOR_REV_ID : 4; - unsigned int MINOR_REV_ID : 4; - unsigned int ATI_REV_ID : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_GC_EDC_CONFIG__CI__VI { - struct { - unsigned int : 1; - unsigned int DIS_EDC : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_GC_PRIM_CONFIG__CI__VI { - struct { - unsigned int : 1; - unsigned int : 15; - unsigned int INACTIVE_IA : 2; - unsigned int : 6; - unsigned int INACTIVE_VGT_PA : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_GC_SHADER_ARRAY_CONFIG__CI__VI { - struct { - unsigned int : 1; - unsigned int DPFP_RATE__SI__CI : 2; - unsigned int SQC_BALANCE_DISABLE__SI__CI : 1; - unsigned int HALF_LDS__SI__CI : 1; - unsigned int : 11; - unsigned int INACTIVE_CUS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_GC_SHADER_ARRAY_CONFIG__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 14; - unsigned int INACTIVE_CUS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_GIO_IOCCFG_FUSES__CI__VI { - struct { - unsigned int : 1; - unsigned int NB_REV_ID : 10; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_GIO_IOC_FUSES__CI__VI { - struct { - unsigned int : 1; - unsigned int IOC_FUSES : 5; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_MC_MAX_CHANNEL { - struct { - unsigned int : 1; - unsigned int NOOFCHAN : 4; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_RB_BACKEND_DISABLE { - struct { - unsigned int : 1; - unsigned int : 15; - unsigned int BACKEND_DISABLE : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_RB_DAISY_CHAIN { - struct { - unsigned int RB_0 : 4; - unsigned int RB_1 : 4; - unsigned int RB_2 : 4; - unsigned int RB_3 : 4; - unsigned int RB_4 : 4; - unsigned int RB_5 : 4; - unsigned int RB_6 : 4; - unsigned int RB_7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_RB_REDUNDANCY__CI__VI { - struct { - unsigned int : 1; - unsigned int : 7; - unsigned int FAILED_RB0 : 4; - unsigned int EN_REDUNDANCY0 : 1; - unsigned int : 3; - unsigned int FAILED_RB1 : 4; - unsigned int EN_REDUNDANCY1 : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_RB_REDUNDANCY__SI { - struct { - unsigned int : 1; - unsigned int : 15; - unsigned int FAILED_RB : 3; - unsigned int : 12; - unsigned int EN_REDUNDANCY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_RCU_FUSES__CI { - struct { - unsigned int : 1; - unsigned int GPU_DIS : 1; - unsigned int DEBUG_DISABLE : 1; - unsigned int : 1; - unsigned int EFUSE_RD_DISABLE : 1; - unsigned int CG_RST_GLB_REQ_DIS : 1; - unsigned int DRV_RST_MODE : 1; - unsigned int ROM_DIS : 1; - unsigned int JPC_REP_DISABLE : 1; - unsigned int RCU_BREAK_POINT1 : 1; - unsigned int RCU_BREAK_POINT2 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int PHY_FUSE_VALID : 1; - unsigned int SMU_IOC_MST_DISABLE : 1; - unsigned int FCH_LOCKOUT_ENABLE : 1; - unsigned int FCH_XFIRE_FILTER_ENABLE : 1; - unsigned int XFIRE_DISABLE : 1; - unsigned int SAMU_FUSE_DISABLE : 1; - unsigned int BIF_RST_POLLING_DISABLE : 1; - unsigned int : 1; - unsigned int MEM_HARDREP_EN : 1; - unsigned int PCIE_INIT_DISABLE : 1; - unsigned int DSMU_DISABLE : 1; - unsigned int RCU_SPARE : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_RCU_FUSES__VI { - struct { - unsigned int : 1; - unsigned int GPU_DIS : 1; - unsigned int DEBUG_DISABLE : 1; - unsigned int : 1; - unsigned int EFUSE_RD_DISABLE : 1; - unsigned int CG_RST_GLB_REQ_DIS : 1; - unsigned int DRV_RST_MODE : 1; - unsigned int ROM_DIS : 1; - unsigned int JPC_REP_DISABLE : 1; - unsigned int RCU_BREAK_POINT1 : 1; - unsigned int RCU_BREAK_POINT2 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SMU_IOC_MST_DISABLE : 1; - unsigned int FCH_LOCKOUT_ENABLE : 1; - unsigned int FCH_XFIRE_FILTER_ENABLE : 1; - unsigned int XFIRE_DISABLE : 1; - unsigned int SAMU_FUSE_DISABLE : 1; - unsigned int BIF_RST_POLLING_DISABLE : 1; - unsigned int : 1; - unsigned int MEM_HARDREP_EN : 1; - unsigned int PCIE_INIT_DISABLE : 1; - unsigned int DSMU_DISABLE : 1; - unsigned int WRP_FUSE_VALID : 1; - unsigned int PHY_FUSE_VALID : 1; - unsigned int RCU_SPARE : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_SCLK_VID_FUSES__CI__VI { - struct { - unsigned int SClkVid0 : 8; - unsigned int SClkVid1 : 8; - unsigned int SClkVid2 : 8; - unsigned int SClkVid3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_SMU_MISC_FUSES__CI__VI { - struct { - unsigned int : 1; - unsigned int IOMMU_V2_DISABLE : 1; - unsigned int MinSClkDid : 7; - unsigned int MISC_SPARE : 2; - unsigned int PostResetGnbClkDid : 7; - unsigned int L2IMU_tn2_dtc_half : 1; - unsigned int L2IMU_tn2_ptc_half : 1; - unsigned int L2IMU_tn2_itc_half : 1; - unsigned int L2IMU_tn2_pdc_half : 1; - unsigned int L2IMU_tn2_ptc_dis : 1; - unsigned int L2IMU_tn2_itc_dis : 1; - unsigned int : 3; - unsigned int VCE_DISABLE : 1; - unsigned int IOC_IOMMU_DISABLE : 1; - unsigned int GNB_SPARE : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_SMU_TST_EFUSE1_MISC__CI__VI { - struct { - unsigned int : 1; - unsigned int RF_RM_6_2 : 5; - unsigned int RME : 1; - unsigned int MBIST_DISABLE : 1; - unsigned int HARD_REPAIR_DISABLE : 1; - unsigned int SOFT_REPAIR_DISABLE : 1; - unsigned int GPU_DIS : 1; - unsigned int SMS_PWRDWN_DISABLE : 1; - unsigned int CRBBMP1500_DISA : 1; - unsigned int CRBBMP1500_DISB : 1; - unsigned int RM_RF8 : 1; - unsigned int : 7; - unsigned int DFT_SPARE1 : 1; - unsigned int DFT_SPARE2 : 1; - unsigned int DFT_SPARE3 : 1; - unsigned int VCE_DISABLE : 1; - unsigned int DCE_SCAN_DISABLE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_SQC_BANK_DISABLE { - struct { - unsigned int : 1; - unsigned int : 15; - unsigned int SQC0_BANK_DISABLE : 4; - unsigned int SQC1_BANK_DISABLE : 4; - unsigned int SQC2_BANK_DISABLE__CI__VI : 4; - unsigned int SQC3_BANK_DISABLE__CI__VI : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_SYS_RB_BACKEND_DISABLE { - struct { - unsigned int : 1; - unsigned int : 15; - unsigned int BACKEND_DISABLE : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_SYS_RB_REDUNDANCY__SI__CI { - struct { - unsigned int : 1; - unsigned int : 15; - unsigned int FAILED_RB : 3; - unsigned int : 12; - unsigned int EN_REDUNDANCY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_SYS_RB_REDUNDANCY__VI { - struct { - unsigned int : 1; - unsigned int : 7; - unsigned int FAILED_RB0 : 4; - unsigned int EN_REDUNDANCY0 : 1; - unsigned int : 3; - unsigned int FAILED_RB1 : 4; - unsigned int EN_REDUNDANCY1 : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_THM_STRAPS0__CI__VI { - struct { - unsigned int : 1; - unsigned int TMON0_BGADJ : 8; - unsigned int TMON1_BGADJ : 8; - unsigned int TMON_CMON_FUSE_SEL : 1; - unsigned int NUM_ACQ : 3; - unsigned int TMON_CLK_SEL : 3; - unsigned int TMON_CONFIG_SOURCE : 1; - unsigned int CTF_DISABLE : 1; - unsigned int TMON0_DISABLE : 1; - unsigned int TMON1_DISABLE : 1; - unsigned int TMON2_DISABLE : 1; - unsigned int TMON3_DISABLE : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_TST_ID_STRAPS__CI__VI { - struct { - unsigned int : 1; - unsigned int : 3; - unsigned int DEVICE_ID : 16; - unsigned int MAJOR_REV_ID : 4; - unsigned int MINOR_REV_ID : 4; - unsigned int ATI_REV_ID__VI : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU0_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU0_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU0_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU0_TA_SQC_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQC : 7; - unsigned int SQC_OVERRIDE : 1; - unsigned int SQC_BUSY_OVERRIDE : 2; - unsigned int SQC_LS_OVERRIDE : 1; - unsigned int SQC_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU0_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU10_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU10_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU10_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU10_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU10_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU11_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU11_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU11_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU11_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU11_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU12_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU12_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU12_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU12_TA_SQC_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQC : 7; - unsigned int SQC_OVERRIDE : 1; - unsigned int SQC_BUSY_OVERRIDE : 2; - unsigned int SQC_LS_OVERRIDE : 1; - unsigned int SQC_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU12_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU13_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU13_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU13_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU13_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU13_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU14_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU14_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU14_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU14_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU14_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU15_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU15_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU15_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU15_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU15_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU1_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU1_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU1_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU1_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU1_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU2_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU2_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU2_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU2_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU2_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU3_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU3_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU3_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU3_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU3_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU4_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU4_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU4_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU4_TA_SQC_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQC : 7; - unsigned int SQC_OVERRIDE : 1; - unsigned int SQC_BUSY_OVERRIDE : 2; - unsigned int SQC_LS_OVERRIDE : 1; - unsigned int SQC_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU4_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU5_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU5_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU5_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU5_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU5_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU6_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU6_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU6_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU6_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU6_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU7_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU7_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU7_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU7_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU7_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU8_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU8_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU8_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU8_TA_SQC_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQC : 7; - unsigned int SQC_OVERRIDE : 1; - unsigned int SQC_BUSY_OVERRIDE : 2; - unsigned int SQC_LS_OVERRIDE : 1; - unsigned int SQC_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU8_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU9_LDS_SQ_CTRL_REG__CI__VI { - struct { - unsigned int LDS : 7; - unsigned int LDS_OVERRIDE : 1; - unsigned int LDS_BUSY_OVERRIDE : 2; - unsigned int LDS_LS_OVERRIDE : 1; - unsigned int LDS_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SQ : 7; - unsigned int SQ_OVERRIDE : 1; - unsigned int SQ_BUSY_OVERRIDE : 2; - unsigned int SQ_LS_OVERRIDE : 1; - unsigned int SQ_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU9_SP0_CTRL_REG__CI__VI { - struct { - unsigned int SP00 : 7; - unsigned int SP00_OVERRIDE : 1; - unsigned int SP00_BUSY_OVERRIDE : 2; - unsigned int SP00_LS_OVERRIDE : 1; - unsigned int SP00_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP01 : 7; - unsigned int SP01_OVERRIDE : 1; - unsigned int SP01_BUSY_OVERRIDE : 2; - unsigned int SP01_LS_OVERRIDE : 1; - unsigned int SP01_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU9_SP1_CTRL_REG__CI__VI { - struct { - unsigned int SP10 : 7; - unsigned int SP10_OVERRIDE : 1; - unsigned int SP10_BUSY_OVERRIDE : 2; - unsigned int SP10_LS_OVERRIDE : 1; - unsigned int SP10_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int SP11 : 7; - unsigned int SP11_OVERRIDE : 1; - unsigned int SP11_BUSY_OVERRIDE : 2; - unsigned int SP11_LS_OVERRIDE : 1; - unsigned int SP11_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU9_TA_CTRL_REG__CI__VI { - struct { - unsigned int TA : 7; - unsigned int TA_OVERRIDE : 1; - unsigned int TA_BUSY_OVERRIDE : 2; - unsigned int TA_LS_OVERRIDE : 1; - unsigned int TA_SIMDBUSY_OVERRIDE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_CU9_TD_TCP_CTRL_REG__CI__VI { - struct { - unsigned int TD : 7; - unsigned int TD_OVERRIDE : 1; - unsigned int TD_BUSY_OVERRIDE : 2; - unsigned int TD_LS_OVERRIDE : 1; - unsigned int TD_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - unsigned int TCP : 7; - unsigned int TCP_OVERRIDE : 1; - unsigned int TCP_BUSY_OVERRIDE : 2; - unsigned int TCP_LS_OVERRIDE : 1; - unsigned int TCP_SIMDBUSY_OVERRIDE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_RD_CTRL_REG { - struct { - unsigned int ROW_MUX_SEL : 5; - unsigned int : 3; - unsigned int REG_MUX_SEL : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_RD_REG { - struct { - unsigned int READ_DATA : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_SM_CTRL_REG { - struct { - unsigned int ON_SEQ_DELAY : 4; - unsigned int OFF_SEQ_DELAY : 8; - unsigned int MGCG_ENABLED : 1; - unsigned int : 3; - unsigned int BASE_MODE : 1; - unsigned int SM_MODE : 3; - unsigned int SM_MODE_ENABLE : 1; - unsigned int OVERRIDE : 1; - unsigned int LS_OVERRIDE : 1; - unsigned int ON_MONITOR_ADD_EN : 1; - unsigned int ON_MONITOR_ADD : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_TCC_DISABLE { - struct { - unsigned int : 1; - unsigned int : 15; - unsigned int TCC_DISABLE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTS_USER_TCC_DISABLE { - struct { - unsigned int : 16; - unsigned int TCC_DISABLE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_BCI_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int RESERVED : 12; - unsigned int CORE6_OVERRIDE : 1; - unsigned int CORE5_OVERRIDE : 1; - unsigned int CORE4_OVERRIDE : 1; - unsigned int CORE3_OVERRIDE : 1; - unsigned int CORE2_OVERRIDE : 1; - unsigned int CORE1_OVERRIDE : 1; - unsigned int CORE0_OVERRIDE : 1; - unsigned int REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_CPC_CLK_CTRL__CI__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 17; - unsigned int SOFT_OVERRIDE_PERFMON__VI : 1; - unsigned int SOFT_OVERRIDE_DYN : 1; - unsigned int SOFT_OVERRIDE_REG : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_CPF_CLK_CTRL__CI__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 17; - unsigned int SOFT_OVERRIDE_PERFMON__VI : 1; - unsigned int SOFT_OVERRIDE_DYN : 1; - unsigned int SOFT_OVERRIDE_REG : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_CP_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 17; - unsigned int SOFT_OVERRIDE_PERFMON__VI : 1; - unsigned int SOFT_OVERRIDE_DYN : 1; - unsigned int SOFT_OVERRIDE_REG : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_GDS_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_IA_CLK_CTRL__CI__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int PERF_ENABLE : 1; - unsigned int DBG_ENABLE : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int CORE_OVERRIDE : 1; - unsigned int REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_IA_CLK_CTRL__SI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int PERF_ENABLE : 1; - unsigned int DBG_ENABLE : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int : 1; - unsigned int CORE_OVERRIDE : 1; - unsigned int : 1; - unsigned int REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_PA_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SU_CLK_OVERRIDE : 1; - unsigned int CL_CLK_OVERRIDE : 1; - unsigned int REG_CLK_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_PC_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 6; - unsigned int GRP5_CG_OFF_HYST : 6; - unsigned int GRP5_CG_OVERRIDE : 1; - unsigned int BACK_CLK_ON_OVERRIDE : 1; - unsigned int FRONT_CLK_ON_OVERRIDE : 1; - unsigned int CORE3_OVERRIDE : 1; - unsigned int CORE2_OVERRIDE : 1; - unsigned int CORE1_OVERRIDE : 1; - unsigned int CORE0_OVERRIDE : 1; - unsigned int REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_RLC_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 18; - unsigned int SOFT_OVERRIDE_DYN : 1; - unsigned int SOFT_OVERRIDE_REG : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_ROM_CLK_CTRL0 { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 18; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SC_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SPI_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 6; - unsigned int GRP5_CG_OFF_HYST : 6; - unsigned int GRP5_CG_OVERRIDE : 1; - unsigned int : 1; - unsigned int ALL_CLK_ON_OVERRIDE : 1; - unsigned int GRP3_OVERRIDE : 1; - unsigned int GRP2_OVERRIDE : 1; - unsigned int GRP1_OVERRIDE : 1; - unsigned int GRP0_OVERRIDE : 1; - unsigned int REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SQG_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 16; - unsigned int TTRACE_OVERRIDE__VI : 1; - unsigned int PERFMON_OVERRIDE__VI : 1; - unsigned int CORE_OVERRIDE : 1; - unsigned int REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SQ_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 17; - unsigned int PERFMON_OVERRIDE__VI : 1; - unsigned int CORE_OVERRIDE : 1; - unsigned int REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SX_CLK_CTRL0 { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int RESERVED : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SX_CLK_CTRL1__SI__CI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int RESERVED : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SX_CLK_CTRL1__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int RESERVED : 12; - unsigned int DBG_EN : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SX_CLK_CTRL2__SI__CI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int RESERVED : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SX_CLK_CTRL2__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int RESERVED : 12; - unsigned int DBG_EN : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SX_CLK_CTRL3__SI__CI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int RESERVED : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SX_CLK_CTRL3__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int RESERVED : 12; - unsigned int DBG_EN : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SX_CLK_CTRL4__SI__CI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int RESERVED : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_SX_CLK_CTRL4__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int RESERVED : 12; - unsigned int DBG_EN : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_TCI_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_TCP_CLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_VGT_CLK_CTRL__SI__CI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int PERF_ENABLE : 1; - unsigned int DBG_ENABLE : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int GS_OVERRIDE : 1; - unsigned int CORE_OVERRIDE : 1; - unsigned int REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_VGT_CLK_CTRL__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int PERF_ENABLE : 1; - unsigned int DBG_ENABLE : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int TESS_OVERRIDE : 1; - unsigned int GS_OVERRIDE : 1; - unsigned int CORE_OVERRIDE : 1; - unsigned int REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_WD_CLK_CTRL__CI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int PERF_ENABLE : 1; - unsigned int DBG_ENABLE : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int ADC_OVERRIDE : 1; - unsigned int CORE_OVERRIDE : 1; - unsigned int RBIU_INPUT_OVERRIDE : 1; - unsigned int REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CGTT_WD_CLK_CTRL__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int PERF_ENABLE : 1; - unsigned int DBG_ENABLE : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int TESS_OVERRIDE : 1; - unsigned int CORE_OVERRIDE : 1; - unsigned int RBIU_INPUT_OVERRIDE : 1; - unsigned int REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_ACLK_CNTL__CI__VI { - struct { - unsigned int ACLK_DIVIDER : 7; - unsigned int : 1; - unsigned int ACLK_DIR_CNTL_EN : 1; - unsigned int ACLK_DIR_CNTL_TOG : 1; - unsigned int ACLK_DIR_CNTL_DIVIDER : 7; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_ACPI_CNTL__CI__VI { - struct { - unsigned int SCLK_ACPI_DIV : 7; - unsigned int SCLK_CHANGE_SKIP : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_CLKPIN_CNTL_2__CI__VI { - struct { - unsigned int ENABLE_XCLK : 1; - unsigned int : 2; - unsigned int FORCE_BIF_REFCLK_EN : 1; - unsigned int : 4; - unsigned int MUX_TCLK_TO_XCLK : 1; - unsigned int : 5; - unsigned int XO_IN_OSCIN_EN : 1; - unsigned int XO_IN_ICORE_CLK_OE : 1; - unsigned int XO_IN_CML_RXEN : 1; - unsigned int XO_IN_BIDIR_CML_OE : 1; - unsigned int XO_IN2_OSCIN_EN : 1; - unsigned int XO_IN2_ICORE_CLK_OE : 1; - unsigned int XO_IN2_CML_RXEN : 1; - unsigned int XO_IN2_BIDIR_CML_OE : 1; - unsigned int CML_CTRL : 2; - unsigned int CLK_SPARE : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_CLKPIN_CNTL__CI__VI { - struct { - unsigned int : 1; - unsigned int XTALIN_DIVIDE : 1; - unsigned int BCLK_AS_XCLK : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_CLKPIN_CNTL__SI { - struct { - unsigned int : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int XTALIN_DIVIDE : 1; - unsigned int : 3; - unsigned int BCLK_AS_XCLK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_DCLK_CNTL__CI__VI { - struct { - unsigned int DCLK_DIVIDER : 7; - unsigned int : 1; - unsigned int DCLK_DIR_CNTL_EN : 1; - unsigned int DCLK_DIR_CNTL_TOG : 1; - unsigned int DCLK_DIR_CNTL_DIVIDER : 7; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_DCLK_STATUS__CI__VI { - struct { - unsigned int DCLK_STATUS : 1; - unsigned int DCLK_DIR_CNTL_DONETOG : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_DISPLAY_GAP_CNTL2__CI__VI { - struct { - unsigned int VBI_PREDICTION : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_DISPLAY_GAP_CNTL__CI__VI { - struct { - unsigned int DISP_GAP : 2; - unsigned int : 2; - unsigned int VBI_TIMER_COUNT : 14; - unsigned int : 2; - unsigned int VBI_TIMER_UNIT : 3; - unsigned int : 1; - unsigned int DISP_GAP_MCHG : 2; - unsigned int : 2; - unsigned int VBI_TIMER_DISABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_DISPLAY_GAP_CNTL__SI { - struct { - unsigned int : 2; - unsigned int : 2; - unsigned int VBI_TIMER_COUNT : 14; - unsigned int : 2; - unsigned int VBI_TIMER_UNIT : 3; - unsigned int : 1; - unsigned int : 2; - unsigned int : 2; - unsigned int VBI_TIMER_DISABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_ECLK_CNTL__CI__VI { - struct { - unsigned int ECLK_DIVIDER : 7; - unsigned int : 1; - unsigned int ECLK_DIR_CNTL_EN : 1; - unsigned int ECLK_DIR_CNTL_TOG : 1; - unsigned int ECLK_DIR_CNTL_DIVIDER : 7; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_ECLK_STATUS__CI__VI { - struct { - unsigned int ECLK_STATUS : 1; - unsigned int ECLK_DIR_CNTL_DONETOG : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FDO_CTRL0 { - struct { - unsigned int FDO_STATIC_DUTY : 8; - unsigned int FAN_SPINUP_DUTY : 8; - unsigned int FDO_PWM_MANUAL : 1; - unsigned int FDO_PWM_HYSTER : 6; - unsigned int FDO_PWM_RAMP_EN : 1; - unsigned int FDO_PWM_RAMP : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FDO_CTRL1 { - struct { - unsigned int FMAX_DUTY100 : 8; - unsigned int FMIN_DUTY : 8; - unsigned int M : 8; - unsigned int RESERVED : 6; - unsigned int FDO_PWRDNB : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FDO_CTRL2 { - struct { - unsigned int TMIN : 8; - unsigned int FAN_SPINUP_TIME : 3; - unsigned int FDO_PWM_MODE : 3; - unsigned int TMIN_HYSTER : 3; - unsigned int TMAX : 8; - unsigned int TACH_PWM_RESP_RATE : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FPS_CNT__CI { - struct { - unsigned int FPS_CNT : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FPS_CNT__VI { - struct { - unsigned int FPS_CNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FREQ_TRAN_VOTING_0__CI__VI { - struct { - unsigned int BIF_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int HDP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ROM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IH_SEM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int PDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DRM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IDCT_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ACP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int UVD_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int VCE_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DC_AZ_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SAM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int AVP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_0_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_1_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_2_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_3_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_4_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_5_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_6_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_7_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_8_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_9_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int RLC_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FREQ_TRAN_VOTING_1__CI__VI { - struct { - unsigned int BIF_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int HDP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ROM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IH_SEM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int PDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DRM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IDCT_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ACP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int UVD_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int VCE_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DC_AZ_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SAM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int AVP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_0_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_1_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_2_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_3_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_4_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_5_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_6_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_7_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_8_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_9_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int RLC_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FREQ_TRAN_VOTING_2__CI__VI { - struct { - unsigned int BIF_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int HDP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ROM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IH_SEM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int PDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DRM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IDCT_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ACP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int UVD_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int VCE_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DC_AZ_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SAM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int AVP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_0_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_1_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_2_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_3_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_4_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_5_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_6_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_7_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_8_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_9_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int RLC_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FREQ_TRAN_VOTING_3__CI__VI { - struct { - unsigned int BIF_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int HDP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ROM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IH_SEM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int PDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DRM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IDCT_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ACP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int UVD_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int VCE_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DC_AZ_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SAM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int AVP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_0_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_1_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_2_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_3_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_4_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_5_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_6_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_7_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_8_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_9_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int RLC_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FREQ_TRAN_VOTING_4__CI__VI { - struct { - unsigned int BIF_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int HDP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ROM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IH_SEM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int PDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DRM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IDCT_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ACP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int UVD_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int VCE_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DC_AZ_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SAM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int AVP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_0_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_1_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_2_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_3_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_4_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_5_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_6_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_7_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_8_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_9_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int RLC_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FREQ_TRAN_VOTING_5__CI__VI { - struct { - unsigned int BIF_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int HDP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ROM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IH_SEM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int PDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DRM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IDCT_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ACP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int UVD_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int VCE_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DC_AZ_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SAM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int AVP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_0_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_1_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_2_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_3_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_4_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_5_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_6_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_7_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_8_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_9_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int RLC_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FREQ_TRAN_VOTING_6__CI__VI { - struct { - unsigned int BIF_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int HDP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ROM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IH_SEM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int PDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DRM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IDCT_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ACP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int UVD_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int VCE_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DC_AZ_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SAM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int AVP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_0_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_1_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_2_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_3_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_4_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_5_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_6_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_7_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_8_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_9_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int RLC_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FREQ_TRAN_VOTING_7__CI__VI { - struct { - unsigned int BIF_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int HDP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ROM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IH_SEM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int PDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DRM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int IDCT_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int ACP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SDMA_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int UVD_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int VCE_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int DC_AZ_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int SAM_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int AVP_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_0_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_1_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_2_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_3_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_4_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_5_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_6_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_7_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_8_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_9_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_10_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_11_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_12_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_13_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_14_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int GRBM_15_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int RLC_FREQ_THROTTLING_VOTE_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_FREQ_TRAN_VOTING__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_MULT_THERMAL_CTRL__SI__CI { - struct { - unsigned int TS_FILTER : 4; - unsigned int UNUSED : 4; - unsigned int : 1; - unsigned int THERMAL_RANGE_RST : 1; - unsigned int : 10; - unsigned int TEMP_SEL : 8; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_MULT_THERMAL_CTRL__VI { - struct { - unsigned int TS_FILTER : 4; - unsigned int UNUSED : 5; - unsigned int THERMAL_RANGE_RST : 1; - unsigned int : 10; - unsigned int TEMP_SEL : 8; - unsigned int THM_READY_CLEAR : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_MULT_THERMAL_STATUS { - struct { - unsigned int ASIC_MAX_TEMP : 9; - unsigned int CTF_TEMP : 9; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_FUNC_CNTL__SI__CI { - struct { - unsigned int SPLL_RESET : 1; - unsigned int : 1; - unsigned int SPLL_DIVEN : 1; - unsigned int SPLL_BYPASS_EN : 1; - unsigned int SPLL_REF_DIV : 6; - unsigned int : 10; - unsigned int SPLL_PDIV_A : 7; - unsigned int : 1; - unsigned int SPLL_BGADJ : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_FUNC_CNTL__VI { - struct { - unsigned int SPLL_RESET : 1; - unsigned int SPLL_PWRON : 1; - unsigned int SPLL_DIVEN : 1; - unsigned int SPLL_BYPASS_EN : 1; - unsigned int SPLL_BYPASS_THRU_DFS : 1; - unsigned int SPLL_REF_DIV : 6; - unsigned int SPLL_PDIV_A_UPDATE : 1; - unsigned int SPLL_PDIV_A_EN : 1; - unsigned int SPLL_BG_PWRON : 1; - unsigned int SPLL_BGADJ : 4; - unsigned int SPLL_PDIV_A : 7; - unsigned int SPLL_REG_BIAS : 3; - unsigned int SPLL_OTEST_LOCK_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_FUNC_CNTL_2 { - struct { - unsigned int SCLK_MUX_SEL : 9; - unsigned int : 2; - unsigned int SPLL_CTLREQ : 1; - unsigned int : 10; - unsigned int SPLL_BYPASS_CHG__VI : 1; - unsigned int SPLL_CTLREQ_CHG : 1; - unsigned int SPLL_RESET_CHG : 1; - unsigned int SPLL_BABY_STEP_CHG : 1; - unsigned int SCLK_MUX_UPDATE : 1; - unsigned int SPLL_UNLOCK_CLEAR : 1; - unsigned int SPLL_CLKF_UPDATE : 1; - unsigned int : 1; - unsigned int SPLL_TEST_UNLOCK_CLR__VI : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_FUNC_CNTL_3 { - struct { - unsigned int SPLL_FB_DIV : 26; - unsigned int : 2; - unsigned int SPLL_DITHEN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_FUNC_CNTL_4__SI__CI { - struct { - unsigned int SPLL_SCLK_TEST_SEL : 3; - unsigned int : 1; - unsigned int SPLL_SCLK_EXT_SEL : 2; - unsigned int SPLL_SCLK_EN : 2; - unsigned int SPLL_SPARE : 10; - unsigned int : 3; - unsigned int TEST_FRAC_BYPASS : 1; - unsigned int : 1; - unsigned int SPLL_ILOCK : 1; - unsigned int SPLL_FBCLK_SEL : 1; - unsigned int SPLL_VCTRLADC_EN : 1; - unsigned int SPLL_SCLK_EXT : 2; - unsigned int SPLL_SPARE_EXT : 3; - unsigned int SPLL_VTOI_BIAS_CNTL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_FUNC_CNTL_4__VI { - struct { - unsigned int SPLL_SCLK_TEST_SEL : 4; - unsigned int : 1; - unsigned int SPLL_SCLK_EXT_SEL : 2; - unsigned int SPLL_SCLK_EN : 2; - unsigned int SPLL_SSAMP_EN : 1; - unsigned int SPLL_SPARE : 9; - unsigned int : 2; - unsigned int TEST_FRAC_BYPASS : 1; - unsigned int : 1; - unsigned int SPLL_ILOCK : 1; - unsigned int SPLL_FBCLK_SEL : 1; - unsigned int SPLL_VCTRLADC_EN : 1; - unsigned int SPLL_SCLK_EXT : 2; - unsigned int SPLL_SPARE_EXT : 3; - unsigned int SPLL_VTOI_BIAS_CNTL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_FUNC_CNTL_5__SI__CI { - struct { - unsigned int FBDIV_SSC_BYPASS : 1; - unsigned int RISEFBVCO_EN : 1; - unsigned int PFD_RESET_CNTRL : 2; - unsigned int RESET_TIMER : 2; - unsigned int FAST_LOCK_CNTRL : 2; - unsigned int FAST_LOCK_EN : 1; - unsigned int RESET_ANTI_MUX : 1; - unsigned int : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_FUNC_CNTL_5__VI { - struct { - unsigned int FBDIV_SSC_BYPASS : 1; - unsigned int RISEFBVCO_EN : 1; - unsigned int PFD_RESET_CNTRL : 2; - unsigned int RESET_TIMER : 2; - unsigned int FAST_LOCK_CNTRL : 2; - unsigned int FAST_LOCK_EN : 1; - unsigned int RESET_ANTI_MUX : 1; - unsigned int REFCLK_BYPASS_EN : 1; - unsigned int PLLBYPASS : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_FUNC_CNTL_6__CI__VI { - struct { - unsigned int SCLKMUX0_CLKOFF_CNT : 8; - unsigned int SCLKMUX1_CLKOFF_CNT : 8; - unsigned int SPLL_VCTL_EN__VI : 1; - unsigned int SPLL_VCTL_CNTRL_IN__VI : 4; - unsigned int SPLL_VCTL_CNTRL_OUT__VI : 4; - unsigned int SPLL_LF_CNTR__VI : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_SPREAD_SPECTRUM { - struct { - unsigned int SSEN : 2; - unsigned int : 2; - unsigned int CLKS : 12; - unsigned int : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_SPREAD_SPECTRUM_2 { - struct { - unsigned int CLKV : 26; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_STATIC_SCREEN_PARAMETER { - struct { - unsigned int STATIC_SCREEN_THRESHOLD : 16; - unsigned int STATIC_SCREEN_THRESHOLD_UNIT : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_TACH_CTRL { - struct { - unsigned int EDGE_PER_REV : 3; - unsigned int TARGET_PERIOD : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_TACH_STATUS { - struct { - unsigned int TACH_PERIOD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_THERMAL_CTRL { - struct { - unsigned int DPM_EVENT_SRC : 3; - unsigned int THERM_INC_CLK : 1; - unsigned int SPARE : 10; - unsigned int DIG_THERM_DPM : 8; - unsigned int RESERVED : 3; - unsigned int CTF_PAD_POLARITY : 1; - unsigned int CTF_PAD_EN : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_THERMAL_INT { - struct { - unsigned int DIG_THERM_CTF : 8; - unsigned int DIG_THERM_INTH : 8; - unsigned int DIG_THERM_INTL : 8; - unsigned int THERM_INT_MASK : 4; - unsigned int : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_THERMAL_INT_CTRL__CI__VI { - struct { - unsigned int DIG_THERM_INTH : 8; - unsigned int DIG_THERM_INTL : 8; - unsigned int GNB_TEMP_THRESHOLD : 8; - unsigned int THERM_INTH_MASK : 1; - unsigned int THERM_INTL_MASK : 1; - unsigned int THERM_TRIGGER_MASK : 1; - unsigned int THERM_TRIGGER_CNB_MASK : 1; - unsigned int THERM_GNB_HW_ENA : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_THERMAL_INT_ENA__CI__VI { - struct { - unsigned int THERM_INTH_SET : 1; - unsigned int THERM_INTL_SET : 1; - unsigned int THERM_TRIGGER_SET : 1; - unsigned int THERM_INTH_CLR : 1; - unsigned int THERM_INTL_CLR : 1; - unsigned int THERM_TRIGGER_CLR : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_THERMAL_INT_STATUS__CI__VI { - struct { - unsigned int THERM_INTH_DETECT : 1; - unsigned int THERM_INTL_DETECT : 1; - unsigned int THERM_TRIGGER_DETECT : 1; - unsigned int THERM_TRIGGER_CNB_DETECT : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_THERMAL_STATUS { - struct { - unsigned int SPARE : 9; - unsigned int FDO_PWM_DUTY : 8; - unsigned int THERM_ALERT : 1; - unsigned int GEN_STATUS : 4; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_ULV_PARAMETER { - struct { - unsigned int ULV_THRESHOLD : 16; - unsigned int ULV_THRESHOLD_UNIT : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_VCLK_CNTL__CI__VI { - struct { - unsigned int VCLK_DIVIDER : 7; - unsigned int : 1; - unsigned int VCLK_DIR_CNTL_EN : 1; - unsigned int VCLK_DIR_CNTL_TOG : 1; - unsigned int VCLK_DIR_CNTL_DIVIDER : 7; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_VCLK_STATUS__CI__VI { - struct { - unsigned int VCLK_STATUS : 1; - unsigned int VCLK_DIR_CNTL_DONETOG : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CHUB_ATC_PERFCOUNTER0_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CHUB_ATC_PERFCOUNTER1_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CHUB_ATC_PERFCOUNTER_HI__CI__VI { - struct { - unsigned int COUNTER_HI : 16; - unsigned int COMPARE_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CHUB_ATC_PERFCOUNTER_LO__CI__VI { - struct { - unsigned int COUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CI__VI { - struct { - unsigned int PERF_COUNTER_SELECT : 4; - unsigned int : 4; - unsigned int START_TRIGGER : 8; - unsigned int STOP_TRIGGER : 8; - unsigned int ENABLE_ANY : 1; - unsigned int CLEAR_ALL : 1; - unsigned int STOP_ALL_ON_SATURATE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_BM { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_CD0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_CD1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_CD2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_CD3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_CK0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_CK1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_CK2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_CK3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_K0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_K1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_K2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_K3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_OFFSET { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_STATUS { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_BM { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_CD0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_CD1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_CD2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_CD3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_CK0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_CK1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_CK2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_CK3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_K0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_K1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_K2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_K3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_OFFSET { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_PORT_STATUS { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_BM { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_CD0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_CD1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_CD2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_CD3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_CK0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_CK1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_CK2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_CK3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_K0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_K1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_K2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_K3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_OFFSET { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_STATUS { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG00 { - struct { - unsigned int ALWAYS_ZERO : 8; - unsigned int clip_ga_bc_fifo_write : 1; - unsigned int su_clip_baryc_free : 2; - unsigned int clip_to_ga_fifo_write : 1; - unsigned int clip_to_ga_fifo_full : 1; - unsigned int primic_to_clprim_fifo_empty : 1; - unsigned int primic_to_clprim_fifo_full : 1; - unsigned int clip_to_outsm_fifo_empty : 1; - unsigned int clip_to_outsm_fifo_full : 1; - unsigned int vgt_to_clipp_fifo_empty : 1; - unsigned int vgt_to_clipp_fifo_full : 1; - unsigned int vgt_to_clips_fifo_empty : 1; - unsigned int vgt_to_clips_fifo_full : 1; - unsigned int clipcode_fifo_fifo_empty : 1; - unsigned int clipcode_fifo_full : 1; - unsigned int vte_out_clip_fifo_fifo_empty : 1; - unsigned int vte_out_clip_fifo_fifo_full : 1; - unsigned int vte_out_orig_fifo_fifo_empty : 1; - unsigned int vte_out_orig_fifo_fifo_full : 1; - unsigned int ccgen_to_clipcc_fifo_empty : 1; - unsigned int ccgen_to_clipcc_fifo_full : 1; - unsigned int clip_to_outsm_fifo_write : 1; - unsigned int vte_out_orig_fifo_fifo_write : 1; - unsigned int vgt_to_clipp_fifo_write : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG01 { - struct { - unsigned int ALWAYS_ZERO : 8; - unsigned int clip_extra_bc_valid : 3; - unsigned int clip_vert_vte_valid : 3; - unsigned int clip_to_outsm_vertex_deallocate : 3; - unsigned int clip_to_outsm_deallocate_slot : 3; - unsigned int clip_to_outsm_null_primitive : 1; - unsigned int vte_positions_vte_clip_vte_naninf_kill_2 : 1; - unsigned int vte_positions_vte_clip_vte_naninf_kill_1 : 1; - unsigned int vte_positions_vte_clip_vte_naninf_kill_0 : 1; - unsigned int vte_out_clip_rd_extra_bc_valid : 1; - unsigned int vte_out_clip_rd_vte_naninf_kill : 1; - unsigned int vte_out_clip_rd_vertex_store_indx : 2; - unsigned int clip_ga_bc_fifo_write : 1; - unsigned int clip_to_ga_fifo_write : 1; - unsigned int vte_out_clip_fifo_fifo_advanceread : 1; - unsigned int vte_out_clip_fifo_fifo_empty : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG02 { - struct { - unsigned int clip_extra_bc_valid : 3; - unsigned int clip_vert_vte_valid : 3; - unsigned int clip_to_outsm_clip_seq_indx : 2; - unsigned int clip_to_outsm_vertex_store_indx_2 : 4; - unsigned int clip_to_outsm_vertex_store_indx_1 : 4; - unsigned int clip_to_outsm_vertex_store_indx_0 : 4; - unsigned int clip_to_clipga_extra_bc_coords : 1; - unsigned int clip_to_clipga_vte_naninf_kill : 1; - unsigned int clip_to_outsm_end_of_packet : 1; - unsigned int clip_to_outsm_first_prim_of_slot : 1; - unsigned int clip_to_outsm_clipped_prim : 1; - unsigned int clip_to_outsm_null_primitive : 1; - unsigned int clip_ga_bc_fifo_full : 1; - unsigned int clip_to_ga_fifo_full : 1; - unsigned int clip_ga_bc_fifo_write : 1; - unsigned int clip_to_ga_fifo_write : 1; - unsigned int clip_to_outsm_fifo_advanceread : 1; - unsigned int clip_to_outsm_fifo_empty : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG03 { - struct { - unsigned int clipsm0_clprim_to_clip_clip_code_or : 14; - unsigned int clipsm0_clprim_to_clip_event_id : 6; - unsigned int clipsm0_clprim_to_clip_state_var_indx : 3; - unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; - unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; - unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; - unsigned int clipsm0_clprim_to_clip_end_of_packet : 1; - unsigned int clipsm0_clprim_to_clip_event : 1; - unsigned int clipsm0_clprim_to_clip_null_primitive : 1; - unsigned int clipsm0_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG04 { - struct { - unsigned int : 1; - unsigned int clipsm0_clprim_to_clip_param_cache_indx_0 : 10; - unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 6; - unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 6; - unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 6; - unsigned int clipsm0_clprim_to_clip_event : 1; - unsigned int clipsm0_clprim_to_clip_null_primitive : 1; - unsigned int clipsm0_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG05 { - struct { - unsigned int clipsm1_clprim_to_clip_clip_code_or : 14; - unsigned int clipsm1_clprim_to_clip_event_id : 6; - unsigned int clipsm1_clprim_to_clip_state_var_indx : 3; - unsigned int clipsm1_clprim_to_clip_clip_primitive : 1; - unsigned int clipsm1_clprim_to_clip_deallocate_slot : 3; - unsigned int clipsm1_clprim_to_clip_first_prim_of_slot : 1; - unsigned int clipsm1_clprim_to_clip_end_of_packet : 1; - unsigned int clipsm1_clprim_to_clip_event : 1; - unsigned int clipsm1_clprim_to_clip_null_primitive : 1; - unsigned int clipsm1_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG06 { - struct { - unsigned int : 1; - unsigned int clipsm1_clprim_to_clip_param_cache_indx_0 : 10; - unsigned int clipsm1_clprim_to_clip_vertex_store_indx_2 : 6; - unsigned int clipsm1_clprim_to_clip_vertex_store_indx_1 : 6; - unsigned int clipsm1_clprim_to_clip_vertex_store_indx_0 : 6; - unsigned int clipsm1_clprim_to_clip_event : 1; - unsigned int clipsm1_clprim_to_clip_null_primitive : 1; - unsigned int clipsm1_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG07 { - struct { - unsigned int clipsm2_clprim_to_clip_clip_code_or : 14; - unsigned int clipsm2_clprim_to_clip_event_id : 6; - unsigned int clipsm2_clprim_to_clip_state_var_indx : 3; - unsigned int clipsm2_clprim_to_clip_clip_primitive : 1; - unsigned int clipsm2_clprim_to_clip_deallocate_slot : 3; - unsigned int clipsm2_clprim_to_clip_first_prim_of_slot : 1; - unsigned int clipsm2_clprim_to_clip_end_of_packet : 1; - unsigned int clipsm2_clprim_to_clip_event : 1; - unsigned int clipsm2_clprim_to_clip_null_primitive : 1; - unsigned int clipsm2_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG08 { - struct { - unsigned int : 1; - unsigned int clipsm2_clprim_to_clip_param_cache_indx_0 : 10; - unsigned int clipsm2_clprim_to_clip_vertex_store_indx_2 : 6; - unsigned int clipsm2_clprim_to_clip_vertex_store_indx_1 : 6; - unsigned int clipsm2_clprim_to_clip_vertex_store_indx_0 : 6; - unsigned int clipsm2_clprim_to_clip_event : 1; - unsigned int clipsm2_clprim_to_clip_null_primitive : 1; - unsigned int clipsm2_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG09 { - struct { - unsigned int clipsm3_clprim_to_clip_clip_code_or : 14; - unsigned int clipsm3_clprim_to_clip_event_id : 6; - unsigned int clipsm3_clprim_to_clip_state_var_indx : 3; - unsigned int clipsm3_clprim_to_clip_clip_primitive : 1; - unsigned int clipsm3_clprim_to_clip_deallocate_slot : 3; - unsigned int clipsm3_clprim_to_clip_first_prim_of_slot : 1; - unsigned int clipsm3_clprim_to_clip_end_of_packet : 1; - unsigned int clipsm3_clprim_to_clip_event : 1; - unsigned int clipsm3_clprim_to_clip_null_primitive : 1; - unsigned int clipsm3_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG10 { - struct { - unsigned int : 1; - unsigned int clipsm3_clprim_to_clip_param_cache_indx_0 : 10; - unsigned int clipsm3_clprim_to_clip_vertex_store_indx_2 : 6; - unsigned int clipsm3_clprim_to_clip_vertex_store_indx_1 : 6; - unsigned int clipsm3_clprim_to_clip_vertex_store_indx_0 : 6; - unsigned int clipsm3_clprim_to_clip_event : 1; - unsigned int clipsm3_clprim_to_clip_null_primitive : 1; - unsigned int clipsm3_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG11 { - struct { - unsigned int clipsm3_clip_to_clipga_event : 1; - unsigned int clipsm2_clip_to_clipga_event : 1; - unsigned int clipsm1_clip_to_clipga_event : 1; - unsigned int clipsm0_clip_to_clipga_event : 1; - unsigned int clipsm3_clip_to_clipga_clip_primitive : 1; - unsigned int clipsm2_clip_to_clipga_clip_primitive : 1; - unsigned int clipsm1_clip_to_clipga_clip_primitive : 1; - unsigned int clipsm0_clip_to_clipga_clip_primitive : 1; - unsigned int clipsm3_clip_to_clipga_clip_to_outsm_cnt : 4; - unsigned int clipsm2_clip_to_clipga_clip_to_outsm_cnt : 4; - unsigned int clipsm1_clip_to_clipga_clip_to_outsm_cnt : 4; - unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 4; - unsigned int clipsm3_clip_to_clipga_prim_valid : 1; - unsigned int clipsm2_clip_to_clipga_prim_valid : 1; - unsigned int clipsm1_clip_to_clipga_prim_valid : 1; - unsigned int clipsm0_clip_to_clipga_prim_valid : 1; - unsigned int clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt : 1; - unsigned int clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt : 1; - unsigned int clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt : 1; - unsigned int clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG12 { - struct { - unsigned int ALWAYS_ZERO : 8; - unsigned int clip_priority_available_vte_out_clip : 5; - unsigned int clip_priority_available_clip_verts : 5; - unsigned int clip_priority_seq_indx_out : 2; - unsigned int clip_priority_seq_indx_vert : 2; - unsigned int clip_priority_seq_indx_load : 2; - unsigned int clipsm3_clprim_to_clip_clip_primitive : 1; - unsigned int clipsm3_clprim_to_clip_prim_valid : 1; - unsigned int clipsm2_clprim_to_clip_clip_primitive : 1; - unsigned int clipsm2_clprim_to_clip_prim_valid : 1; - unsigned int clipsm1_clprim_to_clip_clip_primitive : 1; - unsigned int clipsm1_clprim_to_clip_prim_valid : 1; - unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; - unsigned int clipsm0_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG13 { - struct { - unsigned int clprim_in_back_state_var_indx : 3; - unsigned int point_clip_candidate : 1; - unsigned int prim_nan_kill : 1; - unsigned int clprim_clip_primitive : 1; - unsigned int clprim_cull_primitive : 1; - unsigned int prim_back_valid : 1; - unsigned int vertval_bits_vertex_cc_next_valid : 4; - unsigned int clipcc_vertex_store_indx : 2; - unsigned int vte_out_orig_fifo_fifo_empty : 1; - unsigned int clipcode_fifo_fifo_empty : 1; - unsigned int ccgen_to_clipcc_fifo_empty : 1; - unsigned int clip_priority_seq_indx_out_cnt : 4; - unsigned int outsm_clr_rd_orig_vertices : 2; - unsigned int outsm_clr_rd_clipsm_wait : 1; - unsigned int outsm_clr_fifo_contents : 5; - unsigned int outsm_clr_fifo_full : 1; - unsigned int outsm_clr_fifo_advanceread : 1; - unsigned int outsm_clr_fifo_write : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG14 { - struct { - unsigned int clprim_in_back_vertex_store_indx_2 : 6; - unsigned int clprim_in_back_vertex_store_indx_1 : 6; - unsigned int clprim_in_back_vertex_store_indx_0 : 6; - unsigned int outputclprimtoclip_null_primitive : 1; - unsigned int clprim_in_back_end_of_packet : 1; - unsigned int clprim_in_back_first_prim_of_slot : 1; - unsigned int clprim_in_back_deallocate_slot : 3; - unsigned int clprim_in_back_event_id : 6; - unsigned int clprim_in_back_event : 1; - unsigned int prim_back_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG15 { - struct { - unsigned int vertval_bits_vertex_vertex_store_msb : 16; - unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 5; - unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 5; - unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 5; - unsigned int primic_to_clprim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG16 { - struct { - unsigned int sm0_prim_end_state : 7; - unsigned int sm0_ps_expand : 1; - unsigned int sm0_clip_vert_cnt : 5; - unsigned int sm0_vertex_clip_cnt : 5; - unsigned int sm0_inv_to_clip_data_valid_1 : 1; - unsigned int sm0_inv_to_clip_data_valid_0 : 1; - unsigned int sm0_current_state : 7; - unsigned int sm0_clip_to_clipga_clip_to_outsm_cnt_eq0 : 1; - unsigned int sm0_clip_to_outsm_fifo_full : 1; - unsigned int sm0_highest_priority_seq : 1; - unsigned int sm0_outputcliptoclipga_0 : 1; - unsigned int sm0_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG17 { - struct { - unsigned int sm1_prim_end_state : 7; - unsigned int sm1_ps_expand : 1; - unsigned int sm1_clip_vert_cnt : 5; - unsigned int sm1_vertex_clip_cnt : 5; - unsigned int sm1_inv_to_clip_data_valid_1 : 1; - unsigned int sm1_inv_to_clip_data_valid_0 : 1; - unsigned int sm1_current_state : 7; - unsigned int sm1_clip_to_clipga_clip_to_outsm_cnt_eq0 : 1; - unsigned int sm1_clip_to_outsm_fifo_full : 1; - unsigned int sm1_highest_priority_seq : 1; - unsigned int sm1_outputcliptoclipga_0 : 1; - unsigned int sm1_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG18 { - struct { - unsigned int sm2_prim_end_state : 7; - unsigned int sm2_ps_expand : 1; - unsigned int sm2_clip_vert_cnt : 5; - unsigned int sm2_vertex_clip_cnt : 5; - unsigned int sm2_inv_to_clip_data_valid_1 : 1; - unsigned int sm2_inv_to_clip_data_valid_0 : 1; - unsigned int sm2_current_state : 7; - unsigned int sm2_clip_to_clipga_clip_to_outsm_cnt_eq0 : 1; - unsigned int sm2_clip_to_outsm_fifo_full : 1; - unsigned int sm2_highest_priority_seq : 1; - unsigned int sm2_outputcliptoclipga_0 : 1; - unsigned int sm2_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIPPER_DEBUG_REG19 { - struct { - unsigned int sm3_prim_end_state : 7; - unsigned int sm3_ps_expand : 1; - unsigned int sm3_clip_vert_cnt : 5; - unsigned int sm3_vertex_clip_cnt : 5; - unsigned int sm3_inv_to_clip_data_valid_1 : 1; - unsigned int sm3_inv_to_clip_data_valid_0 : 1; - unsigned int sm3_current_state : 7; - unsigned int sm3_clip_to_clipga_clip_to_outsm_cnt_eq0 : 1; - unsigned int sm3_clip_to_outsm_fifo_full : 1; - unsigned int sm3_highest_priority_seq : 1; - unsigned int sm3_outputcliptoclipga_0 : 1; - unsigned int sm3_clprim_to_clip_prim_valid : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLKREQB_PAD_CNTL__CI__VI { - struct { - unsigned int CLKREQB_PAD_A : 1; - unsigned int CLKREQB_PAD_SEL : 1; - unsigned int CLKREQB_PAD_MODE : 1; - unsigned int CLKREQB_PAD_SPARE : 2; - unsigned int CLKREQB_PAD_SN0 : 1; - unsigned int CLKREQB_PAD_SN1 : 1; - unsigned int CLKREQB_PAD_SN2 : 1; - unsigned int CLKREQB_PAD_SN3 : 1; - unsigned int CLKREQB_PAD_SLEWN : 1; - unsigned int CLKREQB_PAD_WAKE : 1; - unsigned int CLKREQB_PAD_SCHMEN : 1; - unsigned int CLKREQB_PAD_CNTL_EN : 1; - unsigned int CLKREQB_PAD_Y__VI : 1; - unsigned int : 10; - unsigned int CLKREQB_PERF_COUNTER_UPPER__VI : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CM_STAT__SI__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNB_PWRMGT_CNTL__CI__VI { - struct { - unsigned int GNB_SLOW_MODE : 2; - unsigned int GNB_SLOW : 1; - unsigned int FORCE_NB_PS1 : 1; - unsigned int DPM_ENABLED : 1; - unsigned int SPARE : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COHER_DEST_BASE_0 { - struct { - unsigned int DEST_BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COHER_DEST_BASE_1 { - struct { - unsigned int DEST_BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COHER_DEST_BASE_2 { - struct { - unsigned int DEST_BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COHER_DEST_BASE_3 { - struct { - unsigned int DEST_BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COHER_DEST_BASE_HI_0__CI__VI { - struct { - unsigned int DEST_BASE_HI_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COHER_DEST_BASE_HI_1__CI__VI { - struct { - unsigned int DEST_BASE_HI_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COHER_DEST_BASE_HI_2__CI__VI { - struct { - unsigned int DEST_BASE_HI_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COHER_DEST_BASE_HI_3__CI__VI { - struct { - unsigned int DEST_BASE_HI_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMMAND { - struct { - unsigned int IO_ACCESS_EN : 1; - unsigned int MEM_ACCESS_EN : 1; - unsigned int BUS_MASTER_EN : 1; - unsigned int SPECIAL_CYCLE_EN : 1; - unsigned int MEM_WRITE_INVALIDATE_EN : 1; - unsigned int PAL_SNOOP_EN : 1; - unsigned int PARITY_ERROR_RESPONSE : 1; - unsigned int AD_STEPPING : 1; - unsigned int SERR_EN : 1; - unsigned int FAST_B2B_EN : 1; - unsigned int INT_DIS : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_DIM_X { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_DIM_Y { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_DIM_Z { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_DISPATCH_INITIATOR { - struct { - unsigned int COMPUTE_SHADER_EN : 1; - unsigned int PARTIAL_TG_EN : 1; - unsigned int FORCE_START_AT_000 : 1; - unsigned int ORDERED_APPEND_ENBL : 1; - unsigned int ORDERED_APPEND_MODE__CI__VI : 1; - unsigned int USE_THREAD_DIMENSIONS__CI__VI : 1; - unsigned int ORDER_MODE__CI__VI : 1; - unsigned int DISPATCH_CACHE_CNTL__CI__VI : 3; - unsigned int SCALAR_L1_INV_VOL__CI__VI : 1; - unsigned int VECTOR_L1_INV_VOL__CI__VI : 1; - unsigned int DATA_ATC__CI__VI : 1; - unsigned int : 1; - unsigned int RESTORE__CI__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_MAX_WAVE_ID__SI { - struct { - unsigned int : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_MISC_RESERVED__CI__VI { - struct { - unsigned int SEND_SEID : 2; - unsigned int : 3; - unsigned int WAVE_ID_BASE__VI : 12; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_NUM_THREAD_X { - struct { - unsigned int NUM_THREAD_FULL : 16; - unsigned int NUM_THREAD_PARTIAL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_NUM_THREAD_Y { - struct { - unsigned int NUM_THREAD_FULL : 16; - unsigned int NUM_THREAD_PARTIAL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_NUM_THREAD_Z { - struct { - unsigned int NUM_THREAD_FULL : 16; - unsigned int NUM_THREAD_PARTIAL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_PERFCOUNT_ENABLE__CI__VI { - struct { - unsigned int PERFCOUNT_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_PGM_HI { - struct { - unsigned int DATA : 8; - unsigned int INST_ATC__CI__VI : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_PGM_LO { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_PGM_RSRC1 { - struct { - unsigned int VGPRS : 6; - unsigned int SGPRS : 4; - unsigned int PRIORITY : 2; - unsigned int FLOAT_MODE : 8; - unsigned int PRIV : 1; - unsigned int DX10_CLAMP : 1; - unsigned int DEBUG_MODE : 1; - unsigned int IEEE_MODE : 1; - unsigned int BULKY__CI__VI : 1; - unsigned int CDBG_USER__CI__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_PGM_RSRC2 { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int TGID_X_EN : 1; - unsigned int TGID_Y_EN : 1; - unsigned int TGID_Z_EN : 1; - unsigned int TG_SIZE_EN : 1; - unsigned int TIDIG_COMP_CNT : 2; - unsigned int EXCP_EN_MSB__CI__VI : 2; - unsigned int LDS_SIZE : 9; - unsigned int EXCP_EN : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_PIPELINESTAT_ENABLE__CI__VI { - struct { - unsigned int PIPELINESTAT_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_RESOURCE_LIMITS { - struct { - unsigned int WAVES_PER_SH : 10; - unsigned int : 2; - unsigned int TG_PER_CU : 4; - unsigned int LOCK_THRESHOLD : 6; - unsigned int SIMD_DEST_CNTL : 1; - unsigned int FORCE_SIMD_DIST__CI__VI : 1; - unsigned int CU_GROUP_COUNT__CI__VI : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_RESTART_X__CI__VI { - struct { - unsigned int RESTART : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_RESTART_Y__CI__VI { - struct { - unsigned int RESTART : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_RESTART_Z__CI__VI { - struct { - unsigned int RESTART : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_START_X { - struct { - unsigned int START : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_START_Y { - struct { - unsigned int START : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_START_Z { - struct { - unsigned int START : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_STATIC_THREAD_MGMT_SE0 { - struct { - unsigned int SH0_CU_EN : 16; - unsigned int SH1_CU_EN : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_STATIC_THREAD_MGMT_SE1 { - struct { - unsigned int SH0_CU_EN : 16; - unsigned int SH1_CU_EN : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_STATIC_THREAD_MGMT_SE2__CI__VI { - struct { - unsigned int SH0_CU_EN : 16; - unsigned int SH1_CU_EN : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_STATIC_THREAD_MGMT_SE3__CI__VI { - struct { - unsigned int SH0_CU_EN : 16; - unsigned int SH1_CU_EN : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_TBA_HI { - struct { - unsigned int DATA : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_TBA_LO { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_THREAD_TRACE_ENABLE__CI__VI { - struct { - unsigned int THREAD_TRACE_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_TMA_HI { - struct { - unsigned int DATA : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_TMA_LO { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_TMPRING_SIZE { - struct { - unsigned int WAVES : 12; - unsigned int WAVESIZE : 13; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_10 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_11 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_12 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_13 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_14 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_15 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_3 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_4 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_5 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_6 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_7 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_8 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_USER_DATA_9 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_VMID { - struct { - unsigned int DATA : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CONFIG_APER_SIZE { - struct { - unsigned int APER_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CONFIG_CNTL { - struct { - unsigned int CFG_VGA_RAM_EN : 1; - unsigned int VGA_DIS : 1; - unsigned int GENMO_MONO_ADDRESS_B : 1; - unsigned int GRPH_ADRSEL : 2; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CONFIG_F0_BASE { - struct { - unsigned int F0_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CONFIG_MEMSIZE { - struct { - unsigned int CONFIG_MEMSIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CONFIG_REG_APER_SIZE { - struct { - unsigned int REG_APER_SIZE : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CORB_CONTROL__SI__VI { - struct { - unsigned int CORB_MEMORY_ERROR_INTERRUPT_ENABLE : 1; - unsigned int ENABLE_CORB_DMA_ENGINE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CORB_LOWER_BASE_ADDRESS__SI__VI { - struct { - unsigned int CORB_LOWER_BASE_UNIMPLEMENTED_BITS : 7; - unsigned int CORB_LOWER_BASE_ADDRESS : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CORB_READ_POINTER__SI__VI { - struct { - unsigned int CORB_READ_POINTER : 8; - unsigned int : 7; - unsigned int CORB_READ_POINTER_RESET : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CORB_SIZE__SI__VI { - struct { - unsigned int CORB_SIZE : 2; - unsigned int : 2; - unsigned int CORB_SIZE_CAPABILITY : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CORB_STATUS__SI__VI { - struct { - unsigned int CORB_MEMORY_ERROR_INDICATION : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CORB_UPPER_BASE_ADDRESS__SI__VI { - struct { - unsigned int CORB_UPPER_BASE_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CORB_WRITE_POINTER__SI__VI { - struct { - unsigned int CORB_WRITE_POINTER : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC1_CONFIG__CI { - struct { - unsigned int : 8; - unsigned int CPC1_RDREQ_URG : 4; - unsigned int : 4; - unsigned int CPC1_REQ_TRAN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC2_CONFIG__CI { - struct { - unsigned int : 8; - unsigned int CPC2_RDREQ_URG : 4; - unsigned int : 4; - unsigned int CPC2_REQ_TRAN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC_INT_CNTL__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_ENABLE : 1; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int SUA_VIOLATION_INT_ENABLE__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC_INT_CNTX_ID__CI__VI { - struct { - unsigned int CNTX_ID : 28; - unsigned int QUEUE_ID__VI : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC_INT_STATUS__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_STATUS : 1; - unsigned int CP_ECC_ERROR_INT_STATUS : 1; - unsigned int SUA_VIOLATION_INT_STATUS__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STATUS : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_STATUS : 1; - unsigned int OPCODE_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STATUS : 1; - unsigned int RESERVED_BIT_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STATUS : 1; - unsigned int GENERIC1_INT_STATUS : 1; - unsigned int GENERIC0_INT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC_PERFCOUNTER0_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC_PERFCOUNTER0_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 6; - unsigned int : 4; - unsigned int PERF_SEL3 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC_PERFCOUNTER0_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 4; - unsigned int PERF_SEL1 : 6; - unsigned int : 4; - unsigned int CNTR_MODE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC_PERFCOUNTER1_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC_PERFCOUNTER1_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPC_PERFCOUNTER1_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPF_PERFCOUNTER0_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPF_PERFCOUNTER0_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPF_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 6; - unsigned int : 4; - unsigned int PERF_SEL3 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPF_PERFCOUNTER0_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 4; - unsigned int PERF_SEL1 : 6; - unsigned int : 4; - unsigned int CNTR_MODE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPF_PERFCOUNTER1_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPF_PERFCOUNTER1_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPF_PERFCOUNTER1_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPG_CONFIG__CI { - struct { - unsigned int : 8; - unsigned int CPG_RDREQ_URG : 4; - unsigned int : 4; - unsigned int CPG_REQ_TRAN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPG_PERFCOUNTER0_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPG_PERFCOUNTER0_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPG_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 6; - unsigned int : 4; - unsigned int PERF_SEL3 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPG_PERFCOUNTER0_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 4; - unsigned int PERF_SEL1 : 6; - unsigned int : 4; - unsigned int CNTR_MODE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPG_PERFCOUNTER1_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPG_PERFCOUNTER1_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPG_PERFCOUNTER1_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_APPEND_ADDR_HI__SI__CI { - struct { - unsigned int MEM_ADDR_HI : 16; - unsigned int CS_PS_SEL : 2; - unsigned int : 11; - unsigned int COMMAND : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_APPEND_ADDR_HI__VI { - struct { - unsigned int MEM_ADDR_HI : 16; - unsigned int CS_PS_SEL : 1; - unsigned int : 8; - unsigned int CACHE_POLICY : 1; - unsigned int : 1; - unsigned int MTYPE : 2; - unsigned int COMMAND : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_APPEND_ADDR_LO { - struct { - unsigned int : 2; - unsigned int MEM_ADDR_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_APPEND_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_APPEND_LAST_CS_FENCE { - struct { - unsigned int LAST_FENCE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_APPEND_LAST_PS_FENCE { - struct { - unsigned int LAST_FENCE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ATOMIC_PREOP_HI { - struct { - unsigned int ATOMIC_PREOP_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ATOMIC_PREOP_LO { - struct { - unsigned int ATOMIC_PREOP_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_BUSY_STAT { - struct { - unsigned int REG_BUS_FIFO_BUSY : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int COHER_CNT_NEQ_ZERO : 1; - unsigned int PFP_PARSING_PACKETS : 1; - unsigned int ME_PARSING_PACKETS : 1; - unsigned int RCIU_PFP_BUSY : 1; - unsigned int RCIU_ME_BUSY : 1; - unsigned int : 1; - unsigned int SEM_CMDFIFO_NOT_EMPTY : 1; - unsigned int SEM_FAILED_AND_HOLDING : 1; - unsigned int SEM_POLLING_FOR_PASS : 1; - unsigned int GFX_CONTEXT_BUSY : 1; - unsigned int : 1; - unsigned int ME_PARSER_BUSY : 1; - unsigned int EOP_DONE_BUSY : 1; - unsigned int STRM_OUT_BUSY : 1; - unsigned int PIPE_STATS_BUSY : 1; - unsigned int RCIU_CE_BUSY : 1; - unsigned int CE_PARSING_PACKETS : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CEQ1_AVAIL { - struct { - unsigned int CEQ_CNT_RING : 11; - unsigned int : 5; - unsigned int CEQ_CNT_IB1 : 11; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CEQ2_AVAIL { - struct { - unsigned int CEQ_CNT_IB2 : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_COMPARE_COUNT__CI__VI { - struct { - unsigned int COMPARE_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_COUNTER__CI__VI { - struct { - unsigned int CONST_ENGINE_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_DE_COUNT__CI__VI { - struct { - unsigned int DRAW_ENGINE_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_HEADER_DUMP { - struct { - unsigned int CE_HEADER_DUMP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_IB1_BASE_HI { - struct { - unsigned int IB1_BASE_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_IB1_BASE_LO { - struct { - unsigned int : 2; - unsigned int IB1_BASE_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_IB1_BUFSZ { - struct { - unsigned int IB1_BUFSZ : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_IB1_OFFSET__CI__VI { - struct { - unsigned int IB1_OFFSET : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_IB2_BASE_HI { - struct { - unsigned int IB2_BASE_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_IB2_BASE_LO { - struct { - unsigned int : 2; - unsigned int IB2_BASE_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_IB2_BUFSZ { - struct { - unsigned int IB2_BUFSZ : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_IB2_OFFSET__CI__VI { - struct { - unsigned int IB2_OFFSET : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_INIT_BASE_HI { - struct { - unsigned int INIT_BASE_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_INIT_BASE_LO { - struct { - unsigned int : 5; - unsigned int INIT_BASE_LO : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_INIT_BUFSZ { - struct { - unsigned int INIT_BUFSZ : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_INTR_ROUTINE_START__CI__VI { - struct { - unsigned int IR_START : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_PRGRM_CNTR_START__CI__VI { - struct { - unsigned int IP_START : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_ROQ_IB1_STAT { - struct { - unsigned int CEQ_RPTR_INDIRECT1 : 10; - unsigned int : 6; - unsigned int CEQ_WPTR_INDIRECT1 : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_ROQ_IB2_STAT { - struct { - unsigned int CEQ_RPTR_INDIRECT2 : 10; - unsigned int : 6; - unsigned int CEQ_WPTR_INDIRECT2 : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_ROQ_RB_STAT { - struct { - unsigned int CEQ_RPTR_PRIMARY : 10; - unsigned int : 6; - unsigned int CEQ_WPTR_PRIMARY : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_UCODE_ADDR { - struct { - unsigned int UCODE_ADDR : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_UCODE_DATA { - struct { - unsigned int UCODE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CMD_DATA { - struct { - unsigned int CMD_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CMD_INDEX { - struct { - unsigned int CMD_INDEX : 11; - unsigned int : 1; - unsigned int CMD_ME_SEL__CI__VI : 2; - unsigned int : 2; - unsigned int CMD_QUEUE_SEL : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CNTL__SI { - struct { - unsigned int : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CNTX_STAT__CI__VI { - struct { - unsigned int ACTIVE_HP3D_CONTEXTS : 8; - unsigned int CURRENT_HP3D_CONTEXT : 3; - unsigned int : 9; - unsigned int ACTIVE_GFX_CONTEXTS : 8; - unsigned int CURRENT_GFX_CONTEXT : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CNTX_STAT__SI { - struct { - unsigned int : 8; - unsigned int : 3; - unsigned int : 1; - unsigned int : 8; - unsigned int ACTIVE_GFX_CONTEXTS : 8; - unsigned int CURRENT_GFX_CONTEXT : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_COHER_BASE { - struct { - unsigned int COHER_BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_COHER_BASE_HI__CI__VI { - struct { - unsigned int COHER_BASE_HI_256B : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_COHER_CNTL { - struct { - unsigned int DEST_BASE_0_ENA : 1; - unsigned int DEST_BASE_1_ENA : 1; - unsigned int TC_SD_ACTION_ENA__VI : 1; - unsigned int TC_NC_ACTION_ENA__VI : 1; - unsigned int : 2; - unsigned int CB0_DEST_BASE_ENA : 1; - unsigned int CB1_DEST_BASE_ENA : 1; - unsigned int CB2_DEST_BASE_ENA : 1; - unsigned int CB3_DEST_BASE_ENA : 1; - unsigned int CB4_DEST_BASE_ENA : 1; - unsigned int CB5_DEST_BASE_ENA : 1; - unsigned int CB6_DEST_BASE_ENA : 1; - unsigned int CB7_DEST_BASE_ENA : 1; - unsigned int DB_DEST_BASE_ENA : 1; - unsigned int TCL1_VOL_ACTION_ENA__CI__VI : 1; - unsigned int TC_VOL_ACTION_ENA__CI : 1; - unsigned int : 1; - unsigned int TC_WB_ACTION_ENA__CI__VI : 1; - unsigned int DEST_BASE_2_ENA : 1; - unsigned int : 1; - unsigned int DEST_BASE_3_ENA : 1; - unsigned int TCL1_ACTION_ENA : 1; - unsigned int TC_ACTION_ENA : 1; - unsigned int : 1; - unsigned int CB_ACTION_ENA : 1; - unsigned int DB_ACTION_ENA : 1; - unsigned int SH_KCACHE_ACTION_ENA : 1; - unsigned int SH_KCACHE_VOL_ACTION_ENA__CI__VI : 1; - unsigned int SH_ICACHE_ACTION_ENA : 1; - unsigned int SH_KCACHE_WB_ACTION_ENA__VI : 1; - unsigned int SH_SD_ACTION_ENA__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_COHER_SIZE { - struct { - unsigned int COHER_SIZE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_COHER_SIZE_HI__CI__VI { - struct { - unsigned int COHER_SIZE_HI_256B : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_COHER_START_DELAY { - struct { - unsigned int START_DELAY_COUNT : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_COHER_STATUS { - struct { - unsigned int MATCHING_GFX_CNTX : 8; - unsigned int : 16; - unsigned int MEID__CI__VI : 2; - unsigned int : 4; - unsigned int PHASE1_STATUS : 1; - unsigned int STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CONFIG__SI__VI { - struct { - unsigned int : 8; - unsigned int CP_RDREQ_URG : 4; - unsigned int : 4; - unsigned int CP_REQ_TRAN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CONTEXT_CNTL__CI__VI { - struct { - unsigned int ME0PIPE0_MAX_WD_CNTX : 3; - unsigned int : 1; - unsigned int ME0PIPE0_MAX_PIPE_CNTX : 3; - unsigned int : 9; - unsigned int ME0PIPE1_MAX_WD_CNTX : 3; - unsigned int : 1; - unsigned int ME0PIPE1_MAX_PIPE_CNTX : 3; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_BUSY_STAT__CI__VI { - struct { - unsigned int MEC1_LOAD_BUSY : 1; - unsigned int MEC1_SEMAPOHRE_BUSY : 1; - unsigned int MEC1_MUTEX_BUSY : 1; - unsigned int MEC1_MESSAGE_BUSY : 1; - unsigned int MEC1_EOP_QUEUE_BUSY : 1; - unsigned int MEC1_IQ_QUEUE_BUSY : 1; - unsigned int MEC1_IB_QUEUE_BUSY : 1; - unsigned int MEC1_TC_BUSY : 1; - unsigned int MEC1_DMA_BUSY : 1; - unsigned int MEC1_PARTIAL_FLUSH_BUSY : 1; - unsigned int MEC1_PIPE0_BUSY : 1; - unsigned int MEC1_PIPE1_BUSY : 1; - unsigned int MEC1_PIPE2_BUSY : 1; - unsigned int MEC1_PIPE3_BUSY : 1; - unsigned int : 2; - unsigned int MEC2_LOAD_BUSY : 1; - unsigned int MEC2_SEMAPOHRE_BUSY : 1; - unsigned int MEC2_MUTEX_BUSY : 1; - unsigned int MEC2_MESSAGE_BUSY : 1; - unsigned int MEC2_EOP_QUEUE_BUSY : 1; - unsigned int MEC2_IQ_QUEUE_BUSY : 1; - unsigned int MEC2_IB_QUEUE_BUSY : 1; - unsigned int MEC2_TC_BUSY : 1; - unsigned int MEC2_DMA_BUSY : 1; - unsigned int MEC2_PARTIAL_FLUSH_BUSY : 1; - unsigned int MEC2_PIPE0_BUSY : 1; - unsigned int MEC2_PIPE1_BUSY : 1; - unsigned int MEC2_PIPE2_BUSY : 1; - unsigned int MEC2_PIPE3_BUSY : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_GRBM_FREE_COUNT__CI__VI { - struct { - unsigned int FREE_COUNT : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_HALT_HYST_COUNT__CI__VI { - struct { - unsigned int COUNT : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_MC_CNTL__CI { - struct { - unsigned int PACK_DELAY_CNT : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_SCRATCH_DATA__CI__VI { - struct { - unsigned int SCRATCH_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_SCRATCH_INDEX__CI__VI { - struct { - unsigned int SCRATCH_INDEX : 9; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_STALLED_STAT1__CI__VI { - struct { - unsigned int MIU_RDREQ_FREE_STALL__SI__CI : 1; - unsigned int MIU_WRREQ_FREE_STALL__SI__CI : 1; - unsigned int : 1; - unsigned int RCIU_TX_FREE_STALL : 1; - unsigned int RCIU_PRIV_VIOLATION : 1; - unsigned int : 1; - unsigned int TCIU_TX_FREE_STALL : 1; - unsigned int : 1; - unsigned int MEC1_DECODING_PACKET : 1; - unsigned int MEC1_WAIT_ON_RCIU : 1; - unsigned int MEC1_WAIT_ON_RCIU_READ : 1; - unsigned int MEC1_WAIT_ON_MC_READ__SI__CI : 1; - unsigned int MEC1_WAIT_ON_MC_WR_ACK__SI__CI : 1; - unsigned int MEC1_WAIT_ON_ROQ_DATA : 1; - unsigned int : 2; - unsigned int MEC2_DECODING_PACKET : 1; - unsigned int MEC2_WAIT_ON_RCIU : 1; - unsigned int MEC2_WAIT_ON_RCIU_READ : 1; - unsigned int MEC2_WAIT_ON_MC_READ__SI__CI : 1; - unsigned int MEC2_WAIT_ON_MC_WR_ACK__SI__CI : 1; - unsigned int MEC2_WAIT_ON_ROQ_DATA : 1; - unsigned int ATCL2IU_WAITING_ON_FREE__VI : 1; - unsigned int ATCL2IU_WAITING_ON_TAGS__VI : 1; - unsigned int ATCL1_WAITING_ON_TRANS__VI : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_STATUS__CI__VI { - struct { - unsigned int MEC1_BUSY : 1; - unsigned int MEC2_BUSY : 1; - unsigned int DC0_BUSY : 1; - unsigned int DC1_BUSY : 1; - unsigned int RCIU1_BUSY : 1; - unsigned int RCIU2_BUSY : 1; - unsigned int ROQ1_BUSY : 1; - unsigned int ROQ2_BUSY : 1; - unsigned int MIU_RDREQ_BUSY__SI__CI : 1; - unsigned int MIU_WRREQ_BUSY__SI__CI : 1; - unsigned int TCIU_BUSY : 1; - unsigned int SCRATCH_RAM_BUSY : 1; - unsigned int QU_BUSY : 1; - unsigned int ATCL2IU_BUSY__VI : 1; - unsigned int : 15; - unsigned int CPG_CPC_BUSY : 1; - unsigned int CPF_CPC_BUSY : 1; - unsigned int CPC_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPF_BUSY_STAT__CI__VI { - struct { - unsigned int REG_BUS_FIFO_BUSY : 1; - unsigned int CSF_RING_BUSY : 1; - unsigned int CSF_INDIRECT1_BUSY : 1; - unsigned int CSF_INDIRECT2_BUSY : 1; - unsigned int CSF_STATE_BUSY : 1; - unsigned int CSF_CE_INDR1_BUSY : 1; - unsigned int CSF_CE_INDR2_BUSY : 1; - unsigned int CSF_ARBITER_BUSY : 1; - unsigned int CSF_INPUT_BUSY : 1; - unsigned int OUTSTANDING_READ_TAGS : 1; - unsigned int : 1; - unsigned int HPD_PROCESSING_EOP_BUSY : 1; - unsigned int HQD_DISPATCH_BUSY : 1; - unsigned int HQD_IQ_TIMER_BUSY : 1; - unsigned int HQD_DMA_OFFLOAD_BUSY : 1; - unsigned int HQD_WAIT_SEMAPHORE_BUSY : 1; - unsigned int HQD_SIGNAL_SEMAPHORE_BUSY : 1; - unsigned int HQD_MESSAGE_BUSY : 1; - unsigned int HQD_PQ_FETCHER_BUSY : 1; - unsigned int HQD_IB_FETCHER_BUSY : 1; - unsigned int HQD_IQ_FETCHER_BUSY : 1; - unsigned int HQD_EOP_FETCHER_BUSY : 1; - unsigned int HQD_CONSUMED_RPTR_BUSY : 1; - unsigned int HQD_FETCHER_ARB_BUSY : 1; - unsigned int HQD_ROQ_ALIGN_BUSY : 1; - unsigned int HQD_ROQ_EOP_BUSY : 1; - unsigned int HQD_ROQ_IQ_BUSY : 1; - unsigned int HQD_ROQ_PQ_BUSY : 1; - unsigned int HQD_ROQ_IB_BUSY : 1; - unsigned int HQD_WPTR_POLL_BUSY : 1; - unsigned int HQD_PQ_BUSY : 1; - unsigned int HQD_IB_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPF_STALLED_STAT1__CI__VI { - struct { - unsigned int RING_FETCHING_DATA : 1; - unsigned int INDR1_FETCHING_DATA : 1; - unsigned int INDR2_FETCHING_DATA : 1; - unsigned int STATE_FETCHING_DATA : 1; - unsigned int MIU_WAITING_ON_RDREQ_FREE__SI__CI : 1; - unsigned int TCIU_WAITING_ON_FREE : 1; - unsigned int TCIU_WAITING_ON_TAGS : 1; - unsigned int ATCL2IU_WAITING_ON_FREE__VI : 1; - unsigned int ATCL2IU_WAITING_ON_TAGS__VI : 1; - unsigned int ATCL1_WAITING_ON_TRANS__VI : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPF_STATUS__CI__VI { - struct { - unsigned int POST_WPTR_GFX_BUSY : 1; - unsigned int CSF_BUSY : 1; - unsigned int MIU_RDREQ_BUSY__SI__CI : 1; - unsigned int MIU_WRREQ_BUSY__SI__CI : 1; - unsigned int ROQ_ALIGN_BUSY : 1; - unsigned int ROQ_RING_BUSY : 1; - unsigned int ROQ_INDIRECT1_BUSY : 1; - unsigned int ROQ_INDIRECT2_BUSY : 1; - unsigned int ROQ_STATE_BUSY : 1; - unsigned int ROQ_CE_RING_BUSY : 1; - unsigned int ROQ_CE_INDIRECT1_BUSY : 1; - unsigned int ROQ_CE_INDIRECT2_BUSY : 1; - unsigned int SEMAPHORE_BUSY : 1; - unsigned int INTERRUPT_BUSY : 1; - unsigned int TCIU_BUSY : 1; - unsigned int HQD_BUSY : 1; - unsigned int PRT_BUSY__VI : 1; - unsigned int ATCL2IU_BUSY__VI : 1; - unsigned int : 8; - unsigned int CPF_GFX_BUSY__VI : 1; - unsigned int CPF_CMP_BUSY__VI : 1; - unsigned int GRBM_CPF_STAT_BUSY__VI : 2; - unsigned int CPC_CPF_BUSY : 1; - unsigned int CPF_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CSF_CNTL { - struct { - unsigned int FETCH_BUFFER_DEPTH : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CSF_STAT { - struct { - unsigned int BUFFER_SLOTS_ALLOCATED : 4; - unsigned int : 4; - unsigned int BUFFER_REQUEST_COUNT : 9; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DEBUG__CI__VI { - struct { - unsigned int : 6; - unsigned int : 1; - unsigned int : 8; - unsigned int : 1; - unsigned int : 3; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DEBUG__SI { - struct { - unsigned int : 6; - unsigned int : 9; - unsigned int : 1; - unsigned int : 3; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DEVICE_ID__CI__VI { - struct { - unsigned int DEVICE_ID : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DE_CE_COUNT__CI__VI { - struct { - unsigned int CONST_ENGINE_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DE_DE_COUNT__CI__VI { - struct { - unsigned int DRAW_ENGINE_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DE_LAST_INVAL_COUNT__CI__VI { - struct { - unsigned int LAST_INVAL_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_ADDR_HI__CI__VI { - struct { - unsigned int ADDR_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_ADDR_LO__CI__VI { - struct { - unsigned int : 5; - unsigned int ADDR_LO : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_CNTL__CI { - struct { - unsigned int : 8; - unsigned int POLICY : 2; - unsigned int VOL : 1; - unsigned int ATC : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_CNTL__VI { - struct { - unsigned int POLICY : 1; - unsigned int : 1; - unsigned int MTYPE : 2; - unsigned int : 23; - unsigned int : 1; - unsigned int LFSR_RESET : 1; - unsigned int MODE : 2; - unsigned int ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_0__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_10__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_11__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_12__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_13__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_14__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_15__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_1__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_2__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_3__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_4__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_5__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_6__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_7__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_8__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_DATA_9__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_STAT__CI__VI { - struct { - unsigned int BURST_COUNT : 16; - unsigned int TAGS_PENDING : 9; - unsigned int : 6; - unsigned int BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_CNTL { - struct { - unsigned int : 4; - unsigned int MIN_AVAILSZ : 2; - unsigned int : 10; - unsigned int BUFFER_DEPTH : 4; - unsigned int : 8; - unsigned int PIO_FIFO_EMPTY : 1; - unsigned int PIO_FIFO_FULL : 1; - unsigned int PIO_COUNT : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_ME_COMMAND { - struct { - unsigned int BYTE_COUNT : 21; - unsigned int DIS_WC : 1; - unsigned int SRC_SWAP : 2; - unsigned int DST_SWAP : 2; - unsigned int SAS : 1; - unsigned int DAS : 1; - unsigned int SAIC : 1; - unsigned int DAIC : 1; - unsigned int RAW_WAIT : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_ME_CONTROL__CI { - struct { - unsigned int : 12; - unsigned int SRC_ATC : 1; - unsigned int SRC_CACHE_POLICY : 2; - unsigned int SRC_VOLATILE : 1; - unsigned int : 4; - unsigned int DST_SELECT : 2; - unsigned int : 2; - unsigned int DST_ATC : 1; - unsigned int DST_CACHE_POLICY : 2; - unsigned int DST_VOLATILE : 1; - unsigned int : 1; - unsigned int SRC_SELECT : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_ME_CONTROL__VI { - struct { - unsigned int : 10; - unsigned int SRC_MTYPE : 2; - unsigned int SRC_ATC : 1; - unsigned int SRC_CACHE_POLICY : 1; - unsigned int : 6; - unsigned int DST_SELECT : 2; - unsigned int DST_MTYPE : 2; - unsigned int DST_ATC : 1; - unsigned int DST_CACHE_POLICY : 1; - unsigned int : 3; - unsigned int SRC_SELECT : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_ME_DST_ADDR { - struct { - unsigned int DST_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_ME_DST_ADDR_HI { - struct { - unsigned int DST_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_ME_SRC_ADDR { - struct { - unsigned int SRC_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_ME_SRC_ADDR_HI { - struct { - unsigned int SRC_ADDR_HI : 16; - unsigned int : 4; - unsigned int : 2; - unsigned int : 7; - unsigned int : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_PFP_COMMAND { - struct { - unsigned int BYTE_COUNT : 21; - unsigned int DIS_WC : 1; - unsigned int SRC_SWAP : 2; - unsigned int DST_SWAP : 2; - unsigned int SAS : 1; - unsigned int DAS : 1; - unsigned int SAIC : 1; - unsigned int DAIC : 1; - unsigned int RAW_WAIT : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_PFP_CONTROL__CI { - struct { - unsigned int : 12; - unsigned int SRC_ATC : 1; - unsigned int SRC_CACHE_POLICY : 2; - unsigned int SRC_VOLATILE : 1; - unsigned int : 4; - unsigned int DST_SELECT : 2; - unsigned int : 2; - unsigned int DST_ATC : 1; - unsigned int DST_CACHE_POLICY : 2; - unsigned int DST_VOLATILE : 1; - unsigned int : 1; - unsigned int SRC_SELECT : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_PFP_CONTROL__VI { - struct { - unsigned int : 10; - unsigned int SRC_MTYPE : 2; - unsigned int SRC_ATC : 1; - unsigned int SRC_CACHE_POLICY : 1; - unsigned int : 6; - unsigned int DST_SELECT : 2; - unsigned int DST_MTYPE : 2; - unsigned int DST_ATC : 1; - unsigned int DST_CACHE_POLICY : 1; - unsigned int : 3; - unsigned int SRC_SELECT : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_PFP_DST_ADDR { - struct { - unsigned int DST_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_PFP_DST_ADDR_HI { - struct { - unsigned int DST_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_PFP_SRC_ADDR { - struct { - unsigned int SRC_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_PFP_SRC_ADDR_HI { - struct { - unsigned int SRC_ADDR_HI : 16; - unsigned int : 4; - unsigned int : 2; - unsigned int : 7; - unsigned int : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_PIO_COMMAND { - struct { - unsigned int : 21; - unsigned int : 1; - unsigned int : 2; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DMA_READ_TAGS { - struct { - unsigned int DMA_READ_TAG : 26; - unsigned int : 2; - unsigned int DMA_READ_TAG_VALID : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ECC_FIRSTOCCURRENCE__SI__CI { - struct { - unsigned int INTERFACE : 2; - unsigned int : 2; - unsigned int REQUEST_CLIENT : 4; - unsigned int : 2; - unsigned int RING_ID : 4; - unsigned int : 2; - unsigned int VMID : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ECC_FIRSTOCCURRENCE__VI { - struct { - unsigned int INTERFACE : 2; - unsigned int : 2; - unsigned int CLIENT : 4; - unsigned int ME : 2; - unsigned int PIPE : 2; - unsigned int QUEUE : 3; - unsigned int : 1; - unsigned int VMID : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ECC_FIRSTOCCURRENCE_RING0__SI__CI { - struct { - unsigned int INTERFACE : 2; - unsigned int : 2; - unsigned int REQUEST_CLIENT : 4; - unsigned int : 2; - unsigned int RING_ID : 4; - unsigned int : 2; - unsigned int VMID : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ECC_FIRSTOCCURRENCE_RING0__VI { - struct { - unsigned int OBSOLETE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ECC_FIRSTOCCURRENCE_RING1__SI__CI { - struct { - unsigned int INTERFACE : 2; - unsigned int : 2; - unsigned int REQUEST_CLIENT : 4; - unsigned int : 2; - unsigned int RING_ID : 4; - unsigned int : 2; - unsigned int VMID : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ECC_FIRSTOCCURRENCE_RING1__VI { - struct { - unsigned int OBSOLETE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ECC_FIRSTOCCURRENCE_RING2__SI__CI { - struct { - unsigned int INTERFACE : 2; - unsigned int : 2; - unsigned int REQUEST_CLIENT : 4; - unsigned int : 2; - unsigned int RING_ID : 4; - unsigned int : 2; - unsigned int VMID : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ECC_FIRSTOCCURRENCE_RING2__VI { - struct { - unsigned int OBSOLETE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ENDIAN_SWAP__CI__VI { - struct { - unsigned int ENDIAN_SWAP : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_ADDR_HI__CI__VI { - struct { - unsigned int ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_ADDR_HI__SI { - struct { - unsigned int : 8; - unsigned int : 16; - unsigned int : 2; - unsigned int : 3; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_ADDR_LO__CI__VI { - struct { - unsigned int ADDR_SWAP__SI__CI : 2; - unsigned int ADDR_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_ADDR_LO__SI { - struct { - unsigned int : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_DATA_CNTL__CI__VI { - struct { - unsigned int CNTX_ID : 16; - unsigned int DST_SEL : 2; - unsigned int : 6; - unsigned int INT_SEL : 3; - unsigned int : 2; - unsigned int DATA_SEL : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_DATA_HI__CI__VI { - struct { - unsigned int DATA_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_DATA_HI__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_DATA_LO__CI__VI { - struct { - unsigned int DATA_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_DATA_LO__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_EVENT_CNTL__CI { - struct { - unsigned int WBINV_TC_OP : 7; - unsigned int : 5; - unsigned int WBINV_ACTION_ENA : 6; - unsigned int : 7; - unsigned int CACHE_CONTROL : 2; - unsigned int EOP_VOLATILE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_EVENT_CNTL__VI { - struct { - unsigned int WBINV_TC_OP : 7; - unsigned int : 5; - unsigned int WBINV_ACTION_ENA : 6; - unsigned int : 7; - unsigned int CACHE_CONTROL : 1; - unsigned int : 1; - unsigned int MTYPE : 2; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_LAST_FENCE_HI { - struct { - unsigned int LAST_FENCE_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_LAST_FENCE_LO { - struct { - unsigned int LAST_FENCE_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_FETCHER_SOURCE__CI { - struct { - unsigned int ME_SRC : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_GDS_ATOMIC0_PREOP_HI { - struct { - unsigned int GDS_ATOMIC0_PREOP_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_GDS_ATOMIC0_PREOP_LO { - struct { - unsigned int GDS_ATOMIC0_PREOP_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_GDS_ATOMIC1_PREOP_HI { - struct { - unsigned int GDS_ATOMIC1_PREOP_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_GDS_ATOMIC1_PREOP_LO { - struct { - unsigned int GDS_ATOMIC1_PREOP_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_GRBM_FREE_COUNT { - struct { - unsigned int FREE_COUNT : 6; - unsigned int : 2; - unsigned int FREE_COUNT_GDS : 6; - unsigned int : 2; - unsigned int FREE_COUNT_PFP : 6; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HPD_EOP_BASE_ADDR_HI__CI { - struct { - unsigned int BASE_ADDR_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HPD_EOP_BASE_ADDR__CI { - struct { - unsigned int BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HPD_EOP_CONTROL__CI { - struct { - unsigned int EOP_SIZE : 6; - unsigned int : 2; - unsigned int PROCESSING_EOP : 1; - unsigned int PROCESSING_QID : 3; - unsigned int PROCESS_EOP_EN : 1; - unsigned int PROCESSING_EOPIB : 1; - unsigned int PROCESS_EOPIB_EN : 1; - unsigned int : 8; - unsigned int EOP_ATC : 1; - unsigned int CACHE_POLICY : 2; - unsigned int EOP_VOLATILE : 1; - unsigned int : 1; - unsigned int PEND_Q_SEM : 3; - unsigned int PEND_SIG_SEM : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HPD_EOP_VMID__CI { - struct { - unsigned int VMID : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HPD_ROQ_OFFSETS__CI__VI { - struct { - unsigned int IQ_OFFSET : 3; - unsigned int : 5; - unsigned int PQ_OFFSET : 6; - unsigned int : 2; - unsigned int IB_OFFSET : 6; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_ACTIVE__CI__VI { - struct { - unsigned int ACTIVE : 1; - unsigned int BUSY_GATE__VI : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_ATOMIC0_PREOP_HI__CI__VI { - struct { - unsigned int ATOMIC0_PREOP_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_ATOMIC0_PREOP_LO__CI__VI { - struct { - unsigned int ATOMIC0_PREOP_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_ATOMIC1_PREOP_HI__CI__VI { - struct { - unsigned int ATOMIC1_PREOP_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_ATOMIC1_PREOP_LO__CI__VI { - struct { - unsigned int ATOMIC1_PREOP_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_DEQUEUE_REQUEST__CI__VI { - struct { - unsigned int DEQUEUE_REQ : 3; - unsigned int : 1; - unsigned int IQ_REQ_PEND : 1; - unsigned int : 3; - unsigned int DEQUEUE_INT : 1; - unsigned int IQ_REQ_PEND_EN__VI : 1; - unsigned int DEQUEUE_REQ_EN__VI : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_DMA_OFFLOAD__CI__VI { - struct { - unsigned int DMA_OFFLOAD : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_HQ_SCHEDULER0__CI { - struct { - unsigned int DEQUEUE_STATUS : 2; - unsigned int DEQUEUE_RETRY_CNT : 2; - unsigned int : 3; - unsigned int SCRATCH_RAM_INIT : 1; - unsigned int TCL2_DIRTY : 1; - unsigned int PG_ACTIVATED : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_HQ_SCHEDULER0__VI { - struct { - unsigned int SCHEDULER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_HQ_SCHEDULER1__CI__VI { - struct { - unsigned int SCHEDULER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_IB_BASE_ADDR_HI__CI__VI { - struct { - unsigned int IB_BASE_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_IB_BASE_ADDR__CI__VI { - struct { - unsigned int : 2; - unsigned int IB_BASE_ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_IB_CONTROL__CI { - struct { - unsigned int IB_SIZE : 20; - unsigned int MIN_IB_AVAIL_SIZE : 2; - unsigned int : 1; - unsigned int IB_ATC : 1; - unsigned int IB_CACHE_POLICY : 2; - unsigned int IB_VOLATILE : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int PROCESSING_IB : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_IB_CONTROL__VI { - struct { - unsigned int IB_SIZE : 20; - unsigned int MIN_IB_AVAIL_SIZE : 2; - unsigned int : 1; - unsigned int IB_ATC : 1; - unsigned int IB_CACHE_POLICY : 1; - unsigned int : 2; - unsigned int MTYPE : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int PROCESSING_IB : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_IB_RPTR__CI__VI { - struct { - unsigned int CONSUMED_OFFSET : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_IQ_RPTR__CI__VI { - struct { - unsigned int OFFSET : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_IQ_TIMER__CI { - struct { - unsigned int WAIT_TIME : 8; - unsigned int RETRY_TYPE : 3; - unsigned int : 1; - unsigned int INTERRUPT_TYPE : 2; - unsigned int : 2; - unsigned int INTERRUPT_SIZE : 6; - unsigned int : 1; - unsigned int IQ_ATC : 1; - unsigned int CACHE_POLICY : 2; - unsigned int IQ_VOLATILE : 1; - unsigned int : 2; - unsigned int PROCESS_IQ_EN : 1; - unsigned int PROCESSING_IQ : 1; - unsigned int ACTIVE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_IQ_TIMER__VI { - struct { - unsigned int WAIT_TIME : 8; - unsigned int RETRY_TYPE : 3; - unsigned int IMMEDIATE_EXPIRE : 1; - unsigned int INTERRUPT_TYPE : 2; - unsigned int CLOCK_COUNT : 2; - unsigned int INTERRUPT_SIZE : 6; - unsigned int QUANTUM_TIMER : 1; - unsigned int IQ_ATC : 1; - unsigned int CACHE_POLICY : 1; - unsigned int : 2; - unsigned int MTYPE : 2; - unsigned int PROCESS_IQ_EN : 1; - unsigned int PROCESSING_IQ : 1; - unsigned int ACTIVE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_MSG_TYPE__CI__VI { - struct { - unsigned int ACTION : 3; - unsigned int : 1; - unsigned int SAVE_STATE__VI : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PERSISTENT_STATE__CI__VI { - struct { - unsigned int PRELOAD_REQ : 1; - unsigned int : 7; - unsigned int PRELOAD_SIZE : 10; - unsigned int : 10; - unsigned int RESTORE_ACTIVE__VI : 1; - unsigned int RELAUNCH_WAVES__VI : 1; - unsigned int QSWITCH_MODE__VI : 1; - unsigned int DISP_ACTIVE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PIPE_PRIORITY__CI__VI { - struct { - unsigned int PIPE_PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PQ_BASE_HI__CI__VI { - struct { - unsigned int ADDR_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PQ_BASE__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PQ_CONTROL__CI { - struct { - unsigned int QUEUE_SIZE : 6; - unsigned int : 2; - unsigned int RPTR_BLOCK_SIZE : 6; - unsigned int : 2; - unsigned int ENDIAN_SWAP : 2; - unsigned int : 2; - unsigned int MIN_AVAIL_SIZE : 2; - unsigned int : 1; - unsigned int PQ_ATC : 1; - unsigned int CACHE_POLICY : 2; - unsigned int PQ_VOLATILE : 1; - unsigned int NO_UPDATE_RPTR : 1; - unsigned int UNORD_DISPATCH : 1; - unsigned int ROQ_PQ_IB_FLIP : 1; - unsigned int PRIV_STATE : 1; - unsigned int KMD_QUEUE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PQ_CONTROL__VI { - struct { - unsigned int QUEUE_SIZE : 6; - unsigned int : 2; - unsigned int RPTR_BLOCK_SIZE : 6; - unsigned int : 1; - unsigned int MTYPE : 2; - unsigned int ENDIAN_SWAP : 2; - unsigned int : 1; - unsigned int MIN_AVAIL_SIZE : 2; - unsigned int : 1; - unsigned int PQ_ATC : 1; - unsigned int CACHE_POLICY : 1; - unsigned int SLOT_BASED_WPTR : 2; - unsigned int NO_UPDATE_RPTR : 1; - unsigned int UNORD_DISPATCH : 1; - unsigned int ROQ_PQ_IB_FLIP : 1; - unsigned int PRIV_STATE : 1; - unsigned int KMD_QUEUE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PQ_DOORBELL_CONTROL__CI__VI { - struct { - unsigned int DOORBELL_MODE__VI : 1; - unsigned int DOORBELL_BIF_DROP__VI : 1; - unsigned int DOORBELL_OFFSET : 21; - unsigned int DOORBELL_CARRY_BITS__VI : 3; - unsigned int : 2; - unsigned int DOORBELL_SOURCE : 1; - unsigned int DOORBELL_SCHD_HIT : 1; - unsigned int DOORBELL_EN : 1; - unsigned int DOORBELL_HIT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PQ_RPTR_REPORT_ADDR_HI__CI__VI { - struct { - unsigned int RPTR_REPORT_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PQ_RPTR_REPORT_ADDR__CI__VI { - struct { - unsigned int : 2; - unsigned int RPTR_REPORT_ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PQ_RPTR__CI__VI { - struct { - unsigned int CONSUMED_OFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PQ_WPTR_POLL_ADDR_HI__CI__VI { - struct { - unsigned int WPTR_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PQ_WPTR_POLL_ADDR__CI__VI { - struct { - unsigned int : 2; - unsigned int WPTR_ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_PQ_WPTR__CI__VI { - struct { - unsigned int OFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_QUANTUM__CI__VI { - struct { - unsigned int QUANTUM_EN : 1; - unsigned int : 3; - unsigned int QUANTUM_SCALE : 1; - unsigned int : 3; - unsigned int QUANTUM_DURATION : 6; - unsigned int : 17; - unsigned int QUANTUM_ACTIVE__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_QUEUE_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY_LEVEL : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_SEMA_CMD__CI__VI { - struct { - unsigned int RETRY : 1; - unsigned int RESULT : 2; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_VMID__CI__VI { - struct { - unsigned int VMID : 4; - unsigned int : 4; - unsigned int IB_VMID : 4; - unsigned int : 4; - unsigned int VQID : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB1_BASE_HI { - struct { - unsigned int IB1_BASE_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB1_BASE_LO { - struct { - unsigned int : 2; - unsigned int IB1_BASE_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB1_BUFSZ { - struct { - unsigned int IB1_BUFSZ : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB1_OFFSET { - struct { - unsigned int IB1_OFFSET : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB1_PREAMBLE_BEGIN { - struct { - unsigned int IB1_PREAMBLE_BEGIN : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB1_PREAMBLE_END { - struct { - unsigned int IB1_PREAMBLE_END : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB2_BASE_HI { - struct { - unsigned int IB2_BASE_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB2_BASE_LO { - struct { - unsigned int : 2; - unsigned int IB2_BASE_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB2_BUFSZ { - struct { - unsigned int IB2_BUFSZ : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB2_OFFSET { - struct { - unsigned int IB2_OFFSET : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB2_PREAMBLE_BEGIN { - struct { - unsigned int IB2_PREAMBLE_BEGIN : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IB2_PREAMBLE_END { - struct { - unsigned int IB2_PREAMBLE_END : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_CNTL_RING0__CI__VI { - struct { - unsigned int : 11; - unsigned int CP_VM_DOORBELL_WR_INT_ENABLE__VI : 1; - unsigned int : 2; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int : 2; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int CMP_BUSY_INT_ENABLE__VI : 1; - unsigned int CNTX_BUSY_INT_ENABLE : 1; - unsigned int CNTX_EMPTY_INT_ENABLE : 1; - unsigned int GFX_IDLE_INT_ENABLE__VI : 1; - unsigned int PRIV_INSTR_INT_ENABLE : 1; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_CNTL_RING0__SI { - struct { - unsigned int : 14; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 1; - unsigned int CNTX_BUSY_INT_ENABLE : 1; - unsigned int CNTX_EMPTY_INT_ENABLE : 1; - unsigned int : 1; - unsigned int PRIV_INSTR_INT_ENABLE : 1; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_CNTL_RING1__CI__VI { - struct { - unsigned int : 11; - unsigned int CP_VM_DOORBELL_WR_INT_ENABLE__VI : 1; - unsigned int : 2; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int : 2; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int CMP_BUSY_INT_ENABLE__VI : 1; - unsigned int CNTX_BUSY_INT_ENABLE : 1; - unsigned int CNTX_EMPTY_INT_ENABLE : 1; - unsigned int GFX_IDLE_INT_ENABLE__VI : 1; - unsigned int PRIV_INSTR_INT_ENABLE : 1; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_CNTL_RING1__SI { - struct { - unsigned int : 14; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 1; - unsigned int CNTX_BUSY_INT_ENABLE : 1; - unsigned int CNTX_EMPTY_INT_ENABLE : 1; - unsigned int : 1; - unsigned int PRIV_INSTR_INT_ENABLE : 1; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_CNTL_RING2__CI__VI { - struct { - unsigned int : 11; - unsigned int CP_VM_DOORBELL_WR_INT_ENABLE__VI : 1; - unsigned int : 2; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int : 2; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int CMP_BUSY_INT_ENABLE__VI : 1; - unsigned int CNTX_BUSY_INT_ENABLE : 1; - unsigned int CNTX_EMPTY_INT_ENABLE : 1; - unsigned int GFX_IDLE_INT_ENABLE__VI : 1; - unsigned int PRIV_INSTR_INT_ENABLE : 1; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_CNTL_RING2__SI { - struct { - unsigned int : 14; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 1; - unsigned int CNTX_BUSY_INT_ENABLE : 1; - unsigned int CNTX_EMPTY_INT_ENABLE : 1; - unsigned int : 1; - unsigned int PRIV_INSTR_INT_ENABLE : 1; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_CNTL__CI__VI { - struct { - unsigned int : 11; - unsigned int CP_VM_DOORBELL_WR_INT_ENABLE__VI : 1; - unsigned int : 2; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int : 2; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int CMP_BUSY_INT_ENABLE__VI : 1; - unsigned int CNTX_BUSY_INT_ENABLE : 1; - unsigned int CNTX_EMPTY_INT_ENABLE : 1; - unsigned int GFX_IDLE_INT_ENABLE__VI : 1; - unsigned int PRIV_INSTR_INT_ENABLE : 1; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_CNTL__SI { - struct { - unsigned int : 14; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 1; - unsigned int CNTX_BUSY_INT_ENABLE : 1; - unsigned int CNTX_EMPTY_INT_ENABLE : 1; - unsigned int : 1; - unsigned int PRIV_INSTR_INT_ENABLE : 1; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_STATUS_RING0__CI { - struct { - unsigned int : 14; - unsigned int CP_ECC_ERROR_INT_STAT : 1; - unsigned int : 2; - unsigned int WRM_POLL_TIMEOUT_INT_STAT : 1; - unsigned int : 1; - unsigned int CNTX_BUSY_INT_STAT : 1; - unsigned int CNTX_EMPTY_INT_STAT : 1; - unsigned int : 1; - unsigned int PRIV_INSTR_INT_STAT : 1; - unsigned int PRIV_REG_INT_STAT : 1; - unsigned int OPCODE_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STAT : 1; - unsigned int RESERVED_BIT_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STAT : 1; - unsigned int GENERIC1_INT_STAT : 1; - unsigned int GENERIC0_INT_STAT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_STATUS_RING0__VI { - struct { - unsigned int : 11; - unsigned int CP_VM_DOORBELL_WR_INT_STAT : 1; - unsigned int : 2; - unsigned int CP_ECC_ERROR_INT_STAT : 1; - unsigned int : 2; - unsigned int WRM_POLL_TIMEOUT_INT_STAT : 1; - unsigned int CMP_BUSY_INT_STAT : 1; - unsigned int GCNTX_BUSY_INT_STAT : 1; - unsigned int CNTX_EMPTY_INT_STAT : 1; - unsigned int GFX_IDLE_INT_STAT : 1; - unsigned int PRIV_INSTR_INT_STAT : 1; - unsigned int PRIV_REG_INT_STAT : 1; - unsigned int OPCODE_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STAT : 1; - unsigned int RESERVED_BIT_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STAT : 1; - unsigned int GENERIC1_INT_STAT : 1; - unsigned int GENERIC0_INT_STAT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_STATUS_RING0__SI { - struct { - unsigned int : 14; - unsigned int CP_ECC_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STAT : 1; - unsigned int : 1; - unsigned int CNTX_BUSY_INT_STAT : 1; - unsigned int CNTX_EMPTY_INT_STAT : 1; - unsigned int : 1; - unsigned int PRIV_INSTR_INT_STAT : 1; - unsigned int PRIV_REG_INT_STAT : 1; - unsigned int OPCODE_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STAT : 1; - unsigned int RESERVED_BIT_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_STATUS_RING1__CI__VI { - struct { - unsigned int : 11; - unsigned int CP_VM_DOORBELL_WR_INT_STAT__VI : 1; - unsigned int : 2; - unsigned int CP_ECC_ERROR_INT_STAT : 1; - unsigned int : 2; - unsigned int WRM_POLL_TIMEOUT_INT_STAT : 1; - unsigned int CMP_BUSY_INT_STAT__VI : 1; - unsigned int CNTX_BUSY_INT_STAT : 1; - unsigned int CNTX_EMPTY_INT_STAT : 1; - unsigned int GFX_IDLE_INT_STAT__VI : 1; - unsigned int PRIV_INSTR_INT_STAT : 1; - unsigned int PRIV_REG_INT_STAT : 1; - unsigned int OPCODE_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STAT : 1; - unsigned int RESERVED_BIT_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STAT : 1; - unsigned int GENERIC1_INT_STAT : 1; - unsigned int GENERIC0_INT_STAT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_STATUS_RING1__SI { - struct { - unsigned int : 14; - unsigned int CP_ECC_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STAT : 1; - unsigned int : 1; - unsigned int CNTX_BUSY_INT_STAT : 1; - unsigned int CNTX_EMPTY_INT_STAT : 1; - unsigned int : 1; - unsigned int PRIV_INSTR_INT_STAT : 1; - unsigned int PRIV_REG_INT_STAT : 1; - unsigned int OPCODE_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STAT : 1; - unsigned int RESERVED_BIT_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_STATUS_RING2__CI__VI { - struct { - unsigned int : 11; - unsigned int CP_VM_DOORBELL_WR_INT_STAT__VI : 1; - unsigned int : 2; - unsigned int CP_ECC_ERROR_INT_STAT : 1; - unsigned int : 2; - unsigned int WRM_POLL_TIMEOUT_INT_STAT : 1; - unsigned int CMP_BUSY_INT_STAT__VI : 1; - unsigned int CNTX_BUSY_INT_STAT : 1; - unsigned int CNTX_EMPTY_INT_STAT : 1; - unsigned int GFX_IDLE_INT_STAT__VI : 1; - unsigned int PRIV_INSTR_INT_STAT : 1; - unsigned int PRIV_REG_INT_STAT : 1; - unsigned int OPCODE_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STAT : 1; - unsigned int RESERVED_BIT_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STAT : 1; - unsigned int GENERIC1_INT_STAT : 1; - unsigned int GENERIC0_INT_STAT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_STATUS_RING2__SI { - struct { - unsigned int : 14; - unsigned int CP_ECC_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STAT : 1; - unsigned int : 1; - unsigned int CNTX_BUSY_INT_STAT : 1; - unsigned int CNTX_EMPTY_INT_STAT : 1; - unsigned int : 1; - unsigned int PRIV_INSTR_INT_STAT : 1; - unsigned int PRIV_REG_INT_STAT : 1; - unsigned int OPCODE_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STAT : 1; - unsigned int RESERVED_BIT_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_STATUS__CI__VI { - struct { - unsigned int : 11; - unsigned int CP_VM_DOORBELL_WR_INT_STAT__VI : 1; - unsigned int : 2; - unsigned int CP_ECC_ERROR_INT_STAT : 1; - unsigned int : 2; - unsigned int WRM_POLL_TIMEOUT_INT_STAT : 1; - unsigned int CMP_BUSY_INT_STAT__VI : 1; - unsigned int CNTX_BUSY_INT_STAT : 1; - unsigned int CNTX_EMPTY_INT_STAT : 1; - unsigned int GFX_IDLE_INT_STAT__VI : 1; - unsigned int PRIV_INSTR_INT_STAT : 1; - unsigned int PRIV_REG_INT_STAT : 1; - unsigned int OPCODE_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STAT : 1; - unsigned int RESERVED_BIT_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STAT : 1; - unsigned int GENERIC1_INT_STAT : 1; - unsigned int GENERIC0_INT_STAT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_STATUS__SI { - struct { - unsigned int : 14; - unsigned int CP_ECC_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STAT : 1; - unsigned int : 1; - unsigned int CNTX_BUSY_INT_STAT : 1; - unsigned int CNTX_EMPTY_INT_STAT : 1; - unsigned int : 1; - unsigned int PRIV_INSTR_INT_STAT : 1; - unsigned int PRIV_REG_INT_STAT : 1; - unsigned int OPCODE_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STAT : 1; - unsigned int RESERVED_BIT_ERROR_INT_STAT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_STAT_DEBUG__CI__VI { - struct { - unsigned int : 11; - unsigned int CP_VM_DOORBELL_WR_INT_ASSERTED__VI : 1; - unsigned int : 2; - unsigned int CP_ECC_ERROR_INT_ASSERTED : 1; - unsigned int : 2; - unsigned int WRM_POLL_TIMEOUT_INT_ASSERTED : 1; - unsigned int CMP_BUSY_INT_ASSERTED__VI : 1; - unsigned int CNTX_BUSY_INT_ASSERTED : 1; - unsigned int CNTX_EMPTY_INT_ASSERTED : 1; - unsigned int GFX_IDLE_INT_ASSERTED__VI : 1; - unsigned int PRIV_INSTR_INT_ASSERTED : 1; - unsigned int PRIV_REG_INT_ASSERTED : 1; - unsigned int OPCODE_ERROR_INT_ASSERTED : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ASSERTED : 1; - unsigned int RESERVED_BIT_ERROR_INT_ASSERTED : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ASSERTED : 1; - unsigned int GENERIC1_INT_ASSERTED : 1; - unsigned int GENERIC0_INT_ASSERTED : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INT_STAT_DEBUG__SI { - struct { - unsigned int : 14; - unsigned int CP_ECC_ERROR_INT_ASSERTED : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ASSERTED : 1; - unsigned int : 1; - unsigned int CNTX_BUSY_INT_ASSERTED : 1; - unsigned int CNTX_EMPTY_INT_ASSERTED : 1; - unsigned int : 1; - unsigned int PRIV_INSTR_INT_ASSERTED : 1; - unsigned int PRIV_REG_INT_ASSERTED : 1; - unsigned int OPCODE_ERROR_INT_ASSERTED : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ASSERTED : 1; - unsigned int RESERVED_BIT_ERROR_INT_ASSERTED : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IQ_WAIT_TIME1__CI__VI { - struct { - unsigned int IB_OFFLOAD : 8; - unsigned int ATOMIC_OFFLOAD : 8; - unsigned int WRM_OFFLOAD : 8; - unsigned int GWS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_IQ_WAIT_TIME2__CI__VI { - struct { - unsigned int QUE_SLEEP : 8; - unsigned int SCH_WAVE : 8; - unsigned int SEM_REARM : 8; - unsigned int DEQ_RETRY : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MAX_CONTEXT__CI__VI { - struct { - unsigned int MAX_CONTEXT : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MC_PACK_DELAY_CNT__SI__CI { - struct { - unsigned int PACK_DELAY_CNT : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MC_TAG_CNTL__CI { - struct { - unsigned int TAG_RAM_INDEX : 6; - unsigned int : 10; - unsigned int TAG_RAM_SEL : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MC_TAG_DATA__CI { - struct { - unsigned int TAG_RAM_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME0_PIPE0_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME0_PIPE0_VMID__CI__VI { - struct { - unsigned int VMID : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME0_PIPE1_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME0_PIPE1_VMID__CI__VI { - struct { - unsigned int VMID : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME0_PIPE2_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME0_PIPE_PRIORITY_CNTS__CI__VI { - struct { - unsigned int PRIORITY1_CNT : 8; - unsigned int PRIORITY2A_CNT : 8; - unsigned int PRIORITY2B_CNT : 8; - unsigned int PRIORITY3_CNT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_INT_STAT_DEBUG__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_ASSERTED__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_ASSERTED : 1; - unsigned int CP_ECC_ERROR_INT_ASSERTED : 1; - unsigned int SUA_VIOLATION_INT_STATUS__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ASSERTED : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_ASSERTED : 1; - unsigned int OPCODE_ERROR_INT_ASSERTED : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ASSERTED : 1; - unsigned int RESERVED_BIT_ERROR_INT_ASSERTED : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ASSERTED : 1; - unsigned int GENERIC1_INT_ASSERTED : 1; - unsigned int GENERIC0_INT_ASSERTED : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE0_INT_CNTL__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_ENABLE : 1; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int SUA_VIOLATION_INT_ENABLE__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE0_INT_STATUS__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_STATUS : 1; - unsigned int CP_ECC_ERROR_INT_STATUS : 1; - unsigned int SUA_VIOLATION_INT_STATUS__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STATUS : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_STATUS : 1; - unsigned int OPCODE_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STATUS : 1; - unsigned int RESERVED_BIT_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STATUS : 1; - unsigned int GENERIC1_INT_STATUS : 1; - unsigned int GENERIC0_INT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE0_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE1_INT_CNTL__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_ENABLE : 1; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int SUA_VIOLATION_INT_ENABLE__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE1_INT_STATUS__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_STATUS : 1; - unsigned int CP_ECC_ERROR_INT_STATUS : 1; - unsigned int SUA_VIOLATION_INT_STATUS__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STATUS : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_STATUS : 1; - unsigned int OPCODE_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STATUS : 1; - unsigned int RESERVED_BIT_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STATUS : 1; - unsigned int GENERIC1_INT_STATUS : 1; - unsigned int GENERIC0_INT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE1_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE2_INT_CNTL__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_ENABLE : 1; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int SUA_VIOLATION_INT_ENABLE__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE2_INT_STATUS__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_STATUS : 1; - unsigned int CP_ECC_ERROR_INT_STATUS : 1; - unsigned int SUA_VIOLATION_INT_STATUS__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STATUS : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_STATUS : 1; - unsigned int OPCODE_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STATUS : 1; - unsigned int RESERVED_BIT_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STATUS : 1; - unsigned int GENERIC1_INT_STATUS : 1; - unsigned int GENERIC0_INT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE2_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE3_INT_CNTL__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_ENABLE : 1; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int SUA_VIOLATION_INT_ENABLE__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE3_INT_STATUS__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_STATUS : 1; - unsigned int CP_ECC_ERROR_INT_STATUS : 1; - unsigned int SUA_VIOLATION_INT_STATUS__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STATUS : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_STATUS : 1; - unsigned int OPCODE_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STATUS : 1; - unsigned int RESERVED_BIT_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STATUS : 1; - unsigned int GENERIC1_INT_STATUS : 1; - unsigned int GENERIC0_INT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE3_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME1_PIPE_PRIORITY_CNTS__CI__VI { - struct { - unsigned int PRIORITY1_CNT : 8; - unsigned int PRIORITY2A_CNT : 8; - unsigned int PRIORITY2B_CNT : 8; - unsigned int PRIORITY3_CNT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_INT_STAT_DEBUG__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_ASSERTED__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_ASSERTED : 1; - unsigned int CP_ECC_ERROR_INT_ASSERTED : 1; - unsigned int SUA_VIOLATION_INT_STATUS__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ASSERTED : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_ASSERTED : 1; - unsigned int OPCODE_ERROR_INT_ASSERTED : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ASSERTED : 1; - unsigned int RESERVED_BIT_ERROR_INT_ASSERTED : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ASSERTED : 1; - unsigned int GENERIC1_INT_ASSERTED : 1; - unsigned int GENERIC0_INT_ASSERTED : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE0_INT_CNTL__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_ENABLE : 1; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int SUA_VIOLATION_INT_ENABLE__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE0_INT_STATUS__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_STATUS : 1; - unsigned int CP_ECC_ERROR_INT_STATUS : 1; - unsigned int SUA_VIOLATION_INT_STATUS__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STATUS : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_STATUS : 1; - unsigned int OPCODE_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STATUS : 1; - unsigned int RESERVED_BIT_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STATUS : 1; - unsigned int GENERIC1_INT_STATUS : 1; - unsigned int GENERIC0_INT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE0_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE1_INT_CNTL__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_ENABLE : 1; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int SUA_VIOLATION_INT_ENABLE__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE1_INT_STATUS__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_STATUS : 1; - unsigned int CP_ECC_ERROR_INT_STATUS : 1; - unsigned int SUA_VIOLATION_INT_STATUS__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STATUS : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_STATUS : 1; - unsigned int OPCODE_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STATUS : 1; - unsigned int RESERVED_BIT_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STATUS : 1; - unsigned int GENERIC1_INT_STATUS : 1; - unsigned int GENERIC0_INT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE1_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE2_INT_CNTL__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_ENABLE : 1; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int SUA_VIOLATION_INT_ENABLE__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE2_INT_STATUS__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_STATUS : 1; - unsigned int CP_ECC_ERROR_INT_STATUS : 1; - unsigned int SUA_VIOLATION_INT_STATUS__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STATUS : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_STATUS : 1; - unsigned int OPCODE_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STATUS : 1; - unsigned int RESERVED_BIT_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STATUS : 1; - unsigned int GENERIC1_INT_STATUS : 1; - unsigned int GENERIC0_INT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE2_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE3_INT_CNTL__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_ENABLE__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_ENABLE : 1; - unsigned int CP_ECC_ERROR_INT_ENABLE : 1; - unsigned int SUA_VIOLATION_INT_ENABLE__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_ENABLE : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_ENABLE : 1; - unsigned int OPCODE_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_ENABLE : 1; - unsigned int RESERVED_BIT_ERROR_INT_ENABLE : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_ENABLE : 1; - unsigned int GENERIC1_INT_ENABLE : 1; - unsigned int GENERIC0_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE3_INT_STATUS__CI__VI { - struct { - unsigned int : 12; - unsigned int CMP_QUERY_STATUS_INT_STATUS__VI : 1; - unsigned int DEQUEUE_REQUEST_INT_STATUS : 1; - unsigned int CP_ECC_ERROR_INT_STATUS : 1; - unsigned int SUA_VIOLATION_INT_STATUS__VI : 1; - unsigned int : 1; - unsigned int WRM_POLL_TIMEOUT_INT_STATUS : 1; - unsigned int : 5; - unsigned int PRIV_REG_INT_STATUS : 1; - unsigned int OPCODE_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int TIME_STAMP_INT_STATUS : 1; - unsigned int RESERVED_BIT_ERROR_INT_STATUS : 1; - unsigned int : 1; - unsigned int GENERIC2_INT_STATUS : 1; - unsigned int GENERIC1_INT_STATUS : 1; - unsigned int GENERIC0_INT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE3_PRIORITY__CI__VI { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME2_PIPE_PRIORITY_CNTS__CI__VI { - struct { - unsigned int PRIORITY1_CNT : 8; - unsigned int PRIORITY2A_CNT : 8; - unsigned int PRIORITY2B_CNT : 8; - unsigned int PRIORITY3_CNT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC1_F32_INTERRUPT__CI { - struct { - unsigned int : 1; - unsigned int PRIV_REG_INT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC1_F32_INTERRUPT__VI { - struct { - unsigned int : 1; - unsigned int PRIV_REG_INT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC1_INTR_ROUTINE_START__CI__VI { - struct { - unsigned int IR_START : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC1_PRGRM_CNTR_START__CI__VI { - struct { - unsigned int IP_START : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC2_F32_INTERRUPT__CI { - struct { - unsigned int : 1; - unsigned int PRIV_REG_INT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC2_F32_INTERRUPT__VI { - struct { - unsigned int : 1; - unsigned int PRIV_REG_INT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC2_INTR_ROUTINE_START__CI__VI { - struct { - unsigned int IR_START : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC2_PRGRM_CNTR_START__CI__VI { - struct { - unsigned int IP_START : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC_CNTL__CI__VI { - struct { - unsigned int : 4; - unsigned int MEC_INVALIDATE_ICACHE : 1; - unsigned int : 11; - unsigned int MEC_ME1_PIPE0_RESET__VI : 1; - unsigned int MEC_ME1_PIPE1_RESET__VI : 1; - unsigned int MEC_ME1_PIPE2_RESET__VI : 1; - unsigned int MEC_ME1_PIPE3_RESET__VI : 1; - unsigned int MEC_ME2_PIPE0_RESET__VI : 1; - unsigned int MEC_ME2_PIPE1_RESET__VI : 1; - unsigned int : 6; - unsigned int MEC_ME2_HALT : 1; - unsigned int MEC_ME2_STEP : 1; - unsigned int MEC_ME1_HALT : 1; - unsigned int MEC_ME1_STEP : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC_ME1_HEADER_DUMP__CI__VI { - struct { - unsigned int HEADER_DUMP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC_ME1_UCODE_ADDR__CI__VI { - struct { - unsigned int UCODE_ADDR : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC_ME1_UCODE_DATA__CI__VI { - struct { - unsigned int UCODE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC_ME2_HEADER_DUMP__CI__VI { - struct { - unsigned int HEADER_DUMP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC_ME2_UCODE_ADDR__CI__VI { - struct { - unsigned int UCODE_ADDR : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC_ME2_UCODE_DATA__CI__VI { - struct { - unsigned int UCODE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEM_SLP_CNTL { - struct { - unsigned int CP_MEM_LS_EN : 1; - unsigned int CP_MEM_DS_EN : 1; - unsigned int RESERVED__VI : 5; - unsigned int CP_LS_DS_BUSY_OVERRIDE__VI : 1; - unsigned int CP_MEM_LS_ON_DELAY : 8; - unsigned int CP_MEM_LS_OFF_DELAY : 8; - unsigned int RESERVED1 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEQ_AVAIL { - struct { - unsigned int MEQ_CNT : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEQ_STAT { - struct { - unsigned int MEQ_RPTR : 10; - unsigned int : 6; - unsigned int MEQ_WPTR : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEQ_STQ_THRESHOLD__CI__VI { - struct { - unsigned int STQ_START : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEQ_THRESHOLDS { - struct { - unsigned int MEQ1_START : 8; - unsigned int MEQ2_START : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_ATOMIC_PREOP_HI__CI__VI { - struct { - unsigned int ATOMIC_PREOP_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_ATOMIC_PREOP_LO__CI__VI { - struct { - unsigned int ATOMIC_PREOP_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_CNTL { - struct { - unsigned int : 4; - unsigned int CE_INVALIDATE_ICACHE__CI__VI : 1; - unsigned int : 1; - unsigned int PFP_INVALIDATE_ICACHE__CI__VI : 1; - unsigned int : 1; - unsigned int ME_INVALIDATE_ICACHE__CI__VI : 1; - unsigned int : 7; - unsigned int CE_PIPE0_RESET__VI : 1; - unsigned int : 1; - unsigned int PFP_PIPE0_RESET__VI : 1; - unsigned int : 1; - unsigned int ME_PIPE0_RESET__VI : 1; - unsigned int : 3; - unsigned int CE_HALT : 1; - unsigned int CE_STEP : 1; - unsigned int PFP_HALT : 1; - unsigned int PFP_STEP : 1; - unsigned int ME_HALT : 1; - unsigned int ME_STEP : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_GDS_ATOMIC0_PREOP_HI__CI__VI { - struct { - unsigned int GDS_ATOMIC0_PREOP_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_GDS_ATOMIC0_PREOP_LO__CI__VI { - struct { - unsigned int GDS_ATOMIC0_PREOP_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_GDS_ATOMIC1_PREOP_HI__CI__VI { - struct { - unsigned int GDS_ATOMIC1_PREOP_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_GDS_ATOMIC1_PREOP_LO__CI__VI { - struct { - unsigned int GDS_ATOMIC1_PREOP_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_HEADER_DUMP { - struct { - unsigned int ME_HEADER_DUMP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_INTR_ROUTINE_START__CI__VI { - struct { - unsigned int IR_START : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_MC_RADDR_HI { - struct { - unsigned int ME_MC_RADDR_HI : 16; - unsigned int : 4; - unsigned int MTYPE__VI : 2; - unsigned int CACHE_POLICY__VI : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_MC_RADDR_LO { - struct { - unsigned int ME_MC_RADDR_SWAP : 2; - unsigned int ME_MC_RADDR_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_MC_WADDR_HI { - struct { - unsigned int ME_MC_WADDR_HI : 16; - unsigned int : 4; - unsigned int MTYPE__VI : 2; - unsigned int CACHE_POLICY__VI : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_MC_WADDR_LO { - struct { - unsigned int ME_MC_WADDR_SWAP : 2; - unsigned int ME_MC_WADDR_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_MC_WDATA_HI { - struct { - unsigned int ME_MC_WDATA_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_MC_WDATA_LO { - struct { - unsigned int ME_MC_WDATA_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_PREEMPTION__SI__CI { - struct { - unsigned int ME_CNTXSW_PREEMPTION : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_PREEMPTION__VI { - struct { - unsigned int OBSOLETE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_PRGRM_CNTR_START__CI__VI { - struct { - unsigned int IP_START : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_RAM_DATA { - struct { - unsigned int ME_RAM_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_RAM_RADDR { - struct { - unsigned int ME_RAM_RADDR : 13; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ME_RAM_WADDR { - struct { - unsigned int ME_RAM_WADDR : 13; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MQD_BASE_ADDR_HI__CI__VI { - struct { - unsigned int BASE_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MQD_BASE_ADDR__CI__VI { - struct { - unsigned int : 2; - unsigned int BASE_ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MQD_CONTROL__CI { - struct { - unsigned int VMID : 4; - unsigned int : 4; - unsigned int : 1; - unsigned int : 14; - unsigned int MQD_ATC : 1; - unsigned int CACHE_POLICY : 2; - unsigned int MQD_VOLATILE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MQD_CONTROL__VI { - struct { - unsigned int VMID : 4; - unsigned int : 4; - unsigned int : 1; - unsigned int : 3; - unsigned int PROCESSING_MQD : 1; - unsigned int PROCESSING_MQD_EN : 1; - unsigned int : 9; - unsigned int MQD_ATC : 1; - unsigned int CACHE_POLICY : 1; - unsigned int : 2; - unsigned int MTYPE : 2; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_NEEDED_COUNT0_HI { - struct { - unsigned int NUM_PRIM_NEEDED_CNT0_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_NEEDED_COUNT0_LO { - struct { - unsigned int NUM_PRIM_NEEDED_CNT0_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_NEEDED_COUNT1_HI { - struct { - unsigned int NUM_PRIM_NEEDED_CNT1_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_NEEDED_COUNT1_LO { - struct { - unsigned int NUM_PRIM_NEEDED_CNT1_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_NEEDED_COUNT2_HI { - struct { - unsigned int NUM_PRIM_NEEDED_CNT2_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_NEEDED_COUNT2_LO { - struct { - unsigned int NUM_PRIM_NEEDED_CNT2_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_NEEDED_COUNT3_HI { - struct { - unsigned int NUM_PRIM_NEEDED_CNT3_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_NEEDED_COUNT3_LO { - struct { - unsigned int NUM_PRIM_NEEDED_CNT3_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_WRITTEN_COUNT0_HI { - struct { - unsigned int NUM_PRIM_WRITTEN_CNT0_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_WRITTEN_COUNT0_LO { - struct { - unsigned int NUM_PRIM_WRITTEN_CNT0_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_WRITTEN_COUNT1_HI { - struct { - unsigned int NUM_PRIM_WRITTEN_CNT1_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_WRITTEN_COUNT1_LO { - struct { - unsigned int NUM_PRIM_WRITTEN_CNT1_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_WRITTEN_COUNT2_HI { - struct { - unsigned int NUM_PRIM_WRITTEN_CNT2_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_WRITTEN_COUNT2_LO { - struct { - unsigned int NUM_PRIM_WRITTEN_CNT2_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_WRITTEN_COUNT3_HI { - struct { - unsigned int NUM_PRIM_WRITTEN_CNT3_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_NUM_PRIM_WRITTEN_COUNT3_LO { - struct { - unsigned int NUM_PRIM_WRITTEN_CNT3_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PA_CINVOC_COUNT_HI { - struct { - unsigned int CINVOC_COUNT_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PA_CINVOC_COUNT_LO { - struct { - unsigned int CINVOC_COUNT_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PA_CPRIM_COUNT_HI { - struct { - unsigned int CPRIM_COUNT_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PA_CPRIM_COUNT_LO { - struct { - unsigned int CPRIM_COUNT_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PERFCOUNTER_HI__SI { - struct { - unsigned int : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PERFCOUNTER_LO__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PERFCOUNTER_SELECT__SI { - struct { - unsigned int : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PERFMON_CNTL { - struct { - unsigned int PERFMON_STATE : 4; - unsigned int SPM_PERFMON_STATE__CI__VI : 4; - unsigned int PERFMON_ENABLE_MODE : 2; - unsigned int PERFMON_SAMPLE_ENABLE : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PERFMON_CNTX_CNTL { - struct { - unsigned int : 31; - unsigned int PERFMON_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_ATOMIC_PREOP_HI__CI__VI { - struct { - unsigned int ATOMIC_PREOP_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_ATOMIC_PREOP_LO__CI__VI { - struct { - unsigned int ATOMIC_PREOP_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_F32_INTERRUPT__CI__VI { - struct { - unsigned int : 1; - unsigned int PRIV_REG_INT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_GDS_ATOMIC0_PREOP_HI__CI__VI { - struct { - unsigned int GDS_ATOMIC0_PREOP_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_GDS_ATOMIC0_PREOP_LO__CI__VI { - struct { - unsigned int GDS_ATOMIC0_PREOP_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_GDS_ATOMIC1_PREOP_HI__CI__VI { - struct { - unsigned int GDS_ATOMIC1_PREOP_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_GDS_ATOMIC1_PREOP_LO__CI__VI { - struct { - unsigned int GDS_ATOMIC1_PREOP_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_HEADER_DUMP { - struct { - unsigned int PFP_HEADER_DUMP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_IB_CONTROL { - struct { - unsigned int IB_EN : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_INTR_ROUTINE_START__CI__VI { - struct { - unsigned int IR_START : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_LOAD_CONTROL__SI__CI { - struct { - unsigned int CONFIG_REG_EN : 1; - unsigned int CNTX_REG_EN : 1; - unsigned int : 13; - unsigned int UCONFIG_REG_EN__CI : 1; - unsigned int SH_GFX_REG_EN : 1; - unsigned int : 7; - unsigned int SH_CS_REG_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_LOAD_CONTROL__VI { - struct { - unsigned int CONFIG_REG_EN : 1; - unsigned int CNTX_REG_EN : 1; - unsigned int : 14; - unsigned int SH_GFX_REG_EN : 1; - unsigned int : 7; - unsigned int SH_CS_REG_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_PRGRM_CNTR_START__CI__VI { - struct { - unsigned int IP_START : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_UCODE_ADDR { - struct { - unsigned int UCODE_ADDR : 13; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_UCODE_DATA { - struct { - unsigned int UCODE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PIPEID__CI__VI { - struct { - unsigned int PIPE_ID : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PIPE_STATS_ADDR_HI__CI__VI { - struct { - unsigned int PIPE_STATS_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PIPE_STATS_ADDR_HI__SI { - struct { - unsigned int PIPE_STATS_ADDR_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PIPE_STATS_ADDR_LO { - struct { - unsigned int PIPE_STATS_ADDR_SWAP__SI__CI : 2; - unsigned int PIPE_STATS_ADDR_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PQ_WPTR_POLL_CNTL1__CI__VI { - struct { - unsigned int QUEUE_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PQ_WPTR_POLL_CNTL__CI__VI { - struct { - unsigned int PERIOD : 8; - unsigned int : 22; - unsigned int POLL_ACTIVE : 1; - unsigned int EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PRT_LOD_STATS_CNTL0__CI__VI { - struct { - unsigned int BU_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PRT_LOD_STATS_CNTL1__CI__VI { - struct { - unsigned int BASE_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PRT_LOD_STATS_CNTL2__CI__VI { - struct { - unsigned int BASE_HI : 2; - unsigned int INTERVAL : 8; - unsigned int RESET_CNT : 8; - unsigned int RESET_FORCE : 1; - unsigned int REPORT_AND_RESET : 1; - unsigned int MC_ENDIAN_SWAP__SI__CI : 2; - unsigned int : 1; - unsigned int MC_VMID : 4; - unsigned int : 1; - unsigned int CACHE_POLICY__VI : 1; - unsigned int : 1; - unsigned int MTYPE__VI : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PWR_CNTL__CI { - struct { - unsigned int GFX_CLK_HALT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PWR_CNTL__VI { - struct { - unsigned int GFX_CLK_HALT_ME0_PIPE0 : 1; - unsigned int GFX_CLK_HALT_ME0_PIPE1 : 1; - unsigned int : 6; - unsigned int CMP_CLK_HALT_ME1_PIPE0 : 1; - unsigned int CMP_CLK_HALT_ME1_PIPE1 : 1; - unsigned int CMP_CLK_HALT_ME1_PIPE2 : 1; - unsigned int CMP_CLK_HALT_ME1_PIPE3 : 1; - unsigned int : 4; - unsigned int CMP_CLK_HALT_ME2_PIPE0 : 1; - unsigned int CMP_CLK_HALT_ME2_PIPE1 : 1; - unsigned int CMP_CLK_HALT_ME2_PIPE2 : 1; - unsigned int CMP_CLK_HALT_ME2_PIPE3 : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PWR_CNTL__SI { - struct { - unsigned int : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_QUEUE_THRESHOLDS { - struct { - unsigned int ROQ_IB1_START : 6; - unsigned int : 2; - unsigned int ROQ_IB2_START : 6; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB0_BASE { - struct { - unsigned int RB_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB0_BASE_HI__CI__VI { - struct { - unsigned int RB_BASE_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB0_CNTL__CI { - struct { - unsigned int RB_BUFSZ : 6; - unsigned int : 2; - unsigned int RB_BLKSZ : 6; - unsigned int : 2; - unsigned int BUF_SWAP : 2; - unsigned int : 2; - unsigned int MIN_AVAILSZ : 2; - unsigned int MIN_IB_AVAILSZ : 2; - unsigned int CACHE_POLICY : 2; - unsigned int RB_VOLATILE : 1; - unsigned int RB_NO_UPDATE : 1; - unsigned int : 3; - unsigned int RB_RPTR_WR_ENA : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB0_CNTL__VI { - struct { - unsigned int RB_BUFSZ : 6; - unsigned int : 2; - unsigned int RB_BLKSZ : 6; - unsigned int : 1; - unsigned int MTYPE : 2; - unsigned int BUF_SWAP : 2; - unsigned int : 1; - unsigned int MIN_AVAILSZ : 2; - unsigned int MIN_IB_AVAILSZ : 2; - unsigned int CACHE_POLICY : 1; - unsigned int : 2; - unsigned int RB_NO_UPDATE : 1; - unsigned int : 3; - unsigned int RB_RPTR_WR_ENA : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB0_CNTL__SI { - struct { - unsigned int RB_BUFSZ : 6; - unsigned int : 2; - unsigned int RB_BLKSZ : 6; - unsigned int : 2; - unsigned int BUF_SWAP : 2; - unsigned int : 2; - unsigned int MIN_AVAILSZ : 2; - unsigned int MIN_IB_AVAILSZ : 2; - unsigned int : 1; - unsigned int : 2; - unsigned int RB_NO_UPDATE : 1; - unsigned int : 3; - unsigned int RB_RPTR_WR_ENA : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB0_RPTR { - struct { - unsigned int RB_RPTR : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB0_RPTR_ADDR { - struct { - unsigned int RB_RPTR_SWAP : 2; - unsigned int RB_RPTR_ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB0_RPTR_ADDR_HI { - struct { - unsigned int RB_RPTR_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB0_WPTR { - struct { - unsigned int RB_WPTR : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB1_BASE { - struct { - unsigned int RB_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB1_BASE_HI__CI__VI { - struct { - unsigned int RB_BASE_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB1_CNTL__SI__CI { - struct { - unsigned int RB_BUFSZ : 6; - unsigned int : 2; - unsigned int RB_BLKSZ : 6; - unsigned int : 6; - unsigned int MIN_AVAILSZ : 2; - unsigned int MIN_IB_AVAILSZ : 2; - unsigned int CACHE_POLICY__CI : 2; - unsigned int RB_VOLATILE__CI : 1; - unsigned int RB_NO_UPDATE : 1; - unsigned int : 3; - unsigned int RB_RPTR_WR_ENA : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB1_CNTL__VI { - struct { - unsigned int RB_BUFSZ : 6; - unsigned int : 2; - unsigned int RB_BLKSZ : 6; - unsigned int : 1; - unsigned int MTYPE : 2; - unsigned int : 3; - unsigned int MIN_AVAILSZ : 2; - unsigned int MIN_IB_AVAILSZ : 2; - unsigned int CACHE_POLICY : 1; - unsigned int : 2; - unsigned int RB_NO_UPDATE : 1; - unsigned int : 3; - unsigned int RB_RPTR_WR_ENA : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB1_RPTR { - struct { - unsigned int RB_RPTR : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB1_RPTR_ADDR { - struct { - unsigned int RB_RPTR_SWAP : 2; - unsigned int RB_RPTR_ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB1_RPTR_ADDR_HI { - struct { - unsigned int RB_RPTR_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB1_WPTR { - struct { - unsigned int RB_WPTR : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB2_BASE { - struct { - unsigned int RB_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB2_CNTL__SI__CI { - struct { - unsigned int RB_BUFSZ : 6; - unsigned int : 2; - unsigned int RB_BLKSZ : 6; - unsigned int : 6; - unsigned int MIN_AVAILSZ : 2; - unsigned int MIN_IB_AVAILSZ : 2; - unsigned int CACHE_POLICY__CI : 2; - unsigned int RB_VOLATILE__CI : 1; - unsigned int RB_NO_UPDATE : 1; - unsigned int : 3; - unsigned int RB_RPTR_WR_ENA : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB2_CNTL__VI { - struct { - unsigned int RB_BUFSZ : 6; - unsigned int : 2; - unsigned int RB_BLKSZ : 6; - unsigned int : 1; - unsigned int MTYPE : 2; - unsigned int : 3; - unsigned int MIN_AVAILSZ : 2; - unsigned int MIN_IB_AVAILSZ : 2; - unsigned int CACHE_POLICY : 1; - unsigned int : 2; - unsigned int RB_NO_UPDATE : 1; - unsigned int : 3; - unsigned int RB_RPTR_WR_ENA : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB2_RPTR { - struct { - unsigned int RB_RPTR : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB2_RPTR_ADDR { - struct { - unsigned int RB_RPTR_SWAP : 2; - unsigned int RB_RPTR_ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB2_RPTR_ADDR_HI { - struct { - unsigned int RB_RPTR_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB2_WPTR { - struct { - unsigned int RB_WPTR : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_BASE { - struct { - unsigned int RB_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_CNTL__CI { - struct { - unsigned int RB_BUFSZ : 6; - unsigned int : 2; - unsigned int RB_BLKSZ : 6; - unsigned int : 2; - unsigned int BUF_SWAP : 2; - unsigned int : 2; - unsigned int MIN_AVAILSZ : 2; - unsigned int MIN_IB_AVAILSZ : 2; - unsigned int CACHE_POLICY : 2; - unsigned int RB_VOLATILE : 1; - unsigned int RB_NO_UPDATE : 1; - unsigned int : 3; - unsigned int RB_RPTR_WR_ENA : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_CNTL__VI { - struct { - unsigned int RB_BUFSZ : 6; - unsigned int : 2; - unsigned int RB_BLKSZ : 6; - unsigned int : 1; - unsigned int MTYPE : 2; - unsigned int BUF_SWAP : 2; - unsigned int : 1; - unsigned int MIN_AVAILSZ : 2; - unsigned int MIN_IB_AVAILSZ : 2; - unsigned int CACHE_POLICY : 1; - unsigned int : 2; - unsigned int RB_NO_UPDATE : 1; - unsigned int : 3; - unsigned int RB_RPTR_WR_ENA : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_CNTL__SI { - struct { - unsigned int RB_BUFSZ : 6; - unsigned int : 2; - unsigned int RB_BLKSZ : 6; - unsigned int : 2; - unsigned int BUF_SWAP : 2; - unsigned int : 2; - unsigned int MIN_AVAILSZ : 2; - unsigned int MIN_IB_AVAILSZ : 2; - unsigned int : 1; - unsigned int : 2; - unsigned int RB_NO_UPDATE : 1; - unsigned int : 3; - unsigned int RB_RPTR_WR_ENA : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_OFFSET { - struct { - unsigned int RB_OFFSET : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_RPTR { - struct { - unsigned int RB_RPTR : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_RPTR_ADDR { - struct { - unsigned int RB_RPTR_SWAP : 2; - unsigned int RB_RPTR_ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_RPTR_ADDR_HI { - struct { - unsigned int RB_RPTR_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_RPTR_WR { - struct { - unsigned int RB_RPTR_WR : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_VMID { - struct { - unsigned int RB0_VMID : 4; - unsigned int : 4; - unsigned int RB1_VMID : 4; - unsigned int : 4; - unsigned int RB2_VMID : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_WPTR { - struct { - unsigned int RB_WPTR : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_WPTR_DELAY { - struct { - unsigned int PRE_WRITE_TIMER : 28; - unsigned int PRE_WRITE_LIMIT : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_WPTR_POLL_ADDR_HI__CI { - struct { - unsigned int OBSOLETE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_WPTR_POLL_ADDR_HI__VI { - struct { - unsigned int RB_WPTR_POLL_ADDR_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_WPTR_POLL_ADDR_HI__SI { - struct { - unsigned int RB_WPTR_POLL_ADDR_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_WPTR_POLL_ADDR_LO__CI { - struct { - unsigned int : 2; - unsigned int OBSOLETE : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_WPTR_POLL_ADDR_LO__VI { - struct { - unsigned int : 2; - unsigned int RB_WPTR_POLL_ADDR_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_WPTR_POLL_ADDR_LO__SI { - struct { - unsigned int : 2; - unsigned int RB_WPTR_POLL_ADDR_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_WPTR_POLL_CNTL { - struct { - unsigned int POLL_FREQUENCY : 16; - unsigned int IDLE_POLL_COUNT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RING0_PRIORITY { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RING1_PRIORITY { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RING2_PRIORITY { - struct { - unsigned int PRIORITY : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RINGID { - struct { - unsigned int RINGID : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RING_PRIORITY_CNTS { - struct { - unsigned int PRIORITY1_CNT : 8; - unsigned int PRIORITY2A_CNT : 8; - unsigned int PRIORITY2B_CNT : 8; - unsigned int PRIORITY3_CNT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ROQ1_THRESHOLDS { - struct { - unsigned int RB1_START : 8; - unsigned int RB2_START : 8; - unsigned int R0_IB1_START : 8; - unsigned int R1_IB1_START : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ROQ2_AVAIL { - struct { - unsigned int ROQ_CNT_IB2 : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ROQ2_THRESHOLDS { - struct { - unsigned int R2_IB1_START : 8; - unsigned int R0_IB2_START : 8; - unsigned int R1_IB2_START : 8; - unsigned int R2_IB2_START : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ROQ_AVAIL { - struct { - unsigned int ROQ_CNT_RING : 11; - unsigned int : 5; - unsigned int ROQ_CNT_IB1 : 11; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ROQ_IB1_STAT { - struct { - unsigned int ROQ_RPTR_INDIRECT1 : 10; - unsigned int : 6; - unsigned int ROQ_WPTR_INDIRECT1 : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ROQ_IB2_STAT { - struct { - unsigned int ROQ_RPTR_INDIRECT2 : 10; - unsigned int : 6; - unsigned int ROQ_WPTR_INDIRECT2 : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ROQ_RB_STAT { - struct { - unsigned int ROQ_RPTR_PRIMARY : 10; - unsigned int : 6; - unsigned int ROQ_WPTR_PRIMARY : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ROQ_THRESHOLDS__CI__VI { - struct { - unsigned int IB1_START : 8; - unsigned int IB2_START : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SCRATCH_DATA { - struct { - unsigned int SCRATCH_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SCRATCH_INDEX { - struct { - unsigned int SCRATCH_INDEX : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SC_PSINVOC_COUNT0_HI { - struct { - unsigned int PSINVOC_COUNT0_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SC_PSINVOC_COUNT0_LO { - struct { - unsigned int PSINVOC_COUNT0_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SC_PSINVOC_COUNT1_HI__CI__VI { - struct { - unsigned int OBSOLETE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SC_PSINVOC_COUNT1_HI__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SC_PSINVOC_COUNT1_LO__CI__VI { - struct { - unsigned int OBSOLETE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SC_PSINVOC_COUNT1_LO__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SEM_WAIT_TIMER { - struct { - unsigned int SEM_WAIT_TIMER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SIG_SEM_ADDR_HI { - struct { - unsigned int SEM_ADDR_HI : 16; - unsigned int SEM_USE_MAILBOX : 1; - unsigned int : 3; - unsigned int SEM_SIGNAL_TYPE : 1; - unsigned int : 3; - unsigned int SEM_CLIENT_CODE : 2; - unsigned int : 3; - unsigned int SEM_SELECT : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SIG_SEM_ADDR_LO { - struct { - unsigned int SEM_ADDR_SWAP : 2; - unsigned int : 1; - unsigned int SEM_ADDR_LO : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STALLED_STAT1__CI { - struct { - unsigned int RBIU_TO_DMA_NOT_RDY_TO_RCV : 1; - unsigned int : 1; - unsigned int RBIU_TO_SEM_NOT_RDY_TO_RCV : 1; - unsigned int : 1; - unsigned int RBIU_TO_MEMWR_NOT_RDY_TO_RCV : 1; - unsigned int : 5; - unsigned int ME_HAS_ACTIVE_CE_BUFFER_FLAG : 1; - unsigned int ME_HAS_ACTIVE_DE_BUFFER_FLAG : 1; - unsigned int ME_STALLED_ON_TC_WR_CONFIRM : 1; - unsigned int ME_STALLED_ON_ATOMIC_RTN_DATA : 1; - unsigned int ME_WAITING_ON_MC_READ_DATA : 1; - unsigned int ME_WAITING_ON_REG_READ_DATA : 1; - unsigned int MIU_WAITING_ON_RDREQ_FREE : 1; - unsigned int MIU_WAITING_ON_WRREQ_FREE : 1; - unsigned int : 5; - unsigned int RCIU_WAITING_ON_GDS_FREE : 1; - unsigned int RCIU_WAITING_ON_GRBM_FREE : 1; - unsigned int RCIU_WAITING_ON_VGT_FREE : 1; - unsigned int RCIU_STALLED_ON_ME_READ : 1; - unsigned int RCIU_STALLED_ON_DMA_READ : 1; - unsigned int RCIU_STALLED_ON_APPEND_READ : 1; - unsigned int RCIU_HALTED_BY_REG_VIOLATION : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STALLED_STAT1__VI { - struct { - unsigned int RBIU_TO_DMA_NOT_RDY_TO_RCV : 1; - unsigned int : 1; - unsigned int RBIU_TO_SEM_NOT_RDY_TO_RCV : 1; - unsigned int : 1; - unsigned int RBIU_TO_MEMWR_NOT_RDY_TO_RCV : 1; - unsigned int : 5; - unsigned int ME_HAS_ACTIVE_CE_BUFFER_FLAG : 1; - unsigned int ME_HAS_ACTIVE_DE_BUFFER_FLAG : 1; - unsigned int ME_STALLED_ON_TC_WR_CONFIRM : 1; - unsigned int ME_STALLED_ON_ATOMIC_RTN_DATA : 1; - unsigned int ME_WAITING_ON_TC_READ_DATA : 1; - unsigned int ME_WAITING_ON_REG_READ_DATA : 1; - unsigned int : 7; - unsigned int RCIU_WAITING_ON_GDS_FREE : 1; - unsigned int RCIU_WAITING_ON_GRBM_FREE : 1; - unsigned int RCIU_WAITING_ON_VGT_FREE : 1; - unsigned int RCIU_STALLED_ON_ME_READ : 1; - unsigned int RCIU_STALLED_ON_DMA_READ : 1; - unsigned int RCIU_STALLED_ON_APPEND_READ : 1; - unsigned int RCIU_HALTED_BY_REG_VIOLATION : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STALLED_STAT1__SI { - struct { - unsigned int RBIU_TO_DMA_NOT_RDY_TO_RCV : 1; - unsigned int : 1; - unsigned int RBIU_TO_SEM_NOT_RDY_TO_RCV : 1; - unsigned int : 1; - unsigned int RBIU_TO_MEMWR_NOT_RDY_TO_RCV : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int ME_HAS_ACTIVE_CE_BUFFER_FLAG : 1; - unsigned int ME_HAS_ACTIVE_DE_BUFFER_FLAG : 1; - unsigned int ME_STALLED_ON_TC_WR_CONFIRM : 1; - unsigned int ME_STALLED_ON_ATOMIC_RTN_DATA : 1; - unsigned int ME_WAITING_ON_MC_READ_DATA : 1; - unsigned int ME_WAITING_ON_REG_READ_DATA : 1; - unsigned int MIU_WAITING_ON_RDREQ_FREE : 1; - unsigned int MIU_WAITING_ON_WRREQ_FREE : 1; - unsigned int : 5; - unsigned int RCIU_WAITING_ON_GDS_FREE : 1; - unsigned int RCIU_WAITING_ON_GRBM_FREE : 1; - unsigned int RCIU_WAITING_ON_VGT_FREE : 1; - unsigned int RCIU_STALLED_ON_ME_READ : 1; - unsigned int RCIU_STALLED_ON_DMA_READ : 1; - unsigned int RCIU_HALTED_BY_REG_VIOLATION : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STALLED_STAT2 { - struct { - unsigned int PFP_TO_CSF_NOT_RDY_TO_RCV : 1; - unsigned int PFP_TO_MEQ_NOT_RDY_TO_RCV : 1; - unsigned int PFP_TO_RCIU_NOT_RDY_TO_RCV : 1; - unsigned int : 1; - unsigned int PFP_TO_VGT_WRITES_PENDING : 1; - unsigned int PFP_RCIU_READ_PENDING : 1; - unsigned int PFP_MIU_READ_PENDING : 1; - unsigned int PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV : 1; - unsigned int PFP_WAITING_ON_BUFFER_DATA : 1; - unsigned int ME_WAIT_ON_CE_COUNTER : 1; - unsigned int ME_WAIT_ON_AVAIL_BUFFER : 1; - unsigned int GFX_CNTX_NOT_AVAIL_TO_ME : 1; - unsigned int ME_RCIU_NOT_RDY_TO_RCV : 1; - unsigned int ME_TO_CONST_NOT_RDY_TO_RCV : 1; - unsigned int ME_WAITING_DATA_FROM_PFP : 1; - unsigned int ME_WAITING_ON_PARTIAL_FLUSH : 1; - unsigned int MEQ_TO_ME_NOT_RDY_TO_RCV : 1; - unsigned int STQ_TO_ME_NOT_RDY_TO_RCV : 1; - unsigned int ME_WAITING_DATA_FROM_STQ : 1; - unsigned int PFP_STALLED_ON_TC_WR_CONFIRM__CI__VI : 1; - unsigned int PFP_STALLED_ON_ATOMIC_RTN_DATA__CI__VI : 1; - unsigned int EOPD_FIFO_NEEDS_SC_EOP_DONE : 1; - unsigned int EOPD_FIFO_NEEDS_WR_CONFIRM : 1; - unsigned int STRMO_WR_OF_PRIM_DATA_PENDING : 1; - unsigned int PIPE_STATS_WR_DATA_PENDING : 1; - unsigned int APPEND_RDY_WAIT_ON_CS_DONE : 1; - unsigned int APPEND_RDY_WAIT_ON_PS_DONE : 1; - unsigned int APPEND_WAIT_ON_WR_CONFIRM : 1; - unsigned int APPEND_ACTIVE_PARTITION : 1; - unsigned int APPEND_WAITING_TO_SEND_MEMWRITE : 1; - unsigned int SURF_SYNC_NEEDS_IDLE_CNTXS : 1; - unsigned int SURF_SYNC_NEEDS_ALL_CLEAN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STALLED_STAT3 { - struct { - unsigned int CE_TO_CSF_NOT_RDY_TO_RCV : 1; - unsigned int CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV : 1; - unsigned int CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER : 1; - unsigned int CE_TO_RAM_INIT_NOT_RDY : 1; - unsigned int CE_TO_RAM_DUMP_NOT_RDY : 1; - unsigned int CE_TO_RAM_WRITE_NOT_RDY : 1; - unsigned int CE_TO_INC_FIFO_NOT_RDY_TO_RCV : 1; - unsigned int CE_TO_WR_FIFO_NOT_RDY_TO_RCV : 1; - unsigned int CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SI__CI : 1; - unsigned int : 1; - unsigned int CE_WAITING_ON_BUFFER_DATA : 1; - unsigned int CE_WAITING_ON_CE_BUFFER_FLAG : 1; - unsigned int CE_WAITING_ON_DE_COUNTER : 1; - unsigned int CE_WAITING_ON_DE_COUNTER_UNDERFLOW : 1; - unsigned int TCIU_WAITING_ON_FREE : 1; - unsigned int TCIU_WAITING_ON_TAGS : 1; - unsigned int CE_STALLED_ON_TC_WR_CONFIRM__VI : 1; - unsigned int CE_STALLED_ON_ATOMIC_RTN_DATA__VI : 1; - unsigned int ATCL2IU_WAITING_ON_FREE__VI : 1; - unsigned int ATCL2IU_WAITING_ON_TAGS__VI : 1; - unsigned int ATCL1_WAITING_ON_TRANS__VI : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STAT__CI { - struct { - unsigned int : 7; - unsigned int MIU_RDREQ_BUSY : 1; - unsigned int MIU_WRREQ_BUSY : 1; - unsigned int ROQ_RING_BUSY : 1; - unsigned int ROQ_INDIRECT1_BUSY : 1; - unsigned int ROQ_INDIRECT2_BUSY : 1; - unsigned int ROQ_STATE_BUSY : 1; - unsigned int DC_BUSY : 1; - unsigned int : 1; - unsigned int PFP_BUSY : 1; - unsigned int MEQ_BUSY : 1; - unsigned int ME_BUSY : 1; - unsigned int QUERY_BUSY : 1; - unsigned int SEMAPHORE_BUSY : 1; - unsigned int INTERRUPT_BUSY : 1; - unsigned int SURFACE_SYNC_BUSY : 1; - unsigned int DMA_BUSY : 1; - unsigned int RCIU_BUSY : 1; - unsigned int SCRATCH_RAM_BUSY : 1; - unsigned int CPC_CPG_BUSY : 1; - unsigned int CE_BUSY : 1; - unsigned int TCIU_BUSY : 1; - unsigned int ROQ_CE_RING_BUSY : 1; - unsigned int ROQ_CE_INDIRECT1_BUSY : 1; - unsigned int ROQ_CE_INDIRECT2_BUSY : 1; - unsigned int CP_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STAT__VI { - struct { - unsigned int : 9; - unsigned int ROQ_RING_BUSY : 1; - unsigned int ROQ_INDIRECT1_BUSY : 1; - unsigned int ROQ_INDIRECT2_BUSY : 1; - unsigned int ROQ_STATE_BUSY : 1; - unsigned int DC_BUSY : 1; - unsigned int ATCL2IU_BUSY : 1; - unsigned int PFP_BUSY : 1; - unsigned int MEQ_BUSY : 1; - unsigned int ME_BUSY : 1; - unsigned int QUERY_BUSY : 1; - unsigned int SEMAPHORE_BUSY : 1; - unsigned int INTERRUPT_BUSY : 1; - unsigned int SURFACE_SYNC_BUSY : 1; - unsigned int DMA_BUSY : 1; - unsigned int RCIU_BUSY : 1; - unsigned int SCRATCH_RAM_BUSY : 1; - unsigned int CPC_CPG_BUSY : 1; - unsigned int CE_BUSY : 1; - unsigned int TCIU_BUSY : 1; - unsigned int ROQ_CE_RING_BUSY : 1; - unsigned int ROQ_CE_INDIRECT1_BUSY : 1; - unsigned int ROQ_CE_INDIRECT2_BUSY : 1; - unsigned int CP_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STAT__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int MIU_RDREQ_BUSY : 1; - unsigned int MIU_WRREQ_BUSY : 1; - unsigned int ROQ_RING_BUSY : 1; - unsigned int ROQ_INDIRECT1_BUSY : 1; - unsigned int ROQ_INDIRECT2_BUSY : 1; - unsigned int ROQ_STATE_BUSY : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int PFP_BUSY : 1; - unsigned int MEQ_BUSY : 1; - unsigned int ME_BUSY : 1; - unsigned int QUERY_BUSY : 1; - unsigned int SEMAPHORE_BUSY : 1; - unsigned int INTERRUPT_BUSY : 1; - unsigned int SURFACE_SYNC_BUSY : 1; - unsigned int DMA_BUSY : 1; - unsigned int RCIU_BUSY : 1; - unsigned int SCRATCH_RAM_BUSY : 1; - unsigned int : 1; - unsigned int CE_BUSY : 1; - unsigned int TCIU_BUSY : 1; - unsigned int ROQ_CE_RING_BUSY : 1; - unsigned int ROQ_CE_INDIRECT1_BUSY : 1; - unsigned int ROQ_CE_INDIRECT2_BUSY : 1; - unsigned int CP_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STQ_AVAIL { - struct { - unsigned int STQ_CNT : 9; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STQ_STAT { - struct { - unsigned int STQ_RPTR : 10; - unsigned int : 6; - unsigned int : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STQ_THRESHOLDS { - struct { - unsigned int STQ0_START : 8; - unsigned int STQ1_START : 8; - unsigned int STQ2_START : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STQ_WR_STAT__CI__VI { - struct { - unsigned int STQ_WPTR : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STREAM_OUT_ADDR_HI__CI__VI { - struct { - unsigned int STREAM_OUT_ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STREAM_OUT_ADDR_HI__SI { - struct { - unsigned int STREAM_OUT_ADDR_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STREAM_OUT_ADDR_LO { - struct { - unsigned int STREAM_OUT_ADDR_SWAP__SI__CI : 2; - unsigned int STREAM_OUT_ADDR_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STRMOUT_CNTL { - struct { - unsigned int OFFSET_UPDATE_DONE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ST_BASE_HI { - struct { - unsigned int ST_BASE_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ST_BASE_LO { - struct { - unsigned int : 2; - unsigned int ST_BASE_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_ST_BUFSZ { - struct { - unsigned int ST_BUFSZ : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_CSINVOC_COUNT_HI { - struct { - unsigned int CSINVOC_COUNT_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_CSINVOC_COUNT_LO { - struct { - unsigned int CSINVOC_COUNT_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_DSINVOC_COUNT_HI { - struct { - unsigned int DSINVOC_COUNT_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_DSINVOC_COUNT_LO { - struct { - unsigned int DSINVOC_COUNT_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_GSINVOC_COUNT_HI { - struct { - unsigned int GSINVOC_COUNT_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_GSINVOC_COUNT_LO { - struct { - unsigned int GSINVOC_COUNT_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_GSPRIM_COUNT_HI { - struct { - unsigned int GSPRIM_COUNT_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_GSPRIM_COUNT_LO { - struct { - unsigned int GSPRIM_COUNT_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_HSINVOC_COUNT_HI { - struct { - unsigned int HSINVOC_COUNT_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_HSINVOC_COUNT_LO { - struct { - unsigned int HSINVOC_COUNT_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_IAPRIM_COUNT_HI { - struct { - unsigned int IAPRIM_COUNT_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_IAPRIM_COUNT_LO { - struct { - unsigned int IAPRIM_COUNT_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_IAVERT_COUNT_HI { - struct { - unsigned int IAVERT_COUNT_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_IAVERT_COUNT_LO { - struct { - unsigned int IAVERT_COUNT_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_VSINVOC_COUNT_HI { - struct { - unsigned int VSINVOC_COUNT_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VGT_VSINVOC_COUNT_LO { - struct { - unsigned int VSINVOC_COUNT_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VMID { - struct { - unsigned int VMID : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VMID_PREEMPT__CI { - struct { - unsigned int PREEMPT_REQUEST : 16; - unsigned int PREEMPT_STATUS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VMID_PREEMPT__VI { - struct { - unsigned int PREEMPT_REQUEST : 16; - unsigned int VIRT_COMMAND : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VMID_RESET__CI__VI { - struct { - unsigned int RESET_REQUEST : 16; - unsigned int RESET_STATUS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_WAIT_REG_MEM_TIMEOUT { - struct { - unsigned int WAIT_REG_MEM_TIMEOUT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_WAIT_SEM_ADDR_HI { - struct { - unsigned int SEM_ADDR_HI : 16; - unsigned int SEM_USE_MAILBOX : 1; - unsigned int : 3; - unsigned int SEM_SIGNAL_TYPE : 1; - unsigned int : 3; - unsigned int SEM_CLIENT_CODE : 2; - unsigned int : 3; - unsigned int SEM_SELECT : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_WAIT_SEM_ADDR_LO { - struct { - unsigned int SEM_ADDR_SWAP : 2; - unsigned int : 1; - unsigned int SEM_ADDR_LO : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT00__SI__VI { - struct { - unsigned int H_TOTAL : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT01__SI__VI { - struct { - unsigned int H_DISP_END : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT02__SI__VI { - struct { - unsigned int H_BLANK_START : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT03__SI__VI { - struct { - unsigned int H_BLANK_END : 5; - unsigned int H_DE_SKEW : 2; - unsigned int CR10CR11_R_DIS_B : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT04__SI__VI { - struct { - unsigned int H_SYNC_START : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT05__SI__VI { - struct { - unsigned int H_SYNC_END : 5; - unsigned int H_SYNC_SKEW : 2; - unsigned int H_BLANK_END_B5 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT06__SI__VI { - struct { - unsigned int V_TOTAL : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT07__SI__VI { - struct { - unsigned int V_TOTAL_B8 : 1; - unsigned int V_DISP_END_B8 : 1; - unsigned int V_SYNC_START_B8 : 1; - unsigned int V_BLANK_START_B8 : 1; - unsigned int LINE_CMP_B8 : 1; - unsigned int V_TOTAL_B9 : 1; - unsigned int V_DISP_END_B9 : 1; - unsigned int V_SYNC_START_B9 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT08__SI__VI { - struct { - unsigned int ROW_SCAN_START : 5; - unsigned int BYTE_PAN : 2; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT09__SI__VI { - struct { - unsigned int MAX_ROW_SCAN : 5; - unsigned int V_BLANK_START_B9 : 1; - unsigned int LINE_CMP_B9 : 1; - unsigned int DOUBLE_CHAR_HEIGHT : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT0A__SI__VI { - struct { - unsigned int CURSOR_START : 5; - unsigned int CURSOR_DISABLE : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT0B__SI__VI { - struct { - unsigned int CURSOR_END : 5; - unsigned int CURSOR_SKEW : 2; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT0C__SI__VI { - struct { - unsigned int DISP_START : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT0D__SI__VI { - struct { - unsigned int DISP_START : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT0E__SI__VI { - struct { - unsigned int CURSOR_LOC_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT0F__SI__VI { - struct { - unsigned int CURSOR_LOC_LO : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT10__SI__VI { - struct { - unsigned int V_SYNC_START : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT11__SI__VI { - struct { - unsigned int V_SYNC_END : 4; - unsigned int V_INTR_CLR : 1; - unsigned int V_INTR_EN : 1; - unsigned int SEL5_REFRESH_CYC : 1; - unsigned int C0T7_WR_ONLY : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT12__SI__VI { - struct { - unsigned int V_DISP_END : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT13__SI__VI { - struct { - unsigned int DISP_PITCH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT14__SI__VI { - struct { - unsigned int UNDRLN_LOC : 5; - unsigned int ADDR_CNT_BY4 : 1; - unsigned int DOUBLE_WORD : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT15__SI__VI { - struct { - unsigned int V_BLANK_START : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT16__SI__VI { - struct { - unsigned int V_BLANK_END : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT17__SI__VI { - struct { - unsigned int RA0_AS_A13B : 1; - unsigned int RA1_AS_A14B : 1; - unsigned int VCOUNT_BY2 : 1; - unsigned int ADDR_CNT_BY2 : 1; - unsigned int : 1; - unsigned int WRAP_A15TOA0 : 1; - unsigned int BYTE_MODE : 1; - unsigned int CRTC_SYNC_EN : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT18__SI__VI { - struct { - unsigned int LINE_CMP : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT1E__SI__VI { - struct { - unsigned int : 1; - unsigned int GRPH_DEC_RD1 : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT1F__SI__VI { - struct { - unsigned int GRPH_DEC_RD0 : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRT22__SI__VI { - struct { - unsigned int GRPH_LATCH_DATA : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC0_PIXEL_RATE_CNTL__SI { - struct { - unsigned int CRTC0_PIXEL_RATE_SOURCE : 1; - unsigned int DP_DTO0_ENABLE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC0_PIXEL_RATE_CNTL__VI { - struct { - unsigned int CRTC0_PIXEL_RATE_SOURCE : 2; - unsigned int : 2; - unsigned int DP_DTO0_ENABLE : 1; - unsigned int DP_DTO0_DS_DISABLE : 1; - unsigned int : 2; - unsigned int CRTC0_ADD_PIXEL : 1; - unsigned int CRTC0_DROP_PIXEL : 1; - unsigned int : 4; - unsigned int CRTC0_DISPOUT_FIFO_ERROR : 2; - unsigned int CRTC0_DISPOUT_ERROR_COUNT : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC1_PIXEL_RATE_CNTL__SI { - struct { - unsigned int CRTC1_PIXEL_RATE_SOURCE : 1; - unsigned int DP_DTO1_ENABLE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC1_PIXEL_RATE_CNTL__VI { - struct { - unsigned int CRTC1_PIXEL_RATE_SOURCE : 2; - unsigned int : 2; - unsigned int DP_DTO1_ENABLE : 1; - unsigned int DP_DTO1_DS_DISABLE : 1; - unsigned int : 2; - unsigned int CRTC1_ADD_PIXEL : 1; - unsigned int CRTC1_DROP_PIXEL : 1; - unsigned int : 4; - unsigned int CRTC1_DISPOUT_FIFO_ERROR : 2; - unsigned int CRTC1_DISPOUT_ERROR_COUNT : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC2_PIXEL_RATE_CNTL__SI { - struct { - unsigned int CRTC2_PIXEL_RATE_SOURCE : 1; - unsigned int DP_DTO2_ENABLE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC2_PIXEL_RATE_CNTL__VI { - struct { - unsigned int CRTC2_PIXEL_RATE_SOURCE : 2; - unsigned int : 2; - unsigned int DP_DTO2_ENABLE : 1; - unsigned int DP_DTO2_DS_DISABLE : 1; - unsigned int : 2; - unsigned int CRTC2_ADD_PIXEL : 1; - unsigned int CRTC2_DROP_PIXEL : 1; - unsigned int : 4; - unsigned int CRTC2_DISPOUT_FIFO_ERROR : 2; - unsigned int CRTC2_DISPOUT_ERROR_COUNT : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC3_PIXEL_RATE_CNTL__SI { - struct { - unsigned int CRTC3_PIXEL_RATE_SOURCE : 1; - unsigned int DP_DTO3_ENABLE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC3_PIXEL_RATE_CNTL__VI { - struct { - unsigned int CRTC3_PIXEL_RATE_SOURCE : 2; - unsigned int : 2; - unsigned int DP_DTO3_ENABLE : 1; - unsigned int DP_DTO3_DS_DISABLE : 1; - unsigned int : 2; - unsigned int CRTC3_ADD_PIXEL : 1; - unsigned int CRTC3_DROP_PIXEL : 1; - unsigned int : 4; - unsigned int CRTC3_DISPOUT_FIFO_ERROR : 2; - unsigned int CRTC3_DISPOUT_ERROR_COUNT : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC4_PIXEL_RATE_CNTL__SI { - struct { - unsigned int CRTC4_PIXEL_RATE_SOURCE : 1; - unsigned int DP_DTO4_ENABLE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC4_PIXEL_RATE_CNTL__VI { - struct { - unsigned int CRTC4_PIXEL_RATE_SOURCE : 2; - unsigned int : 2; - unsigned int DP_DTO4_ENABLE : 1; - unsigned int DP_DTO4_DS_DISABLE : 1; - unsigned int : 2; - unsigned int CRTC4_ADD_PIXEL : 1; - unsigned int CRTC4_DROP_PIXEL : 1; - unsigned int : 4; - unsigned int CRTC4_DISPOUT_FIFO_ERROR : 2; - unsigned int CRTC4_DISPOUT_ERROR_COUNT : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC5_PIXEL_RATE_CNTL__SI { - struct { - unsigned int CRTC5_PIXEL_RATE_SOURCE : 1; - unsigned int DP_DTO5_ENABLE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC5_PIXEL_RATE_CNTL__VI { - struct { - unsigned int CRTC5_PIXEL_RATE_SOURCE : 2; - unsigned int : 2; - unsigned int DP_DTO5_ENABLE : 1; - unsigned int DP_DTO5_DS_DISABLE : 1; - unsigned int : 2; - unsigned int CRTC5_ADD_PIXEL : 1; - unsigned int CRTC5_DROP_PIXEL : 1; - unsigned int : 4; - unsigned int CRTC5_DISPOUT_FIFO_ERROR : 2; - unsigned int CRTC5_DISPOUT_ERROR_COUNT : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC8_DATA__SI__VI { - struct { - unsigned int VCRTC_DATA : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC8_IDX__SI__VI { - struct { - unsigned int VCRTC_IDX : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_ALLOW_STOP_OFF_V_CNT__SI__VI { - struct { - unsigned int CRTC_ALLOW_STOP_OFF_V_CNT : 8; - unsigned int : 8; - unsigned int CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_BLACK_COLOR__SI__VI { - struct { - unsigned int CRTC_BLACK_COLOR_B_CB : 10; - unsigned int CRTC_BLACK_COLOR_G_Y : 10; - unsigned int CRTC_BLACK_COLOR_R_CR : 10; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_BLANK_CONTROL { - struct { - unsigned int CRTC_CURRENT_BLANK_STATE : 1; - unsigned int : 7; - unsigned int CRTC_BLANK_DATA_EN : 1; - unsigned int : 7; - unsigned int CRTC_BLANK_DE_MODE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_BLANK_DATA_COLOR__SI__VI { - struct { - unsigned int CRTC_BLANK_DATA_COLOR_BLUE_CB : 10; - unsigned int CRTC_BLANK_DATA_COLOR_GREEN_Y : 10; - unsigned int CRTC_BLANK_DATA_COLOR_RED_CR : 10; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CONTROL__SI { - struct { - unsigned int CRTC_MASTER_EN : 1; - unsigned int : 3; - unsigned int CRTC_SYNC_RESET_SEL : 1; - unsigned int : 3; - unsigned int CRTC_DISABLE_POINT_CNTL : 2; - unsigned int : 2; - unsigned int CRTC_START_POINT_CNTL : 1; - unsigned int CRTC_FIELD_NUMBER_CNTL : 1; - unsigned int : 2; - unsigned int CRTC_CURRENT_MASTER_EN_STATE : 1; - unsigned int : 3; - unsigned int CRTC_HBLANK_EARLY_CONTROL : 3; - unsigned int : 1; - unsigned int CRTC_DISP_READ_REQUEST_DISABLE : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int CRTC_SOF_PULL_EN : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CONTROL__VI { - struct { - unsigned int CRTC_MASTER_EN : 1; - unsigned int : 3; - unsigned int CRTC_SYNC_RESET_SEL : 1; - unsigned int : 3; - unsigned int CRTC_DISABLE_POINT_CNTL : 2; - unsigned int : 2; - unsigned int CRTC_START_POINT_CNTL : 1; - unsigned int CRTC_FIELD_NUMBER_CNTL : 1; - unsigned int CRTC_FIELD_NUMBER_POLARITY : 1; - unsigned int : 1; - unsigned int CRTC_CURRENT_MASTER_EN_STATE : 1; - unsigned int : 3; - unsigned int CRTC_HBLANK_EARLY_CONTROL : 3; - unsigned int : 1; - unsigned int CRTC_DISP_READ_REQUEST_DISABLE : 1; - unsigned int : 4; - unsigned int CRTC_SOF_PULL_EN : 1; - unsigned int CRTC_AVSYNC_LOCK_SNAPSHOT : 1; - unsigned int CRTC_AVSYNC_VSYNC_N_HSYNC_MODE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_COUNT_CONTROL__SI__VI { - struct { - unsigned int CRTC_HORZ_COUNT_BY2_EN : 1; - unsigned int CRTC_HORZ_REPETITION_COUNT : 4; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_COUNT_RESET__SI__VI { - struct { - unsigned int CRTC_RESET_FRAME_COUNT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_DOUBLE_BUFFER_CONTROL__SI__VI { - struct { - unsigned int CRTC_UPDATE_PENDING : 1; - unsigned int : 7; - unsigned int CRTC_UPDATE_INSTANTLY : 1; - unsigned int : 7; - unsigned int CRTC_BLANK_DATA_DOUBLE_BUFFER_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_DTMTEST_CNTL__SI__VI { - struct { - unsigned int CRTC_DTMTEST_CRTC_EN : 1; - unsigned int CRTC_DTMTEST_CLK_DIV : 4; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_DTMTEST_STATUS_POSITION__SI__VI { - struct { - unsigned int CRTC_DTMTEST_VERT_COUNT : 14; - unsigned int : 2; - unsigned int CRTC_DTMTEST_HORZ_COUNT : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_FLOW_CONTROL__SI__VI { - struct { - unsigned int CRTC_FLOW_CONTROL_SOURCE_SELECT : 5; - unsigned int : 3; - unsigned int CRTC_FLOW_CONTROL_POLARITY : 1; - unsigned int : 7; - unsigned int CRTC_FLOW_CONTROL_GRANULARITY : 1; - unsigned int : 7; - unsigned int CRTC_FLOW_CONTROL_INPUT_STATUS : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_FORCE_COUNT_NOW_CNTL__SI__VI { - struct { - unsigned int CRTC_FORCE_COUNT_NOW_MODE : 2; - unsigned int : 2; - unsigned int CRTC_FORCE_COUNT_NOW_CHECK__VI : 1; - unsigned int : 3; - unsigned int CRTC_FORCE_COUNT_NOW_TRIG_SEL : 1; - unsigned int : 7; - unsigned int CRTC_FORCE_COUNT_NOW_OCCURRED : 1; - unsigned int : 7; - unsigned int CRTC_FORCE_COUNT_NOW_CLEAR : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_H_BLANK_START_END__SI__VI { - struct { - unsigned int CRTC_H_BLANK_START : 14; - unsigned int : 2; - unsigned int CRTC_H_BLANK_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_H_SYNC_A_CNTL__SI__VI { - struct { - unsigned int CRTC_H_SYNC_A_POL : 1; - unsigned int : 15; - unsigned int CRTC_COMP_SYNC_A_EN : 1; - unsigned int CRTC_H_SYNC_A_CUTOFF : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_H_SYNC_A__SI__VI { - struct { - unsigned int CRTC_H_SYNC_A_START : 14; - unsigned int : 2; - unsigned int CRTC_H_SYNC_A_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_H_SYNC_B_CNTL__SI__VI { - struct { - unsigned int CRTC_H_SYNC_B_POL : 1; - unsigned int : 15; - unsigned int CRTC_COMP_SYNC_B_EN : 1; - unsigned int CRTC_H_SYNC_B_CUTOFF : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_H_SYNC_B__SI__VI { - struct { - unsigned int CRTC_H_SYNC_B_START : 14; - unsigned int : 2; - unsigned int CRTC_H_SYNC_B_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_H_TOTAL__SI__VI { - struct { - unsigned int CRTC_H_TOTAL : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_INTERLACE_CONTROL__SI__VI { - struct { - unsigned int CRTC_INTERLACE_ENABLE : 1; - unsigned int : 15; - unsigned int CRTC_INTERLACE_FORCE_NEXT_FIELD : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_INTERLACE_STATUS__SI__VI { - struct { - unsigned int CRTC_INTERLACE_CURRENT_FIELD : 1; - unsigned int CRTC_INTERLACE_NEXT_FIELD : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_INTERRUPT_CONTROL__SI__VI { - struct { - unsigned int CRTC_SNAPSHOT_INT_MSK : 1; - unsigned int CRTC_SNAPSHOT_INT_TYPE : 1; - unsigned int : 2; - unsigned int CRTC_V_UPDATE_INT_MSK : 1; - unsigned int CRTC_V_UPDATE_INT_TYPE : 1; - unsigned int : 2; - unsigned int CRTC_FORCE_COUNT_NOW_INT_MSK : 1; - unsigned int CRTC_FORCE_COUNT_NOW_INT_TYPE : 1; - unsigned int : 6; - unsigned int CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK : 1; - unsigned int CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE : 1; - unsigned int : 6; - unsigned int CRTC_TRIGA_INT_MSK : 1; - unsigned int CRTC_TRIGB_INT_MSK : 1; - unsigned int CRTC_TRIGA_INT_TYPE : 1; - unsigned int CRTC_TRIGB_INT_TYPE : 1; - unsigned int CRTC_VSYNC_NOM_INT_MSK : 1; - unsigned int CRTC_VSYNC_NOM_INT_TYPE : 1; - unsigned int CRTC_GSL_VSYNC_GAP_INT_MSK__VI : 1; - unsigned int CRTC_GSL_VSYNC_GAP_INT_TYPE__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI__VI { - struct { - unsigned int CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_MASTER_EN__SI__VI { - struct { - unsigned int CRTC_MASTER_EN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI__VI { - struct { - unsigned int CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_MVP_INBAND_CNTL_INSERT__SI__VI { - struct { - unsigned int CRTC_MVP_INBAND_OUT_MODE : 2; - unsigned int : 6; - unsigned int CRTC_MVP_INBAND_CNTL_CHAR_INSERT : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_MVP_STATUS__SI__VI { - struct { - unsigned int CRTC_FLIP_NOW_OCCURRED : 1; - unsigned int : 3; - unsigned int CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED : 1; - unsigned int : 11; - unsigned int CRTC_FLIP_NOW_CLEAR : 1; - unsigned int : 3; - unsigned int CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_NOM_VERT_POSITION__SI__VI { - struct { - unsigned int CRTC_VERT_COUNT_NOM : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_OVERSCAN_COLOR__SI__VI { - struct { - unsigned int CRTC_OVERSCAN_COLOR_BLUE : 10; - unsigned int CRTC_OVERSCAN_COLOR_GREEN : 10; - unsigned int CRTC_OVERSCAN_COLOR_RED : 10; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_PIXEL_DATA_READBACK__SI { - struct { - unsigned int : 10; - unsigned int : 10; - unsigned int : 10; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_SNAPSHOT_CONTROL__SI__VI { - struct { - unsigned int CRTC_AUTO_SNAPSHOT_TRIG_SEL : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_SNAPSHOT_FRAME__SI__VI { - struct { - unsigned int CRTC_SNAPSHOT_FRAME_COUNT : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_SNAPSHOT_POSITION__SI__VI { - struct { - unsigned int CRTC_SNAPSHOT_VERT_COUNT : 14; - unsigned int : 2; - unsigned int CRTC_SNAPSHOT_HORZ_COUNT : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_SNAPSHOT_STATUS__SI__VI { - struct { - unsigned int CRTC_SNAPSHOT_OCCURRED : 1; - unsigned int CRTC_SNAPSHOT_CLEAR : 1; - unsigned int CRTC_SNAPSHOT_MANUAL_TRIGGER : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_START_LINE_CONTROL__SI__VI { - struct { - unsigned int CRTC_PROGRESSIVE_START_LINE_EARLY : 1; - unsigned int : 7; - unsigned int CRTC_INTERLACE_START_LINE_EARLY : 1; - unsigned int : 3; - unsigned int CRTC_ADVANCED_START_LINE_POSITION__VI : 8; - unsigned int CRTC_LEGACY_REQUESTOR_EN__VI : 1; - unsigned int : 7; - unsigned int CRTC_PREFETCH_EN__VI : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_STATUS { - struct { - unsigned int CRTC_V_BLANK : 1; - unsigned int CRTC_V_ACTIVE_DISP : 1; - unsigned int CRTC_V_SYNC_A : 1; - unsigned int CRTC_V_UPDATE : 1; - unsigned int CRTC_V_START_LINE : 1; - unsigned int CRTC_V_BLANK_3D_STRUCTURE__VI : 1; - unsigned int : 10; - unsigned int CRTC_H_BLANK : 1; - unsigned int CRTC_H_ACTIVE_DISP : 1; - unsigned int CRTC_H_SYNC_A : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_STATUS_FRAME_COUNT__SI__VI { - struct { - unsigned int CRTC_FRAME_COUNT : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_STATUS_HV_COUNT__SI__VI { - struct { - unsigned int CRTC_HV_COUNT : 30; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_STATUS_POSITION { - struct { - unsigned int CRTC_VERT_COUNT : 14; - unsigned int : 2; - unsigned int CRTC_HORZ_COUNT : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_STATUS_VF_COUNT__SI__VI { - struct { - unsigned int CRTC_VF_COUNT : 30; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_STEREO_CONTROL__SI { - struct { - unsigned int : 8; - unsigned int CRTC_STEREO_SYNC_OUTPUT_POLARITY : 1; - unsigned int : 7; - unsigned int CRTC_STEREO_SYNC_SELECT_POLARITY : 1; - unsigned int : 7; - unsigned int CRTC_STEREO_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_STEREO_CONTROL__VI { - struct { - unsigned int CRTC_STEREO_SYNC_OUTPUT_LINE_NUM : 14; - unsigned int : 1; - unsigned int CRTC_STEREO_SYNC_OUTPUT_POLARITY : 1; - unsigned int CRTC_STEREO_SYNC_SELECT_POLARITY : 1; - unsigned int CRTC_STEREO_EYE_FLAG_POLARITY : 1; - unsigned int CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP : 1; - unsigned int CRTC_DISABLE_FIELD_NUM : 1; - unsigned int CRTC_DISABLE_V_BLANK_FOR_DP_FIX : 1; - unsigned int : 3; - unsigned int CRTC_STEREO_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_STEREO_FORCE_NEXT_EYE__SI__VI { - struct { - unsigned int CRTC_STEREO_FORCE_NEXT_EYE : 2; - unsigned int : 6; - unsigned int CRTC_AVSYNC_FRAME_COUNTER__VI : 8; - unsigned int CRTC_AVSYNC_LINE_COUNTER__VI : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_STEREO_STATUS__SI__VI { - struct { - unsigned int CRTC_STEREO_CURRENT_EYE : 1; - unsigned int : 7; - unsigned int CRTC_STEREO_SYNC_OUTPUT : 1; - unsigned int : 7; - unsigned int CRTC_STEREO_SYNC_SELECT : 1; - unsigned int : 3; - unsigned int CRTC_STEREO_EYE_FLAG__VI : 1; - unsigned int : 3; - unsigned int CRTC_STEREO_FORCE_NEXT_EYE_PENDING : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int CRTC_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int CRTC_TEST_DEBUG_INDEX : 8; - unsigned int CRTC_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_TEST_PATTERN_COLOR__SI__VI { - struct { - unsigned int CRTC_TEST_PATTERN_DATA : 16; - unsigned int CRTC_TEST_PATTERN_MASK : 6; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_TEST_PATTERN_CONTROL__SI__VI { - struct { - unsigned int CRTC_TEST_PATTERN_EN : 1; - unsigned int : 7; - unsigned int CRTC_TEST_PATTERN_MODE : 3; - unsigned int : 5; - unsigned int CRTC_TEST_PATTERN_DYNAMIC_RANGE : 1; - unsigned int : 7; - unsigned int CRTC_TEST_PATTERN_COLOR_FORMAT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_TEST_PATTERN_PARAMETERS__SI__VI { - struct { - unsigned int CRTC_TEST_PATTERN_INC0 : 4; - unsigned int CRTC_TEST_PATTERN_INC1 : 4; - unsigned int CRTC_TEST_PATTERN_VRES : 4; - unsigned int CRTC_TEST_PATTERN_HRES : 4; - unsigned int CRTC_TEST_PATTERN_RAMP0_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_TRIGA_CNTL__SI { - struct { - unsigned int CRTC_TRIGA_SOURCE_SELECT : 4; - unsigned int CRTC_TRIGA_POLARITY_SELECT : 3; - unsigned int : 1; - unsigned int CRTC_TRIGA_RESYNC_BYPASS_EN : 1; - unsigned int CRTC_TRIGA_INPUT_STATUS : 1; - unsigned int CRTC_TRIGA_POLARITY_STATUS : 1; - unsigned int CRTC_TRIGA_OCCURRED : 1; - unsigned int CRTC_TRIGA_RISING_EDGE_DETECT_CNTL : 2; - unsigned int : 2; - unsigned int CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL : 2; - unsigned int : 2; - unsigned int CRTC_TRIGA_FREQUENCY_SELECT : 2; - unsigned int : 2; - unsigned int CRTC_TRIGA_DELAY : 5; - unsigned int : 2; - unsigned int CRTC_TRIGA_CLEAR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_TRIGA_CNTL__VI { - struct { - unsigned int CRTC_TRIGA_SOURCE_SELECT : 5; - unsigned int CRTC_TRIGA_POLARITY_SELECT : 3; - unsigned int CRTC_TRIGA_RESYNC_BYPASS_EN : 1; - unsigned int CRTC_TRIGA_INPUT_STATUS : 1; - unsigned int CRTC_TRIGA_POLARITY_STATUS : 1; - unsigned int CRTC_TRIGA_OCCURRED : 1; - unsigned int CRTC_TRIGA_RISING_EDGE_DETECT_CNTL : 2; - unsigned int : 2; - unsigned int CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL : 2; - unsigned int : 2; - unsigned int CRTC_TRIGA_FREQUENCY_SELECT : 2; - unsigned int : 2; - unsigned int CRTC_TRIGA_DELAY : 5; - unsigned int : 2; - unsigned int CRTC_TRIGA_CLEAR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_TRIGA_MANUAL_TRIG__SI__VI { - struct { - unsigned int CRTC_TRIGA_MANUAL_TRIG : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_TRIGB_CNTL__SI { - struct { - unsigned int CRTC_TRIGB_SOURCE_SELECT : 4; - unsigned int CRTC_TRIGB_POLARITY_SELECT : 3; - unsigned int : 1; - unsigned int CRTC_TRIGB_RESYNC_BYPASS_EN : 1; - unsigned int CRTC_TRIGB_INPUT_STATUS : 1; - unsigned int CRTC_TRIGB_POLARITY_STATUS : 1; - unsigned int CRTC_TRIGB_OCCURRED : 1; - unsigned int CRTC_TRIGB_RISING_EDGE_DETECT_CNTL : 2; - unsigned int : 2; - unsigned int CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL : 2; - unsigned int : 2; - unsigned int CRTC_TRIGB_FREQUENCY_SELECT : 2; - unsigned int : 2; - unsigned int CRTC_TRIGB_DELAY : 5; - unsigned int : 2; - unsigned int CRTC_TRIGB_CLEAR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_TRIGB_CNTL__VI { - struct { - unsigned int CRTC_TRIGB_SOURCE_SELECT : 5; - unsigned int CRTC_TRIGB_POLARITY_SELECT : 3; - unsigned int CRTC_TRIGB_RESYNC_BYPASS_EN : 1; - unsigned int CRTC_TRIGB_INPUT_STATUS : 1; - unsigned int CRTC_TRIGB_POLARITY_STATUS : 1; - unsigned int CRTC_TRIGB_OCCURRED : 1; - unsigned int CRTC_TRIGB_RISING_EDGE_DETECT_CNTL : 2; - unsigned int : 2; - unsigned int CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL : 2; - unsigned int : 2; - unsigned int CRTC_TRIGB_FREQUENCY_SELECT : 2; - unsigned int : 2; - unsigned int CRTC_TRIGB_DELAY : 5; - unsigned int : 2; - unsigned int CRTC_TRIGB_CLEAR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_TRIGB_MANUAL_TRIG__SI__VI { - struct { - unsigned int CRTC_TRIGB_MANUAL_TRIG : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_UPDATE_LOCK__SI__VI { - struct { - unsigned int CRTC_UPDATE_LOCK : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_VBI_END__SI__VI { - struct { - unsigned int CRTC_VBI_V_END : 14; - unsigned int : 2; - unsigned int CRTC_VBI_H_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_VERT_SYNC_CONTROL__SI__VI { - struct { - unsigned int CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED : 1; - unsigned int : 7; - unsigned int CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR : 1; - unsigned int : 7; - unsigned int CRTC_AUTO_FORCE_VSYNC_MODE : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_VGA_PARAMETER_CAPTURE_MODE__SI__VI { - struct { - unsigned int CRTC_VGA_PARAMETER_CAPTURE_MODE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_VSYNC_NOM_INT_STATUS__SI__VI { - struct { - unsigned int CRTC_VSYNC_NOM : 1; - unsigned int : 3; - unsigned int CRTC_VSYNC_NOM_INT_CLEAR : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_V_BLANK_START_END__SI__VI { - struct { - unsigned int CRTC_V_BLANK_START : 14; - unsigned int : 2; - unsigned int CRTC_V_BLANK_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_V_SYNC_A_CNTL__SI__VI { - struct { - unsigned int CRTC_V_SYNC_A_POL : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_V_SYNC_A__SI__VI { - struct { - unsigned int CRTC_V_SYNC_A_START : 14; - unsigned int : 2; - unsigned int CRTC_V_SYNC_A_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_V_SYNC_B_CNTL__SI__VI { - struct { - unsigned int CRTC_V_SYNC_B_POL : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_V_SYNC_B__SI__VI { - struct { - unsigned int CRTC_V_SYNC_B_START : 14; - unsigned int : 2; - unsigned int CRTC_V_SYNC_B_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_V_TOTAL_CONTROL__SI__VI { - struct { - unsigned int CRTC_V_TOTAL_MIN_SEL : 1; - unsigned int : 3; - unsigned int CRTC_V_TOTAL_MAX_SEL : 1; - unsigned int : 3; - unsigned int CRTC_FORCE_LOCK_ON_EVENT : 1; - unsigned int : 3; - unsigned int CRTC_FORCE_LOCK_TO_MASTER_VSYNC : 1; - unsigned int : 2; - unsigned int CRTC_SET_V_TOTAL_MIN_MASK_EN__VI : 1; - unsigned int CRTC_SET_V_TOTAL_MIN_MASK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_V_TOTAL_INT_STATUS__SI__VI { - struct { - unsigned int CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED : 1; - unsigned int : 3; - unsigned int CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1; - unsigned int : 3; - unsigned int CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK : 1; - unsigned int : 3; - unsigned int CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_V_TOTAL_MAX__SI__VI { - struct { - unsigned int CRTC_V_TOTAL_MAX : 14; - unsigned int : 2; - unsigned int CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_V_TOTAL_MIN__SI__VI { - struct { - unsigned int CRTC_V_TOTAL_MIN : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_V_TOTAL__SI__VI { - struct { - unsigned int CRTC_V_TOTAL : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_V_UPDATE_INT_STATUS__SI__VI { - struct { - unsigned int CRTC_V_UPDATE_INT_OCCURRED : 1; - unsigned int : 7; - unsigned int CRTC_V_UPDATE_INT_CLEAR : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CSPRIV_CONNECT__CI__VI { - struct { - unsigned int DOORBELL_OFFSET : 21; - unsigned int QUEUE_ID : 3; - unsigned int : 2; - unsigned int VMID : 4; - unsigned int : 1; - unsigned int UNORD_DISP : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CSPRIV_THREAD_TRACE_EVENT__CI__VI { - struct { - unsigned int EVENT_ID : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CSPRIV_THREAD_TRACE_TG0__CI__VI { - struct { - unsigned int TGID_X : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CSPRIV_THREAD_TRACE_TG1__CI__VI { - struct { - unsigned int TGID_Y : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CSPRIV_THREAD_TRACE_TG2__CI__VI { - struct { - unsigned int TGID_Z : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CSPRIV_THREAD_TRACE_TG3__CI__VI { - struct { - unsigned int WAVE_ID_BASE : 12; - unsigned int THREADS_IN_GROUP : 12; - unsigned int PARTIAL_X_FLAG : 1; - unsigned int PARTIAL_Y_FLAG : 1; - unsigned int PARTIAL_Z_FLAG : 1; - unsigned int LAST_TG : 1; - unsigned int FIRST_TG : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CS_COPY_STATE { - struct { - unsigned int SRC_STATE_ID : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR_COLOR1__SI__VI { - struct { - unsigned int CUR_COLOR1_BLUE : 8; - unsigned int CUR_COLOR1_GREEN : 8; - unsigned int CUR_COLOR1_RED : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR_COLOR2__SI__VI { - struct { - unsigned int CUR_COLOR2_BLUE : 8; - unsigned int CUR_COLOR2_GREEN : 8; - unsigned int CUR_COLOR2_RED : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR_CONTROL__SI__VI { - struct { - unsigned int CURSOR_EN : 1; - unsigned int : 3; - unsigned int CUR_INV_TRANS_CLAMP__VI : 1; - unsigned int : 3; - unsigned int CURSOR_MODE : 2; - unsigned int : 6; - unsigned int CURSOR_2X_MAGNIFY : 1; - unsigned int : 3; - unsigned int CURSOR_FORCE_MC_ON : 1; - unsigned int : 3; - unsigned int CURSOR_URGENT_CONTROL__VI : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR_HOT_SPOT__SI__VI { - struct { - unsigned int CURSOR_HOT_SPOT_Y : 7; - unsigned int : 9; - unsigned int CURSOR_HOT_SPOT_X : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR_POSITION__SI__VI { - struct { - unsigned int CURSOR_Y_POSITION : 14; - unsigned int : 2; - unsigned int CURSOR_X_POSITION : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR_SIZE__SI__VI { - struct { - unsigned int CURSOR_HEIGHT : 7; - unsigned int : 9; - unsigned int CURSOR_WIDTH : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR_SURFACE_ADDRESS_HIGH__SI__VI { - struct { - unsigned int CURSOR_SURFACE_ADDRESS_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR_SURFACE_ADDRESS__SI__VI { - struct { - unsigned int CURSOR_SURFACE_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR_UPDATE__SI__VI { - struct { - unsigned int CURSOR_UPDATE_PENDING : 1; - unsigned int CURSOR_UPDATE_TAKEN : 1; - unsigned int : 14; - unsigned int CURSOR_UPDATE_LOCK : 1; - unsigned int : 7; - unsigned int CURSOR_DISABLE_MULTIPLE_UPDATE : 1; - unsigned int CURSOR_UPDATE_STEREO_MODE__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union D1VGA_CONTROL__SI__VI { - struct { - unsigned int D1VGA_MODE_ENABLE : 1; - unsigned int : 7; - unsigned int D1VGA_TIMING_SELECT : 1; - unsigned int D1VGA_SYNC_POLARITY_SELECT : 1; - unsigned int : 6; - unsigned int D1VGA_OVERSCAN_COLOR_EN : 1; - unsigned int : 7; - unsigned int D1VGA_ROTATE : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union D2VGA_CONTROL__SI__VI { - struct { - unsigned int D2VGA_MODE_ENABLE : 1; - unsigned int : 7; - unsigned int D2VGA_TIMING_SELECT : 1; - unsigned int D2VGA_SYNC_POLARITY_SELECT : 1; - unsigned int : 6; - unsigned int D2VGA_OVERSCAN_COLOR_EN : 1; - unsigned int : 7; - unsigned int D2VGA_ROTATE : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union D3VGA_CONTROL__SI__VI { - struct { - unsigned int D3VGA_MODE_ENABLE : 1; - unsigned int : 7; - unsigned int D3VGA_TIMING_SELECT : 1; - unsigned int D3VGA_SYNC_POLARITY_SELECT : 1; - unsigned int : 6; - unsigned int D3VGA_OVERSCAN_COLOR_EN : 1; - unsigned int : 7; - unsigned int D3VGA_ROTATE : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union D4VGA_CONTROL__SI__VI { - struct { - unsigned int D4VGA_MODE_ENABLE : 1; - unsigned int : 7; - unsigned int D4VGA_TIMING_SELECT : 1; - unsigned int D4VGA_SYNC_POLARITY_SELECT : 1; - unsigned int : 6; - unsigned int D4VGA_OVERSCAN_COLOR_EN : 1; - unsigned int : 7; - unsigned int D4VGA_ROTATE : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union D5VGA_CONTROL__SI__VI { - struct { - unsigned int D5VGA_MODE_ENABLE : 1; - unsigned int : 7; - unsigned int D5VGA_TIMING_SELECT : 1; - unsigned int D5VGA_SYNC_POLARITY_SELECT : 1; - unsigned int : 6; - unsigned int D5VGA_OVERSCAN_COLOR_EN : 1; - unsigned int : 7; - unsigned int D5VGA_ROTATE : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union D6VGA_CONTROL__SI__VI { - struct { - unsigned int D6VGA_MODE_ENABLE : 1; - unsigned int : 7; - unsigned int D6VGA_TIMING_SELECT : 1; - unsigned int D6VGA_SYNC_POLARITY_SELECT : 1; - unsigned int : 6; - unsigned int D6VGA_OVERSCAN_COLOR_EN : 1; - unsigned int : 7; - unsigned int D6VGA_ROTATE : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_AUTODETECT_CONTROL2__SI__VI { - struct { - unsigned int DAC_AUTODETECT_POWERUP_COUNTER : 8; - unsigned int DAC_AUTODETECT_TESTMODE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_AUTODETECT_CONTROL3__SI__VI { - struct { - unsigned int DAC_AUTODET_COMPARATOR_IN_DELAY : 8; - unsigned int DAC_AUTODET_COMPARATOR_OUT_DELAY : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_AUTODETECT_CONTROL__SI__VI { - struct { - unsigned int DAC_AUTODETECT_MODE : 2; - unsigned int : 6; - unsigned int DAC_AUTODETECT_FRAME_TIME_COUNTER : 8; - unsigned int DAC_AUTODETECT_CHECK_MASK : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_AUTODETECT_INT_CONTROL__SI__VI { - struct { - unsigned int DAC_AUTODETECT_ACK : 1; - unsigned int : 15; - unsigned int DAC_AUTODETECT_INT_ENABLE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_AUTODETECT_STATUS__SI__VI { - struct { - unsigned int DAC_AUTODETECT_STATUS : 1; - unsigned int : 3; - unsigned int DAC_AUTODETECT_CONNECT : 1; - unsigned int : 3; - unsigned int DAC_AUTODETECT_RED_SENSE : 2; - unsigned int : 6; - unsigned int DAC_AUTODETECT_GREEN_SENSE : 2; - unsigned int : 6; - unsigned int DAC_AUTODETECT_BLUE_SENSE : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_AUTO_CALIB_CONTROL__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 10; - unsigned int : 6; - unsigned int : 3; - unsigned int : 5; - unsigned int : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_COMPARATOR_ENABLE__SI__VI { - struct { - unsigned int DAC_COMP_DDET_REF_EN : 1; - unsigned int : 7; - unsigned int DAC_COMP_SDET_REF_EN : 1; - unsigned int : 7; - unsigned int DAC_R_ASYNC_ENABLE : 1; - unsigned int DAC_G_ASYNC_ENABLE : 1; - unsigned int DAC_B_ASYNC_ENABLE : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_COMPARATOR_OUTPUT__SI__VI { - struct { - unsigned int DAC_COMPARATOR_OUTPUT : 1; - unsigned int DAC_COMPARATOR_OUTPUT_BLUE : 1; - unsigned int DAC_COMPARATOR_OUTPUT_GREEN : 1; - unsigned int DAC_COMPARATOR_OUTPUT_RED : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_CONTROL__SI__VI { - struct { - unsigned int DAC_DFORCE_EN : 1; - unsigned int : 7; - unsigned int DAC_TV_ENABLE : 1; - unsigned int : 7; - unsigned int DAC_ZSCALE_SHIFT : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_CRC_CONTROL__SI { - struct { - unsigned int DAC_CRC_FIELD : 1; - unsigned int : 7; - unsigned int DAC_CRC_ONLY_BLANKb : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_CRC_CONTROL__VI { - struct { - unsigned int DAC_CRC_FIELD : 1; - unsigned int : 7; - unsigned int DAC_CRC_ONLY_BLANKB : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_CRC_EN__SI__VI { - struct { - unsigned int DAC_CRC_EN : 1; - unsigned int : 15; - unsigned int DAC_CRC_CONT_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_CRC_SIG_CONTROL_MASK__SI__VI { - struct { - unsigned int DAC_CRC_SIG_CONTROL_MASK : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_CRC_SIG_CONTROL__SI__VI { - struct { - unsigned int DAC_CRC_SIG_CONTROL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_CRC_SIG_RGB_MASK__SI__VI { - struct { - unsigned int DAC_CRC_SIG_BLUE_MASK : 10; - unsigned int DAC_CRC_SIG_GREEN_MASK : 10; - unsigned int DAC_CRC_SIG_RED_MASK : 10; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_CRC_SIG_RGB__SI__VI { - struct { - unsigned int DAC_CRC_SIG_BLUE : 10; - unsigned int DAC_CRC_SIG_GREEN : 10; - unsigned int DAC_CRC_SIG_RED : 10; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_DATA__SI__VI { - struct { - unsigned int DAC_DATA : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_DFT_CONFIG__SI__VI { - struct { - unsigned int DAC_DFT_CONFIG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_ENABLE__SI__VI { - struct { - unsigned int DAC_ENABLE : 1; - unsigned int DAC_RESYNC_FIFO_ENABLE__VI : 1; - unsigned int DAC_RESYNC_FIFO_POINTER_SKEW__VI : 2; - unsigned int DAC_RESYNC_FIFO_ERROR__VI : 1; - unsigned int DAC_RESYNC_FIFO_ERROR_ACK__VI : 1; - unsigned int : 2; - unsigned int DAC_RESYNC_FIFO_TVOUT_SIM__VI : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_FORCE_DATA__SI__VI { - struct { - unsigned int DAC_FORCE_DATA : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_FORCE_OUTPUT_CNTL__SI { - struct { - unsigned int DAC_FORCE_DATA_EN : 1; - unsigned int : 7; - unsigned int DAC_FORCE_DATA_SEL : 3; - unsigned int : 13; - unsigned int DAC_FORCE_DATA_ON_BLANKb_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_FORCE_OUTPUT_CNTL__VI { - struct { - unsigned int DAC_FORCE_DATA_EN : 1; - unsigned int : 7; - unsigned int DAC_FORCE_DATA_SEL : 3; - unsigned int : 13; - unsigned int DAC_FORCE_DATA_ON_BLANKB_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_MACRO_CNTL__SI { - struct { - unsigned int : 2; - unsigned int : 6; - unsigned int : 6; - unsigned int : 2; - unsigned int : 6; - unsigned int : 2; - unsigned int : 4; - unsigned int : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_MASK__SI__VI { - struct { - unsigned int DAC_MASK : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_POWERDOWN__SI__VI { - struct { - unsigned int DAC_POWERDOWN : 1; - unsigned int : 7; - unsigned int DAC_POWERDOWN_BLUE : 1; - unsigned int : 7; - unsigned int DAC_POWERDOWN_GREEN : 1; - unsigned int : 7; - unsigned int DAC_POWERDOWN_RED : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_PWR_CNTL__SI__VI { - struct { - unsigned int DAC_BG_MODE : 2; - unsigned int : 14; - unsigned int DAC_PWRCNTL : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_R_INDEX__SI__VI { - struct { - unsigned int DAC_R_INDEX : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_SOURCE_SELECT__SI__VI { - struct { - unsigned int DAC_SOURCE_SELECT : 3; - unsigned int DAC_TV_SELECT : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_STEREOSYNC_SELECT__SI__VI { - struct { - unsigned int DAC_STEREOSYNC_SELECT : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_SYNC_TRISTATE_CONTROL__SI__VI { - struct { - unsigned int DAC_HSYNCA_TRISTATE : 1; - unsigned int : 7; - unsigned int DAC_VSYNCA_TRISTATE : 1; - unsigned int : 7; - unsigned int DAC_SYNCA_TRISTATE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_W_INDEX__SI__VI { - struct { - unsigned int DAC_W_INDEX : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DATA_FORMAT__SI { - struct { - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 3; - unsigned int : 5; - unsigned int : 3; - unsigned int : 2; - unsigned int : 2; - unsigned int : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DBG_BYPASS_SRBM_ACCESS__CI { - struct { - unsigned int DBG_BYPASS_SRBM_ACCESS_EN : 1; - unsigned int DBG_APER_AD : 4; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_ALPHA_TO_MASK { - struct { - unsigned int ALPHA_TO_MASK_ENABLE : 1; - unsigned int : 7; - unsigned int ALPHA_TO_MASK_OFFSET0 : 2; - unsigned int ALPHA_TO_MASK_OFFSET1 : 2; - unsigned int ALPHA_TO_MASK_OFFSET2 : 2; - unsigned int ALPHA_TO_MASK_OFFSET3 : 2; - unsigned int OFFSET_ROUND : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_CGTT_CLK_CTRL_0 { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int RESERVED : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_COUNT_CONTROL { - struct { - unsigned int ZPASS_INCREMENT_DISABLE : 1; - unsigned int PERFECT_ZPASS_COUNTS : 1; - unsigned int : 2; - unsigned int SAMPLE_RATE : 3; - unsigned int : 1; - unsigned int ZPASS_ENABLE__CI__VI : 4; - unsigned int ZFAIL_ENABLE__CI__VI : 4; - unsigned int SFAIL_ENABLE__CI__VI : 4; - unsigned int DBFAIL_ENABLE__CI__VI : 4; - unsigned int SLICE_EVEN_ENABLE__CI__VI : 4; - unsigned int SLICE_ODD_ENABLE__CI__VI : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_CREDIT_LIMIT { - struct { - unsigned int DB_SC_TILE_CREDITS : 5; - unsigned int DB_SC_QUAD_CREDITS : 5; - unsigned int DB_CB_LQUAD_CREDITS : 3; - unsigned int : 11; - unsigned int DB_CB_TILE_CREDITS : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEBUG { - struct { - unsigned int DEBUG_STENCIL_COMPRESS_DISABLE : 1; - unsigned int DEBUG_DEPTH_COMPRESS_DISABLE : 1; - unsigned int FETCH_FULL_Z_TILE : 1; - unsigned int FETCH_FULL_STENCIL_TILE : 1; - unsigned int FORCE_Z_MODE : 2; - unsigned int DEBUG_FORCE_DEPTH_READ : 1; - unsigned int DEBUG_FORCE_STENCIL_READ : 1; - unsigned int DEBUG_FORCE_HIZ_ENABLE : 2; - unsigned int DEBUG_FORCE_HIS_ENABLE0 : 2; - unsigned int DEBUG_FORCE_HIS_ENABLE1 : 2; - unsigned int DEBUG_FAST_Z_DISABLE : 1; - unsigned int DEBUG_FAST_STENCIL_DISABLE : 1; - unsigned int DEBUG_NOOP_CULL_DISABLE : 1; - unsigned int DISABLE_SUMM_SQUADS : 1; - unsigned int DEPTH_CACHE_FORCE_MISS : 1; - unsigned int DEBUG_FORCE_FULL_Z_RANGE : 2; - unsigned int NEVER_FREE_Z_ONLY : 1; - unsigned int ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS : 1; - unsigned int DISABLE_VPORT_ZPLANE_OPTIMIZATION : 1; - unsigned int DECOMPRESS_AFTER_N_ZPLANES : 4; - unsigned int ONE_FREE_IN_FLIGHT : 1; - unsigned int FORCE_MISS_IF_NOT_INFLIGHT : 1; - unsigned int DISABLE_DEPTH_SURFACE_SYNC : 1; - unsigned int DISABLE_HTILE_SURFACE_SYNC : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEBUG2__CI__VI { - struct { - unsigned int ALLOW_COMPZ_BYTE_MASKING : 1; - unsigned int DISABLE_TC_ZRANGE_L0_CACHE : 1; - unsigned int DISABLE_TC_MASK_L0_CACHE : 1; - unsigned int DTR_ROUND_ROBIN_ARB : 1; - unsigned int DTR_PREZ_STALLS_FOR_ETF_ROOM : 1; - unsigned int DISABLE_PREZL_LPF_STALL : 1; - unsigned int ENABLE_PREZL_CB_STALL : 1; - unsigned int DISABLE_PREZL_LPF_STALL_REZ : 1; - unsigned int DISABLE_PREZL_CB_STALL_REZ : 1; - unsigned int CLK_OFF_DELAY : 5; - unsigned int DISABLE_TILE_COVERED_FOR_PS_ITER : 1; - unsigned int ENABLE_SUBTILE_GROUPING : 1; - unsigned int DISABLE_HTILE_PAIRED_PIPES : 1; - unsigned int DISABLE_NULL_EOT_FORWARDING : 1; - unsigned int DISABLE_DTT_DATA_FORWARDING : 1; - unsigned int DISABLE_QUAD_COHERENCY_STALL : 1; - unsigned int : 8; - unsigned int ENABLE_PREZ_OF_REZ_SUMM : 1; - unsigned int DISABLE_PREZL_VIEWPORT_STALL : 1; - unsigned int DISABLE_SINGLE_STENCIL_QUAD_SUMM : 1; - unsigned int DISABLE_WRITE_STALL_ON_RDWR_CONFLICT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEBUG2__SI { - struct { - unsigned int ALLOW_COMPZ_BYTE_MASKING : 1; - unsigned int DISABLE_TC_ZRANGE_L0_CACHE : 1; - unsigned int DISABLE_TC_MASK_L0_CACHE : 1; - unsigned int DTR_ROUND_ROBIN_ARB : 1; - unsigned int DTR_PREZ_STALLS_FOR_ETF_ROOM : 1; - unsigned int DISABLE_PREZL_LPF_STALL : 1; - unsigned int ENABLE_PREZL_CB_STALL : 1; - unsigned int DISABLE_PREZL_LPF_STALL_REZ : 1; - unsigned int DISABLE_PREZL_CB_STALL_REZ : 1; - unsigned int CLK_OFF_DELAY : 5; - unsigned int DISABLE_TILE_COVERED_FOR_PS_ITER : 1; - unsigned int ENABLE_SUBTILE_GROUPING : 1; - unsigned int DISABLE_HTILE_PAIRED_PIPES : 1; - unsigned int DISABLE_NULL_EOT_FORWARDING : 1; - unsigned int DISABLE_DTT_DATA_FORWARDING : 1; - unsigned int DISABLE_QUAD_COHERENCY_STALL : 1; - unsigned int : 8; - unsigned int ENABLE_PREZ_OF_REZ_SUMM : 1; - unsigned int DISABLE_PREZL_VIEWPORT_STALL : 1; - unsigned int : 1; - unsigned int DISABLE_SINGLE_STENCIL_QUAD_SUMM : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEBUG3__CI { - struct { - unsigned int : 2; - unsigned int FORCE_DB_IS_GOOD : 1; - unsigned int DISABLE_TL_SSO_NULL_SUPPRESSION : 1; - unsigned int DISABLE_HIZ_ON_VPORT_CLAMP : 1; - unsigned int EQAA_INTERPOLATE_COMP_Z : 1; - unsigned int EQAA_INTERPOLATE_SRC_Z : 1; - unsigned int DISABLE_TCP_CAM_BYPASS : 1; - unsigned int DISABLE_ZCMP_DIRTY_SUPPRESSION : 1; - unsigned int DISABLE_REDUNDANT_PLANE_FLUSHES_OPT : 1; - unsigned int DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP : 1; - unsigned int ENABLE_INCOHERENT_EQAA_READS : 1; - unsigned int DISABLE_OP_Z_DATA_FORWARDING : 1; - unsigned int DISABLE_OP_DF_BYPASS : 1; - unsigned int DISABLE_OP_DF_WRITE_COMBINE : 1; - unsigned int DISABLE_OP_DF_DIRECT_FEEDBACK : 1; - unsigned int ALLOW_RF2P_RW_COLLISION : 1; - unsigned int SLOW_PREZ_TO_A2M_OMASK_RATE : 1; - unsigned int DISABLE_OP_S_DATA_FORWARDING : 1; - unsigned int DISABLE_TC_UPDATE_WRITE_COMBINE : 1; - unsigned int DISABLE_HZ_TC_WRITE_COMBINE : 1; - unsigned int ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT : 1; - unsigned int ENABLE_TC_MA_ROUND_ROBIN_ARB : 1; - unsigned int DISABLE_RAM_READ_SUPPRESION_ON_FWD : 1; - unsigned int DISABLE_EQAA_A2M_PERF_OPT : 1; - unsigned int DISABLE_DI_DT_STALL : 1; - unsigned int ENABLE_DB_PROCESS_RESET : 1; - unsigned int DISABLE_OVERRASTERIZATION_FIX : 1; - unsigned int DONT_INSERT_CONTEXT_SUSPEND : 1; - unsigned int DONT_DELETE_CONTEXT_SUSPEND : 1; - unsigned int DB_EXTRA_DEBUG3 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEBUG3__VI { - struct { - unsigned int : 2; - unsigned int FORCE_DB_IS_GOOD : 1; - unsigned int DISABLE_TL_SSO_NULL_SUPPRESSION : 1; - unsigned int DISABLE_HIZ_ON_VPORT_CLAMP : 1; - unsigned int EQAA_INTERPOLATE_COMP_Z : 1; - unsigned int EQAA_INTERPOLATE_SRC_Z : 1; - unsigned int DISABLE_TCP_CAM_BYPASS : 1; - unsigned int DISABLE_ZCMP_DIRTY_SUPPRESSION : 1; - unsigned int DISABLE_REDUNDANT_PLANE_FLUSHES_OPT : 1; - unsigned int DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP : 1; - unsigned int ENABLE_INCOHERENT_EQAA_READS : 1; - unsigned int DISABLE_OP_Z_DATA_FORWARDING : 1; - unsigned int DISABLE_OP_DF_BYPASS : 1; - unsigned int DISABLE_OP_DF_WRITE_COMBINE : 1; - unsigned int DISABLE_OP_DF_DIRECT_FEEDBACK : 1; - unsigned int ALLOW_RF2P_RW_COLLISION : 1; - unsigned int SLOW_PREZ_TO_A2M_OMASK_RATE : 1; - unsigned int DISABLE_OP_S_DATA_FORWARDING : 1; - unsigned int DISABLE_TC_UPDATE_WRITE_COMBINE : 1; - unsigned int DISABLE_HZ_TC_WRITE_COMBINE : 1; - unsigned int ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT : 1; - unsigned int ENABLE_TC_MA_ROUND_ROBIN_ARB : 1; - unsigned int DISABLE_RAM_READ_SUPPRESION_ON_FWD : 1; - unsigned int DISABLE_EQAA_A2M_PERF_OPT : 1; - unsigned int DISABLE_DI_DT_STALL : 1; - unsigned int ENABLE_DB_PROCESS_RESET : 1; - unsigned int DISABLE_OVERRASTERIZATION_FIX : 1; - unsigned int DONT_INSERT_CONTEXT_SUSPEND : 1; - unsigned int DONT_DELETE_CONTEXT_SUSPEND : 1; - unsigned int DISABLE_4XAA_2P_DELAYED_WRITE : 1; - unsigned int DISABLE_4XAA_2P_INTERLEAVED_PMASK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEBUG3__SI { - struct { - unsigned int : 2; - unsigned int FORCE_DB_IS_GOOD : 1; - unsigned int DISABLE_TL_SSO_NULL_SUPPRESSION : 1; - unsigned int DISABLE_HIZ_ON_VPORT_CLAMP : 1; - unsigned int EQAA_INTERPOLATE_COMP_Z : 1; - unsigned int EQAA_INTERPOLATE_SRC_Z : 1; - unsigned int DISABLE_TCP_CAM_BYPASS : 1; - unsigned int DISABLE_ZCMP_DIRTY_SUPPRESSION : 1; - unsigned int : 1; - unsigned int DISABLE_REDUNDANT_PLANE_FLUSHES_OPT : 1; - unsigned int DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP : 1; - unsigned int ENABLE_INCOHERENT_EQAA_READS : 1; - unsigned int DISABLE_OP_Z_DATA_FORWARDING : 1; - unsigned int DISABLE_OP_DF_BYPASS : 1; - unsigned int DISABLE_OP_DF_WRITE_COMBINE : 1; - unsigned int DISABLE_OP_DF_DIRECT_FEEDBACK : 1; - unsigned int ALLOW_RF2P_RW_COLLISION : 1; - unsigned int SLOW_PREZ_TO_A2M_OMASK_RATE : 1; - unsigned int DISABLE_OP_S_DATA_FORWARDING : 1; - unsigned int DISABLE_TC_UPDATE_WRITE_COMBINE : 1; - unsigned int DISABLE_HZ_TC_WRITE_COMBINE : 1; - unsigned int ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT : 1; - unsigned int ENABLE_TC_MA_ROUND_ROBIN_ARB : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DB_EXTRA_DEBUG3 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEBUG4__CI { - struct { - unsigned int DISABLE_QC_Z_MASK_SUMMATION : 1; - unsigned int DISABLE_QC_STENCIL_MASK_SUMMATION : 1; - unsigned int DISABLE_RESUMM_TO_SINGLE_STENCIL : 1; - unsigned int DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL : 1; - unsigned int DB_EXTRA_DEBUG4 : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEBUG4__VI { - struct { - unsigned int DISABLE_QC_Z_MASK_SUMMATION : 1; - unsigned int DISABLE_QC_STENCIL_MASK_SUMMATION : 1; - unsigned int DISABLE_RESUMM_TO_SINGLE_STENCIL : 1; - unsigned int DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL : 1; - unsigned int DISABLE_4XAA_2P_ZD_HOLDOFF : 1; - unsigned int ENABLE_A2M_DQUAD_OPTIMIZATION : 1; - unsigned int DB_EXTRA_DEBUG4 : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEBUG4__SI { - struct { - unsigned int DISABLE_QC_Z_MASK_SUMMATION : 1; - unsigned int DISABLE_QC_STENCIL_MASK_SUMMATION : 1; - unsigned int DISABLE_RESUMM_TO_SINGLE_STENCIL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL : 1; - unsigned int DB_EXTRA_DEBUG4 : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEPTH_BOUNDS_MAX { - struct { - unsigned int MAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEPTH_BOUNDS_MIN { - struct { - unsigned int MIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEPTH_CLEAR { - struct { - unsigned int DEPTH_CLEAR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEPTH_CONTROL { - struct { - unsigned int STENCIL_ENABLE : 1; - unsigned int Z_ENABLE : 1; - unsigned int Z_WRITE_ENABLE : 1; - unsigned int DEPTH_BOUNDS_ENABLE : 1; - unsigned int ZFUNC : 3; - unsigned int BACKFACE_ENABLE : 1; - unsigned int STENCILFUNC : 3; - unsigned int : 9; - unsigned int STENCILFUNC_BF : 3; - unsigned int : 7; - unsigned int ENABLE_COLOR_WRITES_ON_DEPTH_FAIL : 1; - unsigned int DISABLE_COLOR_WRITES_ON_DEPTH_PASS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEPTH_INFO { - struct { - unsigned int ADDR5_SWIZZLE_MASK : 4; - unsigned int ARRAY_MODE__CI__VI : 4; - unsigned int PIPE_CONFIG__CI__VI : 5; - unsigned int BANK_WIDTH__CI__VI : 2; - unsigned int BANK_HEIGHT__CI__VI : 2; - unsigned int MACRO_TILE_ASPECT__CI__VI : 2; - unsigned int NUM_BANKS__CI__VI : 2; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEPTH_SIZE { - struct { - unsigned int PITCH_TILE_MAX : 11; - unsigned int HEIGHT_TILE_MAX : 11; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEPTH_SLICE { - struct { - unsigned int SLICE_TILE_MAX : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_DEPTH_VIEW { - struct { - unsigned int SLICE_START : 11; - unsigned int : 2; - unsigned int SLICE_MAX : 11; - unsigned int Z_READ_ONLY : 1; - unsigned int STENCIL_READ_ONLY : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_EQAA { - struct { - unsigned int MAX_ANCHOR_SAMPLES : 3; - unsigned int : 1; - unsigned int PS_ITER_SAMPLES : 3; - unsigned int : 1; - unsigned int MASK_EXPORT_NUM_SAMPLES : 3; - unsigned int : 1; - unsigned int ALPHA_TO_MASK_NUM_SAMPLES : 3; - unsigned int : 1; - unsigned int HIGH_QUALITY_INTERSECTIONS : 1; - unsigned int INCOHERENT_EQAA_READS : 1; - unsigned int INTERPOLATE_COMP_Z : 1; - unsigned int INTERPOLATE_SRC_Z : 1; - unsigned int STATIC_ANCHOR_ASSOCIATIONS : 1; - unsigned int ALPHA_TO_MASK_EQAA_DISABLE : 1; - unsigned int : 2; - unsigned int OVERRASTERIZATION_AMOUNT : 3; - unsigned int ENABLE_POSTZ_OVERRASTERIZATION : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_FIFO_DEPTH1 { - struct { - unsigned int MI_RDREQ_FIFO_DEPTH : 5; - unsigned int MI_WRREQ_FIFO_DEPTH : 5; - unsigned int MCC_DEPTH : 6; - unsigned int QC_DEPTH : 5; - unsigned int LTILE_PROBE_FIFO_DEPTH : 8; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_FIFO_DEPTH2 { - struct { - unsigned int EQUAD_FIFO_DEPTH : 8; - unsigned int ETILE_OP_FIFO_DEPTH : 7; - unsigned int LQUAD_FIFO_DEPTH : 10; - unsigned int LTILE_OP_FIFO_DEPTH : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_FREE_CACHELINES { - struct { - unsigned int FREE_DTILE_DEPTH : 7; - unsigned int FREE_PLANE_DEPTH : 7; - unsigned int FREE_Z_DEPTH : 7; - unsigned int FREE_HTILE_DEPTH : 4; - unsigned int QUAD_READ_REQS : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_HTILE_DATA_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_HTILE_SURFACE { - struct { - unsigned int LINEAR : 1; - unsigned int FULL_CACHE : 1; - unsigned int HTILE_USES_PRELOAD_WIN : 1; - unsigned int PRELOAD : 1; - unsigned int PREFETCH_WIDTH : 6; - unsigned int PREFETCH_HEIGHT : 6; - unsigned int DST_OUTSIDE_ZERO_TO_ONE : 1; - unsigned int TC_COMPATIBLE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_OCCLUSION_COUNT0_HI__CI__VI { - struct { - unsigned int COUNT_HI : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_OCCLUSION_COUNT0_LOW__CI__VI { - struct { - unsigned int COUNT_LOW : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_OCCLUSION_COUNT1_HI__CI__VI { - struct { - unsigned int COUNT_HI : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_OCCLUSION_COUNT1_LOW__CI__VI { - struct { - unsigned int COUNT_LOW : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_OCCLUSION_COUNT2_HI__CI__VI { - struct { - unsigned int COUNT_HI : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_OCCLUSION_COUNT2_LOW__CI__VI { - struct { - unsigned int COUNT_LOW : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_OCCLUSION_COUNT3_HI__CI__VI { - struct { - unsigned int COUNT_HI : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_OCCLUSION_COUNT3_LOW__CI__VI { - struct { - unsigned int COUNT_LOW : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER0_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int PERF_MODE1__CI__VI : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE3 : 4; - unsigned int PERF_MODE2 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER1_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int PERF_MODE1__CI__VI : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER1_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE3 : 4; - unsigned int PERF_MODE2 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER2_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int PERF_MODE1__CI__VI : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PERFCOUNTER3_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int PERF_MODE1__CI__VI : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_PRELOAD_CONTROL { - struct { - unsigned int START_X : 8; - unsigned int START_Y : 8; - unsigned int MAX_X : 8; - unsigned int MAX_Y : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_0 { - struct { - unsigned int BUSY_DATA0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_1 { - struct { - unsigned int BUSY_DATA1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_2 { - struct { - unsigned int BUSY_DATA2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_3 { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_4 { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_5 { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_6 { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_7 { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_8 { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_9 { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_A { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_B { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_C { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_D { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_E { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_READ_DEBUG_F { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_RENDER_CONTROL { - struct { - unsigned int DEPTH_CLEAR_ENABLE : 1; - unsigned int STENCIL_CLEAR_ENABLE : 1; - unsigned int DEPTH_COPY : 1; - unsigned int STENCIL_COPY : 1; - unsigned int RESUMMARIZE_ENABLE : 1; - unsigned int STENCIL_COMPRESS_DISABLE : 1; - unsigned int DEPTH_COMPRESS_DISABLE : 1; - unsigned int COPY_CENTROID : 1; - unsigned int COPY_SAMPLE : 4; - unsigned int DECOMPRESS_ENABLE__VI : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_RENDER_OVERRIDE { - struct { - unsigned int FORCE_HIZ_ENABLE : 2; - unsigned int FORCE_HIS_ENABLE0 : 2; - unsigned int FORCE_HIS_ENABLE1 : 2; - unsigned int FORCE_SHADER_Z_ORDER : 1; - unsigned int FAST_Z_DISABLE : 1; - unsigned int FAST_STENCIL_DISABLE : 1; - unsigned int NOOP_CULL_DISABLE : 1; - unsigned int FORCE_COLOR_KILL : 1; - unsigned int FORCE_Z_READ : 1; - unsigned int FORCE_STENCIL_READ : 1; - unsigned int FORCE_FULL_Z_RANGE : 2; - unsigned int FORCE_QC_SMASK_CONFLICT : 1; - unsigned int DISABLE_VIEWPORT_CLAMP : 1; - unsigned int IGNORE_SC_ZRANGE : 1; - unsigned int DISABLE_FULLY_COVERED : 1; - unsigned int FORCE_Z_LIMIT_SUMM : 2; - unsigned int MAX_TILES_IN_DTT : 5; - unsigned int DISABLE_TILE_RATE_TILES : 1; - unsigned int FORCE_Z_DIRTY : 1; - unsigned int FORCE_STENCIL_DIRTY : 1; - unsigned int FORCE_Z_VALID : 1; - unsigned int FORCE_STENCIL_VALID : 1; - unsigned int PRESERVE_COMPRESSION : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_RENDER_OVERRIDE2 { - struct { - unsigned int PARTIAL_SQUAD_LAUNCH_CONTROL : 2; - unsigned int PARTIAL_SQUAD_LAUNCH_COUNTDOWN : 3; - unsigned int DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION : 1; - unsigned int DISABLE_SMEM_EXPCLEAR_OPTIMIZATION : 1; - unsigned int DISABLE_COLOR_ON_VALIDATION : 1; - unsigned int DECOMPRESS_Z_ON_FLUSH : 1; - unsigned int DISABLE_REG_SNOOP : 1; - unsigned int DEPTH_BOUNDS_HIER_DEPTH_DISABLE : 1; - unsigned int SEPARATE_HIZS_FUNC_ENABLE__CI__VI : 1; - unsigned int HIZ_ZFUNC__CI__VI : 3; - unsigned int HIS_SFUNC_FF__CI__VI : 3; - unsigned int HIS_SFUNC_BF__CI__VI : 3; - unsigned int PRESERVE_ZRANGE__CI__VI : 1; - unsigned int PRESERVE_SRESULTS__CI__VI : 1; - unsigned int DISABLE_FAST_PASS__CI__VI : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_RING_CONTROL__CI__VI { - struct { - unsigned int COUNTER_CONTROL : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_SHADER_CONTROL { - struct { - unsigned int Z_EXPORT_ENABLE : 1; - unsigned int STENCIL_TEST_VAL_EXPORT_ENABLE : 1; - unsigned int STENCIL_OP_VAL_EXPORT_ENABLE : 1; - unsigned int : 1; - unsigned int Z_ORDER : 2; - unsigned int KILL_ENABLE : 1; - unsigned int COVERAGE_TO_MASK_ENABLE : 1; - unsigned int MASK_EXPORT_ENABLE : 1; - unsigned int EXEC_ON_HIER_FAIL : 1; - unsigned int EXEC_ON_NOOP : 1; - unsigned int ALPHA_TO_MASK_DISABLE : 1; - unsigned int DEPTH_BEFORE_SHADER : 1; - unsigned int CONSERVATIVE_Z_EXPORT : 2; - unsigned int DUAL_QUAD_DISABLE__VI : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_SRESULTS_COMPARE_STATE0 { - struct { - unsigned int COMPAREFUNC0 : 3; - unsigned int : 1; - unsigned int COMPAREVALUE0 : 8; - unsigned int COMPAREMASK0 : 8; - unsigned int : 4; - unsigned int ENABLE0 : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_SRESULTS_COMPARE_STATE1 { - struct { - unsigned int COMPAREFUNC1 : 3; - unsigned int : 1; - unsigned int COMPAREVALUE1 : 8; - unsigned int COMPAREMASK1 : 8; - unsigned int : 4; - unsigned int ENABLE1 : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_STENCILREFMASK { - struct { - unsigned int STENCILTESTVAL : 8; - unsigned int STENCILMASK : 8; - unsigned int STENCILWRITEMASK : 8; - unsigned int STENCILOPVAL : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_STENCILREFMASK_BF { - struct { - unsigned int STENCILTESTVAL_BF : 8; - unsigned int STENCILMASK_BF : 8; - unsigned int STENCILWRITEMASK_BF : 8; - unsigned int STENCILOPVAL_BF : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_STENCIL_CLEAR { - struct { - unsigned int CLEAR : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_STENCIL_CONTROL { - struct { - unsigned int STENCILFAIL : 4; - unsigned int STENCILZPASS : 4; - unsigned int STENCILZFAIL : 4; - unsigned int STENCILFAIL_BF : 4; - unsigned int STENCILZPASS_BF : 4; - unsigned int STENCILZFAIL_BF : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_STENCIL_INFO { - struct { - unsigned int FORMAT : 1; - unsigned int : 12; - unsigned int TILE_SPLIT__CI__VI : 3; - unsigned int : 4; - unsigned int TILE_MODE_INDEX : 3; - unsigned int : 4; - unsigned int ALLOW_EXPCLEAR : 1; - unsigned int : 1; - unsigned int TILE_STENCIL_DISABLE : 1; - unsigned int CLEAR_DISALLOWED__VI : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_STENCIL_READ_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_STENCIL_WRITE_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_SUBTILE_CONTROL { - struct { - unsigned int MSAA1_X : 2; - unsigned int MSAA1_Y : 2; - unsigned int MSAA2_X : 2; - unsigned int MSAA2_Y : 2; - unsigned int MSAA4_X : 2; - unsigned int MSAA4_Y : 2; - unsigned int MSAA8_X : 2; - unsigned int MSAA8_Y : 2; - unsigned int MSAA16_X : 2; - unsigned int MSAA16_Y : 2; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_WATERMARKS { - struct { - unsigned int DEPTH_FREE : 5; - unsigned int DEPTH_FLUSH : 6; - unsigned int FORCE_SUMMARIZE : 4; - unsigned int DEPTH_PENDING_FREE : 5; - unsigned int DEPTH_CACHELINE_FREE : 7; - unsigned int EARLY_Z_PANIC_DISABLE : 1; - unsigned int LATE_Z_PANIC_DISABLE : 1; - unsigned int RE_Z_PANIC_DISABLE : 1; - unsigned int AUTO_FLUSH_HTILE : 1; - unsigned int AUTO_FLUSH_QUAD : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_ZPASS_COUNT_HI { - struct { - unsigned int COUNT_HI : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_ZPASS_COUNT_LOW { - struct { - unsigned int COUNT_LOW : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_Z_INFO { - struct { - unsigned int FORMAT : 2; - unsigned int NUM_SAMPLES : 2; - unsigned int : 9; - unsigned int TILE_SPLIT__CI__VI : 3; - unsigned int : 4; - unsigned int TILE_MODE_INDEX : 3; - unsigned int DECOMPRESS_ON_N_ZPLANES__VI : 4; - unsigned int ALLOW_EXPCLEAR : 1; - unsigned int READ_SIZE : 1; - unsigned int TILE_SURFACE_ENABLE : 1; - unsigned int CLEAR_DISALLOWED__VI : 1; - unsigned int ZRANGE_PRECISION : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_Z_READ_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DB_Z_WRITE_BASE { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_AUDIO_DTO0_MODULE__SI { - struct { - unsigned int DCCG_AUDIO_DTO0_MODULE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_AUDIO_DTO0_MODULE__VI { - struct { - unsigned int DCCG_AUDIO_DTO0_MODULE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_AUDIO_DTO0_PHASE__SI { - struct { - unsigned int DCCG_AUDIO_DTO0_PHASE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_AUDIO_DTO0_PHASE__VI { - struct { - unsigned int DCCG_AUDIO_DTO0_PHASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_GATE_DISABLE_CNTL__SI { - struct { - unsigned int DISPCLK_DCCG_GATE_DISABLE : 1; - unsigned int DISPCLK_R_DCCG_GATE_DISABLE : 1; - unsigned int : 2; - unsigned int DACACLK_GATE_DISABLE : 1; - unsigned int DACBCLK_GATE_DISABLE : 1; - unsigned int DVOACLK_GATE_DISABLE : 1; - unsigned int : 1; - unsigned int SYMCLKA_GATE_DISABLE : 1; - unsigned int SYMCLKB_GATE_DISABLE : 1; - unsigned int SYMCLKC_GATE_DISABLE : 1; - unsigned int SYMCLKD_GATE_DISABLE : 1; - unsigned int SYMCLKE_GATE_DISABLE : 1; - unsigned int SYMCLKF_GATE_DISABLE : 1; - unsigned int : 2; - unsigned int PCLK_TV_GATE_DISABLE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_GATE_DISABLE_CNTL__VI { - struct { - unsigned int DISPCLK_DCCG_GATE_DISABLE : 1; - unsigned int DISPCLK_R_DCCG_GATE_DISABLE : 1; - unsigned int SCLK_GATE_DISABLE : 1; - unsigned int DPREFCLK_GATE_DISABLE : 1; - unsigned int DACACLK_GATE_DISABLE : 1; - unsigned int DACBCLK_GATE_DISABLE : 1; - unsigned int DVOACLK_GATE_DISABLE : 1; - unsigned int DPDBG_CLK_GATE_DISABLE : 1; - unsigned int DPREFCLK_R_DCCG_GATE_DISABLE : 1; - unsigned int : 7; - unsigned int PCLK_TV_GATE_DISABLE : 1; - unsigned int AOMCLK0_GATE_DISABLE : 1; - unsigned int AOMCLK1_GATE_DISABLE : 1; - unsigned int AOMCLK2_GATE_DISABLE : 1; - unsigned int DISPCLK_R_DCCG_RAMP_DISABLE : 1; - unsigned int AUDIO_DTO2_CLK_GATE_DISABLE : 1; - unsigned int DPREFCLK_GTC_GATE_DISABLE : 1; - unsigned int UNB_DB_CLK_GATE_DISABLE : 1; - unsigned int : 2; - unsigned int REFCLK_GATE_DISABLE : 1; - unsigned int REFCLK_R_DIG_GATE_DISABLE : 1; - unsigned int DSICLK_GATE_DISABLE : 1; - unsigned int BYTECLK_GATE_DISABLE : 1; - unsigned int ESCCLK_GATE_DISABLE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_TEST_CLK_SEL__SI { - struct { - unsigned int DCCG_TEST_CLK_GENERICA_SEL : 8; - unsigned int DCCG_TEST_CLK_GENERICB_SEL : 8; - unsigned int DCCG_TEST_CLK_GENERICA_INV : 1; - unsigned int : 7; - unsigned int DCCG_TEST_CLK_GENERICB_INV : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_TEST_CLK_SEL__VI { - struct { - unsigned int DCCG_TEST_CLK_GENERICA_SEL : 9; - unsigned int : 3; - unsigned int DCCG_TEST_CLK_GENERICA_INV : 1; - unsigned int : 3; - unsigned int DCCG_TEST_CLK_GENERICB_SEL : 9; - unsigned int : 3; - unsigned int DCCG_TEST_CLK_GENERICB_INV : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int DCCG_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int DCCG_TEST_DEBUG_INDEX : 8; - unsigned int DCCG_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_VPCLK_CNTL__SI { - struct { - unsigned int DCCG_VPCLK_POL : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCDEBUG_BUS_CLK1_SEL__SI__VI { - struct { - unsigned int DCDEBUG_BUS_CLK1_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCDEBUG_BUS_CLK2_SEL__SI__VI { - struct { - unsigned int DCDEBUG_BUS_CLK2_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCDEBUG_BUS_CLK3_SEL__SI__VI { - struct { - unsigned int DCDEBUG_BUS_CLK3_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCDEBUG_BUS_CLK4_SEL__SI__VI { - struct { - unsigned int DCDEBUG_BUS_CLK4_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCDEBUG_OUT_CNTL__SI { - struct { - unsigned int DCDEBUG_BLOCK_SEL : 5; - unsigned int DCDEBUG_OUT_EN : 1; - unsigned int DCDEBUG_OUT_PIN_SEL : 1; - unsigned int DCDEBUG_OUT_TEST_DATA_EN : 1; - unsigned int DCDEBUG_OUT_TEST_DATA : 12; - unsigned int DCDEBUG_OUT_SEL : 2; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCDEBUG_OUT_CNTL__VI { - struct { - unsigned int DCDEBUG_BLOCK_SEL : 5; - unsigned int : 1; - unsigned int DCDEBUG_OUT_EN : 1; - unsigned int DCDEBUG_OUT_PIN_SEL : 1; - unsigned int DCDEBUG_OUT_TEST_DATA_EN : 1; - unsigned int DCDEBUG_OUT_TEST_DATA : 12; - unsigned int DCDEBUG_OUT_SEL : 2; - unsigned int DCDEBUG_OUT_24BIT_SEL : 1; - unsigned int DCDEBUG_CLK_SEL : 5; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCDEBUG_OUT_PIN_OVERRIDE__SI { - struct { - unsigned int DCDEBUG_OUT_OVERRIDE1_PIN_SEL : 4; - unsigned int DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL : 5; - unsigned int : 3; - unsigned int DCDEBUG_OUT_OVERRIDE1_EN : 1; - unsigned int : 3; - unsigned int DCDEBUG_OUT_OVERRIDE2_PIN_SEL : 4; - unsigned int DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL : 5; - unsigned int : 3; - unsigned int DCDEBUG_OUT_OVERRIDE2_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCDEBUG_OUT_PIN_OVERRIDE__VI { - struct { - unsigned int DCDEBUG_OUT_OVERRIDE1_PIN_SEL : 5; - unsigned int DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL : 5; - unsigned int : 2; - unsigned int DCDEBUG_OUT_OVERRIDE1_EN : 1; - unsigned int : 2; - unsigned int DCDEBUG_OUT_OVERRIDE2_PIN_SEL : 5; - unsigned int DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL : 5; - unsigned int : 3; - unsigned int DCDEBUG_OUT_OVERRIDE2_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG1__SI { - struct { - unsigned int DOUT_DCIO_MVP_DVOCNTL_A0_REG : 2; - unsigned int DOUT_DCIO_MVP_DVOCNTL_MASK_REG : 2; - unsigned int DOUT_DCIO_MVP_DVOCNTL_EN_REG : 2; - unsigned int DOUT_DCIO_MVP_DVOCNTL_A0 : 2; - unsigned int DOUT_DCIO_MVP_DVOCNTL_SEL0 : 2; - unsigned int DOUT_DCIO_MVP_DVOCNTL_EN : 2; - unsigned int DOUT_DCIO_MVP_DVOCLK_C : 1; - unsigned int DOUT_DCIO_DVOCNTL1_A0_REG : 1; - unsigned int DOUT_DCIO_DVOCNTL1_A0_PREMUX : 1; - unsigned int DOUT_DCIO_DVOCNTL1_A0 : 1; - unsigned int DOUT_DCIO_DVOCNTL1_EN_REG : 1; - unsigned int DOUT_DCIO_DVO_HSYNC_TRISTATE : 1; - unsigned int DOUT_DCIO_DVO_CLK_TRISTATE : 1; - unsigned int DOUT_DCIO_DVOCNTL1_EN_PREMUX : 1; - unsigned int DOUT_DCIO_DVOCNTL1_EN : 1; - unsigned int DOUT_DCIO_DVOCNTL1_MUX : 1; - unsigned int DOUT_DCIO_DVOCNTL1_MASK_REG : 1; - unsigned int DOUT_DCIO_DVO_ENABLE : 1; - unsigned int DOUT_DCIO_DVO_VSYNC_TRISTATE : 1; - unsigned int DOUT_DCIO_DVO_RATE_SEL : 1; - unsigned int DOUT_DCIO_DVOCNTL1_SEL0_PREMUX : 1; - unsigned int DOUT_DCIO_DVOCNTL1_SEL0 : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG1__VI { - struct { - unsigned int DCO_DCIO_MVP_DVOCNTL_A0_REG : 2; - unsigned int DCO_DCIO_MVP_DVOCNTL_MASK_REG : 2; - unsigned int DCO_DCIO_MVP_DVOCNTL_EN_REG : 2; - unsigned int DCO_DCIO_MVP_DVOCNTL_A0 : 2; - unsigned int DCO_DCIO_MVP_DVOCNTL_SEL0 : 2; - unsigned int DCO_DCIO_MVP_DVOCNTL_EN : 2; - unsigned int DCO_DCIO_MVP_DVOCLK_C : 1; - unsigned int DCO_DCIO_DVOCNTL1_A0_REG : 1; - unsigned int DCO_DCIO_DVOCNTL1_A0_PREMUX : 1; - unsigned int DCO_DCIO_DVOCNTL1_A0 : 1; - unsigned int DCO_DCIO_DVOCNTL1_EN_REG : 1; - unsigned int DCO_DCIO_DVO_HSYNC_TRISTATE : 1; - unsigned int DCO_DCIO_DVO_CLK_TRISTATE : 1; - unsigned int DCO_DCIO_DVOCNTL1_EN_PREMUX : 1; - unsigned int DCO_DCIO_DVOCNTL1_EN : 1; - unsigned int DCO_DCIO_DVOCNTL1_MUX : 1; - unsigned int DCO_DCIO_DVOCNTL1_MASK_REG : 1; - unsigned int DCO_DCIO_DVO_ENABLE : 1; - unsigned int DCO_DCIO_DVO_VSYNC_TRISTATE : 1; - unsigned int DCO_DCIO_DVO_RATE_SEL : 1; - unsigned int DCO_DCIO_DVOCNTL1_SEL0_PREMUX : 1; - unsigned int DCO_DCIO_DVOCNTL1_SEL0 : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG2__SI__VI { - struct { - unsigned int DCIO_DEBUG2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG3__SI__VI { - struct { - unsigned int DCIO_DEBUG3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG4__SI__VI { - struct { - unsigned int DCIO_DEBUG4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG5__SI__VI { - struct { - unsigned int DCIO_DEBUG5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG6__SI__VI { - struct { - unsigned int DCIO_DEBUG6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG7__SI__VI { - struct { - unsigned int DCIO_DEBUG7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG__SI__VI { - struct { - unsigned int DCIO_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_IMPCAL_CNTL_AB__SI { - struct { - unsigned int CALR_CNTL_OVERRIDE : 4; - unsigned int : 1; - unsigned int IMPCAL_SOFT_RESET : 1; - unsigned int : 2; - unsigned int IMPCAL_STATUS : 2; - unsigned int : 2; - unsigned int IMPCAL_ARB_STATE : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_IMPCAL_CNTL_CD__SI__VI { - struct { - unsigned int CALR_CNTL_OVERRIDE : 4; - unsigned int : 1; - unsigned int IMPCAL_SOFT_RESET : 1; - unsigned int : 2; - unsigned int IMPCAL_STATUS : 2; - unsigned int : 2; - unsigned int IMPCAL_ARB_STATE : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_IMPCAL_CNTL_EF__SI__VI { - struct { - unsigned int CALR_CNTL_OVERRIDE : 4; - unsigned int : 1; - unsigned int IMPCAL_SOFT_RESET : 1; - unsigned int : 2; - unsigned int IMPCAL_STATUS : 2; - unsigned int : 2; - unsigned int IMPCAL_ARB_STATE : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int DCI_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int DCI_TEST_DEBUG_INDEX : 8; - unsigned int DCI_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_CRC_CONTROL__SI__VI { - struct { - unsigned int DCP_CRC_ENABLE : 1; - unsigned int : 1; - unsigned int DCP_CRC_SOURCE_SEL : 3; - unsigned int : 3; - unsigned int DCP_CRC_LINE_SEL : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_CRC_CURRENT__SI__VI { - struct { - unsigned int DCP_CRC_CURRENT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_CRC_LAST__SI__VI { - struct { - unsigned int DCP_CRC_LAST : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_CRC_MASK__SI__VI { - struct { - unsigned int DCP_CRC_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_DEBUG__SI__VI { - struct { - unsigned int DCP_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI__VI { - struct { - unsigned int DCP_LB_GAP_BETWEEN_CHUNK_20BPP : 4; - unsigned int DCP_LB_GAP_BETWEEN_CHUNK_30BPP : 5; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int DCP_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int DCP_TEST_DEBUG_INDEX : 8; - unsigned int DCP_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_ACE_CNTL_MISC__SI__VI { - struct { - unsigned int ABM1_ACE_REG_WR_MISSED_FRAME : 1; - unsigned int : 7; - unsigned int ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_ACE_OFFSET_SLOPE_0__SI__VI { - struct { - unsigned int ABM1_ACE_SLOPE_0 : 15; - unsigned int : 1; - unsigned int ABM1_ACE_OFFSET_0 : 11; - unsigned int : 4; - unsigned int ABM1_ACE_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_ACE_OFFSET_SLOPE_1__SI__VI { - struct { - unsigned int ABM1_ACE_SLOPE_1 : 15; - unsigned int : 1; - unsigned int ABM1_ACE_OFFSET_1 : 11; - unsigned int : 4; - unsigned int ABM1_ACE_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_ACE_OFFSET_SLOPE_2__SI__VI { - struct { - unsigned int ABM1_ACE_SLOPE_2 : 15; - unsigned int : 1; - unsigned int ABM1_ACE_OFFSET_2 : 11; - unsigned int : 4; - unsigned int ABM1_ACE_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_ACE_OFFSET_SLOPE_3__SI__VI { - struct { - unsigned int ABM1_ACE_SLOPE_3 : 15; - unsigned int : 1; - unsigned int ABM1_ACE_OFFSET_3 : 11; - unsigned int : 4; - unsigned int ABM1_ACE_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_ACE_OFFSET_SLOPE_4__SI__VI { - struct { - unsigned int ABM1_ACE_SLOPE_4 : 15; - unsigned int : 1; - unsigned int ABM1_ACE_OFFSET_4 : 11; - unsigned int : 4; - unsigned int ABM1_ACE_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_ACE_THRES_12__SI__VI { - struct { - unsigned int ABM1_ACE_THRES_1 : 10; - unsigned int : 6; - unsigned int ABM1_ACE_THRES_2 : 10; - unsigned int : 5; - unsigned int ABM1_ACE_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_ACE_THRES_34__SI__VI { - struct { - unsigned int ABM1_ACE_THRES_3 : 10; - unsigned int : 6; - unsigned int ABM1_ACE_THRES_4 : 10; - unsigned int : 2; - unsigned int ABM1_ACE_IGNORE_MASTER_LOCK_EN : 1; - unsigned int ABM1_ACE_READBACK_DB_REG_VALUE_EN : 1; - unsigned int ABM1_ACE_DBUF_REG_UPDATE_PENDING : 1; - unsigned int ABM1_ACE_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_BL_MASTER_LOCK__SI__VI { - struct { - unsigned int : 31; - unsigned int ABM1_BL_MASTER_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_CNTL__SI__VI { - struct { - unsigned int ABM1_EN : 1; - unsigned int : 7; - unsigned int ABM1_SOURCE_SELECT : 3; - unsigned int : 20; - unsigned int ABM1_BLANK_MODE_SUPPORT_ENABLE__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_DEBUG_MISC__SI__VI { - struct { - unsigned int ABM1_HG_FORCE_INTERRUPT : 1; - unsigned int : 7; - unsigned int ABM1_LS_FORCE_INTERRUPT : 1; - unsigned int : 7; - unsigned int ABM1_BL_FORCE_INTERRUPT : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HGLS_REG_READ_PROGRESS__SI__VI { - struct { - unsigned int ABM1_HG_REG_READ_IN_PROGRESS : 1; - unsigned int ABM1_LS_REG_READ_IN_PROGRESS : 1; - unsigned int ABM1_BL_REG_READ_IN_PROGRESS : 1; - unsigned int : 5; - unsigned int ABM1_HG_REG_READ_MISSED_FRAME : 1; - unsigned int ABM1_LS_REG_READ_MISSED_FRAME : 1; - unsigned int ABM1_BL_REG_READ_MISSED_FRAME : 1; - unsigned int : 5; - unsigned int ABM1_HG_REG_READ_MISSED_FRAME_CLEAR : 1; - unsigned int : 7; - unsigned int ABM1_LS_REG_READ_MISSED_FRAME_CLEAR : 1; - unsigned int : 6; - unsigned int ABM1_BL_REG_READ_MISSED_FRAME_CLEAR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__SI__VI { - struct { - unsigned int ABM1_HG_BIN_17_24_SHIFT_INDEX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__SI__VI { - struct { - unsigned int ABM1_HG_BIN_1_32_SHIFT_FLAG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__SI__VI { - struct { - unsigned int ABM1_HG_BIN_1_8_SHIFT_INDEX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__SI__VI { - struct { - unsigned int ABM1_HG_BIN_25_32_SHIFT_INDEX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__SI__VI { - struct { - unsigned int ABM1_HG_BIN_9_16_SHIFT_INDEX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_MISC_CTRL__SI { - struct { - unsigned int ABM1_HG_NUM_OF_BINS_SEL : 2; - unsigned int : 6; - unsigned int ABM1_HG_VMAX_SEL : 1; - unsigned int : 3; - unsigned int ABM1_HG_FINE_MODE_BIN_SEL : 1; - unsigned int : 3; - unsigned int ABM1_HG_BIN_BITWIDTH_SIZE_SEL : 2; - unsigned int : 2; - unsigned int ABM1_OVR_SCAN_PIXEL_PROCESS_EN : 1; - unsigned int : 5; - unsigned int ABM1_HGLS_IGNORE_MASTER_LOCK_EN : 1; - unsigned int ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN : 1; - unsigned int ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START : 1; - unsigned int ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL : 1; - unsigned int ABM1_DBUF_HGLS_REG_UPDATE_PENDING : 1; - unsigned int ABM1_HGLS_REG_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_MISC_CTRL__VI { - struct { - unsigned int ABM1_HG_NUM_OF_BINS_SEL : 2; - unsigned int : 6; - unsigned int ABM1_HG_VMAX_SEL : 1; - unsigned int : 3; - unsigned int ABM1_HG_FINE_MODE_BIN_SEL : 1; - unsigned int : 3; - unsigned int ABM1_HG_BIN_BITWIDTH_SIZE_SEL : 2; - unsigned int : 2; - unsigned int ABM1_OVR_SCAN_PIXEL_PROCESS_EN : 1; - unsigned int : 2; - unsigned int ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN : 1; - unsigned int ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL : 3; - unsigned int : 1; - unsigned int ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START : 1; - unsigned int ABM1_HGLS_IGNORE_MASTER_LOCK_EN : 1; - unsigned int ABM1_DBUF_HGLS_REG_UPDATE_PENDING : 1; - unsigned int ABM1_HGLS_REG_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_10__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_10 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_11__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_11 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_12__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_12 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_13__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_13 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_14__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_14 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_15__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_15 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_16__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_16 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_17__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_17 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_18__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_18 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_19__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_19 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_1__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_20__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_20 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_21__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_21 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_22__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_22 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_23__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_23 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_24__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_24 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_2__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_3__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_4__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_5__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_6__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_7__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_8__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_8 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_RESULT_9__SI__VI { - struct { - unsigned int ABM1_HG_RESULT_9 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_HG_SAMPLE_RATE__SI__VI { - struct { - unsigned int ABM1_HG_SAMPLE_RATE_COUNT_EN : 1; - unsigned int ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER : 1; - unsigned int : 6; - unsigned int ABM1_HG_SAMPLE_RATE_FRAME_COUNT : 8; - unsigned int ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET : 8; - unsigned int : 7; - unsigned int ABM1_HGLS_REG_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_IPCSC_COEFF_SEL__SI__VI { - struct { - unsigned int ABM1_IPCSC_COEFF_SEL_B : 4; - unsigned int : 4; - unsigned int ABM1_IPCSC_COEFF_SEL_G : 4; - unsigned int : 4; - unsigned int ABM1_IPCSC_COEFF_SEL_R : 4; - unsigned int : 11; - unsigned int ABM1_HGLS_REG_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__SI__VI { - struct { - unsigned int ABM1_LS_FILTERED_MIN_LUMA : 10; - unsigned int : 6; - unsigned int ABM1_LS_FILTERED_MAX_LUMA : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__SI__VI { - struct { - unsigned int ABM1_LS_MAX_PIXEL_VALUE_COUNT : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_LS_MIN_MAX_LUMA__SI__VI { - struct { - unsigned int ABM1_LS_MIN_LUMA : 10; - unsigned int : 6; - unsigned int ABM1_LS_MAX_LUMA : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__SI__VI { - struct { - unsigned int ABM1_LS_MIN_PIXEL_VALUE_THRES : 10; - unsigned int : 6; - unsigned int ABM1_LS_MAX_PIXEL_VALUE_THRES : 10; - unsigned int : 5; - unsigned int ABM1_HGLS_REG_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__SI__VI { - struct { - unsigned int ABM1_LS_MIN_PIXEL_VALUE_COUNT : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_LS_OVR_SCAN_BIN__SI__VI { - struct { - unsigned int ABM1_LS_OVR_SCAN_BIN : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_LS_PIXEL_COUNT__SI__VI { - struct { - unsigned int ABM1_LS_PIXEL_COUNT : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_LS_SAMPLE_RATE__SI__VI { - struct { - unsigned int ABM1_LS_SAMPLE_RATE_COUNT_EN : 1; - unsigned int ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER : 1; - unsigned int : 6; - unsigned int ABM1_LS_SAMPLE_RATE_FRAME_COUNT : 8; - unsigned int ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET : 8; - unsigned int : 7; - unsigned int ABM1_HGLS_REG_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_LS_SUM_OF_LUMA__SI__VI { - struct { - unsigned int ABM1_LS_SUM_OF_LUMA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_DMCU_SCRATCH__SI__VI { - struct { - unsigned int DMCU_SCRATCH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GENERICA__SI { - struct { - unsigned int GENERICA_EN : 1; - unsigned int : 7; - unsigned int GENERICA_SEL : 4; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GENERICA__VI { - struct { - unsigned int GENERICA_EN : 1; - unsigned int : 6; - unsigned int GENERICA_SEL : 5; - unsigned int GENERICA_UNIPHY_REFDIV_CLK_SEL : 3; - unsigned int : 1; - unsigned int GENERICA_UNIPHY_FBDIV_CLK_SEL : 3; - unsigned int : 1; - unsigned int GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL : 3; - unsigned int : 1; - unsigned int GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GENERICB__SI__VI { - struct { - unsigned int GENERICB_EN : 1; - unsigned int : 7; - unsigned int GENERICB_SEL : 4; - unsigned int GENERICB_UNIPHY_REFDIV_CLK_SEL__VI : 3; - unsigned int : 1; - unsigned int GENERICB_UNIPHY_FBDIV_CLK_SEL__VI : 3; - unsigned int : 1; - unsigned int GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__VI : 3; - unsigned int : 1; - unsigned int GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__VI : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC1_A__SI__VI { - struct { - unsigned int DC_GPIO_DDC1CLK_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC1DATA_A : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC1_EN__SI__VI { - struct { - unsigned int DC_GPIO_DDC1CLK_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC1DATA_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC1_MASK__SI__VI { - struct { - unsigned int DC_GPIO_DDC1CLK_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC1CLK_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC1CLK_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC1DATA_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC1DATA_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC1DATA_RECV : 1; - unsigned int : 1; - unsigned int AUX_PAD1_MODE : 1; - unsigned int : 3; - unsigned int AUX1_POL : 1; - unsigned int : 1; - unsigned int ALLOW_HW_DDC1_PD_EN__VI : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC1CLK_STR : 4; - unsigned int DC_GPIO_DDC1DATA_STR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC1_Y__SI__VI { - struct { - unsigned int DC_GPIO_DDC1CLK_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC1DATA_Y : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC2_A__SI__VI { - struct { - unsigned int DC_GPIO_DDC2CLK_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC2DATA_A : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC2_EN__SI__VI { - struct { - unsigned int DC_GPIO_DDC2CLK_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC2DATA_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC2_MASK__SI__VI { - struct { - unsigned int DC_GPIO_DDC2CLK_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC2CLK_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC2CLK_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC2DATA_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC2DATA_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC2DATA_RECV : 1; - unsigned int : 1; - unsigned int AUX_PAD2_MODE : 1; - unsigned int : 3; - unsigned int AUX2_POL : 1; - unsigned int : 1; - unsigned int ALLOW_HW_DDC2_PD_EN__VI : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC2CLK_STR : 4; - unsigned int DC_GPIO_DDC2DATA_STR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC2_Y__SI__VI { - struct { - unsigned int DC_GPIO_DDC2CLK_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC2DATA_Y : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC3_A__SI__VI { - struct { - unsigned int DC_GPIO_DDC3CLK_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC3DATA_A : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC3_EN__SI__VI { - struct { - unsigned int DC_GPIO_DDC3CLK_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC3DATA_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC3_MASK__SI__VI { - struct { - unsigned int DC_GPIO_DDC3CLK_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC3CLK_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC3CLK_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC3DATA_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC3DATA_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC3DATA_RECV : 1; - unsigned int : 1; - unsigned int AUX_PAD3_MODE : 1; - unsigned int : 3; - unsigned int AUX3_POL : 1; - unsigned int : 1; - unsigned int ALLOW_HW_DDC3_PD_EN__VI : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC3CLK_STR : 4; - unsigned int DC_GPIO_DDC3DATA_STR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC3_Y__SI__VI { - struct { - unsigned int DC_GPIO_DDC3CLK_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC3DATA_Y : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC4_A__SI__VI { - struct { - unsigned int DC_GPIO_DDC4CLK_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC4DATA_A : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC4_EN__SI__VI { - struct { - unsigned int DC_GPIO_DDC4CLK_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC4DATA_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC4_MASK__SI__VI { - struct { - unsigned int DC_GPIO_DDC4CLK_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC4CLK_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC4CLK_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC4DATA_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC4DATA_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC4DATA_RECV : 1; - unsigned int : 1; - unsigned int AUX_PAD4_MODE : 1; - unsigned int : 3; - unsigned int AUX4_POL : 1; - unsigned int : 1; - unsigned int ALLOW_HW_DDC4_PD_EN__VI : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC4CLK_STR : 4; - unsigned int DC_GPIO_DDC4DATA_STR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC4_Y__SI__VI { - struct { - unsigned int DC_GPIO_DDC4CLK_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC4DATA_Y : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC5_A__SI__VI { - struct { - unsigned int DC_GPIO_DDC5CLK_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC5DATA_A : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC5_EN__SI__VI { - struct { - unsigned int DC_GPIO_DDC5CLK_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC5DATA_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC5_MASK__SI__VI { - struct { - unsigned int DC_GPIO_DDC5CLK_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC5CLK_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC5CLK_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC5DATA_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC5DATA_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC5DATA_RECV : 1; - unsigned int : 1; - unsigned int AUX_PAD5_MODE : 1; - unsigned int : 3; - unsigned int AUX5_POL : 1; - unsigned int : 1; - unsigned int ALLOW_HW_DDC5_PD_EN__VI : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC5CLK_STR : 4; - unsigned int DC_GPIO_DDC5DATA_STR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC5_Y__SI__VI { - struct { - unsigned int DC_GPIO_DDC5CLK_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC5DATA_Y : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC6_A__SI__VI { - struct { - unsigned int DC_GPIO_DDC6CLK_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC6DATA_A : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC6_EN__SI__VI { - struct { - unsigned int DC_GPIO_DDC6CLK_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC6DATA_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC6_MASK__SI__VI { - struct { - unsigned int DC_GPIO_DDC6CLK_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC6CLK_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC6CLK_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC6DATA_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDC6DATA_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC6DATA_RECV : 1; - unsigned int : 1; - unsigned int AUX_PAD6_MODE : 1; - unsigned int : 3; - unsigned int AUX6_POL : 1; - unsigned int : 1; - unsigned int ALLOW_HW_DDC6_PD_EN__VI : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDC6CLK_STR : 4; - unsigned int DC_GPIO_DDC6DATA_STR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDC6_Y__SI__VI { - struct { - unsigned int DC_GPIO_DDC6CLK_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDC6DATA_Y : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DEBUG__SI__VI { - struct { - unsigned int DC_GPIO_VIP_DEBUG : 1; - unsigned int : 7; - unsigned int DC_GPIO_MACRO_DEBUG : 2; - unsigned int : 6; - unsigned int DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__VI : 1; - unsigned int DC_GPIO_DEBUG_BUS_FLOP_EN__VI : 1; - unsigned int : 13; - unsigned int DPRX_LOOPBACK_ENABLE__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DVODATA_A__SI { - struct { - unsigned int DC_GPIO_DVODATA_A : 24; - unsigned int DC_GPIO_DVOCNTL_A : 3; - unsigned int : 1; - unsigned int DC_GPIO_DVOCLK_A : 1; - unsigned int : 1; - unsigned int DC_GPIO_MVP_DVOCNTL_A : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DVODATA_A__VI { - struct { - unsigned int DC_GPIO_DVODATA_A : 24; - unsigned int DC_GPIO_DVOCNTL_A : 5; - unsigned int DC_GPIO_DVOCLK_A : 1; - unsigned int DC_GPIO_MVP_DVOCNTL_A : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DVODATA_EN__SI { - struct { - unsigned int DC_GPIO_DVODATA_EN : 24; - unsigned int DC_GPIO_DVOCNTL_EN : 3; - unsigned int : 1; - unsigned int DC_GPIO_DVOCLK_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_MVP_DVOCNTL_EN : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DVODATA_EN__VI { - struct { - unsigned int DC_GPIO_DVODATA_EN : 24; - unsigned int DC_GPIO_DVOCNTL_EN : 5; - unsigned int DC_GPIO_DVOCLK_EN : 1; - unsigned int DC_GPIO_MVP_DVOCNTL_EN : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DVODATA_MASK__SI { - struct { - unsigned int DC_GPIO_DVODATA_MASK : 24; - unsigned int DC_GPIO_DVOCNTL_MASK : 3; - unsigned int : 1; - unsigned int DC_GPIO_DVOCLK_MASK : 1; - unsigned int : 1; - unsigned int DC_GPIO_MVP_DVOCNTL_MASK : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DVODATA_MASK__VI { - struct { - unsigned int DC_GPIO_DVODATA_MASK : 24; - unsigned int DC_GPIO_DVOCNTL_MASK : 5; - unsigned int DC_GPIO_DVOCLK_MASK : 1; - unsigned int DC_GPIO_MVP_DVOCNTL_MASK : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DVODATA_Y__SI { - struct { - unsigned int DC_GPIO_DVODATA_Y : 24; - unsigned int DC_GPIO_DVOCNTL_Y : 3; - unsigned int : 1; - unsigned int DC_GPIO_DVOCLK_Y : 1; - unsigned int : 1; - unsigned int DC_GPIO_MVP_DVOCNTL_Y : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DVODATA_Y__VI { - struct { - unsigned int DC_GPIO_DVODATA_Y : 24; - unsigned int DC_GPIO_DVOCNTL_Y : 5; - unsigned int DC_GPIO_DVOCLK_Y : 1; - unsigned int DC_GPIO_MVP_DVOCNTL_Y : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_GENERIC_A__SI__VI { - struct { - unsigned int DC_GPIO_GENERICA_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_GENERICB_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_GENERICC_A : 1; - unsigned int : 3; - unsigned int DC_GPIO_GENERICD_A : 1; - unsigned int DC_GPIO_GENERICE_A : 1; - unsigned int DC_GPIO_GENERICF_A : 1; - unsigned int DC_GPIO_GENERICG_A : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_GENERIC_EN__SI__VI { - struct { - unsigned int DC_GPIO_GENERICA_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_GENERICB_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_GENERICC_EN : 1; - unsigned int : 3; - unsigned int DC_GPIO_GENERICD_EN : 1; - unsigned int DC_GPIO_GENERICE_EN : 1; - unsigned int DC_GPIO_GENERICF_EN : 1; - unsigned int DC_GPIO_GENERICG_EN : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_GENERIC_MASK__SI__VI { - struct { - unsigned int DC_GPIO_GENERICA_MASK : 1; - unsigned int DC_GPIO_GENERICA_PD_DIS : 1; - unsigned int DC_GPIO_GENERICA_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_GENERICB_MASK : 1; - unsigned int DC_GPIO_GENERICB_PD_DIS : 1; - unsigned int DC_GPIO_GENERICB_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_GENERICC_MASK : 1; - unsigned int DC_GPIO_GENERICC_PD_DIS : 1; - unsigned int DC_GPIO_GENERICC_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_GENERICD_MASK : 1; - unsigned int DC_GPIO_GENERICD_PD_DIS : 1; - unsigned int DC_GPIO_GENERICD_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_GENERICE_MASK : 1; - unsigned int DC_GPIO_GENERICE_PD_DIS : 1; - unsigned int DC_GPIO_GENERICE_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_GENERICF_MASK : 1; - unsigned int DC_GPIO_GENERICF_PD_DIS : 1; - unsigned int DC_GPIO_GENERICF_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_GENERICG_MASK : 1; - unsigned int DC_GPIO_GENERICG_PD_DIS : 1; - unsigned int DC_GPIO_GENERICG_RECV : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_GENERIC_Y__SI__VI { - struct { - unsigned int DC_GPIO_GENERICA_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_GENERICB_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_GENERICC_Y : 1; - unsigned int : 3; - unsigned int DC_GPIO_GENERICD_Y : 1; - unsigned int DC_GPIO_GENERICE_Y : 1; - unsigned int DC_GPIO_GENERICF_Y : 1; - unsigned int DC_GPIO_GENERICG_Y : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_HPD_A__SI__VI { - struct { - unsigned int DC_GPIO_HPD1_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_HPD2_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_HPD3_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_HPD4_A : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD5_A : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD6_A : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_HPD_EN__SI__VI { - struct { - unsigned int DC_GPIO_HPD1_EN : 1; - unsigned int HPD1_SCHMEN_PI__VI : 1; - unsigned int HPD1_SLEWNCORE__VI : 1; - unsigned int RX_HPD_SCHMEN_PI__VI : 1; - unsigned int RX_HPD_SLEWNCORE__VI : 1; - unsigned int : 1; - unsigned int HPD1_SEL0__VI : 1; - unsigned int RX_HPD_SEL0__VI : 1; - unsigned int DC_GPIO_HPD2_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_HPD3_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_HPD4_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD5_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD6_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_HPD_MASK__SI { - struct { - unsigned int DC_GPIO_HPD1_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_HPD1_PD_DIS : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD1_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD2_MASK : 1; - unsigned int : 7; - unsigned int DC_GPIO_HPD3_MASK : 1; - unsigned int : 7; - unsigned int DC_GPIO_HPD4_MASK : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD5_MASK : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD6_MASK : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_HPD_MASK__VI { - struct { - unsigned int DC_GPIO_HPD1_MASK : 1; - unsigned int DC_GPIO_RX_HPD_MASK : 1; - unsigned int DC_GPIO_RX_HPD_PD_DIS : 1; - unsigned int DC_GPIO_RX_HPD_RX_SEL : 1; - unsigned int DC_GPIO_HPD1_PD_DIS : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD1_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD2_MASK : 1; - unsigned int DC_GPIO_HPD2_PD_DIS : 1; - unsigned int DC_GPIO_HPD2_RECV : 1; - unsigned int : 5; - unsigned int DC_GPIO_HPD3_MASK : 1; - unsigned int DC_GPIO_HPD3_PD_DIS : 1; - unsigned int DC_GPIO_HPD3_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD4_MASK : 1; - unsigned int DC_GPIO_HPD4_PD_DIS : 1; - unsigned int DC_GPIO_HPD4_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD5_MASK : 1; - unsigned int DC_GPIO_HPD5_PD_DIS : 1; - unsigned int DC_GPIO_HPD5_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD6_MASK : 1; - unsigned int DC_GPIO_HPD6_PD_DIS : 1; - unsigned int DC_GPIO_HPD6_RECV : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_HPD_Y__SI__VI { - struct { - unsigned int DC_GPIO_HPD1_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_HPD2_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_HPD3_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_HPD4_Y : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD5_Y : 1; - unsigned int : 1; - unsigned int DC_GPIO_HPD6_Y : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_PAD_STRENGTH_1__SI__VI { - struct { - unsigned int GENLK_STRENGTH_SN__VI : 4; - unsigned int GENLK_STRENGTH_SP__VI : 4; - unsigned int RX_HPD_STRENGTH_SN__VI : 4; - unsigned int RX_HPD_STRENGTH_SP__VI : 4; - unsigned int : 8; - unsigned int SYNC_STRENGTH_SN : 4; - unsigned int SYNC_STRENGTH_SP : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_PAD_STRENGTH_2__SI__VI { - struct { - unsigned int STRENGTH_SN : 4; - unsigned int STRENGTH_SP : 4; - unsigned int EXT_RESET_DRVSTRENGTH__VI : 3; - unsigned int : 1; - unsigned int REF_27_DRVSTRENGTH__VI : 3; - unsigned int : 1; - unsigned int PWRSEQ_STRENGTH_SN : 4; - unsigned int PWRSEQ_STRENGTH_SP : 4; - unsigned int : 6; - unsigned int REF_27_SRC_SEL__VI : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_PWRSEQ_A__SI__VI { - struct { - unsigned int DC_GPIO_BLON_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_DIGON_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_ENA_BL_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_VSYNC_IN_A__VI : 1; - unsigned int : 6; - unsigned int DC_GPIO_HSYNC_IN_A__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_PWRSEQ_EN__SI__VI { - struct { - unsigned int DC_GPIO_BLON_EN : 1; - unsigned int DC_GPIO_VARY_BL_GENERICA_EN : 1; - unsigned int : 6; - unsigned int DC_GPIO_DIGON_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_ENA_BL_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_VSYNC_IN_EN__VI : 1; - unsigned int : 6; - unsigned int DC_GPIO_HSYNC_IN_EN__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_PWRSEQ_MASK__SI__VI { - struct { - unsigned int DC_GPIO_BLON_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_BLON_PD_DIS : 1; - unsigned int : 1; - unsigned int DC_GPIO_BLON_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_DIGON_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DIGON_PD_DIS : 1; - unsigned int : 1; - unsigned int DC_GPIO_DIGON_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_ENA_BL_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_ENA_BL_PD_DIS : 1; - unsigned int : 1; - unsigned int DC_GPIO_ENA_BL_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_VSYNC_IN_MASK__VI : 1; - unsigned int DC_GPIO_VSYNC_IN_PD_DIS__VI : 1; - unsigned int DC_GPIO_VSYNC_IN_RECV__VI : 1; - unsigned int : 1; - unsigned int DC_GPIO_HSYNC_IN_MASK__VI : 1; - unsigned int DC_GPIO_HSYNC_IN_PD_DIS__VI : 1; - unsigned int DC_GPIO_HSYNC_IN_RECV__VI : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_PWRSEQ_Y__SI__VI { - struct { - unsigned int DC_GPIO_BLON_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_DIGON_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_ENA_BL_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_VSYNC_IN__VI : 1; - unsigned int : 6; - unsigned int DC_GPIO_HSYNC_IN__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_SYNCA_A__SI__VI { - struct { - unsigned int DC_GPIO_HSYNCA_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_VSYNCA_A : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_SYNCA_EN__SI__VI { - struct { - unsigned int DC_GPIO_HSYNCA_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_VSYNCA_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_SYNCA_MASK__SI__VI { - struct { - unsigned int DC_GPIO_HSYNCA_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_HSYNCA_PD_DIS : 1; - unsigned int : 1; - unsigned int DC_GPIO_HSYNCA_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_VSYNCA_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_VSYNCA_PD_DIS : 1; - unsigned int : 1; - unsigned int DC_GPIO_VSYNCA_RECV : 1; - unsigned int : 9; - unsigned int DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__VI : 3; - unsigned int : 1; - unsigned int DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__VI : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_SYNCA_Y__SI__VI { - struct { - unsigned int DC_GPIO_HSYNCA_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_VSYNCA_Y : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPU_TIMER_READ_CNTL__SI__VI { - struct { - unsigned int DC_GPU_TIMER_READ_SELECT : 6; - unsigned int : 2; - unsigned int DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__VI : 3; - unsigned int DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__VI : 3; - unsigned int DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__VI : 3; - unsigned int DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__VI : 3; - unsigned int DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__VI : 3; - unsigned int DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__VI : 3; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPU_TIMER_READ__SI__VI { - struct { - unsigned int DC_GPU_TIMER_READ : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPU_TIMER_START_POSITION__SI { - struct { - unsigned int : 3; - unsigned int : 13; - unsigned int : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD1_CONTROL__SI { - struct { - unsigned int DC_HPD1_CONNECTION_TIMER : 13; - unsigned int : 3; - unsigned int DC_HPD1_RX_INT_TIMER : 10; - unsigned int : 2; - unsigned int DC_HPD1_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD1_INT_CONTROL__SI { - struct { - unsigned int DC_HPD1_INT_ACK : 1; - unsigned int : 7; - unsigned int DC_HPD1_INT_POLARITY : 1; - unsigned int : 7; - unsigned int DC_HPD1_INT_EN : 1; - unsigned int : 3; - unsigned int DC_HPD1_RX_INT_ACK : 1; - unsigned int : 3; - unsigned int DC_HPD1_RX_INT_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD1_INT_STATUS__SI { - struct { - unsigned int DC_HPD1_INT_STATUS : 1; - unsigned int DC_HPD1_SENSE : 1; - unsigned int : 6; - unsigned int DC_HPD1_RX_INT_STATUS : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD2_CONTROL__SI { - struct { - unsigned int DC_HPD2_CONNECTION_TIMER : 13; - unsigned int : 3; - unsigned int DC_HPD2_RX_INT_TIMER : 10; - unsigned int : 2; - unsigned int DC_HPD2_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD2_INT_CONTROL__SI { - struct { - unsigned int DC_HPD2_INT_ACK : 1; - unsigned int : 7; - unsigned int DC_HPD2_INT_POLARITY : 1; - unsigned int : 7; - unsigned int DC_HPD2_INT_EN : 1; - unsigned int : 3; - unsigned int DC_HPD2_RX_INT_ACK : 1; - unsigned int : 3; - unsigned int DC_HPD2_RX_INT_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD2_INT_STATUS__SI { - struct { - unsigned int DC_HPD2_INT_STATUS : 1; - unsigned int DC_HPD2_SENSE : 1; - unsigned int : 6; - unsigned int DC_HPD2_RX_INT_STATUS : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD3_CONTROL__SI { - struct { - unsigned int DC_HPD3_CONNECTION_TIMER : 13; - unsigned int : 3; - unsigned int DC_HPD3_RX_INT_TIMER : 10; - unsigned int : 2; - unsigned int DC_HPD3_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD3_INT_CONTROL__SI { - struct { - unsigned int DC_HPD3_INT_ACK : 1; - unsigned int : 7; - unsigned int DC_HPD3_INT_POLARITY : 1; - unsigned int : 7; - unsigned int DC_HPD3_INT_EN : 1; - unsigned int : 3; - unsigned int DC_HPD3_RX_INT_ACK : 1; - unsigned int : 3; - unsigned int DC_HPD3_RX_INT_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD3_INT_STATUS__SI { - struct { - unsigned int DC_HPD3_INT_STATUS : 1; - unsigned int DC_HPD3_SENSE : 1; - unsigned int : 6; - unsigned int DC_HPD3_RX_INT_STATUS : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD4_CONTROL__SI { - struct { - unsigned int DC_HPD4_CONNECTION_TIMER : 13; - unsigned int : 3; - unsigned int DC_HPD4_RX_INT_TIMER : 10; - unsigned int : 2; - unsigned int DC_HPD4_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD4_INT_CONTROL__SI { - struct { - unsigned int DC_HPD4_INT_ACK : 1; - unsigned int : 7; - unsigned int DC_HPD4_INT_POLARITY : 1; - unsigned int : 7; - unsigned int DC_HPD4_INT_EN : 1; - unsigned int : 3; - unsigned int DC_HPD4_RX_INT_ACK : 1; - unsigned int : 3; - unsigned int DC_HPD4_RX_INT_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD4_INT_STATUS__SI { - struct { - unsigned int DC_HPD4_INT_STATUS : 1; - unsigned int DC_HPD4_SENSE : 1; - unsigned int : 6; - unsigned int DC_HPD4_RX_INT_STATUS : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD5_CONTROL__SI { - struct { - unsigned int DC_HPD5_CONNECTION_TIMER : 13; - unsigned int : 3; - unsigned int DC_HPD5_RX_INT_TIMER : 10; - unsigned int : 2; - unsigned int DC_HPD5_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD5_INT_CONTROL__SI { - struct { - unsigned int DC_HPD5_INT_ACK : 1; - unsigned int : 7; - unsigned int DC_HPD5_INT_POLARITY : 1; - unsigned int : 7; - unsigned int DC_HPD5_INT_EN : 1; - unsigned int : 3; - unsigned int DC_HPD5_RX_INT_ACK : 1; - unsigned int : 3; - unsigned int DC_HPD5_RX_INT_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD5_INT_STATUS__SI { - struct { - unsigned int DC_HPD5_INT_STATUS : 1; - unsigned int DC_HPD5_SENSE : 1; - unsigned int : 6; - unsigned int DC_HPD5_RX_INT_STATUS : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD6_CONTROL__SI { - struct { - unsigned int DC_HPD6_CONNECTION_TIMER : 13; - unsigned int : 3; - unsigned int DC_HPD6_RX_INT_TIMER : 10; - unsigned int : 2; - unsigned int DC_HPD6_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD6_INT_CONTROL__SI { - struct { - unsigned int DC_HPD6_INT_ACK : 1; - unsigned int : 7; - unsigned int DC_HPD6_INT_POLARITY : 1; - unsigned int : 7; - unsigned int DC_HPD6_INT_EN : 1; - unsigned int : 3; - unsigned int DC_HPD6_RX_INT_ACK : 1; - unsigned int : 3; - unsigned int DC_HPD6_RX_INT_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD6_INT_STATUS__SI { - struct { - unsigned int DC_HPD6_INT_STATUS : 1; - unsigned int DC_HPD6_SENSE : 1; - unsigned int : 6; - unsigned int DC_HPD6_RX_INT_STATUS : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_ARBITRATION__SI__VI { - struct { - unsigned int DC_I2C_SW_PRIORITY : 2; - unsigned int DC_I2C_REG_RW_CNTL_STATUS : 2; - unsigned int DC_I2C_NO_QUEUED_SW_GO : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int DC_I2C_ABORT_HW_XFER : 1; - unsigned int : 3; - unsigned int DC_I2C_ABORT_SW_XFER : 1; - unsigned int : 7; - unsigned int DC_I2C_SW_USE_I2C_REG_REQ : 1; - unsigned int DC_I2C_SW_DONE_USING_I2C_REG : 1; - unsigned int : 2; - unsigned int DC_I2C_DMCU_USE_I2C_REG_REQ : 1; - unsigned int DC_I2C_DMCU_DONE_USING_I2C_REG : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_CONTROL__SI__VI { - struct { - unsigned int DC_I2C_GO : 1; - unsigned int DC_I2C_SOFT_RESET : 1; - unsigned int DC_I2C_SEND_RESET : 1; - unsigned int DC_I2C_SW_STATUS_RESET : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DC_I2C_DDC_SELECT : 3; - unsigned int : 9; - unsigned int DC_I2C_TRANSACTION_COUNT : 2; - unsigned int : 9; - unsigned int DC_I2C_DBG_REF_SEL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DATA__SI__VI { - struct { - unsigned int DC_I2C_DATA_RW : 1; - unsigned int : 7; - unsigned int DC_I2C_DATA : 8; - unsigned int DC_I2C_INDEX : 8; - unsigned int : 7; - unsigned int DC_I2C_INDEX_WRITE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC1_HW_STATUS__SI__VI { - struct { - unsigned int DC_I2C_DDC1_HW_STATUS : 2; - unsigned int : 1; - unsigned int DC_I2C_DDC1_HW_DONE : 1; - unsigned int : 12; - unsigned int DC_I2C_DDC1_HW_REQ : 1; - unsigned int DC_I2C_DDC1_HW_URG : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC1_EDID_DETECT_STATUS__VI : 1; - unsigned int : 3; - unsigned int DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__VI : 4; - unsigned int DC_I2C_DDC1_EDID_DETECT_STATE__VI : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC1_SETUP__SI__VI { - struct { - unsigned int DC_I2C_DDC1_DATA_DRIVE_EN : 1; - unsigned int DC_I2C_DDC1_DATA_DRIVE_SEL : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC1_EDID_DETECT_ENABLE__VI : 1; - unsigned int DC_I2C_DDC1_EDID_DETECT_MODE__VI : 1; - unsigned int DC_I2C_DDC1_ENABLE__VI : 1; - unsigned int DC_I2C_DDC1_CLK_DRIVE_EN : 1; - unsigned int DC_I2C_DDC1_INTRA_BYTE_DELAY : 8; - unsigned int DC_I2C_DDC1_INTRA_TRANSACTION_DELAY : 8; - unsigned int DC_I2C_DDC1_TIME_LIMIT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC1_SPEED__SI__VI { - struct { - unsigned int DC_I2C_DDC1_THRESHOLD : 2; - unsigned int : 2; - unsigned int DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL : 1; - unsigned int : 11; - unsigned int DC_I2C_DDC1_PRESCALE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC2_HW_STATUS__SI__VI { - struct { - unsigned int DC_I2C_DDC2_HW_STATUS : 2; - unsigned int : 1; - unsigned int DC_I2C_DDC2_HW_DONE : 1; - unsigned int : 12; - unsigned int DC_I2C_DDC2_HW_REQ : 1; - unsigned int DC_I2C_DDC2_HW_URG : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC2_EDID_DETECT_STATUS__VI : 1; - unsigned int : 3; - unsigned int DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__VI : 4; - unsigned int DC_I2C_DDC2_EDID_DETECT_STATE__VI : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC2_SETUP__SI__VI { - struct { - unsigned int DC_I2C_DDC2_DATA_DRIVE_EN : 1; - unsigned int DC_I2C_DDC2_DATA_DRIVE_SEL : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC2_EDID_DETECT_ENABLE__VI : 1; - unsigned int DC_I2C_DDC2_EDID_DETECT_MODE__VI : 1; - unsigned int DC_I2C_DDC2_ENABLE__VI : 1; - unsigned int DC_I2C_DDC2_CLK_DRIVE_EN : 1; - unsigned int DC_I2C_DDC2_INTRA_BYTE_DELAY : 8; - unsigned int DC_I2C_DDC2_INTRA_TRANSACTION_DELAY : 8; - unsigned int DC_I2C_DDC2_TIME_LIMIT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC2_SPEED__SI__VI { - struct { - unsigned int DC_I2C_DDC2_THRESHOLD : 2; - unsigned int : 2; - unsigned int DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL : 1; - unsigned int : 11; - unsigned int DC_I2C_DDC2_PRESCALE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC3_HW_STATUS__SI__VI { - struct { - unsigned int DC_I2C_DDC3_HW_STATUS : 2; - unsigned int : 1; - unsigned int DC_I2C_DDC3_HW_DONE : 1; - unsigned int : 12; - unsigned int DC_I2C_DDC3_HW_REQ : 1; - unsigned int DC_I2C_DDC3_HW_URG : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC3_EDID_DETECT_STATUS__VI : 1; - unsigned int : 3; - unsigned int DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__VI : 4; - unsigned int DC_I2C_DDC3_EDID_DETECT_STATE__VI : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC3_SETUP__SI__VI { - struct { - unsigned int DC_I2C_DDC3_DATA_DRIVE_EN : 1; - unsigned int DC_I2C_DDC3_DATA_DRIVE_SEL : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC3_EDID_DETECT_ENABLE__VI : 1; - unsigned int DC_I2C_DDC3_EDID_DETECT_MODE__VI : 1; - unsigned int DC_I2C_DDC3_ENABLE__VI : 1; - unsigned int DC_I2C_DDC3_CLK_DRIVE_EN : 1; - unsigned int DC_I2C_DDC3_INTRA_BYTE_DELAY : 8; - unsigned int DC_I2C_DDC3_INTRA_TRANSACTION_DELAY : 8; - unsigned int DC_I2C_DDC3_TIME_LIMIT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC3_SPEED__SI__VI { - struct { - unsigned int DC_I2C_DDC3_THRESHOLD : 2; - unsigned int : 2; - unsigned int DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL : 1; - unsigned int : 11; - unsigned int DC_I2C_DDC3_PRESCALE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC4_HW_STATUS__SI__VI { - struct { - unsigned int DC_I2C_DDC4_HW_STATUS : 2; - unsigned int : 1; - unsigned int DC_I2C_DDC4_HW_DONE : 1; - unsigned int : 12; - unsigned int DC_I2C_DDC4_HW_REQ : 1; - unsigned int DC_I2C_DDC4_HW_URG : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC4_EDID_DETECT_STATUS__VI : 1; - unsigned int : 3; - unsigned int DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__VI : 4; - unsigned int DC_I2C_DDC4_EDID_DETECT_STATE__VI : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC4_SETUP__SI__VI { - struct { - unsigned int DC_I2C_DDC4_DATA_DRIVE_EN : 1; - unsigned int DC_I2C_DDC4_DATA_DRIVE_SEL : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC4_EDID_DETECT_ENABLE__VI : 1; - unsigned int DC_I2C_DDC4_EDID_DETECT_MODE__VI : 1; - unsigned int DC_I2C_DDC4_ENABLE__VI : 1; - unsigned int DC_I2C_DDC4_CLK_DRIVE_EN : 1; - unsigned int DC_I2C_DDC4_INTRA_BYTE_DELAY : 8; - unsigned int DC_I2C_DDC4_INTRA_TRANSACTION_DELAY : 8; - unsigned int DC_I2C_DDC4_TIME_LIMIT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC4_SPEED__SI__VI { - struct { - unsigned int DC_I2C_DDC4_THRESHOLD : 2; - unsigned int : 2; - unsigned int DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL : 1; - unsigned int : 11; - unsigned int DC_I2C_DDC4_PRESCALE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC5_HW_STATUS__SI__VI { - struct { - unsigned int DC_I2C_DDC5_HW_STATUS : 2; - unsigned int : 1; - unsigned int DC_I2C_DDC5_HW_DONE : 1; - unsigned int : 12; - unsigned int DC_I2C_DDC5_HW_REQ : 1; - unsigned int DC_I2C_DDC5_HW_URG : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC5_EDID_DETECT_STATUS__VI : 1; - unsigned int : 3; - unsigned int DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__VI : 4; - unsigned int DC_I2C_DDC5_EDID_DETECT_STATE__VI : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC5_SETUP__SI__VI { - struct { - unsigned int DC_I2C_DDC5_DATA_DRIVE_EN : 1; - unsigned int DC_I2C_DDC5_DATA_DRIVE_SEL : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC5_EDID_DETECT_ENABLE__VI : 1; - unsigned int DC_I2C_DDC5_EDID_DETECT_MODE__VI : 1; - unsigned int DC_I2C_DDC5_ENABLE__VI : 1; - unsigned int DC_I2C_DDC5_CLK_DRIVE_EN : 1; - unsigned int DC_I2C_DDC5_INTRA_BYTE_DELAY : 8; - unsigned int DC_I2C_DDC5_INTRA_TRANSACTION_DELAY : 8; - unsigned int DC_I2C_DDC5_TIME_LIMIT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC5_SPEED__SI__VI { - struct { - unsigned int DC_I2C_DDC5_THRESHOLD : 2; - unsigned int : 2; - unsigned int DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL : 1; - unsigned int : 11; - unsigned int DC_I2C_DDC5_PRESCALE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC6_HW_STATUS__SI__VI { - struct { - unsigned int DC_I2C_DDC6_HW_STATUS : 2; - unsigned int : 1; - unsigned int DC_I2C_DDC6_HW_DONE : 1; - unsigned int : 12; - unsigned int DC_I2C_DDC6_HW_REQ : 1; - unsigned int DC_I2C_DDC6_HW_URG : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC6_EDID_DETECT_STATUS__VI : 1; - unsigned int : 3; - unsigned int DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__VI : 4; - unsigned int DC_I2C_DDC6_EDID_DETECT_STATE__VI : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC6_SETUP__SI__VI { - struct { - unsigned int DC_I2C_DDC6_DATA_DRIVE_EN : 1; - unsigned int DC_I2C_DDC6_DATA_DRIVE_SEL : 1; - unsigned int : 2; - unsigned int DC_I2C_DDC6_EDID_DETECT_ENABLE__VI : 1; - unsigned int DC_I2C_DDC6_EDID_DETECT_MODE__VI : 1; - unsigned int DC_I2C_DDC6_ENABLE__VI : 1; - unsigned int DC_I2C_DDC6_CLK_DRIVE_EN : 1; - unsigned int DC_I2C_DDC6_INTRA_BYTE_DELAY : 8; - unsigned int DC_I2C_DDC6_INTRA_TRANSACTION_DELAY : 8; - unsigned int DC_I2C_DDC6_TIME_LIMIT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDC6_SPEED__SI__VI { - struct { - unsigned int DC_I2C_DDC6_THRESHOLD : 2; - unsigned int : 2; - unsigned int DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL : 1; - unsigned int : 11; - unsigned int DC_I2C_DDC6_PRESCALE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_INTERRUPT_CONTROL__SI__VI { - struct { - unsigned int DC_I2C_SW_DONE_INT : 1; - unsigned int DC_I2C_SW_DONE_ACK : 1; - unsigned int DC_I2C_SW_DONE_MASK : 1; - unsigned int : 1; - unsigned int DC_I2C_DDC1_HW_DONE_INT : 1; - unsigned int DC_I2C_DDC1_HW_DONE_ACK : 1; - unsigned int DC_I2C_DDC1_HW_DONE_MASK : 1; - unsigned int : 1; - unsigned int DC_I2C_DDC2_HW_DONE_INT : 1; - unsigned int DC_I2C_DDC2_HW_DONE_ACK : 1; - unsigned int DC_I2C_DDC2_HW_DONE_MASK : 1; - unsigned int : 1; - unsigned int DC_I2C_DDC3_HW_DONE_INT : 1; - unsigned int DC_I2C_DDC3_HW_DONE_ACK : 1; - unsigned int DC_I2C_DDC3_HW_DONE_MASK : 1; - unsigned int : 1; - unsigned int DC_I2C_DDC4_HW_DONE_INT : 1; - unsigned int DC_I2C_DDC4_HW_DONE_ACK : 1; - unsigned int DC_I2C_DDC4_HW_DONE_MASK : 1; - unsigned int : 1; - unsigned int DC_I2C_DDC5_HW_DONE_INT : 1; - unsigned int DC_I2C_DDC5_HW_DONE_ACK : 1; - unsigned int DC_I2C_DDC5_HW_DONE_MASK : 1; - unsigned int : 1; - unsigned int DC_I2C_DDC6_HW_DONE_INT : 1; - unsigned int DC_I2C_DDC6_HW_DONE_ACK : 1; - unsigned int DC_I2C_DDC6_HW_DONE_MASK : 1; - unsigned int DC_I2C_DDCVGA_HW_DONE_INT__VI : 1; - unsigned int DC_I2C_DDCVGA_HW_DONE_ACK__VI : 1; - unsigned int DC_I2C_DDCVGA_HW_DONE_MASK__VI : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_SW_STATUS__SI { - struct { - unsigned int DC_I2C_SW_STATUS : 2; - unsigned int DC_I2C_SW_DONE : 1; - unsigned int : 1; - unsigned int DC_I2C_SW_ABORTED : 1; - unsigned int DC_I2C_SW_TIMEOUT : 1; - unsigned int DC_I2C_SW_INTERRUPTED : 1; - unsigned int DC_I2C_SW_BUFFER_OVERFLOW : 1; - unsigned int DC_I2C_SW_STOPPED_ON_NACK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DC_I2C_SW_NACK0 : 1; - unsigned int DC_I2C_SW_NACK1 : 1; - unsigned int DC_I2C_SW_NACK2 : 1; - unsigned int DC_I2C_SW_NACK3 : 1; - unsigned int : 2; - unsigned int DC_I2C_SW_REQ : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_SW_STATUS__VI { - struct { - unsigned int DC_I2C_SW_STATUS : 2; - unsigned int DC_I2C_SW_DONE : 1; - unsigned int : 1; - unsigned int DC_I2C_SW_ABORTED : 1; - unsigned int DC_I2C_SW_TIMEOUT : 1; - unsigned int DC_I2C_SW_INTERRUPTED : 1; - unsigned int DC_I2C_SW_BUFFER_OVERFLOW : 1; - unsigned int DC_I2C_SW_STOPPED_ON_NACK : 1; - unsigned int : 3; - unsigned int DC_I2C_SW_NACK0 : 1; - unsigned int DC_I2C_SW_NACK1 : 1; - unsigned int DC_I2C_SW_NACK2 : 1; - unsigned int DC_I2C_SW_NACK3 : 1; - unsigned int : 2; - unsigned int DC_I2C_SW_REQ : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_TRANSACTION0__SI__VI { - struct { - unsigned int DC_I2C_RW0 : 1; - unsigned int : 7; - unsigned int DC_I2C_STOP_ON_NACK0 : 1; - unsigned int : 3; - unsigned int DC_I2C_START0 : 1; - unsigned int DC_I2C_STOP0 : 1; - unsigned int : 2; - unsigned int DC_I2C_COUNT0 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_TRANSACTION1__SI__VI { - struct { - unsigned int DC_I2C_RW1 : 1; - unsigned int : 7; - unsigned int DC_I2C_STOP_ON_NACK1 : 1; - unsigned int : 3; - unsigned int DC_I2C_START1 : 1; - unsigned int DC_I2C_STOP1 : 1; - unsigned int : 2; - unsigned int DC_I2C_COUNT1 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_TRANSACTION2__SI__VI { - struct { - unsigned int DC_I2C_RW2 : 1; - unsigned int : 7; - unsigned int DC_I2C_STOP_ON_NACK2 : 1; - unsigned int : 3; - unsigned int DC_I2C_START2 : 1; - unsigned int DC_I2C_STOP2 : 1; - unsigned int : 2; - unsigned int DC_I2C_COUNT2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_TRANSACTION3__SI__VI { - struct { - unsigned int DC_I2C_RW3 : 1; - unsigned int : 7; - unsigned int DC_I2C_STOP_ON_NACK3 : 1; - unsigned int : 3; - unsigned int DC_I2C_START3 : 1; - unsigned int DC_I2C_STOP3 : 1; - unsigned int : 2; - unsigned int DC_I2C_COUNT3 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_30_COLOR__SI__VI { - struct { - unsigned int DC_LUT_COLOR_10_BLUE : 10; - unsigned int DC_LUT_COLOR_10_GREEN : 10; - unsigned int DC_LUT_COLOR_10_RED : 10; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_AUTOFILL__SI__VI { - struct { - unsigned int DC_LUT_AUTOFILL : 1; - unsigned int DC_LUT_AUTOFILL_DONE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_BLACK_OFFSET_BLUE__SI__VI { - struct { - unsigned int DC_LUT_BLACK_OFFSET_BLUE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_BLACK_OFFSET_GREEN__SI__VI { - struct { - unsigned int DC_LUT_BLACK_OFFSET_GREEN : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_BLACK_OFFSET_RED__SI__VI { - struct { - unsigned int DC_LUT_BLACK_OFFSET_RED : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_CONTROL__SI__VI { - struct { - unsigned int DC_LUT_INC_B : 4; - unsigned int DC_LUT_DATA_B_SIGNED_EN : 1; - unsigned int DC_LUT_DATA_B_FLOAT_POINT_EN : 1; - unsigned int DC_LUT_DATA_B_FORMAT__VI : 2; - unsigned int DC_LUT_INC_G : 4; - unsigned int DC_LUT_DATA_G_SIGNED_EN : 1; - unsigned int DC_LUT_DATA_G_FLOAT_POINT_EN : 1; - unsigned int DC_LUT_DATA_G_FORMAT__VI : 2; - unsigned int DC_LUT_INC_R : 4; - unsigned int DC_LUT_DATA_R_SIGNED_EN : 1; - unsigned int DC_LUT_DATA_R_FLOAT_POINT_EN : 1; - unsigned int DC_LUT_DATA_R_FORMAT__VI : 2; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_PWL_DATA__SI__VI { - struct { - unsigned int DC_LUT_BASE : 16; - unsigned int DC_LUT_DELTA : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_RW_INDEX__SI__VI { - struct { - unsigned int DC_LUT_RW_INDEX : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_RW_MODE__SI__VI { - struct { - unsigned int DC_LUT_RW_MODE : 1; - unsigned int : 15; - unsigned int DC_LUT_ERROR__VI : 1; - unsigned int DC_LUT_ERROR_RST__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_SEQ_COLOR__SI__VI { - struct { - unsigned int DC_LUT_SEQ_COLOR : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_WHITE_OFFSET_BLUE__SI__VI { - struct { - unsigned int DC_LUT_WHITE_OFFSET_BLUE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_WHITE_OFFSET_GREEN__SI__VI { - struct { - unsigned int DC_LUT_WHITE_OFFSET_GREEN : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_WHITE_OFFSET_RED__SI__VI { - struct { - unsigned int DC_LUT_WHITE_OFFSET_RED : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_WRITE_EN_MASK__SI__VI { - struct { - unsigned int DC_LUT_WRITE_EN_MASK : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_MVP_LB_CONTROL__SI { - struct { - unsigned int MVP_SWAP_LOCK_IN_MODE : 2; - unsigned int : 6; - unsigned int DC_MVP_SWAP_LOCK_OUT_SEL : 1; - unsigned int : 3; - unsigned int DC_MVP_SWAP_LOCK_OUT_FORCE_ONE : 1; - unsigned int : 3; - unsigned int DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DC_MVP_SWAP_LOCK_STATUS : 1; - unsigned int : 7; - unsigned int DC_MVP_SWAP_LOCK_IN_CAP : 1; - unsigned int : 2; - unsigned int DC_MVP_SPARE_FLOPS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_MVP_LB_CONTROL__VI { - struct { - unsigned int MVP_SWAP_LOCK_IN_MODE : 2; - unsigned int : 6; - unsigned int DC_MVP_SWAP_LOCK_OUT_SEL : 1; - unsigned int : 3; - unsigned int DC_MVP_SWAP_LOCK_OUT_FORCE_ONE : 1; - unsigned int : 3; - unsigned int DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO : 1; - unsigned int : 3; - unsigned int DC_MVP_SWAP_LOCK_STATUS : 1; - unsigned int : 7; - unsigned int DC_MVP_SWAP_LOCK_IN_CAP : 1; - unsigned int : 2; - unsigned int DC_MVP_SPARE_FLOPS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_PAD_EXTERN_SIG__SI__VI { - struct { - unsigned int DC_PAD_EXTERN_SIG_SEL : 4; - unsigned int MVP_PIXEL_SRC_STATUS : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_PINSTRAPS__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DC_PINSTRAPS_VIP_DEVICE : 1; - unsigned int : 1; - unsigned int DC_PINSTRAPS_SMS_EN_HARD : 1; - unsigned int DC_PINSTRAPS_AUDIO : 2; - unsigned int DC_PINSTRAPS_CCBYPASS : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_PINSTRAPS__VI { - struct { - unsigned int : 10; - unsigned int DC_PINSTRAPS_BIF_CEC_DIS : 1; - unsigned int : 2; - unsigned int DC_PINSTRAPS_SMS_EN_HARD : 1; - unsigned int DC_PINSTRAPS_AUDIO : 2; - unsigned int DC_PINSTRAPS_CCBYPASS : 1; - unsigned int DC_PINSTRAPS_CONNECTIVITY : 3; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_REF_CLK_CNTL__SI { - struct { - unsigned int HSYNCA_OUTPUT_SEL : 2; - unsigned int : 6; - unsigned int : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_REF_CLK_CNTL__VI { - struct { - unsigned int HSYNCA_OUTPUT_SEL : 2; - unsigned int : 6; - unsigned int GENLK_CLK_OUTPUT_SEL : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int DC_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int DC_TEST_DEBUG_INDEX : 8; - unsigned int DC_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEBUG_DATA { - struct { - unsigned int DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEBUG_INDEX { - struct { - unsigned int DEBUG_INDEX : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DENTIST_DISPCLK_CNTL__SI { - struct { - unsigned int DENTIST_DISPCLK_WDIVIDER : 7; - unsigned int : 1; - unsigned int DENTIST_DISPCLK_RDIVIDER : 7; - unsigned int : 1; - unsigned int DENTIST_DISPCLK_CHG_DONE : 1; - unsigned int DENTIST_DISPCLK_CHGTOG : 1; - unsigned int DENTIST_DISPCLK_DONETOG : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DENTIST_DISPCLK_CNTL__VI { - struct { - unsigned int DENTIST_DISPCLK_WDIVIDER : 7; - unsigned int : 1; - unsigned int DENTIST_DISPCLK_RDIVIDER : 7; - unsigned int DENTIST_DISPCLK_CHG_MODE : 2; - unsigned int DENTIST_DISPCLK_CHGTOG : 1; - unsigned int DENTIST_DISPCLK_DONETOG : 1; - unsigned int DENTIST_DISPCLK_CHG_DONE : 1; - unsigned int DENTIST_DPREFCLK_CHG_DONE : 1; - unsigned int DENTIST_DPREFCLK_CHGTOG : 1; - unsigned int DENTIST_DPREFCLK_DONETOG : 1; - unsigned int : 1; - unsigned int DENTIST_DPREFCLK_WDIVIDER : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DESKTOP_HEIGHT__SI { - struct { - unsigned int : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEVICE_CAP { - struct { - unsigned int MAX_PAYLOAD_SUPPORT : 3; - unsigned int PHANTOM_FUNC : 2; - unsigned int EXTENDED_TAG : 1; - unsigned int L0S_ACCEPTABLE_LATENCY : 3; - unsigned int L1_ACCEPTABLE_LATENCY : 3; - unsigned int : 3; - unsigned int ROLE_BASED_ERR_REPORTING : 1; - unsigned int : 2; - unsigned int CAPTURED_SLOT_POWER_LIMIT : 8; - unsigned int CAPTURED_SLOT_POWER_SCALE : 2; - unsigned int FLR_CAPABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEVICE_CAP2__CI__VI { - struct { - unsigned int CPL_TIMEOUT_RANGE_SUPPORTED : 4; - unsigned int CPL_TIMEOUT_DIS_SUPPORTED : 1; - unsigned int ARI_FORWARDING_SUPPORTED : 1; - unsigned int ATOMICOP_ROUTING_SUPPORTED__VI : 1; - unsigned int ATOMICOP_32CMPLT_SUPPORTED__VI : 1; - unsigned int ATOMICOP_64CMPLT_SUPPORTED__VI : 1; - unsigned int CAS128_CMPLT_SUPPORTED__VI : 1; - unsigned int NO_RO_ENABLED_P2P_PASSING__VI : 1; - unsigned int LTR_SUPPORTED__VI : 1; - unsigned int TPH_CPLR_SUPPORTED__VI : 2; - unsigned int : 4; - unsigned int OBFF_SUPPORTED__VI : 2; - unsigned int EXTENDED_FMT_FIELD_SUPPORTED : 1; - unsigned int END_END_TLP_PREFIX_SUPPORTED : 1; - unsigned int MAX_END_END_TLP_PREFIXES : 2; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEVICE_CAP2__SI { - struct { - unsigned int CPL_TIMEOUT_RANGE_SUP : 4; - unsigned int CPL_TIMEOUT_DIS_SUP : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEVICE_CNTL2 { - struct { - unsigned int CPL_TIMEOUT_VALUE : 4; - unsigned int CPL_TIMEOUT_DIS : 1; - unsigned int ARI_FORWARDING_EN__CI__VI : 1; - unsigned int ATOMICOP_REQUEST_EN__VI : 1; - unsigned int ATOMICOP_EGRESS_BLOCKING__VI : 1; - unsigned int IDO_REQUEST_ENABLE__VI : 1; - unsigned int IDO_COMPLETION_ENABLE__VI : 1; - unsigned int LTR_EN__VI : 1; - unsigned int : 2; - unsigned int OBFF_EN__VI : 2; - unsigned int END_END_TLP_PREFIX_BLOCKING__CI__VI : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEVICE_CNTL__CI__VI { - struct { - unsigned int CORR_ERR_EN : 1; - unsigned int NON_FATAL_ERR_EN : 1; - unsigned int FATAL_ERR_EN : 1; - unsigned int USR_REPORT_EN : 1; - unsigned int RELAXED_ORD_EN : 1; - unsigned int MAX_PAYLOAD_SIZE : 3; - unsigned int EXTENDED_TAG_EN : 1; - unsigned int PHANTOM_FUNC_EN : 1; - unsigned int AUX_POWER_PM_EN : 1; - unsigned int NO_SNOOP_EN : 1; - unsigned int MAX_READ_REQUEST_SIZE : 3; - unsigned int INITIATE_FLR : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEVICE_CNTL__SI { - struct { - unsigned int CORR_ERR_EN : 1; - unsigned int NON_FATAL_ERR_EN : 1; - unsigned int FATAL_ERR_EN : 1; - unsigned int USR_REPORT_EN : 1; - unsigned int RELAXED_ORD_EN : 1; - unsigned int MAX_PAYLOAD_SIZE : 3; - unsigned int EXTENDED_TAG_EN : 1; - unsigned int PHANTOM_FUNC_EN : 1; - unsigned int AUX_POWER_PM_EN : 1; - unsigned int NO_SNOOP_EN : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEVICE_ID { - struct { - unsigned int DEVICE_ID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEVICE_STATUS { - struct { - unsigned int CORR_ERR : 1; - unsigned int NON_FATAL_ERR : 1; - unsigned int FATAL_ERR : 1; - unsigned int USR_DETECTED : 1; - unsigned int AUX_PWR : 1; - unsigned int TRANSACTIONS_PEND : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEVICE_STATUS2 { - struct { - unsigned int RESERVED : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DH_TEST { - struct { - unsigned int DH_TEST : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DB_CTRL0__CI__VI { - struct { - unsigned int DIDT_CTRL_EN : 1; - unsigned int USE_REF_CLOCK : 1; - unsigned int PHASE_OFFSET : 2; - unsigned int DIDT_CTRL_RST : 1; - unsigned int DIDT_CLK_EN_OVERRIDE : 1; - unsigned int : 6; - unsigned int : 6; - unsigned int UNUSED_0__VI : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DB_CTRL1__CI__VI { - struct { - unsigned int MIN_POWER : 16; - unsigned int MAX_POWER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DB_CTRL2__CI__VI { - struct { - unsigned int MAX_POWER_DELTA : 14; - unsigned int : 2; - unsigned int SHORT_TERM_INTERVAL_SIZE : 10; - unsigned int : 1; - unsigned int LONG_TERM_INTERVAL_RATIO : 4; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DB_WEIGHT0_3__CI__VI { - struct { - unsigned int WEIGHT0 : 8; - unsigned int WEIGHT1 : 8; - unsigned int WEIGHT2 : 8; - unsigned int WEIGHT3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DB_WEIGHT4_7__CI__VI { - struct { - unsigned int WEIGHT4 : 8; - unsigned int WEIGHT5 : 8; - unsigned int WEIGHT6 : 8; - unsigned int WEIGHT7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DB_WEIGHT8_11__CI__VI { - struct { - unsigned int WEIGHT8 : 8; - unsigned int WEIGHT9 : 8; - unsigned int WEIGHT10 : 8; - unsigned int WEIGHT11 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_IND_DATA__CI__VI { - struct { - unsigned int DIDT_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_IND_INDEX__CI__VI { - struct { - unsigned int DIDT_IND_INDEX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_SQ_CTRL0__CI__VI { - struct { - unsigned int DIDT_CTRL_EN : 1; - unsigned int USE_REF_CLOCK : 1; - unsigned int PHASE_OFFSET : 2; - unsigned int DIDT_CTRL_RST : 1; - unsigned int DIDT_CLK_EN_OVERRIDE : 1; - unsigned int DIDT_MAX_STALLS_ALLOWED_HI__VI : 6; - unsigned int DIDT_MAX_STALLS_ALLOWED_LO__VI : 6; - unsigned int UNUSED_0__VI : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_SQ_CTRL1__CI__VI { - struct { - unsigned int MIN_POWER : 16; - unsigned int MAX_POWER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_SQ_CTRL2__CI__VI { - struct { - unsigned int MAX_POWER_DELTA : 14; - unsigned int : 2; - unsigned int SHORT_TERM_INTERVAL_SIZE : 10; - unsigned int : 1; - unsigned int LONG_TERM_INTERVAL_RATIO : 4; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_SQ_WEIGHT0_3__CI__VI { - struct { - unsigned int WEIGHT0 : 8; - unsigned int WEIGHT1 : 8; - unsigned int WEIGHT2 : 8; - unsigned int WEIGHT3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_SQ_WEIGHT4_7__CI__VI { - struct { - unsigned int WEIGHT4 : 8; - unsigned int WEIGHT5 : 8; - unsigned int WEIGHT6 : 8; - unsigned int WEIGHT7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_SQ_WEIGHT8_11__CI__VI { - struct { - unsigned int WEIGHT8 : 8; - unsigned int WEIGHT9 : 8; - unsigned int WEIGHT10 : 8; - unsigned int WEIGHT11 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TCP_CTRL0__CI__VI { - struct { - unsigned int DIDT_CTRL_EN : 1; - unsigned int USE_REF_CLOCK : 1; - unsigned int PHASE_OFFSET : 2; - unsigned int DIDT_CTRL_RST : 1; - unsigned int DIDT_CLK_EN_OVERRIDE : 1; - unsigned int DIDT_MAX_STALLS_ALLOWED_HI__VI : 6; - unsigned int DIDT_MAX_STALLS_ALLOWED_LO__VI : 6; - unsigned int UNUSED_0__VI : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TCP_CTRL1__CI__VI { - struct { - unsigned int MIN_POWER : 16; - unsigned int MAX_POWER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TCP_CTRL2__CI__VI { - struct { - unsigned int MAX_POWER_DELTA : 14; - unsigned int : 2; - unsigned int SHORT_TERM_INTERVAL_SIZE : 10; - unsigned int : 1; - unsigned int LONG_TERM_INTERVAL_RATIO : 4; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TCP_WEIGHT0_3__CI__VI { - struct { - unsigned int WEIGHT0 : 8; - unsigned int WEIGHT1 : 8; - unsigned int WEIGHT2 : 8; - unsigned int WEIGHT3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TCP_WEIGHT4_7__CI__VI { - struct { - unsigned int WEIGHT4 : 8; - unsigned int WEIGHT5 : 8; - unsigned int WEIGHT6 : 8; - unsigned int WEIGHT7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TCP_WEIGHT8_11__CI__VI { - struct { - unsigned int WEIGHT8 : 8; - unsigned int WEIGHT9 : 8; - unsigned int WEIGHT10 : 8; - unsigned int WEIGHT11 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TD_CTRL0__CI__VI { - struct { - unsigned int DIDT_CTRL_EN : 1; - unsigned int USE_REF_CLOCK : 1; - unsigned int PHASE_OFFSET : 2; - unsigned int DIDT_CTRL_RST : 1; - unsigned int DIDT_CLK_EN_OVERRIDE : 1; - unsigned int DIDT_MAX_STALLS_ALLOWED_HI__VI : 6; - unsigned int DIDT_MAX_STALLS_ALLOWED_LO__VI : 6; - unsigned int UNUSED_0__VI : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TD_CTRL1__CI__VI { - struct { - unsigned int MIN_POWER : 16; - unsigned int MAX_POWER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TD_CTRL2__CI__VI { - struct { - unsigned int MAX_POWER_DELTA : 14; - unsigned int : 2; - unsigned int SHORT_TERM_INTERVAL_SIZE : 10; - unsigned int : 1; - unsigned int LONG_TERM_INTERVAL_RATIO : 4; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TD_WEIGHT0_3__CI__VI { - struct { - unsigned int WEIGHT0 : 8; - unsigned int WEIGHT1 : 8; - unsigned int WEIGHT2 : 8; - unsigned int WEIGHT3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TD_WEIGHT4_7__CI__VI { - struct { - unsigned int WEIGHT4 : 8; - unsigned int WEIGHT5 : 8; - unsigned int WEIGHT6 : 8; - unsigned int WEIGHT7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TD_WEIGHT8_11__CI__VI { - struct { - unsigned int WEIGHT8 : 8; - unsigned int WEIGHT9 : 8; - unsigned int WEIGHT10 : 8; - unsigned int WEIGHT11 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_CLOCK_PATTERN__SI__VI { - struct { - unsigned int DIG_CLOCK_PATTERN : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_OUTPUT_CRC_CNTL__SI__VI { - struct { - unsigned int DIG_OUTPUT_CRC_EN : 1; - unsigned int : 3; - unsigned int DIG_OUTPUT_CRC_LINK_SEL : 1; - unsigned int : 3; - unsigned int DIG_OUTPUT_CRC_DATA_SEL : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_OUTPUT_CRC_RESULT__SI__VI { - struct { - unsigned int DIG_OUTPUT_CRC_RESULT : 30; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_RANDOM_PATTERN_SEED__SI__VI { - struct { - unsigned int DIG_RANDOM_PATTERN_SEED : 24; - unsigned int DIG_RAN_PAT_DURING_DE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_TEST_PATTERN__SI__VI { - struct { - unsigned int DIG_TEST_PATTERN_OUT_EN : 1; - unsigned int DIG_HALF_CLOCK_PATTERN_SEL : 1; - unsigned int LVDS_TEST_CLOCK_DATA : 1; - unsigned int : 1; - unsigned int DIG_RANDOM_PATTERN_OUT_EN : 1; - unsigned int DIG_RANDOM_PATTERN_RESET : 1; - unsigned int DIG_TEST_PATTERN_EXTERNAL_RESET_EN : 1; - unsigned int : 1; - unsigned int LVDS_EYE_PATTERN : 1; - unsigned int : 7; - unsigned int DIG_STATIC_TEST_PATTERN : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISPCLK_CGTT_BLK_CTRL_REG__SI__VI { - struct { - unsigned int DISPCLK_TURN_ON_DELAY : 4; - unsigned int DISPCLK_TURN_OFF_DELAY : 8; - unsigned int CGTT_DISPCLK_OVERRIDE__VI : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS_CONTINUE2__SI { - struct { - unsigned int DC_HPD3_RX_INTERRUPT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int AUX3_SW_DONE_INTERRUPT : 1; - unsigned int AUX3_LS_DONE_INTERRUPT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS_CONTINUE2__VI { - struct { - unsigned int SCL_DISP3_MODE_CHANGE_INTERRUPT : 1; - unsigned int D3BLND_DATA_UNDERFLOW_INTERRUPT : 1; - unsigned int LB_D3_VLINE_INTERRUPT : 1; - unsigned int LB_D3_VBLANK_INTERRUPT : 1; - unsigned int CRTC3_SNAPSHOT_INTERRUPT : 1; - unsigned int CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1; - unsigned int CRTC3_FORCE_COUNT_NOW_INTERRUPT : 1; - unsigned int CRTC3_TRIGA_INTERRUPT : 1; - unsigned int CRTC3_TRIGB_INTERRUPT : 1; - unsigned int CRTC3_VSYNC_NOM_INTERRUPT : 1; - unsigned int CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1; - unsigned int DIGC_DP_VID_STREAM_DISABLE_INTERRUPT : 1; - unsigned int DC_HPD3_INTERRUPT : 1; - unsigned int DC_HPD3_RX_INTERRUPT : 1; - unsigned int AUX3_SW_DONE_INTERRUPT : 1; - unsigned int AUX3_LS_DONE_INTERRUPT : 1; - unsigned int LB_D4_VLINE2_INTERRUPT : 1; - unsigned int LB_D5_VLINE2_INTERRUPT : 1; - unsigned int LB_D6_VLINE2_INTERRUPT : 1; - unsigned int : 1; - unsigned int CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1; - unsigned int CRTC2_EXT_TIMING_SYNC_INTERRUPT : 1; - unsigned int CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1; - unsigned int CRTC2_VERTICAL_INTERRUPT0 : 1; - unsigned int CRTC2_VERTICAL_INTERRUPT1 : 1; - unsigned int CRTC2_VERTICAL_INTERRUPT2 : 1; - unsigned int DISP_INTERRUPT_STATUS_CONTINUE3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS_CONTINUE__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DC_HPD2_RX_INTERRUPT : 1; - unsigned int DISP_INTERRUPT_STATUS_CONTINUE2 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS_CONTINUE__VI { - struct { - unsigned int SCL_DISP2_MODE_CHANGE_INTERRUPT : 1; - unsigned int D2BLND_DATA_UNDERFLOW_INTERRUPT : 1; - unsigned int LB_D2_VLINE_INTERRUPT : 1; - unsigned int LB_D2_VBLANK_INTERRUPT : 1; - unsigned int CRTC2_SNAPSHOT_INTERRUPT : 1; - unsigned int CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1; - unsigned int CRTC2_FORCE_COUNT_NOW_INTERRUPT : 1; - unsigned int CRTC2_TRIGA_INTERRUPT : 1; - unsigned int CRTC2_TRIGB_INTERRUPT : 1; - unsigned int CRTC2_VSYNC_NOM_INTERRUPT : 1; - unsigned int CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1; - unsigned int DIGB_DP_VID_STREAM_DISABLE_INTERRUPT : 1; - unsigned int DC_HPD2_INTERRUPT : 1; - unsigned int DC_HPD2_RX_INTERRUPT : 1; - unsigned int AUX2_SW_DONE_INTERRUPT : 1; - unsigned int AUX2_LS_DONE_INTERRUPT : 1; - unsigned int LB_D1_VLINE2_INTERRUPT : 1; - unsigned int LB_D2_VLINE2_INTERRUPT : 1; - unsigned int LB_D3_VLINE2_INTERRUPT : 1; - unsigned int : 1; - unsigned int CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1; - unsigned int CRTC1_EXT_TIMING_SYNC_INTERRUPT : 1; - unsigned int CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1; - unsigned int CRTC1_VERTICAL_INTERRUPT0 : 1; - unsigned int CRTC1_VERTICAL_INTERRUPT1 : 1; - unsigned int CRTC1_VERTICAL_INTERRUPT2 : 1; - unsigned int DISP_INTERRUPT_STATUS_CONTINUE2 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS__SI { - struct { - unsigned int SCL_DISP1_MODE_CHANGE_INTERRUPT : 1; - unsigned int : 1; - unsigned int LB_D1_VLINE_INTERRUPT : 1; - unsigned int : 1; - unsigned int LB_D1_VBLANK_INTERRUPT : 1; - unsigned int : 1; - unsigned int CRTC1_SNAPSHOT_INTERRUPT : 1; - unsigned int CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1; - unsigned int CRTC1_FORCE_COUNT_NOW_INTERRUPT : 1; - unsigned int CRTC1_TRIGA_INTERRUPT : 1; - unsigned int CRTC1_TRIGB_INTERRUPT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DACA_AUTODETECT_INTERRUPT : 1; - unsigned int DACB_AUTODETECT_INTERRUPT : 1; - unsigned int DC_HPD1_INTERRUPT : 1; - unsigned int : 1; - unsigned int DC_I2C_SW_DONE_INTERRUPT : 1; - unsigned int DC_I2C_HW_DONE_INTERRUPT : 1; - unsigned int : 1; - unsigned int CRTC1_VSYNC_NOM_INTERRUPT : 1; - unsigned int : 1; - unsigned int CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1; - unsigned int : 1; - unsigned int DMCU_UC_INTERNAL_INT : 1; - unsigned int ABM1_HG_READY_INT : 1; - unsigned int ABM1_LS_READY_INT : 1; - unsigned int ABM1_BL_UPDATE_INT : 1; - unsigned int DISP_INTERRUPT_STATUS_CONTINUE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS__VI { - struct { - unsigned int SCL_DISP1_MODE_CHANGE_INTERRUPT : 1; - unsigned int D1BLND_DATA_UNDERFLOW_INTERRUPT : 1; - unsigned int LB_D1_VLINE_INTERRUPT : 1; - unsigned int LB_D1_VBLANK_INTERRUPT : 1; - unsigned int CRTC1_SNAPSHOT_INTERRUPT : 1; - unsigned int CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1; - unsigned int CRTC1_FORCE_COUNT_NOW_INTERRUPT : 1; - unsigned int CRTC1_TRIGA_INTERRUPT : 1; - unsigned int CRTC1_TRIGB_INTERRUPT : 1; - unsigned int CRTC1_VSYNC_NOM_INTERRUPT : 1; - unsigned int CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1; - unsigned int DIGA_DP_VID_STREAM_DISABLE_INTERRUPT : 1; - unsigned int DC_HPD1_INTERRUPT : 1; - unsigned int DC_HPD1_RX_INTERRUPT : 1; - unsigned int AUX1_SW_DONE_INTERRUPT : 1; - unsigned int AUX1_LS_DONE_INTERRUPT : 1; - unsigned int DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT : 1; - unsigned int DACA_AUTODETECT_INTERRUPT : 1; - unsigned int DACB_AUTODETECT_INTERRUPT : 1; - unsigned int DC_I2C_SW_DONE_INTERRUPT : 1; - unsigned int DC_I2C_HW_DONE_INTERRUPT : 1; - unsigned int DMCU_UC_INTERNAL_INT : 1; - unsigned int DMCU_SCP_INT : 1; - unsigned int ABM1_HG_READY_INT : 1; - unsigned int ABM1_LS_READY_INT : 1; - unsigned int ABM1_BL_UPDATE_INT : 1; - unsigned int DISP_INTERRUPT_STATUS_CONTINUE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_TIMER_CONTROL__SI { - struct { - unsigned int DISP_TIMER_INT_COUNT : 25; - unsigned int DISP_TIMER_INT_ENABLE : 1; - unsigned int DISP_TIMER_INT_RUNNING : 1; - unsigned int DISP_TIMER_INT_MSK : 1; - unsigned int DISP_TIMER_INT_STAT : 1; - unsigned int DISP_TIMER_INT_STAT_AK : 1; - unsigned int DISP_TIMER_INT : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DLL_CNTL__SI__CI { - struct { - unsigned int DLL_RESET_TIME : 10; - unsigned int : 2; - unsigned int DLL_LOCK_TIME : 10; - unsigned int : 2; - unsigned int MRDCK0_BYPASS : 1; - unsigned int MRDCK1_BYPASS : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMA_POSITION_LOWER_BASE_ADDRESS__SI__VI { - struct { - unsigned int DMA_POSITION_BUFFER_ENABLE : 1; - unsigned int DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS : 6; - unsigned int DMA_POSITION_LOWER_BASE_ADDRESS : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMA_POSITION_UPPER_BASE_ADDRESS__SI__VI { - struct { - unsigned int DMA_POSITION_UPPER_BASE_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_CTRL__SI { - struct { - unsigned int RESET_UC : 1; - unsigned int IGNORE_PWRMGT : 1; - unsigned int DISABLE_IRQ_TO_UC : 1; - unsigned int DISABLE_XIRQ_TO_UC : 1; - unsigned int : 18; - unsigned int UC_REG_RD_TIMEOUT : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_CTRL__VI { - struct { - unsigned int RESET_UC : 1; - unsigned int IGNORE_PWRMGT : 1; - unsigned int DISABLE_IRQ_TO_UC : 1; - unsigned int DISABLE_XIRQ_TO_UC : 1; - unsigned int DMCU_ENABLE : 1; - unsigned int : 11; - unsigned int UC_REG_RD_TIMEOUT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_ERAM_RD_CTRL__SI__VI { - struct { - unsigned int ERAM_RD_ADDR : 16; - unsigned int ERAM_RD_BE : 4; - unsigned int ERAM_RD_BYTE_MODE : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_ERAM_RD_DATA__SI__VI { - struct { - unsigned int ERAM_RD_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_ERAM_WR_CTRL__SI__VI { - struct { - unsigned int ERAM_WR_ADDR : 16; - unsigned int ERAM_WR_BE : 4; - unsigned int ERAM_WR_BYTE_MODE : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_ERAM_WR_DATA__SI__VI { - struct { - unsigned int ERAM_WR_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_EVENT_TRIGGER__SI__VI { - struct { - unsigned int GEN_SW_INT_TO_UC : 1; - unsigned int : 15; - unsigned int UC_INTERNAL_INT_CODE : 7; - unsigned int GEN_UC_INTERNAL_INT_TO_HOST : 1; - unsigned int : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_FW_CHECKSUM_SMPL_BYTE_POS__SI__VI { - struct { - unsigned int DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS : 2; - unsigned int DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS : 2; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_FW_CS_HI__SI__VI { - struct { - unsigned int FW_CHECKSUM_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_FW_CS_LO__SI__VI { - struct { - unsigned int FW_CHECKSUM_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_FW_END_ADDR__SI__VI { - struct { - unsigned int FW_END_ADDR_LSB : 8; - unsigned int FW_END_ADDR_MSB : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_FW_ISR_START_ADDR__SI__VI { - struct { - unsigned int FW_ISR_START_ADDR_LSB : 8; - unsigned int FW_ISR_START_ADDR_MSB : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_FW_START_ADDR__SI__VI { - struct { - unsigned int FW_START_ADDR_LSB : 8; - unsigned int FW_START_ADDR_MSB : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_INTERRUPT_STATUS__SI { - struct { - unsigned int ABM1_HG_READY_INT_OCCURRED : 1; - unsigned int ABM1_LS_READY_INT_OCCURRED : 1; - unsigned int ABM1_BL_UPDATE_INT_OCCURRED : 1; - unsigned int MCP_INT_OCCURRED : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int VBLANK1_INT_OCCURRED : 1; - unsigned int VBLANK2_INT_OCCURRED : 1; - unsigned int EXTERNAL_SW_INT_OCCURRED : 1; - unsigned int SCP_INT_OCCURRED : 1; - unsigned int UC_INTERNAL_INT_OCCURRED : 1; - unsigned int UC_REG_RD_TIMEOUT_INT_OCCURRED : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_INTERRUPT_STATUS__VI { - struct { - unsigned int ABM1_HG_READY_INT_OCCURRED : 1; - unsigned int ABM1_LS_READY_INT_OCCURRED : 1; - unsigned int ABM1_BL_UPDATE_INT_OCCURRED : 1; - unsigned int MCP_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DSI_POWER_UP_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED : 1; - unsigned int : 2; - unsigned int EXTERNAL_SW_INT_OCCURRED : 1; - unsigned int SCP_INT_OCCURRED : 1; - unsigned int UC_INTERNAL_INT_OCCURRED : 1; - unsigned int UC_REG_RD_TIMEOUT_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED : 1; - unsigned int DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED : 1; - unsigned int VBLANK1_INT_OCCURRED : 1; - unsigned int VBLANK2_INT_OCCURRED : 1; - unsigned int VBLANK3_INT_OCCURRED : 1; - unsigned int VBLANK4_INT_OCCURRED : 1; - unsigned int VBLANK5_INT_OCCURRED : 1; - unsigned int VBLANK6_INT_OCCURRED : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_INTERRUPT_TO_HOST_EN_MASK__SI__VI { - struct { - unsigned int ABM1_HG_READY_INT_MASK : 1; - unsigned int ABM1_LS_READY_INT_MASK : 1; - unsigned int ABM1_BL_UPDATE_INT_MASK : 1; - unsigned int : 1; - unsigned int DCPG_IHC_DSI_POWER_UP_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DSI_POWER_DOWN_INT_MASK__VI : 1; - unsigned int : 3; - unsigned int SCP_INT_MASK : 1; - unsigned int UC_INTERNAL_INT_MASK : 1; - unsigned int UC_REG_RD_TIMEOUT_INT_MASK : 1; - unsigned int DCPG_IHC_DCFE0_POWER_UP_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DCFE1_POWER_UP_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DCFE2_POWER_UP_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DCFE3_POWER_UP_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DCFE4_POWER_UP_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DCFE5_POWER_UP_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__VI : 1; - unsigned int DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__VI : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_INTERRUPT_TO_UC_EN_MASK__SI { - struct { - unsigned int ABM1_HG_READY_INT_TO_UC_EN : 1; - unsigned int ABM1_LS_READY_INT_TO_UC_EN : 1; - unsigned int ABM1_BL_UPDATE_INT_TO_UC_EN : 1; - unsigned int MCP_INT_TO_UC_EN : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int VBLANK1_INT_TO_UC_EN : 1; - unsigned int VBLANK2_INT_TO_UC_EN : 1; - unsigned int EXTERNAL_SW_INT_TO_UC_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_INTERRUPT_TO_UC_EN_MASK__VI { - struct { - unsigned int ABM1_HG_READY_INT_TO_UC_EN : 1; - unsigned int ABM1_LS_READY_INT_TO_UC_EN : 1; - unsigned int ABM1_BL_UPDATE_INT_TO_UC_EN : 1; - unsigned int MCP_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN : 1; - unsigned int STATIC_SCREEN1_INT_TO_UC_EN : 1; - unsigned int STATIC_SCREEN2_INT_TO_UC_EN : 1; - unsigned int EXTERNAL_SW_INT_TO_UC_EN : 1; - unsigned int STATIC_SCREEN3_INT_TO_UC_EN : 1; - unsigned int STATIC_SCREEN4_INT_TO_UC_EN : 1; - unsigned int STATIC_SCREEN5_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN : 1; - unsigned int DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN : 1; - unsigned int VBLANK1_INT_TO_UC_EN : 1; - unsigned int VBLANK2_INT_TO_UC_EN : 1; - unsigned int VBLANK3_INT_TO_UC_EN : 1; - unsigned int VBLANK4_INT_TO_UC_EN : 1; - unsigned int VBLANK5_INT_TO_UC_EN : 1; - unsigned int VBLANK6_INT_TO_UC_EN : 1; - unsigned int STATIC_SCREEN6_INT_TO_UC_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__SI { - struct { - unsigned int ABM1_HG_READY_INT_XIRQ_IRQ_SEL : 1; - unsigned int ABM1_LS_READY_INT_XIRQ_IRQ_SEL : 1; - unsigned int ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL : 1; - unsigned int MCP_INT_XIRQ_IRQ_SEL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int VBLANK1_INT_XIRQ_IRQ_SEL : 1; - unsigned int VBLANK2_INT_XIRQ_IRQ_SEL : 1; - unsigned int EXTERNAL_SW_INT_XIRQ_IRQ_SEL : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VI { - struct { - unsigned int ABM1_HG_READY_INT_XIRQ_IRQ_SEL : 1; - unsigned int ABM1_LS_READY_INT_XIRQ_IRQ_SEL : 1; - unsigned int ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL : 1; - unsigned int MCP_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1; - unsigned int STATIC_SCREEN1_INT_XIRQ_IRQ_SEL : 1; - unsigned int STATIC_SCREEN2_INT_XIRQ_IRQ_SEL : 1; - unsigned int EXTERNAL_SW_INT_XIRQ_IRQ_SEL : 1; - unsigned int STATIC_SCREEN3_INT_XIRQ_IRQ_SEL : 1; - unsigned int STATIC_SCREEN4_INT_XIRQ_IRQ_SEL : 1; - unsigned int STATIC_SCREEN5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL : 1; - unsigned int VBLANK1_INT_XIRQ_IRQ_SEL : 1; - unsigned int VBLANK2_INT_XIRQ_IRQ_SEL : 1; - unsigned int VBLANK3_INT_XIRQ_IRQ_SEL : 1; - unsigned int VBLANK4_INT_XIRQ_IRQ_SEL : 1; - unsigned int VBLANK5_INT_XIRQ_IRQ_SEL : 1; - unsigned int VBLANK6_INT_XIRQ_IRQ_SEL : 1; - unsigned int STATIC_SCREEN6_INT_XIRQ_IRQ_SEL : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_INT_CNT__SI__VI { - struct { - unsigned int DMCU_ABM1_HG_READY_INT_CNT : 8; - unsigned int DMCU_ABM1_LS_READY_INT_CNT : 8; - unsigned int DMCU_ABM1_BL_UPDATE_INT_CNT : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_IRAM_RD_CTRL__SI__VI { - struct { - unsigned int IRAM_RD_ADDR : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_IRAM_RD_DATA__SI__VI { - struct { - unsigned int IRAM_RD_DATA : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_IRAM_WR_CTRL__SI__VI { - struct { - unsigned int IRAM_WR_ADDR : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_IRAM_WR_DATA__SI__VI { - struct { - unsigned int IRAM_WR_DATA : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PC_START_ADDR__SI__VI { - struct { - unsigned int PC_START_ADDR_LSB : 8; - unsigned int PC_START_ADDR_MSB : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_RAM_ACCESS_CTRL__SI__VI { - struct { - unsigned int ERAM_WR_ADDR_AUTO_INC : 1; - unsigned int ERAM_RD_ADDR_AUTO_INC : 1; - unsigned int IRAM_WR_ADDR_AUTO_INC : 1; - unsigned int IRAM_RD_ADDR_AUTO_INC : 1; - unsigned int ERAM_HOST_ACCESS_EN__VI : 1; - unsigned int IRAM_HOST_ACCESS_EN__VI : 1; - unsigned int : 2; - unsigned int UC_RST_RELEASE_DELAY_CNT__VI : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_STATUS__SI__VI { - struct { - unsigned int UC_IN_RESET : 1; - unsigned int UC_IN_WAIT_MODE : 1; - unsigned int UC_IN_STOP_MODE : 1; - unsigned int : 28; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int DMCU_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int DMCU_TEST_DEBUG_INDEX : 8; - unsigned int DMCU_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_UC_INTERNAL_INT_STATUS__SI__VI { - struct { - unsigned int UC_INT_IRQ_N_PIN : 1; - unsigned int UC_INT_XIRQ_N_PIN : 1; - unsigned int UC_INT_SOFTWARE_INTERRUPT : 1; - unsigned int UC_INT_ILLEGAL_OPCODE_TRAP : 1; - unsigned int UC_INT_TIMER_OUTPUT_COMPARE_4 : 1; - unsigned int UC_INT_TIMER_OUTPUT_COMPARE_3 : 1; - unsigned int UC_INT_TIMER_OUTPUT_COMPARE_2 : 1; - unsigned int UC_INT_TIMER_OUTPUT_COMPARE_1 : 1; - unsigned int UC_INT_TIMER_OVERFLOW : 1; - unsigned int UC_INT_REAL_TIME_INTERRUPT : 1; - unsigned int UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5 : 1; - unsigned int UC_INT_TIMER_INPUT_CAPTURE_3 : 1; - unsigned int UC_INT_TIMER_INPUT_CAPTURE_2 : 1; - unsigned int UC_INT_TIMER_INPUT_CAPTURE_1 : 1; - unsigned int UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE : 1; - unsigned int UC_INT_PULSE_ACCUMULATOR_OVERFLOW : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_ARBITRATION_CONTROL__SI__VI { - struct { - unsigned int DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD : 16; - unsigned int PIPE_SWITCH_EFFICIENCY_WEIGHT__VI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_CONTROL__SI__VI { - struct { - unsigned int DMIF_BUFF_SIZE : 2; - unsigned int DMIF_GROUP_REQUESTS_IN_CHUNK__VI : 1; - unsigned int : 1; - unsigned int DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__VI : 1; - unsigned int : 3; - unsigned int DMIF_REQ_BURST_SIZE : 3; - unsigned int DMIF_UNDERFLOW_RECOVERY_EN__VI : 1; - unsigned int DMIF_FORCE_TOTAL_REQ_BURST_SIZE__VI : 4; - unsigned int DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__VI : 6; - unsigned int : 2; - unsigned int DMIF_DELAY_ARBITRATION__VI : 5; - unsigned int DMIF_CHUNK_BUFF_MARGIN__VI : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_DEBUG02__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_HW_DEBUG__SI__VI { - struct { - unsigned int DMIF_HW_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_STATUS__SI__VI { - struct { - unsigned int DMIF_MC_SEND_ON_IDLE : 8; - unsigned int DMIF_CLEAR_MC_SEND_ON_IDLE : 8; - unsigned int DMIF_MC_LATENCY_COUNTER_ENABLE : 1; - unsigned int DMIF_MC_LATENCY_COUNTER_URGENT_ONLY : 1; - unsigned int : 2; - unsigned int DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__VI : 3; - unsigned int : 1; - unsigned int DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__VI : 3; - unsigned int : 1; - unsigned int DMIF_UNDERFLOW__VI : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int DMIF_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int DMIF_TEST_DEBUG_INDEX : 8; - unsigned int DMIF_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DOUT_POWER_MANAGEMENT_CNTL__SI { - struct { - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int PM_ASSERT_RESET : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DOUT_SCRATCH0__SI { - struct { - unsigned int DOUT_SCRATCH0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DOUT_SCRATCH1__SI { - struct { - unsigned int DOUT_SCRATCH1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DOUT_SCRATCH2__SI { - struct { - unsigned int DOUT_SCRATCH2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DOUT_SCRATCH3__SI { - struct { - unsigned int DOUT_SCRATCH3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DOUT_SCRATCH4__SI { - struct { - unsigned int DOUT_SCRATCH4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DOUT_SCRATCH5__SI { - struct { - unsigned int DOUT_SCRATCH5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DOUT_SCRATCH6__SI { - struct { - unsigned int DOUT_SCRATCH6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DOUT_SCRATCH7__SI { - struct { - unsigned int DOUT_SCRATCH7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DOUT_TEST_DEBUG_DATA__SI { - struct { - unsigned int DOUT_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DOUT_TEST_DEBUG_INDEX__SI { - struct { - unsigned int DOUT_TEST_DEBUG_INDEX : 8; - unsigned int DOUT_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX1_DEBUG_A__SI { - struct { - unsigned int DP_AUX1_DEBUG_A : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX1_DEBUG_B__SI { - struct { - unsigned int DP_AUX1_DEBUG_B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX1_DEBUG_C__SI { - struct { - unsigned int DP_AUX1_DEBUG_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX1_DEBUG_D__SI { - struct { - unsigned int DP_AUX1_DEBUG_D : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX1_DEBUG_E__SI { - struct { - unsigned int DP_AUX1_DEBUG_E : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX1_DEBUG_F__SI { - struct { - unsigned int DP_AUX1_DEBUG_F : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX1_DEBUG_G__SI { - struct { - unsigned int DP_AUX1_DEBUG_G : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX1_DEBUG_H__SI { - struct { - unsigned int DP_AUX1_DEBUG_H : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX1_DEBUG_I__SI { - struct { - unsigned int DP_AUX1_DEBUG_I : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX2_DEBUG_A__SI { - struct { - unsigned int DP_AUX2_DEBUG_A : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX2_DEBUG_B__SI { - struct { - unsigned int DP_AUX2_DEBUG_B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX2_DEBUG_C__SI { - struct { - unsigned int DP_AUX2_DEBUG_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX2_DEBUG_D__SI { - struct { - unsigned int DP_AUX2_DEBUG_D : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX2_DEBUG_E__SI { - struct { - unsigned int DP_AUX2_DEBUG_E : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX2_DEBUG_F__SI { - struct { - unsigned int DP_AUX2_DEBUG_F : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX2_DEBUG_G__SI { - struct { - unsigned int DP_AUX2_DEBUG_G : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX2_DEBUG_H__SI { - struct { - unsigned int DP_AUX2_DEBUG_H : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX2_DEBUG_I__SI { - struct { - unsigned int DP_AUX2_DEBUG_I : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX3_DEBUG_A__SI { - struct { - unsigned int DP_AUX3_DEBUG_A : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX3_DEBUG_B__SI { - struct { - unsigned int DP_AUX3_DEBUG_B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX3_DEBUG_C__SI { - struct { - unsigned int DP_AUX3_DEBUG_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX3_DEBUG_D__SI { - struct { - unsigned int DP_AUX3_DEBUG_D : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX3_DEBUG_E__SI { - struct { - unsigned int DP_AUX3_DEBUG_E : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX3_DEBUG_F__SI { - struct { - unsigned int DP_AUX3_DEBUG_F : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX3_DEBUG_G__SI { - struct { - unsigned int DP_AUX3_DEBUG_G : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX3_DEBUG_H__SI { - struct { - unsigned int DP_AUX3_DEBUG_H : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX3_DEBUG_I__SI { - struct { - unsigned int DP_AUX3_DEBUG_I : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX4_DEBUG_A__SI { - struct { - unsigned int DP_AUX4_DEBUG_A : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX4_DEBUG_B__SI { - struct { - unsigned int DP_AUX4_DEBUG_B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX4_DEBUG_C__SI { - struct { - unsigned int DP_AUX4_DEBUG_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX4_DEBUG_D__SI { - struct { - unsigned int DP_AUX4_DEBUG_D : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX4_DEBUG_E__SI { - struct { - unsigned int DP_AUX4_DEBUG_E : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX4_DEBUG_F__SI { - struct { - unsigned int DP_AUX4_DEBUG_F : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX4_DEBUG_G__SI { - struct { - unsigned int DP_AUX4_DEBUG_G : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX4_DEBUG_H__SI { - struct { - unsigned int DP_AUX4_DEBUG_H : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX4_DEBUG_I__SI { - struct { - unsigned int DP_AUX4_DEBUG_I : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX5_DEBUG_A__SI { - struct { - unsigned int DP_AUX5_DEBUG_A : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX5_DEBUG_B__SI { - struct { - unsigned int DP_AUX5_DEBUG_B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX5_DEBUG_C__SI { - struct { - unsigned int DP_AUX5_DEBUG_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX5_DEBUG_D__SI { - struct { - unsigned int DP_AUX5_DEBUG_D : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX5_DEBUG_E__SI { - struct { - unsigned int DP_AUX5_DEBUG_E : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX5_DEBUG_F__SI { - struct { - unsigned int DP_AUX5_DEBUG_F : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX5_DEBUG_G__SI { - struct { - unsigned int DP_AUX5_DEBUG_G : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX5_DEBUG_H__SI { - struct { - unsigned int DP_AUX5_DEBUG_H : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX5_DEBUG_I__SI { - struct { - unsigned int DP_AUX5_DEBUG_I : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX6_DEBUG_A__SI { - struct { - unsigned int DP_AUX6_DEBUG_A : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX6_DEBUG_B__SI { - struct { - unsigned int DP_AUX6_DEBUG_B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX6_DEBUG_C__SI { - struct { - unsigned int DP_AUX6_DEBUG_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX6_DEBUG_D__SI { - struct { - unsigned int DP_AUX6_DEBUG_D : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX6_DEBUG_E__SI { - struct { - unsigned int DP_AUX6_DEBUG_E : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX6_DEBUG_F__SI { - struct { - unsigned int DP_AUX6_DEBUG_F : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX6_DEBUG_G__SI { - struct { - unsigned int DP_AUX6_DEBUG_G : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX6_DEBUG_H__SI { - struct { - unsigned int DP_AUX6_DEBUG_H : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX6_DEBUG_I__SI { - struct { - unsigned int DP_AUX6_DEBUG_I : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_CONFIG__SI__VI { - struct { - unsigned int DP_UDI_LANES : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_8B10B_CNTL__SI { - struct { - unsigned int : 8; - unsigned int DPHY_8B10B_RESET : 1; - unsigned int : 7; - unsigned int DPHY_8B10B_EXT_DISP : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_8B10B_CNTL__VI { - struct { - unsigned int : 8; - unsigned int DPHY_8B10B_RESET : 1; - unsigned int : 7; - unsigned int DPHY_8B10B_EXT_DISP : 1; - unsigned int : 7; - unsigned int DPHY_8B10B_CUR_DISP : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_CNTL__SI__VI { - struct { - unsigned int DPHY_ATEST_SEL_LANE0 : 1; - unsigned int DPHY_ATEST_SEL_LANE1 : 1; - unsigned int DPHY_ATEST_SEL_LANE2 : 1; - unsigned int DPHY_ATEST_SEL_LANE3 : 1; - unsigned int : 4; - unsigned int : 1; - unsigned int : 7; - unsigned int DPHY_BYPASS : 1; - unsigned int : 7; - unsigned int DPHY_SKEW_BYPASS : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_CRC_CNTL__SI__VI { - struct { - unsigned int DPHY_CRC_FIELD : 1; - unsigned int : 3; - unsigned int DPHY_CRC_SEL : 2; - unsigned int : 10; - unsigned int DPHY_CRC_MASK : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_CRC_EN__SI__VI { - struct { - unsigned int DPHY_CRC_EN : 1; - unsigned int : 3; - unsigned int DPHY_CRC_CONT_EN : 1; - unsigned int : 3; - unsigned int DPHY_CRC_RESULT_VALID__VI : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_CRC_RESULT__SI__VI { - struct { - unsigned int DPHY_CRC_RESULT : 8; - unsigned int DPHY_CRC_RESULT1__VI : 8; - unsigned int DPHY_CRC_RESULT2__VI : 8; - unsigned int DPHY_CRC_RESULT3__VI : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_FAST_TRAINING__SI { - struct { - unsigned int DPHY_RX_FAST_TRAINING_CAPABLE : 1; - unsigned int DPHY_SW_FAST_TRAINING_START : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DPHY_FAST_TRAINING_TP1_TIME : 12; - unsigned int DPHY_FAST_TRAINING_TP2_TIME : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_FAST_TRAINING__VI { - struct { - unsigned int DPHY_RX_FAST_TRAINING_CAPABLE : 1; - unsigned int DPHY_SW_FAST_TRAINING_START : 1; - unsigned int DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN : 1; - unsigned int : 5; - unsigned int DPHY_FAST_TRAINING_TP1_TIME : 12; - unsigned int DPHY_FAST_TRAINING_TP2_TIME : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_PRBS_CNTL__SI__VI { - struct { - unsigned int DPHY_PRBS_EN : 1; - unsigned int : 3; - unsigned int DPHY_PRBS_SEL : 2; - unsigned int : 2; - unsigned int DPHY_PRBS_SEED : 23; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_SYM__SI { - struct { - unsigned int : 10; - unsigned int : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_TRAINING_PATTERN_SEL__SI__VI { - struct { - unsigned int DPHY_TRAINING_PATTERN_SEL : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO0_MODULO__SI__VI { - struct { - unsigned int DP_DTO0_MODULO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO0_PHASE__SI__VI { - struct { - unsigned int DP_DTO0_PHASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO1_MODULO__SI__VI { - struct { - unsigned int DP_DTO1_MODULO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO1_PHASE__SI__VI { - struct { - unsigned int DP_DTO1_PHASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO2_MODULO__SI__VI { - struct { - unsigned int DP_DTO2_MODULO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO2_PHASE__SI__VI { - struct { - unsigned int DP_DTO2_PHASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO3_MODULO__SI__VI { - struct { - unsigned int DP_DTO3_MODULO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO3_PHASE__SI__VI { - struct { - unsigned int DP_DTO3_PHASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO4_MODULO__SI__VI { - struct { - unsigned int DP_DTO4_MODULO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO4_PHASE__SI__VI { - struct { - unsigned int DP_DTO4_PHASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO5_MODULO__SI__VI { - struct { - unsigned int DP_DTO5_MODULO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DTO5_PHASE__SI__VI { - struct { - unsigned int DP_DTO5_PHASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_LINK_CNTL__SI { - struct { - unsigned int : 4; - unsigned int DP_LINK_TRAINING_COMPLETE : 1; - unsigned int : 3; - unsigned int DP_LINK_STATUS : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int DP_EMBEDDED_PANEL_MODE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_LINK_CNTL__VI { - struct { - unsigned int : 4; - unsigned int DP_LINK_TRAINING_COMPLETE : 1; - unsigned int : 3; - unsigned int DP_LINK_STATUS : 1; - unsigned int : 8; - unsigned int DP_EMBEDDED_PANEL_MODE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_PIXEL_FORMAT__SI__VI { - struct { - unsigned int DP_PIXEL_ENCODING : 3; - unsigned int : 5; - unsigned int DP_DYN_RANGE : 1; - unsigned int : 7; - unsigned int DP_YCBCR_RANGE : 1; - unsigned int : 7; - unsigned int DP_COMPONENT_DEPTH : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_AUD_M_READBACK__SI__VI { - struct { - unsigned int DP_SEC_AUD_M_READBACK : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_AUD_M__SI__VI { - struct { - unsigned int DP_SEC_AUD_M : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_AUD_N_READBACK__SI__VI { - struct { - unsigned int DP_SEC_AUD_N_READBACK : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_AUD_N__SI__VI { - struct { - unsigned int DP_SEC_AUD_N : 24; - unsigned int : 4; - unsigned int : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_CNTL__SI { - struct { - unsigned int DP_SEC_STREAM_ENABLE : 1; - unsigned int : 3; - unsigned int DP_SEC_ASP_ENABLE : 1; - unsigned int : 3; - unsigned int DP_SEC_ATP_ENABLE : 1; - unsigned int : 3; - unsigned int DP_SEC_AIP_ENABLE : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 3; - unsigned int DP_SEC_AVI_ENABLE : 1; - unsigned int : 3; - unsigned int DP_SEC_MPG_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_CNTL__VI { - struct { - unsigned int DP_SEC_STREAM_ENABLE : 1; - unsigned int : 3; - unsigned int DP_SEC_ASP_ENABLE : 1; - unsigned int : 3; - unsigned int DP_SEC_ATP_ENABLE : 1; - unsigned int : 3; - unsigned int DP_SEC_AIP_ENABLE : 1; - unsigned int : 3; - unsigned int DP_SEC_ACM_ENABLE : 1; - unsigned int : 3; - unsigned int DP_SEC_GSP0_ENABLE : 1; - unsigned int DP_SEC_GSP1_ENABLE : 1; - unsigned int DP_SEC_GSP2_ENABLE : 1; - unsigned int DP_SEC_GSP3_ENABLE : 1; - unsigned int DP_SEC_AVI_ENABLE : 1; - unsigned int : 3; - unsigned int DP_SEC_MPG_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_FRAMING1__SI__VI { - struct { - unsigned int DP_SEC_FRAME_START_LOCATION : 12; - unsigned int : 4; - unsigned int DP_SEC_VBLANK_TRANSMIT_WIDTH : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_FRAMING2__SI__VI { - struct { - unsigned int DP_SEC_START_POSITION : 16; - unsigned int DP_SEC_HBLANK_TRANSMIT_WIDTH : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_FRAMING3__SI__VI { - struct { - unsigned int DP_SEC_IDLE_FRAME_SIZE : 14; - unsigned int : 2; - unsigned int DP_SEC_IDLE_TRANSMIT_WIDTH : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_FRAMING4__SI__VI { - struct { - unsigned int : 20; - unsigned int DP_SEC_COLLISION_STATUS : 1; - unsigned int : 3; - unsigned int DP_SEC_COLLISION_ACK : 1; - unsigned int : 3; - unsigned int DP_SEC_AUDIO_MUTE : 1; - unsigned int DP_SEC_AUDIO_MUTE_STATUS : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_PACKET_CNTL__SI { - struct { - unsigned int DP_SEC_ASP_CODING_TYPE : 4; - unsigned int DP_SEC_ASP_PRIORITY : 1; - unsigned int : 3; - unsigned int DP_SEC_VERSION : 6; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_PACKET_CNTL__VI { - struct { - unsigned int : 1; - unsigned int DP_SEC_ASP_CODING_TYPE : 3; - unsigned int DP_SEC_ASP_PRIORITY : 1; - unsigned int : 3; - unsigned int DP_SEC_VERSION : 6; - unsigned int : 2; - unsigned int DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_TIMESTAMP__SI__VI { - struct { - unsigned int DP_SEC_TIMESTAMP_MODE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_STEER_FIFO__SI__VI { - struct { - unsigned int DP_STEER_FIFO_RESET : 1; - unsigned int : 3; - unsigned int DP_STEER_OVERFLOW_FLAG : 1; - unsigned int DP_STEER_OVERFLOW_INT : 1; - unsigned int DP_STEER_OVERFLOW_ACK : 1; - unsigned int DP_STEER_OVERFLOW_MASK : 1; - unsigned int DP_TU_OVERFLOW_FLAG__VI : 1; - unsigned int : 3; - unsigned int DP_TU_OVERFLOW_ACK__VI : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int DP_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int DP_TEST_DEBUG_INDEX : 8; - unsigned int DP_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_VID_INTERRUPT_CNTL__SI__VI { - struct { - unsigned int DP_VID_STREAM_DISABLE_INT : 1; - unsigned int DP_VID_STREAM_DISABLE_ACK : 1; - unsigned int DP_VID_STREAM_DISABLE_MASK : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_VID_MSA_VBID__SI__VI { - struct { - unsigned int DP_VID_MSA_LOCATION : 12; - unsigned int : 4; - unsigned int DP_VID_MSA_TOP_FIELD_MODE : 1; - unsigned int : 7; - unsigned int DP_VID_VBID_FIELD_POL : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_VID_M__SI__VI { - struct { - unsigned int DP_VID_M : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_VID_N__SI__VI { - struct { - unsigned int DP_VID_N : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_VID_STREAM_CNTL__SI__VI { - struct { - unsigned int DP_VID_STREAM_ENABLE : 1; - unsigned int : 7; - unsigned int DP_VID_STREAM_DIS_DEFER : 2; - unsigned int : 6; - unsigned int DP_VID_STREAM_STATUS : 1; - unsigned int : 3; - unsigned int DP_VID_STREAM_CHANGE_KEEPOUT : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_VID_TIMING__SI__VI { - struct { - unsigned int DP_VID_TIMING_MODE : 1; - unsigned int : 7; - unsigned int DP_VID_M_N_GEN_EN : 1; - unsigned int : 15; - unsigned int DP_VID_N_DIV : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVOACLKC_CNTL__SI__VI { - struct { - unsigned int DVOACLKC_FINE_SKEW_CNTL : 3; - unsigned int : 5; - unsigned int DVOACLKC_COARSE_SKEW_CNTL : 5; - unsigned int : 3; - unsigned int DVOACLKC_FINE_ADJUST_EN : 1; - unsigned int DVOACLKC_COARSE_ADJUST_EN : 1; - unsigned int DVOACLKC_IN_PHASE : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVOACLKC_MVP_CNTL__SI__VI { - struct { - unsigned int DVOACLKC_MVP_FINE_SKEW_CNTL : 3; - unsigned int : 5; - unsigned int DVOACLKC_MVP_COARSE_SKEW_CNTL : 5; - unsigned int : 3; - unsigned int DVOACLKC_MVP_FINE_ADJUST_EN : 1; - unsigned int DVOACLKC_MVP_COARSE_ADJUST_EN : 1; - unsigned int DVOACLKC_MVP_IN_PHASE : 1; - unsigned int : 1; - unsigned int DVOACLKC_MVP_SKEW_PHASE_OVERRIDE : 1; - unsigned int : 3; - unsigned int MVP_CLK_A_SRC_SEL : 2; - unsigned int : 2; - unsigned int MVP_CLK_B_SRC_SEL : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVOACLKD_CNTL__SI__VI { - struct { - unsigned int DVOACLKD_FINE_SKEW_CNTL : 3; - unsigned int : 5; - unsigned int DVOACLKD_COARSE_SKEW_CNTL : 5; - unsigned int : 3; - unsigned int DVOACLKD_FINE_ADJUST_EN : 1; - unsigned int DVOACLKD_COARSE_ADJUST_EN : 1; - unsigned int DVOACLKD_IN_PHASE : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_CONTROL__SI { - struct { - unsigned int DVO_RATE_SELECT : 1; - unsigned int DVO_SDRCLK_SEL : 1; - unsigned int : 6; - unsigned int DVO_DUAL_CHANNEL_EN : 1; - unsigned int : 7; - unsigned int DVO_RESET_FIFO : 1; - unsigned int DVO_SYNC_PHASE : 1; - unsigned int DVO_INVERT_DVOCLK : 1; - unsigned int : 5; - unsigned int DVO_COLOR_FORMAT : 2; - unsigned int : 2; - unsigned int : 1; - unsigned int : 2; - unsigned int DVO_CTL3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_CONTROL__VI { - struct { - unsigned int DVO_RATE_SELECT : 1; - unsigned int DVO_SDRCLK_SEL : 1; - unsigned int : 2; - unsigned int DVO_DVPDATA_WIDTH : 2; - unsigned int : 2; - unsigned int DVO_DUAL_CHANNEL_EN : 1; - unsigned int : 7; - unsigned int DVO_RESET_FIFO : 1; - unsigned int DVO_SYNC_PHASE : 1; - unsigned int DVO_INVERT_DVOCLK : 1; - unsigned int : 1; - unsigned int DVO_HSYNC_POLARITY : 1; - unsigned int DVO_VSYNC_POLARITY : 1; - unsigned int DVO_DE_POLARITY : 1; - unsigned int : 1; - unsigned int DVO_COLOR_FORMAT : 2; - unsigned int : 5; - unsigned int DVO_CTL3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_CRC2_SIG_MASK__SI__VI { - struct { - unsigned int DVO_CRC2_SIG_MASK : 27; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_CRC2_SIG_RESULT__SI__VI { - struct { - unsigned int DVO_CRC2_SIG_RESULT : 27; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_CRC_EN__SI__VI { - struct { - unsigned int : 16; - unsigned int DVO_CRC2_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_ENABLE__SI { - struct { - unsigned int DVO_ENABLE : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_ENABLE__VI { - struct { - unsigned int DVO_ENABLE : 1; - unsigned int : 3; - unsigned int DVO_PIXEL_WIDTH : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_OUTPUT__SI__VI { - struct { - unsigned int DVO_OUTPUT_ENABLE_MODE : 2; - unsigned int : 6; - unsigned int DVO_CLOCK_MODE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_SOURCE_SELECT__SI__VI { - struct { - unsigned int DVO_SOURCE_SELECT : 3; - unsigned int : 13; - unsigned int DVO_STEREOSYNC_SELECT : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_STRENGTH_CONTROL__SI { - struct { - unsigned int DVO_SP : 4; - unsigned int DVO_SN : 4; - unsigned int DVOCLK_SP : 4; - unsigned int DVOCLK_SN : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int DVO_LSB_VMODE : 1; - unsigned int DVO_MSB_VMODE : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_STRENGTH_CONTROL__VI { - struct { - unsigned int DVO_SP : 4; - unsigned int DVO_SN : 4; - unsigned int DVOCLK_SP : 4; - unsigned int DVOCLK_SN : 4; - unsigned int DVO_DRVSTRENGTH : 3; - unsigned int : 1; - unsigned int DVOCLK_DRVSTRENGTH : 3; - unsigned int : 1; - unsigned int FLDO_VITNE_DRVSTRENGTH : 3; - unsigned int : 1; - unsigned int DVO_LSB_VMODE : 1; - unsigned int DVO_MSB_VMODE : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EFUSE_STATUS__CI__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 14; - unsigned int : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EXP0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EXP1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EXP2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EXP3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EXP4 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EXP5 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EXP6 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EXP7 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EXTERN_TRIG_CNTL__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EXT_OVERSCAN_LEFT_RIGHT__SI__VI { - struct { - unsigned int EXT_OVERSCAN_RIGHT : 13; - unsigned int : 3; - unsigned int EXT_OVERSCAN_LEFT : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union EXT_OVERSCAN_TOP_BOTTOM__SI__VI { - struct { - unsigned int EXT_OVERSCAN_BOTTOM : 13; - unsigned int : 3; - unsigned int EXT_OVERSCAN_TOP : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_CLIENT_REGION_MASK__SI__VI { - struct { - unsigned int : 16; - unsigned int FBC_MEMORY_REGION_MASK : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_CNTL__SI__VI { - struct { - unsigned int FBC_GRPH_COMP_EN : 1; - unsigned int FBC_SRC_SEL : 3; - unsigned int : 12; - unsigned int FBC_COHERENCY_MODE : 2; - unsigned int : 7; - unsigned int FBC_SOFT_COMPRESS_EN : 1; - unsigned int : 5; - unsigned int FBC_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_COMP_CNTL__SI__VI { - struct { - unsigned int FBC_MIN_COMPRESSION : 4; - unsigned int : 12; - unsigned int FBC_DEPTH_MONO08_EN : 1; - unsigned int FBC_DEPTH_MONO16_EN : 1; - unsigned int FBC_DEPTH_RGB04_EN : 1; - unsigned int FBC_DEPTH_RGB08_EN : 1; - unsigned int FBC_DEPTH_RGB16_EN : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_COMP_MODE__SI__VI { - struct { - unsigned int FBC_RLE_EN : 1; - unsigned int : 7; - unsigned int FBC_DPCM4_RGB_EN : 1; - unsigned int FBC_DPCM8_RGB_EN : 1; - unsigned int FBC_DPCM4_YUV_EN : 1; - unsigned int FBC_DPCM8_YUV_EN : 1; - unsigned int : 4; - unsigned int FBC_IND_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_CSM_REGION_OFFSET_01__SI__VI { - struct { - unsigned int FBC_CSM_REGION_OFFSET_0 : 10; - unsigned int : 6; - unsigned int FBC_CSM_REGION_OFFSET_1 : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_CSM_REGION_OFFSET_23__SI__VI { - struct { - unsigned int FBC_CSM_REGION_OFFSET_2 : 10; - unsigned int : 6; - unsigned int FBC_CSM_REGION_OFFSET_3 : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_DEBUG0__SI__VI { - struct { - unsigned int FBC_PERF_MUX0 : 8; - unsigned int FBC_PERF_MUX1 : 8; - unsigned int FBC_COMP_WAKE_DIS : 1; - unsigned int FBC_DEBUG0 : 7; - unsigned int FBC_DEBUG_MUX : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_DEBUG1__SI__VI { - struct { - unsigned int FBC_DEBUG1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_DEBUG2__SI__VI { - struct { - unsigned int FBC_DEBUG2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_DEBUG_COMP__SI__VI { - struct { - unsigned int FBC_COMP_SWAP : 2; - unsigned int : 1; - unsigned int FBC_COMP_RSIZE : 1; - unsigned int FBC_COMP_BUSY_HYSTERESIS : 4; - unsigned int FBC_COMP_CLK_CNTL : 2; - unsigned int FBC_COMP_PRIVILEGED_ACCESS_ENABLE__VI : 1; - unsigned int FBC_COMP_ADDRESS_TRANSLATION_ENABLE__VI : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_DEBUG_CSR_RDATA__SI__VI { - struct { - unsigned int FBC_DEBUG_CSR_RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_DEBUG_CSR_WDATA__SI__VI { - struct { - unsigned int FBC_DEBUG_CSR_WDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_DEBUG_CSR__SI__VI { - struct { - unsigned int FBC_DEBUG_CSR_ADDR : 10; - unsigned int : 6; - unsigned int FBC_DEBUG_CSR_WR_DATA__VI : 1; - unsigned int FBC_DEBUG_CSR_RD_DATA__VI : 1; - unsigned int : 13; - unsigned int FBC_DEBUG_CSR_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IDLE_FORCE_CLEAR_MASK__SI__VI { - struct { - unsigned int FBC_IDLE_FORCE_CLEAR_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IDLE_MASK__SI__VI { - struct { - unsigned int FBC_IDLE_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT0__SI__VI { - struct { - unsigned int FBC_IND_LUT0 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT10__SI__VI { - struct { - unsigned int FBC_IND_LUT10 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT11__SI__VI { - struct { - unsigned int FBC_IND_LUT11 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT12__SI__VI { - struct { - unsigned int FBC_IND_LUT12 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT13__SI__VI { - struct { - unsigned int FBC_IND_LUT13 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT14__SI__VI { - struct { - unsigned int FBC_IND_LUT14 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT15__SI__VI { - struct { - unsigned int FBC_IND_LUT15 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT1__SI__VI { - struct { - unsigned int FBC_IND_LUT1 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT2__SI__VI { - struct { - unsigned int FBC_IND_LUT2 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT3__SI__VI { - struct { - unsigned int FBC_IND_LUT3 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT4__SI__VI { - struct { - unsigned int FBC_IND_LUT4 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT5__SI__VI { - struct { - unsigned int FBC_IND_LUT5 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT6__SI__VI { - struct { - unsigned int FBC_IND_LUT6 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT7__SI__VI { - struct { - unsigned int FBC_IND_LUT7 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT8__SI__VI { - struct { - unsigned int FBC_IND_LUT8 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_IND_LUT9__SI__VI { - struct { - unsigned int FBC_IND_LUT9 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_MISC__SI__VI { - struct { - unsigned int FBC_DECOMPRESS_ERROR : 2; - unsigned int FBC_STOP_ON_ERROR : 1; - unsigned int FBC_INVALIDATE_ON_ERROR : 1; - unsigned int FBC_ERROR_PIXEL : 4; - unsigned int FBC_DIVIDE_X : 2; - unsigned int FBC_DIVIDE_Y : 1; - unsigned int FBC_RSM_WRITE_VALUE : 1; - unsigned int FBC_RSM_UNCOMP_DATA_IMMEDIATELY : 1; - unsigned int : 3; - unsigned int FBC_DECOMPRESS_ERROR_CLEAR : 1; - unsigned int : 3; - unsigned int FBC_RESET_AT_ENABLE__VI : 1; - unsigned int FBC_RESET_AT_DISABLE__VI : 1; - unsigned int : 2; - unsigned int FBC_SLOW_REQ_INTERVAL__VI : 5; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_START_STOP_DELAY__SI__VI { - struct { - unsigned int FBC_DECOMP_START_DELAY : 5; - unsigned int : 2; - unsigned int FBC_DECOMP_STOP_DELAY : 1; - unsigned int FBC_COMP_START_DELAY : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int FBC_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int FBC_TEST_DEBUG_INDEX : 8; - unsigned int FBC_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FIRMWARE_FLAGS__CI__VI { - struct { - unsigned int INTERRUPTS_ENABLED : 1; - unsigned int : 23; - unsigned int TEST_COUNT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_BIT_DEPTH_CONTROL__SI { - struct { - unsigned int FMT_TRUNCATE_EN : 1; - unsigned int : 3; - unsigned int FMT_TRUNCATE_DEPTH : 1; - unsigned int : 3; - unsigned int FMT_SPATIAL_DITHER_EN : 1; - unsigned int FMT_SPATIAL_DITHER_MODE : 2; - unsigned int : 1; - unsigned int FMT_SPATIAL_DITHER_DEPTH : 1; - unsigned int FMT_FRAME_RANDOM_ENABLE : 1; - unsigned int FMT_RGB_RANDOM_ENABLE : 1; - unsigned int FMT_HIGHPASS_RANDOM_ENABLE : 1; - unsigned int FMT_TEMPORAL_DITHER_EN : 1; - unsigned int : 3; - unsigned int FMT_TEMPORAL_DITHER_DEPTH : 1; - unsigned int FMT_TEMPORAL_DITHER_OFFSET : 2; - unsigned int : 1; - unsigned int FMT_TEMPORAL_LEVEL : 1; - unsigned int FMT_TEMPORAL_DITHER_RESET : 1; - unsigned int FMT_25FRC_SEL : 2; - unsigned int FMT_50FRC_SEL : 2; - unsigned int FMT_75FRC_SEL : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_BIT_DEPTH_CONTROL__VI { - struct { - unsigned int FMT_TRUNCATE_EN : 1; - unsigned int FMT_TRUNCATE_MODE : 1; - unsigned int : 2; - unsigned int FMT_TRUNCATE_DEPTH : 2; - unsigned int : 2; - unsigned int FMT_SPATIAL_DITHER_EN : 1; - unsigned int FMT_SPATIAL_DITHER_MODE : 2; - unsigned int FMT_SPATIAL_DITHER_DEPTH : 2; - unsigned int FMT_FRAME_RANDOM_ENABLE : 1; - unsigned int FMT_RGB_RANDOM_ENABLE : 1; - unsigned int FMT_HIGHPASS_RANDOM_ENABLE : 1; - unsigned int FMT_TEMPORAL_DITHER_EN : 1; - unsigned int FMT_TEMPORAL_DITHER_DEPTH : 2; - unsigned int : 2; - unsigned int FMT_TEMPORAL_DITHER_OFFSET : 2; - unsigned int : 1; - unsigned int FMT_TEMPORAL_LEVEL : 1; - unsigned int FMT_TEMPORAL_DITHER_RESET : 1; - unsigned int FMT_25FRC_SEL : 2; - unsigned int FMT_50FRC_SEL : 2; - unsigned int FMT_75FRC_SEL : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_CLAMP_CNTL__SI__VI { - struct { - unsigned int FMT_CLAMP_DATA_EN : 1; - unsigned int : 15; - unsigned int FMT_CLAMP_COLOR_FORMAT : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_CONTROL__SI__VI { - struct { - unsigned int FMT_STEREOSYNC_OVERRIDE__VI : 1; - unsigned int : 3; - unsigned int FMT_STEREOSYNC_OVR_POL__VI : 1; - unsigned int : 3; - unsigned int FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__VI : 4; - unsigned int FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__VI : 2; - unsigned int : 2; - unsigned int FMT_PIXEL_ENCODING : 1; - unsigned int FMT_SUBSAMPLING_MODE__VI : 1; - unsigned int FMT_SUBSAMPLING_ORDER__VI : 1; - unsigned int : 5; - unsigned int FMT_SRC_SELECT__VI : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_CRC_CNTL__SI { - struct { - unsigned int FMT_CRC_EN : 1; - unsigned int : 3; - unsigned int FMT_CRC_CONT_EN : 1; - unsigned int : 3; - unsigned int FMT_CRC_ONLY_BLANKb : 1; - unsigned int : 3; - unsigned int FMT_CRC_INTERLACE_MODE : 2; - unsigned int : 2; - unsigned int FMT_CRC_USE_NEW_AND_REPEATED_PIXELS : 1; - unsigned int : 3; - unsigned int FMT_CRC_EVEN_ODD_PIX_ENABLE : 1; - unsigned int : 3; - unsigned int FMT_CRC_EVEN_ODD_PIX_SELECT : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_CRC_CNTL__VI { - struct { - unsigned int FMT_CRC_EN : 1; - unsigned int FMT_DTMTEST_CRC_EN : 1; - unsigned int : 2; - unsigned int FMT_CRC_CONT_EN : 1; - unsigned int : 3; - unsigned int FMT_CRC_ONLY_BLANKB : 1; - unsigned int : 3; - unsigned int FMT_CRC_INTERLACE_MODE : 2; - unsigned int : 2; - unsigned int FMT_CRC_USE_NEW_AND_REPEATED_PIXELS : 1; - unsigned int : 3; - unsigned int FMT_CRC_EVEN_ODD_PIX_ENABLE : 1; - unsigned int : 3; - unsigned int FMT_CRC_EVEN_ODD_PIX_SELECT : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_CRC_SIG_BLUE_CONTROL_MASK__SI__VI { - struct { - unsigned int FMT_CRC_SIG_BLUE_MASK : 16; - unsigned int FMT_CRC_SIG_CONTROL_MASK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_CRC_SIG_BLUE_CONTROL__SI__VI { - struct { - unsigned int FMT_CRC_SIG_BLUE : 16; - unsigned int FMT_CRC_SIG_CONTROL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_CRC_SIG_RED_GREEN_MASK__SI__VI { - struct { - unsigned int FMT_CRC_SIG_RED_MASK : 16; - unsigned int FMT_CRC_SIG_GREEN_MASK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_CRC_SIG_RED_GREEN__SI__VI { - struct { - unsigned int FMT_CRC_SIG_RED : 16; - unsigned int FMT_CRC_SIG_GREEN : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_DEBUG_CNTL__SI__VI { - struct { - unsigned int FMT_DEBUG_COLOR_SELECT : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_DITHER_RAND_B_SEED__SI__VI { - struct { - unsigned int FMT_RAND_B_SEED : 8; - unsigned int : 8; - unsigned int FMT_OFFSET_B_CB__VI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_DITHER_RAND_G_SEED__SI__VI { - struct { - unsigned int FMT_RAND_G_SEED : 8; - unsigned int : 8; - unsigned int FMT_OFFSET_G_Y__VI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_DITHER_RAND_R_SEED__SI__VI { - struct { - unsigned int FMT_RAND_R_SEED : 8; - unsigned int : 8; - unsigned int FMT_OFFSET_R_CR__VI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_DYNAMIC_EXP_CNTL__SI__VI { - struct { - unsigned int FMT_DYNAMIC_EXP_EN : 1; - unsigned int : 3; - unsigned int FMT_DYNAMIC_EXP_MODE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_FORCE_DATA_0_1__SI__VI { - struct { - unsigned int FMT_FORCE_DATA0 : 16; - unsigned int FMT_FORCE_DATA1 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_FORCE_DATA_2_3__SI__VI { - struct { - unsigned int FMT_FORCE_DATA2 : 16; - unsigned int FMT_FORCE_DATA3 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_FORCE_OUTPUT_CNTL__SI { - struct { - unsigned int FMT_FORCE_DATA_EN : 1; - unsigned int : 7; - unsigned int FMT_FORCE_DATA_SEL_COLOR : 3; - unsigned int : 1; - unsigned int FMT_FORCE_DATA_SEL_SLOT : 4; - unsigned int FMT_FORCE_DATA_ON_BLANKb_ONLY : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_FORCE_OUTPUT_CNTL__VI { - struct { - unsigned int FMT_FORCE_DATA_EN : 1; - unsigned int : 7; - unsigned int FMT_FORCE_DATA_SEL_COLOR : 3; - unsigned int : 1; - unsigned int FMT_FORCE_DATA_SEL_SLOT : 4; - unsigned int FMT_FORCE_DATA_ON_BLANKB_ONLY : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI__VI { - struct { - unsigned int FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT : 1; - unsigned int : 3; - unsigned int FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0 : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI__VI { - struct { - unsigned int FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI__VI { - struct { - unsigned int FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_END_0__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR_END : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_END_1__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR_END : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_END_2__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR_END : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_END_3__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR_END : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_END_4__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR_END : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_END_5__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR_END : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_END_6__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR_END : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_END_7__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR_END : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_START_0__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int MODE : 1; - unsigned int ADDR_START : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_START_1__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int MODE : 1; - unsigned int ADDR_START : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_START_2__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int MODE : 1; - unsigned int ADDR_START : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_START_3__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int MODE : 1; - unsigned int ADDR_START : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_START_4__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int MODE : 1; - unsigned int ADDR_START : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_START_5__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int MODE : 1; - unsigned int ADDR_START : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_START_6__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int MODE : 1; - unsigned int ADDR_START : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_ADDR_START_7__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int MODE : 1; - unsigned int ADDR_START : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_CNTL__CI { - struct { - unsigned int CP_RB0_WPTR : 1; - unsigned int CP_RB1_WPTR : 1; - unsigned int CP_RB2_WPTR : 1; - unsigned int UVD_RBC_RB_WPTR : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int CP_DMA_ME_COMMAND : 1; - unsigned int CP_DMA_PFP_COMMAND : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int VCE_OUT_RB_WPTR : 1; - unsigned int VCE_RB_WPTR2 : 1; - unsigned int VCE_RB_WPTR : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int DISPLAY : 1; - unsigned int : 14; - unsigned int DISABLE_ALL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_CNTL__VI { - struct { - unsigned int CP_RB0_WPTR : 1; - unsigned int CP_RB1_WPTR : 1; - unsigned int CP_RB2_WPTR : 1; - unsigned int UVD_RBC_RB_WPTR : 1; - unsigned int SDMA0_GFX_RB_WPTR : 1; - unsigned int SDMA1_GFX_RB_WPTR : 1; - unsigned int CP_DMA_ME_COMMAND : 1; - unsigned int CP_DMA_PFP_COMMAND : 1; - unsigned int SAM_SAB_RBI_WPTR : 1; - unsigned int SAM_SAB_RBO_WPTR : 1; - unsigned int VCE_OUT_RB_WPTR : 1; - unsigned int VCE_RB_WPTR2 : 1; - unsigned int VCE_RB_WPTR : 1; - unsigned int HOST_DOORBELL : 1; - unsigned int SELFRING_DOORBELL : 1; - unsigned int CP_DMA_PIO_COMMAND : 1; - unsigned int DISPLAY : 1; - unsigned int SDMA2_GFX_RB_WPTR : 1; - unsigned int SDMA3_GFX_RB_WPTR : 1; - unsigned int : 11; - unsigned int IGNORE_MC_DISABLE : 1; - unsigned int DISABLE_ALL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_FLUSH_REQ__CI__VI { - struct { - unsigned int FLUSH_REQ : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_ADDR_CONFIG { - struct { - unsigned int NUM_PIPES : 3; - unsigned int : 1; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int BANK_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_SHADER_ENGINES : 2; - unsigned int : 2; - unsigned int SHADER_ENGINE_TILE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_GPUS : 3; - unsigned int : 1; - unsigned int MULTI_GPU_TILE_SIZE : 2; - unsigned int : 2; - unsigned int ROW_SIZE : 2; - unsigned int NUM_LOWER_PIPES : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_BACKEND_MAP { - struct { - unsigned int BACKEND_MAP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_EDC_MODE { - struct { - unsigned int : 16; - unsigned int FORCE_SEC_ON_DED : 1; - unsigned int : 3; - unsigned int DED_MODE : 2; - unsigned int : 7; - unsigned int PROP_FED : 1; - unsigned int : 1; - unsigned int BYPASS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_GPU_ID { - struct { - unsigned int GPU_ID : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE0__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE10__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE11__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE12__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE13__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE14__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE15__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE1__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE2__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE3__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE4__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE5__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE6__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE7__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE8__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_MACROTILE_MODE9__CI__VI { - struct { - unsigned int BANK_WIDTH : 2; - unsigned int BANK_HEIGHT : 2; - unsigned int MACRO_TILE_ASPECT : 2; - unsigned int NUM_BANKS : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE0 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE1 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE10 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE11 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE12 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE13 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE14 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE15 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE16 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE17 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE18 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE19 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE2 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE20 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE21 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE22 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE23 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE24 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE25 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE26 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE27 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE28 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE29 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE3 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE30 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE31 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE4 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE5 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE6 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE7 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE8 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GB_TILE_MODE9 { - struct { - unsigned int MICRO_TILE_MODE__SI : 2; - unsigned int ARRAY_MODE : 4; - unsigned int PIPE_CONFIG : 5; - unsigned int TILE_SPLIT : 3; - unsigned int BANK_WIDTH__SI : 2; - unsigned int BANK_HEIGHT__SI : 2; - unsigned int MACRO_TILE_ASPECT__SI : 2; - unsigned int NUM_BANKS__SI : 2; - unsigned int MICRO_TILE_MODE_NEW__CI__VI : 3; - unsigned int SAMPLE_SPLIT__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GCK_PLL_TEST_CNTL__CI { - struct { - unsigned int TST_SRC_SEL : 4; - unsigned int TST_REF_SEL : 4; - unsigned int REF_TEST_COUNT : 7; - unsigned int TST_RESET : 1; - unsigned int TST_CLK_SEL_MODE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GCK_PLL_TEST_CNTL__VI { - struct { - unsigned int TST_SRC_SEL : 5; - unsigned int TST_REF_SEL : 5; - unsigned int REF_TEST_COUNT : 7; - unsigned int TST_RESET : 1; - unsigned int TST_CLK_SEL_MODE : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GCK_SMC_IND_DATA__CI__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GCK_SMC_IND_INDEX__CI__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_USER_PRIM_CONFIG__CI__VI { - struct { - unsigned int : 16; - unsigned int INACTIVE_IA : 2; - unsigned int : 6; - unsigned int INACTIVE_VGT_PA : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_USER_RB_BACKEND_DISABLE { - struct { - unsigned int : 16; - unsigned int BACKEND_DISABLE : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_USER_RB_REDUNDANCY__CI__VI { - struct { - unsigned int : 8; - unsigned int FAILED_RB0 : 4; - unsigned int EN_REDUNDANCY0 : 1; - unsigned int : 3; - unsigned int FAILED_RB1 : 4; - unsigned int EN_REDUNDANCY1 : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_USER_SHADER_ARRAY_CONFIG__SI__CI { - struct { - unsigned int : 1; - unsigned int DPFP_RATE__CI : 2; - unsigned int SQC_BALANCE_DISABLE__CI : 1; - unsigned int HALF_LDS__CI : 1; - unsigned int : 11; - unsigned int INACTIVE_CUS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_USER_SHADER_ARRAY_CONFIG__VI { - struct { - unsigned int : 16; - unsigned int INACTIVE_CUS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_USER_SYS_RB_BACKEND_DISABLE { - struct { - unsigned int : 16; - unsigned int BACKEND_DISABLE : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_BASE { - struct { - unsigned int BASE : 16; - unsigned int UNUSED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_CNTL { - struct { - unsigned int AINC : 6; - unsigned int : 2; - unsigned int DMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_COMPLETE { - struct { - unsigned int COMPLETE : 1; - unsigned int UNUSED : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_DST { - struct { - unsigned int DST : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_OFFSET0 { - struct { - unsigned int OFFSET0 : 8; - unsigned int UNUSED : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_OFFSET1 { - struct { - unsigned int OFFSET1 : 8; - unsigned int UNUSED : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_OP { - struct { - unsigned int OP : 8; - unsigned int UNUSED : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_READ0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_READ0_U { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_READ1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_READ1_U { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_SIZE { - struct { - unsigned int SIZE : 16; - unsigned int UNUSED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_SRC0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_SRC0_U { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_SRC1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ATOM_SRC1_U { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_CNTL_STATUS { - struct { - unsigned int GDS_BUSY : 1; - unsigned int GRBM_WBUF_BUSY : 1; - unsigned int ORD_APP_BUSY : 1; - unsigned int DS_BANK_CONFLICT : 1; - unsigned int DS_ADDR_CONFLICT : 1; - unsigned int DS_WR_CLAMP : 1; - unsigned int DS_RD_CLAMP : 1; - unsigned int GRBM_RBUF_BUSY__VI : 1; - unsigned int DS_BUSY__VI : 1; - unsigned int GWS_BUSY__VI : 1; - unsigned int ORD_FIFO_BUSY__VI : 1; - unsigned int CREDIT_BUSY0__VI : 1; - unsigned int CREDIT_BUSY1__VI : 1; - unsigned int CREDIT_BUSY2__VI : 1; - unsigned int CREDIT_BUSY3__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_COMPUTE_MAX_WAVE_ID__CI__VI { - struct { - unsigned int MAX_WAVE_ID : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_CONFIG { - struct { - unsigned int : 1; - unsigned int SH0_GPR_PHASE_SEL : 2; - unsigned int SH1_GPR_PHASE_SEL : 2; - unsigned int SH2_GPR_PHASE_SEL : 2; - unsigned int SH3_GPR_PHASE_SEL : 2; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_CNTL { - struct { - unsigned int GDS_DEBUG_INDX : 5; - unsigned int UNUSED : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG0__CI__VI { - struct { - unsigned int spare1 : 6; - unsigned int write_buff_valid : 1; - unsigned int wr_pixel_nxt_ptr : 5; - unsigned int last_pixel_ptr : 1; - unsigned int cstate : 4; - unsigned int buff_write : 1; - unsigned int flush_request : 1; - unsigned int wr_buffer_wr_complete : 1; - unsigned int wbuf_fifo_empty : 1; - unsigned int wbuf_fifo_full : 1; - unsigned int spare : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG0__SI { - struct { - unsigned int spare1 : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 8; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int spare : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG1__CI__VI { - struct { - unsigned int tag_hit : 1; - unsigned int tag_miss : 1; - unsigned int pixel_addr : 15; - unsigned int pixel_vld : 1; - unsigned int data_ready : 1; - unsigned int awaiting_data : 1; - unsigned int addr_fifo_full : 1; - unsigned int addr_fifo_empty : 1; - unsigned int buffer_loaded : 1; - unsigned int buffer_invalid : 1; - unsigned int spare : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG1__SI { - struct { - unsigned int : 6; - unsigned int : 1; - unsigned int : 5; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int spare : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG2__CI__VI { - struct { - unsigned int ds_full : 1; - unsigned int ds_credit_avail : 1; - unsigned int ord_idx_free : 1; - unsigned int cmd_write : 1; - unsigned int app_sel : 4; - unsigned int req : 15; - unsigned int spare : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG2__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 15; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int spare : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG3__CI__VI { - struct { - unsigned int pipe_num_busy : 11; - unsigned int pipe0_busy_num : 4; - unsigned int spare : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG3__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 9; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 8; - unsigned int spare : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG4__CI__VI { - struct { - unsigned int gws_busy : 1; - unsigned int gws_req : 1; - unsigned int gws_out_stall : 1; - unsigned int cur_reso : 6; - unsigned int cur_reso_head_valid : 1; - unsigned int cur_reso_head_dirty : 1; - unsigned int cur_reso_head_flag : 1; - unsigned int cur_reso_fed : 1; - unsigned int cur_reso_barrier : 1; - unsigned int cur_reso_flag : 1; - unsigned int cur_reso_cnt_gt0 : 1; - unsigned int credit_cnt_gt0 : 1; - unsigned int cmd_write : 1; - unsigned int grbm_gws_reso_wr : 1; - unsigned int grbm_gws_reso_rd : 1; - unsigned int ram_read_busy : 1; - unsigned int gws_bulkfree : 1; - unsigned int ram_gws_re : 1; - unsigned int ram_gws_we : 1; - unsigned int spare : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG4__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int : 3; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int spare : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG5__CI__VI { - struct { - unsigned int write_dis : 1; - unsigned int dec_error : 1; - unsigned int alloc_opco_error : 1; - unsigned int dealloc_opco_error : 1; - unsigned int wrap_opco_error : 1; - unsigned int spare : 3; - unsigned int error_ds_address : 14; - unsigned int spare1 : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG5__SI { - struct { - unsigned int : 3; - unsigned int : 8; - unsigned int : 8; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int spare : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG6__CI__VI { - struct { - unsigned int oa_busy : 1; - unsigned int counters_enabled : 4; - unsigned int counters_busy : 16; - unsigned int spare : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DEBUG_REG6__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 8; - unsigned int : 8; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int spare : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ENHANCE2__CI__VI { - struct { - unsigned int MISC : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ENHANCE__CI__VI { - struct { - unsigned int MISC : 16; - unsigned int AUTO_INC_INDEX : 1; - unsigned int CGPG_RESTORE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_ENHANCE__SI { - struct { - unsigned int MISC : 16; - unsigned int UNUSED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GRBM_SECDED_CNT__CI { - struct { - unsigned int DED : 16; - unsigned int SEC : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GRBM_SECDED_CNT__SI { - struct { - unsigned int SEC : 16; - unsigned int DED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_RESET0__CI__VI { - struct { - unsigned int RESOURCE0_RESET : 1; - unsigned int RESOURCE1_RESET : 1; - unsigned int RESOURCE2_RESET : 1; - unsigned int RESOURCE3_RESET : 1; - unsigned int RESOURCE4_RESET : 1; - unsigned int RESOURCE5_RESET : 1; - unsigned int RESOURCE6_RESET : 1; - unsigned int RESOURCE7_RESET : 1; - unsigned int RESOURCE8_RESET : 1; - unsigned int RESOURCE9_RESET : 1; - unsigned int RESOURCE10_RESET : 1; - unsigned int RESOURCE11_RESET : 1; - unsigned int RESOURCE12_RESET : 1; - unsigned int RESOURCE13_RESET : 1; - unsigned int RESOURCE14_RESET : 1; - unsigned int RESOURCE15_RESET : 1; - unsigned int RESOURCE16_RESET : 1; - unsigned int RESOURCE17_RESET : 1; - unsigned int RESOURCE18_RESET : 1; - unsigned int RESOURCE19_RESET : 1; - unsigned int RESOURCE20_RESET : 1; - unsigned int RESOURCE21_RESET : 1; - unsigned int RESOURCE22_RESET : 1; - unsigned int RESOURCE23_RESET : 1; - unsigned int RESOURCE24_RESET : 1; - unsigned int RESOURCE25_RESET : 1; - unsigned int RESOURCE26_RESET : 1; - unsigned int RESOURCE27_RESET : 1; - unsigned int RESOURCE28_RESET : 1; - unsigned int RESOURCE29_RESET : 1; - unsigned int RESOURCE30_RESET : 1; - unsigned int RESOURCE31_RESET : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_RESET1__CI__VI { - struct { - unsigned int RESOURCE32_RESET : 1; - unsigned int RESOURCE33_RESET : 1; - unsigned int RESOURCE34_RESET : 1; - unsigned int RESOURCE35_RESET : 1; - unsigned int RESOURCE36_RESET : 1; - unsigned int RESOURCE37_RESET : 1; - unsigned int RESOURCE38_RESET : 1; - unsigned int RESOURCE39_RESET : 1; - unsigned int RESOURCE40_RESET : 1; - unsigned int RESOURCE41_RESET : 1; - unsigned int RESOURCE42_RESET : 1; - unsigned int RESOURCE43_RESET : 1; - unsigned int RESOURCE44_RESET : 1; - unsigned int RESOURCE45_RESET : 1; - unsigned int RESOURCE46_RESET : 1; - unsigned int RESOURCE47_RESET : 1; - unsigned int RESOURCE48_RESET : 1; - unsigned int RESOURCE49_RESET : 1; - unsigned int RESOURCE50_RESET : 1; - unsigned int RESOURCE51_RESET : 1; - unsigned int RESOURCE52_RESET : 1; - unsigned int RESOURCE53_RESET : 1; - unsigned int RESOURCE54_RESET : 1; - unsigned int RESOURCE55_RESET : 1; - unsigned int RESOURCE56_RESET : 1; - unsigned int RESOURCE57_RESET : 1; - unsigned int RESOURCE58_RESET : 1; - unsigned int RESOURCE59_RESET : 1; - unsigned int RESOURCE60_RESET : 1; - unsigned int RESOURCE61_RESET : 1; - unsigned int RESOURCE62_RESET : 1; - unsigned int RESOURCE63_RESET : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_RESOURCE_CNTL { - struct { - unsigned int INDEX : 6; - unsigned int UNUSED : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_RESOURCE_CNT__CI__VI { - struct { - unsigned int RESOURCE_CNT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_RESOURCE_RESET__CI__VI { - struct { - unsigned int RESET : 1; - unsigned int : 7; - unsigned int RESOURCE_ID : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_RESOURCE__CI { - struct { - unsigned int FLAG : 1; - unsigned int COUNTER : 12; - unsigned int TYPE : 1; - unsigned int DED : 1; - unsigned int RELEASE_ALL : 1; - unsigned int HEAD_QUEUE : 11; - unsigned int HEAD_VALID : 1; - unsigned int HEAD_FLAG : 1; - unsigned int UNUSED1 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_RESOURCE__VI { - struct { - unsigned int FLAG : 1; - unsigned int COUNTER : 12; - unsigned int TYPE : 1; - unsigned int DED : 1; - unsigned int RELEASE_ALL : 1; - unsigned int HEAD_QUEUE : 12; - unsigned int HEAD_VALID : 1; - unsigned int HEAD_FLAG : 1; - unsigned int UNUSED1 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_RESOURCE__SI { - struct { - unsigned int FLAG : 1; - unsigned int COUNTER : 12; - unsigned int TYPE : 1; - unsigned int DED : 1; - unsigned int UNUSED : 1; - unsigned int HEAD_QUEUE : 11; - unsigned int HEAD_VALID : 1; - unsigned int HEAD_FLAG : 1; - unsigned int UNUSED1 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID0__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID10__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID11__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID12__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID13__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID14__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID15__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID1__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID2__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID3__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID4__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID5__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID6__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID7__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID8__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GWS_VMID9__CI__VI { - struct { - unsigned int BASE : 6; - unsigned int : 10; - unsigned int SIZE : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_ADDRESS__CI { - struct { - unsigned int DS_ADDRESS : 16; - unsigned int CRAWLER_TYPE : 4; - unsigned int CRAWLER : 4; - unsigned int UNUSED : 6; - unsigned int NO_ALLOC : 1; - unsigned int ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_ADDRESS__VI { - struct { - unsigned int DS_ADDRESS : 16; - unsigned int CRAWLER : 4; - unsigned int CRAWLER_TYPE : 2; - unsigned int UNUSED : 8; - unsigned int NO_ALLOC : 1; - unsigned int ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_CGPG_RESTORE__CI__VI { - struct { - unsigned int VMID : 8; - unsigned int MEID : 4; - unsigned int PIPEID : 4; - unsigned int QUEUEID__VI : 4; - unsigned int UNUSED__VI : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_CNTL__CI__VI { - struct { - unsigned int INDEX : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_COUNTER__CI__VI { - struct { - unsigned int SPACE_AVAILABLE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_DED__CI { - struct { - unsigned int ME0_GFXHP3D_PIX_DED : 1; - unsigned int ME0_GFXHP3D_VTX_DED : 1; - unsigned int ME0_CS_DED : 1; - unsigned int UNUSED0 : 1; - unsigned int ME1_PIPE0_DED : 1; - unsigned int ME1_PIPE1_DED : 1; - unsigned int ME1_PIPE2_DED : 1; - unsigned int ME1_PIPE3_DED : 1; - unsigned int ME2_PIPE0_DED : 1; - unsigned int ME2_PIPE1_DED : 1; - unsigned int ME2_PIPE2_DED : 1; - unsigned int ME2_PIPE3_DED : 1; - unsigned int UNUSED1 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_DED__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int UNUSED : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_INCDEC__CI__VI { - struct { - unsigned int VALUE : 31; - unsigned int INCDEC : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_RESET_MASK__CI__VI { - struct { - unsigned int ME0_GFXHP3D_PIX_RESET : 1; - unsigned int ME0_GFXHP3D_VTX_RESET : 1; - unsigned int ME0_CS_RESET : 1; - unsigned int : 1; - unsigned int ME1_PIPE0_RESET : 1; - unsigned int ME1_PIPE1_RESET : 1; - unsigned int ME1_PIPE2_RESET : 1; - unsigned int ME1_PIPE3_RESET : 1; - unsigned int ME2_PIPE0_RESET : 1; - unsigned int ME2_PIPE1_RESET : 1; - unsigned int ME2_PIPE2_RESET : 1; - unsigned int ME2_PIPE3_RESET : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_RESET__CI__VI { - struct { - unsigned int RESET : 1; - unsigned int : 7; - unsigned int PIPE_ID : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_RING_SIZE__CI__VI { - struct { - unsigned int RING_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID0__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID10__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID11__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID12__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID13__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID14__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID15__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID1__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID2__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID3__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID4__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID5__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID6__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID7__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID8__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_OA_VMID9__CI__VI { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER0_SELECT { - struct { - unsigned int PERFCOUNTER_SELECT : 10; - unsigned int PERFCOUNTER_SELECT1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERFCOUNTER_SELECT2 : 10; - unsigned int PERFCOUNTER_SELECT3 : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER1_SELECT { - struct { - unsigned int PERFCOUNTER_SELECT : 10; - unsigned int PERFCOUNTER_SELECT1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER2_SELECT { - struct { - unsigned int PERFCOUNTER_SELECT : 10; - unsigned int PERFCOUNTER_SELECT1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PERFCOUNTER3_SELECT { - struct { - unsigned int PERFCOUNTER_SELECT : 10; - unsigned int PERFCOUNTER_SELECT1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PROTECTION_FAULT__CI__VI { - struct { - unsigned int WRITE_DIS : 1; - unsigned int FAULT_DETECTED : 1; - unsigned int GRBM : 1; - unsigned int SH_ID : 3; - unsigned int CU_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int WAVE_ID : 4; - unsigned int ADDRESS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_RD_ADDR { - struct { - unsigned int READ_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_RD_BURST_ADDR { - struct { - unsigned int BURST_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_RD_BURST_COUNT { - struct { - unsigned int BURST_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_RD_BURST_DATA { - struct { - unsigned int BURST_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_RD_DATA { - struct { - unsigned int READ_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_SECDED_CNT__CI { - struct { - unsigned int DED : 16; - unsigned int SEC : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_SECDED_CNT__SI { - struct { - unsigned int SEC : 16; - unsigned int DED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID0_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID0_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID10_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID10_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID11_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID11_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID12_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID12_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID13_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID13_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID14_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID14_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID15_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID15_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID1_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID1_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID2_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID2_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID3_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID3_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID4_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID4_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID5_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID5_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID6_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID6_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID7_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID7_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID8_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID8_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID9_BASE__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VMID9_SIZE__CI__VI { - struct { - unsigned int SIZE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VM_PROTECTION_FAULT__CI__VI { - struct { - unsigned int WRITE_DIS : 1; - unsigned int FAULT_DETECTED : 1; - unsigned int GWS : 1; - unsigned int OA : 1; - unsigned int GRBM : 1; - unsigned int : 3; - unsigned int VMID : 4; - unsigned int : 4; - unsigned int ADDRESS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_WRITE_COMPLETE { - struct { - unsigned int WRITE_COMPLETE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_WR_ADDR { - struct { - unsigned int WRITE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_WR_BURST_ADDR { - struct { - unsigned int WRITE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_WR_BURST_DATA { - struct { - unsigned int WRITE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_WR_DATA { - struct { - unsigned int WRITE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENENB__SI__VI { - struct { - unsigned int BLK_IO_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENERAL_PWRMGT__CI__VI { - struct { - unsigned int GLOBAL_PWRMGT_EN : 1; - unsigned int STATIC_PM_EN : 1; - unsigned int THERMAL_PROTECTION_DIS : 1; - unsigned int THERMAL_PROTECTION_TYPE : 1; - unsigned int : 2; - unsigned int SW_SMIO_INDEX : 1; - unsigned int : 1; - unsigned int LOW_VOLT_D2_ACPI : 1; - unsigned int LOW_VOLT_D3_ACPI : 1; - unsigned int VOLT_PWRMGT_EN : 1; - unsigned int SPARE11 : 1; - unsigned int : 2; - unsigned int GPU_COUNTER_ACPI : 1; - unsigned int GPU_COUNTER_CLK : 1; - unsigned int GPU_COUNTER_OFF : 1; - unsigned int GPU_COUNTER_INTF_OFF : 1; - unsigned int SPARE18 : 1; - unsigned int ACPI_D3_VID : 2; - unsigned int : 2; - unsigned int DYN_SPREAD_SPECTRUM_EN : 1; - unsigned int : 3; - unsigned int SPARE27 : 1; - unsigned int SPARE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENERAL_PWRMGT__SI { - struct { - unsigned int GLOBAL_PWRMGT_EN : 1; - unsigned int STATIC_PM_EN : 1; - unsigned int THERMAL_PROTECTION_DIS : 1; - unsigned int THERMAL_PROTECTION_TYPE : 1; - unsigned int : 2; - unsigned int SW_SMIO_INDEX : 1; - unsigned int : 3; - unsigned int VOLT_PWRMGT_EN : 1; - unsigned int SPARE11 : 1; - unsigned int : 6; - unsigned int SPARE18 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int DYN_SPREAD_SPECTRUM_EN : 1; - unsigned int : 3; - unsigned int SPARE : 1; - unsigned int : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENERIC_I2C_CONTROL__SI__VI { - struct { - unsigned int GENERIC_I2C_GO : 1; - unsigned int GENERIC_I2C_SOFT_RESET : 1; - unsigned int GENERIC_I2C_SEND_RESET : 1; - unsigned int GENERIC_I2C_ENABLE__VI : 1; - unsigned int : 27; - unsigned int GENERIC_I2C_DBG_REF_SEL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENERIC_I2C_DATA__SI__VI { - struct { - unsigned int GENERIC_I2C_DATA_RW : 1; - unsigned int : 7; - unsigned int GENERIC_I2C_DATA : 8; - unsigned int GENERIC_I2C_INDEX : 4; - unsigned int : 11; - unsigned int GENERIC_I2C_INDEX_WRITE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENERIC_I2C_INTERRUPT_CONTROL__SI__VI { - struct { - unsigned int GENERIC_I2C_DONE_INT : 1; - unsigned int GENERIC_I2C_DONE_ACK : 1; - unsigned int GENERIC_I2C_DONE_MASK : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENERIC_I2C_PIN_DEBUG__SI__VI { - struct { - unsigned int GENERIC_I2C_SCL_OUTPUT : 1; - unsigned int GENERIC_I2C_SCL_INPUT : 1; - unsigned int GENERIC_I2C_SCL_EN : 1; - unsigned int : 1; - unsigned int GENERIC_I2C_SDA_OUTPUT : 1; - unsigned int GENERIC_I2C_SDA_INPUT : 1; - unsigned int GENERIC_I2C_SDA_EN : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENERIC_I2C_PIN_SELECTION__SI__VI { - struct { - unsigned int GENERIC_I2C_SCL_PIN_SEL : 7; - unsigned int : 1; - unsigned int GENERIC_I2C_SDA_PIN_SEL : 7; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENERIC_I2C_SETUP__SI__VI { - struct { - unsigned int GENERIC_I2C_DATA_DRIVE_EN : 1; - unsigned int GENERIC_I2C_DATA_DRIVE_SEL : 1; - unsigned int : 5; - unsigned int GENERIC_I2C_CLK_DRIVE_EN : 1; - unsigned int GENERIC_I2C_INTRA_BYTE_DELAY : 8; - unsigned int : 8; - unsigned int GENERIC_I2C_TIME_LIMIT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENERIC_I2C_SPEED__SI__VI { - struct { - unsigned int GENERIC_I2C_THRESHOLD : 2; - unsigned int : 2; - unsigned int GENERIC_I2C_DISABLE_FILTER_DURING_STALL : 1; - unsigned int : 11; - unsigned int GENERIC_I2C_PRESCALE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENERIC_I2C_STATUS__SI__VI { - struct { - unsigned int GENERIC_I2C_STATUS : 4; - unsigned int GENERIC_I2C_DONE : 1; - unsigned int GENERIC_I2C_ABORTED : 1; - unsigned int GENERIC_I2C_TIMEOUT : 1; - unsigned int : 2; - unsigned int GENERIC_I2C_STOPPED_ON_NACK : 1; - unsigned int GENERIC_I2C_NACK : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENERIC_I2C_TRANSACTION__SI__VI { - struct { - unsigned int GENERIC_I2C_RW : 1; - unsigned int : 7; - unsigned int GENERIC_I2C_STOP_ON_NACK : 1; - unsigned int GENERIC_I2C_ACK_ON_READ : 1; - unsigned int : 2; - unsigned int GENERIC_I2C_START : 1; - unsigned int GENERIC_I2C_STOP : 1; - unsigned int : 2; - unsigned int GENERIC_I2C_COUNT : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENFC_RD__SI__VI { - struct { - unsigned int : 3; - unsigned int VSYNC_SEL_R : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENFC_WT__SI__VI { - struct { - unsigned int : 3; - unsigned int VSYNC_SEL_W : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENMO_RD__SI__VI { - struct { - unsigned int GENMO_MONO_ADDRESS_B : 1; - unsigned int VGA_RAM_EN : 1; - unsigned int VGA_CKSEL : 2; - unsigned int : 1; - unsigned int ODD_EVEN_MD_PGSEL : 1; - unsigned int VGA_HSYNC_POL : 1; - unsigned int VGA_VSYNC_POL : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENMO_WT__SI__VI { - struct { - unsigned int GENMO_MONO_ADDRESS_B : 1; - unsigned int VGA_RAM_EN : 1; - unsigned int VGA_CKSEL : 2; - unsigned int : 1; - unsigned int ODD_EVEN_MD_PGSEL : 1; - unsigned int VGA_HSYNC_POL : 1; - unsigned int VGA_VSYNC_POL : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENS0__SI__VI { - struct { - unsigned int : 4; - unsigned int SENSE_SWITCH : 1; - unsigned int : 2; - unsigned int CRT_INTR : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GENS1__SI__VI { - struct { - unsigned int NO_DISPLAY : 1; - unsigned int : 2; - unsigned int VGA_VSTATUS : 1; - unsigned int PIXEL_READ_BACK : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GFX_COPY_STATE { - struct { - unsigned int SRC_STATE_ID : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GFX_PIPE_CONTROL__CI__VI { - struct { - unsigned int HYSTERESIS_CNT : 13; - unsigned int : 3; - unsigned int CONTEXT_SUSPEND_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GFX_PIPE_PRIORITY__CI__VI { - struct { - unsigned int HP_PIPE_SELECT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GLOBAL_CAPABILITIES__SI__VI { - struct { - unsigned int SIXTY_FOUR_BIT_ADDRESS_SUPPORTED : 1; - unsigned int NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS : 2; - unsigned int NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED : 5; - unsigned int NUMBER_OF_INPUT_STREAMS_SUPPORTED : 4; - unsigned int NUMBER_OF_OUTPUT_STREAMS_SUPPORTED : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GLOBAL_CONTROL__SI__VI { - struct { - unsigned int CONTROLLER_RESET : 1; - unsigned int FLUSH_CONTROL : 1; - unsigned int : 6; - unsigned int ACCEPT_UNSOLICITED_RESPONSE_ENABLE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GLOBAL_STATUS__SI__VI { - struct { - unsigned int : 1; - unsigned int FLUSH_STATUS : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_DEBUG__CI { - struct { - unsigned int GFX_STALL : 1; - unsigned int GFX_CLEAR : 1; - unsigned int MISC_FLAGS : 28; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_DEBUG__VI { - struct { - unsigned int GFX_STALL : 1; - unsigned int GFX_CLEAR : 1; - unsigned int GMCON_DEBUG_RESERVED0 : 1; - unsigned int SR_COMMIT_STATE : 1; - unsigned int STCTRL_ST : 4; - unsigned int MISC_FLAGS : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_MASK__CI__VI { - struct { - unsigned int STCTRL_BUSY_MASK_ACP_RD : 1; - unsigned int STCTRL_BUSY_MASK_ACP_WR : 1; - unsigned int STCTRL_BUSY_MASK_VCE_RD : 1; - unsigned int STCTRL_BUSY_MASK_VCE_WR : 1; - unsigned int STCTRL_SR_HANDSHAKE_MASK : 8; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_MISC2__CI { - struct { - unsigned int RENG_MEM_POWER_CTRL_OVERRIDE0 : 3; - unsigned int RENG_MEM_POWER_CTRL_OVERRIDE1 : 3; - unsigned int STCTRL_NONDISP_IDLE_THRESHOLD : 5; - unsigned int RENG_SR_HOLD_THRESHOLD : 6; - unsigned int STCTRL_LPT_TARGET : 12; - unsigned int STCTRL_IGNORE_ARB_BUSY : 1; - unsigned int STCTRL_EXTEND_GMC_OFFLINE : 1; - unsigned int STCTRL_TIMER_PULSE_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_MISC2__VI { - struct { - unsigned int GMCON_MISC2_RESERVED0 : 6; - unsigned int STCTRL_NONDISP_IDLE_THRESHOLD : 5; - unsigned int RENG_SR_HOLD_THRESHOLD : 6; - unsigned int GMCON_MISC2_RESERVED1 : 12; - unsigned int STCTRL_IGNORE_ARB_BUSY : 1; - unsigned int STCTRL_EXTEND_GMC_OFFLINE : 1; - unsigned int STCTRL_TIMER_PULSE_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_MISC3__CI { - struct { - unsigned int RENG_DISABLE_MCC : 6; - unsigned int RENG_DISABLE_MCD : 6; - unsigned int STCTRL_FORCE_PGFSM_CMD_DONE : 12; - unsigned int STCTRL_IGNORE_ALLOW_STUTTER : 1; - unsigned int RENG_MEM_LS_ENABLE : 1; - unsigned int STCTRL_EXCLUDE_NONMEM_CLIENTS : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_MISC3__VI { - struct { - unsigned int RENG_DISABLE_MCC : 8; - unsigned int RENG_DISABLE_MCD : 8; - unsigned int STCTRL_FORCE_PGFSM_CMD_DONE : 12; - unsigned int STCTRL_IGNORE_ALLOW_STUTTER : 1; - unsigned int RENG_MEM_LS_ENABLE : 1; - unsigned int STCTRL_EXCLUDE_NONMEM_CLIENTS : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_MISC__CI__VI { - struct { - unsigned int : 10; - unsigned int RENG_EXECUTE_NOW_MODE : 1; - unsigned int RENG_EXECUTE_ON_REG_UPDATE : 1; - unsigned int RENG_SRBM_CREDITS_MCD : 4; - unsigned int STCTRL_STUTTER_EN : 1; - unsigned int STCTRL_GMC_IDLE_THRESHOLD : 2; - unsigned int STCTRL_SRBM_IDLE_THRESHOLD : 2; - unsigned int STCTRL_IGNORE_PRE_SR : 1; - unsigned int STCTRL_IGNORE_ALLOW_STOP : 1; - unsigned int STCTRL_IGNORE_SR_COMMIT : 1; - unsigned int STCTRL_IGNORE_PROTECTION_FAULT : 1; - unsigned int STCTRL_DISABLE_ALLOW_SR : 1; - unsigned int STCTRL_DISABLE_GMC_OFFLINE : 1; - unsigned int CRITICAL_REGS_LOCK : 1; - unsigned int ALLOW_DEEP_SLEEP_MODE : 3; - unsigned int STCTRL_FORCE_ALLOW_SR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_PERF_MON_CNTL0__CI__VI { - struct { - unsigned int START_THRESH : 12; - unsigned int STOP_THRESH : 12; - unsigned int START_MODE : 2; - unsigned int STOP_MODE : 2; - unsigned int ALLOW_WRAP : 1; - unsigned int THRESH_CNTR_ID_EXT__VI : 1; - unsigned int START_TRIG_ID_EXT__VI : 1; - unsigned int STOP_TRIG_ID_EXT__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_PERF_MON_CNTL1__CI { - struct { - unsigned int THRESH_CNTR_ID : 6; - unsigned int START_TRIG_ID : 6; - unsigned int STOP_TRIG_ID : 6; - unsigned int MON0_ID : 6; - unsigned int MON1_ID : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_PERF_MON_CNTL1__VI { - struct { - unsigned int THRESH_CNTR_ID : 6; - unsigned int START_TRIG_ID : 6; - unsigned int STOP_TRIG_ID : 6; - unsigned int MON0_ID : 7; - unsigned int MON1_ID : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_PERF_MON_RSLT0__CI__VI { - struct { - unsigned int COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_PERF_MON_RSLT1__CI__VI { - struct { - unsigned int COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_PGFSM_CONFIG__CI__VI { - struct { - unsigned int FSM_ADDR : 8; - unsigned int POWER_DOWN : 1; - unsigned int POWER_UP : 1; - unsigned int P1_SELECT : 1; - unsigned int P2_SELECT : 1; - unsigned int WRITE : 1; - unsigned int READ : 1; - unsigned int RSRVD : 13; - unsigned int SRBM_OVERRIDE : 1; - unsigned int REG_ADDR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_PGFSM_READ__CI__VI { - struct { - unsigned int READ_VALUE : 24; - unsigned int PGFSM_SELECT : 4; - unsigned int SERDES_MASTER_BUSY : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_PGFSM_WRITE__CI__VI { - struct { - unsigned int WRITE_VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_RENG_EXECUTE__CI__VI { - struct { - unsigned int RENG_EXECUTE_ON_PWR_UP : 1; - unsigned int RENG_EXECUTE_NOW : 1; - unsigned int RENG_EXECUTE_NOW_START_PTR : 10; - unsigned int RENG_EXECUTE_DSP_END_PTR : 10; - unsigned int RENG_EXECUTE_END_PTR : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_RENG_RAM_DATA__CI__VI { - struct { - unsigned int RENG_RAM_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_RENG_RAM_INDEX__CI__VI { - struct { - unsigned int RENG_RAM_INDEX : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__CI__VI { - struct { - unsigned int STCTRL_REGISTER_SAVE_EXCL0 : 16; - unsigned int STCTRL_REGISTER_SAVE_EXCL1 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__CI__VI { - struct { - unsigned int STCTRL_REGISTER_SAVE_EXCL2 : 16; - unsigned int STCTRL_REGISTER_SAVE_EXCL3 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_STCTRL_REGISTER_SAVE_RANGE0__CI__VI { - struct { - unsigned int STCTRL_REGISTER_SAVE_BASE0 : 16; - unsigned int STCTRL_REGISTER_SAVE_LIMIT0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_STCTRL_REGISTER_SAVE_RANGE1__CI__VI { - struct { - unsigned int STCTRL_REGISTER_SAVE_BASE1 : 16; - unsigned int STCTRL_REGISTER_SAVE_LIMIT1 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_STCTRL_REGISTER_SAVE_RANGE2__CI__VI { - struct { - unsigned int STCTRL_REGISTER_SAVE_BASE2 : 16; - unsigned int STCTRL_REGISTER_SAVE_LIMIT2 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_A { - struct { - unsigned int GPIO_A : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_EN { - struct { - unsigned int GPIO_EN : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_EXTERN_TRIG_CNTL { - struct { - unsigned int EXTERN_TRIG_SEL : 5; - unsigned int EXTERN_TRIG_CLR : 1; - unsigned int EXTERN_TRIG_READ : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_INT_EN { - struct { - unsigned int GPIO_INT_EN : 29; - unsigned int : 2; - unsigned int SW_INITIATED_INT_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_INT_POLARITY { - struct { - unsigned int GPIO_INT_POLARITY : 29; - unsigned int : 2; - unsigned int SW_INITIATED_INT_POLARITY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_INT_STAT { - struct { - unsigned int GPIO_INT_STAT : 29; - unsigned int : 2; - unsigned int SW_INITIATED_INT_STAT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_INT_STAT_AK { - struct { - unsigned int GPIO_INT_STAT_AK_0 : 1; - unsigned int GPIO_INT_STAT_AK_1 : 1; - unsigned int GPIO_INT_STAT_AK_2 : 1; - unsigned int GPIO_INT_STAT_AK_3 : 1; - unsigned int GPIO_INT_STAT_AK_4 : 1; - unsigned int GPIO_INT_STAT_AK_5 : 1; - unsigned int GPIO_INT_STAT_AK_6 : 1; - unsigned int GPIO_INT_STAT_AK_7 : 1; - unsigned int GPIO_INT_STAT_AK_8 : 1; - unsigned int GPIO_INT_STAT_AK_9 : 1; - unsigned int GPIO_INT_STAT_AK_10 : 1; - unsigned int GPIO_INT_STAT_AK_11 : 1; - unsigned int GPIO_INT_STAT_AK_12 : 1; - unsigned int GPIO_INT_STAT_AK_13 : 1; - unsigned int GPIO_INT_STAT_AK_14 : 1; - unsigned int GPIO_INT_STAT_AK_15 : 1; - unsigned int GPIO_INT_STAT_AK_16 : 1; - unsigned int GPIO_INT_STAT_AK_17 : 1; - unsigned int GPIO_INT_STAT_AK_18 : 1; - unsigned int GPIO_INT_STAT_AK_19 : 1; - unsigned int GPIO_INT_STAT_AK_20 : 1; - unsigned int GPIO_INT_STAT_AK_21 : 1; - unsigned int GPIO_INT_STAT_AK_22 : 1; - unsigned int GPIO_INT_STAT_AK_23 : 1; - unsigned int GPIO_INT_STAT_AK_24 : 1; - unsigned int GPIO_INT_STAT_AK_25 : 1; - unsigned int GPIO_INT_STAT_AK_26 : 1; - unsigned int GPIO_INT_STAT_AK_27 : 1; - unsigned int GPIO_INT_STAT_AK_28 : 1; - unsigned int : 2; - unsigned int SW_INITIATED_INT_STAT_AK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_INT_STAT_EN { - struct { - unsigned int GPIO_INT_STAT_EN : 29; - unsigned int : 2; - unsigned int SW_INITIATED_INT_STAT_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_INT_TYPE { - struct { - unsigned int GPIO_INT_TYPE : 29; - unsigned int : 2; - unsigned int SW_INITIATED_INT_TYPE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_MASK { - struct { - unsigned int GPIO_MASK : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_PD_EN { - struct { - unsigned int GPIO_PD_EN : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_PINSTRAPS { - struct { - unsigned int GPIO_PINSTRAP_0 : 1; - unsigned int GPIO_PINSTRAP_1 : 1; - unsigned int GPIO_PINSTRAP_2 : 1; - unsigned int GPIO_PINSTRAP_3 : 1; - unsigned int GPIO_PINSTRAP_4 : 1; - unsigned int GPIO_PINSTRAP_5 : 1; - unsigned int GPIO_PINSTRAP_6 : 1; - unsigned int GPIO_PINSTRAP_7 : 1; - unsigned int GPIO_PINSTRAP_8 : 1; - unsigned int GPIO_PINSTRAP_9 : 1; - unsigned int GPIO_PINSTRAP_10 : 1; - unsigned int GPIO_PINSTRAP_11 : 1; - unsigned int GPIO_PINSTRAP_12 : 1; - unsigned int GPIO_PINSTRAP_13 : 1; - unsigned int GPIO_PINSTRAP_14 : 1; - unsigned int GPIO_PINSTRAP_15 : 1; - unsigned int GPIO_PINSTRAP_16 : 1; - unsigned int GPIO_PINSTRAP_17 : 1; - unsigned int GPIO_PINSTRAP_18 : 1; - unsigned int GPIO_PINSTRAP_19 : 1; - unsigned int GPIO_PINSTRAP_20 : 1; - unsigned int GPIO_PINSTRAP_21 : 1; - unsigned int GPIO_PINSTRAP_22 : 1; - unsigned int GPIO_PINSTRAP_23 : 1; - unsigned int GPIO_PINSTRAP_24 : 1; - unsigned int GPIO_PINSTRAP_25 : 1; - unsigned int GPIO_PINSTRAP_26 : 1; - unsigned int GPIO_PINSTRAP_27 : 1; - unsigned int GPIO_PINSTRAP_28 : 1; - unsigned int GPIO_PINSTRAP_29 : 1; - unsigned int GPIO_PINSTRAP_30 : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_PU_EN { - struct { - unsigned int GPIO_PU_EN : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_RCVR_SEL { - struct { - unsigned int GPIO_RCVR_SEL : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_STRENGTH { - struct { - unsigned int GPIO_STRENGTH_SN : 4; - unsigned int GPIO_STRENGTH_SP : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_SW_INT_STAT { - struct { - unsigned int SW_INT_STAT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPIOPAD_Y { - struct { - unsigned int GPIO_Y : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPU_GARLIC_FLUSH_DONE__CI__VI { - struct { - unsigned int CP0 : 1; - unsigned int CP1 : 1; - unsigned int CP2 : 1; - unsigned int CP3 : 1; - unsigned int CP4 : 1; - unsigned int CP5 : 1; - unsigned int CP6 : 1; - unsigned int CP7 : 1; - unsigned int CP8 : 1; - unsigned int CP9 : 1; - unsigned int SDMA0 : 1; - unsigned int SDMA1 : 1; - unsigned int SDMA2__VI : 1; - unsigned int SDMA3__VI : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPU_GARLIC_FLUSH_REQ__CI__VI { - struct { - unsigned int CP0 : 1; - unsigned int CP1 : 1; - unsigned int CP2 : 1; - unsigned int CP3 : 1; - unsigned int CP4 : 1; - unsigned int CP5 : 1; - unsigned int CP6 : 1; - unsigned int CP7 : 1; - unsigned int CP8 : 1; - unsigned int CP9 : 1; - unsigned int SDMA0 : 1; - unsigned int SDMA1 : 1; - unsigned int SDMA2__VI : 1; - unsigned int SDMA3__VI : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPU_HDP_FLUSH_DONE__CI__VI { - struct { - unsigned int CP0 : 1; - unsigned int CP1 : 1; - unsigned int CP2 : 1; - unsigned int CP3 : 1; - unsigned int CP4 : 1; - unsigned int CP5 : 1; - unsigned int CP6 : 1; - unsigned int CP7 : 1; - unsigned int CP8 : 1; - unsigned int CP9 : 1; - unsigned int SDMA0 : 1; - unsigned int SDMA1 : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPU_HDP_FLUSH_REQ__CI__VI { - struct { - unsigned int CP0 : 1; - unsigned int CP1 : 1; - unsigned int CP2 : 1; - unsigned int CP3 : 1; - unsigned int CP4 : 1; - unsigned int CP5 : 1; - unsigned int CP6 : 1; - unsigned int CP7 : 1; - unsigned int CP8 : 1; - unsigned int CP9 : 1; - unsigned int SDMA0 : 1; - unsigned int SDMA1 : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRA00__SI__VI { - struct { - unsigned int GRPH_SET_RESET0 : 1; - unsigned int GRPH_SET_RESET1 : 1; - unsigned int GRPH_SET_RESET2 : 1; - unsigned int GRPH_SET_RESET3 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRA01__SI__VI { - struct { - unsigned int GRPH_SET_RESET_ENA0 : 1; - unsigned int GRPH_SET_RESET_ENA1 : 1; - unsigned int GRPH_SET_RESET_ENA2 : 1; - unsigned int GRPH_SET_RESET_ENA3 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRA02__SI__VI { - struct { - unsigned int GRPH_CCOMP : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRA03__SI__VI { - struct { - unsigned int GRPH_ROTATE : 3; - unsigned int GRPH_FN_SEL : 2; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRA04__SI__VI { - struct { - unsigned int GRPH_RMAP : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRA05__SI__VI { - struct { - unsigned int GRPH_WRITE_MODE : 2; - unsigned int : 1; - unsigned int GRPH_READ1 : 1; - unsigned int CGA_ODDEVEN : 1; - unsigned int GRPH_OES : 1; - unsigned int GRPH_PACK : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRA06__SI__VI { - struct { - unsigned int GRPH_GRAPHICS : 1; - unsigned int GRPH_ODDEVEN : 1; - unsigned int GRPH_ADRSEL : 2; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRA07__SI__VI { - struct { - unsigned int GRPH_XCARE0 : 1; - unsigned int GRPH_XCARE1 : 1; - unsigned int GRPH_XCARE2 : 1; - unsigned int GRPH_XCARE3 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRA08__SI__VI { - struct { - unsigned int GRPH_BMSK : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_CAM_DATA { - struct { - unsigned int CAM_ADDR : 16; - unsigned int CAM_REMAPADDR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_CAM_INDEX { - struct { - unsigned int CAM_INDEX : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_CNTL { - struct { - unsigned int READ_TIMEOUT : 8; - unsigned int : 23; - unsigned int REPORT_LAST_RDERR__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_DEBUG { - struct { - unsigned int : 1; - unsigned int IGNORE_RDY : 1; - unsigned int : 3; - unsigned int IGNORE_FAO : 1; - unsigned int DISABLE_READ_TIMEOUT : 1; - unsigned int SNAPSHOT_FREE_CNTRS : 1; - unsigned int HYSTERESIS_GUI_ACTIVE : 4; - unsigned int GFX_CLOCK_DOMAIN_OVERRIDE : 1; - unsigned int GRBM_TRAP_ENABLE__VI : 1; - unsigned int : 17; - unsigned int DEBUG_BUS_FGCG_EN__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_DEBUG_CNTL { - struct { - unsigned int GRBM_DEBUG_INDEX : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_DEBUG_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_DEBUG_SNAPSHOT__CI__VI { - struct { - unsigned int CPF_RDY : 1; - unsigned int CPG_RDY : 1; - unsigned int SRBM_RDY : 1; - unsigned int WD_ME0PIPE0_RDY : 1; - unsigned int WD_ME0PIPE1_RDY : 1; - unsigned int GDS_RDY : 1; - unsigned int SE0SPI_ME0PIPE0_RDY0 : 1; - unsigned int SE0SPI_ME0PIPE1_RDY0 : 1; - unsigned int SE1SPI_ME0PIPE0_RDY0 : 1; - unsigned int SE1SPI_ME0PIPE1_RDY0 : 1; - unsigned int SE2SPI_ME0PIPE0_RDY0 : 1; - unsigned int SE2SPI_ME0PIPE1_RDY0 : 1; - unsigned int SE3SPI_ME0PIPE0_RDY0 : 1; - unsigned int SE3SPI_ME0PIPE1_RDY0 : 1; - unsigned int SE0SPI_ME0PIPE0_RDY1 : 1; - unsigned int SE0SPI_ME0PIPE1_RDY1 : 1; - unsigned int SE1SPI_ME0PIPE0_RDY1 : 1; - unsigned int SE1SPI_ME0PIPE1_RDY1 : 1; - unsigned int SE2SPI_ME0PIPE0_RDY1 : 1; - unsigned int SE2SPI_ME0PIPE1_RDY1 : 1; - unsigned int SE3SPI_ME0PIPE0_RDY1 : 1; - unsigned int SE3SPI_ME0PIPE1_RDY1 : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_DEBUG_SNAPSHOT__SI { - struct { - unsigned int : 1; - unsigned int SRBM_RDY : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int GDS_RDY : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_GFX_CLKEN_CNTL { - struct { - unsigned int PREFIX_DELAY_CNT : 4; - unsigned int : 4; - unsigned int POST_DELAY_CNT : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_GFX_INDEX { - struct { - unsigned int INSTANCE_INDEX : 8; - unsigned int SH_INDEX : 8; - unsigned int SE_INDEX : 8; - unsigned int : 5; - unsigned int SH_BROADCAST_WRITES : 1; - unsigned int INSTANCE_BROADCAST_WRITES : 1; - unsigned int SE_BROADCAST_WRITES : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_INT_CNTL { - struct { - unsigned int RDERR_INT_ENABLE : 1; - unsigned int : 18; - unsigned int GUI_IDLE_INT_ENABLE : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_NOWHERE { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_PERFCOUNTER0_SELECT { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 4; - unsigned int DB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int CB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int VGT_BUSY_USER_DEFINED_MASK : 1; - unsigned int TA_BUSY_USER_DEFINED_MASK : 1; - unsigned int SX_BUSY_USER_DEFINED_MASK : 1; - unsigned int : 1; - unsigned int SPI_BUSY_USER_DEFINED_MASK : 1; - unsigned int SC_BUSY_USER_DEFINED_MASK : 1; - unsigned int PA_BUSY_USER_DEFINED_MASK : 1; - unsigned int GRBM_BUSY_USER_DEFINED_MASK : 1; - unsigned int DB_BUSY_USER_DEFINED_MASK : 1; - unsigned int CB_BUSY_USER_DEFINED_MASK : 1; - unsigned int CP_BUSY_USER_DEFINED_MASK : 1; - unsigned int IA_BUSY_USER_DEFINED_MASK : 1; - unsigned int GDS_BUSY_USER_DEFINED_MASK : 1; - unsigned int BCI_BUSY_USER_DEFINED_MASK : 1; - unsigned int RLC_BUSY_USER_DEFINED_MASK : 1; - unsigned int TC_BUSY_USER_DEFINED_MASK : 1; - unsigned int WD_BUSY_USER_DEFINED_MASK__CI__VI : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_PERFCOUNTER1_SELECT { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 4; - unsigned int DB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int CB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int VGT_BUSY_USER_DEFINED_MASK : 1; - unsigned int TA_BUSY_USER_DEFINED_MASK : 1; - unsigned int SX_BUSY_USER_DEFINED_MASK : 1; - unsigned int : 1; - unsigned int SPI_BUSY_USER_DEFINED_MASK : 1; - unsigned int SC_BUSY_USER_DEFINED_MASK : 1; - unsigned int PA_BUSY_USER_DEFINED_MASK : 1; - unsigned int GRBM_BUSY_USER_DEFINED_MASK : 1; - unsigned int DB_BUSY_USER_DEFINED_MASK : 1; - unsigned int CB_BUSY_USER_DEFINED_MASK : 1; - unsigned int CP_BUSY_USER_DEFINED_MASK : 1; - unsigned int IA_BUSY_USER_DEFINED_MASK : 1; - unsigned int GDS_BUSY_USER_DEFINED_MASK : 1; - unsigned int BCI_BUSY_USER_DEFINED_MASK : 1; - unsigned int RLC_BUSY_USER_DEFINED_MASK : 1; - unsigned int TC_BUSY_USER_DEFINED_MASK : 1; - unsigned int WD_BUSY_USER_DEFINED_MASK__CI__VI : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_PWR_CNTL__SI__CI { - struct { - unsigned int REQ_TYPE : 4; - unsigned int RSP_TYPE : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_PWR_CNTL__VI { - struct { - unsigned int ALL_REQ_TYPE : 2; - unsigned int GFX_REQ_TYPE : 2; - unsigned int ALL_RSP_TYPE : 2; - unsigned int GFX_RSP_TYPE : 2; - unsigned int : 6; - unsigned int GFX_REQ_EN : 1; - unsigned int ALL_REQ_EN : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_READ_ERROR2__CI__VI { - struct { - unsigned int : 17; - unsigned int READ_REQUESTER_SRBM : 1; - unsigned int READ_REQUESTER_RLC : 1; - unsigned int READ_REQUESTER_GDS_DMA : 1; - unsigned int READ_REQUESTER_ME0PIPE0_CF : 1; - unsigned int READ_REQUESTER_ME0PIPE0_PF : 1; - unsigned int READ_REQUESTER_ME0PIPE1_CF : 1; - unsigned int READ_REQUESTER_ME0PIPE1_PF : 1; - unsigned int READ_REQUESTER_ME1PIPE0 : 1; - unsigned int READ_REQUESTER_ME1PIPE1 : 1; - unsigned int READ_REQUESTER_ME1PIPE2 : 1; - unsigned int READ_REQUESTER_ME1PIPE3 : 1; - unsigned int READ_REQUESTER_ME2PIPE0 : 1; - unsigned int READ_REQUESTER_ME2PIPE1 : 1; - unsigned int READ_REQUESTER_ME2PIPE2 : 1; - unsigned int READ_REQUESTER_ME2PIPE3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_READ_ERROR__CI__VI { - struct { - unsigned int : 2; - unsigned int READ_ADDRESS : 16; - unsigned int : 2; - unsigned int READ_PIPEID : 2; - unsigned int READ_MEID : 2; - unsigned int : 7; - unsigned int READ_ERROR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_READ_ERROR__SI { - struct { - unsigned int : 2; - unsigned int READ_ADDRESS : 16; - unsigned int : 2; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int READ_ERROR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SCRATCH_REG0 { - struct { - unsigned int SCRATCH_REG0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SCRATCH_REG1 { - struct { - unsigned int SCRATCH_REG1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SCRATCH_REG2 { - struct { - unsigned int SCRATCH_REG2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SCRATCH_REG3 { - struct { - unsigned int SCRATCH_REG3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SCRATCH_REG4 { - struct { - unsigned int SCRATCH_REG4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SCRATCH_REG5 { - struct { - unsigned int SCRATCH_REG5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SCRATCH_REG6 { - struct { - unsigned int SCRATCH_REG6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SCRATCH_REG7 { - struct { - unsigned int SCRATCH_REG7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE0_PERFCOUNTER_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE0_PERFCOUNTER_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE0_PERFCOUNTER_SELECT { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 4; - unsigned int DB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int CB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int TA_BUSY_USER_DEFINED_MASK : 1; - unsigned int SX_BUSY_USER_DEFINED_MASK : 1; - unsigned int : 1; - unsigned int SPI_BUSY_USER_DEFINED_MASK : 1; - unsigned int SC_BUSY_USER_DEFINED_MASK : 1; - unsigned int DB_BUSY_USER_DEFINED_MASK : 1; - unsigned int CB_BUSY_USER_DEFINED_MASK : 1; - unsigned int VGT_BUSY_USER_DEFINED_MASK : 1; - unsigned int PA_BUSY_USER_DEFINED_MASK : 1; - unsigned int BCI_BUSY_USER_DEFINED_MASK : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE1_PERFCOUNTER_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE1_PERFCOUNTER_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE1_PERFCOUNTER_SELECT { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 4; - unsigned int DB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int CB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int TA_BUSY_USER_DEFINED_MASK : 1; - unsigned int SX_BUSY_USER_DEFINED_MASK : 1; - unsigned int : 1; - unsigned int SPI_BUSY_USER_DEFINED_MASK : 1; - unsigned int SC_BUSY_USER_DEFINED_MASK : 1; - unsigned int DB_BUSY_USER_DEFINED_MASK : 1; - unsigned int CB_BUSY_USER_DEFINED_MASK : 1; - unsigned int VGT_BUSY_USER_DEFINED_MASK : 1; - unsigned int PA_BUSY_USER_DEFINED_MASK : 1; - unsigned int BCI_BUSY_USER_DEFINED_MASK : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE2_PERFCOUNTER_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE2_PERFCOUNTER_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE2_PERFCOUNTER_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 4; - unsigned int DB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int CB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int TA_BUSY_USER_DEFINED_MASK : 1; - unsigned int SX_BUSY_USER_DEFINED_MASK : 1; - unsigned int : 1; - unsigned int SPI_BUSY_USER_DEFINED_MASK : 1; - unsigned int SC_BUSY_USER_DEFINED_MASK : 1; - unsigned int DB_BUSY_USER_DEFINED_MASK : 1; - unsigned int CB_BUSY_USER_DEFINED_MASK : 1; - unsigned int VGT_BUSY_USER_DEFINED_MASK : 1; - unsigned int PA_BUSY_USER_DEFINED_MASK : 1; - unsigned int BCI_BUSY_USER_DEFINED_MASK : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE3_PERFCOUNTER_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE3_PERFCOUNTER_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SE3_PERFCOUNTER_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 4; - unsigned int DB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int CB_CLEAN_USER_DEFINED_MASK : 1; - unsigned int TA_BUSY_USER_DEFINED_MASK : 1; - unsigned int SX_BUSY_USER_DEFINED_MASK : 1; - unsigned int : 1; - unsigned int SPI_BUSY_USER_DEFINED_MASK : 1; - unsigned int SC_BUSY_USER_DEFINED_MASK : 1; - unsigned int DB_BUSY_USER_DEFINED_MASK : 1; - unsigned int CB_BUSY_USER_DEFINED_MASK : 1; - unsigned int VGT_BUSY_USER_DEFINED_MASK : 1; - unsigned int PA_BUSY_USER_DEFINED_MASK : 1; - unsigned int BCI_BUSY_USER_DEFINED_MASK : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SKEW_CNTL { - struct { - unsigned int SKEW_TOP_THRESHOLD : 6; - unsigned int SKEW_COUNT : 6; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_SOFT_RESET { - struct { - unsigned int SOFT_RESET_CP : 1; - unsigned int : 1; - unsigned int SOFT_RESET_RLC : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SOFT_RESET_GFX__CI__VI : 1; - unsigned int SOFT_RESET_CPF__CI__VI : 1; - unsigned int SOFT_RESET_CPC__CI__VI : 1; - unsigned int SOFT_RESET_CPG__CI__VI : 1; - unsigned int SOFT_RESET_CAC__VI : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_STATUS2__CI__VI { - struct { - unsigned int ME0PIPE1_CMDFIFO_AVAIL : 4; - unsigned int ME0PIPE1_CF_RQ_PENDING : 1; - unsigned int ME0PIPE1_PF_RQ_PENDING : 1; - unsigned int ME1PIPE0_RQ_PENDING : 1; - unsigned int ME1PIPE1_RQ_PENDING : 1; - unsigned int ME1PIPE2_RQ_PENDING : 1; - unsigned int ME1PIPE3_RQ_PENDING : 1; - unsigned int ME2PIPE0_RQ_PENDING : 1; - unsigned int ME2PIPE1_RQ_PENDING : 1; - unsigned int ME2PIPE2_RQ_PENDING : 1; - unsigned int ME2PIPE3_RQ_PENDING : 1; - unsigned int RLC_RQ_PENDING : 1; - unsigned int : 9; - unsigned int RLC_BUSY : 1; - unsigned int TC_BUSY : 1; - unsigned int TCC_CC_RESIDENT__VI : 1; - unsigned int : 1; - unsigned int CPF_BUSY : 1; - unsigned int CPC_BUSY : 1; - unsigned int CPG_BUSY : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_STATUS2__SI { - struct { - unsigned int RLC_RQ_PENDING : 1; - unsigned int : 7; - unsigned int RLC_BUSY : 1; - unsigned int TC_BUSY : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_STATUS_SE0 { - struct { - unsigned int : 1; - unsigned int DB_CLEAN : 1; - unsigned int CB_CLEAN : 1; - unsigned int : 19; - unsigned int BCI_BUSY : 1; - unsigned int VGT_BUSY : 1; - unsigned int PA_BUSY : 1; - unsigned int TA_BUSY : 1; - unsigned int SX_BUSY : 1; - unsigned int SPI_BUSY : 1; - unsigned int : 1; - unsigned int SC_BUSY : 1; - unsigned int DB_BUSY : 1; - unsigned int CB_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_STATUS_SE1 { - struct { - unsigned int : 1; - unsigned int DB_CLEAN : 1; - unsigned int CB_CLEAN : 1; - unsigned int : 19; - unsigned int BCI_BUSY : 1; - unsigned int VGT_BUSY : 1; - unsigned int PA_BUSY : 1; - unsigned int TA_BUSY : 1; - unsigned int SX_BUSY : 1; - unsigned int SPI_BUSY : 1; - unsigned int : 1; - unsigned int SC_BUSY : 1; - unsigned int DB_BUSY : 1; - unsigned int CB_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_STATUS_SE2__CI__VI { - struct { - unsigned int : 1; - unsigned int DB_CLEAN : 1; - unsigned int CB_CLEAN : 1; - unsigned int : 19; - unsigned int BCI_BUSY : 1; - unsigned int VGT_BUSY : 1; - unsigned int PA_BUSY : 1; - unsigned int TA_BUSY : 1; - unsigned int SX_BUSY : 1; - unsigned int SPI_BUSY : 1; - unsigned int : 1; - unsigned int SC_BUSY : 1; - unsigned int DB_BUSY : 1; - unsigned int CB_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_STATUS_SE3__CI__VI { - struct { - unsigned int : 1; - unsigned int DB_CLEAN : 1; - unsigned int CB_CLEAN : 1; - unsigned int : 19; - unsigned int BCI_BUSY : 1; - unsigned int VGT_BUSY : 1; - unsigned int PA_BUSY : 1; - unsigned int TA_BUSY : 1; - unsigned int SX_BUSY : 1; - unsigned int SPI_BUSY : 1; - unsigned int : 1; - unsigned int SC_BUSY : 1; - unsigned int DB_BUSY : 1; - unsigned int CB_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_STATUS__CI__VI { - struct { - unsigned int ME0PIPE0_CMDFIFO_AVAIL : 4; - unsigned int : 1; - unsigned int SRBM_RQ_PENDING : 1; - unsigned int : 1; - unsigned int ME0PIPE0_CF_RQ_PENDING : 1; - unsigned int ME0PIPE0_PF_RQ_PENDING : 1; - unsigned int GDS_DMA_RQ_PENDING : 1; - unsigned int : 2; - unsigned int DB_CLEAN : 1; - unsigned int CB_CLEAN : 1; - unsigned int TA_BUSY : 1; - unsigned int GDS_BUSY : 1; - unsigned int WD_BUSY_NO_DMA : 1; - unsigned int VGT_BUSY : 1; - unsigned int IA_BUSY_NO_DMA : 1; - unsigned int IA_BUSY : 1; - unsigned int SX_BUSY : 1; - unsigned int WD_BUSY : 1; - unsigned int SPI_BUSY : 1; - unsigned int BCI_BUSY : 1; - unsigned int SC_BUSY : 1; - unsigned int PA_BUSY : 1; - unsigned int DB_BUSY : 1; - unsigned int : 1; - unsigned int CP_COHERENCY_BUSY : 1; - unsigned int CP_BUSY : 1; - unsigned int CB_BUSY : 1; - unsigned int GUI_ACTIVE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_STATUS__SI { - struct { - unsigned int : 4; - unsigned int : 1; - unsigned int SRBM_RQ_PENDING : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int GDS_DMA_RQ_PENDING : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DB_CLEAN : 1; - unsigned int CB_CLEAN : 1; - unsigned int TA_BUSY : 1; - unsigned int GDS_BUSY : 1; - unsigned int : 1; - unsigned int VGT_BUSY : 1; - unsigned int IA_BUSY_NO_DMA : 1; - unsigned int IA_BUSY : 1; - unsigned int SX_BUSY : 1; - unsigned int : 1; - unsigned int SPI_BUSY : 1; - unsigned int BCI_BUSY : 1; - unsigned int SC_BUSY : 1; - unsigned int PA_BUSY : 1; - unsigned int DB_BUSY : 1; - unsigned int : 1; - unsigned int CP_COHERENCY_BUSY : 1; - unsigned int CP_BUSY : 1; - unsigned int CB_BUSY : 1; - unsigned int GUI_ACTIVE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_WAIT_IDLE_CLOCKS { - struct { - unsigned int WAIT_IDLE_CLOCKS : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH8_DATA__SI__VI { - struct { - unsigned int GRPH_DATA : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH8_IDX__SI__VI { - struct { - unsigned int GRPH_IDX : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_ALPHA__SI { - struct { - unsigned int : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_COMPRESS_PITCH__SI__VI { - struct { - unsigned int : 6; - unsigned int GRPH_COMPRESS_PITCH : 11; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI__VI { - struct { - unsigned int GRPH_COMPRESS_SURFACE_ADDRESS_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_COMPRESS_SURFACE_ADDRESS__SI__VI { - struct { - unsigned int : 8; - unsigned int GRPH_COMPRESS_SURFACE_ADDRESS : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_CONTROL { - struct { - unsigned int GRPH_DEPTH : 2; - unsigned int GRPH_NUM_BANKS : 2; - unsigned int GRPH_Z : 2; - unsigned int GRPH_BANK_WIDTH : 2; - unsigned int GRPH_FORMAT : 3; - unsigned int GRPH_BANK_HEIGHT : 2; - unsigned int GRPH_TILE_SPLIT : 3; - unsigned int GRPH_ADDRESS_TRANSLATION_ENABLE : 1; - unsigned int GRPH_PRIVILEGED_ACCESS_ENABLE : 1; - unsigned int GRPH_MACRO_TILE_ASPECT : 2; - unsigned int GRPH_ARRAY_MODE : 4; - unsigned int GRPH_PIPE_CONFIG : 5; - unsigned int GRPH_MICRO_TILE_MODE__CI__VI : 2; - unsigned int GRPH_COLOR_EXPANSION_MODE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_DFQ_CONTROL__SI__VI { - struct { - unsigned int GRPH_DFQ_RESET : 1; - unsigned int : 3; - unsigned int GRPH_DFQ_SIZE : 3; - unsigned int : 1; - unsigned int GRPH_DFQ_MIN_FREE_ENTRIES : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_DFQ_STATUS__SI__VI { - struct { - unsigned int GRPH_PRIMARY_DFQ_NUM_ENTRIES : 4; - unsigned int GRPH_SECONDARY_DFQ_NUM_ENTRIES : 4; - unsigned int GRPH_DFQ_RESET_FLAG : 1; - unsigned int GRPH_DFQ_RESET_ACK : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_ENABLE__SI__VI { - struct { - unsigned int GRPH_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_FLIP_CONTROL { - struct { - unsigned int GRPH_SURFACE_UPDATE_H_RETRACE_EN : 1; - unsigned int GRPH_XDMA_SUPER_AA_EN__VI : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_INTERRUPT_CONTROL__SI__VI { - struct { - unsigned int GRPH_PFLIP_INT_MASK : 1; - unsigned int : 7; - unsigned int GRPH_PFLIP_INT_TYPE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_INTERRUPT_STATUS__SI__VI { - struct { - unsigned int GRPH_PFLIP_INT_OCCURRED : 1; - unsigned int : 7; - unsigned int GRPH_PFLIP_INT_CLEAR : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_LUT_10BIT_BYPASS__SI__VI { - struct { - unsigned int : 8; - unsigned int GRPH_LUT_10BIT_BYPASS_EN : 1; - unsigned int : 7; - unsigned int GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_PITCH { - struct { - unsigned int GRPH_PITCH : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_PRIMARY_SURFACE_ADDRESS { - struct { - unsigned int GRPH_PRIMARY_DFQ_ENABLE : 1; - unsigned int : 7; - unsigned int GRPH_PRIMARY_SURFACE_ADDRESS : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_PRIMARY_SURFACE_ADDRESS_HIGH { - struct { - unsigned int GRPH_PRIMARY_SURFACE_ADDRESS_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI__VI { - struct { - unsigned int GRPH_SECONDARY_SURFACE_ADDRESS_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_SECONDARY_SURFACE_ADDRESS__SI__VI { - struct { - unsigned int GRPH_SECONDARY_DFQ_ENABLE : 1; - unsigned int : 7; - unsigned int GRPH_SECONDARY_SURFACE_ADDRESS : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI__VI { - struct { - unsigned int GRPH_SURFACE_ADDRESS_HIGH_INUSE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_SURFACE_ADDRESS_INUSE__SI__VI { - struct { - unsigned int : 8; - unsigned int GRPH_SURFACE_ADDRESS_INUSE : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_SURFACE_OFFSET_X__SI__VI { - struct { - unsigned int GRPH_SURFACE_OFFSET_X : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_SURFACE_OFFSET_Y__SI__VI { - struct { - unsigned int GRPH_SURFACE_OFFSET_Y : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_SWAP_CNTL__SI__VI { - struct { - unsigned int GRPH_ENDIAN_SWAP : 2; - unsigned int : 2; - unsigned int GRPH_RED_CROSSBAR : 2; - unsigned int GRPH_GREEN_CROSSBAR : 2; - unsigned int GRPH_BLUE_CROSSBAR : 2; - unsigned int GRPH_ALPHA_CROSSBAR : 2; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_UPDATE { - struct { - unsigned int GRPH_MODE_UPDATE_PENDING : 1; - unsigned int GRPH_MODE_UPDATE_TAKEN : 1; - unsigned int GRPH_SURFACE_UPDATE_PENDING : 1; - unsigned int GRPH_SURFACE_UPDATE_TAKEN : 1; - unsigned int : 4; - unsigned int GRPH_SURFACE_XDMA_PENDING_ENABLE__VI : 1; - unsigned int : 7; - unsigned int GRPH_UPDATE_LOCK : 1; - unsigned int : 3; - unsigned int GRPH_SURFACE_IGNORE_UPDATE_LOCK__VI : 1; - unsigned int : 3; - unsigned int GRPH_MODE_DISABLE_MULTIPLE_UPDATE : 1; - unsigned int : 3; - unsigned int GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_X_END__SI__VI { - struct { - unsigned int GRPH_X_END : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_X_START__SI__VI { - struct { - unsigned int GRPH_X_START : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_Y_END__SI__VI { - struct { - unsigned int GRPH_Y_END : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_Y_START__SI__VI { - struct { - unsigned int GRPH_Y_START : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_ACR_32_0__SI__VI { - struct { - unsigned int : 12; - unsigned int HDMI_ACR_CTS_32 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_ACR_32_1__SI__VI { - struct { - unsigned int HDMI_ACR_N_32 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_ACR_44_0__SI__VI { - struct { - unsigned int : 12; - unsigned int HDMI_ACR_CTS_44 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_ACR_44_1__SI__VI { - struct { - unsigned int HDMI_ACR_N_44 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_ACR_48_0__SI__VI { - struct { - unsigned int : 12; - unsigned int HDMI_ACR_CTS_48 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_ACR_48_1__SI__VI { - struct { - unsigned int HDMI_ACR_N_48 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_ACR_PACKET_CONTROL__SI__VI { - struct { - unsigned int HDMI_ACR_SEND : 1; - unsigned int HDMI_ACR_CONT : 1; - unsigned int : 2; - unsigned int HDMI_ACR_SELECT : 2; - unsigned int : 2; - unsigned int HDMI_ACR_SOURCE : 1; - unsigned int : 3; - unsigned int HDMI_ACR_AUTO_SEND : 1; - unsigned int : 3; - unsigned int HDMI_ACR_N_MULTIPLE : 3; - unsigned int : 12; - unsigned int HDMI_ACR_AUDIO_PRIORITY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_ACR_STATUS_0__SI__VI { - struct { - unsigned int : 12; - unsigned int HDMI_ACR_CTS : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_ACR_STATUS_1__SI__VI { - struct { - unsigned int HDMI_ACR_N : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_AUDIO_PACKET_CONTROL__SI__VI { - struct { - unsigned int : 4; - unsigned int HDMI_AUDIO_DELAY_EN : 2; - unsigned int : 2; - unsigned int HDMI_AUDIO_SEND_MAX_PACKETS : 1; - unsigned int : 7; - unsigned int HDMI_AUDIO_PACKETS_PER_LINE : 5; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_CONTROL__SI__VI { - struct { - unsigned int HDMI_KEEPOUT_MODE : 1; - unsigned int : 3; - unsigned int HDMI_PACKET_GEN_VERSION : 1; - unsigned int : 3; - unsigned int HDMI_ERROR_ACK : 1; - unsigned int HDMI_ERROR_MASK : 1; - unsigned int : 14; - unsigned int HDMI_DEEP_COLOR_ENABLE : 1; - unsigned int : 3; - unsigned int HDMI_DEEP_COLOR_DEPTH : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_GC__SI__VI { - struct { - unsigned int HDMI_GC_AVMUTE : 1; - unsigned int : 1; - unsigned int HDMI_GC_AVMUTE_CONT : 1; - unsigned int : 1; - unsigned int HDMI_DEFAULT_PHASE : 1; - unsigned int : 3; - unsigned int HDMI_PACKING_PHASE : 4; - unsigned int HDMI_PACKING_PHASE_OVERRIDE : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_GENERIC_PACKET_CONTROL__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 10; - unsigned int : 6; - unsigned int : 2; - unsigned int : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_INFOFRAME_CONTROL0__SI__VI { - struct { - unsigned int HDMI_AVI_INFO_SEND : 1; - unsigned int HDMI_AVI_INFO_CONT : 1; - unsigned int : 2; - unsigned int HDMI_AUDIO_INFO_SEND : 1; - unsigned int HDMI_AUDIO_INFO_CONT : 1; - unsigned int : 2; - unsigned int HDMI_MPEG_INFO_SEND : 1; - unsigned int HDMI_MPEG_INFO_CONT : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_INFOFRAME_CONTROL1__SI__VI { - struct { - unsigned int HDMI_AVI_INFO_LINE : 6; - unsigned int : 2; - unsigned int HDMI_AUDIO_INFO_LINE : 6; - unsigned int : 2; - unsigned int HDMI_MPEG_INFO_LINE : 6; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_STATUS__SI__VI { - struct { - unsigned int HDMI_ACTIVE_AVMUTE : 1; - unsigned int : 15; - unsigned int HDMI_AUDIO_PACKET_ERROR : 1; - unsigned int : 3; - unsigned int HDMI_VBI_PACKET_ERROR : 1; - unsigned int : 6; - unsigned int HDMI_ERROR_INT : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_VBI_PACKET_CONTROL__SI__VI { - struct { - unsigned int HDMI_NULL_SEND : 1; - unsigned int : 3; - unsigned int HDMI_GC_SEND : 1; - unsigned int HDMI_GC_CONT : 1; - unsigned int : 2; - unsigned int HDMI_ISRC_SEND : 1; - unsigned int HDMI_ISRC_CONT : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 3; - unsigned int HDMI_ISRC_LINE : 6; - unsigned int : 2; - unsigned int : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_DEBUG0 { - struct { - unsigned int HDP_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_DEBUG1 { - struct { - unsigned int HDP_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_HOST_PATH_CNTL { - struct { - unsigned int BIF_RDRET_CREDIT : 3; - unsigned int MC_WRREQ_CREDIT : 6; - unsigned int WR_STALL_TIMER : 2; - unsigned int RD_STALL_TIMER : 2; - unsigned int : 6; - unsigned int WRITE_COMBINE_TIMER : 2; - unsigned int WRITE_COMBINE_EN : 1; - unsigned int CACHE_INVALIDATE : 1; - unsigned int CLOCK_GATING_DIS : 1; - unsigned int REG_CLK_ENABLE_COUNT : 4; - unsigned int : 1; - unsigned int ALL_SURFACES_DIS : 1; - unsigned int WRITE_THROUGH_CACHE_DIS : 1; - unsigned int LIN_RD_CACHE_DIS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_LAST_SURFACE_HIT { - struct { - unsigned int LAST_SURFACE_HIT : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_MEM_COHERENCY_FLUSH_CNTL { - struct { - unsigned int HDP_MEM_FLUSH_ADDR : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_NONSURFACE_BASE { - struct { - unsigned int NONSURF_BASE : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_NONSURFACE_INFO { - struct { - unsigned int NONSURF_ADDR_TYPE : 1; - unsigned int NONSURF_ARRAY_MODE : 4; - unsigned int NONSURF_ENDIAN : 2; - unsigned int NONSURF_PIXEL_SIZE : 3; - unsigned int NONSURF_SAMPLE_NUM : 3; - unsigned int NONSURF_SAMPLE_SIZE : 2; - unsigned int NONSURF_PRIV : 1; - unsigned int NONSURF_TILE_COMPACT : 1; - unsigned int NONSURF_TILE_SPLIT__VI : 3; - unsigned int NONSURF_NUM_BANKS__VI : 2; - unsigned int NONSURF_BANK_WIDTH__VI : 2; - unsigned int NONSURF_BANK_HEIGHT__VI : 2; - unsigned int NONSURF_MACRO_TILE_ASPECT__VI : 2; - unsigned int NONSURF_MICRO_TILE_MODE__VI : 3; - unsigned int NONSURF_SLICE_TILE_MAX_MSB__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_NONSURFACE_SIZE { - struct { - unsigned int NONSURF_PITCH_TILE_MAX : 10; - unsigned int NONSURF_SLICE_TILE_MAX : 20; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_NONSURF_FLAGS { - struct { - unsigned int NONSURF_WRITE_FLAG : 1; - unsigned int NONSURF_READ_FLAG : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_NONSURF_FLAGS_CLR { - struct { - unsigned int NONSURF_WRITE_FLAG_CLR : 1; - unsigned int NONSURF_READ_FLAG_CLR : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_OUTSTANDING_REQ { - struct { - unsigned int WRITE_REQ : 8; - unsigned int READ_REQ : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_REG_COHERENCY_FLUSH_CNTL { - struct { - unsigned int HDP_REG_FLUSH_ADDR : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_SC_MULTI_CHIP_CNTL { - struct { - unsigned int LOG2_NUM_CHIPS : 3; - unsigned int MULTI_CHIP_TILE_SIZE : 2; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_SW_SEMAPHORE { - struct { - unsigned int SW_SEMAPHORE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_TILING_CONFIG { - struct { - unsigned int : 1; - unsigned int PIPE_TILING : 3; - unsigned int BANK_TILING : 2; - unsigned int GROUP_SIZE : 2; - unsigned int ROW_TILING : 3; - unsigned int BANK_SWAPS : 3; - unsigned int SAMPLE_SPLIT : 2; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_BUSY_STS { - struct { - unsigned int BUSY_BITS : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_CGTT_BLK_CTRL { - struct { - unsigned int CGTT_BLK_CTRL_0_ON_DELAY : 4; - unsigned int CGTT_BLK_CTRL_1_OFF_DELAY : 8; - unsigned int CGTT_BLK_CTRL_2_RSVD : 18; - unsigned int CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE : 1; - unsigned int CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_CHKN { - struct { - unsigned int CHKN_0_RSVD : 8; - unsigned int CHKN_1_RSVD : 8; - unsigned int CHKN_2_RSVD : 8; - unsigned int CHKN_3_RSVD : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_BAR_UPDATE { - struct { - unsigned int D2H_BAR_UPDATE_ADDR : 16; - unsigned int D2H_BAR_UPDATE_FLUSH_NUM : 4; - unsigned int D2H_BAR_UPDATE_BAR_NUM : 3; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_FLUSH { - struct { - unsigned int D2H_FLUSH_FLUSH_NUM : 4; - unsigned int D2H_FLUSH_MBX_ENC_DATA : 4; - unsigned int D2H_FLUSH_MBX_ADDR_SEL : 3; - unsigned int D2H_FLUSH_XPB_CLG : 5; - unsigned int D2H_FLUSH_SEND_HOST : 1; - unsigned int D2H_FLUSH_SEND_SIDE : 1; - unsigned int D2H_FLUSH_ALTER_FLUSH_NUM : 1; - unsigned int D2H_FLUSH_RSVD_0 : 1; - unsigned int D2H_FLUSH_RSVD_1 : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_10 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_11 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_12 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_13 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_14 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_15 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_16 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_17 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_18 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_19 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_20 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_21 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_22 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_23 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_24 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_25 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_26 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_27 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_28 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_29 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_30 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_31 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_32 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_33 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_34 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_4 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_5 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_6 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_7 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_8 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_D2H_RSVD_9 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_DBG_ADDR { - struct { - unsigned int STS : 16; - unsigned int CTRL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_DBG_DATA { - struct { - unsigned int STS : 16; - unsigned int CTRL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_DBG_MASK { - struct { - unsigned int STS : 16; - unsigned int CTRL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_DIRECT2HDP_FIRST { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_DIRECT2HDP_LAST { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_FLUSH_ARMED_STS { - struct { - unsigned int FLUSH_ARMED_STS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_FLUSH_CNTR0_STS { - struct { - unsigned int FLUSH_CNTR0_STS : 26; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_HDP_IPH_CFG { - struct { - unsigned int HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE : 6; - unsigned int HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE : 6; - unsigned int HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING : 1; - unsigned int HDP_IPH_CFG_P2P_RD_EN__VI : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_HDP_MBX_MC_CFG { - struct { - unsigned int HDP_MBX_MC_CFG_TAP_WRREQ_PRIV : 1; - unsigned int HDP_MBX_MC_CFG_TAP_WRREQ_SWAP : 2; - unsigned int HDP_MBX_MC_CFG_TAP_WRREQ_TRAN : 1; - unsigned int HDP_MBX_MC_CFG_TAP_WRREQ_VMID__VI : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_HDP_MC_CFG { - struct { - unsigned int HDP_MC_CFG_HST_TAP_WRREQ_PRIV : 1; - unsigned int HDP_MC_CFG_HST_TAP_WRREQ_SWAP : 2; - unsigned int HDP_MC_CFG_HST_TAP_WRREQ_TRAN : 1; - unsigned int HDP_MC_CFG_SID_TAP_WRREQ_PRIV : 1; - unsigned int HDP_MC_CFG_SID_TAP_WRREQ_SWAP : 2; - unsigned int HDP_MC_CFG_SID_TAP_WRREQ_TRAN : 1; - unsigned int HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE : 6; - unsigned int HDP_MC_CFG_XDP_HIGHER_PRI_THRESH : 6; - unsigned int HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK : 3; - unsigned int HDP_MC_CFG_HST_TAP_WRREQ_VMID__VI : 4; - unsigned int HDP_MC_CFG_SID_TAP_WRREQ_VMID__VI : 4; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_HST_CFG { - struct { - unsigned int HST_CFG_WR_COMBINE_EN : 1; - unsigned int HST_CFG_WR_COMBINE_TIMER : 2; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_BAR0 { - struct { - unsigned int ADDR : 16; - unsigned int FLUSH : 4; - unsigned int VALID : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_BAR1 { - struct { - unsigned int ADDR : 16; - unsigned int FLUSH : 4; - unsigned int VALID : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_BAR2 { - struct { - unsigned int ADDR : 16; - unsigned int FLUSH : 4; - unsigned int VALID : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_BAR3 { - struct { - unsigned int ADDR : 16; - unsigned int FLUSH : 4; - unsigned int VALID : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_BAR4 { - struct { - unsigned int ADDR : 16; - unsigned int FLUSH : 4; - unsigned int VALID : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_BAR5 { - struct { - unsigned int ADDR : 16; - unsigned int FLUSH : 4; - unsigned int VALID : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_BAR6 { - struct { - unsigned int ADDR : 16; - unsigned int FLUSH : 4; - unsigned int VALID : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_BAR7 { - struct { - unsigned int ADDR : 16; - unsigned int FLUSH : 4; - unsigned int VALID : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_BAR_CFG { - struct { - unsigned int P2P_BAR_CFG_ADDR_SIZE : 4; - unsigned int P2P_BAR_CFG_BAR_FROM : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_MBX_ADDR0 { - struct { - unsigned int VALID : 1; - unsigned int ADDR : 20; - unsigned int ADDR_39_36__VI : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_MBX_ADDR1 { - struct { - unsigned int VALID : 1; - unsigned int ADDR : 20; - unsigned int ADDR_39_36__VI : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_MBX_ADDR2 { - struct { - unsigned int VALID : 1; - unsigned int ADDR : 20; - unsigned int ADDR_39_36__VI : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_MBX_ADDR3 { - struct { - unsigned int VALID : 1; - unsigned int ADDR : 20; - unsigned int ADDR_39_36__VI : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_MBX_ADDR4 { - struct { - unsigned int VALID : 1; - unsigned int ADDR : 20; - unsigned int ADDR_39_36__VI : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_MBX_ADDR5 { - struct { - unsigned int VALID : 1; - unsigned int ADDR : 20; - unsigned int ADDR_39_36__VI : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_MBX_ADDR6 { - struct { - unsigned int VALID : 1; - unsigned int ADDR : 20; - unsigned int ADDR_39_36__VI : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_P2P_MBX_OFFSET { - struct { - unsigned int P2P_MBX_OFFSET : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_SID_CFG { - struct { - unsigned int SID_CFG_WR_COMBINE_EN : 1; - unsigned int SID_CFG_WR_COMBINE_TIMER : 2; - unsigned int SID_CFG_FLNUM_MSB_SEL : 2; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_SRBM_CFG { - struct { - unsigned int SRBM_CFG_REG_CLK_ENABLE_COUNT : 6; - unsigned int SRBM_CFG_REG_CLK_GATING_DIS : 1; - unsigned int SRBM_CFG_WAKE_DYN_CLK : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_STICKY { - struct { - unsigned int STICKY_STS : 16; - unsigned int STICKY_W1C : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HEADER { - struct { - unsigned int HEADER_TYPE : 7; - unsigned int DEVICE_TYPE : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HFS_SEED0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HFS_SEED1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HFS_SEED2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HFS_SEED3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HOST_BUSNUM { - struct { - unsigned int HOST_ID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HW_DEBUG { - struct { - unsigned int HW_00_DEBUG : 1; - unsigned int HW_01_DEBUG : 1; - unsigned int HW_02_DEBUG : 1; - unsigned int HW_03_DEBUG : 1; - unsigned int HW_04_DEBUG : 1; - unsigned int HW_05_DEBUG : 1; - unsigned int HW_06_DEBUG : 1; - unsigned int HW_07_DEBUG : 1; - unsigned int HW_08_DEBUG : 1; - unsigned int HW_09_DEBUG : 1; - unsigned int HW_10_DEBUG : 1; - unsigned int HW_11_DEBUG : 1; - unsigned int HW_12_DEBUG : 1; - unsigned int HW_13_DEBUG : 1; - unsigned int HW_14_DEBUG : 1; - unsigned int HW_15_DEBUG : 1; - unsigned int HW_16_DEBUG : 1; - unsigned int HW_17_DEBUG : 1; - unsigned int HW_18_DEBUG : 1; - unsigned int HW_19_DEBUG : 1; - unsigned int HW_20_DEBUG : 1; - unsigned int HW_21_DEBUG : 1; - unsigned int HW_22_DEBUG : 1; - unsigned int HW_23_DEBUG : 1; - unsigned int HW_24_DEBUG : 1; - unsigned int HW_25_DEBUG : 1; - unsigned int HW_26_DEBUG : 1; - unsigned int HW_27_DEBUG : 1; - unsigned int HW_28_DEBUG : 1; - unsigned int HW_29_DEBUG : 1; - unsigned int HW_30_DEBUG : 1; - unsigned int HW_31_DEBUG : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union I2C_DATA__SI { - struct { - unsigned int : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_CNTL_STATUS { - struct { - unsigned int IA_BUSY : 1; - unsigned int IA_DMA_BUSY : 1; - unsigned int IA_DMA_REQ_BUSY : 1; - unsigned int IA_GRP_BUSY : 1; - unsigned int IA_ADC_BUSY : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_CNTL { - struct { - unsigned int IA_DEBUG_INDX : 6; - unsigned int IA_DEBUG_SEL_BUS_B : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG0__CI__VI { - struct { - unsigned int ia_busy_extended : 1; - unsigned int ia_nodma_busy_extended : 1; - unsigned int ia_busy : 1; - unsigned int ia_nodma_busy : 1; - unsigned int SPARE0 : 1; - unsigned int dma_req_busy : 1; - unsigned int dma_busy : 1; - unsigned int mc_xl8r_busy : 1; - unsigned int grp_busy : 1; - unsigned int SPARE1 : 1; - unsigned int dma_grp_valid : 1; - unsigned int grp_dma_read : 1; - unsigned int dma_grp_hp_valid : 1; - unsigned int grp_dma_hp_read : 1; - unsigned int SPARE2 : 10; - unsigned int reg_clk_busy : 1; - unsigned int core_clk_busy : 1; - unsigned int SPARE3 : 1; - unsigned int SPARE4 : 1; - unsigned int sclk_reg_vld : 1; - unsigned int sclk_core_vld : 1; - unsigned int SPARE5 : 1; - unsigned int SPARE6 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG0__SI { - struct { - unsigned int ia_busy_extended : 1; - unsigned int ia_nodma_busy_extended : 1; - unsigned int ia_busy : 1; - unsigned int ia_nodma_busy : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int dma_busy : 1; - unsigned int mc_xl8r_busy : 1; - unsigned int grp_busy : 1; - unsigned int : 1; - unsigned int dma_grp_valid : 1; - unsigned int grp_dma_read : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SPARE3 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int reg_clk_busy : 1; - unsigned int : 1; - unsigned int core_clk_busy : 1; - unsigned int : 1; - unsigned int sclk_reg_vld : 1; - unsigned int sclk_core_vld : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG1__CI__VI { - struct { - unsigned int dma_input_fifo_empty : 1; - unsigned int dma_input_fifo_full : 1; - unsigned int start_new_packet : 1; - unsigned int dma_rdreq_dr_q : 1; - unsigned int dma_zero_indices_q : 1; - unsigned int dma_buf_type_q : 2; - unsigned int dma_req_path_q : 1; - unsigned int discard_1st_chunk : 1; - unsigned int discard_2nd_chunk : 1; - unsigned int second_tc_ret_data_q : 1; - unsigned int dma_tc_ret_sel_q : 1; - unsigned int last_rdreq_in_dma_op : 1; - unsigned int dma_mask_fifo_empty : 1; - unsigned int dma_data_fifo_empty_q : 1; - unsigned int dma_data_fifo_full : 1; - unsigned int dma_req_fifo_empty : 1; - unsigned int dma_req_fifo_full : 1; - unsigned int stage2_dr : 1; - unsigned int stage2_rtr : 1; - unsigned int stage3_dr : 1; - unsigned int stage3_rtr : 1; - unsigned int stage4_dr : 1; - unsigned int stage4_rtr : 1; - unsigned int dma_skid_fifo_empty : 1; - unsigned int dma_skid_fifo_full : 1; - unsigned int dma_grp_valid : 1; - unsigned int grp_dma_read : 1; - unsigned int current_data_valid : 1; - unsigned int out_of_range_r2_q : 1; - unsigned int dma_mask_fifo_we : 1; - unsigned int dma_ret_data_we_q : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG1__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 5; - unsigned int : 3; - unsigned int : 6; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG2__CI__VI { - struct { - unsigned int hp_dma_input_fifo_empty : 1; - unsigned int hp_dma_input_fifo_full : 1; - unsigned int hp_start_new_packet : 1; - unsigned int hp_dma_rdreq_dr_q : 1; - unsigned int hp_dma_zero_indices_q : 1; - unsigned int hp_dma_buf_type_q : 2; - unsigned int hp_dma_req_path_q : 1; - unsigned int hp_discard_1st_chunk : 1; - unsigned int hp_discard_2nd_chunk : 1; - unsigned int hp_second_tc_ret_data_q : 1; - unsigned int hp_dma_tc_ret_sel_q : 1; - unsigned int hp_last_rdreq_in_dma_op : 1; - unsigned int hp_dma_mask_fifo_empty : 1; - unsigned int hp_dma_data_fifo_empty_q : 1; - unsigned int hp_dma_data_fifo_full : 1; - unsigned int hp_dma_req_fifo_empty : 1; - unsigned int hp_dma_req_fifo_full : 1; - unsigned int hp_stage2_dr : 1; - unsigned int hp_stage2_rtr : 1; - unsigned int hp_stage3_dr : 1; - unsigned int hp_stage3_rtr : 1; - unsigned int hp_stage4_dr : 1; - unsigned int hp_stage4_rtr : 1; - unsigned int hp_dma_skid_fifo_empty : 1; - unsigned int hp_dma_skid_fifo_full : 1; - unsigned int hp_dma_grp_valid : 1; - unsigned int hp_grp_dma_read : 1; - unsigned int hp_current_data_valid : 1; - unsigned int hp_out_of_range_r2_q : 1; - unsigned int hp_dma_mask_fifo_we : 1; - unsigned int hp_dma_ret_data_we_q : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG2__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG3__CI__VI { - struct { - unsigned int dma_pipe0_rdreq_valid : 1; - unsigned int dma_pipe0_rdreq_read : 1; - unsigned int dma_pipe0_rdreq_null_out : 1; - unsigned int dma_pipe0_rdreq_eop_out : 1; - unsigned int dma_pipe0_rdreq_use_tc_out : 1; - unsigned int grp_dma_draw_is_pipe0 : 1; - unsigned int must_service_pipe0_req : 1; - unsigned int send_pipe1_req : 1; - unsigned int dma_pipe1_rdreq_valid : 1; - unsigned int dma_pipe1_rdreq_read : 1; - unsigned int dma_pipe1_rdreq_null_out : 1; - unsigned int dma_pipe1_rdreq_eop_out : 1; - unsigned int dma_pipe1_rdreq_use_tc_out : 1; - unsigned int ia_mc_rdreq_rtr_q : 1; - unsigned int mc_out_rtr : 1; - unsigned int dma_rdreq_send_out : 1; - unsigned int pipe0_dr : 1; - unsigned int pipe0_rtr : 1; - unsigned int ia_tc_rdreq_rtr_q : 1; - unsigned int tc_out_rtr : 1; - unsigned int pair0_valid_p1 : 1; - unsigned int pair1_valid_p1 : 1; - unsigned int pair2_valid_p1 : 1; - unsigned int pair3_valid_p1 : 1; - unsigned int tc_req_count_q : 2; - unsigned int discard_1st_chunk : 1; - unsigned int discard_2nd_chunk : 1; - unsigned int last_tc_req_p1 : 1; - unsigned int IA_TC_rdreq_send_out : 1; - unsigned int TC_IA_rdret_valid_in : 1; - unsigned int TAP_IA_rdret_vld_in : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG3__SI { - struct { - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG4__CI__VI { - struct { - unsigned int pipe0_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe2_dr : 1; - unsigned int pipe3_dr : 1; - unsigned int pipe4_dr : 1; - unsigned int pipe5_dr : 1; - unsigned int grp_se0_fifo_empty : 1; - unsigned int grp_se0_fifo_full : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int pipe2_rtr : 1; - unsigned int pipe3_rtr : 1; - unsigned int pipe4_rtr : 1; - unsigned int pipe5_rtr : 1; - unsigned int ia_vgt_prim_rtr_q : 1; - unsigned int ia_se1vgt_prim_rtr_q : 1; - unsigned int di_major_mode_p1_q : 1; - unsigned int gs_mode_p1_q : 3; - unsigned int di_event_flag_p1_q : 1; - unsigned int di_state_sel_p1_q : 3; - unsigned int draw_opaq_en_p1_q : 1; - unsigned int draw_opaq_active_q : 1; - unsigned int di_source_select_p1_q : 2; - unsigned int ready_to_read_di : 1; - unsigned int di_first_group_of_draw_q : 1; - unsigned int last_shift_of_draw : 1; - unsigned int current_shift_is_vect1_q : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG4__SI { - struct { - unsigned int pipe0_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe2_dr : 1; - unsigned int pipe3_dr : 1; - unsigned int pipe4_dr : 1; - unsigned int pipe5_dr : 1; - unsigned int grp_se0_fifo_empty : 1; - unsigned int grp_se0_fifo_full : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int pipe2_rtr : 1; - unsigned int pipe3_rtr : 1; - unsigned int pipe4_rtr : 1; - unsigned int pipe5_rtr : 1; - unsigned int ia_vgt_prim_rtr_q : 1; - unsigned int ia_se1vgt_prim_rtr_q : 1; - unsigned int : 1; - unsigned int gs_mode_p1_q : 3; - unsigned int di_event_flag_p1_q : 1; - unsigned int di_state_sel_p1_q : 3; - unsigned int draw_opaq_en_p1_q : 1; - unsigned int draw_opaq_active_q : 1; - unsigned int di_source_select_p1_q : 2; - unsigned int ready_to_read_di : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int current_shift_is_vect1_q : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG5__CI__VI { - struct { - unsigned int di_index_counter_q_15_0 : 16; - unsigned int instanceid_13_0 : 14; - unsigned int draw_input_fifo_full : 1; - unsigned int draw_input_fifo_empty : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG5__SI { - struct { - unsigned int di_index_counter_q_15_0 : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG6__CI__VI { - struct { - unsigned int current_shift_q : 4; - unsigned int current_stride_pre : 4; - unsigned int current_stride_q : 5; - unsigned int first_group_partial : 1; - unsigned int second_group_partial : 1; - unsigned int curr_prim_partial : 1; - unsigned int next_stride_q : 5; - unsigned int next_group_partial : 1; - unsigned int after_group_partial : 1; - unsigned int extract_group : 1; - unsigned int grp_shift_debug_data : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG6__SI { - struct { - unsigned int current_shift_q : 4; - unsigned int current_stride_pre : 4; - unsigned int current_stride_q : 5; - unsigned int : 1; - unsigned int : 1; - unsigned int curr_prim_partial : 1; - unsigned int next_stride_q : 5; - unsigned int : 1; - unsigned int : 1; - unsigned int extract_group : 1; - unsigned int : 5; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG7__CI__VI { - struct { - unsigned int reset_indx_state_q : 4; - unsigned int shift_vect_valid_p2_q : 4; - unsigned int shift_vect1_valid_p2_q : 4; - unsigned int shift_vect0_reset_match_p2_q : 4; - unsigned int shift_vect1_reset_match_p2_q : 4; - unsigned int num_indx_in_group_p2_q : 3; - unsigned int last_group_of_draw_p2_q : 1; - unsigned int shift_event_flag_p2_q : 1; - unsigned int indx_shift_is_one_p2_q : 1; - unsigned int indx_shift_is_two_p2_q : 1; - unsigned int indx_stride_is_four_p2_q : 1; - unsigned int shift_prim1_reset_p3_q : 1; - unsigned int shift_prim1_partial_p3_q : 1; - unsigned int shift_prim0_reset_p3_q : 1; - unsigned int shift_prim0_partial_p3_q : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG7__SI { - struct { - unsigned int reset_indx_state_q : 4; - unsigned int shift_vect_valid_p2_q : 4; - unsigned int : 4; - unsigned int shift_vect0_reset_match_p2_q : 4; - unsigned int shift_vect1_reset_match_p2_q : 4; - unsigned int num_indx_in_group_p2_q : 3; - unsigned int : 1; - unsigned int shift_event_flag_p2_q : 1; - unsigned int indx_shift_is_one_p2_q : 1; - unsigned int indx_shift_is_two_p2_q : 1; - unsigned int indx_stride_is_four_p2_q : 1; - unsigned int shift_prim1_reset_p3_q : 1; - unsigned int shift_prim1_partial_p3_q : 1; - unsigned int shift_prim0_reset_p3_q : 1; - unsigned int shift_prim0_partial_p3_q : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG8 { - struct { - unsigned int di_prim_type_p1_q : 5; - unsigned int two_cycle_xfer_p1_q : 1; - unsigned int two_prim_input_p1_q : 1; - unsigned int shift_vect_end_of_packet_p5_q : 1; - unsigned int last_group_of_inst_p5_q : 1; - unsigned int shift_prim1_null_flag_p5_q : 1; - unsigned int shift_prim0_null_flag_p5_q : 1; - unsigned int grp_continued : 1; - unsigned int grp_state_sel : 3; - unsigned int grp_sub_prim_type : 6; - unsigned int grp_output_path : 3; - unsigned int grp_null_primitive : 1; - unsigned int grp_eop : 1; - unsigned int grp_eopg : 1; - unsigned int grp_event_flag : 1; - unsigned int grp_components_valid : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG9__CI__VI { - struct { - unsigned int send_to_se1_p6 : 1; - unsigned int gfx_se_switch_p6 : 1; - unsigned int null_eoi_xfer_prim1_p6 : 1; - unsigned int null_eoi_xfer_prim0_p6 : 1; - unsigned int prim1_eoi_p6 : 1; - unsigned int prim0_eoi_p6 : 1; - unsigned int prim1_valid_eopg_p6 : 1; - unsigned int prim0_valid_eopg_p6 : 1; - unsigned int prim1_to_other_se_p6 : 1; - unsigned int eopg_on_last_prim_p6 : 1; - unsigned int eopg_between_prims_p6 : 1; - unsigned int prim_count_eq_group_size_p6 : 1; - unsigned int prim_count_gt_group_size_p6 : 1; - unsigned int two_prim_output_p5_q : 1; - unsigned int SPARE0 : 1; - unsigned int SPARE1 : 1; - unsigned int shift_vect_end_of_packet_p5_q : 1; - unsigned int prim1_xfer_p6 : 1; - unsigned int grp_se1_fifo_empty : 1; - unsigned int grp_se1_fifo_full : 1; - unsigned int prim_counter_q : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_DEBUG_REG9__SI { - struct { - unsigned int : 1; - unsigned int gfx_se_switch_p6 : 1; - unsigned int null_eoi_xfer_prim1_p6 : 1; - unsigned int null_eoi_xfer_prim0_p6 : 1; - unsigned int prim1_eoi_p6 : 1; - unsigned int prim0_eoi_p6 : 1; - unsigned int prim1_valid_eopg_p6 : 1; - unsigned int prim0_valid_eopg_p6 : 1; - unsigned int prim1_to_other_se_p6 : 1; - unsigned int eopg_on_last_prim_p6 : 1; - unsigned int eopg_between_prims_p6 : 1; - unsigned int prim_count_eq_group_size_p6 : 1; - unsigned int prim_count_gt_group_size_p6 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int prim1_xfer_p6 : 1; - unsigned int prim_counter_q : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_ENHANCE { - struct { - unsigned int MISC : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_MULTI_VGT_PARAM { - struct { - unsigned int PRIMGROUP_SIZE : 16; - unsigned int PARTIAL_VS_WAVE_ON : 1; - unsigned int SWITCH_ON_EOP : 1; - unsigned int PARTIAL_ES_WAVE_ON : 1; - unsigned int SWITCH_ON_EOI : 1; - unsigned int WD_SWITCH_ON_EOP__CI__VI : 1; - unsigned int : 7; - unsigned int MAX_PRIMGRP_IN_WAVE__VI : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE3 : 4; - unsigned int PERF_MODE2 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER0_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1 : 10; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER0_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER1_SELECT { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER2_SELECT { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_PERFCOUNTER3_SELECT { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IA_VMID_OVERRIDE__SI__CI { - struct { - unsigned int ENABLE : 1; - unsigned int VMID : 4; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IDDCCIF02_DBG_DCCIF_C__SI__VI { - struct { - unsigned int DBG_DCCIF_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IDDCCIF04_DBG_DCCIF_E__SI__VI { - struct { - unsigned int DBG_DCCIF_E : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IDDCCIF05_DBG_DCCIF_F__SI__VI { - struct { - unsigned int DBG_DCCIF_F : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_ADVFAULT_CNTL__SI__CI { - struct { - unsigned int WATERMARK : 3; - unsigned int WATERMARK_ENABLE : 1; - unsigned int WATERMARK_REACHED : 1; - unsigned int : 3; - unsigned int NUM_FAULTS_DROPPED : 8; - unsigned int WAIT_TIMER : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_CNTL { - struct { - unsigned int ENABLE_INTR : 1; - unsigned int MC_SWAP : 2; - unsigned int MC_TRAN : 1; - unsigned int RPTR_REARM : 1; - unsigned int : 3; - unsigned int CLIENT_FIFO_HIGHWATER : 2; - unsigned int MC_FIFO_HIGHWATER : 5; - unsigned int MC_WRREQ_CREDIT : 5; - unsigned int MC_WR_CLEAN_CNT : 5; - unsigned int MC_VMID__CI__VI : 4; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_LEVEL_STATUS { - struct { - unsigned int DC_STATUS : 1; - unsigned int : 1; - unsigned int ROM_STATUS : 1; - unsigned int SRBM_STATUS : 1; - unsigned int BIF_STATUS : 1; - unsigned int XDMA_STATUS__CI__VI : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_PERFCOUNTER0_RESULT__CI__VI { - struct { - unsigned int PERF_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_PERFCOUNTER1_RESULT__CI__VI { - struct { - unsigned int PERF_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_PERFMON_CNTL__CI__VI { - struct { - unsigned int ENABLE0 : 1; - unsigned int CLEAR0 : 1; - unsigned int PERF_SEL0 : 6; - unsigned int ENABLE1 : 1; - unsigned int CLEAR1 : 1; - unsigned int PERF_SEL1 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_RB_BASE { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_RB_CNTL { - struct { - unsigned int RB_ENABLE : 1; - unsigned int RB_SIZE : 5; - unsigned int RB_FULL_DRAIN_ENABLE : 1; - unsigned int RB_GPU_TS_ENABLE : 1; - unsigned int WPTR_WRITEBACK_ENABLE : 1; - unsigned int WPTR_WRITEBACK_TIMER : 5; - unsigned int : 2; - unsigned int WPTR_OVERFLOW_ENABLE : 1; - unsigned int ENABLE_INTR__VI : 1; - unsigned int MC_SWAP__VI : 2; - unsigned int : 1; - unsigned int RPTR_REARM__VI : 1; - unsigned int : 2; - unsigned int MC_VMID__VI : 4; - unsigned int : 3; - unsigned int WPTR_OVERFLOW_CLEAR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_RB_RPTR { - struct { - unsigned int : 2; - unsigned int OFFSET : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_RB_WPTR { - struct { - unsigned int RB_OVERFLOW : 1; - unsigned int : 1; - unsigned int OFFSET : 16; - unsigned int RB_LEFT_NONE__VI : 1; - unsigned int RB_MAY_OVERFLOW__VI : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_RB_WPTR_ADDR_HI { - struct { - unsigned int ADDR : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_RB_WPTR_ADDR_LO { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_STATUS { - struct { - unsigned int IDLE : 1; - unsigned int INPUT_IDLE : 1; - unsigned int RB_IDLE : 1; - unsigned int RB_FULL : 1; - unsigned int RB_FULL_DRAIN : 1; - unsigned int RB_OVERFLOW : 1; - unsigned int MC_WR_IDLE : 1; - unsigned int MC_WR_STALL : 1; - unsigned int MC_WR_CLEAN_PENDING : 1; - unsigned int MC_WR_CLEAN_STALL : 1; - unsigned int BIF_INTERRUPT_LINE : 1; - unsigned int SWITCH_READY__VI : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_0_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_10_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_11_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_12_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_13_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_14_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_15_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_1_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_2_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_3_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_4_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_5_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_6_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_7_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_8_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VMID_9_LUT__CI__VI { - struct { - unsigned int PASID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__SI__VI { - struct { - unsigned int IMMEDIATE_COMMAND_WRITE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__SI__VI { - struct { - unsigned int IMMEDIATE_COMMAND_WRITE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IMMEDIATE_COMMAND_OUTPUT_INTERFACE__SI__VI { - struct { - unsigned int IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD : 28; - unsigned int IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IMMEDIATE_COMMAND_STATUS__SI__VI { - struct { - unsigned int IMMEDIATE_COMMAND_BUSY : 1; - unsigned int IMMEDIATE_RESULT_VALID : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IMMEDIATE_RESPONSE_INPUT_INTERFACE__SI__VI { - struct { - unsigned int IMMEDIATE_RESPONSE_READ : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IMPCTL_RESET__CI__VI { - struct { - unsigned int IMP_SW_RESET : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_PAYLOAD_CAPABILITY__SI__VI { - struct { - unsigned int INPUT_PAYLOAD_CAPABILITY : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INTERRUPT_CNTL { - struct { - unsigned int IH_DUMMY_RD_OVERRIDE : 1; - unsigned int IH_DUMMY_RD_EN : 1; - unsigned int : 1; - unsigned int IH_REQ_NONSNOOP_EN : 1; - unsigned int IH_INTR_DLY_CNTR : 4; - unsigned int GEN_IH_INT_EN : 1; - unsigned int GEN_GPIO_INT_EN : 4; - unsigned int SELECT_INT_GPIO_OUTPUT : 2; - unsigned int BIF_RB_REQ_NONSNOOP_EN__VI : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INTERRUPT_CNTL2 { - struct { - unsigned int IH_DUMMY_RD_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INTERRUPT_CONTROL__SI { - struct { - unsigned int OUTPUT_STREAM_0_INTERRUPT_ENABLE : 1; - unsigned int : 29; - unsigned int CONTROLLER_INTERRUPT_ENABLE : 1; - unsigned int GLOBAL_INTERRUPT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INTERRUPT_CONTROL__VI { - struct { - unsigned int STREAM_0_INTERRUPT_ENABLE : 1; - unsigned int STREAM_1_INTERRUPT_ENABLE : 1; - unsigned int STREAM_2_INTERRUPT_ENABLE : 1; - unsigned int STREAM_3_INTERRUPT_ENABLE : 1; - unsigned int STREAM_4_INTERRUPT_ENABLE : 1; - unsigned int STREAM_5_INTERRUPT_ENABLE : 1; - unsigned int STREAM_6_INTERRUPT_ENABLE : 1; - unsigned int STREAM_7_INTERRUPT_ENABLE : 1; - unsigned int STREAM_8_INTERRUPT_ENABLE : 1; - unsigned int STREAM_9_INTERRUPT_ENABLE : 1; - unsigned int STREAM_10_INTERRUPT_ENABLE : 1; - unsigned int STREAM_11_INTERRUPT_ENABLE : 1; - unsigned int STREAM_12_INTERRUPT_ENABLE : 1; - unsigned int STREAM_13_INTERRUPT_ENABLE : 1; - unsigned int STREAM_14_INTERRUPT_ENABLE : 1; - unsigned int STREAM_15_INTERRUPT_ENABLE : 1; - unsigned int : 14; - unsigned int CONTROLLER_INTERRUPT_ENABLE : 1; - unsigned int GLOBAL_INTERRUPT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INTERRUPT_LINE { - struct { - unsigned int INTERRUPT_LINE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INTERRUPT_PIN { - struct { - unsigned int INTERRUPT_PIN : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INTERRUPT_STATUS__SI { - struct { - unsigned int OUTPUT_STREAM_0_INTERRUPT_STATUS : 1; - unsigned int : 29; - unsigned int CONTROLLER_INTERRUPT_STATUS : 1; - unsigned int GLOBAL_INTERRUPT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INTERRUPT_STATUS__VI { - struct { - unsigned int STREAM_0_INTERRUPT_STATUS : 1; - unsigned int STREAM_1_INTERRUPT_STATUS : 1; - unsigned int STREAM_2_INTERRUPT_STATUS : 1; - unsigned int STREAM_3_INTERRUPT_STATUS : 1; - unsigned int STREAM_4_INTERRUPT_STATUS : 1; - unsigned int STREAM_5_INTERRUPT_STATUS : 1; - unsigned int STREAM_6_INTERRUPT_STATUS : 1; - unsigned int STREAM_7_INTERRUPT_STATUS : 1; - unsigned int STREAM_8_INTERRUPT_STATUS : 1; - unsigned int STREAM_9_INTERRUPT_STATUS : 1; - unsigned int STREAM_10_INTERRUPT_STATUS : 1; - unsigned int STREAM_11_INTERRUPT_STATUS : 1; - unsigned int STREAM_12_INTERRUPT_STATUS : 1; - unsigned int STREAM_13_INTERRUPT_STATUS : 1; - unsigned int STREAM_14_INTERRUPT_STATUS : 1; - unsigned int STREAM_15_INTERRUPT_STATUS : 1; - unsigned int : 14; - unsigned int CONTROLLER_INTERRUPT_STATUS : 1; - unsigned int GLOBAL_INTERRUPT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INT_MASK__SI { - struct { - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 25; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IT_INT_EN__SI__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IT_STAT__SI__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KEFUSE0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KEFUSE1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KEFUSE2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KEFUSE3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KHFS0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KHFS1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KHFS2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KHFS3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KSESSION0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KSESSION1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KSESSION2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KSESSION3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KSIG0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KSIG1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KSIG2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KSIG3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LATENCY { - struct { - unsigned int LATENCY_TIMER : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_DEBUG__SI__VI { - struct { - unsigned int LB_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_SYNC_RESET_SEL__SI__VI { - struct { - unsigned int LB_SYNC_RESET_SEL : 2; - unsigned int : 2; - unsigned int LB_SYNC_RESET_SEL2__VI : 1; - unsigned int : 3; - unsigned int LB_SYNC_RESET_DELAY__VI : 8; - unsigned int : 6; - unsigned int LB_SYNC_DURATION__VI : 2; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int LB_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int LB_TEST_DEBUG_INDEX : 8; - unsigned int LB_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_CPL_CNTL__CI__VI { - struct { - unsigned int CPL_ENABLE : 1; - unsigned int CPL_THRESHOLD : 16; - unsigned int CPL_BLOCK_ID : 5; - unsigned int CPL_SIGNAL_ID : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_CPL_OVR_SEL__CI__VI { - struct { - unsigned int CPL_OVR_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_CPL_OVR_VAL__CI__VI { - struct { - unsigned int CPL_OVR_VAL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC0_CNTL { - struct { - unsigned int MC0_ENABLE : 1; - unsigned int MC0_THRESHOLD : 16; - unsigned int MC0_BLOCK_ID__CI__VI : 5; - unsigned int MC0_SIGNAL_ID__CI__VI : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC0_OVR_SEL { - struct { - unsigned int MC0_OVR_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC0_OVR_VAL { - struct { - unsigned int MC0_OVR_VAL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC1_CNTL { - struct { - unsigned int MC1_ENABLE : 1; - unsigned int MC1_THRESHOLD : 16; - unsigned int MC1_BLOCK_ID__CI__VI : 5; - unsigned int MC1_SIGNAL_ID__CI__VI : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC1_OVR_SEL { - struct { - unsigned int MC1_OVR_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC1_OVR_VAL { - struct { - unsigned int MC1_OVR_VAL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC2_CNTL { - struct { - unsigned int MC2_ENABLE : 1; - unsigned int MC2_THRESHOLD : 16; - unsigned int MC2_BLOCK_ID__CI__VI : 5; - unsigned int MC2_SIGNAL_ID__CI__VI : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC2_OVR_SEL { - struct { - unsigned int MC2_OVR_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC2_OVR_VAL { - struct { - unsigned int MC2_OVR_VAL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC3_CNTL { - struct { - unsigned int MC3_ENABLE : 1; - unsigned int MC3_THRESHOLD : 16; - unsigned int MC3_BLOCK_ID__CI__VI : 5; - unsigned int MC3_SIGNAL_ID__CI__VI : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC3_OVR_SEL { - struct { - unsigned int MC3_OVR_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC3_OVR_VAL { - struct { - unsigned int MC3_OVR_VAL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC4_CNTL__SI__VI { - struct { - unsigned int MC4_ENABLE : 1; - unsigned int MC4_THRESHOLD : 16; - unsigned int MC4_BLOCK_ID__VI : 5; - unsigned int MC4_SIGNAL_ID__VI : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC4_OVR_SEL__SI__VI { - struct { - unsigned int MC4_OVR_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC4_OVR_VAL__SI__VI { - struct { - unsigned int MC4_OVR_VAL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC5_CNTL__SI__VI { - struct { - unsigned int MC5_ENABLE : 1; - unsigned int MC5_THRESHOLD : 16; - unsigned int MC5_BLOCK_ID__VI : 5; - unsigned int MC5_SIGNAL_ID__VI : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC5_OVR_SEL__SI__VI { - struct { - unsigned int MC5_OVR_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC5_OVR_VAL__SI__VI { - struct { - unsigned int MC5_OVR_VAL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_SX0_CNTL__CI { - struct { - unsigned int SX0_ENABLE : 1; - unsigned int SX0_THRESHOLD : 16; - unsigned int SX0_BLOCK_ID : 5; - unsigned int SX0_SIGNAL_ID : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_SX0_OVR_SEL__CI { - struct { - unsigned int SX0_OVR_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_SX0_OVR_VAL__CI { - struct { - unsigned int SX0_OVR_VAL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCLK_DEEP_SLEEP_CNTL2__CI__VI { - struct { - unsigned int RFE_BUSY_MASK : 1; - unsigned int BIF_CG_LCLK_BUSY_MASK : 1; - unsigned int L1IMU_SMU_IDLE_MASK : 1; - unsigned int : 1; - unsigned int SCLK_RUNNING_MASK : 1; - unsigned int SMU_BUSY_MASK : 1; - unsigned int PCIE_LCLK_IDLE1_MASK : 1; - unsigned int PCIE_LCLK_IDLE2_MASK : 1; - unsigned int PCIE_LCLK_IDLE3_MASK : 1; - unsigned int PCIE_LCLK_IDLE4_MASK : 1; - unsigned int L1IMUGPP_IDLE_MASK : 1; - unsigned int L1IMUGPPSB_IDLE_MASK : 1; - unsigned int L1IMUBIF_IDLE_MASK : 1; - unsigned int L1IMUINTGEN_IDLE_MASK : 1; - unsigned int L2IMU_IDLE_MASK : 1; - unsigned int ORB_IDLE_MASK : 1; - unsigned int ON_INB_WAKE_MASK : 1; - unsigned int ON_INB_WAKE_ACK_MASK : 1; - unsigned int ON_OUTB_WAKE_MASK : 1; - unsigned int ON_OUTB_WAKE_ACK_MASK : 1; - unsigned int DMAACTIVE_MASK : 1; - unsigned int RLC_SMU_GFXCLK_OFF_MASK__VI : 1; - unsigned int RESERVED__VI : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCLK_DEEP_SLEEP_CNTL__CI__VI { - struct { - unsigned int DIV_ID : 3; - unsigned int RAMP_DIS : 1; - unsigned int HYSTERESIS : 12; - unsigned int : 15; - unsigned int ENABLE_DS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LINK_CAP { - struct { - unsigned int LINK_SPEED : 4; - unsigned int LINK_WIDTH : 6; - unsigned int PM_SUPPORT : 2; - unsigned int L0S_EXIT_LATENCY : 3; - unsigned int L1_EXIT_LATENCY : 3; - unsigned int CLOCK_POWER_MANAGEMENT : 1; - unsigned int SURPRISE_DOWN_ERR_REPORTING : 1; - unsigned int DL_ACTIVE_REPORTING_CAPABLE : 1; - unsigned int LINK_BW_NOTIFICATION_CAP : 1; - unsigned int ASPM_OPTIONALITY_COMPLIANCE__CI__VI : 1; - unsigned int : 1; - unsigned int PORT_NUMBER : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LINK_CAP2__CI__VI { - struct { - unsigned int : 1; - unsigned int SUPPORTED_LINK_SPEED : 7; - unsigned int CROSSLINK_SUPPORTED : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LINK_CAP2__SI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LINK_CNTL { - struct { - unsigned int PM_CONTROL : 2; - unsigned int : 1; - unsigned int READ_CPL_BOUNDARY : 1; - unsigned int LINK_DIS : 1; - unsigned int RETRAIN_LINK : 1; - unsigned int COMMON_CLOCK_CFG : 1; - unsigned int EXTENDED_SYNC : 1; - unsigned int CLOCK_POWER_MANAGEMENT_EN : 1; - unsigned int HW_AUTONOMOUS_WIDTH_DISABLE : 1; - unsigned int LINK_BW_MANAGEMENT_INT_EN : 1; - unsigned int LINK_AUTONOMOUS_BW_INT_EN : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LINK_CNTL2 { - struct { - unsigned int TARGET_LINK_SPEED : 4; - unsigned int ENTER_COMPLIANCE : 1; - unsigned int HW_AUTONOMOUS_SPEED_DISABLE : 1; - unsigned int SELECTABLE_DEEMPHASIS : 1; - unsigned int XMIT_MARGIN : 3; - unsigned int ENTER_MOD_COMPLIANCE : 1; - unsigned int COMPLIANCE_SOS : 1; - unsigned int COMPLIANCE_DEEMPHASIS : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LINK_STATUS { - struct { - unsigned int CURRENT_LINK_SPEED : 4; - unsigned int NEGOTIATED_LINK_WIDTH : 6; - unsigned int : 1; - unsigned int LINK_TRAINING : 1; - unsigned int SLOT_CLOCK_CFG : 1; - unsigned int DL_ACTIVE : 1; - unsigned int LINK_BW_MANAGEMENT_STATUS : 1; - unsigned int LINK_AUTONOMOUS_BW_STATUS : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LINK_STATUS2 { - struct { - unsigned int CUR_DEEMPHASIS_LEVEL : 1; - unsigned int EQUALIZATION_COMPLETE__CI__VI : 1; - unsigned int EQUALIZATION_PHASE1_SUCCESS__CI__VI : 1; - unsigned int EQUALIZATION_PHASE2_SUCCESS__CI__VI : 1; - unsigned int EQUALIZATION_PHASE3_SUCCESS__CI__VI : 1; - unsigned int LINK_EQUALIZATION_REQUEST__CI__VI : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LNCNT_CONTROL__CI { - struct { - unsigned int LNCNT_ACC_MODE : 1; - unsigned int LNCNT_REF_TIMEBASE : 2; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LNCNT_CONTROL__VI { - struct { - unsigned int CFG_LNC_WINDOW_EN0 : 1; - unsigned int CFG_LNC_BW_CNT_EN1 : 1; - unsigned int CFG_LNC_CMN_CNT_EN2 : 1; - unsigned int CFG_LNC_OVRD_EN3 : 1; - unsigned int CFG_LNC_OVRD_VAL4 : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LVDS_DATA_CNTL__SI__VI { - struct { - unsigned int LVDS_24BIT_ENABLE : 1; - unsigned int : 3; - unsigned int LVDS_24BIT_FORMAT : 1; - unsigned int : 3; - unsigned int LVDS_2ND_CHAN_DE : 1; - unsigned int LVDS_2ND_CHAN_VS : 1; - unsigned int LVDS_2ND_CHAN_HS : 1; - unsigned int : 1; - unsigned int LVDS_2ND_LINK_CNTL_BITS : 3; - unsigned int : 1; - unsigned int LVDS_FP_POL : 1; - unsigned int LVDS_LP_POL : 1; - unsigned int LVDS_DTMG_POL : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LVTMA_PWRSEQ_CNTL__SI__VI { - struct { - unsigned int LVTMA_PWRSEQ_EN : 1; - unsigned int LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int LVTMA_PWRSEQ_TARGET_STATE : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int LVTMA_SYNCEN : 1; - unsigned int LVTMA_SYNCEN_OVRD : 1; - unsigned int LVTMA_SYNCEN_POL : 1; - unsigned int : 5; - unsigned int LVTMA_DIGON : 1; - unsigned int LVTMA_DIGON_OVRD : 1; - unsigned int LVTMA_DIGON_POL : 1; - unsigned int : 5; - unsigned int LVTMA_BLON : 1; - unsigned int LVTMA_BLON_OVRD : 1; - unsigned int LVTMA_BLON_POL : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LVTMA_PWRSEQ_DELAY1__SI__VI { - struct { - unsigned int LVTMA_PWRUP_DELAY1 : 8; - unsigned int LVTMA_PWRUP_DELAY2 : 8; - unsigned int LVTMA_PWRDN_DELAY1 : 8; - unsigned int LVTMA_PWRDN_DELAY2 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LVTMA_PWRSEQ_DELAY2__SI__VI { - struct { - unsigned int LVTMA_PWRDN_MIN_LENGTH : 8; - unsigned int LVTMA_PWRUP_DELAY3__VI : 8; - unsigned int LVTMA_PWRDN_DELAY3__VI : 8; - unsigned int LVTMA_VARY_BL_OVERRIDE_EN__VI : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LVTMA_PWRSEQ_REF_DIV__SI__VI { - struct { - unsigned int LVTMA_PWRSEQ_REF_DIV : 12; - unsigned int : 4; - unsigned int BL_PWM_REF_DIV : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LVTMA_PWRSEQ_STATE__SI__VI { - struct { - unsigned int LVTMA_PWRSEQ_TARGET_STATE_R : 1; - unsigned int LVTMA_PWRSEQ_DIGON : 1; - unsigned int LVTMA_PWRSEQ_SYNCEN : 1; - unsigned int LVTMA_PWRSEQ_BLON : 1; - unsigned int LVTMA_PWRSEQ_DONE : 1; - unsigned int : 3; - unsigned int LVTMA_PWRSEQ_STATE : 4; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LX0 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LX1 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LX2 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LX3 { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAJOR_VERSION__SI__VI { - struct { - unsigned int MAJOR_VERSION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MASTER_COMM_CMD_REG__SI__VI { - struct { - unsigned int MASTER_COMM_CMD_REG_BYTE0 : 8; - unsigned int MASTER_COMM_CMD_REG_BYTE1 : 8; - unsigned int MASTER_COMM_CMD_REG_BYTE2 : 8; - unsigned int MASTER_COMM_CMD_REG_BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MASTER_COMM_CNTL_REG__SI__VI { - struct { - unsigned int MASTER_COMM_INTERRUPT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MASTER_COMM_DATA_REG1__SI__VI { - struct { - unsigned int MASTER_COMM_DATA_REG1_BYTE0 : 8; - unsigned int MASTER_COMM_DATA_REG1_BYTE1 : 8; - unsigned int MASTER_COMM_DATA_REG1_BYTE2 : 8; - unsigned int MASTER_COMM_DATA_REG1_BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MASTER_COMM_DATA_REG2__SI__VI { - struct { - unsigned int MASTER_COMM_DATA_REG2_BYTE0 : 8; - unsigned int MASTER_COMM_DATA_REG2_BYTE1 : 8; - unsigned int MASTER_COMM_DATA_REG2_BYTE2 : 8; - unsigned int MASTER_COMM_DATA_REG2_BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MASTER_COMM_DATA_REG3__SI__VI { - struct { - unsigned int MASTER_COMM_DATA_REG3_BYTE0 : 8; - unsigned int MASTER_COMM_DATA_REG3_BYTE1 : 8; - unsigned int MASTER_COMM_DATA_REG3_BYTE2 : 8; - unsigned int MASTER_COMM_DATA_REG3_BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MASTER_CREDIT_CNTL { - struct { - unsigned int BIF_MC_RDRET_CREDIT : 7; - unsigned int : 9; - unsigned int BIF_AZ_RDRET_CREDIT : 6; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MASTER_UPDATE_LOCK__SI__VI { - struct { - unsigned int MASTER_UPDATE_LOCK : 1; - unsigned int : 7; - unsigned int GSL_CONTROL_MASTER_UPDATE_LOCK__VI : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MASTER_UPDATE_MODE { - struct { - unsigned int MASTER_UPDATE_MODE : 3; - unsigned int : 13; - unsigned int MASTER_UPDATE_INTERLACED_MODE : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAX_LATENCY { - struct { - unsigned int MAX_LAT : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_CONTROL__SI__VI { - struct { - unsigned int MCIF_BUFF_SIZE : 2; - unsigned int : 2; - unsigned int ADDRESS_TRANSLATION_ENABLE : 1; - unsigned int : 3; - unsigned int PRIVILEGED_ACCESS_ENABLE : 1; - unsigned int : 3; - unsigned int MCIF_SLOW_REQ_INTERVAL__VI : 4; - unsigned int LOW_READ_URG_LEVEL : 8; - unsigned int MC_CLEAN_DEASSERT_LATENCY : 6; - unsigned int MCIF_MC_LATENCY_COUNTER_ENABLE : 1; - unsigned int MCIF_MC_LATENCY_COUNTER_URGENT_ONLY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int MCIF_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int MCIF_TEST_DEBUG_INDEX : 8; - unsigned int MCIF_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WRITE_COMBINE_CONTROL__SI__VI { - struct { - unsigned int MCIF_WRITE_COMBINE_TIMEOUT : 8; - unsigned int VIP_WRITE_COMBINE_TIMEOUT : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCLK_PWRMGT_CNTL__SI__CI { - struct { - unsigned int DLL_SPEED : 5; - unsigned int : 1; - unsigned int DLL_READY : 1; - unsigned int MC_INT_CNTL : 1; - unsigned int MRDCK0_PDNB : 1; - unsigned int MRDCK1_PDNB : 1; - unsigned int : 6; - unsigned int MRDCK0_RESET : 1; - unsigned int MRDCK1_RESET : 1; - unsigned int : 6; - unsigned int DLL_READY_READ : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_ADDR_HASH { - struct { - unsigned int BANK_XOR_ENABLE : 4; - unsigned int COL_XOR : 8; - unsigned int ROW_XOR : 16; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_ADDR_SWIZ0__CI__VI { - struct { - unsigned int A8 : 4; - unsigned int A9 : 4; - unsigned int A10 : 4; - unsigned int A11 : 4; - unsigned int A12 : 4; - unsigned int A13 : 4; - unsigned int A14 : 4; - unsigned int A15 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_ADDR_SWIZ1__CI__VI { - struct { - unsigned int A16 : 4; - unsigned int A17 : 4; - unsigned int A18 : 4; - unsigned int A19 : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_AGE_CNTL__CI__VI { - struct { - unsigned int RESET_RD_GROUP0 : 1; - unsigned int RESET_RD_GROUP1 : 1; - unsigned int RESET_RD_GROUP2 : 1; - unsigned int RESET_RD_GROUP3 : 1; - unsigned int RESET_RD_GROUP4 : 1; - unsigned int RESET_RD_GROUP5 : 1; - unsigned int RESET_RD_GROUP6 : 1; - unsigned int RESET_RD_GROUP7 : 1; - unsigned int RESET_WR_GROUP0 : 1; - unsigned int RESET_WR_GROUP1 : 1; - unsigned int RESET_WR_GROUP2 : 1; - unsigned int RESET_WR_GROUP3 : 1; - unsigned int RESET_WR_GROUP4 : 1; - unsigned int RESET_WR_GROUP5 : 1; - unsigned int RESET_WR_GROUP6 : 1; - unsigned int RESET_WR_GROUP7 : 1; - unsigned int AGE_LOW_RATE_RD : 3; - unsigned int AGE_LOW_RATE_WR : 3; - unsigned int TIMER_STALL_RD__VI : 1; - unsigned int TIMER_STALL_WR__VI : 1; - unsigned int EXTEND_WEIGHT_RD__VI : 1; - unsigned int EXTEND_WEIGHT_WR__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_AGE_RD { - struct { - unsigned int RATE_GROUP0 : 2; - unsigned int RATE_GROUP1 : 2; - unsigned int RATE_GROUP2 : 2; - unsigned int RATE_GROUP3 : 2; - unsigned int RATE_GROUP4 : 2; - unsigned int RATE_GROUP5 : 2; - unsigned int RATE_GROUP6 : 2; - unsigned int RATE_GROUP7 : 2; - unsigned int ENABLE_GROUP0 : 1; - unsigned int ENABLE_GROUP1 : 1; - unsigned int ENABLE_GROUP2 : 1; - unsigned int ENABLE_GROUP3 : 1; - unsigned int ENABLE_GROUP4 : 1; - unsigned int ENABLE_GROUP5 : 1; - unsigned int ENABLE_GROUP6 : 1; - unsigned int ENABLE_GROUP7 : 1; - unsigned int DIVIDE_GROUP0 : 1; - unsigned int DIVIDE_GROUP1 : 1; - unsigned int DIVIDE_GROUP2 : 1; - unsigned int DIVIDE_GROUP3 : 1; - unsigned int DIVIDE_GROUP4 : 1; - unsigned int DIVIDE_GROUP5 : 1; - unsigned int DIVIDE_GROUP6 : 1; - unsigned int DIVIDE_GROUP7 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_AGE_WR { - struct { - unsigned int RATE_GROUP0 : 2; - unsigned int RATE_GROUP1 : 2; - unsigned int RATE_GROUP2 : 2; - unsigned int RATE_GROUP3 : 2; - unsigned int RATE_GROUP4 : 2; - unsigned int RATE_GROUP5 : 2; - unsigned int RATE_GROUP6 : 2; - unsigned int RATE_GROUP7 : 2; - unsigned int ENABLE_GROUP0 : 1; - unsigned int ENABLE_GROUP1 : 1; - unsigned int ENABLE_GROUP2 : 1; - unsigned int ENABLE_GROUP3 : 1; - unsigned int ENABLE_GROUP4 : 1; - unsigned int ENABLE_GROUP5 : 1; - unsigned int ENABLE_GROUP6 : 1; - unsigned int ENABLE_GROUP7 : 1; - unsigned int DIVIDE_GROUP0 : 1; - unsigned int DIVIDE_GROUP1 : 1; - unsigned int DIVIDE_GROUP2 : 1; - unsigned int DIVIDE_GROUP3 : 1; - unsigned int DIVIDE_GROUP4 : 1; - unsigned int DIVIDE_GROUP5 : 1; - unsigned int DIVIDE_GROUP6 : 1; - unsigned int DIVIDE_GROUP7 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_BANKMAP { - struct { - unsigned int BANK0 : 4; - unsigned int BANK1 : 4; - unsigned int BANK2 : 4; - unsigned int BANK3 : 4; - unsigned int RANK : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_BURST_TIME { - struct { - unsigned int STATE0 : 5; - unsigned int STATE1 : 5; - unsigned int STATE2 : 5; - unsigned int STATE3 : 5; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_BUSY_STATUS__CI { - struct { - unsigned int LM_RD0 : 1; - unsigned int LM_RD1 : 1; - unsigned int LM_WR0 : 1; - unsigned int LM_WR1 : 1; - unsigned int HM_RD0 : 1; - unsigned int HM_RD1 : 1; - unsigned int HM_WR0 : 1; - unsigned int HM_WR1 : 1; - unsigned int WDE_RD0 : 1; - unsigned int WDE_RD1 : 1; - unsigned int WDE_WR0 : 1; - unsigned int WDE_WR1 : 1; - unsigned int POP0 : 1; - unsigned int POP1 : 1; - unsigned int TAGFIFO0 : 1; - unsigned int TAGFIFO1 : 1; - unsigned int REPLAY0 : 1; - unsigned int REPLAY1 : 1; - unsigned int RDRET0 : 1; - unsigned int RDRET1 : 1; - unsigned int GECC2_RD0 : 1; - unsigned int GECC2_RD1 : 1; - unsigned int GECC2_WR0 : 1; - unsigned int GECC2_WR1 : 1; - unsigned int WCDR0 : 1; - unsigned int WCDR1 : 1; - unsigned int RTT0 : 1; - unsigned int RTT1 : 1; - unsigned int REM_RD0 : 1; - unsigned int REM_RD1 : 1; - unsigned int REM_WR0 : 1; - unsigned int REM_WR1 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_BUSY_STATUS__VI { - struct { - unsigned int LM_RD0 : 1; - unsigned int LM_RD1 : 1; - unsigned int LM_WR0 : 1; - unsigned int LM_WR1 : 1; - unsigned int HM_RD0 : 1; - unsigned int HM_RD1 : 1; - unsigned int HM_WR0 : 1; - unsigned int HM_WR1 : 1; - unsigned int WDE_RD0 : 1; - unsigned int WDE_RD1 : 1; - unsigned int WDE_WR0 : 1; - unsigned int WDE_WR1 : 1; - unsigned int POP0 : 1; - unsigned int POP1 : 1; - unsigned int TAGFIFO0 : 1; - unsigned int TAGFIFO1 : 1; - unsigned int REPLAY0 : 1; - unsigned int REPLAY1 : 1; - unsigned int RDRET0 : 1; - unsigned int RDRET1 : 1; - unsigned int GECC2_RD0 : 1; - unsigned int GECC2_RD1 : 1; - unsigned int GECC2_WR0 : 1; - unsigned int GECC2_WR1 : 1; - unsigned int WRRET0 : 1; - unsigned int WRRET1 : 1; - unsigned int RTT0 : 1; - unsigned int RTT1 : 1; - unsigned int REM_RD0 : 1; - unsigned int REM_RD1 : 1; - unsigned int REM_WR0 : 1; - unsigned int REM_WR1 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_CAC_CNTL { - struct { - unsigned int ENABLE : 1; - unsigned int READ_WEIGHT : 6; - unsigned int WRITE_WEIGHT : 6; - unsigned int ALLOW_OVERFLOW : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_CG__CI__VI { - struct { - unsigned int CG_ARB_REQ : 8; - unsigned int CG_ARB_RESP : 8; - unsigned int RSV_0 : 8; - unsigned int RSV_1 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_CG__SI { - struct { - unsigned int CG_ARB_REQ : 8; - unsigned int CG_ARB_RESP : 8; - unsigned int : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_DRAM_TIMING { - struct { - unsigned int ACTRD : 8; - unsigned int ACTWR : 8; - unsigned int RASMACTRD : 8; - unsigned int RASMACTWR : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_DRAM_TIMING2 { - struct { - unsigned int RAS2RAS : 8; - unsigned int RP : 8; - unsigned int WRPLUSRP : 8; - unsigned int BUS_TURN : 5; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_DRAM_TIMING2_1 { - struct { - unsigned int RAS2RAS : 8; - unsigned int RP : 8; - unsigned int WRPLUSRP : 8; - unsigned int BUS_TURN : 5; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_DRAM_TIMING_1 { - struct { - unsigned int ACTRD : 8; - unsigned int ACTWR : 8; - unsigned int RASMACTRD : 8; - unsigned int RASMACTWR : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_FED_CNTL { - struct { - unsigned int MODE : 2; - unsigned int WR_ERR : 2; - unsigned int KEEP_POISON_IN_PAGE : 1; - unsigned int RDRET_PARITY_NACK__CI__VI : 1; - unsigned int USE_LEGACY_NACK__CI__VI : 1; - unsigned int DEBUG_RSV__CI__VI : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GDEC_RD_CNTL { - struct { - unsigned int PAGEBIT0 : 4; - unsigned int PAGEBIT1 : 4; - unsigned int USE_RANK : 1; - unsigned int USE_RSNO : 1; - unsigned int REM_DEFAULT_GRP : 4; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GDEC_WR_CNTL { - struct { - unsigned int PAGEBIT0 : 4; - unsigned int PAGEBIT1 : 4; - unsigned int USE_RANK : 1; - unsigned int USE_RSNO : 1; - unsigned int REM_DEFAULT_GRP : 4; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GECC2 { - struct { - unsigned int ENABLE : 1; - unsigned int ECC_MODE : 2; - unsigned int PAGE_BIT0 : 2; - unsigned int EXOR_BANK_SEL : 2; - unsigned int NO_GECC_CLI : 4; - unsigned int READ_ERR : 3; - unsigned int CLOSE_BANK_RMW : 1; - unsigned int COLFIFO_WATER : 6; - unsigned int WRADDR_CONV__CI__VI : 1; - unsigned int RMWRD_UNCOR_POISON__CI__VI : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GECC2_CLI { - struct { - unsigned int NO_GECC_CLI0 : 8; - unsigned int NO_GECC_CLI1 : 8; - unsigned int NO_GECC_CLI2 : 8; - unsigned int NO_GECC_CLI3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GECC2_DEBUG { - struct { - unsigned int NUM_ERR_BITS : 2; - unsigned int DIRECTION : 1; - unsigned int DATA_FIELD : 2; - unsigned int SW_INJECTION : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GECC2_DEBUG2 { - struct { - unsigned int PERIOD : 8; - unsigned int ERR0_START : 8; - unsigned int ERR1_START : 8; - unsigned int ERR2_START : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GECC2_MISC__SI__CI { - struct { - unsigned int STREAK_BREAK : 4; - unsigned int COL10_HACK__CI : 1; - unsigned int CWRD_IN_REPLAY__CI : 1; - unsigned int NO_EOB_ALL_WR_IN_REPLAY__CI : 1; - unsigned int DEBUG_RSV__CI : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GECC2_MISC__VI { - struct { - unsigned int STREAK_BREAK : 4; - unsigned int COL10_HACK : 1; - unsigned int CWRD_IN_REPLAY : 1; - unsigned int NO_EOB_ALL_WR_IN_REPLAY : 1; - unsigned int RMW_LM_WR_STALL : 1; - unsigned int RMW_STALL_RELEASE : 1; - unsigned int WR_EDC_MASK_REPLAY : 1; - unsigned int CWRD_REPLAY_AGAIN : 1; - unsigned int WRRDWR_REPLAY_AGAIN : 1; - unsigned int ALLOW_RMW_ERR_AFTER_REPLAY : 1; - unsigned int DEBUG_RSV : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GECC2_STATUS { - struct { - unsigned int CORR_STS0 : 1; - unsigned int UNCORR_STS0 : 1; - unsigned int FED_STS0 : 1; - unsigned int RSVD0 : 1; - unsigned int CORR_STS1 : 1; - unsigned int UNCORR_STS1 : 1; - unsigned int FED_STS1 : 1; - unsigned int RSVD1 : 1; - unsigned int CORR_CLEAR0 : 1; - unsigned int UNCORR_CLEAR0 : 1; - unsigned int FED_CLEAR0 : 1; - unsigned int RSVD2 : 1; - unsigned int CORR_CLEAR1 : 1; - unsigned int UNCORR_CLEAR1 : 1; - unsigned int FED_CLEAR1 : 1; - unsigned int RSVD3__CI__VI : 1; - unsigned int RMWRD_CORR_STS0__CI__VI : 1; - unsigned int RMWRD_UNCORR_STS0__CI__VI : 1; - unsigned int RSVD4__CI__VI : 2; - unsigned int RMWRD_CORR_STS1__CI__VI : 1; - unsigned int RMWRD_UNCORR_STS1__CI__VI : 1; - unsigned int RSVD5__CI__VI : 2; - unsigned int RMWRD_CORR_CLEAR0__CI__VI : 1; - unsigned int RMWRD_UNCORR_CLEAR0__CI__VI : 1; - unsigned int RSVD6__CI__VI : 2; - unsigned int RMWRD_CORR_CLEAR1__CI__VI : 1; - unsigned int RMWRD_UNCORR_CLEAR1__CI__VI : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_BWCNT0_RD__CI__VI { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_BWCNT0_WR__CI__VI { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_BWCNT1_RD__CI__VI { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_BWCNT1_WR__CI__VI { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_BWPERIOD0_RD__CI__VI { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_BWPERIOD0_WR__CI__VI { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_BWPERIOD1_RD__CI__VI { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_BWPERIOD1_WR__CI__VI { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_CTL_RD__CI__VI { - struct { - unsigned int FORCE_HIGHEST : 8; - unsigned int HARSH_RR : 1; - unsigned int BANK_AGE_ONLY : 1; - unsigned int USE_LEGACY_HARSH : 1; - unsigned int BWCNT_CATCHUP : 1; - unsigned int ST_MODE : 2; - unsigned int FORCE_STALL : 8; - unsigned int PERF_MON_SEL : 3; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_CTL_WR__CI__VI { - struct { - unsigned int FORCE_HIGHEST : 8; - unsigned int HARSH_RR : 1; - unsigned int BANK_AGE_ONLY : 1; - unsigned int USE_LEGACY_HARSH : 1; - unsigned int BWCNT_CATCHUP : 1; - unsigned int ST_MODE : 2; - unsigned int FORCE_STALL : 8; - unsigned int PERF_MON_SEL : 3; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_EN_RD__CI__VI { - struct { - unsigned int TX_PRI : 8; - unsigned int BW_PRI : 8; - unsigned int FIX_PRI : 8; - unsigned int ST_PRI : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_EN_WR__CI__VI { - struct { - unsigned int TX_PRI : 8; - unsigned int BW_PRI : 8; - unsigned int FIX_PRI : 8; - unsigned int ST_PRI : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_SAT0_RD__CI__VI { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_SAT0_WR__CI__VI { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_SAT1_RD__CI__VI { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_SAT1_WR__CI__VI { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_TX_HI0_RD__CI__VI { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_TX_HI0_WR__CI__VI { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_TX_HI1_RD__CI__VI { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_TX_HI1_WR__CI__VI { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_TX_LO0_RD__CI__VI { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_TX_LO0_WR__CI__VI { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_TX_LO1_RD__CI__VI { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_HARSH_TX_LO1_WR__CI__VI { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_LAZY0_RD { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_LAZY0_WR { - struct { - unsigned int GROUP0 : 8; - unsigned int GROUP1 : 8; - unsigned int GROUP2 : 8; - unsigned int GROUP3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_LAZY1_RD { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_LAZY1_WR { - struct { - unsigned int GROUP4 : 8; - unsigned int GROUP5 : 8; - unsigned int GROUP6 : 8; - unsigned int GROUP7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_LM_RD { - struct { - unsigned int STREAK_LIMIT : 8; - unsigned int STREAK_LIMIT_UBER : 8; - unsigned int STREAK_BREAK : 1; - unsigned int STREAK_UBER : 1; - unsigned int ENABLE_TWO_LIST : 1; - unsigned int POPIDLE_RST_TWOLIST : 1; - unsigned int SKID1_RST_TWOLIST : 1; - unsigned int BANKGROUP_CONFIG : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_LM_WR { - struct { - unsigned int STREAK_LIMIT : 8; - unsigned int STREAK_LIMIT_UBER : 8; - unsigned int STREAK_BREAK : 1; - unsigned int STREAK_UBER : 1; - unsigned int ENABLE_TWO_LIST : 1; - unsigned int POPIDLE_RST_TWOLIST : 1; - unsigned int SKID1_RST_TWOLIST : 1; - unsigned int BANKGROUP_CONFIG : 3; - unsigned int MASKWR_LM_EOB__VI : 1; - unsigned int ATOMIC_LM_EOB__VI : 1; - unsigned int ATOMIC_RTN_LM_EOB__VI : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_MAX_LAT_CID__CI__VI { - struct { - unsigned int CID_CH0 : 8; - unsigned int CID_CH1 : 8; - unsigned int WRITE_CH0 : 1; - unsigned int WRITE_CH1 : 1; - unsigned int REALTIME_CH0 : 1; - unsigned int REALTIME_CH1 : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_MAX_LAT_RSLT0__CI__VI { - struct { - unsigned int MAX_LATENCY : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_MAX_LAT_RSLT1__CI__VI { - struct { - unsigned int MAX_LATENCY : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_MINCLKS { - struct { - unsigned int READ_CLKS : 8; - unsigned int WRITE_CLKS : 8; - unsigned int ARB_RW_SWITCH : 1; - unsigned int RW_SWITCH_HARSH__CI__VI : 2; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_MISC { - struct { - unsigned int STICKY_RFSH : 1; - unsigned int IDLE_RFSH : 1; - unsigned int STUTTER_RFSH : 1; - unsigned int CHAN_COUPLE : 8; - unsigned int HARSHNESS : 8; - unsigned int SMART_RDWR_SW : 1; - unsigned int CALI_ENABLE : 1; - unsigned int CALI_RATES : 2; - unsigned int DISPURGVLD_NOWRT : 1; - unsigned int DISPURG_NOSW2WR : 1; - unsigned int DISPURG_STALL : 1; - unsigned int DISPURG_THROTTLE : 4; - unsigned int EXTEND_WEIGHT__CI__VI : 1; - unsigned int ACPURG_STALL__CI__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_MISC2 { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int TCCDL4_BANKBIT3_XOR_ENABLE : 1; - unsigned int TCCDL4_BANKBIT3_XOR_COLBIT4 : 1; - unsigned int TCCDL4_BANKBIT3_XOR_COLBIT5 : 1; - unsigned int TCCDL4_BANKBIT3_XOR_COLBIT6 : 1; - unsigned int TCCDL4_BANKBIT3_XOR_COLBIT7 : 1; - unsigned int TCCDL4_BANKBIT3_XOR_COLBIT8 : 1; - unsigned int POP_IDLE_REPLAY : 1; - unsigned int RDRET_NO_REORDERING : 1; - unsigned int RDRET_NO_BP : 1; - unsigned int RDRET_SEQ_SKID : 4; - unsigned int GECC : 1; - unsigned int GECC_RST : 1; - unsigned int GECC_STATUS : 1; - unsigned int TAGFIFO_THRESHOLD : 4; - unsigned int WCDR_REPLAY_MASKCNT : 3; - unsigned int REPLAY_DEBUG : 1; - unsigned int ARB_DEBUG29 : 1; - unsigned int SEQ_RDY_POP_IDLE : 1; - unsigned int TCCDL4_REPLAY_EOB : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_MISC3__CI { - struct { - unsigned int NO_GECC_EXT_EOB : 1; - unsigned int TBD_FIELD : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_MISC3__VI { - struct { - unsigned int NO_GECC_EXT_EOB : 1; - unsigned int CHAN4_EN : 1; - unsigned int CHAN4_ARB_SEL : 1; - unsigned int UVD_URG_MODE : 1; - unsigned int UVD_DMIF_HARSH_WT_EN : 1; - unsigned int TBD_FIELD : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PERFCOUNTER0_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PERFCOUNTER1_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PERFCOUNTER2_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PERFCOUNTER3_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PERFCOUNTER_HI__CI__VI { - struct { - unsigned int COUNTER_HI : 16; - unsigned int COMPARE_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PERFCOUNTER_LO__CI__VI { - struct { - unsigned int COUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PERFCOUNTER_RSLT_CNTL__CI__VI { - struct { - unsigned int PERF_COUNTER_SELECT : 4; - unsigned int : 4; - unsigned int START_TRIGGER : 8; - unsigned int STOP_TRIGGER : 8; - unsigned int ENABLE_ANY : 1; - unsigned int CLEAR_ALL : 1; - unsigned int STOP_ALL_ON_SATURATE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PERF_MON_CNTL0_ECC__CI { - struct { - unsigned int ALLOW_WRAP : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PERF_MON_CNTL0__SI { - struct { - unsigned int : 12; - unsigned int : 12; - unsigned int : 2; - unsigned int : 2; - unsigned int : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PM_CNTL__CI { - struct { - unsigned int OVERRIDE_CGSTATE : 2; - unsigned int OVRR_CGRFSH : 1; - unsigned int OVRR_CGSQM : 1; - unsigned int SRFSH_ON_D1 : 1; - unsigned int BLKOUT_ON_D1 : 1; - unsigned int IDLE_ON_D1 : 1; - unsigned int OVRR_PM : 1; - unsigned int OVRR_PM_STATE : 2; - unsigned int OVRR_RD : 1; - unsigned int OVRR_RD_STATE : 1; - unsigned int OVRR_WR : 1; - unsigned int OVRR_WR_STATE : 1; - unsigned int OVRR_RFSH : 1; - unsigned int OVRR_RFSH_STATE : 1; - unsigned int RSV_0 : 2; - unsigned int IDLE_ON_D2 : 1; - unsigned int IDLE_ON_D3 : 1; - unsigned int IDLE_CNT : 4; - unsigned int RSV_1 : 1; - unsigned int RSV_2 : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PM_CNTL__VI { - struct { - unsigned int OVERRIDE_CGSTATE : 2; - unsigned int OVRR_CGRFSH : 1; - unsigned int OVRR_CGSQM : 1; - unsigned int SRFSH_ON_D1 : 1; - unsigned int BLKOUT_ON_D1 : 1; - unsigned int IDLE_ON_D1 : 1; - unsigned int OVRR_PM : 1; - unsigned int OVRR_PM_STATE : 2; - unsigned int OVRR_RD : 1; - unsigned int OVRR_RD_STATE : 1; - unsigned int OVRR_WR : 1; - unsigned int OVRR_WR_STATE : 1; - unsigned int OVRR_RFSH : 1; - unsigned int OVRR_RFSH_STATE : 1; - unsigned int OVRR_RD0_BUSY : 1; - unsigned int OVRR_RD1_BUSY : 1; - unsigned int IDLE_ON_D2 : 1; - unsigned int IDLE_ON_D3 : 1; - unsigned int IDLE_CNT : 4; - unsigned int OVRR_WR0_BUSY : 1; - unsigned int OVRR_WR1_BUSY : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PM_CNTL__SI { - struct { - unsigned int OVERRIDE_CGSTATE : 2; - unsigned int OVRR_CGRFSH : 1; - unsigned int OVRR_CGSQM : 1; - unsigned int SRFSH_ON_D1 : 1; - unsigned int BLKOUT_ON_D1 : 1; - unsigned int IDLE_ON_D1 : 1; - unsigned int OVRR_PM : 1; - unsigned int OVRR_PM_STATE : 2; - unsigned int OVRR_RD : 1; - unsigned int OVRR_RD_STATE : 1; - unsigned int OVRR_WR : 1; - unsigned int OVRR_WR_STATE : 1; - unsigned int OVRR_RFSH : 1; - unsigned int OVRR_RFSH_STATE : 1; - unsigned int : 2; - unsigned int IDLE_ON_D2 : 1; - unsigned int IDLE_ON_D3 : 1; - unsigned int IDLE_CNT : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_POP { - struct { - unsigned int ENABLE_ARB : 1; - unsigned int SPEC_OPEN : 1; - unsigned int POP_DEPTH : 4; - unsigned int WRDATAINDEX_DEPTH : 6; - unsigned int SKID_DEPTH : 3; - unsigned int WAIT_AFTER_RFSH : 2; - unsigned int QUICK_STOP : 1; - unsigned int ENABLE_TWO_PAGE : 1; - unsigned int ALLOW_EOB_BY_WRRET_STALL : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RAMCFG__CI__VI { - struct { - unsigned int NOOFBANK : 2; - unsigned int NOOFRANKS : 1; - unsigned int NOOFROWS : 3; - unsigned int NOOFCOLS : 2; - unsigned int CHANSIZE : 1; - unsigned int RSV_1 : 1; - unsigned int RSV_2 : 1; - unsigned int RSV_3 : 1; - unsigned int NOOFGROUPS : 1; - unsigned int RSV_4 : 5; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RAMCFG__SI { - struct { - unsigned int NOOFBANK : 2; - unsigned int NOOFRANKS : 1; - unsigned int NOOFROWS : 3; - unsigned int NOOFCOLS : 2; - unsigned int CHANSIZE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int NOOFGROUPS : 1; - unsigned int : 5; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_REMREQ { - struct { - unsigned int RD_WATER : 8; - unsigned int WR_WATER : 8; - unsigned int WR_MAXBURST_SIZE : 4; - unsigned int WR_LAZY_TIMER : 4; - unsigned int ENABLE_REMOTE_NACK_REQ__VI : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_REPLAY { - struct { - unsigned int ENABLE_RD : 1; - unsigned int ENABLE_WR : 1; - unsigned int WRACK_MODE : 1; - unsigned int WAW_ENABLE : 1; - unsigned int RAW_ENABLE : 1; - unsigned int IGNORE_WR_CDC : 1; - unsigned int BREAK_ON_STALL : 1; - unsigned int BOS_ENABLE_WAIT_CYC : 1; - unsigned int BOS_WAIT_CYC : 7; - unsigned int NO_PCH_AT_REPLAY_START__CI__VI : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RET_CREDITS2__CI__VI { - struct { - unsigned int ACP_WR : 8; - unsigned int NECKDOWN_CNTR_EN_RD__VI : 1; - unsigned int NECKDOWN_CNTR_EN_WR__VI : 1; - unsigned int ACP_RDRET_URG__VI : 1; - unsigned int HDP_RDRET_URG__VI : 1; - unsigned int NECKDOWN_CNTR_MONITOR_RD__VI : 1; - unsigned int NECKDOWN_CNTR_MONITOR_WR__VI : 1; - unsigned int DISABLE_DISP_RDY_RD__VI : 1; - unsigned int DISABLE_ACP_RDY_WR__VI : 1; - unsigned int RDRET_CREDIT_MED__VI : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RET_CREDITS_RD { - struct { - unsigned int LCL : 8; - unsigned int HUB : 8; - unsigned int DISP : 8; - unsigned int RETURN_CREDIT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RET_CREDITS_WR { - struct { - unsigned int LCL : 8; - unsigned int HUB : 8; - unsigned int RETURN_CREDIT : 8; - unsigned int WRRET_SEQ_SKID : 4; - unsigned int WRRET_BP__VI : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RFSH_CNTL { - struct { - unsigned int ENABLE : 1; - unsigned int URG0 : 5; - unsigned int URG1 : 5; - unsigned int ACCUM : 1; - unsigned int SINGLE_BANK__VI : 1; - unsigned int PUSH_SINGLE_BANK_REFRESH__VI : 1; - unsigned int PENDING_RATE_SEL__VI : 3; - unsigned int REFSB_PER_PAGE__VI : 1; - unsigned int : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RFSH_RATE { - struct { - unsigned int POWERMODE0 : 8; - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RTT_CNTL0 { - struct { - unsigned int ENABLE : 1; - unsigned int START_IDLE : 1; - unsigned int START_R2W : 2; - unsigned int FLUSH_ON_ENTER : 1; - unsigned int HARSH_START : 1; - unsigned int TPS_HARSH_PRIORITY : 1; - unsigned int TWRT_HARSH_PRIORITY : 1; - unsigned int BREAK_ON_HARSH : 1; - unsigned int BREAK_ON_URGENTRD : 1; - unsigned int BREAK_ON_URGENTWR : 1; - unsigned int TRAIN_PERIOD : 3; - unsigned int START_R2W_RFSH : 1; - unsigned int DEBUG_RSV_0 : 1; - unsigned int DEBUG_RSV_1 : 1; - unsigned int DEBUG_RSV_2 : 1; - unsigned int DEBUG_RSV_3 : 1; - unsigned int DEBUG_RSV_4 : 1; - unsigned int DEBUG_RSV_5 : 1; - unsigned int DEBUG_RSV_6 : 1; - unsigned int DEBUG_RSV_7 : 1; - unsigned int DEBUG_RSV_8 : 1; - unsigned int DATA_CNTL : 1; - unsigned int NEIGHBOR_BIT : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RTT_CNTL1 { - struct { - unsigned int WINDOW_SIZE : 5; - unsigned int WINDOW_UPDATE : 1; - unsigned int WINDOW_INC_THRESHOLD : 7; - unsigned int WINDOW_DEC_THRESHOLD : 7; - unsigned int WINDOW_SIZE_MAX : 5; - unsigned int WINDOW_SIZE_MIN : 5; - unsigned int WINDOW_UPDATE_COUNT : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RTT_CNTL2 { - struct { - unsigned int SAMPLE_CNT : 6; - unsigned int PHASE_ADJUST_THRESHOLD : 6; - unsigned int PHASE_ADJUST_SIZE : 1; - unsigned int FILTER_CNTL : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RTT_DATA { - struct { - unsigned int PATTERN : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_RTT_DEBUG { - struct { - unsigned int DEBUG_BYTE_CH0 : 2; - unsigned int DEBUG_BYTE_CH1 : 2; - unsigned int SHIFTED_PHASE_CH0 : 8; - unsigned int WINDOW_SIZE_CH0 : 5; - unsigned int SHIFTED_PHASE_CH1 : 8; - unsigned int WINDOW_SIZE_CH1 : 5; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_SQM_CNTL__CI__VI { - struct { - unsigned int MIN_PENAL : 8; - unsigned int DYN_SQM_ENABLE : 1; - unsigned int SQM_RDY16 : 1; - unsigned int SQM_RESERVE : 6; - unsigned int RATIO : 8; - unsigned int RATIO_DEBUG : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_SQM_CNTL__SI { - struct { - unsigned int MIN_PENAL : 8; - unsigned int DYN_SQM_ENABLE : 1; - unsigned int SQM_RESERVE : 7; - unsigned int RATIO : 8; - unsigned int RATIO_DEBUG : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_SSM__CI { - struct { - unsigned int FORMAT : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_TM_CNTL_RD { - struct { - unsigned int GROUPBY_RANK : 1; - unsigned int BANK_SELECT : 2; - unsigned int MATCH_RANK : 1; - unsigned int MATCH_BANK : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_TM_CNTL_WR { - struct { - unsigned int GROUPBY_RANK : 1; - unsigned int BANK_SELECT : 2; - unsigned int MATCH_RANK : 1; - unsigned int MATCH_BANK : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_WCDR__SI__CI { - struct { - unsigned int IDLE_ENABLE : 1; - unsigned int SEQ_IDLE : 1; - unsigned int IDLE_PERIOD : 5; - unsigned int IDLE_BURST : 6; - unsigned int IDLE_BURST_MODE : 1; - unsigned int IDLE_WAKEUP : 2; - unsigned int IDLE_DEGLITCH_ENABLE : 1; - unsigned int WPRE_ENABLE : 1; - unsigned int WPRE_THRESHOLD : 4; - unsigned int WPRE_MAX_BURST : 3; - unsigned int WPRE_INC_READ : 1; - unsigned int WPRE_INC_SKIDIDLE : 1; - unsigned int WPRE_INC_SEQIDLE : 1; - unsigned int WPRE_TWOPAGE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_WCDR_2__SI__CI { - struct { - unsigned int WPRE_INC_STEP : 4; - unsigned int WPRE_MIN_THRESHOLD : 5; - unsigned int DEBUG_0 : 1; - unsigned int DEBUG_1 : 1; - unsigned int DEBUG_2 : 1; - unsigned int DEBUG_3 : 1; - unsigned int DEBUG_4 : 1; - unsigned int DEBUG_5 : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_WTM_CNTL_RD { - struct { - unsigned int WTMODE : 2; - unsigned int HARSH_PRI : 1; - unsigned int ALLOW_STUTTER_GRP0 : 1; - unsigned int ALLOW_STUTTER_GRP1 : 1; - unsigned int ALLOW_STUTTER_GRP2 : 1; - unsigned int ALLOW_STUTTER_GRP3 : 1; - unsigned int ALLOW_STUTTER_GRP4 : 1; - unsigned int ALLOW_STUTTER_GRP5 : 1; - unsigned int ALLOW_STUTTER_GRP6 : 1; - unsigned int ALLOW_STUTTER_GRP7 : 1; - unsigned int ACP_HARSH_PRI__CI__VI : 1; - unsigned int ACP_OVER_DISP__CI__VI : 1; - unsigned int FORCE_ACP_URG__CI__VI : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_WTM_CNTL_WR { - struct { - unsigned int WTMODE : 2; - unsigned int HARSH_PRI : 1; - unsigned int ALLOW_STUTTER_GRP0 : 1; - unsigned int ALLOW_STUTTER_GRP1 : 1; - unsigned int ALLOW_STUTTER_GRP2 : 1; - unsigned int ALLOW_STUTTER_GRP3 : 1; - unsigned int ALLOW_STUTTER_GRP4 : 1; - unsigned int ALLOW_STUTTER_GRP5 : 1; - unsigned int ALLOW_STUTTER_GRP6 : 1; - unsigned int ALLOW_STUTTER_GRP7 : 1; - unsigned int ACP_HARSH_PRI__CI__VI : 1; - unsigned int ACP_OVER_DISP__CI__VI : 1; - unsigned int FORCE_ACP_URG__CI__VI : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_WTM_GRPWT_RD { - struct { - unsigned int GRP0 : 2; - unsigned int GRP1 : 2; - unsigned int GRP2 : 2; - unsigned int GRP3 : 2; - unsigned int GRP4 : 2; - unsigned int GRP5 : 2; - unsigned int GRP6 : 2; - unsigned int GRP7 : 2; - unsigned int GRP_EXT : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_WTM_GRPWT_WR { - struct { - unsigned int GRP0 : 2; - unsigned int GRP1 : 2; - unsigned int GRP2 : 2; - unsigned int GRP3 : 2; - unsigned int GRP4 : 2; - unsigned int GRP5 : 2; - unsigned int GRP6 : 2; - unsigned int GRP7 : 2; - unsigned int GRP_EXT : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_AUTO_CNTL__SI__CI { - struct { - unsigned int MOP : 2; - unsigned int : 2; - unsigned int ADR_GEN : 4; - unsigned int LFSR_KEY : 16; - unsigned int LFSR_RESET : 1; - unsigned int ADR_RESET : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_CMD_CNTL__SI__CI { - struct { - unsigned int RESET : 1; - unsigned int CMD_ISSUE_MODE : 1; - unsigned int CMD_ISSUE_LOOP : 1; - unsigned int LOOP_END_CONDITION : 1; - unsigned int LOOP_CNT_MAX : 12; - unsigned int CMD_ISSUE_MODE_U : 1; - unsigned int CMD_ISSUE_RUN : 1; - unsigned int LOOP_CNT_RD : 10; - unsigned int ENABLE_D0 : 1; - unsigned int ENABLE_D1 : 1; - unsigned int STATUS_CH : 1; - unsigned int DONE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_CMP_CNTL__SI__CI { - struct { - unsigned int CMP_MASK_BYTE : 4; - unsigned int CMP_MASK_BIT : 8; - unsigned int LOAD_RTEDC : 1; - unsigned int DATA_STORE_SEL : 1; - unsigned int EDC_STORE_SEL : 1; - unsigned int ENABLE_CMD_FIFO : 1; - unsigned int CMP : 2; - unsigned int DAT_MODE : 1; - unsigned int EDC_STORE_MODE : 1; - unsigned int DATA_STORE_MODE : 2; - unsigned int MISMATCH_CNT : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_CMP_CNTL_2__SI__CI { - struct { - unsigned int DATA_STORE_CNT : 5; - unsigned int : 3; - unsigned int DATA_STORE_CNT_RST : 1; - unsigned int : 3; - unsigned int EDC_STORE_CNT : 5; - unsigned int : 3; - unsigned int EDC_STORE_CNT_RST : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_CNTL__SI__CI { - struct { - unsigned int RESET : 1; - unsigned int RUN : 1; - unsigned int PTR_RST_D0 : 1; - unsigned int PTR_RST_D1 : 1; - unsigned int MOP_MODE : 1; - unsigned int ADR_MODE : 1; - unsigned int DAT_MODE : 1; - unsigned int : 3; - unsigned int LOOP : 2; - unsigned int ENABLE_D0 : 1; - unsigned int ENABLE_D1 : 1; - unsigned int LOAD_RTDATA_CH : 1; - unsigned int : 1; - unsigned int LOOP_CNT : 12; - unsigned int : 2; - unsigned int DONE : 1; - unsigned int LOAD_RTDATA : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_CNTL__VI { - struct { - unsigned int RESET : 1; - unsigned int RUN : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int LOOP_CNT : 12; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_DATA_MASK__SI__CI { - struct { - unsigned int MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_DATA_WORD0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_DATA_WORD1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_DATA_WORD2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_DATA_WORD3 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_DATA_WORD4 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_DATA_WORD5 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_DATA_WORD6 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_DATA_WORD7 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_DIR_CNTL__SI__CI { - struct { - unsigned int MOP : 3; - unsigned int EOB : 1; - unsigned int MOP_LOAD : 1; - unsigned int DATA_LOAD : 1; - unsigned int CMD_RTR_D0 : 1; - unsigned int DAT_RTR_D0 : 1; - unsigned int CMD_RTR_D1 : 1; - unsigned int DAT_RTR_D1 : 1; - unsigned int MOP3 : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_EADDR__SI__CI { - struct { - unsigned int COL : 10; - unsigned int ROW : 14; - unsigned int BANK : 4; - unsigned int RANK : 1; - unsigned int COLH : 1; - unsigned int ROWH : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_MISMATCH_ADDR__SI__CI { - struct { - unsigned int COL : 10; - unsigned int ROW : 14; - unsigned int BANK : 4; - unsigned int RANK : 1; - unsigned int COLH : 1; - unsigned int ROWH : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_MISMATCH_ADDR__VI { - struct { - unsigned int COL : 8; - unsigned int ROW : 16; - unsigned int BANK : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_RDATA_EDC__SI__CI { - struct { - unsigned int EDC : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_RDATA_MASK__SI__CI { - struct { - unsigned int MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_RDATA_WORD0 { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_RDATA_WORD1 { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_RDATA_WORD2 { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_RDATA_WORD3 { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_RDATA_WORD4 { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_RDATA_WORD5 { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_RDATA_WORD6 { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_RDATA_WORD7 { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_SADDR__SI__CI { - struct { - unsigned int COL : 10; - unsigned int ROW : 14; - unsigned int BANK : 4; - unsigned int RANK : 1; - unsigned int COLH : 1; - unsigned int ROWH : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CG_CONFIG { - struct { - unsigned int MCDW_WR_ENABLE : 1; - unsigned int MCDX_WR_ENABLE : 1; - unsigned int MCDY_WR_ENABLE : 1; - unsigned int MCDZ_WR_ENABLE : 1; - unsigned int MC_RD_ENABLE : 2; - unsigned int INDEX : 16; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CG_CONFIG_MCD { - struct { - unsigned int MCD0_WR_ENABLE : 1; - unsigned int MCD1_WR_ENABLE : 1; - unsigned int MCD2_WR_ENABLE : 1; - unsigned int MCD3_WR_ENABLE : 1; - unsigned int MCD4_WR_ENABLE : 1; - unsigned int MCD5_WR_ENABLE : 1; - unsigned int MCD6_WR_ENABLE__VI : 1; - unsigned int MCD7_WR_ENABLE__VI : 1; - unsigned int MC_RD_ENABLE : 3; - unsigned int MC_RD_ENABLE_SUB__VI : 1; - unsigned int : 1; - unsigned int INDEX : 16; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CG_DATAPORT { - struct { - unsigned int DATA_FIELD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_CNTL__CI { - struct { - unsigned int : 2; - unsigned int IGNOREPM : 1; - unsigned int EXEMPTPM : 1; - unsigned int GFX_IDLE_OVERRIDE : 2; - unsigned int MCD_SRBM_MASK_ENABLE : 1; - unsigned int CNTR_CHMAP_MODE : 1; - unsigned int REMOTE_RB_CONNECT_ENABLE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_CNTL__VI { - struct { - unsigned int : 2; - unsigned int IGNOREPM : 1; - unsigned int EXEMPTPM : 1; - unsigned int GFX_IDLE_OVERRIDE : 2; - unsigned int MCD_SRBM_MASK_ENABLE : 1; - unsigned int CNTR_CHMAP_MODE : 2; - unsigned int REMOTE_RB_CONNECT_ENABLE : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_CNTL__SI { - struct { - unsigned int : 2; - unsigned int IGNOREPM : 1; - unsigned int EXEMPTPM : 1; - unsigned int GFX_IDLE_OVERRIDE : 2; - unsigned int MCD_SRBM_MASK_ENABLE : 1; - unsigned int : 7; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_CREDITS_ARB_RD { - struct { - unsigned int READ_LCL : 8; - unsigned int READ_HUB : 8; - unsigned int READ_PRI : 8; - unsigned int LCL_PRI : 1; - unsigned int HUB_PRI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_CREDITS_ARB_WR__SI__CI { - struct { - unsigned int WRITE_LCL : 8; - unsigned int WRITE_HUB : 8; - unsigned int HUB_PRI : 1; - unsigned int LCL_PRI__CI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_CREDITS_ARB_WR__VI { - struct { - unsigned int WRITE_LCL : 8; - unsigned int WRITE_HUB : 8; - unsigned int WRITE_PRI : 8; - unsigned int HUB_PRI : 1; - unsigned int LCL_PRI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_CREDITS_VM { - struct { - unsigned int READ_ALL : 6; - unsigned int WRITE_ALL : 6; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_CREDITS_XBAR { - struct { - unsigned int READ_LCL : 8; - unsigned int WRITE_LCL : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_DAGB_CNTL { - struct { - unsigned int JUMP_AHEAD : 1; - unsigned int CENTER_RD_MAX_BURST : 4; - unsigned int DISABLE_SELF_INIT : 1; - unsigned int CENTER_WR_MAX_BURST__CI__VI : 4; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_DAGB_DLY { - struct { - unsigned int DLY : 6; - unsigned int : 10; - unsigned int CLI : 6; - unsigned int : 2; - unsigned int POS : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_INT_CREDITS { - struct { - unsigned int REMRDRET : 6; - unsigned int : 6; - unsigned int CNTR_RD_HUB_LP : 6; - unsigned int CNTR_RD_HUB_HP : 6; - unsigned int CNTR_RD_LCL : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_INT_CREDITS_WR__CI__VI { - struct { - unsigned int CNTR_WR_HUB : 6; - unsigned int CNTR_WR_LCL : 6; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_MISC_RD_CG { - struct { - unsigned int ONDLY : 6; - unsigned int OFFDLY : 6; - unsigned int RDYDLY : 6; - unsigned int ENABLE : 1; - unsigned int MEM_LS_ENABLE : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_MISC_VM_CG { - struct { - unsigned int ONDLY : 6; - unsigned int OFFDLY : 6; - unsigned int RDYDLY : 6; - unsigned int ENABLE : 1; - unsigned int MEM_LS_ENABLE : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_MISC_WR_CG { - struct { - unsigned int ONDLY : 6; - unsigned int OFFDLY : 6; - unsigned int RDYDLY : 6; - unsigned int ENABLE : 1; - unsigned int MEM_LS_ENABLE : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_PERFCOUNTER0_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_PERFCOUNTER1_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_PERFCOUNTER2_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_PERFCOUNTER3_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_PERFCOUNTER_HI__CI__VI { - struct { - unsigned int COUNTER_HI : 16; - unsigned int COMPARE_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_PERFCOUNTER_LO__CI__VI { - struct { - unsigned int COUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_PERFCOUNTER_RSLT_CNTL__CI__VI { - struct { - unsigned int PERF_COUNTER_SELECT : 4; - unsigned int : 4; - unsigned int START_TRIGGER : 8; - unsigned int STOP_TRIGGER : 8; - unsigned int ENABLE_ANY : 1; - unsigned int CLEAR_ALL : 1; - unsigned int STOP_ALL_ON_SATURATE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_PERF_MON_CNTL2 { - struct { - unsigned int CID : 9; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_PERF_MON_RSLT2__SI__CI { - struct { - unsigned int : 6; - unsigned int CB_RD_BUSY : 1; - unsigned int DB_RD_BUSY : 1; - unsigned int TC0_RD_BUSY : 1; - unsigned int VC0_RD_BUSY : 1; - unsigned int TC1_RD_BUSY : 1; - unsigned int VC1_RD_BUSY : 1; - unsigned int CB_WR_BUSY : 1; - unsigned int DB_WR_BUSY : 1; - unsigned int SX_WR_BUSY : 1; - unsigned int TC2_RD_BUSY : 1; - unsigned int TC0_WR_BUSY : 1; - unsigned int TC1_WR_BUSY : 1; - unsigned int TC2_WR_BUSY : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_PERF_MON_RSLT2__VI { - struct { - unsigned int : 1; - unsigned int CB_RD_BUSY : 1; - unsigned int DB_RD_BUSY : 1; - unsigned int TC0_RD_BUSY : 1; - unsigned int VC0_RD_BUSY : 1; - unsigned int TC1_RD_BUSY : 1; - unsigned int VC1_RD_BUSY : 1; - unsigned int CB_WR_BUSY : 1; - unsigned int DB_WR_BUSY : 1; - unsigned int SX_WR_BUSY : 1; - unsigned int TC2_RD_BUSY : 1; - unsigned int TC0_WR_BUSY : 1; - unsigned int TC1_WR_BUSY : 1; - unsigned int TC2_WR_BUSY : 1; - unsigned int TC0_ATOM_BUSY : 1; - unsigned int TC1_ATOM_BUSY : 1; - unsigned int TC2_ATOM_BUSY : 1; - unsigned int CB_ATOM_BUSY : 1; - unsigned int DB_ATOM_BUSY : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_REMREQ { - struct { - unsigned int READ_CREDITS : 7; - unsigned int WRITE_CREDITS : 7; - unsigned int CREDITS_ENABLE : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_RET_MODE { - struct { - unsigned int INORDER_RD : 1; - unsigned int INORDER_WR : 1; - unsigned int REMPRI_RD : 1; - unsigned int REMPRI_WR : 1; - unsigned int LCLPRI_RD : 1; - unsigned int LCLPRI_WR : 1; - unsigned int RDRET_STALL_EN__VI : 1; - unsigned int RDRET_STALL_THRESHOLD__VI : 8; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_WTM_RD_CNTL__CI__VI { - struct { - unsigned int GROUP0_DECREMENT : 3; - unsigned int GROUP1_DECREMENT : 3; - unsigned int GROUP2_DECREMENT : 3; - unsigned int GROUP3_DECREMENT : 3; - unsigned int GROUP4_DECREMENT : 3; - unsigned int GROUP5_DECREMENT : 3; - unsigned int GROUP6_DECREMENT : 3; - unsigned int GROUP7_DECREMENT : 3; - unsigned int DISABLE_REMOTE : 1; - unsigned int DISABLE_LOCAL : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_WTM_RD_CNTL__SI { - struct { - unsigned int GROUP0_DECREMENT : 3; - unsigned int GROUP1_DECREMENT : 3; - unsigned int GROUP2_DECREMENT : 3; - unsigned int GROUP3_DECREMENT : 3; - unsigned int GROUP4_DECREMENT : 3; - unsigned int GROUP5_DECREMENT : 3; - unsigned int GROUP6_DECREMENT : 3; - unsigned int GROUP7_DECREMENT : 3; - unsigned int DISABLE_REMOTE : 1; - unsigned int : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_WTM_WR_CNTL__CI__VI { - struct { - unsigned int GROUP0_DECREMENT : 3; - unsigned int GROUP1_DECREMENT : 3; - unsigned int GROUP2_DECREMENT : 3; - unsigned int GROUP3_DECREMENT : 3; - unsigned int GROUP4_DECREMENT : 3; - unsigned int GROUP5_DECREMENT : 3; - unsigned int GROUP6_DECREMENT : 3; - unsigned int GROUP7_DECREMENT : 3; - unsigned int DISABLE_REMOTE : 1; - unsigned int DISABLE_LOCAL : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_WTM_WR_CNTL__SI { - struct { - unsigned int GROUP0_DECREMENT : 3; - unsigned int GROUP1_DECREMENT : 3; - unsigned int GROUP2_DECREMENT : 3; - unsigned int GROUP3_DECREMENT : 3; - unsigned int GROUP4_DECREMENT : 3; - unsigned int GROUP5_DECREMENT : 3; - unsigned int GROUP6_DECREMENT : 3; - unsigned int GROUP7_DECREMENT : 3; - unsigned int DISABLE_REMOTE : 1; - unsigned int : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_XTRA_ENABLE { - struct { - unsigned int CB1_RD : 1; - unsigned int CB1_WR : 1; - unsigned int DB1_RD : 1; - unsigned int DB1_WR : 1; - unsigned int TC2_RD : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int ARB_DBG : 4; - unsigned int TC2_WR : 1; - unsigned int CB0_CONNECT_CNTL__CI__VI : 2; - unsigned int DB0_CONNECT_CNTL__CI__VI : 2; - unsigned int CB1_CONNECT_CNTL__CI__VI : 2; - unsigned int DB1_CONNECT_CNTL__CI__VI : 2; - unsigned int TC0_CONNECT_CNTL__CI__VI : 2; - unsigned int TC1_CONNECT_CNTL__CI__VI : 2; - unsigned int CB0_CID_CNTL_ENABLE__CI__VI : 1; - unsigned int DB0_CID_CNTL_ENABLE__CI__VI : 1; - unsigned int CB1_CID_CNTL_ENABLE__CI__VI : 1; - unsigned int DB1_CID_CNTL_ENABLE__CI__VI : 1; - unsigned int TC2_REPAIR_ENABLE__CI__VI : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CONFIG__SI__CI { - struct { - unsigned int MCDW_WR_ENABLE : 1; - unsigned int MCDX_WR_ENABLE : 1; - unsigned int MCDY_WR_ENABLE : 1; - unsigned int MCDZ_WR_ENABLE : 1; - unsigned int MC_RD_ENABLE : 2; - unsigned int : 25; - unsigned int MCC_INDEX_MODE_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CONFIG__VI { - struct { - unsigned int MCDW_WR_ENABLE : 1; - unsigned int MCDX_WR_ENABLE : 1; - unsigned int MCDY_WR_ENABLE : 1; - unsigned int MCDZ_WR_ENABLE : 1; - unsigned int MCDS_WR_ENABLE : 1; - unsigned int MCDT_WR_ENABLE : 1; - unsigned int MCDU_WR_ENABLE : 1; - unsigned int MCDV_WR_ENABLE : 1; - unsigned int MC_RD_ENABLE : 3; - unsigned int : 20; - unsigned int MCC_INDEX_MODE_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CONFIG_MCD { - struct { - unsigned int MCD0_WR_ENABLE : 1; - unsigned int MCD1_WR_ENABLE : 1; - unsigned int MCD2_WR_ENABLE : 1; - unsigned int MCD3_WR_ENABLE : 1; - unsigned int MCD4_WR_ENABLE : 1; - unsigned int MCD5_WR_ENABLE : 1; - unsigned int MCD6_WR_ENABLE__VI : 1; - unsigned int MCD7_WR_ENABLE__VI : 1; - unsigned int MC_RD_ENABLE : 3; - unsigned int MC_RD_ENABLE_SUB__VI : 1; - unsigned int ARB0_WR_ENABLE__VI : 1; - unsigned int ARB1_WR_ENABLE__VI : 1; - unsigned int : 17; - unsigned int MCD_INDEX_MODE_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DC_INTERFACE_NACK_STATUS__SI__VI { - struct { - unsigned int DMIF_RDRET_NACK_OCCURRED : 1; - unsigned int : 3; - unsigned int DMIF_RDRET_NACK_CLEAR : 1; - unsigned int : 3; - unsigned int VIP_WRRET_NACK_OCCURRED : 1; - unsigned int : 3; - unsigned int VIP_WRRET_NACK_CLEAR : 1; - unsigned int : 3; - unsigned int MCIF_RDRET_NACK_OCCURRED : 1; - unsigned int : 3; - unsigned int MCIF_RDRET_NACK_CLEAR : 1; - unsigned int : 3; - unsigned int MCIF_WRRET_NACK_OCCURRED : 1; - unsigned int : 3; - unsigned int MCIF_WRRET_NACK_CLEAR : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_CONFIG0__CI { - struct { - unsigned int CONF_EN_CH0 : 1; - unsigned int CONF_EN_CH1 : 1; - unsigned int CONF_AUTO_EN : 1; - unsigned int : 1; - unsigned int MASK : 4; - unsigned int PTR : 10; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_CONFIG1__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_MISCCTRL0__CI { - struct { - unsigned int UDD_ON_STATUS_BITS : 1; - unsigned int LOAD_DATA_SEL : 1; - unsigned int LOAD_UDD : 1; - unsigned int ADR_STATUS_SEL : 1; - unsigned int DATA_SEL : 4; - unsigned int PRBS_CHK_LOAD_CNT : 7; - unsigned int : 1; - unsigned int UDD : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_MISCCTRL1__CI { - struct { - unsigned int PRBS_ERR_CNT_LIMIT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_MISCCTRL2__CI { - struct { - unsigned int PRBS_RUN_LENGTH : 17; - unsigned int PRBS_FREERUN : 1; - unsigned int PRBS15_MODE : 1; - unsigned int PRBS23_MODE : 1; - unsigned int STOP_ON_NEXT_ERR : 1; - unsigned int STOP_CLK : 1; - unsigned int : 2; - unsigned int SWEEP_DLY : 2; - unsigned int GRAY_CODE_EN : 1; - unsigned int : 1; - unsigned int SEL_PHY_PRBS_CHK : 1; - unsigned int SEL_AC_PRBS_CHK : 1; - unsigned int STATUS_SEL : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_SETUPFIFO__CI { - struct { - unsigned int WRITE_FIFO_RST : 1; - unsigned int READ_FIFO_RST : 1; - unsigned int BOTH_FIFO_RST : 1; - unsigned int SYNC_RST : 1; - unsigned int SYNC_RST_MASK : 2; - unsigned int OUTPUT_EN_RST : 1; - unsigned int : 1; - unsigned int SHIFT_WR_FIFO_PTR : 2; - unsigned int DELAY_RD_FIFO_PTR : 3; - unsigned int : 3; - unsigned int STROBE : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_SETUPSWEEP__CI { - struct { - unsigned int DLL_RST : 1; - unsigned int CONFIG : 1; - unsigned int MASTER : 1; - unsigned int : 1; - unsigned int DLLDLY : 4; - unsigned int DLLSTEPS : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_SETUP__CI { - struct { - unsigned int DLB_EN : 1; - unsigned int DLB_FIFO_EN : 1; - unsigned int DLB_STATUS_EN : 1; - unsigned int DLB_CONFIG_EN : 1; - unsigned int DLB_PRBS_EN : 1; - unsigned int PRBS_GEN_RST : 1; - unsigned int PRBS_CHK_RST : 1; - unsigned int PRBS_PHY_RST : 1; - unsigned int QDR_MODE : 1; - unsigned int : 7; - unsigned int CHK_DATA_BITS : 8; - unsigned int MEM_BIT_SEL : 5; - unsigned int : 2; - unsigned int RXTXLP_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_STATUS_MISC0__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_STATUS_MISC1__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_STATUS_MISC2__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_STATUS_MISC3__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_STATUS_MISC4__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_STATUS_MISC5__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_STATUS_MISC6__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_STATUS_MISC7__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_STATUS__CI { - struct { - unsigned int STICK_ERROR : 4; - unsigned int LOCK : 4; - unsigned int SWEEP_DONE : 4; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_DLB_WRITE_MASK__CI { - struct { - unsigned int BIT_MASK : 22; - unsigned int : 2; - unsigned int CH_MASK : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_DBG__SI__CI { - struct { - unsigned int SELECT0 : 4; - unsigned int SELECT1 : 4; - unsigned int CTRL0__CI : 5; - unsigned int CTRL1__CI : 5; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_FRAMING { - struct { - unsigned int BITS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_HUB_CG { - struct { - unsigned int ONDLY : 6; - unsigned int OFFDLY : 6; - unsigned int RDYDLY : 6; - unsigned int ENABLE : 1; - unsigned int MEM_LS_ENABLE : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_IDLE_STATUS__CI { - struct { - unsigned int OUTSTANDING_GFX_READ : 1; - unsigned int OUTSTANDING_GFX_WRITE : 1; - unsigned int OUTSTANDING_RLC_READ : 1; - unsigned int OUTSTANDING_RLC_WRITE : 1; - unsigned int OUTSTANDING_SDMA0_READ : 1; - unsigned int OUTSTANDING_SDMA0_WRITE : 1; - unsigned int OUTSTANDING_SDMA1_READ : 1; - unsigned int OUTSTANDING_SDMA1_WRITE : 1; - unsigned int OUTSTANDING_DISP_READ : 1; - unsigned int OUTSTANDING_DISP_WRITE : 1; - unsigned int OUTSTANDING_UVD_READ : 1; - unsigned int OUTSTANDING_UVD_WRITE : 1; - unsigned int OUTSTANDING_SMU_READ : 1; - unsigned int OUTSTANDING_SMU_WRITE : 1; - unsigned int OUTSTANDING_HDP_READ : 1; - unsigned int OUTSTANDING_HDP_WRITE : 1; - unsigned int OUTSTANDING_OTH_READ : 1; - unsigned int OUTSTANDING_OTH_WRITE : 1; - unsigned int OUTSTANDING_VMC_READ : 1; - unsigned int OUTSTANDING_VMC_WRITE : 1; - unsigned int OUTSTANDING_IA_READ : 1; - unsigned int OUTSTANDING_IA_WRITE : 1; - unsigned int OUTSTANDING_VCE_READ : 1; - unsigned int OUTSTANDING_VCE_WRITE : 1; - unsigned int OUTSTANDING_ACP_READ : 1; - unsigned int OUTSTANDING_ACP_WRITE : 1; - unsigned int OUTSTANDING_CP_READ : 1; - unsigned int OUTSTANDING_CP_WRITE : 1; - unsigned int OUTSTANDING_XDMA_READ : 1; - unsigned int OUTSTANDING_XDMA_WRITE : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_IDLE_STATUS__VI { - struct { - unsigned int OUTSTANDING_GFX_READ : 1; - unsigned int OUTSTANDING_GFX_WRITE : 1; - unsigned int OUTSTANDING_RLC_READ : 1; - unsigned int OUTSTANDING_RLC_WRITE : 1; - unsigned int OUTSTANDING_SDMA0_READ : 1; - unsigned int OUTSTANDING_SDMA0_WRITE : 1; - unsigned int OUTSTANDING_SDMA1_READ : 1; - unsigned int OUTSTANDING_SDMA1_WRITE : 1; - unsigned int OUTSTANDING_DISP_READ : 1; - unsigned int OUTSTANDING_DISP_WRITE : 1; - unsigned int OUTSTANDING_UVD_READ : 1; - unsigned int OUTSTANDING_UVD_WRITE : 1; - unsigned int OUTSTANDING_SMU_READ : 1; - unsigned int OUTSTANDING_SMU_WRITE : 1; - unsigned int OUTSTANDING_HDP_READ : 1; - unsigned int OUTSTANDING_HDP_WRITE : 1; - unsigned int OUTSTANDING_OTH_READ : 1; - unsigned int OUTSTANDING_OTH_WRITE : 1; - unsigned int OUTSTANDING_VMC_READ : 1; - unsigned int OUTSTANDING_VMC_WRITE : 1; - unsigned int OUTSTANDING_VCE_READ : 1; - unsigned int OUTSTANDING_VCE_WRITE : 1; - unsigned int OUTSTANDING_ACP_READ : 1; - unsigned int OUTSTANDING_ACP_WRITE : 1; - unsigned int OUTSTANDING_SAMMSP_READ : 1; - unsigned int OUTSTANDING_SAMMSP_WRITE : 1; - unsigned int OUTSTANDING_XDMA_READ : 1; - unsigned int OUTSTANDING_XDMA_WRITE : 1; - unsigned int OUTSTANDING_ISP_READ : 1; - unsigned int OUTSTANDING_ISP_WRITE : 1; - unsigned int OUTSTANDING_VP8_READ : 1; - unsigned int OUTSTANDING_VP8_WRITE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_IDLE_STATUS__SI { - struct { - unsigned int OUTSTANDING_CP_READ : 1; - unsigned int OUTSTANDING_CP_WRITE : 1; - unsigned int OUTSTANDING_GFX_READ : 1; - unsigned int OUTSTANDING_GFX_WRITE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int OUTSTANDING_RLC_READ : 1; - unsigned int OUTSTANDING_RLC_WRITE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int OUTSTANDING_DISP_READ : 1; - unsigned int OUTSTANDING_DISP_WRITE : 1; - unsigned int OUTSTANDING_UVD_READ : 1; - unsigned int OUTSTANDING_UVD_WRITE : 1; - unsigned int OUTSTANDING_SMU_READ : 1; - unsigned int OUTSTANDING_SMU_WRITE : 1; - unsigned int OUTSTANDING_HDP_READ : 1; - unsigned int OUTSTANDING_HDP_WRITE : 1; - unsigned int OUTSTANDING_OTH_READ : 1; - unsigned int OUTSTANDING_OTH_WRITE : 1; - unsigned int OUTSTANDING_VMC_READ : 1; - unsigned int OUTSTANDING_VMC_WRITE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int OUTSTANDING_VCE_READ : 1; - unsigned int OUTSTANDING_VCE_WRITE : 1; - unsigned int OUTSTANDING_XDMA_READ : 1; - unsigned int OUTSTANDING_XDMA_WRITE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_OVERRIDE { - struct { - unsigned int IDLE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_POWER { - struct { - unsigned int : 2; - unsigned int SRBM_GATE_OVERRIDE : 1; - unsigned int PM_BLACKOUT_CNTL : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_SIP_CG { - struct { - unsigned int ONDLY : 6; - unsigned int OFFDLY : 6; - unsigned int RDYDLY : 6; - unsigned int ENABLE : 1; - unsigned int MEM_LS_ENABLE : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_STATUS__SI__CI { - struct { - unsigned int OUTSTANDING_READ : 1; - unsigned int OUTSTANDING_WRITE : 1; - unsigned int OUTSTANDING_HUB_RDREQ : 1; - unsigned int OUTSTANDING_HUB_RDRET : 1; - unsigned int OUTSTANDING_HUB_WRREQ : 1; - unsigned int OUTSTANDING_HUB_WRRET : 1; - unsigned int OUTSTANDING_RPB_READ : 1; - unsigned int OUTSTANDING_RPB_WRITE : 1; - unsigned int OUTSTANDING_MCD_READ : 1; - unsigned int OUTSTANDING_MCD_WRITE : 1; - unsigned int RPB_BUSY : 1; - unsigned int WRITE_DEADLOCK_WARNING : 1; - unsigned int READ_DEADLOCK_WARNING : 1; - unsigned int GFX_BUSY : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_STATUS__VI { - struct { - unsigned int OUTSTANDING_READ : 1; - unsigned int OUTSTANDING_WRITE : 1; - unsigned int OUTSTANDING_ATOMIC : 1; - unsigned int OUTSTANDING_HUB_RDREQ : 1; - unsigned int OUTSTANDING_HUB_RDRET : 1; - unsigned int OUTSTANDING_HUB_WRREQ : 1; - unsigned int OUTSTANDING_HUB_WRRET : 1; - unsigned int OUTSTANDING_HUB_ATOMIC_REQ : 1; - unsigned int OUTSTANDING_HUB_ATOMIC_RET : 1; - unsigned int OUTSTANDING_RPB_READ : 1; - unsigned int OUTSTANDING_RPB_WRITE : 1; - unsigned int OUTSTANDING_RPB_ATOMIC : 1; - unsigned int OUTSTANDING_MCD_READ : 1; - unsigned int OUTSTANDING_MCD_WRITE : 1; - unsigned int OUTSTANDING_MCD_ATOMIC : 1; - unsigned int RPB_BUSY : 1; - unsigned int WRITE_DEADLOCK_WARNING : 1; - unsigned int READ_DEADLOCK_WARNING : 1; - unsigned int ATOMIC_DEADLOCK_WARNING : 1; - unsigned int GFX_BUSY : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_VM_CG { - struct { - unsigned int ONDLY : 6; - unsigned int OFFDLY : 6; - unsigned int RDYDLY : 6; - unsigned int ENABLE : 1; - unsigned int MEM_LS_ENABLE : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_PERFCOUNTER0_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_PERFCOUNTER1_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_PERFCOUNTER2_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_PERFCOUNTER3_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_PERFCOUNTER_HI__CI__VI { - struct { - unsigned int COUNTER_HI : 16; - unsigned int COMPARE_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_PERFCOUNTER_LO__CI__VI { - struct { - unsigned int COUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_PERFCOUNTER_RSLT_CNTL__CI__VI { - struct { - unsigned int PERF_COUNTER_SELECT : 4; - unsigned int : 4; - unsigned int START_TRIGGER : 8; - unsigned int STOP_TRIGGER : 8; - unsigned int ENABLE_ANY : 1; - unsigned int CLEAR_ALL : 1; - unsigned int STOP_ALL_ON_SATURATE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_ACPG_LIMIT__CI__VI { - struct { - unsigned int ENABLE : 2; - unsigned int LIMIT_COUNT : 5; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_ACPG__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int PRIORITY_DISABLE : 1; - unsigned int STALL_FILTER_ENABLE : 1; - unsigned int STALL_THRESHOLD : 6; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_ACPO__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int PRIORITY_DISABLE : 1; - unsigned int STALL_FILTER_ENABLE : 1; - unsigned int STALL_THRESHOLD : 6; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_CNTL__SI__CI { - struct { - unsigned int REMOTE_BLACKOUT : 1; - unsigned int : 1; - unsigned int JUMPAHEAD_GBL0 : 1; - unsigned int JUMPAHEAD_GBL1 : 1; - unsigned int OVERRIDE_STALL_ENABLE : 1; - unsigned int MCDW_STALL_MODE : 1; - unsigned int MCDX_STALL_MODE : 1; - unsigned int MCDY_STALL_MODE : 1; - unsigned int MCDZ_STALL_MODE : 1; - unsigned int BREAK_HDP_DEADLOCK : 1; - unsigned int DEBUG_REG : 7; - unsigned int DISABLE_SELF_INIT_GBL0 : 1; - unsigned int DISABLE_SELF_INIT_GBL1 : 1; - unsigned int PWRXPRESS_MODE : 1; - unsigned int ACPG_HP_TO_MCD_OVERRIDE__CI : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_CNTL__VI { - struct { - unsigned int REMOTE_BLACKOUT : 1; - unsigned int : 1; - unsigned int JUMPAHEAD_GBL0 : 1; - unsigned int JUMPAHEAD_GBL1 : 1; - unsigned int OVERRIDE_STALL_ENABLE : 1; - unsigned int MCDW_STALL_MODE : 1; - unsigned int MCDX_STALL_MODE : 1; - unsigned int MCDY_STALL_MODE : 1; - unsigned int MCDZ_STALL_MODE : 1; - unsigned int MCDS_STALL_MODE : 1; - unsigned int MCDT_STALL_MODE : 1; - unsigned int MCDU_STALL_MODE : 1; - unsigned int MCDV_STALL_MODE : 1; - unsigned int BREAK_HDP_DEADLOCK : 1; - unsigned int DEBUG_REG : 7; - unsigned int DISABLE_SELF_INIT_GBL0 : 1; - unsigned int DISABLE_SELF_INIT_GBL1 : 1; - unsigned int PWRXPRESS_MODE : 1; - unsigned int ACPG_HP_TO_MCD_OVERRIDE : 1; - unsigned int GBL0_PRI_ENABLE : 1; - unsigned int UVD_TRANSCODE_ENABLE : 1; - unsigned int DMIF_URG_THRESHOLD : 4; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_CPC__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_CPF__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_CPG__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_CP__SI { - struct { - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 4; - unsigned int : 4; - unsigned int : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_CREDITS { - struct { - unsigned int VM0 : 8; - unsigned int VM1 : 8; - unsigned int STOR0 : 8; - unsigned int STOR1 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_CREDITS2__SI__CI { - struct { - unsigned int STOR1_PRI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_CREDITS2__VI { - struct { - unsigned int STOR0_PRI : 8; - unsigned int STOR1_PRI : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_DMIF { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_DMIF_LIMIT { - struct { - unsigned int ENABLE : 2; - unsigned int LIMIT_COUNT : 5; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_GBL0 { - struct { - unsigned int STALL_THRESHOLD : 8; - unsigned int STALL_THRESHOLD_PRI__VI : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_GBL1 { - struct { - unsigned int STALL_THRESHOLD : 8; - unsigned int STALL_THRESHOLD_PRI__VI : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_HDP { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_IA0__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_IA1__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_IA__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDW__SI__CI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int STALL_THRESHOLD : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDW__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int MED_CREDITS : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDX__SI__CI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int STALL_THRESHOLD : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDX__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int MED_CREDITS : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDY__SI__CI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int STALL_THRESHOLD : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDY__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int MED_CREDITS : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDZ__SI__CI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int STALL_THRESHOLD : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDZ__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int MED_CREDITS : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCIF { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_RLC { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_SAM__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_SDMA0__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_SDMA1__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_SEM { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_SIP__SI__CI { - struct { - unsigned int ASK_CREDITS : 7; - unsigned int DUMMY : 1; - unsigned int DISPLAY_CREDITS : 7; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_SIP__VI { - struct { - unsigned int ASK_CREDITS : 7; - unsigned int MED_CREDIT_SEL : 1; - unsigned int DISPLAY_CREDITS : 7; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_SMU { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_STATUS__SI__CI { - struct { - unsigned int SIP_AVAIL : 1; - unsigned int MCDW_RD_AVAIL : 1; - unsigned int MCDX_RD_AVAIL : 1; - unsigned int MCDY_RD_AVAIL : 1; - unsigned int MCDZ_RD_AVAIL : 1; - unsigned int GBL0_VM_FULL : 1; - unsigned int GBL0_STOR_FULL : 1; - unsigned int GBL0_BYPASS_STOR_FULL : 1; - unsigned int GBL1_VM_FULL : 1; - unsigned int GBL1_STOR_FULL : 1; - unsigned int GBL1_BYPASS_STOR_FULL : 1; - unsigned int PWRXPRESS_ERR : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_STATUS__VI { - struct { - unsigned int SIP_AVAIL : 1; - unsigned int MCDW_RD_AVAIL : 1; - unsigned int MCDX_RD_AVAIL : 1; - unsigned int MCDY_RD_AVAIL : 1; - unsigned int MCDZ_RD_AVAIL : 1; - unsigned int MCDS_RD_AVAIL : 1; - unsigned int MCDT_RD_AVAIL : 1; - unsigned int MCDU_RD_AVAIL : 1; - unsigned int MCDV_RD_AVAIL : 1; - unsigned int GBL0_VM_FULL : 1; - unsigned int GBL0_STOR_FULL : 1; - unsigned int GBL0_BYPASS_STOR_FULL : 1; - unsigned int GBL1_VM_FULL : 1; - unsigned int GBL1_STOR_FULL : 1; - unsigned int GBL1_BYPASS_STOR_FULL : 1; - unsigned int PWRXPRESS_ERR : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_UMC { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int VM_BYPASS__VI : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_UVD { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int VM_BYPASS : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_VCE__SI__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_VCEU__SI__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_VMC { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_WTM_CNTL { - struct { - unsigned int GROUP0_DECREMENT : 3; - unsigned int GROUP1_DECREMENT : 3; - unsigned int GROUP2_DECREMENT : 3; - unsigned int GROUP3_DECREMENT : 3; - unsigned int GROUP4_DECREMENT : 3; - unsigned int GROUP5_DECREMENT : 3; - unsigned int GROUP6_DECREMENT : 3; - unsigned int GROUP7_DECREMENT : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_XDMAM { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_SHARED_DAGB_DLY { - struct { - unsigned int DLY : 6; - unsigned int : 10; - unsigned int CLI : 6; - unsigned int : 2; - unsigned int POS : 5; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_ACPG__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int PRIORITY_DISABLE : 1; - unsigned int STALL_FILTER_ENABLE : 1; - unsigned int STALL_THRESHOLD : 6; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_ACPO__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int PRIORITY_DISABLE : 1; - unsigned int STALL_FILTER_ENABLE : 1; - unsigned int STALL_THRESHOLD : 6; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_BP { - struct { - unsigned int ENABLE : 1; - unsigned int RDRET : 17; - unsigned int WRREQ : 12; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CNTL { - struct { - unsigned int : 1; - unsigned int JUMPAHEAD_GBL0 : 1; - unsigned int JUMPAHEAD_GBL1 : 1; - unsigned int JUMPAHEAD_INTERNAL : 1; - unsigned int OVERRIDE_STALL_ENABLE : 1; - unsigned int DEBUG_REG : 8; - unsigned int DISABLE_SELF_INIT_GBL0 : 1; - unsigned int DISABLE_SELF_INIT_GBL1 : 1; - unsigned int DISABLE_SELF_INIT_INTERNAL : 1; - unsigned int FAIR_CH_SW : 1; - unsigned int LCLWRREQ_BYPASS : 1; - unsigned int DISP_WAIT_EOP : 1; - unsigned int MCD_WAIT_EOP : 1; - unsigned int SIP_WAIT_EOP : 1; - unsigned int UVD_VCE_WRITE_PRI_EN__VI : 1; - unsigned int WRITE_PRI_EN__VI : 1; - unsigned int IH_PHYSADDR_ENABLE__VI : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CPC__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CPF__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CPG__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CP__SI { - struct { - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 4; - unsigned int : 4; - unsigned int : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CREDITS { - struct { - unsigned int VM0 : 8; - unsigned int VM1 : 8; - unsigned int STOR0 : 8; - unsigned int STOR1 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_ERR { - struct { - unsigned int MGPU1_TARG_SYS : 1; - unsigned int MGPU2_TARG_SYS : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_GBL0 { - struct { - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_THRESHOLD : 8; - unsigned int STALL_MODE : 1; - unsigned int STALL_THRESHOLD_PRI__VI : 8; - unsigned int STALL_THRESHOLD_URG__VI : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_GBL1 { - struct { - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_THRESHOLD : 8; - unsigned int STALL_MODE : 1; - unsigned int STALL_THRESHOLD_PRI__VI : 8; - unsigned int STALL_THRESHOLD_URG__VI : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_HDP { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_IH { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_MCDW { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 1; - unsigned int MAXBURST : 4; - unsigned int ASK_CREDITS : 6; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_THRESHOLD : 7; - unsigned int ASK_CREDITS_W : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_MCDX { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 1; - unsigned int MAXBURST : 4; - unsigned int ASK_CREDITS : 6; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_THRESHOLD : 7; - unsigned int ASK_CREDITS_W : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_MCDY { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 1; - unsigned int MAXBURST : 4; - unsigned int ASK_CREDITS : 6; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_THRESHOLD : 7; - unsigned int ASK_CREDITS_W : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_MCDZ { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 1; - unsigned int MAXBURST : 4; - unsigned int ASK_CREDITS : 6; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_THRESHOLD : 7; - unsigned int ASK_CREDITS_W : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_MCIF { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_MGPU__SI__CI { - struct { - unsigned int STOR : 8; - unsigned int CID : 8; - unsigned int MGPU_PRIORITY_TIME : 7; - unsigned int ENABLE : 1; - unsigned int OTH_PRIORITY_TIME : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_MGPU2__SI__CI { - struct { - unsigned int CID2 : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_RLC { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_SAM__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_SDMA0__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_SDMA1__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_SEM { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_SH0 { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_SH1 { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_SH2__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_SH3__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_SIP { - struct { - unsigned int STALL_MODE : 2; - unsigned int ASK_CREDITS : 7; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_SMU { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_STATUS__SI__CI { - struct { - unsigned int SIP_AVAIL : 1; - unsigned int MCDW_RD_AVAIL : 1; - unsigned int MCDX_RD_AVAIL : 1; - unsigned int MCDY_RD_AVAIL : 1; - unsigned int MCDZ_RD_AVAIL : 1; - unsigned int GBL0_VM_FULL : 1; - unsigned int GBL0_STOR_FULL : 1; - unsigned int GBL0_BYPASS_STOR_FULL : 1; - unsigned int GBL1_VM_FULL : 1; - unsigned int GBL1_STOR_FULL : 1; - unsigned int GBL1_BYPASS_STOR_FULL : 1; - unsigned int MCDW_WR_AVAIL : 1; - unsigned int MCDX_WR_AVAIL : 1; - unsigned int MCDY_WR_AVAIL : 1; - unsigned int MCDZ_WR_AVAIL : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_STATUS__VI { - struct { - unsigned int SIP_AVAIL : 1; - unsigned int MCDW_RD_AVAIL : 1; - unsigned int MCDX_RD_AVAIL : 1; - unsigned int MCDY_RD_AVAIL : 1; - unsigned int MCDZ_RD_AVAIL : 1; - unsigned int MCDS_RD_AVAIL : 1; - unsigned int MCDT_RD_AVAIL : 1; - unsigned int MCDU_RD_AVAIL : 1; - unsigned int MCDV_RD_AVAIL : 1; - unsigned int MCDW_WR_AVAIL : 1; - unsigned int MCDX_WR_AVAIL : 1; - unsigned int MCDY_WR_AVAIL : 1; - unsigned int MCDZ_WR_AVAIL : 1; - unsigned int MCDS_WR_AVAIL : 1; - unsigned int MCDT_WR_AVAIL : 1; - unsigned int MCDU_WR_AVAIL : 1; - unsigned int MCDV_WR_AVAIL : 1; - unsigned int GBL0_VM_FULL : 1; - unsigned int GBL0_STOR_FULL : 1; - unsigned int GBL0_BYPASS_STOR_FULL : 1; - unsigned int GBL1_VM_FULL : 1; - unsigned int GBL1_STOR_FULL : 1; - unsigned int GBL1_BYPASS_STOR_FULL : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_UMC { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_UVD { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int VM_BYPASS : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_VCE__SI__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_VCEU__SI__CI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_WTM_CNTL { - struct { - unsigned int GROUP0_DECREMENT : 3; - unsigned int GROUP1_DECREMENT : 3; - unsigned int GROUP2_DECREMENT : 3; - unsigned int GROUP3_DECREMENT : 3; - unsigned int GROUP4_DECREMENT : 3; - unsigned int GROUP5_DECREMENT : 3; - unsigned int GROUP6_DECREMENT : 3; - unsigned int GROUP7_DECREMENT : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_XDMA { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_XDMAM { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_XDP { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE__VI : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WRRET_CNTL { - struct { - unsigned int JUMPAHEAD : 1; - unsigned int BP : 20; - unsigned int BP_ENABLE : 1; - unsigned int DEBUG_REG : 8; - unsigned int DISABLE_SELF_INIT : 1; - unsigned int FAIR_CH_SW : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WRRET_MCDW { - struct { - unsigned int STALL_MODE : 1; - unsigned int CREDIT_COUNT : 7; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WRRET_MCDX { - struct { - unsigned int STALL_MODE : 1; - unsigned int CREDIT_COUNT : 7; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WRRET_MCDY { - struct { - unsigned int STALL_MODE : 1; - unsigned int CREDIT_COUNT : 7; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WRRET_MCDZ { - struct { - unsigned int STALL_MODE : 1; - unsigned int CREDIT_COUNT : 7; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WRRET_STATUS { - struct { - unsigned int MCDW_AVAIL : 1; - unsigned int MCDX_AVAIL : 1; - unsigned int MCDY_AVAIL : 1; - unsigned int MCDZ_AVAIL : 1; - unsigned int MCDS_AVAIL__VI : 1; - unsigned int MCDT_AVAIL__VI : 1; - unsigned int MCDU_AVAIL__VI : 1; - unsigned int MCDV_AVAIL__VI : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IMP_CNTL__SI__CI { - struct { - unsigned int MEM_IO_UPDATE_RATE : 5; - unsigned int CAL_VREF_SEL : 1; - unsigned int CAL_VREFMODE : 1; - unsigned int : 1; - unsigned int TIMEOUT_ERR : 1; - unsigned int CLEAR_TIMEOUT_ERR : 1; - unsigned int : 3; - unsigned int MEM_IO_SAMPLE_CNT : 3; - unsigned int CAL_VREF : 7; - unsigned int : 6; - unsigned int CAL_WHEN_IDLE : 1; - unsigned int CAL_WHEN_REFRESH : 1; - unsigned int CAL_PWRON : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IMP_DEBUG__SI__CI { - struct { - unsigned int TSTARTUP_CNTR : 8; - unsigned int TIMEOUT_CNTR : 8; - unsigned int PMVCAL_RESERVED : 12; - unsigned int DEBUG_CAL_EN : 1; - unsigned int DEBUG_CAL_START : 1; - unsigned int DEBUG_CAL_INTR : 1; - unsigned int DEBUG_CAL_DONE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IMP_DQ_STATUS__SI__CI { - struct { - unsigned int CH0_DQ_PSTR : 8; - unsigned int CH0_DQ_NSTR : 8; - unsigned int CH1_DQ_PSTR : 8; - unsigned int CH1_DQ_NSTR : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IMP_STATUS__SI__CI { - struct { - unsigned int PSTR_CAL : 8; - unsigned int PSTR_ACCUM_VAL : 8; - unsigned int NSTR_CAL : 8; - unsigned int NSTR_ACCUM_VAL : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_APHY_STR_CNTL_D0__SI__CI { - struct { - unsigned int PSTR_OFF_A : 6; - unsigned int NSTR_OFF_A : 6; - unsigned int PSTR_OFF_D_RD : 6; - unsigned int : 6; - unsigned int USE_A_CAL : 1; - unsigned int USE_D_RD_CAL : 1; - unsigned int CAL_SEL : 2; - unsigned int LOAD_A_STR : 1; - unsigned int LOAD_D_RD_STR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_APHY_STR_CNTL_D1__SI__CI { - struct { - unsigned int PSTR_OFF_A : 6; - unsigned int NSTR_OFF_A : 6; - unsigned int PSTR_OFF_D_RD : 6; - unsigned int : 6; - unsigned int USE_A_CAL : 1; - unsigned int USE_D_RD_CAL : 1; - unsigned int CAL_SEL : 2; - unsigned int LOAD_A_STR : 1; - unsigned int LOAD_D_RD_STR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_CDRCNTL1_D0__SI__CI { - struct { - unsigned int DQ_RXPHASE_B0 : 8; - unsigned int DQ_RXPHASE_B1 : 8; - unsigned int WCDR_TXPHASE_B0 : 8; - unsigned int WCDR_TXPHASE_B1 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_CDRCNTL1_D1__SI__CI { - struct { - unsigned int DQ_RXPHASE_B0 : 8; - unsigned int DQ_RXPHASE_B1 : 8; - unsigned int WCDR_TXPHASE_B0 : 8; - unsigned int WCDR_TXPHASE_B1 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_CDRCNTL2_D0__SI__CI { - struct { - unsigned int CDR_FB_SEL0 : 1; - unsigned int CDR_FB_SEL1 : 1; - unsigned int EDC_RXEN_OVR0 : 1; - unsigned int EDC_RXEN_OVR1 : 1; - unsigned int TXCDRBYPASS0 : 1; - unsigned int TXCDRBYPASS1 : 1; - unsigned int WCK_RXEN_OVR0 : 1; - unsigned int WCK_RXEN_OVR1 : 1; - unsigned int WCDRTXPWRON__CI : 4; - unsigned int WCDRTXSEL__CI : 4; - unsigned int WCDRTRACK01__CI : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_CDRCNTL2_D1__SI__CI { - struct { - unsigned int CDR_FB_SEL0 : 1; - unsigned int CDR_FB_SEL1 : 1; - unsigned int EDC_RXEN_OVR0 : 1; - unsigned int EDC_RXEN_OVR1 : 1; - unsigned int TXCDRBYPASS0 : 1; - unsigned int TXCDRBYPASS1 : 1; - unsigned int WCK_RXEN_OVR0 : 1; - unsigned int WCK_RXEN_OVR1 : 1; - unsigned int WCDRTXPWRON__CI : 4; - unsigned int WCDRTXSEL__CI : 4; - unsigned int WCDRTRACK01__CI : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_CDRCNTL_D0__SI__CI { - struct { - unsigned int RXPHASE_B01 : 4; - unsigned int RXPHASE_B23 : 4; - unsigned int RXCDREN_B01 : 1; - unsigned int RXCDREN_B23 : 1; - unsigned int RXCDRBYPASS_B01 : 1; - unsigned int RXCDRBYPASS_B23 : 1; - unsigned int RXPHASE1_B01 : 4; - unsigned int RXPHASE1_B23 : 4; - unsigned int DQTXCDREN_B0 : 1; - unsigned int DQTXCDREN_B1 : 1; - unsigned int DQRXCDREN_B0 : 1; - unsigned int DQRXCDREN_B1 : 1; - unsigned int WCDRRXCDREN_B0 : 1; - unsigned int WCDRRXCDREN_B1 : 1; - unsigned int WCDREDC_B0 : 1; - unsigned int WCDREDC_B1 : 1; - unsigned int DQRXSEL_B0 : 1; - unsigned int DQRXSEL_B1 : 1; - unsigned int DQTXSEL_B0 : 1; - unsigned int DQTXSEL_B1 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_CDRCNTL_D1__SI__CI { - struct { - unsigned int RXPHASE_B01 : 4; - unsigned int RXPHASE_B23 : 4; - unsigned int RXCDREN_B01 : 1; - unsigned int RXCDREN_B23 : 1; - unsigned int RXCDRBYPASS_B01 : 1; - unsigned int RXCDRBYPASS_B23 : 1; - unsigned int RXPHASE1_B01 : 4; - unsigned int RXPHASE1_B23 : 4; - unsigned int DQTXCDREN_B0 : 1; - unsigned int DQTXCDREN_B1 : 1; - unsigned int DQRXCDREN_B0 : 1; - unsigned int DQRXCDREN_B1 : 1; - unsigned int WCDRRXCDREN_B0 : 1; - unsigned int WCDRRXCDREN_B1 : 1; - unsigned int WCDREDC_B0 : 1; - unsigned int WCDREDC_B1 : 1; - unsigned int DQRXSEL_B0 : 1; - unsigned int DQRXSEL_B1 : 1; - unsigned int DQTXSEL_B0 : 1; - unsigned int DQTXSEL_B1 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ACMD_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRH_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_ADDRL_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CK_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_CMD_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DBI_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0H_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0L_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1H_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1L_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2H_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2L_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3H_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3L_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_RX_DYN_PM_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_RX_DYN_PM_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_RX_EQ_PM_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_RX_EQ_PM_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_EDC_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_0 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_1 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_10 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_100 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_101 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_102 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_103 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_104 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_105 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_106 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_107 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_108 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_109 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_11 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_110 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_111 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_112 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_113 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_114 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_115 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_116 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_117 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_118 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_119 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_12 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_120 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_121 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_122 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_123 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_124 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_125 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_126 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_127 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_128 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_129 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_13 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_130 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_131 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_132 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_133 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_134 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_135 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_136 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_137 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_138 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_139 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_14 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_140 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_141 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_142 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_143 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_144 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_145 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_146 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_147 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_148 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_149 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_15 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_150 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_151 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_152 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_153 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_154 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_155 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_156 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_157 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_158 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_159 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_16 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_17 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_18 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_19 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_2 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_20 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_21 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_22 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_23 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_24 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_25 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_26 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_27 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_28 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_29 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_3 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_30 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_31 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_32 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_33 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_34 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_35 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_36 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_37 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_38 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_39 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_4 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_40 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_41 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_42 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_43 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_44 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_45 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_46 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_47 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_48 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_49 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_5 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_50 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_51 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_52 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_53 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_54 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_55 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_56 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_57 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_58 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_59 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_6 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_60 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_61 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_62 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_63 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_64 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_65 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_66 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_67 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_68 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_69 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_7 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_70 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_71 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_72 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_73 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_74 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_75 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_76 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_77 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_78 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_79 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_8 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_80 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_81 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_82 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_83 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_84 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_85 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_86 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_87 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_88 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_89 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_9 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_90 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_91 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_92 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_93 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_94 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_95 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_96 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_97 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_98 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_UP_99 { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCDR_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_CLKSEL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_CLKSEL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_MISC_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_MISC_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_OFSCAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_OFSCAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_RXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_RXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_RX_EQ_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_RX_EQ_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_TXBST_PD_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_TXBST_PD_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_TXBST_PU_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_TXBST_PU_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_TXPHASE_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_TXPHASE_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_TXSLF_D0__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DEBUG_WCK_TXSLF_D1__SI__CI { - struct { - unsigned int VALUE0 : 8; - unsigned int VALUE1 : 8; - unsigned int VALUE2 : 8; - unsigned int VALUE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DPHY_STR_CNTL_D0__SI__CI { - struct { - unsigned int PSTR_OFF_D : 6; - unsigned int NSTR_OFF_D : 6; - unsigned int PSTR_OFF_S : 6; - unsigned int NSTR_OFF_S : 6; - unsigned int USE_D_CAL : 1; - unsigned int USE_S_CAL : 1; - unsigned int CAL_SEL : 2; - unsigned int LOAD_D_STR : 1; - unsigned int LOAD_S_STR : 1; - unsigned int AUTO_LD_STR__CI : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_DPHY_STR_CNTL_D1__SI__CI { - struct { - unsigned int PSTR_OFF_D : 6; - unsigned int NSTR_OFF_D : 6; - unsigned int PSTR_OFF_S : 6; - unsigned int NSTR_OFF_S : 6; - unsigned int USE_D_CAL : 1; - unsigned int USE_S_CAL : 1; - unsigned int CAL_SEL : 2; - unsigned int LOAD_D_STR : 1; - unsigned int LOAD_S_STR : 1; - unsigned int AUTO_LD_STR__CI : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_PAD_CNTL__SI__CI { - struct { - unsigned int MEM_IO_IMP_MIN : 8; - unsigned int MEM_IO_IMP_MAX : 8; - unsigned int TXPHASE_GRAY : 1; - unsigned int RXPHASE_GRAY : 1; - unsigned int OVL_YCLKON_D0 : 1; - unsigned int OVL_YCLKON_D1 : 1; - unsigned int ATBSEL : 4; - unsigned int ATBEN : 6; - unsigned int ATBSEL_D1 : 1; - unsigned int ATBSEL_D0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_PAD_CNTL_D0__SI__CI { - struct { - unsigned int : 2; - unsigned int DELAY_CLK_SYNC : 1; - unsigned int DELAY_CMD_SYNC : 1; - unsigned int DELAY_ADR_SYNC : 1; - unsigned int : 2; - unsigned int MEM_FALL_OUT_CLK : 1; - unsigned int MEM_FALL_OUT_CMD : 1; - unsigned int MEM_FALL_OUT_ADR : 1; - unsigned int FORCE_EN_RD_STR : 1; - unsigned int EN_RD_STR_DLY : 1; - unsigned int DISABLE_CMD : 1; - unsigned int DISABLE_ADR : 1; - unsigned int VREFI_EN : 1; - unsigned int VREFI_SEL : 5; - unsigned int CK_AUTO_EN : 1; - unsigned int CK_DELAY_SEL : 1; - unsigned int CK_DELAY_N : 2; - unsigned int CK_DELAY_P : 2; - unsigned int : 1; - unsigned int TXPWROFF_CKE : 1; - unsigned int UNI_STR : 1; - unsigned int DIFF_STR : 1; - unsigned int GDDR_PWRON : 1; - unsigned int TXPWROFF_CLK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_PAD_CNTL_D1__SI__CI { - struct { - unsigned int DELAY_DATA_SYNC : 1; - unsigned int DELAY_STR_SYNC : 1; - unsigned int DELAY_CLK_SYNC : 1; - unsigned int DELAY_CMD_SYNC : 1; - unsigned int DELAY_ADR_SYNC : 1; - unsigned int MEM_FALL_OUT_DATA : 1; - unsigned int MEM_FALL_OUT_STR : 1; - unsigned int MEM_FALL_OUT_CLK : 1; - unsigned int MEM_FALL_OUT_CMD : 1; - unsigned int MEM_FALL_OUT_ADR : 1; - unsigned int FORCE_EN_RD_STR : 1; - unsigned int EN_RD_STR_DLY : 1; - unsigned int DISABLE_CMD : 1; - unsigned int DISABLE_ADR : 1; - unsigned int VREFI_EN : 1; - unsigned int VREFI_SEL : 5; - unsigned int CK_AUTO_EN : 1; - unsigned int CK_DELAY_SEL : 1; - unsigned int CK_DELAY_N : 2; - unsigned int CK_DELAY_P : 2; - unsigned int : 1; - unsigned int TXPWROFF_CKE : 1; - unsigned int UNI_STR : 1; - unsigned int DIFF_STR : 1; - unsigned int GDDR_PWRON : 1; - unsigned int TXPWROFF_CLK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL1_DPHY0_D0__CI { - struct { - unsigned int VREFCAL1_MSB : 4; - unsigned int VREFCAL2_MSB : 4; - unsigned int VREFCAL3 : 8; - unsigned int VREFSEL2 : 1; - unsigned int VREFSEL3 : 1; - unsigned int VREFPDNB_1 : 1; - unsigned int DLL_PWRGOOD_OVR : 1; - unsigned int DLL_VCTRLADC_EN : 1; - unsigned int DLL_MSTR_STBY : 1; - unsigned int RXLEQ_EN : 1; - unsigned int RXLEQ_NXT : 1; - unsigned int : 1; - unsigned int PMD_LOOPBACK : 3; - unsigned int DLL_RSV : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL1_DPHY0_D0__SI { - struct { - unsigned int VREFCAL1_MSB : 4; - unsigned int VREFCAL2_MSB : 4; - unsigned int VREFCAL3 : 8; - unsigned int VREFSEL2 : 1; - unsigned int VREFSEL3 : 1; - unsigned int VREFPDNB_1 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int PMD_LOOPBACK : 3; - unsigned int DLL_RSV : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL1_DPHY0_D1__CI { - struct { - unsigned int VREFCAL1_MSB : 4; - unsigned int VREFCAL2_MSB : 4; - unsigned int VREFCAL3 : 8; - unsigned int VREFSEL2 : 1; - unsigned int VREFSEL3 : 1; - unsigned int VREFPDNB_1 : 1; - unsigned int DLL_PWRGOOD_OVR : 1; - unsigned int DLL_VCTRLADC_EN : 1; - unsigned int DLL_MSTR_STBY : 1; - unsigned int RXLEQ_EN : 1; - unsigned int RXLEQ_NXT : 1; - unsigned int : 1; - unsigned int PMD_LOOPBACK : 3; - unsigned int DLL_RSV : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL1_DPHY0_D1__SI { - struct { - unsigned int VREFCAL1_MSB : 4; - unsigned int VREFCAL2_MSB : 4; - unsigned int VREFCAL3 : 8; - unsigned int VREFSEL2 : 1; - unsigned int VREFSEL3 : 1; - unsigned int VREFPDNB_1 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int PMD_LOOPBACK : 3; - unsigned int DLL_RSV : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL1_DPHY1_D0__CI { - struct { - unsigned int VREFCAL1_MSB : 4; - unsigned int VREFCAL2_MSB : 4; - unsigned int VREFCAL3 : 8; - unsigned int VREFSEL2 : 1; - unsigned int VREFSEL3 : 1; - unsigned int VREFPDNB_1 : 1; - unsigned int DLL_PWRGOOD_OVR : 1; - unsigned int DLL_VCTRLADC_EN : 1; - unsigned int DLL_MSTR_STBY : 1; - unsigned int RXLEQ_EN : 1; - unsigned int RXLEQ_NXT : 1; - unsigned int : 1; - unsigned int PMD_LOOPBACK : 3; - unsigned int DLL_RSV : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL1_DPHY1_D0__SI { - struct { - unsigned int VREFCAL1_MSB : 4; - unsigned int VREFCAL2_MSB : 4; - unsigned int VREFCAL3 : 8; - unsigned int VREFSEL2 : 1; - unsigned int VREFSEL3 : 1; - unsigned int VREFPDNB_1 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int PMD_LOOPBACK : 3; - unsigned int DLL_RSV : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL1_DPHY1_D1__CI { - struct { - unsigned int VREFCAL1_MSB : 4; - unsigned int VREFCAL2_MSB : 4; - unsigned int VREFCAL3 : 8; - unsigned int VREFSEL2 : 1; - unsigned int VREFSEL3 : 1; - unsigned int VREFPDNB_1 : 1; - unsigned int DLL_PWRGOOD_OVR : 1; - unsigned int DLL_VCTRLADC_EN : 1; - unsigned int DLL_MSTR_STBY : 1; - unsigned int RXLEQ_EN : 1; - unsigned int RXLEQ_NXT : 1; - unsigned int : 1; - unsigned int PMD_LOOPBACK : 3; - unsigned int DLL_RSV : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL1_DPHY1_D1__SI { - struct { - unsigned int VREFCAL1_MSB : 4; - unsigned int VREFCAL2_MSB : 4; - unsigned int VREFCAL3 : 8; - unsigned int VREFSEL2 : 1; - unsigned int VREFSEL3 : 1; - unsigned int VREFPDNB_1 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int PMD_LOOPBACK : 3; - unsigned int DLL_RSV : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL_DPHY0_D0__SI__CI { - struct { - unsigned int RXBIASSEL : 2; - unsigned int RCVSEL : 1; - unsigned int VREFPDNB : 1; - unsigned int RXDPWRON_DLY : 2; - unsigned int RXPDNB : 1; - unsigned int RXLP : 1; - unsigned int VREFCAL : 4; - unsigned int VREFCAL_STR : 4; - unsigned int VREFSEL : 1; - unsigned int : 1; - unsigned int RX_PEAKSEL : 2; - unsigned int DLL_ADJ_B0 : 3; - unsigned int : 1; - unsigned int DLL_ADJ_B1 : 3; - unsigned int : 1; - unsigned int DLL_ADJ_M : 1; - unsigned int REFCLK_PWRON : 1; - unsigned int DLL_BW_CTRL : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL_DPHY0_D1__SI__CI { - struct { - unsigned int RXBIASSEL : 2; - unsigned int RCVSEL : 1; - unsigned int VREFPDNB : 1; - unsigned int RXDPWRON_DLY : 2; - unsigned int RXPDNB : 1; - unsigned int RXLP : 1; - unsigned int VREFCAL : 4; - unsigned int VREFCAL_STR : 4; - unsigned int VREFSEL : 1; - unsigned int : 1; - unsigned int RX_PEAKSEL : 2; - unsigned int DLL_ADJ_B0 : 3; - unsigned int : 1; - unsigned int DLL_ADJ_B1 : 3; - unsigned int : 1; - unsigned int DLL_ADJ_M : 1; - unsigned int REFCLK_PWRON : 1; - unsigned int DLL_BW_CTRL : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL_DPHY1_D0__SI__CI { - struct { - unsigned int RXBIASSEL : 2; - unsigned int RCVSEL : 1; - unsigned int VREFPDNB : 1; - unsigned int RXDPWRON_DLY : 2; - unsigned int RXPDNB : 1; - unsigned int RXLP : 1; - unsigned int VREFCAL : 4; - unsigned int VREFCAL_STR : 4; - unsigned int VREFSEL : 1; - unsigned int : 1; - unsigned int RX_PEAKSEL : 2; - unsigned int DLL_ADJ_B0 : 3; - unsigned int : 1; - unsigned int DLL_ADJ_B1 : 3; - unsigned int : 1; - unsigned int DLL_ADJ_M : 1; - unsigned int REFCLK_PWRON : 1; - unsigned int DLL_BW_CTRL : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_RXCNTL_DPHY1_D1__SI__CI { - struct { - unsigned int RXBIASSEL : 2; - unsigned int RCVSEL : 1; - unsigned int VREFPDNB : 1; - unsigned int RXDPWRON_DLY : 2; - unsigned int RXPDNB : 1; - unsigned int RXLP : 1; - unsigned int VREFCAL : 4; - unsigned int VREFCAL_STR : 4; - unsigned int VREFSEL : 1; - unsigned int : 1; - unsigned int RX_PEAKSEL : 2; - unsigned int DLL_ADJ_B0 : 3; - unsigned int : 1; - unsigned int DLL_ADJ_B1 : 3; - unsigned int : 1; - unsigned int DLL_ADJ_M : 1; - unsigned int REFCLK_PWRON : 1; - unsigned int DLL_BW_CTRL : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_TXCNTL_APHY_D0__SI__CI { - struct { - unsigned int BIASSEL : 2; - unsigned int DRVDUTY : 2; - unsigned int LOWCMEN : 1; - unsigned int QDR : 1; - unsigned int EMPH : 1; - unsigned int TXPD : 1; - unsigned int PTERM : 4; - unsigned int TXBPASS_SEL : 1; - unsigned int PMA_LOOPBACK : 3; - unsigned int PDRV : 4; - unsigned int NDRV : 3; - unsigned int YCLKON : 1; - unsigned int TSTEN : 1; - unsigned int TXRESET : 1; - unsigned int TXBYPASS : 1; - unsigned int TXBYPASS_DATA : 3; - unsigned int CKE_BIT : 1; - unsigned int CKE_SEL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_TXCNTL_APHY_D1__SI__CI { - struct { - unsigned int BIASSEL : 2; - unsigned int DRVDUTY : 2; - unsigned int LOWCMEN : 1; - unsigned int QDR : 1; - unsigned int EMPH : 1; - unsigned int TXPD : 1; - unsigned int PTERM : 4; - unsigned int TXBPASS_SEL : 1; - unsigned int PMA_LOOPBACK : 3; - unsigned int PDRV : 4; - unsigned int NDRV : 3; - unsigned int YCLKON : 1; - unsigned int TSTEN : 1; - unsigned int TXRESET : 1; - unsigned int TXBYPASS : 1; - unsigned int TXBYPASS_DATA : 3; - unsigned int CKE_BIT : 1; - unsigned int CKE_SEL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_TXCNTL_DPHY0_D0__SI__CI { - struct { - unsigned int BIASSEL : 2; - unsigned int DRVDUTY : 2; - unsigned int LOWCMEN : 1; - unsigned int QDR : 1; - unsigned int EMPH : 1; - unsigned int TXPD : 1; - unsigned int PTERM : 4; - unsigned int NTERM : 4; - unsigned int PDRV : 4; - unsigned int NDRV : 4; - unsigned int TSTEN : 1; - unsigned int EDCTX_CLKGATE_EN : 1; - unsigned int TXBYPASS : 1; - unsigned int PLL_LOOPBCK : 1; - unsigned int TXBYPASS_DATA : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_TXCNTL_DPHY0_D1__SI__CI { - struct { - unsigned int BIASSEL : 2; - unsigned int DRVDUTY : 2; - unsigned int LOWCMEN : 1; - unsigned int QDR : 1; - unsigned int EMPH : 1; - unsigned int TXPD : 1; - unsigned int PTERM : 4; - unsigned int NTERM : 4; - unsigned int PDRV : 4; - unsigned int NDRV : 4; - unsigned int TSTEN : 1; - unsigned int EDCTX_CLKGATE_EN : 1; - unsigned int TXBYPASS : 1; - unsigned int PLL_LOOPBCK : 1; - unsigned int TXBYPASS_DATA : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_TXCNTL_DPHY1_D0__SI__CI { - struct { - unsigned int BIASSEL : 2; - unsigned int DRVDUTY : 2; - unsigned int LOWCMEN : 1; - unsigned int QDR : 1; - unsigned int EMPH : 1; - unsigned int TXPD : 1; - unsigned int PTERM : 4; - unsigned int NTERM : 4; - unsigned int PDRV : 4; - unsigned int NDRV : 4; - unsigned int TSTEN : 1; - unsigned int EDCTX_CLKGATE_EN : 1; - unsigned int TXBYPASS : 1; - unsigned int PLL_LOOPBCK : 1; - unsigned int TXBYPASS_DATA : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_IO_TXCNTL_DPHY1_D1__SI__CI { - struct { - unsigned int BIASSEL : 2; - unsigned int DRVDUTY : 2; - unsigned int LOWCMEN : 1; - unsigned int QDR : 1; - unsigned int EMPH : 1; - unsigned int TXPD : 1; - unsigned int PTERM : 4; - unsigned int NTERM : 4; - unsigned int PDRV : 4; - unsigned int NDRV : 4; - unsigned int TSTEN : 1; - unsigned int EDCTX_CLKGATE_EN : 1; - unsigned int TXBYPASS : 1; - unsigned int PLL_LOOPBCK : 1; - unsigned int TXBYPASS_DATA : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCBVM_PERFCOUNTER0_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCBVM_PERFCOUNTER1_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCBVM_PERFCOUNTER2_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCBVM_PERFCOUNTER3_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCBVM_PERFCOUNTER_HI__CI__VI { - struct { - unsigned int COUNTER_HI : 16; - unsigned int COMPARE_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCBVM_PERFCOUNTER_LO__CI__VI { - struct { - unsigned int COUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CI__VI { - struct { - unsigned int PERF_COUNTER_SELECT : 4; - unsigned int : 4; - unsigned int START_TRIGGER : 8; - unsigned int STOP_TRIGGER : 8; - unsigned int ENABLE_ANY : 1; - unsigned int CLEAR_ALL : 1; - unsigned int STOP_ALL_ON_SATURATE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCDVM_PERFCOUNTER0_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCDVM_PERFCOUNTER1_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCDVM_PERFCOUNTER2_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCDVM_PERFCOUNTER3_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCDVM_PERFCOUNTER_HI__CI__VI { - struct { - unsigned int COUNTER_HI : 16; - unsigned int COMPARE_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCDVM_PERFCOUNTER_LO__CI__VI { - struct { - unsigned int COUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CI__VI { - struct { - unsigned int PERF_COUNTER_SELECT : 4; - unsigned int : 4; - unsigned int START_TRIGGER : 8; - unsigned int STOP_TRIGGER : 8; - unsigned int ENABLE_ANY : 1; - unsigned int CLEAR_ALL : 1; - unsigned int STOP_ALL_ON_SATURATE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_MEM_POWER_LS { - struct { - unsigned int LS_SETUP : 6; - unsigned int LS_HOLD : 6; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_NPL_STATUS__SI__CI { - struct { - unsigned int D0_PDELAY : 2; - unsigned int D0_NDELAY : 2; - unsigned int D0_PEARLY : 1; - unsigned int D0_NEARLY : 1; - unsigned int D1_PDELAY : 2; - unsigned int D1_NDELAY : 2; - unsigned int D1_PEARLY : 1; - unsigned int D1_NEARLY : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PHY_TIMING_2__SI__CI { - struct { - unsigned int IND_LD_CNT : 7; - unsigned int : 1; - unsigned int RXC0_INV : 1; - unsigned int RXC1_INV : 1; - unsigned int TXC0_INV : 1; - unsigned int TXC1_INV : 1; - unsigned int RXC0_FRC : 1; - unsigned int RXC1_FRC : 1; - unsigned int TXC0_FRC : 1; - unsigned int TXC1_FRC : 1; - unsigned int TX_CDREN_D0 : 1; - unsigned int TX_CDREN_D1 : 1; - unsigned int ADR_CLKEN_D0 : 1; - unsigned int ADR_CLKEN_D1 : 1; - unsigned int WR_DLY : 4; - unsigned int RXDPWRONC0_FRC__CI : 1; - unsigned int RXDPWRONC1_FRC__CI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PHY_TIMING_D0__SI__CI { - struct { - unsigned int RXC0_DLY : 4; - unsigned int RXC0_EXT : 4; - unsigned int RXC1_DLY : 4; - unsigned int RXC1_EXT : 4; - unsigned int TXC0_DLY : 3; - unsigned int : 1; - unsigned int TXC0_EXT : 4; - unsigned int TXC1_DLY : 3; - unsigned int : 1; - unsigned int TXC1_EXT : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PHY_TIMING_D1__SI__CI { - struct { - unsigned int RXC0_DLY : 4; - unsigned int RXC0_EXT : 4; - unsigned int RXC1_DLY : 4; - unsigned int RXC1_EXT : 4; - unsigned int TXC0_DLY : 3; - unsigned int : 1; - unsigned int TXC0_EXT : 4; - unsigned int TXC1_DLY : 3; - unsigned int : 1; - unsigned int TXC1_EXT : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_AUTO_CFG__SI__CI { - struct { - unsigned int SYC_CLK : 1; - unsigned int RST_MRS : 1; - unsigned int TRI_MIO : 1; - unsigned int : 1; - unsigned int XSR_TMR : 4; - unsigned int SS_ALWAYS_SLF : 1; - unsigned int SS_S_SLF : 1; - unsigned int SCDS_MODE : 1; - unsigned int EXIT_ALLOW_STOP : 1; - unsigned int RFS_SRX : 1; - unsigned int PREA_SRX : 1; - unsigned int STUTTER_EN : 1; - unsigned int SELFREFR_COMMIT_0 : 1; - unsigned int MRS_WAIT_CNT : 4; - unsigned int WRITE_DURING_DLOCK : 1; - unsigned int YCLK_ON__CI : 1; - unsigned int RXPDNB : 1; - unsigned int SELFREFR_COMMIT_1 : 1; - unsigned int DLL_CNT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_AUTO_CMD__SI__CI { - struct { - unsigned int ADR : 17; - unsigned int : 11; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_CFG__SI__CI { - struct { - unsigned int SYC_CLK : 1; - unsigned int RST_MRS : 1; - unsigned int RST_EMRS : 1; - unsigned int TRI_MIO : 1; - unsigned int XSR_TMR : 4; - unsigned int RST_MRS1 : 1; - unsigned int RST_MRS2 : 1; - unsigned int DPM_WAKE : 1; - unsigned int : 1; - unsigned int RFS_SRX : 1; - unsigned int PREA_SRX : 1; - unsigned int : 2; - unsigned int MRS_WAIT_CNT : 4; - unsigned int WRITE_DURING_DLOCK : 1; - unsigned int YCLK_ON__CI : 1; - unsigned int EARLY_ACK_ACPI : 1; - unsigned int : 2; - unsigned int RXPDNB : 1; - unsigned int ZQCL_SEND : 2; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_CFG__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int WRITE_DURING_DLOCK : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int EARLY_ACK_ACPI : 1; - unsigned int : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_CMD_EMRS__SI__CI { - struct { - unsigned int ADR : 16; - unsigned int MOP : 3; - unsigned int BNK_MSB : 1; - unsigned int END : 1; - unsigned int CSB : 2; - unsigned int : 5; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_CMD_EMRS__VI { - struct { - unsigned int ADR : 16; - unsigned int : 4; - unsigned int MOP : 4; - unsigned int END : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_CMD_MRS__SI__CI { - struct { - unsigned int ADR : 16; - unsigned int MOP : 3; - unsigned int BNK_MSB : 1; - unsigned int END : 1; - unsigned int CSB : 2; - unsigned int : 5; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_CMD_MRS__VI { - struct { - unsigned int ADR : 16; - unsigned int : 4; - unsigned int MOP : 4; - unsigned int END : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_CMD_MRS1__SI__CI { - struct { - unsigned int ADR : 16; - unsigned int MOP : 3; - unsigned int BNK_MSB : 1; - unsigned int END : 1; - unsigned int CSB : 2; - unsigned int : 5; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_CMD_MRS1__VI { - struct { - unsigned int ADR : 16; - unsigned int : 4; - unsigned int MOP : 4; - unsigned int END : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_CMD_MRS2__SI__CI { - struct { - unsigned int ADR : 16; - unsigned int MOP : 3; - unsigned int BNK_MSB : 1; - unsigned int END : 1; - unsigned int CSB : 2; - unsigned int : 5; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_PMG_CMD_MRS2__VI { - struct { - unsigned int ADR : 16; - unsigned int : 4; - unsigned int MOP : 4; - unsigned int END : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_CB { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAX_BURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_DB { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAX_BURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_GRP_EXT { - struct { - unsigned int DBSTEN0 : 4; - unsigned int TC0 : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_GRP_GFX__CI { - struct { - unsigned int CP : 4; - unsigned int SH : 4; - unsigned int IA : 4; - unsigned int ACPG : 4; - unsigned int ACPO : 4; - unsigned int XDMAM : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_GRP_GFX__VI { - struct { - unsigned int CP : 4; - unsigned int SH : 4; - unsigned int IA : 4; - unsigned int ACPG : 4; - unsigned int ACPO : 4; - unsigned int ISP : 4; - unsigned int VP8 : 4; - unsigned int XDMAM : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_GRP_GFX__SI { - struct { - unsigned int CP : 4; - unsigned int : 4; - unsigned int : 4; - unsigned int : 4; - unsigned int XDMAM : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_GRP_LCL { - struct { - unsigned int : 12; - unsigned int CB0 : 4; - unsigned int CBCMASK0 : 4; - unsigned int CBFMASK0 : 4; - unsigned int DB0 : 4; - unsigned int DBHTILE0 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_GRP_OTH__CI { - struct { - unsigned int UVD_EXT0 : 4; - unsigned int SDMA0 : 4; - unsigned int HDP : 4; - unsigned int SEM : 4; - unsigned int UMC : 4; - unsigned int UVD : 4; - unsigned int UVD_EXT1 : 4; - unsigned int SAM : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_GRP_OTH__VI { - struct { - unsigned int UVD_EXT0 : 4; - unsigned int SDMA0 : 4; - unsigned int HDP : 4; - unsigned int SEM : 4; - unsigned int UMC : 4; - unsigned int UVD : 4; - unsigned int UVD_EXT1 : 4; - unsigned int SAMMSP : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_GRP_OTH__SI { - struct { - unsigned int UVD_EXT0 : 4; - unsigned int : 4; - unsigned int HDP : 4; - unsigned int SEM : 4; - unsigned int UMC : 4; - unsigned int UVD : 4; - unsigned int UVD_EXT1 : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_GRP_SYS__CI__VI { - struct { - unsigned int RLC : 4; - unsigned int VMC : 4; - unsigned int SDMA1 : 4; - unsigned int DMIF : 4; - unsigned int MCIF : 4; - unsigned int SMU : 4; - unsigned int VCE : 4; - unsigned int VCEU : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_GRP_SYS__SI { - struct { - unsigned int RLC : 4; - unsigned int VMC : 4; - unsigned int : 4; - unsigned int DMIF : 4; - unsigned int MCIF : 4; - unsigned int SMU : 4; - unsigned int VCE : 4; - unsigned int VCEU : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_HUB { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAX_BURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_TC0 { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAX_BURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RD_TC1 { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAX_BURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_ARB_CNTL { - struct { - unsigned int WR_SWITCH_NUM : 8; - unsigned int RD_SWITCH_NUM : 8; - unsigned int ATC_SWITCH_NUM : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_BIF_CNTL { - struct { - unsigned int ARB_SWITCH_NUM : 8; - unsigned int XPB_SWITCH_NUM : 8; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_CID_QUEUE_EX { - struct { - unsigned int START : 1; - unsigned int OFFSET : 5; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_CID_QUEUE_EX_DATA { - struct { - unsigned int WRITE_ENTRIES : 16; - unsigned int READ_ENTRIES : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_CID_QUEUE_RD { - struct { - unsigned int CLIENT_ID : 8; - unsigned int WRITE_QUEUE : 2; - unsigned int READ_QUEUE : 2; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_CID_QUEUE_WR { - struct { - unsigned int CLIENT_ID : 8; - unsigned int UPDATE_MODE : 1; - unsigned int WRITE_QUEUE : 2; - unsigned int READ_QUEUE : 2; - unsigned int UPDATE : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_CONF { - struct { - unsigned int : 15; - unsigned int XPB_PCIE_ORDER : 1; - unsigned int RPB_RD_PCIE_ORDER : 1; - unsigned int RPB_WR_PCIE_ORDER : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_DBG1 { - struct { - unsigned int RPB_BIF_OUTSTANDING_RD : 8; - unsigned int RPB_BIF_OUTSTANDING_RD_32B : 12; - unsigned int DEBUG_BITS : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_EFF_CNTL { - struct { - unsigned int WR_LAZY_TIMER : 8; - unsigned int RD_LAZY_TIMER : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_IF_CONF { - struct { - unsigned int RPB_BIF_CREDITS : 8; - unsigned int OUTSTANDING_WRRET_ASK : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_PERFCOUNTER0_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_PERFCOUNTER1_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_PERFCOUNTER2_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_PERFCOUNTER3_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_PERFCOUNTER_HI__CI__VI { - struct { - unsigned int COUNTER_HI : 16; - unsigned int COMPARE_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_PERFCOUNTER_LO__CI__VI { - struct { - unsigned int COUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_PERFCOUNTER_RSLT_CNTL__CI__VI { - struct { - unsigned int PERF_COUNTER_SELECT : 4; - unsigned int : 4; - unsigned int START_TRIGGER : 8; - unsigned int STOP_TRIGGER : 8; - unsigned int ENABLE_ANY : 1; - unsigned int CLEAR_ALL : 1; - unsigned int STOP_ALL_ON_SATURATE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_PERF_COUNTER_CNTL { - struct { - unsigned int PERF_COUNTER_SELECT : 2; - unsigned int CLEAR_SELECTED_PERF_COUNTER : 1; - unsigned int CLEAR_ALL_PERF_COUNTERS : 1; - unsigned int STOP_ON_COUNTER_SATURATION : 1; - unsigned int ENABLE_PERF_COUNTERS : 4; - unsigned int PERF_COUNTER_ASSIGN_0 : 5; - unsigned int PERF_COUNTER_ASSIGN_1 : 5; - unsigned int PERF_COUNTER_ASSIGN_2 : 5; - unsigned int PERF_COUNTER_ASSIGN_3 : 5; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_PERF_COUNTER_STATUS { - struct { - unsigned int PERFORMANCE_COUNTER_VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_RD_SWITCH_CNTL { - struct { - unsigned int QUEUE0_SWITCH_NUM : 8; - unsigned int QUEUE1_SWITCH_NUM : 8; - unsigned int QUEUE2_SWITCH_NUM : 8; - unsigned int QUEUE3_SWITCH_NUM : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_WR_COMBINE_CNTL { - struct { - unsigned int WC_ENABLE : 1; - unsigned int WC_MAX_PACKET_SIZE : 2; - unsigned int WC_FLUSH_TIMER : 4; - unsigned int WC_ALIGN : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_WR_SWITCH_CNTL { - struct { - unsigned int QUEUE0_SWITCH_NUM : 8; - unsigned int QUEUE1_SWITCH_NUM : 8; - unsigned int QUEUE2_SWITCH_NUM : 8; - unsigned int QUEUE3_SWITCH_NUM : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_BIT_REMAP_B0_D0__SI__CI { - struct { - unsigned int BIT0 : 3; - unsigned int BIT1 : 3; - unsigned int BIT2 : 3; - unsigned int BIT3 : 3; - unsigned int BIT4 : 3; - unsigned int BIT5 : 3; - unsigned int BIT6 : 3; - unsigned int BIT7 : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_BIT_REMAP_B0_D1__SI__CI { - struct { - unsigned int BIT0 : 3; - unsigned int BIT1 : 3; - unsigned int BIT2 : 3; - unsigned int BIT3 : 3; - unsigned int BIT4 : 3; - unsigned int BIT5 : 3; - unsigned int BIT6 : 3; - unsigned int BIT7 : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_BIT_REMAP_B1_D0__SI__CI { - struct { - unsigned int BIT0 : 3; - unsigned int BIT1 : 3; - unsigned int BIT2 : 3; - unsigned int BIT3 : 3; - unsigned int BIT4 : 3; - unsigned int BIT5 : 3; - unsigned int BIT6 : 3; - unsigned int BIT7 : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_BIT_REMAP_B1_D1__SI__CI { - struct { - unsigned int BIT0 : 3; - unsigned int BIT1 : 3; - unsigned int BIT2 : 3; - unsigned int BIT3 : 3; - unsigned int BIT4 : 3; - unsigned int BIT5 : 3; - unsigned int BIT6 : 3; - unsigned int BIT7 : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_BIT_REMAP_B2_D0__SI__CI { - struct { - unsigned int BIT0 : 3; - unsigned int BIT1 : 3; - unsigned int BIT2 : 3; - unsigned int BIT3 : 3; - unsigned int BIT4 : 3; - unsigned int BIT5 : 3; - unsigned int BIT6 : 3; - unsigned int BIT7 : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_BIT_REMAP_B2_D1__SI__CI { - struct { - unsigned int BIT0 : 3; - unsigned int BIT1 : 3; - unsigned int BIT2 : 3; - unsigned int BIT3 : 3; - unsigned int BIT4 : 3; - unsigned int BIT5 : 3; - unsigned int BIT6 : 3; - unsigned int BIT7 : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_BIT_REMAP_B3_D0__SI__CI { - struct { - unsigned int BIT0 : 3; - unsigned int BIT1 : 3; - unsigned int BIT2 : 3; - unsigned int BIT3 : 3; - unsigned int BIT4 : 3; - unsigned int BIT5 : 3; - unsigned int BIT6 : 3; - unsigned int BIT7 : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_BIT_REMAP_B3_D1__SI__CI { - struct { - unsigned int BIT0 : 3; - unsigned int BIT1 : 3; - unsigned int BIT2 : 3; - unsigned int BIT3 : 3; - unsigned int BIT4 : 3; - unsigned int BIT5 : 3; - unsigned int BIT6 : 3; - unsigned int BIT7 : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_BYTE_REMAP_D0__SI__CI { - struct { - unsigned int BYTE0 : 2; - unsigned int BYTE1 : 2; - unsigned int BYTE2 : 2; - unsigned int BYTE3 : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_BYTE_REMAP_D1__SI__CI { - struct { - unsigned int BYTE0 : 2; - unsigned int BYTE1 : 2; - unsigned int BYTE2 : 2; - unsigned int BYTE3 : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CAS_TIMING__SI__CI { - struct { - unsigned int TNOPW : 2; - unsigned int TNOPR : 2; - unsigned int TR2W : 5; - unsigned int TCCDL : 3; - unsigned int TR2R : 4; - unsigned int TW2R : 5; - unsigned int : 3; - unsigned int TCL : 5; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CAS_TIMING__VI { - struct { - unsigned int TNOPW : 2; - unsigned int TNOPR : 2; - unsigned int TR2W : 5; - unsigned int TCCDL : 3; - unsigned int TR2R : 4; - unsigned int TW2R : 5; - unsigned int TCL : 5; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CAS_TIMING_LP__SI__CI { - struct { - unsigned int TNOPW : 2; - unsigned int TNOPR : 2; - unsigned int TR2W : 5; - unsigned int TCCDL : 3; - unsigned int TR2R : 4; - unsigned int TW2R : 5; - unsigned int : 3; - unsigned int TCL : 5; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CAS_TIMING_LP__VI { - struct { - unsigned int TNOPW : 2; - unsigned int TNOPR : 2; - unsigned int TR2W : 5; - unsigned int TCCDL : 3; - unsigned int TR2R : 4; - unsigned int TW2R : 5; - unsigned int TCL : 5; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CG { - struct { - unsigned int CG_SEQ_REQ : 8; - unsigned int CG_SEQ_RESP : 8; - unsigned int SEQ_CG_REQ : 8; - unsigned int SEQ_CG_RESP : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CMD__SI__CI { - struct { - unsigned int ADR : 16; - unsigned int MOP : 4; - unsigned int END : 1; - unsigned int CSB : 2; - unsigned int : 1; - unsigned int CHAN0 : 1; - unsigned int CHAN1 : 1; - unsigned int : 2; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CMD__VI { - struct { - unsigned int ADR : 16; - unsigned int : 4; - unsigned int MOP : 4; - unsigned int END : 1; - unsigned int : 3; - unsigned int CHAN0 : 1; - unsigned int CHAN1 : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CNTL__SI__CI { - struct { - unsigned int MEM_ADDR_MAP_COLS : 2; - unsigned int MEM_ADDR_MAP_BANK : 2; - unsigned int SAFE_MODE : 2; - unsigned int DAT_INV : 1; - unsigned int MSK_DF1 : 1; - unsigned int CHANNEL_DISABLE : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int MSKOFF_DAT_TL : 1; - unsigned int MSKOFF_DAT_TH : 1; - unsigned int RET_HOLD_EOP : 1; - unsigned int BANKGROUP_SIZE : 1; - unsigned int BANKGROUP_ENB : 1; - unsigned int RTR_OVERRIDE : 1; - unsigned int ARB_REQCMD_WMK : 4; - unsigned int ARB_REQDAT_WMK : 4; - unsigned int ARB_RTDAT_WMK : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CNTL__VI { - struct { - unsigned int CHANNEL_DISABLE : 4; - unsigned int SAFE_MODE : 2; - unsigned int DAT_INV : 1; - unsigned int RET_HOLD_EOP : 1; - unsigned int BANKGROUP_SIZE : 1; - unsigned int BANKGROUP_ENB : 1; - unsigned int MSKOFF_DAT_TL : 1; - unsigned int MSKOFF_DAT_TH : 1; - unsigned int ARB_REQCMD_WMK : 4; - unsigned int ARB_REQDAT_WMK : 4; - unsigned int ARB_RTDAT_WMK : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int RTR_OVERRIDE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CNTL_2__CI { - struct { - unsigned int DRST_PDRV : 4; - unsigned int DRST_PU : 1; - unsigned int DRST_PD : 1; - unsigned int : 2; - unsigned int ARB_RTDAT_WMK_MSB : 2; - unsigned int DRST_NSTR : 6; - unsigned int DRST_PSTR : 6; - unsigned int PLL_TX_PWRON_D0 : 1; - unsigned int PLL_TX_PWRON_D1 : 1; - unsigned int PLL_RX_PWRON_D0 : 4; - unsigned int PLL_RX_PWRON_D1 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CNTL_2__VI { - struct { - unsigned int : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CNTL_2__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int ARB_RTDAT_WMK_MSB : 2; - unsigned int DRST_NSTR : 6; - unsigned int DRST_PSTR : 6; - unsigned int PLL_TX_PWRON_D0 : 1; - unsigned int PLL_TX_PWRON_D1 : 1; - unsigned int PLL_RX_PWRON_D0 : 4; - unsigned int PLL_RX_PWRON_D1 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CNTL_3__CI { - struct { - unsigned int PIPE_DELAY_OUT_D0 : 3; - unsigned int PIPE_DELAY_IN_D0 : 3; - unsigned int PIPE_DELAY_OUT_D1 : 3; - unsigned int PIPE_DELAY_IN_D1 : 3; - unsigned int REPCG_EN_D0 : 1; - unsigned int REPCG_EN_D1 : 1; - unsigned int : 2; - unsigned int REPCG_OFF_DLY : 4; - unsigned int FCK_FRC : 1; - unsigned int DBI_FRC : 1; - unsigned int PRGRM_CDC : 1; - unsigned int DQS_FRC : 1; - unsigned int DQS_FRC_PAT : 4; - unsigned int : 2; - unsigned int IDSC_EN : 1; - unsigned int CAC_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_CNTL_3__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int : 3; - unsigned int : 1; - unsigned int : 8; - unsigned int : 4; - unsigned int : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_DLL_STBY_LP__CI { - struct { - unsigned int EN : 1; - unsigned int VCTRLADC_FRC : 1; - unsigned int VCTRLADC_VAL : 1; - unsigned int MSTRSTBY_FRC : 1; - unsigned int MSTRSTBY_VAL : 1; - unsigned int ENTR_DLY : 3; - unsigned int STBY_DLY : 4; - unsigned int TCKE_PULSE_EXTN : 4; - unsigned int TCKE_EXTN : 8; - unsigned int EXIT_DLY : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_DLL_STBY__CI { - struct { - unsigned int EN : 1; - unsigned int VCTRLADC_FRC : 1; - unsigned int VCTRLADC_VAL : 1; - unsigned int MSTRSTBY_FRC : 1; - unsigned int MSTRSTBY_VAL : 1; - unsigned int ENTR_DLY : 3; - unsigned int STBY_DLY : 4; - unsigned int TCKE_PULSE_EXTN : 4; - unsigned int TCKE_EXTN : 8; - unsigned int EXIT_DLY : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_DRAM__SI__CI { - struct { - unsigned int ADR_2CK : 1; - unsigned int ADR_MUX : 1; - unsigned int ADR_DF1 : 1; - unsigned int AP8 : 1; - unsigned int DAT_DF1 : 1; - unsigned int DQS_DF1 : 1; - unsigned int DQM_DF1 : 1; - unsigned int DQM_ACT : 1; - unsigned int STB_CNT : 4; - unsigned int CKE_DYN : 1; - unsigned int CKE_ACT : 1; - unsigned int BO4 : 1; - unsigned int DLL_CLR : 1; - unsigned int DLL_CNT : 8; - unsigned int DAT_INV : 1; - unsigned int INV_ACM : 1; - unsigned int ODT_ENB : 1; - unsigned int ODT_ACT : 1; - unsigned int RST_CTL : 1; - unsigned int TRI_MIO_DYN : 1; - unsigned int TRI_CKE : 1; - unsigned int RDSTRB_RSYC_DIS__CI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_DRAM__VI { - struct { - unsigned int STB_CNT : 4; - unsigned int CKE_DYN : 1; - unsigned int CKE_ACT : 1; - unsigned int DAT_INV : 1; - unsigned int INV_ACM : 1; - unsigned int RST_CTL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DQM_ACT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_DRAM_2__SI__CI { - struct { - unsigned int ADR_DDR : 1; - unsigned int ADR_DBI : 1; - unsigned int ADR_DBI_ACM : 1; - unsigned int CMD_QDR : 1; - unsigned int DAT_QDR : 1; - unsigned int WDAT_EDC : 1; - unsigned int RDAT_EDC : 1; - unsigned int DQM_EST : 1; - unsigned int RD_DQS : 1; - unsigned int WR_DQS : 1; - unsigned int PLL_EST : 1; - unsigned int PLL_CLR : 1; - unsigned int DLL_EST : 1; - unsigned int BNK_MRS : 1; - unsigned int DBI_OVR : 1; - unsigned int TRI_CLK : 1; - unsigned int PLL_CNT : 8; - unsigned int PCH_BNK : 1; - unsigned int ADBI_DF1 : 1; - unsigned int ADBI_ACT : 1; - unsigned int DBI_DF1 : 1; - unsigned int DBI_ACT : 1; - unsigned int DBI_EDC_DF1 : 1; - unsigned int TESTCHIP_EN : 1; - unsigned int CS_BY16 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_DRAM_2__VI { - struct { - unsigned int : 2; - unsigned int PCH_BNK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int WDAT_EDC : 1; - unsigned int RDAT_EDC : 1; - unsigned int : 4; - unsigned int DLL_EST : 1; - unsigned int : 1; - unsigned int : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_DRAM_ERROR_INSERTION__SI__CI { - struct { - unsigned int TX : 16; - unsigned int RX : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_FIFO_CTL__SI__CI { - struct { - unsigned int W_LD_INIT_D0 : 2; - unsigned int W_SYC_SEL : 2; - unsigned int R_LD_INIT : 2; - unsigned int R_SYC_SEL : 2; - unsigned int CG_DIS_D0 : 1; - unsigned int CG_DIS_D1 : 1; - unsigned int W_LD_INIT_D1 : 2; - unsigned int SYC_DLY : 3; - unsigned int : 1; - unsigned int W_ASYC_EXT : 2; - unsigned int W_DSYC_EXT : 2; - unsigned int R_DQS_LD_INIT__CI : 4; - unsigned int R_DQS_STEP__CI : 4; - unsigned int R_DQS_FRC__CI : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_FIFO_CTL__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_G5PDX_CMD0_LP__CI { - struct { - unsigned int CMD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_G5PDX_CMD0__CI { - struct { - unsigned int CMD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_G5PDX_CMD1_LP__CI { - struct { - unsigned int CMD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_G5PDX_CMD1__CI { - struct { - unsigned int CMD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_G5PDX_CTRL_LP__CI { - struct { - unsigned int CH0_ENABLE : 1; - unsigned int CH1_ENABLE : 1; - unsigned int WCKOFF_EARLY : 1; - unsigned int WCKOFF_LATE : 1; - unsigned int TPD2MRS : 6; - unsigned int : 2; - unsigned int TMRS2WCK : 4; - unsigned int TWCK2MRS : 4; - unsigned int TMRD : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_G5PDX_CTRL__CI { - struct { - unsigned int CH0_ENABLE : 1; - unsigned int CH1_ENABLE : 1; - unsigned int WCKOFF_EARLY : 1; - unsigned int WCKOFF_LATE : 1; - unsigned int TPD2MRS : 6; - unsigned int : 2; - unsigned int TMRS2WCK : 4; - unsigned int TWCK2MRS : 4; - unsigned int TMRD : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_DEBUG_DATA { - struct { - unsigned int IO_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_DEBUG_INDEX { - struct { - unsigned int IO_DEBUG_INDEX : 9; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RDBI__SI__CI { - struct { - unsigned int MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_REDC__SI__CI { - struct { - unsigned int EDC : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RESERVE_D0__SI__CI { - struct { - unsigned int DPHY0_RSV : 12; - unsigned int DPHY1_RSV : 12; - unsigned int APHY_RSV : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RESERVE_D1__SI__CI { - struct { - unsigned int DPHY0_RSV : 12; - unsigned int DPHY1_RSV : 12; - unsigned int APHY_RSV : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RWORD0__SI__CI { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RWORD1__SI__CI { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RWORD2__SI__CI { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RWORD3__SI__CI { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RWORD4__SI__CI { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RWORD5__SI__CI { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RWORD6__SI__CI { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RWORD7__SI__CI { - struct { - unsigned int RDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC0 { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC1 { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC3 { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC4 { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC5 { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC6 { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC7 { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC8 { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC9 { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC_TIMING__SI__CI { - struct { - unsigned int TRP_WRA : 6; - unsigned int : 2; - unsigned int TRP_RDA : 6; - unsigned int : 1; - unsigned int TRP : 5; - unsigned int TRFC : 9; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC_TIMING__VI { - struct { - unsigned int TRP_WRA : 6; - unsigned int TRP_RDA : 6; - unsigned int TRP : 5; - unsigned int TRFC : 7; - unsigned int : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC_TIMING2__SI__CI { - struct { - unsigned int PA2RDATA : 3; - unsigned int : 1; - unsigned int PA2WDATA : 3; - unsigned int : 1; - unsigned int FAW : 5; - unsigned int TREDC : 3; - unsigned int TWEDC : 5; - unsigned int T32AW : 4; - unsigned int : 3; - unsigned int TWDATATR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC_TIMING2__VI { - struct { - unsigned int PA2RDATA : 3; - unsigned int PA2WDATA : 3; - unsigned int FAW : 5; - unsigned int : 3; - unsigned int : 3; - unsigned int T32AW : 4; - unsigned int TWDATATR : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC_TIMING2_LP__SI__CI { - struct { - unsigned int PA2RDATA : 3; - unsigned int : 1; - unsigned int PA2WDATA : 3; - unsigned int : 1; - unsigned int FAW : 5; - unsigned int TREDC : 3; - unsigned int TWEDC : 5; - unsigned int TADR : 3; - unsigned int TFCKTR : 4; - unsigned int TWDATATR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC_TIMING2_LP__VI { - struct { - unsigned int PA2RDATA : 3; - unsigned int PA2WDATA : 3; - unsigned int FAW : 5; - unsigned int : 3; - unsigned int : 3; - unsigned int : 4; - unsigned int TWDATATR : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC_TIMING_LP__SI__CI { - struct { - unsigned int TRP_WRA : 6; - unsigned int : 2; - unsigned int TRP_RDA : 6; - unsigned int : 1; - unsigned int TRP : 5; - unsigned int TRFC : 9; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MISC_TIMING_LP__VI { - struct { - unsigned int TRP_WRA : 6; - unsigned int TRP_RDA : 6; - unsigned int TRP : 5; - unsigned int TRFC : 7; - unsigned int : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_MPLL_OVERRIDE__SI__CI { - struct { - unsigned int AD_PLL_RESET_OVERRIDE : 1; - unsigned int DQ_0_0_PLL_RESET_OVERRIDE : 1; - unsigned int DQ_0_1_PLL_RESET_OVERRIDE : 1; - unsigned int DQ_1_0_PLL_RESET_OVERRIDE : 1; - unsigned int DQ_1_1_PLL_RESET_OVERRIDE : 1; - unsigned int ATGM_CLK_SEL_OVERRIDE : 1; - unsigned int TEST_BYPASS_CLK_EN_OVERRIDE : 1; - unsigned int TEST_BYPASS_CLK_SEL_OVERRIDE : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PERF_CNTL__SI__CI { - struct { - unsigned int MONITOR_PERIOD : 30; - unsigned int CNTL : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PERF_CNTL_1__SI__CI { - struct { - unsigned int PAUSE : 1; - unsigned int : 7; - unsigned int SEL_A_MSB : 1; - unsigned int SEL_B_MSB : 1; - unsigned int SEL_CH0_C_MSB : 1; - unsigned int SEL_CH0_D_MSB : 1; - unsigned int SEL_CH1_A_MSB : 1; - unsigned int SEL_CH1_B_MSB : 1; - unsigned int SEL_CH1_C_MSB : 1; - unsigned int SEL_CH1_D_MSB : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PERF_SEQ_CNT_A_I0__SI__CI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PERF_SEQ_CNT_A_I1__SI__CI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PERF_SEQ_CNT_B_I0__SI__CI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PERF_SEQ_CNT_B_I1__SI__CI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PERF_SEQ_CNT_C_I0__SI__CI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PERF_SEQ_CNT_C_I1__SI__CI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PERF_SEQ_CNT_D_I0__SI__CI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PERF_SEQ_CNT_D_I1__SI__CI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PERF_SEQ_CTL__SI__CI { - struct { - unsigned int SEL_A : 4; - unsigned int SEL_B : 4; - unsigned int SEL_CH0_C : 4; - unsigned int SEL_CH0_D : 4; - unsigned int SEL_CH1_A : 4; - unsigned int SEL_CH1_B : 4; - unsigned int SEL_CH1_C : 4; - unsigned int SEL_CH1_D : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PHYREG_BCAST__CI { - struct { - unsigned int CH0_EN : 1; - unsigned int CH1_EN : 1; - unsigned int : 5; - unsigned int CKE_MASK : 1; - unsigned int DQ_MASK : 1; - unsigned int DBI_MASK : 1; - unsigned int EDC_MASK : 1; - unsigned int WCK_MASK : 1; - unsigned int WCDR_MASK : 1; - unsigned int CLK_MASK : 1; - unsigned int CMD_MASK : 1; - unsigned int ADR_MASK : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_CMD_EMRS_LP__SI__CI { - struct { - unsigned int ADR : 16; - unsigned int MOP : 3; - unsigned int BNK_MSB : 1; - unsigned int END : 1; - unsigned int CSB : 2; - unsigned int : 5; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_CMD_MRS1_LP__SI__CI { - struct { - unsigned int ADR : 16; - unsigned int MOP : 3; - unsigned int BNK_MSB : 1; - unsigned int END : 1; - unsigned int CSB : 2; - unsigned int : 5; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_CMD_MRS2_LP__SI__CI { - struct { - unsigned int ADR : 16; - unsigned int MOP : 3; - unsigned int BNK_MSB : 1; - unsigned int END : 1; - unsigned int CSB : 2; - unsigned int : 5; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_CMD_MRS_LP__SI__CI { - struct { - unsigned int ADR : 16; - unsigned int MOP : 3; - unsigned int BNK_MSB : 1; - unsigned int END : 1; - unsigned int CSB : 2; - unsigned int : 5; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_DVS_CMD_LP__CI { - struct { - unsigned int ADR : 16; - unsigned int MOP : 3; - unsigned int BNK_MSB : 1; - unsigned int END : 1; - unsigned int CSB : 2; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_DVS_CMD__CI { - struct { - unsigned int ADR : 16; - unsigned int MOP : 3; - unsigned int BNK_MSB : 1; - unsigned int END : 1; - unsigned int CSB : 2; - unsigned int ADR_MSB1 : 1; - unsigned int ADR_MSB0 : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_DVS_CTL_LP__CI { - struct { - unsigned int ENABLE : 1; - unsigned int TDVS : 5; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_DVS_CTL__CI { - struct { - unsigned int ENABLE : 1; - unsigned int TDVS : 5; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_PG_HWCNTL__SI__CI { - struct { - unsigned int PWRGATE_EN : 1; - unsigned int STAGGER_EN : 1; - unsigned int TPGCG : 4; - unsigned int D_DLY : 2; - unsigned int AC_DLY : 2; - unsigned int G_DLY : 4; - unsigned int : 2; - unsigned int TXAO : 1; - unsigned int RXAO : 1; - unsigned int ACAO : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_PG_SWCNTL_0__SI__CI { - struct { - unsigned int PMD0_DQ_TX_ENB : 1; - unsigned int PMD0_DBI_TX_ENB : 1; - unsigned int PMD0_EDC_TX_ENB : 1; - unsigned int PMD0_WCLKX_TX_ENB : 1; - unsigned int PMD0_DQ_RX_ENB : 1; - unsigned int PMD0_DBI_RX_ENB : 1; - unsigned int PMD0_EDC_RX_ENB : 1; - unsigned int PMD0_WCLKX_RX_ENB : 1; - unsigned int PMD1_DQ_TX_ENB : 1; - unsigned int PMD1_DBI_TX_ENB : 1; - unsigned int PMD1_EDC_TX_ENB : 1; - unsigned int PMD1_WCLKX_TX_ENB : 1; - unsigned int PMD1_DQ_RX_ENB : 1; - unsigned int PMD1_DBI_RX_ENB : 1; - unsigned int PMD1_EDC_RX_ENB : 1; - unsigned int PMD1_WCLKX_RX_ENB : 1; - unsigned int PMA0_AC_ENB : 1; - unsigned int : 14; - unsigned int GMCON_SR_COMMIT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_PG_SWCNTL_1__SI__CI { - struct { - unsigned int PMD2_DQ_TX_ENB : 1; - unsigned int PMD2_DBI_TX_ENB : 1; - unsigned int PMD2_EDC_TX_ENB : 1; - unsigned int PMD2_WCLKX_TX_ENB : 1; - unsigned int PMD2_DQ_RX_ENB : 1; - unsigned int PMD2_DBI_RX_ENB : 1; - unsigned int PMD2_EDC_RX_ENB : 1; - unsigned int PMD2_WCLKX_RX_ENB : 1; - unsigned int PMD3_DQ_TX_ENB : 1; - unsigned int PMD3_DBI_TX_ENB : 1; - unsigned int PMD3_EDC_TX_ENB : 1; - unsigned int PMD3_WCLKX_TX_ENB : 1; - unsigned int PMD3_DQ_RX_ENB : 1; - unsigned int PMD3_DBI_RX_ENB : 1; - unsigned int PMD3_EDC_RX_ENB : 1; - unsigned int PMD3_WCLKX_RX_ENB : 1; - unsigned int PMA1_AC_ENB : 1; - unsigned int : 14; - unsigned int GMCON_SR_COMMIT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_TIMING__SI__CI { - struct { - unsigned int TCKSRE : 3; - unsigned int : 1; - unsigned int TCKSRX : 3; - unsigned int : 1; - unsigned int TCKE_PULSE : 4; - unsigned int TCKE : 6; - unsigned int SEQ_IDLE : 3; - unsigned int : 2; - unsigned int TCKE_PULSE_MSB : 1; - unsigned int SEQ_IDLE_SS__CI : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_TIMING__VI { - struct { - unsigned int TCKSRE : 3; - unsigned int TCKSRX : 3; - unsigned int TCKE_PULSE : 5; - unsigned int TCKE : 8; - unsigned int SEQ_IDLE : 3; - unsigned int SEQ_IDLE_SS : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_TIMING_LP__SI__CI { - struct { - unsigned int TCKSRE : 3; - unsigned int : 1; - unsigned int TCKSRX : 3; - unsigned int : 1; - unsigned int TCKE_PULSE : 4; - unsigned int TCKE : 6; - unsigned int SEQ_IDLE : 3; - unsigned int : 2; - unsigned int TCKE_PULSE_MSB : 1; - unsigned int SEQ_IDLE_SS__CI : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_PMG_TIMING_LP__VI { - struct { - unsigned int TCKSRE : 3; - unsigned int TCKSRX : 3; - unsigned int TCKE_PULSE : 5; - unsigned int TCKE : 8; - unsigned int SEQ_IDLE : 3; - unsigned int SEQ_IDLE_SS : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RAS_TIMING { - struct { - unsigned int TRCDW : 5; - unsigned int TRCDWA : 5; - unsigned int TRCDR : 5; - unsigned int TRCDRA : 5; - unsigned int TRRD : 4; - unsigned int TRC : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RAS_TIMING_LP { - struct { - unsigned int TRCDW : 5; - unsigned int TRCDWA : 5; - unsigned int TRCDR : 5; - unsigned int TRCDRA : 5; - unsigned int TRRD : 4; - unsigned int TRC : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RD_CTL_D0__SI__CI { - struct { - unsigned int RCV_DLY : 3; - unsigned int RCV_EXT : 5; - unsigned int RST_SEL : 2; - unsigned int RXDPWRON_DLY : 2; - unsigned int RST_HLD : 4; - unsigned int STR_PRE : 1; - unsigned int STR_PST : 1; - unsigned int : 2; - unsigned int RBS_DLY : 5; - unsigned int RBS_WEDC_DLY : 5; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RD_CTL_D0__VI { - struct { - unsigned int RCV_DLY : 3; - unsigned int RCV_EXT : 5; - unsigned int RST_SEL : 2; - unsigned int RST_HLD : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int RBS_DLY : 5; - unsigned int : 2; - unsigned int : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RD_CTL_D0_LP__SI__CI { - struct { - unsigned int RCV_DLY : 3; - unsigned int RCV_EXT : 5; - unsigned int RST_SEL : 2; - unsigned int RXDPWRON_DLY : 2; - unsigned int RST_HLD : 4; - unsigned int STR_PRE : 1; - unsigned int STR_PST : 1; - unsigned int : 2; - unsigned int RBS_DLY : 5; - unsigned int RBS_WEDC_DLY : 5; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RD_CTL_D0_LP__VI { - struct { - unsigned int RCV_DLY : 3; - unsigned int RCV_EXT : 5; - unsigned int RST_SEL : 2; - unsigned int RST_HLD : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int RBS_DLY : 5; - unsigned int : 2; - unsigned int : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RD_CTL_D1__SI__CI { - struct { - unsigned int RCV_DLY : 3; - unsigned int RCV_EXT : 5; - unsigned int RST_SEL : 2; - unsigned int RXDPWRON_DLY : 2; - unsigned int RST_HLD : 4; - unsigned int STR_PRE : 1; - unsigned int STR_PST : 1; - unsigned int : 2; - unsigned int RBS_DLY : 5; - unsigned int RBS_WEDC_DLY : 5; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RD_CTL_D1__VI { - struct { - unsigned int RCV_DLY : 3; - unsigned int RCV_EXT : 5; - unsigned int RST_SEL : 2; - unsigned int RST_HLD : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int RBS_DLY : 5; - unsigned int : 2; - unsigned int : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RD_CTL_D1_LP__SI__CI { - struct { - unsigned int RCV_DLY : 3; - unsigned int RCV_EXT : 5; - unsigned int RST_SEL : 2; - unsigned int RXDPWRON_DLY : 2; - unsigned int RST_HLD : 4; - unsigned int STR_PRE : 1; - unsigned int STR_PST : 1; - unsigned int : 2; - unsigned int RBS_DLY : 5; - unsigned int RBS_WEDC_DLY : 5; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RD_CTL_D1_LP__VI { - struct { - unsigned int RCV_DLY : 3; - unsigned int RCV_EXT : 5; - unsigned int RST_SEL : 2; - unsigned int RST_HLD : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int RBS_DLY : 5; - unsigned int : 2; - unsigned int : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RESERVE_0_S { - struct { - unsigned int SCLK_FIELD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RESERVE_1_S { - struct { - unsigned int SCLK_FIELD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RESERVE_M { - struct { - unsigned int MCLK_FIELD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_BYTE0_D0__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_BYTE0_D1__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_BYTE1_D0__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_BYTE1_D1__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_BYTE2_D0__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_BYTE2_D1__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_BYTE3_D0__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_BYTE3_D1__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_DBI_D0__SI__CI { - struct { - unsigned int DBI0 : 4; - unsigned int DBI1 : 4; - unsigned int DBI2 : 4; - unsigned int DBI3 : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_DBI_D1__SI__CI { - struct { - unsigned int DBI0 : 4; - unsigned int DBI1 : 4; - unsigned int DBI2 : 4; - unsigned int DBI3 : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_EDC_D0__SI__CI { - struct { - unsigned int EDC0 : 4; - unsigned int EDC1 : 4; - unsigned int EDC2 : 4; - unsigned int EDC3 : 4; - unsigned int WCDR0 : 4; - unsigned int WCDR1 : 4; - unsigned int WCDR2 : 4; - unsigned int WCDR3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_RXFRAMING_EDC_D1__SI__CI { - struct { - unsigned int EDC0 : 4; - unsigned int EDC1 : 4; - unsigned int EDC2 : 4; - unsigned int EDC3 : 4; - unsigned int WCDR0 : 4; - unsigned int WCDR1 : 4; - unsigned int WCDR2 : 4; - unsigned int WCDR3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SREG_READ__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SREG_STATUS__CI__VI { - struct { - unsigned int AVAIL_RTN : 4; - unsigned int : 4; - unsigned int PND_RD : 4; - unsigned int PND_WR : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_STATUS_M__SI__CI { - struct { - unsigned int PWRUP_COMPL_D0 : 1; - unsigned int PWRUP_COMPL_D1 : 1; - unsigned int CMD_RDY_D0 : 1; - unsigned int CMD_RDY_D1 : 1; - unsigned int SLF_D0 : 1; - unsigned int SLF_D1 : 1; - unsigned int SS_SLF_D0 : 1; - unsigned int SS_SLF_D1 : 1; - unsigned int SEQ0_ARB_CMD_FIFO_EMPTY : 1; - unsigned int SEQ1_ARB_CMD_FIFO_EMPTY : 1; - unsigned int : 2; - unsigned int SEQ0_RS_DATA_FIFO_FULL : 1; - unsigned int SEQ1_RS_DATA_FIFO_FULL : 1; - unsigned int SEQ0_BUSY : 1; - unsigned int SEQ1_BUSY : 1; - unsigned int PMG_PWRSTATE : 1; - unsigned int : 3; - unsigned int PMG_FSMSTATE : 5; - unsigned int SEQ0_BUSY_HYS : 1; - unsigned int SEQ1_BUSY_HYS : 1; - unsigned int SEQ0_ALLOWSTOP__CI : 1; - unsigned int SEQ1_ALLOWSTOP__CI : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_STATUS_M__VI { - struct { - unsigned int PWRUP_COMPL_D0 : 1; - unsigned int PWRUP_COMPL_D1 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int CMD_RDY_D0 : 1; - unsigned int CMD_RDY_D1 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SEQ0_ARB_CMD_FIFO_EMPTY : 1; - unsigned int SEQ1_ARB_CMD_FIFO_EMPTY : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SEQ0_RS_DATA_FIFO_FULL : 1; - unsigned int SEQ1_RS_DATA_FIFO_FULL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SEQ0_BUSY : 1; - unsigned int SEQ1_BUSY : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_STATUS_S { - struct { - unsigned int SEQ0_ARB_DATA_FIFO_FULL : 1; - unsigned int SEQ1_ARB_DATA_FIFO_FULL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SEQ0_ARB_CMD_FIFO_FULL : 1; - unsigned int SEQ1_ARB_CMD_FIFO_FULL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SEQ0_RS_DATA_FIFO_EMPTY : 1; - unsigned int SEQ1_RS_DATA_FIFO_EMPTY : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SUP_CNTL__SI__CI { - struct { - unsigned int RUN : 1; - unsigned int SINGLE_STEP : 1; - unsigned int SW_WAKE : 1; - unsigned int RESET_PC : 1; - unsigned int PGM_WRITE : 1; - unsigned int PGM_READ : 1; - unsigned int FAST_WRITE : 1; - unsigned int BKPT_CLEAR : 1; - unsigned int : 15; - unsigned int PGM_CHKSUM : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SUP_CNTL__VI { - struct { - unsigned int RUN : 1; - unsigned int SINGLE_STEP : 1; - unsigned int SW_WAKE : 1; - unsigned int RESET_PC : 1; - unsigned int PGM_WRITE : 1; - unsigned int PGM_READ : 1; - unsigned int FAST_WRITE : 1; - unsigned int BKPT_CLEAR : 1; - unsigned int : 16; - unsigned int PGM_CHKSUM : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SUP_DEC_STAT { - struct { - unsigned int STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SUP_GP0_STAT { - struct { - unsigned int STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SUP_GP1_STAT { - struct { - unsigned int STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SUP_GP2_STAT { - struct { - unsigned int STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SUP_GP3_STAT { - struct { - unsigned int STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SUP_IR_STAT { - struct { - unsigned int STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SUP_PGM { - struct { - unsigned int CNTL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SUP_PGM_STAT { - struct { - unsigned int STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_SUP_R_PGM { - struct { - unsigned int PGM : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TCG_CNTL__SI__CI { - struct { - unsigned int RESET : 1; - unsigned int ENABLE_D0 : 1; - unsigned int ENABLE_D1 : 1; - unsigned int START : 1; - unsigned int NFIFO : 3; - unsigned int INFINITE_CMD : 1; - unsigned int MOP : 4; - unsigned int DATA_CNT : 4; - unsigned int LOAD_FIFO : 1; - unsigned int SHORT_LDFF : 1; - unsigned int FRAME_TRAIN : 1; - unsigned int BURST_NUM : 3; - unsigned int ISSUE_AREF : 1; - unsigned int TXDBI_CNTL : 1; - unsigned int VPTR_MASK : 1; - unsigned int AREF_LAST : 1; - unsigned int AREF_BOTH : 1; - unsigned int : 1; - unsigned int LD_RTDATA_OVR__CI : 1; - unsigned int LD_RTDATA_CH__CI : 1; - unsigned int : 1; - unsigned int DONE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TIMER_RD { - struct { - unsigned int COUNTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TIMER_WR { - struct { - unsigned int COUNTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_CAPTURE__SI__CI { - struct { - unsigned int D0_ARF_WAKEUP : 1; - unsigned int D1_ARF_WAKEUP : 1; - unsigned int D0_REDC_WAKEUP : 1; - unsigned int D1_REDC_WAKEUP : 1; - unsigned int D0_WEDC_WAKEUP : 1; - unsigned int D1_WEDC_WAKEUP : 1; - unsigned int MCLK_FREQ_CHANGE_WAKEUP : 1; - unsigned int SCLK_SRBM_READY_WAKEUP : 1; - unsigned int D0_CMD_FIFO_READY_WAKEUP : 1; - unsigned int D1_CMD_FIFO_READY_WAKEUP : 1; - unsigned int D0_DATA_FIFO_READY_WAKEUP : 1; - unsigned int D1_DATA_FIFO_READY_WAKEUP : 1; - unsigned int SOFTWARE_WAKEUP_WAKEUP : 1; - unsigned int RESERVE0_WAKEUP : 1; - unsigned int TSM_DONE_WAKEUP : 1; - unsigned int TIMER_DONE_WAKEUP : 1; - unsigned int : 1; - unsigned int TCG_DONE_WAKEUP : 1; - unsigned int ALLOWSTOP0_WAKEUP : 1; - unsigned int ALLOWSTOP1_WAKEUP : 1; - unsigned int DPM_WAKEUP : 1; - unsigned int ALLOWSTOPB0_WAKEUP : 1; - unsigned int ALLOWSTOPB1_WAKEUP : 1; - unsigned int DPM_LPT_WAKEUP : 1; - unsigned int D0_IDLEH_WAKEUP : 1; - unsigned int D1_IDLEH_WAKEUP : 1; - unsigned int PHY_PG_WAKEUP__CI : 1; - unsigned int SREG_WAKEUP__CI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_CAPTURE__VI { - struct { - unsigned int D0_IDLEH_WAKEUP : 1; - unsigned int D1_IDLEH_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SCLK_SRBM_READY_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SOFTWARE_WAKEUP : 1; - unsigned int : 2; - unsigned int TIMER_DONE_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_EDC_THRESHOLD__SI__CI { - struct { - unsigned int WRITE_EDC_THRESHOLD : 16; - unsigned int READ_EDC_THRESHOLD : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_EDC_THRESHOLD2__SI__CI { - struct { - unsigned int THRESHOLD_PERIOD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_EDC_THRESHOLD3__SI__CI { - struct { - unsigned int CH0_LINK_RETRAIN_STATUS : 1; - unsigned int CH1_LINK_RETRAIN_STATUS : 1; - unsigned int CLEAR_RETRAIN_STATUS : 1; - unsigned int RETRAIN_VBI : 1; - unsigned int RETRAIN_MONITOR : 2; - unsigned int : 2; - unsigned int CH0_LINK_RETRAIN_IN_PROGRESS : 1; - unsigned int CH1_LINK_RETRAIN_IN_PROGRESS : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_TIMING__SI__CI { - struct { - unsigned int TWT2RT : 5; - unsigned int TARF2T : 5; - unsigned int TT2ROW : 5; - unsigned int TLD2LD : 5; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_WAKEUP_CLEAR__SI__CI { - struct { - unsigned int D0_ARF_WAKEUP : 1; - unsigned int D1_ARF_WAKEUP : 1; - unsigned int D0_REDC_WAKEUP : 1; - unsigned int D1_REDC_WAKEUP : 1; - unsigned int D0_WEDC_WAKEUP : 1; - unsigned int D1_WEDC_WAKEUP : 1; - unsigned int MCLK_FREQ_CHANGE_WAKEUP : 1; - unsigned int SCLK_SRBM_READY_WAKEUP : 1; - unsigned int D0_CMD_FIFO_READY_WAKEUP : 1; - unsigned int D1_CMD_FIFO_READY_WAKEUP : 1; - unsigned int D0_DATA_FIFO_READY_WAKEUP : 1; - unsigned int D1_DATA_FIFO_READY_WAKEUP : 1; - unsigned int SOFTWARE_WAKEUP_WAKEUP : 1; - unsigned int RESERVE0_WAKEUP : 1; - unsigned int TSM_DONE_WAKEUP : 1; - unsigned int TIMER_DONE_WAKEUP : 1; - unsigned int CLEARALL : 1; - unsigned int TCG_DONE_WAKEUP : 1; - unsigned int ALLOWSTOP0_WAKEUP : 1; - unsigned int ALLOWSTOP1_WAKEUP : 1; - unsigned int DPM_WAKEUP : 1; - unsigned int ALLOWSTOPB0_WAKEUP : 1; - unsigned int ALLOWSTOPB1_WAKEUP : 1; - unsigned int DPM_LPT_WAKEUP : 1; - unsigned int D0_IDLEH_WAKEUP : 1; - unsigned int D1_IDLEH_WAKEUP : 1; - unsigned int PHY_PG_WAKEUP__CI : 1; - unsigned int SREG_WAKEUP__CI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_WAKEUP_CLEAR__VI { - struct { - unsigned int D0_IDLEH_WAKEUP : 1; - unsigned int D1_IDLEH_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SCLK_SRBM_READY_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SOFTWARE_WAKEUP : 1; - unsigned int : 2; - unsigned int TIMER_DONE_WAKEUP : 1; - unsigned int CLEARALL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_WAKEUP_CNTL__SI__CI { - struct { - unsigned int BOOT_UP_ADDR_TRAIN : 1; - unsigned int BOOT_UP_WCK_TRAIN : 1; - unsigned int BOOT_UP_READ_TRAIN : 1; - unsigned int BOOT_UP_WRITE_TRAIN : 1; - unsigned int SELF_REFRESH_ADDR_TRAIN : 1; - unsigned int SELF_REFRESH_WCK_TRAIN : 1; - unsigned int SELF_REFRESH_READ_TRAIN : 1; - unsigned int SELF_REFRESH_WRITE_TRAIN : 1; - unsigned int AUTO_REFRESH_ADDR_TRAIN : 1; - unsigned int AUTO_REFRESH_WCK_TRAIN : 1; - unsigned int AUTO_REFRESH_READ_TRAIN : 1; - unsigned int AUTO_REFRESH_WRITE_TRAIN : 1; - unsigned int WRITE_ECC_ADDR_TRAIN : 1; - unsigned int WRITE_ECC_WCK_TRAIN : 1; - unsigned int WRITE_ECC_READ_TRAIN : 1; - unsigned int WRITE_ECC_WRITE_TRAIN : 1; - unsigned int READ_ECC_ADDR_TRAIN : 1; - unsigned int READ_ECC_WCK_TRAIN : 1; - unsigned int READ_ECC_READ_TRAIN : 1; - unsigned int READ_ECC_WRITE_TRAIN : 1; - unsigned int AUTO_REFRESH_WAKEUP_EARLY : 1; - unsigned int STOP_WCK_D0 : 1; - unsigned int STOP_WCK_D1 : 1; - unsigned int : 1; - unsigned int BLOCK_ARB_RD_D0 : 1; - unsigned int BLOCK_ARB_WR_D0 : 1; - unsigned int BLOCK_ARB_RD_D1 : 1; - unsigned int BLOCK_ARB_WR_D1 : 1; - unsigned int SW_WAKEUP : 1; - unsigned int DISP_ASTOP_WAKEUP : 1; - unsigned int TRAIN_DONE_D0 : 1; - unsigned int TRAIN_DONE_D1 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_WAKEUP_CNTL__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int AUTO_REFRESH_WAKEUP_EARLY : 1; - unsigned int SW_WAKEUP : 1; - unsigned int BLOCK_ARB_RD_D0 : 1; - unsigned int BLOCK_ARB_RD_D1 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int BLOCK_ARB_WR_D0 : 1; - unsigned int BLOCK_ARB_WR_D1 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int TRAIN_DONE_D0 : 1; - unsigned int TRAIN_DONE_D1 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_WAKEUP_EDGE__SI__CI { - struct { - unsigned int D0_ARF_WAKEUP : 1; - unsigned int D1_ARF_WAKEUP : 1; - unsigned int D0_REDC_WAKEUP : 1; - unsigned int D1_REDC_WAKEUP : 1; - unsigned int D0_WEDC_WAKEUP : 1; - unsigned int D1_WEDC_WAKEUP : 1; - unsigned int MCLK_FREQ_CHANGE_WAKEUP : 1; - unsigned int SCLK_SRBM_READY_WAKEUP : 1; - unsigned int D0_CMD_FIFO_READY_WAKEUP : 1; - unsigned int D1_CMD_FIFO_READY_WAKEUP : 1; - unsigned int D0_DATA_FIFO_READY_WAKEUP : 1; - unsigned int D1_DATA_FIFO_READY_WAKEUP : 1; - unsigned int SOFTWARE_WAKEUP_WAKEUP : 1; - unsigned int RESERVE0_WAKEUP : 1; - unsigned int TSM_DONE_WAKEUP : 1; - unsigned int TIMER_DONE_WAKEUP : 1; - unsigned int : 1; - unsigned int TCG_DONE_WAKEUP : 1; - unsigned int ALLOWSTOP0_WAKEUP : 1; - unsigned int ALLOWSTOP1_WAKEUP : 1; - unsigned int DPM_WAKEUP : 1; - unsigned int ALLOWSTOPB0_WAKEUP : 1; - unsigned int ALLOWSTOPB1_WAKEUP : 1; - unsigned int DPM_LPT_WAKEUP : 1; - unsigned int D0_IDLEH_WAKEUP : 1; - unsigned int D1_IDLEH_WAKEUP : 1; - unsigned int PHY_PG_WAKEUP__CI : 1; - unsigned int SREG_WAKEUP__CI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_WAKEUP_EDGE__VI { - struct { - unsigned int D0_IDLEH_WAKEUP : 1; - unsigned int D1_IDLEH_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SCLK_SRBM_READY_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SOFTWARE_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int TIMER_DONE_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_WAKEUP_MASK__SI__CI { - struct { - unsigned int D0_ARF_WAKEUP : 1; - unsigned int D1_ARF_WAKEUP : 1; - unsigned int D0_REDC_WAKEUP : 1; - unsigned int D1_REDC_WAKEUP : 1; - unsigned int D0_WEDC_WAKEUP : 1; - unsigned int D1_WEDC_WAKEUP : 1; - unsigned int MCLK_FREQ_CHANGE_WAKEUP : 1; - unsigned int SCLK_SRBM_READY_WAKEUP : 1; - unsigned int D0_CMD_FIFO_READY_WAKEUP : 1; - unsigned int D1_CMD_FIFO_READY_WAKEUP : 1; - unsigned int D0_DATA_FIFO_READY_WAKEUP : 1; - unsigned int D1_DATA_FIFO_READY_WAKEUP : 1; - unsigned int SOFTWARE_WAKEUP_WAKEUP : 1; - unsigned int RESERVE0_WAKEUP : 1; - unsigned int TSM_DONE_WAKEUP : 1; - unsigned int TIMER_DONE_WAKEUP : 1; - unsigned int : 1; - unsigned int TCG_DONE_WAKEUP : 1; - unsigned int ALLOWSTOP0_WAKEUP : 1; - unsigned int ALLOWSTOP1_WAKEUP : 1; - unsigned int DPM_WAKEUP : 1; - unsigned int ALLOWSTOPB0_WAKEUP : 1; - unsigned int ALLOWSTOPB1_WAKEUP : 1; - unsigned int DPM_LPT_WAKEUP : 1; - unsigned int D0_IDLEH_WAKEUP : 1; - unsigned int D1_IDLEH_WAKEUP : 1; - unsigned int PHY_PG_WAKEUP__CI : 1; - unsigned int SREG_WAKEUP__CI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TRAIN_WAKEUP_MASK__VI { - struct { - unsigned int D0_IDLEH_WAKEUP : 1; - unsigned int D1_IDLEH_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SCLK_SRBM_READY_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SOFTWARE_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int TIMER_DONE_WAKEUP : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_BCNT__SI__CI { - struct { - unsigned int TRUE_ACT : 4; - unsigned int FALSE_ACT : 4; - unsigned int BCNT_TESTS : 8; - unsigned int COMP_VALUE : 8; - unsigned int DONE_TESTS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_CTRL__SI__CI { - struct { - unsigned int START : 1; - unsigned int CAPTURE_START : 1; - unsigned int DONE : 1; - unsigned int ERR : 1; - unsigned int STEP : 1; - unsigned int DIRECTION : 1; - unsigned int INVERT : 1; - unsigned int MASK_BITS : 1; - unsigned int UPDATE_LOOP : 2; - unsigned int ROT_INV : 1; - unsigned int DUAL_CH_EN__CI : 1; - unsigned int DONE0__CI : 1; - unsigned int DONE1__CI : 1; - unsigned int : 2; - unsigned int POINTER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_DBI__SI__CI { - struct { - unsigned int DBI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_DEBUG_DATA__SI__CI { - struct { - unsigned int TSM_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_DEBUG_INDEX__SI__CI { - struct { - unsigned int TSM_DEBUG_INDEX : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_EDC__SI__CI { - struct { - unsigned int EDC : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_FLAG__SI__CI { - struct { - unsigned int TRUE_ACT : 4; - unsigned int FALSE_ACT : 4; - unsigned int FLAG_TESTS : 8; - unsigned int NBBL_MASK : 4; - unsigned int : 4; - unsigned int ERROR_TESTS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_GCNT__SI__CI { - struct { - unsigned int TRUE_ACT : 4; - unsigned int FALSE_ACT : 4; - unsigned int TESTS : 8; - unsigned int COMP_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_MISC__SI__CI { - struct { - unsigned int WCDR_PTR : 16; - unsigned int WCDR_MASK : 4; - unsigned int CH1_OFFSET__CI : 6; - unsigned int CH1_WCDR_OFFSET__CI : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_NCNT__SI__CI { - struct { - unsigned int TRUE_ACT : 4; - unsigned int FALSE_ACT : 4; - unsigned int TESTS : 8; - unsigned int RANGE_LOW : 4; - unsigned int RANGE_HIGH : 4; - unsigned int NIBBLE_SKIP : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_OCNT__SI__CI { - struct { - unsigned int TRUE_ACT : 4; - unsigned int FALSE_ACT : 4; - unsigned int TESTS : 8; - unsigned int CMP_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_UPDATE__SI__CI { - struct { - unsigned int TRUE_ACT : 4; - unsigned int FALSE_ACT : 4; - unsigned int UPDT_TESTS : 8; - unsigned int AREF_COUNT : 8; - unsigned int CAPTR_TESTS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TSM_WCDR__SI__CI { - struct { - unsigned int WCDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_BYTE0_D0__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_BYTE0_D1__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_BYTE1_D0__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_BYTE1_D1__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_BYTE2_D0__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_BYTE2_D1__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_BYTE3_D0__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_BYTE3_D1__SI__CI { - struct { - unsigned int DQ0 : 4; - unsigned int DQ1 : 4; - unsigned int DQ2 : 4; - unsigned int DQ3 : 4; - unsigned int DQ4 : 4; - unsigned int DQ5 : 4; - unsigned int DQ6 : 4; - unsigned int DQ7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_DBI_D0__SI__CI { - struct { - unsigned int DBI0 : 4; - unsigned int DBI1 : 4; - unsigned int DBI2 : 4; - unsigned int DBI3 : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_DBI_D1__SI__CI { - struct { - unsigned int DBI0 : 4; - unsigned int DBI1 : 4; - unsigned int DBI2 : 4; - unsigned int DBI3 : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_EDC_D0__SI__CI { - struct { - unsigned int EDC0 : 4; - unsigned int EDC1 : 4; - unsigned int EDC2 : 4; - unsigned int EDC3 : 4; - unsigned int WCDR0 : 4; - unsigned int WCDR1 : 4; - unsigned int WCDR2 : 4; - unsigned int WCDR3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_EDC_D1__SI__CI { - struct { - unsigned int EDC0 : 4; - unsigned int EDC1 : 4; - unsigned int EDC2 : 4; - unsigned int EDC3 : 4; - unsigned int WCDR0 : 4; - unsigned int WCDR1 : 4; - unsigned int WCDR2 : 4; - unsigned int WCDR3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_FCK_D0__SI__CI { - struct { - unsigned int FCK0 : 4; - unsigned int FCK1 : 4; - unsigned int FCK2 : 4; - unsigned int FCK3 : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_TXFRAMING_FCK_D1__SI__CI { - struct { - unsigned int FCK0 : 4; - unsigned int FCK1 : 4; - unsigned int FCK2 : 4; - unsigned int FCK3 : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_VENDOR_ID_I0__SI__CI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_VENDOR_ID_I1__SI__CI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_WCDR_CTRL__SI__CI { - struct { - unsigned int WCDR_PRE : 8; - unsigned int WCDR_TIM : 4; - unsigned int WR_EN : 1; - unsigned int RD_EN : 1; - unsigned int AREF_EN : 1; - unsigned int TRAIN_EN : 1; - unsigned int TWCDRL : 4; - unsigned int PRBS_EN : 1; - unsigned int PRBS_RST : 1; - unsigned int : 2; - unsigned int PREAMBLE : 4; - unsigned int PRE_MASK : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_WR_CTL_2__SI__CI { - struct { - unsigned int DAT_DLY_H_D0 : 1; - unsigned int DQS_DLY_H_D0 : 1; - unsigned int OEN_DLY_H_D0 : 1; - unsigned int DAT_DLY_H_D1 : 1; - unsigned int DQS_DLY_H_D1 : 1; - unsigned int OEN_DLY_H_D1 : 1; - unsigned int WCDR_EN : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_WR_CTL_2_LP__SI__CI { - struct { - unsigned int DAT_DLY_H_D0 : 1; - unsigned int DQS_DLY_H_D0 : 1; - unsigned int OEN_DLY_H_D0 : 1; - unsigned int DAT_DLY_H_D1 : 1; - unsigned int DQS_DLY_H_D1 : 1; - unsigned int OEN_DLY_H_D1 : 1; - unsigned int WCDR_EN : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_WR_CTL_D0__SI__CI { - struct { - unsigned int DAT_DLY : 4; - unsigned int DQS_DLY : 4; - unsigned int DQS_XTR : 1; - unsigned int DAT_2Y_DLY : 1; - unsigned int ADR_2Y_DLY : 1; - unsigned int CMD_2Y_DLY : 1; - unsigned int OEN_DLY : 4; - unsigned int OEN_EXT : 4; - unsigned int OEN_SEL : 2; - unsigned int : 2; - unsigned int ODT_DLY : 4; - unsigned int ODT_EXT : 1; - unsigned int ADR_DLY : 1; - unsigned int CMD_DLY : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_WR_CTL_D0__VI { - struct { - unsigned int DAT_DLY : 5; - unsigned int DQS_DLY : 5; - unsigned int DQS_XTR : 1; - unsigned int OEN_DLY : 5; - unsigned int OEN_EXT : 4; - unsigned int OEN_SEL : 2; - unsigned int CMD_DLY : 1; - unsigned int ADR_DLY : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_WR_CTL_D0_LP__SI__CI { - struct { - unsigned int DAT_DLY : 4; - unsigned int DQS_DLY : 4; - unsigned int DQS_XTR : 1; - unsigned int DAT_2Y_DLY : 1; - unsigned int ADR_2Y_DLY : 1; - unsigned int CMD_2Y_DLY : 1; - unsigned int OEN_DLY : 4; - unsigned int OEN_EXT : 4; - unsigned int OEN_SEL : 2; - unsigned int : 2; - unsigned int ODT_DLY : 4; - unsigned int ODT_EXT : 1; - unsigned int ADR_DLY : 1; - unsigned int CMD_DLY : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_WR_CTL_D0_LP__VI { - struct { - unsigned int DAT_DLY : 5; - unsigned int DQS_DLY : 5; - unsigned int DQS_XTR : 1; - unsigned int OEN_DLY : 5; - unsigned int OEN_EXT : 4; - unsigned int OEN_SEL : 2; - unsigned int CMD_DLY : 1; - unsigned int ADR_DLY : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_WR_CTL_D1__SI__CI { - struct { - unsigned int DAT_DLY : 4; - unsigned int DQS_DLY : 4; - unsigned int DQS_XTR : 1; - unsigned int DAT_2Y_DLY : 1; - unsigned int ADR_2Y_DLY : 1; - unsigned int CMD_2Y_DLY : 1; - unsigned int OEN_DLY : 4; - unsigned int OEN_EXT : 4; - unsigned int OEN_SEL : 2; - unsigned int : 2; - unsigned int ODT_DLY : 4; - unsigned int ODT_EXT : 1; - unsigned int ADR_DLY : 1; - unsigned int CMD_DLY : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_WR_CTL_D1__VI { - struct { - unsigned int DAT_DLY : 5; - unsigned int DQS_DLY : 5; - unsigned int DQS_XTR : 1; - unsigned int OEN_DLY : 5; - unsigned int OEN_EXT : 4; - unsigned int OEN_SEL : 2; - unsigned int CMD_DLY : 1; - unsigned int ADR_DLY : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_WR_CTL_D1_LP__SI__CI { - struct { - unsigned int DAT_DLY : 4; - unsigned int DQS_DLY : 4; - unsigned int DQS_XTR : 1; - unsigned int DAT_2Y_DLY : 1; - unsigned int ADR_2Y_DLY : 1; - unsigned int CMD_2Y_DLY : 1; - unsigned int OEN_DLY : 4; - unsigned int OEN_EXT : 4; - unsigned int OEN_SEL : 2; - unsigned int : 2; - unsigned int ODT_DLY : 4; - unsigned int ODT_EXT : 1; - unsigned int ADR_DLY : 1; - unsigned int CMD_DLY : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_WR_CTL_D1_LP__VI { - struct { - unsigned int DAT_DLY : 5; - unsigned int DQS_DLY : 5; - unsigned int DQS_XTR : 1; - unsigned int OEN_DLY : 5; - unsigned int OEN_EXT : 4; - unsigned int OEN_SEL : 2; - unsigned int CMD_DLY : 1; - unsigned int ADR_DLY : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SHARED_BLACKOUT_CNTL__SI__CI { - struct { - unsigned int BLACKOUT_MODE : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SHARED_BLACKOUT_CNTL__VI { - struct { - unsigned int BLACKOUT_MODE : 3; - unsigned int BLACKOUT_SEQ_FREE : 1; - unsigned int BLACKOUT_MCD_NUM : 8; - unsigned int FREE_TIE_HIGH : 1; - unsigned int SRBM_DUMMY_READ_RETURN : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SHARED_CHMAP { - struct { - unsigned int CHAN0 : 4; - unsigned int CHAN1 : 4; - unsigned int CHAN2 : 4; - unsigned int NOOFCHAN : 4; - unsigned int CHAN3__VI : 4; - unsigned int CHAN4__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SHARED_CHREMAP__SI__CI { - struct { - unsigned int CHAN0 : 3; - unsigned int CHAN1 : 3; - unsigned int CHAN2 : 3; - unsigned int CHAN3 : 3; - unsigned int CHAN4 : 3; - unsigned int CHAN5 : 3; - unsigned int CHAN6 : 3; - unsigned int CHAN7 : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SHARED_CHREMAP__VI { - struct { - unsigned int CHAN0 : 4; - unsigned int CHAN1 : 4; - unsigned int CHAN2 : 4; - unsigned int CHAN3 : 4; - unsigned int CHAN4 : 4; - unsigned int CHAN5 : 4; - unsigned int CHAN6 : 4; - unsigned int CHAN7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TRAIN_EDCCDR_R_D0__SI__CI { - struct { - unsigned int EDC0 : 8; - unsigned int EDC1 : 8; - unsigned int EDC2 : 8; - unsigned int EDC3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TRAIN_EDCCDR_R_D1__SI__CI { - struct { - unsigned int EDC0 : 8; - unsigned int EDC1 : 8; - unsigned int EDC2 : 8; - unsigned int EDC3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TRAIN_EDC_STATUS_D0__SI__CI { - struct { - unsigned int WEDC_CNT : 16; - unsigned int REDC_CNT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TRAIN_EDC_STATUS_D1__SI__CI { - struct { - unsigned int WEDC_CNT : 16; - unsigned int REDC_CNT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TRAIN_PRBSERR_0_D0__SI__CI { - struct { - unsigned int DQ_STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TRAIN_PRBSERR_0_D1__SI__CI { - struct { - unsigned int DQ_STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TRAIN_PRBSERR_1_D0__SI__CI { - struct { - unsigned int DBI_STATUS : 4; - unsigned int EDC_STATUS : 4; - unsigned int WCK_STATUS : 4; - unsigned int WCDR_STATUS : 4; - unsigned int : 12; - unsigned int PMA_PRBSCLR : 1; - unsigned int PMD0_PRBSCLR : 1; - unsigned int PMD1_PRBSCLR : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TRAIN_PRBSERR_1_D1__SI__CI { - struct { - unsigned int DBI_STATUS : 4; - unsigned int EDC_STATUS : 4; - unsigned int WCK_STATUS : 4; - unsigned int WCDR_STATUS : 4; - unsigned int : 12; - unsigned int PMA_PRBSCLR : 1; - unsigned int PMD0_PRBSCLR : 1; - unsigned int PMD1_PRBSCLR : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TRAIN_PRBSERR_2_D0__SI__CI { - struct { - unsigned int CK_STATUS : 1; - unsigned int CKB_STATUS : 1; - unsigned int : 2; - unsigned int CS_STATUS : 2; - unsigned int : 2; - unsigned int CKE_STATUS : 1; - unsigned int RAS_STATUS : 1; - unsigned int CAS_STATUS : 1; - unsigned int WE_STATUS : 1; - unsigned int : 4; - unsigned int ADDR_STATUS : 10; - unsigned int : 2; - unsigned int ABI_STATUS : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TRAIN_PRBSERR_2_D1__SI__CI { - struct { - unsigned int CK_STATUS : 1; - unsigned int CKB_STATUS : 1; - unsigned int : 2; - unsigned int CS_STATUS : 2; - unsigned int : 2; - unsigned int CKE_STATUS : 1; - unsigned int RAS_STATUS : 1; - unsigned int CAS_STATUS : 1; - unsigned int WE_STATUS : 1; - unsigned int : 4; - unsigned int ADDR_STATUS : 10; - unsigned int : 2; - unsigned int ABI_STATUS : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BCNT0__SI__CI { - struct { - unsigned int BYTE0 : 8; - unsigned int BYTE1 : 8; - unsigned int BYTE2 : 8; - unsigned int BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BCNT1__SI__CI { - struct { - unsigned int BYTE0 : 8; - unsigned int BYTE1 : 8; - unsigned int BYTE2 : 8; - unsigned int BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BCNT10__SI__CI { - struct { - unsigned int BYTE0 : 8; - unsigned int BYTE1 : 8; - unsigned int BYTE2 : 8; - unsigned int BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BCNT2__SI__CI { - struct { - unsigned int BYTE0 : 8; - unsigned int BYTE1 : 8; - unsigned int BYTE2 : 8; - unsigned int BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BCNT3__SI__CI { - struct { - unsigned int BYTE0 : 8; - unsigned int BYTE1 : 8; - unsigned int BYTE2 : 8; - unsigned int BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BCNT4__SI__CI { - struct { - unsigned int BYTE0 : 8; - unsigned int BYTE1 : 8; - unsigned int BYTE2 : 8; - unsigned int BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BCNT5__SI__CI { - struct { - unsigned int BYTE0 : 8; - unsigned int BYTE1 : 8; - unsigned int BYTE2 : 8; - unsigned int BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BCNT6__SI__CI { - struct { - unsigned int BYTE0 : 8; - unsigned int BYTE1 : 8; - unsigned int BYTE2 : 8; - unsigned int BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BCNT7__SI__CI { - struct { - unsigned int BYTE0 : 8; - unsigned int BYTE1 : 8; - unsigned int BYTE2 : 8; - unsigned int BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BCNT8__SI__CI { - struct { - unsigned int BYTE0 : 8; - unsigned int BYTE1 : 8; - unsigned int BYTE2 : 8; - unsigned int BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BCNT9__SI__CI { - struct { - unsigned int BYTE0 : 8; - unsigned int BYTE1 : 8; - unsigned int BYTE2 : 8; - unsigned int BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_BKPT__SI__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_FLAG__SI__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_GCNT__SI__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_MISC__SI__CI { - struct { - unsigned int FLAG : 8; - unsigned int NCNT_RD : 4; - unsigned int NCNT_WR : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_ST01__SI__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_ST23__SI__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_TSM_DEBUG_ST45__SI__CI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_AGP_BASE { - struct { - unsigned int AGP_BASE : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_AGP_BOT { - struct { - unsigned int AGP_BOT : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_AGP_TOP { - struct { - unsigned int AGP_TOP : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_DC_WRITE_CNTL { - struct { - unsigned int DC_WRITE_HIT_REGION_0_MODE : 2; - unsigned int DC_WRITE_HIT_REGION_1_MODE : 2; - unsigned int DC_WRITE_HIT_REGION_2_MODE : 2; - unsigned int DC_WRITE_HIT_REGION_3_MODE : 2; - unsigned int DC_MEMORY_WRITE_LOCAL : 1; - unsigned int DC_MEMORY_WRITE_SYSTEM : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR { - struct { - unsigned int PHYSICAL_ADDRESS : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR { - struct { - unsigned int PHYSICAL_ADDRESS : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR { - struct { - unsigned int PHYSICAL_ADDRESS : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR { - struct { - unsigned int PHYSICAL_ADDRESS : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR { - struct { - unsigned int PHYSICAL_ADDRESS : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR { - struct { - unsigned int PHYSICAL_ADDRESS : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR { - struct { - unsigned int PHYSICAL_ADDRESS : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR { - struct { - unsigned int PHYSICAL_ADDRESS : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_LOCATION { - struct { - unsigned int FB_BASE : 16; - unsigned int FB_TOP : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_OFFSET { - struct { - unsigned int FB_OFFSET : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_L2_PERFCOUNTER0_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_L2_PERFCOUNTER1_CFG__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_L2_PERFCOUNTER_HI__CI__VI { - struct { - unsigned int COUNTER_HI : 16; - unsigned int COMPARE_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_L2_PERFCOUNTER_LO__CI__VI { - struct { - unsigned int COUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CI__VI { - struct { - unsigned int PERF_COUNTER_SELECT : 4; - unsigned int : 4; - unsigned int START_TRIGGER : 8; - unsigned int STOP_TRIGGER : 8; - unsigned int ENABLE_ANY : 1; - unsigned int CLEAR_ALL : 1; - unsigned int STOP_ALL_ON_SATURATE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLB0_DEBUG { - struct { - unsigned int INVALIDATE_L1_TLB : 1; - unsigned int : 7; - unsigned int SEND_FREE_AT_RTN : 1; - unsigned int EFFECTIVE_L1_TLB_SIZE : 3; - unsigned int EFFECTIVE_L1_QUEUE_SIZE : 3; - unsigned int L1_TLB_DEBUG : 4; - unsigned int L1_TLB_FORCE_MISS__CI__VI : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLB0_STATUS { - struct { - unsigned int BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLB1_STATUS { - struct { - unsigned int BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLB2_DEBUG { - struct { - unsigned int INVALIDATE_L1_TLB : 1; - unsigned int : 7; - unsigned int SEND_FREE_AT_RTN : 1; - unsigned int EFFECTIVE_L1_TLB_SIZE : 3; - unsigned int EFFECTIVE_L1_QUEUE_SIZE : 3; - unsigned int L1_TLB_DEBUG : 4; - unsigned int L1_TLB_FORCE_MISS__CI__VI : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLB2_STATUS { - struct { - unsigned int BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLB3_DEBUG { - struct { - unsigned int INVALIDATE_L1_TLB : 1; - unsigned int : 7; - unsigned int SEND_FREE_AT_RTN : 1; - unsigned int EFFECTIVE_L1_TLB_SIZE : 3; - unsigned int EFFECTIVE_L1_QUEUE_SIZE : 3; - unsigned int L1_TLB_DEBUG : 4; - unsigned int L1_TLB_FORCE_MISS__CI__VI : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLB3_STATUS { - struct { - unsigned int BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L2ARBITER_L2_CREDITS { - struct { - unsigned int L2_IF_CREDITS : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MD_L1_TLB0_DEBUG { - struct { - unsigned int INVALIDATE_L1_TLB : 1; - unsigned int : 7; - unsigned int SEND_FREE_AT_RTN : 1; - unsigned int EFFECTIVE_L1_TLB_SIZE : 3; - unsigned int EFFECTIVE_L1_QUEUE_SIZE : 3; - unsigned int L1_TLB_DEBUG : 4; - unsigned int L1_TLB_FORCE_MISS__CI__VI : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MD_L1_TLB0_STATUS { - struct { - unsigned int BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MD_L1_TLB1_DEBUG { - struct { - unsigned int INVALIDATE_L1_TLB : 1; - unsigned int : 7; - unsigned int SEND_FREE_AT_RTN : 1; - unsigned int EFFECTIVE_L1_TLB_SIZE : 3; - unsigned int EFFECTIVE_L1_QUEUE_SIZE : 3; - unsigned int L1_TLB_DEBUG : 4; - unsigned int L1_TLB_FORCE_MISS__CI__VI : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MD_L1_TLB1_STATUS { - struct { - unsigned int BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MD_L1_TLB2_DEBUG { - struct { - unsigned int INVALIDATE_L1_TLB : 1; - unsigned int : 7; - unsigned int SEND_FREE_AT_RTN : 1; - unsigned int EFFECTIVE_L1_TLB_SIZE : 3; - unsigned int EFFECTIVE_L1_QUEUE_SIZE : 3; - unsigned int L1_TLB_DEBUG : 4; - unsigned int L1_TLB_FORCE_MISS__CI__VI : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MD_L1_TLB2_STATUS { - struct { - unsigned int BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MD_L1_TLB3_DEBUG { - struct { - unsigned int INVALIDATE_L1_TLB : 1; - unsigned int : 7; - unsigned int SEND_FREE_AT_RTN : 1; - unsigned int EFFECTIVE_L1_TLB_SIZE : 3; - unsigned int EFFECTIVE_L1_QUEUE_SIZE : 3; - unsigned int L1_TLB_DEBUG : 4; - unsigned int L1_TLB_FORCE_MISS__CI__VI : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MD_L1_TLB3_STATUS { - struct { - unsigned int BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MD_L2ARBITER_L2_CREDITS { - struct { - unsigned int L2_IF_CREDITS : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MX_L1_TLB_CNTL { - struct { - unsigned int ENABLE_L1_TLB : 1; - unsigned int ENABLE_L1_FRAGMENT_PROCESSING : 1; - unsigned int : 1; - unsigned int SYSTEM_ACCESS_MODE : 2; - unsigned int SYSTEM_APERTURE_UNMAPPED_ACCESS : 1; - unsigned int ENABLE_ADVANCED_DRIVER_MODEL : 1; - unsigned int ECO_BITS : 4; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_STEERING__CI__VI { - struct { - unsigned int DEFAULT_STEERING : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_SYSTEM_APERTURE_HIGH_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_SYSTEM_APERTURE_LOW_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_CB { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAX_BURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_DB { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAX_BURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_GRP_EXT { - struct { - unsigned int DBSTEN0 : 4; - unsigned int TC0 : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_GRP_GFX__CI { - struct { - unsigned int CP : 4; - unsigned int SH : 4; - unsigned int ACPG : 4; - unsigned int ACPO : 4; - unsigned int XDMA : 4; - unsigned int XDMAM : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_GRP_GFX__VI { - struct { - unsigned int CP : 4; - unsigned int SH : 4; - unsigned int ACPG : 4; - unsigned int ACPO : 4; - unsigned int ISP : 4; - unsigned int VP8 : 4; - unsigned int XDMA : 4; - unsigned int XDMAM : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_GRP_GFX__SI { - struct { - unsigned int CP : 4; - unsigned int : 4; - unsigned int : 4; - unsigned int XDMA : 4; - unsigned int XDMAM : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_GRP_LCL { - struct { - unsigned int CB0 : 4; - unsigned int CBCMASK0 : 4; - unsigned int CBFMASK0 : 4; - unsigned int DB0 : 4; - unsigned int DBHTILE0 : 4; - unsigned int SX0 : 4; - unsigned int : 4; - unsigned int CBIMMED0 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_GRP_OTH__CI__VI { - struct { - unsigned int UVD_EXT0 : 4; - unsigned int SDMA0 : 4; - unsigned int HDP : 4; - unsigned int SEM : 4; - unsigned int UMC : 4; - unsigned int UVD : 4; - unsigned int XDP : 4; - unsigned int UVD_EXT1 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_GRP_OTH__SI { - struct { - unsigned int UVD_EXT0 : 4; - unsigned int : 4; - unsigned int HDP : 4; - unsigned int SEM : 4; - unsigned int UMC : 4; - unsigned int UVD : 4; - unsigned int XDP : 4; - unsigned int UVD_EXT1 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_GRP_SYS__CI { - struct { - unsigned int IH : 4; - unsigned int MCIF : 4; - unsigned int RLC : 4; - unsigned int SAM : 4; - unsigned int SMU : 4; - unsigned int SDMA1 : 4; - unsigned int VCE : 4; - unsigned int VCEU : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_GRP_SYS__VI { - struct { - unsigned int IH : 4; - unsigned int MCIF : 4; - unsigned int RLC : 4; - unsigned int SAMMSP : 4; - unsigned int SMU : 4; - unsigned int SDMA1 : 4; - unsigned int VCE : 4; - unsigned int VCEU : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_GRP_SYS__SI { - struct { - unsigned int IH : 4; - unsigned int MCIF : 4; - unsigned int RLC : 4; - unsigned int : 4; - unsigned int : 4; - unsigned int SMU : 4; - unsigned int VCE : 4; - unsigned int VCEU : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_HUB { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAX_BURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_TC0 { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAX_BURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_WR_TC1 { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAX_BURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_ADDR_DEC { - struct { - unsigned int NO_DIV_BY_3 : 1; - unsigned int GECC : 1; - unsigned int RB_SPLIT : 1; - unsigned int RB_SPLIT_COLHI : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_ARB { - struct { - unsigned int HUBRD_HIGHEST : 1; - unsigned int DISABLE_HUB_STALL_HIGHEST : 1; - unsigned int BREAK_BURST_CID_CHANGE : 1; - unsigned int ACP_RDRET_URG__VI : 1; - unsigned int HDP_RDRET_URG__VI : 1; - unsigned int BREAK_BURST_BY_URG__VI : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_ARB_MAX_BURST { - struct { - unsigned int RD_PORT0 : 4; - unsigned int RD_PORT1 : 4; - unsigned int RD_PORT2 : 4; - unsigned int RD_PORT3 : 4; - unsigned int WR_PORT0 : 4; - unsigned int WR_PORT1 : 4; - unsigned int WR_PORT2 : 4; - unsigned int WR_PORT3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_CHTRIREMAP { - struct { - unsigned int CH0 : 2; - unsigned int CH1 : 2; - unsigned int CH2 : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_PERF_MON_CNTL0__SI__CI { - struct { - unsigned int START_THRESH : 12; - unsigned int STOP_THRESH : 12; - unsigned int START_MODE : 2; - unsigned int STOP_MODE : 2; - unsigned int ALLOW_WRAP : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_PERF_MON_CNTL1__SI__CI { - struct { - unsigned int THRESH_CNTR_ID : 8; - unsigned int START_TRIG_ID : 8; - unsigned int STOP_TRIG_ID : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_PERF_MON_CNTL2__SI__CI { - struct { - unsigned int MON0_ID : 8; - unsigned int MON1_ID : 8; - unsigned int MON2_ID : 8; - unsigned int MON3_ID : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_PERF_MON_MAX_THSH__SI__CI { - struct { - unsigned int MON0 : 8; - unsigned int MON1 : 8; - unsigned int MON2 : 8; - unsigned int MON3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_PERF_MON_RSLT0__SI__CI { - struct { - unsigned int COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_PERF_MON_RSLT1__SI__CI { - struct { - unsigned int COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_PERF_MON_RSLT2__SI__CI { - struct { - unsigned int COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_PERF_MON_RSLT3__SI__CI { - struct { - unsigned int COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_RDREQ_CREDIT { - struct { - unsigned int OUT0 : 8; - unsigned int OUT1 : 8; - unsigned int OUT2 : 8; - unsigned int OUT3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_RDREQ_PRI_CREDIT { - struct { - unsigned int OUT0 : 8; - unsigned int OUT1 : 8; - unsigned int OUT2 : 8; - unsigned int OUT3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_RDRET_CREDIT1 { - struct { - unsigned int OUT0 : 8; - unsigned int OUT1 : 8; - unsigned int OUT2 : 8; - unsigned int OUT3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_RDRET_CREDIT2 { - struct { - unsigned int OUT4 : 8; - unsigned int OUT5 : 8; - unsigned int HUB_LP_RDRET_SKID : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_RDRET_PRI_CREDIT1 { - struct { - unsigned int OUT0 : 8; - unsigned int OUT1 : 8; - unsigned int OUT2 : 8; - unsigned int OUT3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_RDRET_PRI_CREDIT2 { - struct { - unsigned int OUT4 : 8; - unsigned int OUT5 : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_REMOTE { - struct { - unsigned int WRREQ_EN_GOQ : 1; - unsigned int RDREQ_EN_GOQ : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_SPARE0 { - struct { - unsigned int BIT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_SPARE1 { - struct { - unsigned int BIT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_TWOCHAN { - struct { - unsigned int DISABLE_ONEPORT : 1; - unsigned int CH0 : 2; - unsigned int CH1 : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_WRREQ_CREDIT { - struct { - unsigned int OUT0 : 8; - unsigned int OUT1 : 8; - unsigned int OUT2 : 8; - unsigned int OUT3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_WRRET_CREDIT1 { - struct { - unsigned int OUT0 : 8; - unsigned int OUT1 : 8; - unsigned int OUT2 : 8; - unsigned int OUT3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_WRRET_CREDIT2 { - struct { - unsigned int OUT4 : 8; - unsigned int OUT5 : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG0 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG1 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG10 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG11 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG12 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG13 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG14 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG15 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG16 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG17 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG18 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG19 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG2 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG20 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG21 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG22 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG23 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG24 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG25 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG26 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG27 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG28 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG29 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG3 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG30 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG31 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG32 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG33 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG34 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG35 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG36 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG4 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG5 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG6 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG7 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG8 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_CFG9 { - struct { - unsigned int WCB_NUM : 4; - unsigned int LB_TYPE : 3; - unsigned int P2P_BAR : 3; - unsigned int HOST_FLUSH : 4; - unsigned int SIDE_FLUSH : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_EXTRA { - struct { - unsigned int CMP0 : 8; - unsigned int MSK0 : 8; - unsigned int VLD0 : 1; - unsigned int CMP1 : 8; - unsigned int VLD1 : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLG_EXTRA_RD { - struct { - unsigned int CMP0 : 8; - unsigned int MSK0 : 8; - unsigned int VLD0 : 1; - unsigned int CMP1 : 8; - unsigned int VLD1 : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_CLK_GAT { - struct { - unsigned int ONDLY : 6; - unsigned int OFFDLY : 6; - unsigned int RDYDLY : 6; - unsigned int ENABLE : 1; - unsigned int MEM_LS_ENABLE : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_INTF_CFG { - struct { - unsigned int RPB_WRREQ_CRD : 8; - unsigned int MC_WRRET_ASK : 8; - unsigned int XSP_REQ_CRD : 7; - unsigned int BIF_REG_SNOOP_SEL : 1; - unsigned int BIF_REG_SNOOP_VAL : 1; - unsigned int BIF_MEM_SNOOP_SEL : 1; - unsigned int BIF_MEM_SNOOP_VAL : 1; - unsigned int XSP_SNOOP_SEL : 2; - unsigned int XSP_SNOOP_VAL : 1; - unsigned int XSP_ORDERING_SEL : 1; - unsigned int XSP_ORDERING_VAL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_INTF_CFG2 { - struct { - unsigned int RPB_RDREQ_CRD : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_INTF_STS { - struct { - unsigned int RPB_WRREQ_CRD : 8; - unsigned int XSP_REQ_CRD : 7; - unsigned int HOP_DATA_BUF_FULL : 1; - unsigned int HOP_ATTR_BUF_FULL : 1; - unsigned int CNS_BUF_FULL : 1; - unsigned int CNS_BUF_BUSY : 1; - unsigned int RPB_RDREQ_CRD : 8; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_LB_ADDR { - struct { - unsigned int CMP0 : 10; - unsigned int MASK0 : 10; - unsigned int CMP1 : 6; - unsigned int MASK1 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_MAP_INVERT_FLUSH_NUM_LSB { - struct { - unsigned int ALTER_FLUSH_NUM : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_MISC_CFG { - struct { - unsigned int FIELDNAME0 : 8; - unsigned int FIELDNAME1 : 8; - unsigned int FIELDNAME2 : 8; - unsigned int FIELDNAME3 : 7; - unsigned int TRIGGERNAME : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR0 { - struct { - unsigned int HOST_FLUSH : 4; - unsigned int REG_SYS_BAR : 4; - unsigned int MEM_SYS_BAR : 4; - unsigned int VALID : 1; - unsigned int SEND_DIS : 1; - unsigned int COMPRESS_DIS : 1; - unsigned int RESERVED : 1; - unsigned int ADDRESS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR1 { - struct { - unsigned int HOST_FLUSH : 4; - unsigned int REG_SYS_BAR : 4; - unsigned int MEM_SYS_BAR : 4; - unsigned int VALID : 1; - unsigned int SEND_DIS : 1; - unsigned int COMPRESS_DIS : 1; - unsigned int RESERVED : 1; - unsigned int ADDRESS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR2 { - struct { - unsigned int HOST_FLUSH : 4; - unsigned int REG_SYS_BAR : 4; - unsigned int MEM_SYS_BAR : 4; - unsigned int VALID : 1; - unsigned int SEND_DIS : 1; - unsigned int COMPRESS_DIS : 1; - unsigned int RESERVED : 1; - unsigned int ADDRESS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR3 { - struct { - unsigned int HOST_FLUSH : 4; - unsigned int REG_SYS_BAR : 4; - unsigned int MEM_SYS_BAR : 4; - unsigned int VALID : 1; - unsigned int SEND_DIS : 1; - unsigned int COMPRESS_DIS : 1; - unsigned int RESERVED : 1; - unsigned int ADDRESS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR4 { - struct { - unsigned int HOST_FLUSH : 4; - unsigned int REG_SYS_BAR : 4; - unsigned int MEM_SYS_BAR : 4; - unsigned int VALID : 1; - unsigned int SEND_DIS : 1; - unsigned int COMPRESS_DIS : 1; - unsigned int RESERVED : 1; - unsigned int ADDRESS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR5 { - struct { - unsigned int HOST_FLUSH : 4; - unsigned int REG_SYS_BAR : 4; - unsigned int MEM_SYS_BAR : 4; - unsigned int VALID : 1; - unsigned int SEND_DIS : 1; - unsigned int COMPRESS_DIS : 1; - unsigned int RESERVED : 1; - unsigned int ADDRESS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR6 { - struct { - unsigned int HOST_FLUSH : 4; - unsigned int REG_SYS_BAR : 4; - unsigned int MEM_SYS_BAR : 4; - unsigned int VALID : 1; - unsigned int SEND_DIS : 1; - unsigned int COMPRESS_DIS : 1; - unsigned int RESERVED : 1; - unsigned int ADDRESS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR7 { - struct { - unsigned int HOST_FLUSH : 4; - unsigned int REG_SYS_BAR : 4; - unsigned int MEM_SYS_BAR : 4; - unsigned int VALID : 1; - unsigned int SEND_DIS : 1; - unsigned int COMPRESS_DIS : 1; - unsigned int RESERVED : 1; - unsigned int ADDRESS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR_CFG { - struct { - unsigned int ADDR_SIZE : 4; - unsigned int SEND_BAR : 2; - unsigned int SNOOP : 1; - unsigned int SEND_DIS : 1; - unsigned int COMPRESS_DIS : 1; - unsigned int UPDATE_DIS : 1; - unsigned int REGBAR_FROM_SYSBAR : 1; - unsigned int RD_EN : 1; - unsigned int ATC_TRANSLATED : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR_DEBUG { - struct { - unsigned int SEL : 8; - unsigned int HOST_FLUSH : 4; - unsigned int MEM_SYS_BAR : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR_DELTA_ABOVE { - struct { - unsigned int EN : 8; - unsigned int DELTA : 20; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR_DELTA_BELOW { - struct { - unsigned int EN : 8; - unsigned int DELTA : 20; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_P2P_BAR_SETUP { - struct { - unsigned int SEL : 8; - unsigned int REG_SYS_BAR : 4; - unsigned int VALID : 1; - unsigned int SEND_DIS : 1; - unsigned int COMPRESS_DIS : 1; - unsigned int RESERVED : 1; - unsigned int ADDRESS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PEER_SYS_BAR0 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PEER_SYS_BAR1 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PEER_SYS_BAR2 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PEER_SYS_BAR3 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PEER_SYS_BAR4 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PEER_SYS_BAR5 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PEER_SYS_BAR6 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PEER_SYS_BAR7 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PEER_SYS_BAR8 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PEER_SYS_BAR9 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PERF_KNOBS { - struct { - unsigned int CNS_FIFO_DEPTH : 6; - unsigned int WCB_HST_FIFO_DEPTH : 6; - unsigned int WCB_SID_FIFO_DEPTH : 6; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_PIPE_STS { - struct { - unsigned int WCB_ANY_PBUF : 1; - unsigned int WCB_HST_DATA_BUF_CNT : 7; - unsigned int WCB_SID_DATA_BUF_CNT : 7; - unsigned int WCB_HST_RD_PTR_BUF_FULL : 1; - unsigned int WCB_SID_RD_PTR_BUF_FULL : 1; - unsigned int WCB_HST_REQ_FIFO_FULL : 1; - unsigned int WCB_SID_REQ_FIFO_FULL : 1; - unsigned int WCB_HST_REQ_OBUF_FULL : 1; - unsigned int WCB_SID_REQ_OBUF_FULL : 1; - unsigned int WCB_HST_DATA_OBUF_FULL : 1; - unsigned int WCB_SID_DATA_OBUF_FULL : 1; - unsigned int RET_BUF_FULL : 1; - unsigned int XPB_CLK_BUSY_BITS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_DEST_MAP0 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_DEST_MAP1 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_DEST_MAP2 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_DEST_MAP3 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_DEST_MAP4 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_DEST_MAP5 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_DEST_MAP6 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_DEST_MAP7 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_DEST_MAP8 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_DEST_MAP9 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_SRC_APRTR0 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_SRC_APRTR1 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_SRC_APRTR2 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_SRC_APRTR3 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_SRC_APRTR4 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_SRC_APRTR5 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_SRC_APRTR6 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_SRC_APRTR7 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_SRC_APRTR8 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_RTR_SRC_APRTR9 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_STICKY { - struct { - unsigned int BITS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_STICKY_W1C { - struct { - unsigned int BITS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_SUB_CTRL { - struct { - unsigned int WRREQ_BYPASS_XPB : 1; - unsigned int STALL_CNS_RTR_REQ : 1; - unsigned int STALL_RTR_RPB_WRREQ : 1; - unsigned int STALL_RTR_MAP_REQ : 1; - unsigned int STALL_MAP_WCB_REQ : 1; - unsigned int STALL_WCB_SID_REQ : 1; - unsigned int STALL_MC_XSP_REQ_SEND : 1; - unsigned int STALL_WCB_HST_REQ : 1; - unsigned int STALL_HST_HOP_REQ : 1; - unsigned int STALL_XPB_RPB_REQ_ATTR : 1; - unsigned int RESET_CNS : 1; - unsigned int RESET_RTR : 1; - unsigned int RESET_RET : 1; - unsigned int RESET_MAP : 1; - unsigned int RESET_WCB : 1; - unsigned int RESET_HST : 1; - unsigned int RESET_HOP : 1; - unsigned int RESET_SID : 1; - unsigned int RESET_SRB : 1; - unsigned int RESET_CGR : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_UNC_THRESH_HST { - struct { - unsigned int CHANGE_PREF : 6; - unsigned int STRONG_PREF : 6; - unsigned int USE_UNFULL : 6; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_UNC_THRESH_SID { - struct { - unsigned int CHANGE_PREF : 6; - unsigned int STRONG_PREF : 6; - unsigned int USE_UNFULL : 6; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_WCB_CFG { - struct { - unsigned int TIMEOUT : 16; - unsigned int HST_MAX : 2; - unsigned int SID_MAX : 2; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_WCB_STS { - struct { - unsigned int PBUF_VLD : 16; - unsigned int WCB_HST_DATA_BUF_CNT : 7; - unsigned int WCB_SID_DATA_BUF_CNT : 7; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_PEER_SYS_BAR0 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_PEER_SYS_BAR1 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_PEER_SYS_BAR2 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_PEER_SYS_BAR3 { - struct { - unsigned int VALID : 1; - unsigned int SIDE_OK : 1; - unsigned int ADDR : 25; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_RTR_DEST_MAP0 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_RTR_DEST_MAP1 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_RTR_DEST_MAP2 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_RTR_DEST_MAP3 { - struct { - unsigned int NMR : 1; - unsigned int DEST_OFFSET : 19; - unsigned int DEST_SEL : 4; - unsigned int DEST_SEL_RPB : 1; - unsigned int SIDE_OK : 1; - unsigned int APRTR_SIZE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_RTR_SRC_APRTR0 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_RTR_SRC_APRTR1 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_RTR_SRC_APRTR2 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XPB_XDMA_RTR_SRC_APRTR3 { - struct { - unsigned int BASE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MEM_TYPE_CNTL__CI__VI { - struct { - unsigned int BF_MEM_PHY_G5_G3 : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MICROSECOND_TIME_BASE_DIV__SI__VI { - struct { - unsigned int MICROSECOND_TIME_BASE_DIV : 7; - unsigned int : 1; - unsigned int XTAL_REF_DIV : 7; - unsigned int : 1; - unsigned int XTAL_REF_SEL : 1; - unsigned int XTAL_REF_CLOCK_SOURCE_SEL : 1; - unsigned int : 2; - unsigned int MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MINOR_VERSION__SI__VI { - struct { - unsigned int MINOR_VERSION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MIN_GRANT { - struct { - unsigned int MIN_GNT : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MISC_CLK_CTRL__CI__VI { - struct { - unsigned int DEEP_SLEEP_CLK_SEL : 8; - unsigned int ZCLK_SEL : 8; - unsigned int DFT_SMS_PG_CLK_SEL : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MM_CFGREGS_CNTL { - struct { - unsigned int MM_CFG_FUNC_SEL : 3; - unsigned int MM_WR_TO_CFG_EN : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MM_DATA { - struct { - unsigned int MM_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MM_INDEX { - struct { - unsigned int MM_OFFSET : 31; - unsigned int MM_APER : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MM_INDEX_HI__CI__VI { - struct { - unsigned int MM_OFFSET_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_AD_FUNC_CNTL__SI__CI { - struct { - unsigned int YCLK_POST_DIV : 3; - unsigned int SPARE : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_AD_STATUS__SI__CI { - struct { - unsigned int VCTRLADC : 3; - unsigned int : 1; - unsigned int TEST_FBDIV_FRAC : 3; - unsigned int TEST_FBDIV_INT : 10; - unsigned int OINT_RESET : 1; - unsigned int FREQ_LOCK : 1; - unsigned int FREQ_UNLOCK_STICKY : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_BYPASSCLK_SEL { - struct { - unsigned int : 8; - unsigned int MPLL_CLKOUT_SEL : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_CNTL_MODE__SI__CI { - struct { - unsigned int INSTR_DELAY : 8; - unsigned int MPLL_SW_DIR_CONTROL : 1; - unsigned int : 2; - unsigned int MPLL_MCLK_SEL : 1; - unsigned int SPARE_1 : 1; - unsigned int QDR : 1; - unsigned int MPLL_CTLREQ : 1; - unsigned int : 1; - unsigned int MPLL_CHG_STATUS : 1; - unsigned int FORCE_TESTMODE : 1; - unsigned int : 2; - unsigned int FAST_LOCK_EN : 1; - unsigned int FAST_LOCK_CNTRL : 2; - unsigned int SPARE_2 : 1; - unsigned int SS_SSEN : 2; - unsigned int SS_DSMODE_EN : 1; - unsigned int VTOI_BIAS_CNTRL : 1; - unsigned int SPARE_3 : 3; - unsigned int GLOBAL_MPLL_RESET : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_CONTROL__SI__CI { - struct { - unsigned int GDDR_PWRON : 1; - unsigned int REFCLK_PWRON : 1; - unsigned int PLL_BUF_PWRON_TX : 1; - unsigned int : 9; - unsigned int AD_BG_PWRON : 1; - unsigned int AD_PLL_PWRON : 1; - unsigned int AD_PLL_RESET : 1; - unsigned int SPARE_AD_0 : 1; - unsigned int DQ_0_0_BG_PWRON : 1; - unsigned int DQ_0_0_PLL_PWRON : 1; - unsigned int DQ_0_0_PLL_RESET : 1; - unsigned int SPARE_DQ_0_0 : 1; - unsigned int DQ_0_1_BG_PWRON : 1; - unsigned int DQ_0_1_PLL_PWRON : 1; - unsigned int DQ_0_1_PLL_RESET : 1; - unsigned int SPARE_DQ_0_1 : 1; - unsigned int DQ_1_0_BG_PWRON : 1; - unsigned int DQ_1_0_PLL_PWRON : 1; - unsigned int DQ_1_0_PLL_RESET : 1; - unsigned int SPARE_DQ_1_0 : 1; - unsigned int DQ_1_1_BG_PWRON : 1; - unsigned int DQ_1_1_PLL_PWRON : 1; - unsigned int DQ_1_1_PLL_RESET : 1; - unsigned int SPARE_DQ_1_1 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_DQ_0_0_STATUS__SI__CI { - struct { - unsigned int VCTRLADC : 3; - unsigned int : 1; - unsigned int TEST_FBDIV_FRAC : 3; - unsigned int TEST_FBDIV_INT : 10; - unsigned int OINT_RESET : 1; - unsigned int FREQ_LOCK : 1; - unsigned int FREQ_UNLOCK_STICKY : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_DQ_0_1_STATUS__SI__CI { - struct { - unsigned int VCTRLADC : 3; - unsigned int : 1; - unsigned int TEST_FBDIV_FRAC : 3; - unsigned int TEST_FBDIV_INT : 10; - unsigned int OINT_RESET : 1; - unsigned int FREQ_LOCK : 1; - unsigned int FREQ_UNLOCK_STICKY : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_DQ_1_0_STATUS__SI__CI { - struct { - unsigned int VCTRLADC : 3; - unsigned int : 1; - unsigned int TEST_FBDIV_FRAC : 3; - unsigned int TEST_FBDIV_INT : 10; - unsigned int OINT_RESET : 1; - unsigned int FREQ_LOCK : 1; - unsigned int FREQ_UNLOCK_STICKY : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_DQ_1_1_STATUS__SI__CI { - struct { - unsigned int VCTRLADC : 3; - unsigned int : 1; - unsigned int TEST_FBDIV_FRAC : 3; - unsigned int TEST_FBDIV_INT : 10; - unsigned int OINT_RESET : 1; - unsigned int FREQ_LOCK : 1; - unsigned int FREQ_UNLOCK_STICKY : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_DQ_FUNC_CNTL__SI__CI { - struct { - unsigned int YCLK_POST_DIV : 3; - unsigned int SPARE_0 : 1; - unsigned int YCLK_SEL : 1; - unsigned int SPARE : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_FUNC_CNTL__SI__CI { - struct { - unsigned int : 5; - unsigned int SPARE_0 : 1; - unsigned int : 2; - unsigned int BG_100ADJ : 4; - unsigned int : 4; - unsigned int BG_135ADJ : 4; - unsigned int BWCTRL : 8; - unsigned int : 2; - unsigned int REG_BIAS : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_FUNC_CNTL_1__SI__CI { - struct { - unsigned int VCO_MODE : 2; - unsigned int SPARE_0 : 2; - unsigned int CLKFRAC : 12; - unsigned int CLKF : 12; - unsigned int SPARE_1 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_FUNC_CNTL_2__CI { - struct { - unsigned int VCTRLADC_EN : 1; - unsigned int TEST_VCTL_EN : 1; - unsigned int RESET_EN : 1; - unsigned int TEST_BYPCLK_EN : 1; - unsigned int TEST_BYPCLK_SRC : 1; - unsigned int TEST_FBDIV_FRAC_BYPASS : 1; - unsigned int TEST_BYPMCLK : 1; - unsigned int MPLL_UNLOCK_CLEAR : 1; - unsigned int TEST_VCTL_CNTRL : 1; - unsigned int TEST_FBDIV_SSC_BYPASS : 1; - unsigned int RESET_TIMER : 2; - unsigned int PFD_RESET_CNTRL : 2; - unsigned int RISEFBVCO_EN : 1; - unsigned int PWRGOOD_OVR : 1; - unsigned int ISO_DIS_P : 1; - unsigned int BACKUP_2 : 3; - unsigned int LF_CNTRL : 7; - unsigned int BACKUP : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_FUNC_CNTL_2__SI { - struct { - unsigned int VCTRLADC_EN : 1; - unsigned int TEST_VCTL_EN : 1; - unsigned int RESET_EN : 1; - unsigned int TEST_BYPCLK_EN : 1; - unsigned int TEST_BYPCLK_SRC : 1; - unsigned int TEST_FBDIV_FRAC_BYPASS : 1; - unsigned int TEST_BYPMCLK : 1; - unsigned int MPLL_UNLOCK_CLEAR : 1; - unsigned int TEST_VCTL_CNTRL : 1; - unsigned int TEST_FBDIV_SSC_BYPASS : 1; - unsigned int RESET_TIMER : 2; - unsigned int PFD_RESET_CNTRL : 2; - unsigned int : 3; - unsigned int BACKUP_2 : 3; - unsigned int LF_CNTRL : 7; - unsigned int BACKUP : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_SEQ_UCODE_1__SI__CI { - struct { - unsigned int INSTR0 : 4; - unsigned int INSTR1 : 4; - unsigned int INSTR2 : 4; - unsigned int INSTR3 : 4; - unsigned int INSTR4 : 4; - unsigned int INSTR5 : 4; - unsigned int INSTR6 : 4; - unsigned int INSTR7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_SEQ_UCODE_2__SI__CI { - struct { - unsigned int INSTR8 : 4; - unsigned int INSTR9 : 4; - unsigned int INSTR10 : 4; - unsigned int INSTR11 : 4; - unsigned int INSTR12 : 4; - unsigned int INSTR13 : 4; - unsigned int INSTR14 : 4; - unsigned int INSTR15 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_SS1__SI__CI { - struct { - unsigned int CLKV : 26; - unsigned int SPARE : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_SS2__SI__CI { - struct { - unsigned int CLKS : 12; - unsigned int SPARE : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MPLL_TIME__SI__CI { - struct { - unsigned int MPLL_LOCK_TIME : 16; - unsigned int MPLL_RESET_TIME : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MP_INT_EN__SI__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MP_INT_STAT__SI__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MP_STAT__SI__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MSI_CAP_LIST { - struct { - unsigned int CAP_ID : 8; - unsigned int NEXT_PTR : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MSI_MSG_ADDR_HI { - struct { - unsigned int MSI_MSG_ADDR_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MSI_MSG_ADDR_LO { - struct { - unsigned int : 2; - unsigned int MSI_MSG_ADDR_LO : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MSI_MSG_CNTL { - struct { - unsigned int MSI_EN : 1; - unsigned int MSI_MULTI_CAP : 3; - unsigned int MSI_MULTI_EN : 3; - unsigned int MSI_64BIT : 1; - unsigned int MSI_PERVECTOR_MASKING_CAP__VI : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MSI_MSG_DATA { - struct { - unsigned int MSI_DATA : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MSI_MSG_DATA_64 { - struct { - unsigned int MSI_DATA_64 : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_AFR_FLIP_FIFO_CNTL__SI__VI { - struct { - unsigned int MVP_AFR_FLIP_FIFO_NUM_ENTRIES : 4; - unsigned int MVP_AFR_FLIP_FIFO_RESET : 1; - unsigned int : 3; - unsigned int MVP_AFR_FLIP_FIFO_RESET_FLAG : 1; - unsigned int : 3; - unsigned int MVP_AFR_FLIP_FIFO_RESET_ACK : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_AFR_FLIP_MODE__SI__VI { - struct { - unsigned int MVP_AFR_FLIP_MODE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_BLACK_KEYER__SI__VI { - struct { - unsigned int MVP_BLACK_KEYER_R : 10; - unsigned int MVP_BLACK_KEYER_G : 10; - unsigned int MVP_BLACK_KEYER_B : 10; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_CONTROL1__SI__VI { - struct { - unsigned int MVP_EN : 1; - unsigned int : 3; - unsigned int MVP_MIXER_MODE : 3; - unsigned int : 1; - unsigned int MVP_MIXER_SLAVE_SEL : 1; - unsigned int MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK : 1; - unsigned int MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE : 1; - unsigned int : 1; - unsigned int MVP_RATE_CONTROL : 1; - unsigned int : 3; - unsigned int MVP_CHANNEL_CONTROL : 1; - unsigned int : 3; - unsigned int MVP_GPU_CHAIN_LOCATION : 2; - unsigned int : 2; - unsigned int MVP_DISABLE_MSB_EXPAND : 1; - unsigned int : 3; - unsigned int MVP_30BPP_EN : 1; - unsigned int : 1; - unsigned int MVP_TERMINATION_CNTL_A : 1; - unsigned int MVP_TERMINATION_CNTL_B : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_CONTROL2__SI__VI { - struct { - unsigned int MVP_MUX_DE_DVOCNTL0_SEL : 1; - unsigned int : 3; - unsigned int MVP_MUX_DE_DVOCNTL2_SEL : 1; - unsigned int : 3; - unsigned int MVP_MUXA_CLK_SEL : 1; - unsigned int : 3; - unsigned int MVP_MUXB_CLK_SEL : 1; - unsigned int : 3; - unsigned int MVP_DVOCNTL_MUX : 1; - unsigned int : 3; - unsigned int MVP_FLOW_CONTROL_OUT_EN : 1; - unsigned int : 3; - unsigned int MVP_SWAP_LOCK_OUT_EN : 1; - unsigned int : 3; - unsigned int MVP_SWAP_AB_IN_DC_DDR : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_CONTROL3__SI__VI { - struct { - unsigned int MVP_RESET_IN_BETWEEN_FRAMES : 1; - unsigned int : 3; - unsigned int MVP_DDR_SC_AB_SEL : 1; - unsigned int : 3; - unsigned int MVP_DDR_SC_B_START_MODE : 1; - unsigned int : 3; - unsigned int MVP_FLOW_CONTROL_OUT_FORCE_ONE : 1; - unsigned int : 3; - unsigned int MVP_FLOW_CONTROL_OUT_FORCE_ZERO : 1; - unsigned int : 3; - unsigned int MVP_FLOW_CONTROL_CASCADE_EN : 1; - unsigned int : 3; - unsigned int MVP_SWAP_48BIT_EN : 1; - unsigned int : 3; - unsigned int MVP_FLOW_CONTROL_IN_CAP : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_CRC_CNTL__SI__VI { - struct { - unsigned int MVP_CRC_BLUE_MASK : 8; - unsigned int MVP_CRC_GREEN_MASK : 8; - unsigned int MVP_CRC_RED_MASK : 8; - unsigned int : 4; - unsigned int MVP_CRC_EN : 1; - unsigned int MVP_CRC_CONT_EN : 1; - unsigned int MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_CRC_RESULT_BLUE_GREEN__SI__VI { - struct { - unsigned int MVP_CRC_BLUE_RESULT : 16; - unsigned int MVP_CRC_GREEN_RESULT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_CRC_RESULT_RED__SI__VI { - struct { - unsigned int MVP_CRC_RED_RESULT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_DEBUG_05__SI__VI { - struct { - unsigned int : 1; - unsigned int IDE0_MVP_GPU_CHAIN_LOCATION : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_DEBUG_09__SI__VI { - struct { - unsigned int : 1; - unsigned int IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION : 2; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_DEBUG_12__SI__VI { - struct { - unsigned int IDEC_MVP_DATA_A_H : 1; - unsigned int IDEC_MVP_DATA_A : 24; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_DEBUG_13__SI__VI { - struct { - unsigned int IDED_MVP_DATA_B_H : 1; - unsigned int IDED_MVP_DATA_B : 24; - unsigned int IDED_START_READ_B : 1; - unsigned int IDED_READ_FIFO_ENTRY_DE_B : 1; - unsigned int IDED_WRITE_ADD_B : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_DEBUG_14__SI__VI { - struct { - unsigned int IDEE_READ_ADD : 3; - unsigned int IDEE_WRITE_ADD_A : 3; - unsigned int IDEE_WRITE_ADD_B : 3; - unsigned int IDEE_START_READ : 1; - unsigned int IDEE_START_READ_B : 1; - unsigned int IDEE_START_INCR_WR_A : 1; - unsigned int IDEE_START_INCR_WR_B : 1; - unsigned int IDEE_WRITE2FIFO : 1; - unsigned int IDEE_READ_FIFO_ENTRY_DE : 1; - unsigned int IDEE_READ_FIFO_ENTRY_DE_B : 1; - unsigned int IDEE_READ_FIFO_DE : 1; - unsigned int IDEE_READ_FIFO_DE_B : 1; - unsigned int IDEE_READ_FIFO_ENABLE : 1; - unsigned int IDEE_CRTC1_CNTL_CAPTURE_START_A : 1; - unsigned int IDEE_CRC_PHASE : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_DEBUG_15__SI__VI { - struct { - unsigned int IDEF_MVP_ASYNC_FIFO_WEN : 1; - unsigned int : 3; - unsigned int IDEF_MVP_ASYNC_FIFO_WDATA : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_DEBUG_16__SI__VI { - struct { - unsigned int IDCC_MVP_ASYNC_FIFO_READ : 1; - unsigned int IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL : 1; - unsigned int IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL : 1; - unsigned int IDCC_FLOW_CONTROL_OUT : 1; - unsigned int IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES : 8; - unsigned int IDCC_MVP_ASYNC_FIFO_OVERFLOW : 1; - unsigned int IDCC_MVP_ASYNC_FIFO_UNDERFLOW : 1; - unsigned int : 2; - unsigned int IDCC_MVP_ASYNC_READ_ADDR : 8; - unsigned int IDCC_MVP_ASYNC_WRITE_ADDR : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_DEBUG_17__SI__VI { - struct { - unsigned int IDCD_MVP_ASYNC_FIFO_READ : 1; - unsigned int IDCD_MVP_ASYNC_FIFO_PHASE : 1; - unsigned int IDCD_MVP_ASYNC_FIFO_READ_DATA : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_FIFO_CONTROL__SI__VI { - struct { - unsigned int MVP_STOP_SLAVE_WM : 8; - unsigned int MVP_PAUSE_SLAVE_WM : 8; - unsigned int MVP_PAUSE_SLAVE_CNT : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_FIFO_STATUS__SI__VI { - struct { - unsigned int MVP_FIFO_LEVEL : 8; - unsigned int MVP_FIFO_OVERFLOW : 1; - unsigned int : 3; - unsigned int MVP_FIFO_OVERFLOW_OCCURRED : 1; - unsigned int : 3; - unsigned int MVP_FIFO_OVERFLOW_ACK : 1; - unsigned int : 3; - unsigned int MVP_FIFO_UNDERFLOW : 1; - unsigned int : 3; - unsigned int MVP_FIFO_UNDERFLOW_OCCURRED : 1; - unsigned int : 3; - unsigned int MVP_FIFO_UNDERFLOW_ACK : 1; - unsigned int : 1; - unsigned int MVP_FIFO_ERROR_MASK : 1; - unsigned int MVP_FIFO_ERROR_INT_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_FLIP_LINE_NUM_INSERT__SI__VI { - struct { - unsigned int MVP_FLIP_LINE_NUM_INSERT_MODE : 2; - unsigned int : 6; - unsigned int MVP_FLIP_LINE_NUM_INSERT : 15; - unsigned int : 1; - unsigned int MVP_FLIP_LINE_NUM_OFFSET : 6; - unsigned int MVP_FLIP_AUTO_ENABLE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_INBAND_CNTL_CAP__SI__VI { - struct { - unsigned int MVP_IGNOR_INBAND_CNTL : 1; - unsigned int : 3; - unsigned int MVP_PASSING_INBAND_CNTL_EN : 1; - unsigned int : 3; - unsigned int MVP_INBAND_CNTL_CHAR_CAP : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_RECEIVE_CNT_CNTL1__SI__VI { - struct { - unsigned int MVP_SLAVE_PIXEL_ERROR_CNT : 13; - unsigned int : 3; - unsigned int MVP_SLAVE_LINE_ERROR_CNT : 13; - unsigned int : 2; - unsigned int MVP_SLAVE_DATA_CHK_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_RECEIVE_CNT_CNTL2__SI__VI { - struct { - unsigned int MVP_SLAVE_FRAME_ERROR_CNT : 13; - unsigned int : 18; - unsigned int MVP_SLAVE_FRAME_ERROR_CNT_RESET : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_SLAVE_STATUS__SI__VI { - struct { - unsigned int MVP_SLAVE_PIXELS_PER_LINE_RCVED : 13; - unsigned int : 3; - unsigned int MVP_SLAVE_LINES_PER_FRAME_RCVED : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int MVP_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int MVP_TEST_DEBUG_INDEX : 8; - unsigned int MVP_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union NEW_REFCLKB_TIMER_1__CI { - struct { - unsigned int PHY_PLL_PDWN_TIMER : 10; - unsigned int PLL0_PDNB_EN : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union NEW_REFCLKB_TIMER__CI { - struct { - unsigned int REG_STOP_REFCLK_EN : 1; - unsigned int STOP_REFCLK_TIMER : 20; - unsigned int REFCLK_ON : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_PAYLOAD_CAPABILITY__SI__VI { - struct { - unsigned int OUTPUT_PAYLOAD_CAPABILITY : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVLSCL_EDGE_PIXEL_CNTL__SI__VI { - struct { - unsigned int OVLSCL_BLACK_COLOR_BCB : 10; - unsigned int OVLSCL_BLACK_COLOR_GY : 10; - unsigned int OVLSCL_BLACK_COLOR_RCR : 10; - unsigned int : 1; - unsigned int OVLSCL_EDGE_PIXEL_SEL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_ALPHA__SI { - struct { - unsigned int : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_CONTROL1__SI { - struct { - unsigned int OVL_DEPTH : 2; - unsigned int : 2; - unsigned int OVL_Z : 2; - unsigned int : 2; - unsigned int OVL_FORMAT : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int OVL_ADDRESS_TRANSLATION_ENABLE : 1; - unsigned int OVL_PRIVILEGED_ACCESS_ENABLE : 1; - unsigned int : 2; - unsigned int OVL_ARRAY_MODE : 4; - unsigned int OVL_COLOR_EXPANSION_MODE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_CONTROL1__VI { - struct { - unsigned int OVL_DEPTH : 2; - unsigned int OVL_NUM_BANKS : 2; - unsigned int OVL_Z : 2; - unsigned int OVL_BANK_WIDTH : 2; - unsigned int OVL_FORMAT : 3; - unsigned int OVL_BANK_HEIGHT : 2; - unsigned int OVL_TILE_SPLIT : 3; - unsigned int OVL_ADDRESS_TRANSLATION_ENABLE : 1; - unsigned int OVL_PRIVILEGED_ACCESS_ENABLE : 1; - unsigned int OVL_MACRO_TILE_ASPECT : 2; - unsigned int OVL_ARRAY_MODE : 4; - unsigned int OVL_COLOR_EXPANSION_MODE : 1; - unsigned int OVL_PIPE_CONFIG : 5; - unsigned int OVL_MICRO_TILE_MODE : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_CONTROL2__SI__VI { - struct { - unsigned int OVL_HALF_RESOLUTION_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_DFQ_CONTROL__SI__VI { - struct { - unsigned int OVL_DFQ_RESET : 1; - unsigned int : 3; - unsigned int OVL_DFQ_SIZE : 3; - unsigned int : 1; - unsigned int OVL_DFQ_MIN_FREE_ENTRIES : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_DFQ_STATUS__SI__VI { - struct { - unsigned int OVL_DFQ_NUM_ENTRIES : 4; - unsigned int OVL_SECONDARY_DFQ_NUM_ENTRIES__VI : 4; - unsigned int OVL_DFQ_RESET_FLAG : 1; - unsigned int OVL_DFQ_RESET_ACK : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_ENABLE__SI__VI { - struct { - unsigned int OVL_ENABLE : 1; - unsigned int : 7; - unsigned int OVLSCL_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_END__SI__VI { - struct { - unsigned int OVL_Y_END : 15; - unsigned int : 1; - unsigned int OVL_X_END : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_PITCH__SI__VI { - struct { - unsigned int OVL_PITCH : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_START__SI__VI { - struct { - unsigned int OVL_Y_START : 14; - unsigned int : 2; - unsigned int OVL_X_START : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_SURFACE_ADDRESS { - struct { - unsigned int OVL_DFQ_ENABLE : 1; - unsigned int : 7; - unsigned int OVL_SURFACE_ADDRESS : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_SURFACE_ADDRESS_HIGH { - struct { - unsigned int OVL_SURFACE_ADDRESS_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_SURFACE_ADDRESS_HIGH_INUSE__SI__VI { - struct { - unsigned int OVL_SURFACE_ADDRESS_HIGH_INUSE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_SURFACE_ADDRESS_INUSE__SI__VI { - struct { - unsigned int : 8; - unsigned int OVL_SURFACE_ADDRESS_INUSE : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_SURFACE_OFFSET_X__SI__VI { - struct { - unsigned int OVL_SURFACE_OFFSET_X : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_SURFACE_OFFSET_Y__SI__VI { - struct { - unsigned int OVL_SURFACE_OFFSET_Y : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_SWAP_CNTL__SI__VI { - struct { - unsigned int OVL_ENDIAN_SWAP : 2; - unsigned int : 2; - unsigned int OVL_RED_CROSSBAR : 2; - unsigned int OVL_GREEN_CROSSBAR : 2; - unsigned int OVL_BLUE_CROSSBAR : 2; - unsigned int OVL_ALPHA_CROSSBAR : 2; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_UPDATE__SI__VI { - struct { - unsigned int OVL_UPDATE_PENDING : 1; - unsigned int OVL_UPDATE_TAKEN : 1; - unsigned int : 14; - unsigned int OVL_UPDATE_LOCK : 1; - unsigned int : 7; - unsigned int OVL_DISABLE_MULTIPLE_UPDATE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PAGE_MIRROR_CNTL { - struct { - unsigned int PAGE_MIRROR_BASE_ADDR : 24; - unsigned int PAGE_MIRROR_INVALIDATE : 1; - unsigned int PAGE_MIRROR_ENABLE : 1; - unsigned int PAGE_MIRROR_USAGE : 2; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_CLIP_CNTL { - struct { - unsigned int UCP_ENA_0 : 1; - unsigned int UCP_ENA_1 : 1; - unsigned int UCP_ENA_2 : 1; - unsigned int UCP_ENA_3 : 1; - unsigned int UCP_ENA_4 : 1; - unsigned int UCP_ENA_5 : 1; - unsigned int : 7; - unsigned int PS_UCP_Y_SCALE_NEG : 1; - unsigned int PS_UCP_MODE : 2; - unsigned int CLIP_DISABLE : 1; - unsigned int UCP_CULL_ONLY_ENA : 1; - unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; - unsigned int DX_CLIP_SPACE_DEF : 1; - unsigned int DIS_CLIP_ERR_DETECT : 1; - unsigned int VTX_KILL_OR : 1; - unsigned int DX_RASTERIZATION_KILL : 1; - unsigned int : 1; - unsigned int DX_LINEAR_ATTR_CLIP_ENA : 1; - unsigned int VTE_VPORT_PROVOKE_DISABLE : 1; - unsigned int ZCLIP_NEAR_DISABLE : 1; - unsigned int ZCLIP_FAR_DISABLE : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_CNTL_STATUS { - struct { - unsigned int : 31; - unsigned int CL_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_ENHANCE { - struct { - unsigned int CLIP_VTX_REORDER_ENA : 1; - unsigned int NUM_CLIP_SEQ : 2; - unsigned int CLIPPED_PRIM_SEQ_STALL : 1; - unsigned int VE_NAN_PROC_DISABLE : 1; - unsigned int XTRA_DEBUG_REG_SEL : 1; - unsigned int : 22; - unsigned int ECO_SPARE3 : 1; - unsigned int ECO_SPARE2 : 1; - unsigned int ECO_SPARE1 : 1; - unsigned int ECO_SPARE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_GB_HORZ_CLIP_ADJ { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_GB_HORZ_DISC_ADJ { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_GB_VERT_CLIP_ADJ { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_GB_VERT_DISC_ADJ { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_NANINF_CNTL { - struct { - unsigned int VTE_XY_INF_DISCARD : 1; - unsigned int VTE_Z_INF_DISCARD : 1; - unsigned int VTE_W_INF_DISCARD : 1; - unsigned int VTE_0XNANINF_IS_0 : 1; - unsigned int VTE_XY_NAN_RETAIN : 1; - unsigned int VTE_Z_NAN_RETAIN : 1; - unsigned int VTE_W_NAN_RETAIN : 1; - unsigned int VTE_W_RECIP_NAN_IS_0 : 1; - unsigned int VS_XY_NAN_TO_INF : 1; - unsigned int VS_XY_INF_RETAIN : 1; - unsigned int VS_Z_NAN_TO_INF : 1; - unsigned int VS_Z_INF_RETAIN : 1; - unsigned int VS_W_NAN_TO_INF : 1; - unsigned int VS_W_INF_RETAIN : 1; - unsigned int VS_CLIP_DIST_INF_DISCARD : 1; - unsigned int : 5; - unsigned int VTE_NO_OUTPUT_NEG_0 : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_POINT_CULL_RAD { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_POINT_SIZE { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_POINT_X_RAD { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_POINT_Y_RAD { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_RESET_DEBUG__CI__VI { - struct { - unsigned int CL_TRIV_DISC_DISABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_0_W { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_0_X { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_0_Y { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_0_Z { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_1_W { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_1_X { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_1_Y { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_1_Z { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_2_W { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_2_X { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_2_Y { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_2_Z { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_3_W { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_3_X { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_3_Y { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_3_Z { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_4_W { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_4_X { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_4_Y { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_4_Z { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_5_W { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_5_X { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_5_Y { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_UCP_5_Z { - struct { - unsigned int DATA_REGISTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_1 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_10 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_11 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_12 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_13 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_14 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_15 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_2 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_3 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_4 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_5 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_6 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_7 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_8 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XOFFSET_9 { - struct { - unsigned int VPORT_XOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_1 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_10 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_11 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_12 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_13 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_14 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_15 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_2 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_3 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_4 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_5 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_6 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_7 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_8 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_XSCALE_9 { - struct { - unsigned int VPORT_XSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_1 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_10 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_11 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_12 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_13 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_14 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_15 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_2 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_3 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_4 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_5 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_6 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_7 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_8 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YOFFSET_9 { - struct { - unsigned int VPORT_YOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_1 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_10 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_11 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_12 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_13 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_14 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_15 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_2 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_3 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_4 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_5 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_6 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_7 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_8 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_YSCALE_9 { - struct { - unsigned int VPORT_YSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_1 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_10 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_11 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_12 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_13 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_14 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_15 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_2 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_3 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_4 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_5 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_6 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_7 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_8 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZOFFSET_9 { - struct { - unsigned int VPORT_ZOFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_1 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_10 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_11 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_12 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_13 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_14 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_15 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_2 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_3 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_4 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_5 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_6 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_7 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_8 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VPORT_ZSCALE_9 { - struct { - unsigned int VPORT_ZSCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VS_OUT_CNTL { - struct { - unsigned int CLIP_DIST_ENA_0 : 1; - unsigned int CLIP_DIST_ENA_1 : 1; - unsigned int CLIP_DIST_ENA_2 : 1; - unsigned int CLIP_DIST_ENA_3 : 1; - unsigned int CLIP_DIST_ENA_4 : 1; - unsigned int CLIP_DIST_ENA_5 : 1; - unsigned int CLIP_DIST_ENA_6 : 1; - unsigned int CLIP_DIST_ENA_7 : 1; - unsigned int CULL_DIST_ENA_0 : 1; - unsigned int CULL_DIST_ENA_1 : 1; - unsigned int CULL_DIST_ENA_2 : 1; - unsigned int CULL_DIST_ENA_3 : 1; - unsigned int CULL_DIST_ENA_4 : 1; - unsigned int CULL_DIST_ENA_5 : 1; - unsigned int CULL_DIST_ENA_6 : 1; - unsigned int CULL_DIST_ENA_7 : 1; - unsigned int USE_VTX_POINT_SIZE : 1; - unsigned int USE_VTX_EDGE_FLAG : 1; - unsigned int USE_VTX_RENDER_TARGET_INDX : 1; - unsigned int USE_VTX_VIEWPORT_INDX : 1; - unsigned int USE_VTX_KILL_FLAG : 1; - unsigned int VS_OUT_MISC_VEC_ENA : 1; - unsigned int VS_OUT_CCDIST0_VEC_ENA : 1; - unsigned int VS_OUT_CCDIST1_VEC_ENA : 1; - unsigned int VS_OUT_MISC_SIDE_BUS_ENA : 1; - unsigned int USE_VTX_GS_CUT_FLAG : 1; - unsigned int USE_VTX_LINE_WIDTH__VI : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_CL_VTE_CNTL { - struct { - unsigned int VPORT_X_SCALE_ENA : 1; - unsigned int VPORT_X_OFFSET_ENA : 1; - unsigned int VPORT_Y_SCALE_ENA : 1; - unsigned int VPORT_Y_OFFSET_ENA : 1; - unsigned int VPORT_Z_SCALE_ENA : 1; - unsigned int VPORT_Z_OFFSET_ENA : 1; - unsigned int : 2; - unsigned int VTX_XY_FMT : 1; - unsigned int VTX_Z_FMT : 1; - unsigned int VTX_W0_FMT : 1; - unsigned int PERFCOUNTER_REF : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_CONFIG { - struct { - unsigned int MSAA_NUM_SAMPLES : 3; - unsigned int : 1; - unsigned int AA_MASK_CENTROID_DTMN : 1; - unsigned int : 8; - unsigned int MAX_SAMPLE_DIST : 4; - unsigned int : 3; - unsigned int MSAA_EXPOSED_SAMPLES : 3; - unsigned int : 1; - unsigned int DETAIL_TO_EXPOSED_MODE : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_MASK_X0Y0_X1Y0 { - struct { - unsigned int AA_MASK_X0Y0 : 16; - unsigned int AA_MASK_X1Y0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_MASK_X0Y1_X1Y1 { - struct { - unsigned int AA_MASK_X0Y1 : 16; - unsigned int AA_MASK_X1Y1 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 { - struct { - unsigned int S0_X : 4; - unsigned int S0_Y : 4; - unsigned int S1_X : 4; - unsigned int S1_Y : 4; - unsigned int S2_X : 4; - unsigned int S2_Y : 4; - unsigned int S3_X : 4; - unsigned int S3_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 { - struct { - unsigned int S4_X : 4; - unsigned int S4_Y : 4; - unsigned int S5_X : 4; - unsigned int S5_Y : 4; - unsigned int S6_X : 4; - unsigned int S6_Y : 4; - unsigned int S7_X : 4; - unsigned int S7_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 { - struct { - unsigned int S8_X : 4; - unsigned int S8_Y : 4; - unsigned int S9_X : 4; - unsigned int S9_Y : 4; - unsigned int S10_X : 4; - unsigned int S10_Y : 4; - unsigned int S11_X : 4; - unsigned int S11_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 { - struct { - unsigned int S12_X : 4; - unsigned int S12_Y : 4; - unsigned int S13_X : 4; - unsigned int S13_Y : 4; - unsigned int S14_X : 4; - unsigned int S14_Y : 4; - unsigned int S15_X : 4; - unsigned int S15_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 { - struct { - unsigned int S0_X : 4; - unsigned int S0_Y : 4; - unsigned int S1_X : 4; - unsigned int S1_Y : 4; - unsigned int S2_X : 4; - unsigned int S2_Y : 4; - unsigned int S3_X : 4; - unsigned int S3_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 { - struct { - unsigned int S4_X : 4; - unsigned int S4_Y : 4; - unsigned int S5_X : 4; - unsigned int S5_Y : 4; - unsigned int S6_X : 4; - unsigned int S6_Y : 4; - unsigned int S7_X : 4; - unsigned int S7_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 { - struct { - unsigned int S8_X : 4; - unsigned int S8_Y : 4; - unsigned int S9_X : 4; - unsigned int S9_Y : 4; - unsigned int S10_X : 4; - unsigned int S10_Y : 4; - unsigned int S11_X : 4; - unsigned int S11_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 { - struct { - unsigned int S12_X : 4; - unsigned int S12_Y : 4; - unsigned int S13_X : 4; - unsigned int S13_Y : 4; - unsigned int S14_X : 4; - unsigned int S14_Y : 4; - unsigned int S15_X : 4; - unsigned int S15_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 { - struct { - unsigned int S0_X : 4; - unsigned int S0_Y : 4; - unsigned int S1_X : 4; - unsigned int S1_Y : 4; - unsigned int S2_X : 4; - unsigned int S2_Y : 4; - unsigned int S3_X : 4; - unsigned int S3_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 { - struct { - unsigned int S4_X : 4; - unsigned int S4_Y : 4; - unsigned int S5_X : 4; - unsigned int S5_Y : 4; - unsigned int S6_X : 4; - unsigned int S6_Y : 4; - unsigned int S7_X : 4; - unsigned int S7_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 { - struct { - unsigned int S8_X : 4; - unsigned int S8_Y : 4; - unsigned int S9_X : 4; - unsigned int S9_Y : 4; - unsigned int S10_X : 4; - unsigned int S10_Y : 4; - unsigned int S11_X : 4; - unsigned int S11_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 { - struct { - unsigned int S12_X : 4; - unsigned int S12_Y : 4; - unsigned int S13_X : 4; - unsigned int S13_Y : 4; - unsigned int S14_X : 4; - unsigned int S14_Y : 4; - unsigned int S15_X : 4; - unsigned int S15_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 { - struct { - unsigned int S0_X : 4; - unsigned int S0_Y : 4; - unsigned int S1_X : 4; - unsigned int S1_Y : 4; - unsigned int S2_X : 4; - unsigned int S2_Y : 4; - unsigned int S3_X : 4; - unsigned int S3_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 { - struct { - unsigned int S4_X : 4; - unsigned int S4_Y : 4; - unsigned int S5_X : 4; - unsigned int S5_Y : 4; - unsigned int S6_X : 4; - unsigned int S6_Y : 4; - unsigned int S7_X : 4; - unsigned int S7_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 { - struct { - unsigned int S8_X : 4; - unsigned int S8_Y : 4; - unsigned int S9_X : 4; - unsigned int S9_Y : 4; - unsigned int S10_X : 4; - unsigned int S10_Y : 4; - unsigned int S11_X : 4; - unsigned int S11_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 { - struct { - unsigned int S12_X : 4; - unsigned int S12_Y : 4; - unsigned int S13_X : 4; - unsigned int S13_Y : 4; - unsigned int S14_X : 4; - unsigned int S14_Y : 4; - unsigned int S15_X : 4; - unsigned int S15_Y : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_CENTROID_PRIORITY_0 { - struct { - unsigned int DISTANCE_0 : 4; - unsigned int DISTANCE_1 : 4; - unsigned int DISTANCE_2 : 4; - unsigned int DISTANCE_3 : 4; - unsigned int DISTANCE_4 : 4; - unsigned int DISTANCE_5 : 4; - unsigned int DISTANCE_6 : 4; - unsigned int DISTANCE_7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_CENTROID_PRIORITY_1 { - struct { - unsigned int DISTANCE_8 : 4; - unsigned int DISTANCE_9 : 4; - unsigned int DISTANCE_10 : 4; - unsigned int DISTANCE_11 : 4; - unsigned int DISTANCE_12 : 4; - unsigned int DISTANCE_13 : 4; - unsigned int DISTANCE_14 : 4; - unsigned int DISTANCE_15 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_CLIPRECT_0_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_CLIPRECT_0_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_CLIPRECT_1_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_CLIPRECT_1_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_CLIPRECT_2_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_CLIPRECT_2_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_CLIPRECT_3_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_CLIPRECT_3_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_CLIPRECT_RULE { - struct { - unsigned int CLIP_RULE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_DEBUG_CNTL { - struct { - unsigned int SC_DEBUG_INDX : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_DEBUG_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_DEBUG_REG0 { - struct { - unsigned int REG0_FIELD0 : 2; - unsigned int REG0_FIELD1 : 2; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_DEBUG_REG1 { - struct { - unsigned int REG1_FIELD0 : 2; - unsigned int REG1_FIELD1 : 2; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_EDGERULE { - struct { - unsigned int ER_TRI : 4; - unsigned int ER_POINT : 4; - unsigned int ER_RECT : 4; - unsigned int ER_LINE_LR : 6; - unsigned int ER_LINE_RL : 6; - unsigned int ER_LINE_TB : 4; - unsigned int ER_LINE_BT : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_ENHANCE__CI__VI { - struct { - unsigned int ENABLE_PA_SC_OUT_OF_ORDER : 1; - unsigned int DISABLE_SC_DB_TILE_FIX : 1; - unsigned int DISABLE_AA_MASK_FULL_FIX : 1; - unsigned int ENABLE_1XMSAA_SAMPLE_LOCATIONS : 1; - unsigned int ENABLE_1XMSAA_SAMPLE_LOC_CENTROID : 1; - unsigned int DISABLE_SCISSOR_FIX : 1; - unsigned int DISABLE_PW_BUBBLE_COLLAPSE : 2; - unsigned int SEND_UNLIT_STILES_TO_PACKER : 1; - unsigned int DISABLE_DUALGRAD_PERF_OPTIMIZATION : 1; - unsigned int DISABLE_SC_PROCESS_RESET_PRIM : 1; - unsigned int DISABLE_SC_PROCESS_RESET_SUPERTILE : 1; - unsigned int DISABLE_SC_PROCESS_RESET_TILE : 1; - unsigned int DISABLE_PA_SC_GUIDANCE : 1; - unsigned int DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS : 1; - unsigned int ENABLE_MULTICYCLE_BUBBLE_FREEZE : 1; - unsigned int DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE : 1; - unsigned int ENABLE_OUT_OF_ORDER_POLY_MODE : 1; - unsigned int DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST : 1; - unsigned int DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING : 1; - unsigned int ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY : 1; - unsigned int DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING : 1; - unsigned int DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING : 1; - unsigned int DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS : 1; - unsigned int ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID : 1; - unsigned int DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO : 1; - unsigned int OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT : 1; - unsigned int OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING : 1; - unsigned int DISABLE_EOP_LINE_STIPPLE_RESET : 1; - unsigned int DISABLE_VPZ_EOP_LINE_STIPPLE_RESET : 1; - unsigned int ECO_SPARE1 : 1; - unsigned int ECO_SPARE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_ENHANCE__SI { - struct { - unsigned int ENABLE_PA_SC_OUT_OF_ORDER : 1; - unsigned int DISABLE_SC_DB_TILE_FIX : 1; - unsigned int DISABLE_AA_MASK_FULL_FIX : 1; - unsigned int ENABLE_1XMSAA_SAMPLE_LOCATIONS : 1; - unsigned int ENABLE_1XMSAA_SAMPLE_LOC_CENTROID : 1; - unsigned int DISABLE_SCISSOR_FIX : 1; - unsigned int DISABLE_PW_BUBBLE_COLLAPSE : 2; - unsigned int SEND_UNLIT_STILES_TO_PACKER : 1; - unsigned int DISABLE_DUALGRAD_PERF_OPTIMIZATION : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 12; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int ECO_SPARE1 : 1; - unsigned int ECO_SPARE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_FIFO_DEPTH_CNTL { - struct { - unsigned int DEPTH : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_FIFO_SIZE { - struct { - unsigned int SC_FRONTEND_PRIM_FIFO_SIZE : 6; - unsigned int SC_BACKEND_PRIM_FIFO_SIZE : 9; - unsigned int SC_HIZ_TILE_FIFO_SIZE : 6; - unsigned int : 2; - unsigned int SC_EARLYZ_TILE_FIFO_SIZE : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_FORCE_EOV_MAX_CNTS { - struct { - unsigned int FORCE_EOV_MAX_CLK_CNT : 16; - unsigned int FORCE_EOV_MAX_REZ_CNT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_GENERIC_SCISSOR_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_GENERIC_SCISSOR_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_HP3D_TRAP_SCREEN_COUNT__CI__VI { - struct { - unsigned int COUNT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_HP3D_TRAP_SCREEN_HV_EN__CI__VI { - struct { - unsigned int ENABLE_HV_PRE_SHADER : 1; - unsigned int FORCE_PRE_SHADER_ALL_PIXELS : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__CI__VI { - struct { - unsigned int DISABLE_NON_PRIV_WRITES : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_HP3D_TRAP_SCREEN_H__CI__VI { - struct { - unsigned int X_COORD : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__CI__VI { - struct { - unsigned int COUNT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_HP3D_TRAP_SCREEN_V__CI__VI { - struct { - unsigned int Y_COORD : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_IF_FIFO_SIZE { - struct { - unsigned int SC_DB_TILE_IF_FIFO_SIZE : 6; - unsigned int SC_DB_QUAD_IF_FIFO_SIZE : 6; - unsigned int SC_SPI_IF_FIFO_SIZE : 6; - unsigned int SC_BCI_IF_FIFO_SIZE : 6; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_LINE_CNTL { - struct { - unsigned int : 9; - unsigned int EXPAND_LINE_WIDTH : 1; - unsigned int LAST_PIXEL : 1; - unsigned int PERPENDICULAR_ENDCAP_ENA : 1; - unsigned int DX10_DIAMOND_TEST_ENA : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_LINE_STIPPLE { - struct { - unsigned int LINE_PATTERN : 16; - unsigned int REPEAT_COUNT : 8; - unsigned int : 4; - unsigned int PATTERN_BIT_ORDER : 1; - unsigned int AUTO_RESET_CNTL : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_LINE_STIPPLE_STATE { - struct { - unsigned int CURRENT_PTR : 4; - unsigned int : 4; - unsigned int CURRENT_COUNT : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_MODE_CNTL_0 { - struct { - unsigned int MSAA_ENABLE : 1; - unsigned int VPORT_SCISSOR_ENABLE : 1; - unsigned int LINE_STIPPLE_ENABLE : 1; - unsigned int SEND_UNLIT_STILES_TO_PKR : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_MODE_CNTL_1 { - struct { - unsigned int WALK_SIZE : 1; - unsigned int WALK_ALIGNMENT : 1; - unsigned int WALK_ALIGN8_PRIM_FITS_ST : 1; - unsigned int WALK_FENCE_ENABLE : 1; - unsigned int WALK_FENCE_SIZE : 3; - unsigned int SUPERTILE_WALK_ORDER_ENABLE : 1; - unsigned int TILE_WALK_ORDER_ENABLE : 1; - unsigned int TILE_COVER_DISABLE : 1; - unsigned int TILE_COVER_NO_SCISSOR : 1; - unsigned int ZMM_LINE_EXTENT : 1; - unsigned int ZMM_LINE_OFFSET : 1; - unsigned int ZMM_RECT_EXTENT : 1; - unsigned int KILL_PIX_POST_HI_Z : 1; - unsigned int KILL_PIX_POST_DETAIL_MASK : 1; - unsigned int PS_ITER_SAMPLE : 1; - unsigned int MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE : 1; - unsigned int MULTI_GPU_SUPERTILE_ENABLE : 1; - unsigned int GPU_ID_OVERRIDE_ENABLE : 1; - unsigned int GPU_ID_OVERRIDE : 4; - unsigned int MULTI_GPU_PRIM_DISCARD_ENABLE : 1; - unsigned int FORCE_EOV_CNTDWN_ENABLE : 1; - unsigned int FORCE_EOV_REZ_ENABLE : 1; - unsigned int OUT_OF_ORDER_PRIMITIVE_ENABLE : 1; - unsigned int OUT_OF_ORDER_WATER_MARK : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_P3D_TRAP_SCREEN_COUNT__CI__VI { - struct { - unsigned int COUNT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_P3D_TRAP_SCREEN_HV_EN__CI__VI { - struct { - unsigned int ENABLE_HV_PRE_SHADER : 1; - unsigned int FORCE_PRE_SHADER_ALL_PIXELS : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_P3D_TRAP_SCREEN_HV_LOCK__CI__VI { - struct { - unsigned int DISABLE_NON_PRIV_WRITES : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_P3D_TRAP_SCREEN_H__CI__VI { - struct { - unsigned int X_COORD : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__CI__VI { - struct { - unsigned int COUNT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_P3D_TRAP_SCREEN_V__CI__VI { - struct { - unsigned int Y_COORD : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER0_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER1_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER2_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER3_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER4_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER4_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER4_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER5_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER5_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER5_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER6_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER6_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER6_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER7_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER7_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_PERFCOUNTER7_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_RASTER_CONFIG { - struct { - unsigned int RB_MAP_PKR0 : 2; - unsigned int RB_MAP_PKR1 : 2; - unsigned int RB_XSEL2 : 2; - unsigned int RB_XSEL : 1; - unsigned int RB_YSEL : 1; - unsigned int PKR_MAP : 2; - unsigned int PKR_XSEL : 2; - unsigned int PKR_YSEL : 2; - unsigned int PKR_XSEL2__CI__VI : 2; - unsigned int SC_MAP : 2; - unsigned int SC_XSEL : 2; - unsigned int SC_YSEL : 2; - unsigned int : 2; - unsigned int SE_MAP : 2; - unsigned int SE_XSEL : 2; - unsigned int SE_YSEL : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_RASTER_CONFIG_1__CI__VI { - struct { - unsigned int SE_PAIR_MAP : 2; - unsigned int SE_PAIR_XSEL : 2; - unsigned int SE_PAIR_YSEL : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_SCREEN_SCISSOR_BR { - struct { - unsigned int BR_X : 16; - unsigned int BR_Y : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_SCREEN_SCISSOR_TL { - struct { - unsigned int TL_X : 16; - unsigned int TL_Y : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_TRAP_SCREEN_COUNT__CI__VI { - struct { - unsigned int COUNT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_TRAP_SCREEN_HV_EN__CI__VI { - struct { - unsigned int ENABLE_HV_PRE_SHADER : 1; - unsigned int FORCE_PRE_SHADER_ALL_PIXELS : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_TRAP_SCREEN_HV_LOCK__CI__VI { - struct { - unsigned int DISABLE_NON_PRIV_WRITES : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_TRAP_SCREEN_H__CI__VI { - struct { - unsigned int X_COORD : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_TRAP_SCREEN_OCCURRENCE__CI__VI { - struct { - unsigned int COUNT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_TRAP_SCREEN_V__CI__VI { - struct { - unsigned int Y_COORD : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_0_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_0_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_10_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_10_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_11_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_11_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_12_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_12_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_13_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_13_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_14_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_14_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_15_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_15_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_1_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_1_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_2_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_2_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_3_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_3_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_4_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_4_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_5_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_5_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_6_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_6_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_7_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_7_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_8_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_8_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_9_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_SCISSOR_9_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_0 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_1 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_10 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_11 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_12 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_13 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_14 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_15 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_2 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_3 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_4 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_5 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_6 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_7 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_8 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMAX_9 { - struct { - unsigned int VPORT_ZMAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_0 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_1 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_10 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_11 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_12 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_13 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_14 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_15 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_2 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_3 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_4 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_5 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_6 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_7 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_8 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_VPORT_ZMIN_9 { - struct { - unsigned int VPORT_ZMIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_WINDOW_OFFSET { - struct { - unsigned int WINDOW_X_OFFSET : 16; - unsigned int WINDOW_Y_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_WINDOW_SCISSOR_BR { - struct { - unsigned int BR_X : 15; - unsigned int : 1; - unsigned int BR_Y : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SC_WINDOW_SCISSOR_TL { - struct { - unsigned int TL_X : 15; - unsigned int : 1; - unsigned int TL_Y : 15; - unsigned int WINDOW_OFFSET_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_CNTL_STATUS { - struct { - unsigned int : 31; - unsigned int SU_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_DEBUG_CNTL { - struct { - unsigned int SU_DEBUG_INDX : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_DEBUG_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_HARDWARE_SCREEN_OFFSET { - struct { - unsigned int HW_SCREEN_OFFSET_X : 9; - unsigned int : 7; - unsigned int HW_SCREEN_OFFSET_Y : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_LINE_CNTL { - struct { - unsigned int WIDTH : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_LINE_STIPPLE_CNTL { - struct { - unsigned int LINE_STIPPLE_RESET : 2; - unsigned int EXPAND_FULL_LENGTH : 1; - unsigned int FRACTIONAL_ACCUM : 1; - unsigned int DIAMOND_ADJUST : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_LINE_STIPPLE_SCALE { - struct { - unsigned int LINE_STIPPLE_SCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_LINE_STIPPLE_VALUE { - struct { - unsigned int LINE_STIPPLE_VALUE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER0_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER1_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER1_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER2_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PERFCOUNTER3_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_POINT_MINMAX { - struct { - unsigned int MIN_SIZE : 16; - unsigned int MAX_SIZE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_POINT_SIZE { - struct { - unsigned int HEIGHT : 16; - unsigned int WIDTH : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_POLY_OFFSET_BACK_OFFSET { - struct { - unsigned int OFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_POLY_OFFSET_BACK_SCALE { - struct { - unsigned int SCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_POLY_OFFSET_CLAMP { - struct { - unsigned int CLAMP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_POLY_OFFSET_DB_FMT_CNTL { - struct { - unsigned int POLY_OFFSET_NEG_NUM_DB_BITS : 8; - unsigned int POLY_OFFSET_DB_IS_FLOAT_FMT : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_POLY_OFFSET_FRONT_OFFSET { - struct { - unsigned int OFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_POLY_OFFSET_FRONT_SCALE { - struct { - unsigned int SCALE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_PRIM_FILTER_CNTL { - struct { - unsigned int TRIANGLE_FILTER_DISABLE : 1; - unsigned int LINE_FILTER_DISABLE : 1; - unsigned int POINT_FILTER_DISABLE : 1; - unsigned int RECTANGLE_FILTER_DISABLE : 1; - unsigned int TRIANGLE_EXPAND_ENA : 1; - unsigned int LINE_EXPAND_ENA : 1; - unsigned int POINT_EXPAND_ENA : 1; - unsigned int RECTANGLE_EXPAND_ENA : 1; - unsigned int PRIM_EXPAND_CONSTANT : 8; - unsigned int : 14; - unsigned int XMAX_RIGHT_EXCLUSION__CI__VI : 1; - unsigned int YMAX_BOTTOM_EXCLUSION__CI__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_SC_MODE_CNTL { - struct { - unsigned int CULL_FRONT : 1; - unsigned int CULL_BACK : 1; - unsigned int FACE : 1; - unsigned int POLY_MODE : 2; - unsigned int POLYMODE_FRONT_PTYPE : 3; - unsigned int POLYMODE_BACK_PTYPE : 3; - unsigned int POLY_OFFSET_FRONT_ENABLE : 1; - unsigned int POLY_OFFSET_BACK_ENABLE : 1; - unsigned int POLY_OFFSET_PARA_ENABLE : 1; - unsigned int : 2; - unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; - unsigned int : 2; - unsigned int PROVOKING_VTX_LAST : 1; - unsigned int PERSP_CORR_DIS : 1; - unsigned int MULTI_PRIM_IB_ENA : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PA_SU_VTX_CNTL { - struct { - unsigned int PIX_CENTER : 1; - unsigned int ROUND_MODE : 2; - unsigned int QUANT_MODE : 3; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_DFT_DEBUG_CTRL_REG0__CI__VI { - struct { - unsigned int DFT_PHY_DEBUG_EN : 1; - unsigned int DFT_PHY_DEBUG_MODE : 5; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_DFT_JIT_INJ_REG0__CI__VI { - struct { - unsigned int DFT_NUM_STEPS : 6; - unsigned int : 1; - unsigned int DFT_DISABLE_ERR : 1; - unsigned int DFT_CLK_PER_STEP : 4; - unsigned int : 8; - unsigned int DFT_MODE_CDR_EN : 1; - unsigned int DFT_EN_RECOVERY : 1; - unsigned int DFT_INCR_SWP_EN : 1; - unsigned int DFT_DECR_SWP_EN : 1; - unsigned int DFT_RECOVERY_TIME : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_DFT_JIT_INJ_REG1__CI__VI { - struct { - unsigned int DFT_BYPASS_VALUE : 8; - unsigned int DFT_BYPASS_EN : 1; - unsigned int : 7; - unsigned int DFT_BLOCK_EN : 1; - unsigned int DFT_NUM_OF_TESTS : 3; - unsigned int DFT_CHECK_TIME : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_DFT_JIT_INJ_REG2__CI__VI { - struct { - unsigned int DFT_LANE_EN : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_DFT_JIT_INJ_STAT_REG0__CI__VI { - struct { - unsigned int DFT_STAT_DECR : 8; - unsigned int DFT_STAT_INCR : 8; - unsigned int DFT_STAT_FINISHED : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_CTRL_REG0__CI__VI { - struct { - unsigned int BACKUP : 16; - unsigned int CFG_IDLEDET_TH : 2; - unsigned int : 2; - unsigned int DBG_RX2TXBYP_SEL : 3; - unsigned int DBG_RXFEBYP_EN : 1; - unsigned int DBG_RXPRBS_CLR : 1; - unsigned int DBG_RXTOGGLE_EN : 1; - unsigned int DBG_TX2RXLBACK_EN : 1; - unsigned int : 3; - unsigned int TXCFG_CMGOOD_RANGE : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_CTRL_REG1__CI__VI { - struct { - unsigned int RXDBG_CDR_FR_BYP_EN : 1; - unsigned int RXDBG_CDR_FR_BYP_VAL : 6; - unsigned int RXDBG_CDR_PH_BYP_EN : 1; - unsigned int RXDBG_CDR_PH_BYP_VAL : 6; - unsigned int RXDBG_D0TH_BYP_EN : 1; - unsigned int RXDBG_D0TH_BYP_VAL : 7; - unsigned int RXDBG_D1TH_BYP_EN : 1; - unsigned int RXDBG_D1TH_BYP_VAL : 7; - unsigned int TST_LOSPDTST_EN : 1; - unsigned int PLL_CFG_DISPCLK_DIV : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_CTRL_REG2__CI__VI { - struct { - unsigned int RXDBG_D2TH_BYP_EN : 1; - unsigned int RXDBG_D2TH_BYP_VAL : 7; - unsigned int RXDBG_D3TH_BYP_EN : 1; - unsigned int RXDBG_D3TH_BYP_VAL : 7; - unsigned int RXDBG_DXTH_BYP_EN : 1; - unsigned int RXDBG_DXTH_BYP_VAL : 7; - unsigned int RXDBG_ETH_BYP_EN : 1; - unsigned int RXDBG_ETH_BYP_VAL : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_CTRL_REG3__CI__VI { - struct { - unsigned int RXDBG_SEL : 5; - unsigned int BG_CFG_LC_REG_VREF0_SEL : 2; - unsigned int BG_CFG_LC_REG_VREF1_SEL : 2; - unsigned int BG_CFG_RO_REG_VREF_SEL : 2; - unsigned int BG_DBG_VREFBYP_EN : 1; - unsigned int BG_DBG_IREFBYP_EN : 1; - unsigned int : 1; - unsigned int BG_DBG_ANALOG_SEL : 3; - unsigned int : 1; - unsigned int DBG_DLL_CLK_SEL : 3; - unsigned int PLL_DISPCLK_CMOS_SEL : 1; - unsigned int DBG_RXPI_OFFSET_BYP_EN : 1; - unsigned int DBG_RXPI_OFFSET_BYP_VAL : 4; - unsigned int DBG_RXSWAPDX_BYP_EN : 1; - unsigned int DBG_RXSWAPDX_BYP_VAL : 3; - unsigned int DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_CTRL_REG4__CI__VI { - struct { - unsigned int DBG_RXAPU_INST : 16; - unsigned int DBG_RXDFEMUX_BYP_VAL : 2; - unsigned int DBG_RXDFEMUX_BYP_EN : 1; - unsigned int : 3; - unsigned int DBG_RXAPU_EXEC : 4; - unsigned int DBG_RXDLL_VREG_REF_SEL : 1; - unsigned int PWRGOOD_OVRD : 1; - unsigned int DBG_RXRDATA_GATING_DISABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_CTRL_REG5__CI__VI { - struct { - unsigned int DBG_RXAPU_MODE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_OVRD_REG0__CI__VI { - struct { - unsigned int TXPDTERM_VAL_OVRD_VAL : 16; - unsigned int TXPUTERM_VAL_OVRD_VAL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_OVRD_REG1__CI__VI { - struct { - unsigned int TXPDTERM_VAL_OVRD_EN : 1; - unsigned int TXPUTERM_VAL_OVRD_EN : 1; - unsigned int TST_LOSPDTST_RST_OVRD_EN : 1; - unsigned int TST_LOSPDTST_RST_OVRD_VAL : 1; - unsigned int : 11; - unsigned int RXTERM_VAL_OVRD_EN : 1; - unsigned int RXTERM_VAL_OVRD_VAL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_OVRD_REG2__CI__VI { - struct { - unsigned int BG_PWRON_OVRD_EN : 1; - unsigned int BG_PWRON_OVRD_VAL : 1; - unsigned int PLL_DBG_LC_EXT_RESET_OVRD_EN__VI : 1; - unsigned int PLL_DBG_LC_EXT_RESET_OVRD_VAL__VI : 1; - unsigned int PLL_DBG_RO_EXT_RESET_OVRD_EN__VI : 1; - unsigned int PLL_DBG_RO_EXT_RESET_OVRD_VAL__VI : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int IGNR_ALL_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_ALL_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_ALL_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_ALL_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_IMPCAL_ACTIVE_SCI_UPDT : 1; - unsigned int : 3; - unsigned int TXNIMP : 4; - unsigned int TXPIMP : 4; - unsigned int RXIMP : 4; - unsigned int IMPCAL_ACTIVE : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int IGNR_ALL_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_ALL_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_ALL_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_ALL_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_IMPCAL_ACTIVE_CBI_UPDT : 1; - unsigned int : 3; - unsigned int TXNIMP : 4; - unsigned int TXPIMP : 4; - unsigned int RXIMP : 4; - unsigned int IMPCAL_ACTIVE : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_SCI_STAT_OVRD_REG1__CI { - struct { - unsigned int IGNR_MODE_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_FREQDIV_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_DLL_LOCK_SCI_UPDT_L0T3 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_0 : 1; - unsigned int DLL_LOCK_1 : 1; - unsigned int DLL_LOCK_2 : 1; - unsigned int DLL_LOCK_3 : 1; - unsigned int MODE_0 : 2; - unsigned int FREQDIV_0 : 2; - unsigned int MODE_1 : 2; - unsigned int FREQDIV_1 : 2; - unsigned int MODE_2 : 2; - unsigned int FREQDIV_2 : 2; - unsigned int MODE_3 : 2; - unsigned int FREQDIV_3 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_SCI_STAT_OVRD_REG1__VI { - struct { - unsigned int IGNR_LINKSPEED_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_FREQDIV_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_DLL_LOCK_CBI_UPDT_L0T3 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_0 : 1; - unsigned int DLL_LOCK_1 : 1; - unsigned int DLL_LOCK_2 : 1; - unsigned int DLL_LOCK_3 : 1; - unsigned int LINKSPEED_0 : 2; - unsigned int FREQDIV_0 : 2; - unsigned int LINKSPEED_1 : 2; - unsigned int FREQDIV_1 : 2; - unsigned int LINKSPEED_2 : 2; - unsigned int FREQDIV_2 : 2; - unsigned int LINKSPEED_3 : 2; - unsigned int FREQDIV_3 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_SCI_STAT_OVRD_REG2__CI { - struct { - unsigned int IGNR_MODE_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_FREQDIV_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_DLL_LOCK_SCI_UPDT_L4T7 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_4 : 1; - unsigned int DLL_LOCK_5 : 1; - unsigned int DLL_LOCK_6 : 1; - unsigned int DLL_LOCK_7 : 1; - unsigned int MODE_4 : 2; - unsigned int FREQDIV_4 : 2; - unsigned int MODE_5 : 2; - unsigned int FREQDIV_5 : 2; - unsigned int MODE_6 : 2; - unsigned int FREQDIV_6 : 2; - unsigned int MODE_7 : 2; - unsigned int FREQDIV_7 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_SCI_STAT_OVRD_REG2__VI { - struct { - unsigned int IGNR_LINKSPEED_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_FREQDIV_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_DLL_LOCK_CBI_UPDT_L4T7 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_4 : 1; - unsigned int DLL_LOCK_5 : 1; - unsigned int DLL_LOCK_6 : 1; - unsigned int DLL_LOCK_7 : 1; - unsigned int LINKSPEED_4 : 2; - unsigned int FREQDIV_4 : 2; - unsigned int LINKSPEED_5 : 2; - unsigned int FREQDIV_5 : 2; - unsigned int LINKSPEED_6 : 2; - unsigned int FREQDIV_6 : 2; - unsigned int LINKSPEED_7 : 2; - unsigned int FREQDIV_7 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_SCI_STAT_OVRD_REG3__CI { - struct { - unsigned int IGNR_MODE_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_FREQDIV_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_DLL_LOCK_SCI_UPDT_L8T11 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_8 : 1; - unsigned int DLL_LOCK_9 : 1; - unsigned int DLL_LOCK_10 : 1; - unsigned int DLL_LOCK_11 : 1; - unsigned int MODE_8 : 2; - unsigned int FREQDIV_8 : 2; - unsigned int MODE_9 : 2; - unsigned int FREQDIV_9 : 2; - unsigned int MODE_10 : 2; - unsigned int FREQDIV_10 : 2; - unsigned int MODE_11 : 2; - unsigned int FREQDIV_11 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_SCI_STAT_OVRD_REG3__VI { - struct { - unsigned int IGNR_LINKSPEED_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_FREQDIV_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_DLL_LOCK_CBI_UPDT_L8T11 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_8 : 1; - unsigned int DLL_LOCK_9 : 1; - unsigned int DLL_LOCK_10 : 1; - unsigned int DLL_LOCK_11 : 1; - unsigned int LINKSPEED_8 : 2; - unsigned int FREQDIV_8 : 2; - unsigned int LINKSPEED_9 : 2; - unsigned int FREQDIV_9 : 2; - unsigned int LINKSPEED_10 : 2; - unsigned int FREQDIV_10 : 2; - unsigned int LINKSPEED_11 : 2; - unsigned int FREQDIV_11 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_SCI_STAT_OVRD_REG4__CI { - struct { - unsigned int IGNR_MODE_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_FREQDIV_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_DLL_LOCK_SCI_UPDT_L12T15 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_12 : 1; - unsigned int DLL_LOCK_13 : 1; - unsigned int DLL_LOCK_14 : 1; - unsigned int DLL_LOCK_15 : 1; - unsigned int MODE_12 : 2; - unsigned int FREQDIV_12 : 2; - unsigned int MODE_13 : 2; - unsigned int FREQDIV_13 : 2; - unsigned int MODE_14 : 2; - unsigned int FREQDIV_14 : 2; - unsigned int MODE_15 : 2; - unsigned int FREQDIV_15 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_GLB_SCI_STAT_OVRD_REG4__VI { - struct { - unsigned int IGNR_LINKSPEED_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_FREQDIV_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_DLL_LOCK_CBI_UPDT_L12T15 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_12 : 1; - unsigned int DLL_LOCK_13 : 1; - unsigned int DLL_LOCK_14 : 1; - unsigned int DLL_LOCK_15 : 1; - unsigned int LINKSPEED_12 : 2; - unsigned int FREQDIV_12 : 2; - unsigned int LINKSPEED_13 : 2; - unsigned int FREQDIV_13 : 2; - unsigned int LINKSPEED_14 : 2; - unsigned int FREQDIV_14 : 2; - unsigned int LINKSPEED_15 : 2; - unsigned int FREQDIV_15 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_HW_DEBUG__CI { - struct { - unsigned int PB0_HW_00_DEBUG : 1; - unsigned int PB0_HW_01_DEBUG : 1; - unsigned int PB0_HW_02_DEBUG : 1; - unsigned int PB0_HW_03_DEBUG : 1; - unsigned int PB0_HW_04_DEBUG : 1; - unsigned int PB0_HW_05_DEBUG : 1; - unsigned int PB0_HW_06_DEBUG : 1; - unsigned int PB0_HW_07_DEBUG : 1; - unsigned int PB0_HW_08_DEBUG : 1; - unsigned int PB0_HW_09_DEBUG : 1; - unsigned int PB0_HW_10_DEBUG : 1; - unsigned int PB0_HW_11_DEBUG : 1; - unsigned int PB0_HW_12_DEBUG : 1; - unsigned int PB0_HW_13_DEBUG : 1; - unsigned int PB0_HW_14_DEBUG : 1; - unsigned int PB0_HW_15_DEBUG : 1; - unsigned int PB0_HW_16_DEBUG : 1; - unsigned int PB0_HW_17_DEBUG : 1; - unsigned int PB0_HW_18_DEBUG : 1; - unsigned int PB0_HW_19_DEBUG : 1; - unsigned int PB0_HW_20_DEBUG : 1; - unsigned int PB0_HW_21_DEBUG : 1; - unsigned int PB0_HW_22_DEBUG : 1; - unsigned int PB0_HW_23_DEBUG : 1; - unsigned int PB0_HW_24_DEBUG : 1; - unsigned int PB0_HW_25_DEBUG : 1; - unsigned int PB0_HW_26_DEBUG : 1; - unsigned int PB0_HW_27_DEBUG : 1; - unsigned int PB0_HW_28_DEBUG : 1; - unsigned int PB0_HW_29_DEBUG : 1; - unsigned int PB0_HW_30_DEBUG : 1; - unsigned int PB0_HW_31_DEBUG : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_HW_DEBUG__VI { - struct { - unsigned int HW_00_DEBUG : 1; - unsigned int HW_01_DEBUG : 1; - unsigned int HW_02_DEBUG : 1; - unsigned int HW_03_DEBUG : 1; - unsigned int HW_04_DEBUG : 1; - unsigned int HW_05_DEBUG : 1; - unsigned int HW_06_DEBUG : 1; - unsigned int HW_07_DEBUG : 1; - unsigned int HW_08_DEBUG : 1; - unsigned int HW_09_DEBUG : 1; - unsigned int HW_10_DEBUG : 1; - unsigned int HW_11_DEBUG : 1; - unsigned int HW_12_DEBUG : 1; - unsigned int HW_13_DEBUG : 1; - unsigned int HW_14_DEBUG : 1; - unsigned int HW_15_DEBUG : 1; - unsigned int HW_16_DEBUG : 1; - unsigned int HW_17_DEBUG : 1; - unsigned int HW_18_DEBUG : 1; - unsigned int HW_19_DEBUG : 1; - unsigned int HW_20_DEBUG : 1; - unsigned int HW_21_DEBUG : 1; - unsigned int HW_22_DEBUG : 1; - unsigned int HW_23_DEBUG : 1; - unsigned int HW_24_DEBUG : 1; - unsigned int HW_25_DEBUG : 1; - unsigned int HW_26_DEBUG : 1; - unsigned int HW_27_DEBUG : 1; - unsigned int HW_28_DEBUG : 1; - unsigned int HW_29_DEBUG : 1; - unsigned int HW_30_DEBUG : 1; - unsigned int HW_31_DEBUG : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_CNTL2__CI { - struct { - unsigned int : 1; - unsigned int RXDETECT_SAMPL_TIME : 2; - unsigned int : 4; - unsigned int RXDETECT_OVERRIDE_EN : 1; - unsigned int RXDETECT_OVERRIDE_VAL_0 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_1 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_2 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_3 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_4 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_5 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_6 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_7 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_8 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_9 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_10 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_11 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_12 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_13 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_14 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_15 : 1; - unsigned int RXPHYSTATUS_DELAY : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_CNTL__CI { - struct { - unsigned int SERIAL_CFG_ENABLE : 1; - unsigned int DA_FIFO_RESET_0 : 1; - unsigned int PHY_CR_EN_MODE : 1; - unsigned int PHYCMD_CR_EN_MODE : 1; - unsigned int EI_DET_CYCLE_MODE : 1; - unsigned int DA_FIFO_RESET_1 : 1; - unsigned int RXDETECT_FIFO_RESET_MODE : 1; - unsigned int RXDETECT_TX_PWR_MODE : 1; - unsigned int DIVINIT_MODE : 1; - unsigned int DA_FIFO_RESET_2 : 1; - unsigned int PLL_BINDING_ENABLE : 1; - unsigned int SC_CALIB_DONE_CNTL : 1; - unsigned int : 1; - unsigned int DA_FIFO_RESET_3 : 1; - unsigned int : 2; - unsigned int TXGND_TIME : 1; - unsigned int LS2_EXIT_TIME : 3; - unsigned int EI_CYCLE_OFF_TIME : 3; - unsigned int EXIT_L0S_INIT_DIS : 1; - unsigned int RXEN_GATER : 4; - unsigned int EXTEND_WAIT_FOR_RAMPUP : 1; - unsigned int IGNORE_TxDataValid_EP_DIS : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_HW_DEBUG__CI { - struct { - unsigned int PB0_PIF_HW_00_DEBUG : 1; - unsigned int PB0_PIF_HW_01_DEBUG : 1; - unsigned int PB0_PIF_HW_02_DEBUG : 1; - unsigned int PB0_PIF_HW_03_DEBUG : 1; - unsigned int PB0_PIF_HW_04_DEBUG : 1; - unsigned int PB0_PIF_HW_05_DEBUG : 1; - unsigned int PB0_PIF_HW_06_DEBUG : 1; - unsigned int PB0_PIF_HW_07_DEBUG : 1; - unsigned int PB0_PIF_HW_08_DEBUG : 1; - unsigned int PB0_PIF_HW_09_DEBUG : 1; - unsigned int PB0_PIF_HW_10_DEBUG : 1; - unsigned int PB0_PIF_HW_11_DEBUG : 1; - unsigned int PB0_PIF_HW_12_DEBUG : 1; - unsigned int PB0_PIF_HW_13_DEBUG : 1; - unsigned int PB0_PIF_HW_14_DEBUG : 1; - unsigned int PB0_PIF_HW_15_DEBUG : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_HW_DEBUG__VI { - struct { - unsigned int HW_00_DEBUG : 1; - unsigned int HW_01_DEBUG : 1; - unsigned int HW_02_DEBUG : 1; - unsigned int HW_03_DEBUG : 1; - unsigned int HW_04_DEBUG : 1; - unsigned int HW_05_DEBUG : 1; - unsigned int HW_06_DEBUG : 1; - unsigned int HW_07_DEBUG : 1; - unsigned int HW_08_DEBUG : 1; - unsigned int HW_09_DEBUG : 1; - unsigned int HW_10_DEBUG : 1; - unsigned int HW_11_DEBUG : 1; - unsigned int HW_12_DEBUG : 1; - unsigned int HW_13_DEBUG : 1; - unsigned int HW_14_DEBUG : 1; - unsigned int HW_15_DEBUG : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PAIRING__CI { - struct { - unsigned int X2_LANE_1_0 : 1; - unsigned int X2_LANE_3_2 : 1; - unsigned int X2_LANE_5_4 : 1; - unsigned int X2_LANE_7_6 : 1; - unsigned int X2_LANE_9_8 : 1; - unsigned int X2_LANE_11_10 : 1; - unsigned int X2_LANE_13_12 : 1; - unsigned int X2_LANE_15_14 : 1; - unsigned int X4_LANE_3_0 : 1; - unsigned int X4_LANE_7_4 : 1; - unsigned int X4_LANE_11_8 : 1; - unsigned int X4_LANE_15_12 : 1; - unsigned int : 4; - unsigned int X8_LANE_7_0 : 1; - unsigned int X8_LANE_15_8 : 1; - unsigned int : 2; - unsigned int X16_LANE_15_0 : 1; - unsigned int : 4; - unsigned int MULTI_PIF : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_0__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_0 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_0 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_0 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_0 : 3; - unsigned int RXEN_OVERRIDE_EN_0 : 1; - unsigned int RXEN_OVERRIDE_VAL_0 : 1; - unsigned int TXPWR_OVERRIDE_EN_0 : 1; - unsigned int TXPWR_OVERRIDE_VAL_0 : 3; - unsigned int RXPWR_OVERRIDE_EN_0 : 1; - unsigned int RXPWR_OVERRIDE_VAL_0 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_10__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_10 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_10 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_10 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_10 : 3; - unsigned int RXEN_OVERRIDE_EN_10 : 1; - unsigned int RXEN_OVERRIDE_VAL_10 : 1; - unsigned int TXPWR_OVERRIDE_EN_10 : 1; - unsigned int TXPWR_OVERRIDE_VAL_10 : 3; - unsigned int RXPWR_OVERRIDE_EN_10 : 1; - unsigned int RXPWR_OVERRIDE_VAL_10 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_11__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_11 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_11 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_11 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_11 : 3; - unsigned int RXEN_OVERRIDE_EN_11 : 1; - unsigned int RXEN_OVERRIDE_VAL_11 : 1; - unsigned int TXPWR_OVERRIDE_EN_11 : 1; - unsigned int TXPWR_OVERRIDE_VAL_11 : 3; - unsigned int RXPWR_OVERRIDE_EN_11 : 1; - unsigned int RXPWR_OVERRIDE_VAL_11 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_12__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_12 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_12 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_12 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_12 : 3; - unsigned int RXEN_OVERRIDE_EN_12 : 1; - unsigned int RXEN_OVERRIDE_VAL_12 : 1; - unsigned int TXPWR_OVERRIDE_EN_12 : 1; - unsigned int TXPWR_OVERRIDE_VAL_12 : 3; - unsigned int RXPWR_OVERRIDE_EN_12 : 1; - unsigned int RXPWR_OVERRIDE_VAL_12 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_13__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_13 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_13 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_13 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_13 : 3; - unsigned int RXEN_OVERRIDE_EN_13 : 1; - unsigned int RXEN_OVERRIDE_VAL_13 : 1; - unsigned int TXPWR_OVERRIDE_EN_13 : 1; - unsigned int TXPWR_OVERRIDE_VAL_13 : 3; - unsigned int RXPWR_OVERRIDE_EN_13 : 1; - unsigned int RXPWR_OVERRIDE_VAL_13 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_14__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_14 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_14 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_14 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_14 : 3; - unsigned int RXEN_OVERRIDE_EN_14 : 1; - unsigned int RXEN_OVERRIDE_VAL_14 : 1; - unsigned int TXPWR_OVERRIDE_EN_14 : 1; - unsigned int TXPWR_OVERRIDE_VAL_14 : 3; - unsigned int RXPWR_OVERRIDE_EN_14 : 1; - unsigned int RXPWR_OVERRIDE_VAL_14 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_15__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_15 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_15 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_15 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_15 : 3; - unsigned int RXEN_OVERRIDE_EN_15 : 1; - unsigned int RXEN_OVERRIDE_VAL_15 : 1; - unsigned int TXPWR_OVERRIDE_EN_15 : 1; - unsigned int TXPWR_OVERRIDE_VAL_15 : 3; - unsigned int RXPWR_OVERRIDE_EN_15 : 1; - unsigned int RXPWR_OVERRIDE_VAL_15 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_1__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_1 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_1 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_1 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_1 : 3; - unsigned int RXEN_OVERRIDE_EN_1 : 1; - unsigned int RXEN_OVERRIDE_VAL_1 : 1; - unsigned int TXPWR_OVERRIDE_EN_1 : 1; - unsigned int TXPWR_OVERRIDE_VAL_1 : 3; - unsigned int RXPWR_OVERRIDE_EN_1 : 1; - unsigned int RXPWR_OVERRIDE_VAL_1 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_2__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_2 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_2 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_2 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_2 : 3; - unsigned int RXEN_OVERRIDE_EN_2 : 1; - unsigned int RXEN_OVERRIDE_VAL_2 : 1; - unsigned int TXPWR_OVERRIDE_EN_2 : 1; - unsigned int TXPWR_OVERRIDE_VAL_2 : 3; - unsigned int RXPWR_OVERRIDE_EN_2 : 1; - unsigned int RXPWR_OVERRIDE_VAL_2 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_3__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_3 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_3 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_3 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_3 : 3; - unsigned int RXEN_OVERRIDE_EN_3 : 1; - unsigned int RXEN_OVERRIDE_VAL_3 : 1; - unsigned int TXPWR_OVERRIDE_EN_3 : 1; - unsigned int TXPWR_OVERRIDE_VAL_3 : 3; - unsigned int RXPWR_OVERRIDE_EN_3 : 1; - unsigned int RXPWR_OVERRIDE_VAL_3 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_4__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_4 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_4 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_4 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_4 : 3; - unsigned int RXEN_OVERRIDE_EN_4 : 1; - unsigned int RXEN_OVERRIDE_VAL_4 : 1; - unsigned int TXPWR_OVERRIDE_EN_4 : 1; - unsigned int TXPWR_OVERRIDE_VAL_4 : 3; - unsigned int RXPWR_OVERRIDE_EN_4 : 1; - unsigned int RXPWR_OVERRIDE_VAL_4 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_5__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_5 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_5 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_5 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_5 : 3; - unsigned int RXEN_OVERRIDE_EN_5 : 1; - unsigned int RXEN_OVERRIDE_VAL_5 : 1; - unsigned int TXPWR_OVERRIDE_EN_5 : 1; - unsigned int TXPWR_OVERRIDE_VAL_5 : 3; - unsigned int RXPWR_OVERRIDE_EN_5 : 1; - unsigned int RXPWR_OVERRIDE_VAL_5 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_6__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_6 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_6 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_6 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_6 : 3; - unsigned int RXEN_OVERRIDE_EN_6 : 1; - unsigned int RXEN_OVERRIDE_VAL_6 : 1; - unsigned int TXPWR_OVERRIDE_EN_6 : 1; - unsigned int TXPWR_OVERRIDE_VAL_6 : 3; - unsigned int RXPWR_OVERRIDE_EN_6 : 1; - unsigned int RXPWR_OVERRIDE_VAL_6 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_7__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_7 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_7 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_7 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_7 : 3; - unsigned int RXEN_OVERRIDE_EN_7 : 1; - unsigned int RXEN_OVERRIDE_VAL_7 : 1; - unsigned int TXPWR_OVERRIDE_EN_7 : 1; - unsigned int TXPWR_OVERRIDE_VAL_7 : 3; - unsigned int RXPWR_OVERRIDE_EN_7 : 1; - unsigned int RXPWR_OVERRIDE_VAL_7 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_8__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_8 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_8 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_8 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_8 : 3; - unsigned int RXEN_OVERRIDE_EN_8 : 1; - unsigned int RXEN_OVERRIDE_VAL_8 : 1; - unsigned int TXPWR_OVERRIDE_EN_8 : 1; - unsigned int TXPWR_OVERRIDE_VAL_8 : 3; - unsigned int RXPWR_OVERRIDE_EN_8 : 1; - unsigned int RXPWR_OVERRIDE_VAL_8 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PDNB_OVERRIDE_9__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_9 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_9 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_9 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_9 : 3; - unsigned int RXEN_OVERRIDE_EN_9 : 1; - unsigned int RXEN_OVERRIDE_VAL_9 : 1; - unsigned int TXPWR_OVERRIDE_EN_9 : 1; - unsigned int TXPWR_OVERRIDE_VAL_9 : 3; - unsigned int RXPWR_OVERRIDE_EN_9 : 1; - unsigned int RXPWR_OVERRIDE_VAL_9 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PWRDOWN_0__CI { - struct { - unsigned int TX_POWER_STATE_IN_TXS2_0 : 3; - unsigned int FORCE_RXEN_IN_L0s_0 : 1; - unsigned int RX_POWER_STATE_IN_RXS2_0 : 3; - unsigned int PLL_POWER_STATE_IN_TXS2_0 : 3; - unsigned int PLL_POWER_STATE_IN_OFF_0 : 3; - unsigned int : 3; - unsigned int TX2P5CLK_CLOCK_GATING_EN_0 : 1; - unsigned int : 7; - unsigned int PLL_RAMP_UP_TIME_0 : 3; - unsigned int : 1; - unsigned int PLLPWR_OVERRIDE_EN_0 : 1; - unsigned int PLLPWR_OVERRIDE_VAL_0 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PWRDOWN_1__CI { - struct { - unsigned int TX_POWER_STATE_IN_TXS2_1 : 3; - unsigned int FORCE_RXEN_IN_L0s_1 : 1; - unsigned int RX_POWER_STATE_IN_RXS2_1 : 3; - unsigned int PLL_POWER_STATE_IN_TXS2_1 : 3; - unsigned int PLL_POWER_STATE_IN_OFF_1 : 3; - unsigned int : 3; - unsigned int TX2P5CLK_CLOCK_GATING_EN_1 : 1; - unsigned int : 7; - unsigned int PLL_RAMP_UP_TIME_1 : 3; - unsigned int : 1; - unsigned int PLLPWR_OVERRIDE_EN_1 : 1; - unsigned int PLLPWR_OVERRIDE_VAL_1 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PWRDOWN_2__CI { - struct { - unsigned int TX_POWER_STATE_IN_TXS2_2 : 3; - unsigned int FORCE_RXEN_IN_L0s_2 : 1; - unsigned int RX_POWER_STATE_IN_RXS2_2 : 3; - unsigned int PLL_POWER_STATE_IN_TXS2_2 : 3; - unsigned int PLL_POWER_STATE_IN_OFF_2 : 3; - unsigned int : 3; - unsigned int TX2P5CLK_CLOCK_GATING_EN_2 : 1; - unsigned int : 7; - unsigned int PLL_RAMP_UP_TIME_2 : 3; - unsigned int : 1; - unsigned int PLLPWR_OVERRIDE_EN_2 : 1; - unsigned int PLLPWR_OVERRIDE_VAL_2 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_PWRDOWN_3__CI { - struct { - unsigned int TX_POWER_STATE_IN_TXS2_3 : 3; - unsigned int FORCE_RXEN_IN_L0s_3 : 1; - unsigned int RX_POWER_STATE_IN_RXS2_3 : 3; - unsigned int PLL_POWER_STATE_IN_TXS2_3 : 3; - unsigned int PLL_POWER_STATE_IN_OFF_3 : 3; - unsigned int : 3; - unsigned int TX2P5CLK_CLOCK_GATING_EN_3 : 1; - unsigned int : 7; - unsigned int PLL_RAMP_UP_TIME_3 : 3; - unsigned int : 1; - unsigned int PLLPWR_OVERRIDE_EN_3 : 1; - unsigned int PLLPWR_OVERRIDE_VAL_3 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SCRATCH__CI__VI { - struct { - unsigned int PIF_SCRATCH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SC_CTL__CI { - struct { - unsigned int SC_CALIBRATION : 1; - unsigned int SC_RXDETECT : 1; - unsigned int SC_EXIT_L1_TO_L0S : 1; - unsigned int SC_EXIT_L1_TO_L0 : 1; - unsigned int SC_ENTER_L1_FROM_L0S : 1; - unsigned int SC_ENTER_L1_FROM_L0 : 1; - unsigned int SC_SPEED_CHANGE : 1; - unsigned int : 1; - unsigned int SC_PHASE_1 : 1; - unsigned int SC_PHASE_2 : 1; - unsigned int SC_PHASE_3 : 1; - unsigned int SC_PHASE_4 : 1; - unsigned int SC_PHASE_5 : 1; - unsigned int SC_PHASE_6 : 1; - unsigned int SC_PHASE_7 : 1; - unsigned int SC_PHASE_8 : 1; - unsigned int SC_LANE_0_RESUME : 1; - unsigned int SC_LANE_1_RESUME : 1; - unsigned int SC_LANE_2_RESUME : 1; - unsigned int SC_LANE_3_RESUME : 1; - unsigned int SC_LANE_4_RESUME : 1; - unsigned int SC_LANE_5_RESUME : 1; - unsigned int SC_LANE_6_RESUME : 1; - unsigned int SC_LANE_7_RESUME : 1; - unsigned int SC_LANE_8_RESUME : 1; - unsigned int SC_LANE_9_RESUME : 1; - unsigned int SC_LANE_10_RESUME : 1; - unsigned int SC_LANE_11_RESUME : 1; - unsigned int SC_LANE_12_RESUME : 1; - unsigned int SC_LANE_13_RESUME : 1; - unsigned int SC_LANE_14_RESUME : 1; - unsigned int SC_LANE_15_RESUME : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_0__CI { - struct { - unsigned int SEQ_CALIBRATION_0 : 1; - unsigned int SEQ_RXDETECT_0 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_0 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_0 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_0 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_0 : 1; - unsigned int SEQ_SPEED_CHANGE_0 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_0 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_10__CI { - struct { - unsigned int SEQ_CALIBRATION_10 : 1; - unsigned int SEQ_RXDETECT_10 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_10 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_10 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_10 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_10 : 1; - unsigned int SEQ_SPEED_CHANGE_10 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_10 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_11__CI { - struct { - unsigned int SEQ_CALIBRATION_11 : 1; - unsigned int SEQ_RXDETECT_11 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_11 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_11 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_11 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_11 : 1; - unsigned int SEQ_SPEED_CHANGE_11 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_11 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_12__CI { - struct { - unsigned int SEQ_CALIBRATION_12 : 1; - unsigned int SEQ_RXDETECT_12 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_12 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_12 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_12 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_12 : 1; - unsigned int SEQ_SPEED_CHANGE_12 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_12 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_13__CI { - struct { - unsigned int SEQ_CALIBRATION_13 : 1; - unsigned int SEQ_RXDETECT_13 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_13 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_13 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_13 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_13 : 1; - unsigned int SEQ_SPEED_CHANGE_13 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_13 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_14__CI { - struct { - unsigned int SEQ_CALIBRATION_14 : 1; - unsigned int SEQ_RXDETECT_14 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_14 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_14 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_14 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_14 : 1; - unsigned int SEQ_SPEED_CHANGE_14 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_14 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_15__CI { - struct { - unsigned int SEQ_CALIBRATION_15 : 1; - unsigned int SEQ_RXDETECT_15 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_15 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_15 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_15 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_15 : 1; - unsigned int SEQ_SPEED_CHANGE_15 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_15 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_1__CI { - struct { - unsigned int SEQ_CALIBRATION_1 : 1; - unsigned int SEQ_RXDETECT_1 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_1 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_1 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_1 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_1 : 1; - unsigned int SEQ_SPEED_CHANGE_1 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_1 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_2__CI { - struct { - unsigned int SEQ_CALIBRATION_2 : 1; - unsigned int SEQ_RXDETECT_2 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_2 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_2 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_2 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_2 : 1; - unsigned int SEQ_SPEED_CHANGE_2 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_2 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_3__CI { - struct { - unsigned int SEQ_CALIBRATION_3 : 1; - unsigned int SEQ_RXDETECT_3 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_3 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_3 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_3 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_3 : 1; - unsigned int SEQ_SPEED_CHANGE_3 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_3 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_4__CI { - struct { - unsigned int SEQ_CALIBRATION_4 : 1; - unsigned int SEQ_RXDETECT_4 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_4 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_4 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_4 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_4 : 1; - unsigned int SEQ_SPEED_CHANGE_4 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_4 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_5__CI { - struct { - unsigned int SEQ_CALIBRATION_5 : 1; - unsigned int SEQ_RXDETECT_5 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_5 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_5 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_5 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_5 : 1; - unsigned int SEQ_SPEED_CHANGE_5 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_5 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_6__CI { - struct { - unsigned int SEQ_CALIBRATION_6 : 1; - unsigned int SEQ_RXDETECT_6 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_6 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_6 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_6 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_6 : 1; - unsigned int SEQ_SPEED_CHANGE_6 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_6 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_7__CI { - struct { - unsigned int SEQ_CALIBRATION_7 : 1; - unsigned int SEQ_RXDETECT_7 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_7 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_7 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_7 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_7 : 1; - unsigned int SEQ_SPEED_CHANGE_7 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_7 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_8__CI { - struct { - unsigned int SEQ_CALIBRATION_8 : 1; - unsigned int SEQ_RXDETECT_8 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_8 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_8 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_8 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_8 : 1; - unsigned int SEQ_SPEED_CHANGE_8 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_8 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_SEQ_STATUS_9__CI { - struct { - unsigned int SEQ_CALIBRATION_9 : 1; - unsigned int SEQ_RXDETECT_9 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_9 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_9 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_9 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_9 : 1; - unsigned int SEQ_SPEED_CHANGE_9 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_9 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_TXPHYSTATUS__CI { - struct { - unsigned int TXPHYSTATUS_0 : 1; - unsigned int TXPHYSTATUS_1 : 1; - unsigned int TXPHYSTATUS_2 : 1; - unsigned int TXPHYSTATUS_3 : 1; - unsigned int TXPHYSTATUS_4 : 1; - unsigned int TXPHYSTATUS_5 : 1; - unsigned int TXPHYSTATUS_6 : 1; - unsigned int TXPHYSTATUS_7 : 1; - unsigned int TXPHYSTATUS_8 : 1; - unsigned int TXPHYSTATUS_9 : 1; - unsigned int TXPHYSTATUS_10 : 1; - unsigned int TXPHYSTATUS_11 : 1; - unsigned int TXPHYSTATUS_12 : 1; - unsigned int TXPHYSTATUS_13 : 1; - unsigned int TXPHYSTATUS_14 : 1; - unsigned int TXPHYSTATUS_15 : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_LC0_CTRL_REG0__CI__VI { - struct { - unsigned int PLL_DBG_LC_ANALOG_SEL_0 : 2; - unsigned int PLL_DBG_LC_EXT_RESET_EN_0 : 1; - unsigned int PLL_DBG_LC_VCTL_ADC_EN_0 : 1; - unsigned int PLL_TST_LC_USAMPLE_EN_0 : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_LC0_OVRD_REG0__CI__VI { - struct { - unsigned int PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 : 3; - unsigned int PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 : 1; - unsigned int PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0 : 3; - unsigned int PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 : 1; - unsigned int PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 : 1; - unsigned int PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 : 1; - unsigned int PLL_CFG_LC_FBDIV_OVRD_VAL_0 : 8; - unsigned int PLL_CFG_LC_FBDIV_OVRD_EN_0 : 1; - unsigned int PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 : 9; - unsigned int PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 : 1; - unsigned int PLL_CFG_LC_REFDIV_OVRD_VAL_0 : 2; - unsigned int PLL_CFG_LC_REFDIV_OVRD_EN_0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_LC0_OVRD_REG1__CI__VI { - struct { - unsigned int PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0 : 3; - unsigned int PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 : 1; - unsigned int PLL_LC_PWRON_OVRD_VAL_0 : 1; - unsigned int PLL_LC_PWRON_OVRD_EN_0 : 1; - unsigned int : 4; - unsigned int PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 : 4; - unsigned int PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_LC0_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_LC0_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_LC0_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_LC0_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_LC0_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_LC0_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_LC0_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int : 3; - unsigned int PLL_LC0_PLLPWR : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_LC1_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_LC1_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_LC1_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_LC1_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_LC1_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_LC1_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_LC1_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int : 3; - unsigned int PLL_LC1_PLLPWR : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_LC2_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_LC2_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_LC2_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_LC2_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_LC2_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_LC2_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_LC2_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int : 3; - unsigned int PLL_LC2_PLLPWR : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_LC3_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_LC3_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_LC3_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_LC3_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_LC3_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_LC3_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_LC3_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int : 3; - unsigned int PLL_LC3_PLLPWR : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO0_CTRL_REG0__CI__VI { - struct { - unsigned int PLL_DBG_RO_ANALOG_SEL_0 : 2; - unsigned int PLL_DBG_RO_EXT_RESET_EN_0 : 1; - unsigned int PLL_DBG_RO_VCTL_ADC_EN_0 : 1; - unsigned int PLL_DBG_RO_LF_CNTRL_0 : 7; - unsigned int PLL_TST_RO_USAMPLE_EN_0 : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO0_OVRD_REG0__CI__VI { - struct { - unsigned int PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 : 8; - unsigned int PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 : 1; - unsigned int PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 : 3; - unsigned int PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 : 1; - unsigned int PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 : 1; - unsigned int PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 : 1; - unsigned int PLL_CFG_RO_FBDIV_OVRD_VAL_0 : 13; - unsigned int PLL_CFG_RO_FBDIV_OVRD_EN_0 : 1; - unsigned int : 1; - unsigned int PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0 : 1; - unsigned int PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO0_OVRD_REG1__CI__VI { - struct { - unsigned int PLL_CFG_RO_REFDIV_OVRD_VAL_0 : 5; - unsigned int PLL_CFG_RO_REFDIV_OVRD_EN_0 : 1; - unsigned int PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 : 2; - unsigned int PLL_CFG_RO_VCO_MODE_OVRD_EN_0 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 : 1; - unsigned int PLL_RO_PWRON_OVRD_VAL_0 : 1; - unsigned int PLL_RO_PWRON_OVRD_EN_0 : 1; - unsigned int : 4; - unsigned int PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0 : 3; - unsigned int PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO0_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_RO0_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_RO0_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO0_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO0_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO0_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_RO0_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int PLL_RO0_IGNR_PLLFREQ_CBI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO0_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO0_PLLFREQ : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO1_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_RO1_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_RO1_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO1_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO1_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO1_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_RO1_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int PLL_RO1_IGNR_PLLFREQ_CBI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO1_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO1_PLLFREQ : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO2_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_RO2_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_RO2_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO2_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO2_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO2_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_RO2_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int PLL_RO2_IGNR_PLLFREQ_CBI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO2_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO2_PLLFREQ : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO3_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_RO3_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_RO3_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO3_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO3_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO3_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_RO3_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int PLL_RO3_IGNR_PLLFREQ_CBI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO3_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO3_PLLFREQ : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO_GLB_CTRL_REG0__CI { - struct { - unsigned int PLL_TST_LOSPDTST_SRC : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_RO_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1; - unsigned int : 1; - unsigned int PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN : 1; - unsigned int PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN : 1; - unsigned int PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN : 1; - unsigned int PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PLL_RO_GLB_CTRL_REG0__VI { - struct { - unsigned int PLL_TST_LOSPDTST_SRC : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_RO_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_GATING_EN : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_GATING_EN : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_CTRL_REG0__CI__VI { - struct { - unsigned int RX_CFG_ADAPT_MODE_GEN1 : 10; - unsigned int RX_CFG_ADAPT_MODE_GEN2 : 10; - unsigned int RX_CFG_ADAPT_MODE_GEN3 : 10; - unsigned int RX_CFG_ADAPT_RST_MODE : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_CTRL_REG1__CI__VI { - struct { - unsigned int RX_CFG_CDR_FR_GAIN_GEN1 : 4; - unsigned int RX_CFG_CDR_FR_GAIN_GEN2 : 4; - unsigned int RX_CFG_CDR_FR_GAIN_GEN3 : 4; - unsigned int RX_CFG_CDR_PH_GAIN_GEN1 : 4; - unsigned int RX_CFG_CDR_PH_GAIN_GEN2 : 4; - unsigned int RX_CFG_CDR_PH_GAIN_GEN3 : 4; - unsigned int RX_CFG_CDR_PI_STPSZ_GEN1 : 1; - unsigned int RX_CFG_CDR_PI_STPSZ_GEN2 : 1; - unsigned int RX_CFG_CDR_PI_STPSZ_GEN3 : 1; - unsigned int RX_CFG_LEQ_DCATTN_BYP_EN_GEN1 : 1; - unsigned int RX_CFG_LEQ_DCATTN_BYP_EN_GEN2 : 1; - unsigned int RX_CFG_LEQ_DCATTN_BYP_EN_GEN3 : 1; - unsigned int RX_ADAPT_HLD_ASRT_TO_DCLK_EN : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_CTRL_REG2__CI__VI { - struct { - unsigned int : 12; - unsigned int RX_CFG_CDR_TIME_GEN1 : 4; - unsigned int RX_CFG_CDR_TIME_GEN2 : 4; - unsigned int RX_CFG_CDR_TIME_GEN3 : 4; - unsigned int RX_CFG_LEQ_LOOP_GAIN_GEN1 : 2; - unsigned int RX_CFG_LEQ_LOOP_GAIN_GEN2 : 2; - unsigned int RX_CFG_LEQ_LOOP_GAIN_GEN3 : 2; - unsigned int RX_DCLK_EN_ASRT_TO_ADAPT_HLD : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_CTRL_REG3__CI__VI { - struct { - unsigned int RX_CFG_CDR_FR_EN_GEN1 : 1; - unsigned int RX_CFG_CDR_FR_EN_GEN2 : 1; - unsigned int RX_CFG_CDR_FR_EN_GEN3 : 1; - unsigned int RX_ADAPT_RST_MODE_GEN1__VI : 2; - unsigned int RX_ADAPT_RST_MODE_GEN2__VI : 2; - unsigned int RX_ADAPT_RST_MODE_GEN3__VI : 2; - unsigned int RX_ADAPT_RST_SUB_MODE__VI : 3; - unsigned int RX_L0_ENTRY_MODE_GEN1__VI : 2; - unsigned int RX_L0_ENTRY_MODE_GEN2__VI : 2; - unsigned int RX_L0_ENTRY_MODE_GEN3__VI : 2; - unsigned int : 2; - unsigned int RX_CFG_DFE_TIME_GEN1 : 4; - unsigned int RX_CFG_DFE_TIME_GEN2 : 4; - unsigned int RX_CFG_DFE_TIME_GEN3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_CTRL_REG4__CI__VI { - struct { - unsigned int RX_CFG_FOM_BER_GEN1 : 3; - unsigned int RX_CFG_FOM_BER_GEN2 : 3; - unsigned int RX_CFG_FOM_BER_GEN3 : 3; - unsigned int RX_CFG_LEQ_POLE_BYP_VAL_GEN1 : 3; - unsigned int RX_CFG_LEQ_POLE_BYP_VAL_GEN2 : 3; - unsigned int RX_CFG_LEQ_POLE_BYP_VAL_GEN3 : 3; - unsigned int : 2; - unsigned int RX_CFG_FOM_TIME_GEN1 : 4; - unsigned int RX_CFG_FOM_TIME_GEN2 : 4; - unsigned int RX_CFG_FOM_TIME_GEN3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_CTRL_REG5__CI__VI { - struct { - unsigned int RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 : 5; - unsigned int RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 : 5; - unsigned int RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 : 5; - unsigned int RX_CFG_LEQ_POLE_BYP_EN_GEN1 : 1; - unsigned int RX_CFG_LEQ_POLE_BYP_EN_GEN2 : 1; - unsigned int RX_CFG_LEQ_POLE_BYP_EN_GEN3 : 1; - unsigned int RX_CFG_LEQ_SHUNT_EN_GEN1 : 1; - unsigned int RX_CFG_LEQ_SHUNT_EN_GEN2 : 1; - unsigned int RX_CFG_LEQ_SHUNT_EN_GEN3 : 1; - unsigned int : 6; - unsigned int RX_CFG_TERM_MODE_GEN1 : 1; - unsigned int RX_CFG_TERM_MODE_GEN2 : 1; - unsigned int RX_CFG_TERM_MODE_GEN3 : 1; - unsigned int RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0 : 1; - unsigned int RX_ADAPT_AUX_PWRON_MODE__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_CTRL_REG6__CI__VI { - struct { - unsigned int RX_CFG_LEQ_TIME_GEN1 : 4; - unsigned int RX_CFG_LEQ_TIME_GEN2 : 4; - unsigned int RX_CFG_LEQ_TIME_GEN3 : 4; - unsigned int RX_CFG_OC_TIME_GEN1 : 4; - unsigned int RX_CFG_OC_TIME_GEN2 : 4; - unsigned int RX_CFG_OC_TIME_GEN3 : 4; - unsigned int RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0 : 1; - unsigned int : 1; - unsigned int RX_FRONTEND_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int RX_AUX_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__VI : 1; - unsigned int RX_ADAPT_HLD_L1_DLL_OFF__VI : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_CTRL_REG7__CI { - struct { - unsigned int RX_CFG_TH_LOOP_GAIN_GEN1 : 4; - unsigned int RX_CFG_TH_LOOP_GAIN_GEN2 : 4; - unsigned int RX_CFG_TH_LOOP_GAIN_GEN3 : 4; - unsigned int RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 : 1; - unsigned int RX_DCLK_EN_LUT_ENTRY_LS2 : 1; - unsigned int : 3; - unsigned int RX_DLL_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int RX_CFG_DLL_CPI_SEL_GEN1 : 3; - unsigned int RX_CFG_DLL_CPI_SEL_GEN2 : 3; - unsigned int RX_CFG_DLL_CPI_SEL_GEN3 : 3; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN1 : 1; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN2 : 1; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN3 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_CTRL_REG7__VI { - struct { - unsigned int RX_CFG_TH_LOOP_GAIN_GEN1 : 4; - unsigned int RX_CFG_TH_LOOP_GAIN_GEN2 : 4; - unsigned int RX_CFG_TH_LOOP_GAIN_GEN3 : 4; - unsigned int RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 : 1; - unsigned int RX_DCLK_EN_LUT_ENTRY_LS2 : 1; - unsigned int RX_DCLK_EN_AFTER_DLL_LOCK : 1; - unsigned int : 1; - unsigned int RX_DLL_PWRON_LUT_ENTRY_PS3 : 1; - unsigned int RX_DLL_PWRON_LUT_ENTRY_PS2 : 1; - unsigned int RX_CFG_DLL_CPI_SEL_GEN1 : 3; - unsigned int RX_CFG_DLL_CPI_SEL_GEN2 : 3; - unsigned int RX_CFG_DLL_CPI_SEL_GEN3 : 3; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN1 : 1; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN2 : 1; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN3 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_CTRL_REG8__CI__VI { - struct { - unsigned int RX_DLL_LOCK_TIME__VI : 2; - unsigned int RX_DLL_SPEEDCHANGE_RESET_TIME__VI : 2; - unsigned int RX_DLL_PWRON_IN_RAMPDOWN__VI : 1; - unsigned int RX_FSM_L0S_IF_RX_RDY__VI : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_OVRD_REG0__CI__VI { - struct { - unsigned int RX_ADAPT_HLD_OVRD_VAL : 1; - unsigned int RX_ADAPT_HLD_OVRD_EN : 1; - unsigned int RX_ADAPT_RST_OVRD_VAL : 1; - unsigned int RX_ADAPT_RST_OVRD_EN : 1; - unsigned int : 2; - unsigned int RX_CFG_DCLK_DIV_OVRD_VAL : 2; - unsigned int RX_CFG_DCLK_DIV_OVRD_EN : 1; - unsigned int RX_CFG_DLL_FREQ_MODE_OVRD_VAL : 1; - unsigned int RX_CFG_DLL_FREQ_MODE_OVRD_EN : 1; - unsigned int RX_CFG_PLLCLK_SEL_OVRD_VAL : 1; - unsigned int RX_CFG_PLLCLK_SEL_OVRD_EN : 1; - unsigned int RX_CFG_RCLK_DIV_OVRD_VAL : 1; - unsigned int RX_CFG_RCLK_DIV_OVRD_EN : 1; - unsigned int RX_DCLK_EN_OVRD_VAL : 1; - unsigned int RX_DCLK_EN_OVRD_EN : 1; - unsigned int RX_DLL_PWRON_OVRD_VAL : 1; - unsigned int RX_DLL_PWRON_OVRD_EN : 1; - unsigned int RX_FRONTEND_PWRON_OVRD_VAL : 1; - unsigned int RX_FRONTEND_PWRON_OVRD_EN : 1; - unsigned int RX_IDLEDET_PWRON_OVRD_VAL : 1; - unsigned int RX_IDLEDET_PWRON_OVRD_EN : 1; - unsigned int RX_TERM_EN_OVRD_VAL : 1; - unsigned int RX_TERM_EN_OVRD_EN : 1; - unsigned int : 3; - unsigned int RX_AUX_PWRON_OVRD_VAL : 1; - unsigned int RX_AUX_PWRON_OVRD_EN : 1; - unsigned int RX_ADAPT_FOM_OVRD_VAL : 1; - unsigned int RX_ADAPT_FOM_OVRD_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_OVRD_REG1__CI__VI { - struct { - unsigned int RX_ADAPT_TRK_OVRD_VAL : 1; - unsigned int RX_ADAPT_TRK_OVRD_EN : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int IGNR_RXPWR_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_RXPWR_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_RXPWR_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_RXPWR_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_ENABLEFOM_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_ENABLEFOM_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_ENABLEFOM_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_ENABLEFOM_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_REQUESTFOM_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_REQUESTFOM_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_REQUESTFOM_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_REQUESTFOM_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L12T15 : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_GLB_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int IGNR_RXPWR_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_RXPWR_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_RXPWR_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_RXPWR_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_REQUESTTRK_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_REQUESTTRK_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_REQUESTTRK_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_REQUESTTRK_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_ENABLEFOM_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_ENABLEFOM_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_ENABLEFOM_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_ENABLEFOM_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_REQUESTFOM_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_REQUESTFOM_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_REQUESTFOM_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_REQUESTFOM_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L12T15 : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE0_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_0 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_0 : 2; - unsigned int RX_TST_BSCAN_EN_0 : 1; - unsigned int RX_CFG_OVR_PWRSF_0 : 1; - unsigned int RX_TERM_EN_0__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE0_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_0 : 3; - unsigned int ELECIDLEDETEN_0 : 1; - unsigned int RXPRESETHINT_0 : 3; - unsigned int ENABLEFOM_0 : 1; - unsigned int REQUESTFOM_0 : 1; - unsigned int RESPONSEMODE_0 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE0_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_0 : 3; - unsigned int ELECIDLEDETEN_0 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_0 : 1; - unsigned int ENABLEFOM_0 : 1; - unsigned int REQUESTFOM_0 : 1; - unsigned int RESPONSEMODE_0 : 1; - unsigned int RXEYEFOM_0 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE10_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_10 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_10 : 2; - unsigned int RX_TST_BSCAN_EN_10 : 1; - unsigned int RX_CFG_OVR_PWRSF_10 : 1; - unsigned int RX_TERM_EN_10__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE10_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_10 : 3; - unsigned int ELECIDLEDETEN_10 : 1; - unsigned int RXPRESETHINT_10 : 3; - unsigned int ENABLEFOM_10 : 1; - unsigned int REQUESTFOM_10 : 1; - unsigned int RESPONSEMODE_10 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE10_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_10 : 3; - unsigned int ELECIDLEDETEN_10 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_10 : 1; - unsigned int ENABLEFOM_10 : 1; - unsigned int REQUESTFOM_10 : 1; - unsigned int RESPONSEMODE_10 : 1; - unsigned int RXEYEFOM_10 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE11_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_11 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_11 : 2; - unsigned int RX_TST_BSCAN_EN_11 : 1; - unsigned int RX_CFG_OVR_PWRSF_11 : 1; - unsigned int RX_TERM_EN_11__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE11_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_11 : 3; - unsigned int ELECIDLEDETEN_11 : 1; - unsigned int RXPRESETHINT_11 : 3; - unsigned int ENABLEFOM_11 : 1; - unsigned int REQUESTFOM_11 : 1; - unsigned int RESPONSEMODE_11 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE11_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_11 : 3; - unsigned int ELECIDLEDETEN_11 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_11 : 1; - unsigned int ENABLEFOM_11 : 1; - unsigned int REQUESTFOM_11 : 1; - unsigned int RESPONSEMODE_11 : 1; - unsigned int RXEYEFOM_11 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE12_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_12 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_12 : 2; - unsigned int RX_TST_BSCAN_EN_12 : 1; - unsigned int RX_CFG_OVR_PWRSF_12 : 1; - unsigned int RX_TERM_EN_12__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE12_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_12 : 3; - unsigned int ELECIDLEDETEN_12 : 1; - unsigned int RXPRESETHINT_12 : 3; - unsigned int ENABLEFOM_12 : 1; - unsigned int REQUESTFOM_12 : 1; - unsigned int RESPONSEMODE_12 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE12_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_12 : 3; - unsigned int ELECIDLEDETEN_12 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_12 : 1; - unsigned int ENABLEFOM_12 : 1; - unsigned int REQUESTFOM_12 : 1; - unsigned int RESPONSEMODE_12 : 1; - unsigned int RXEYEFOM_12 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE13_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_13 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_13 : 2; - unsigned int RX_TST_BSCAN_EN_13 : 1; - unsigned int RX_CFG_OVR_PWRSF_13 : 1; - unsigned int RX_TERM_EN_13__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE13_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_13 : 3; - unsigned int ELECIDLEDETEN_13 : 1; - unsigned int RXPRESETHINT_13 : 3; - unsigned int ENABLEFOM_13 : 1; - unsigned int REQUESTFOM_13 : 1; - unsigned int RESPONSEMODE_13 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE13_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_13 : 3; - unsigned int ELECIDLEDETEN_13 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_13 : 1; - unsigned int ENABLEFOM_13 : 1; - unsigned int REQUESTFOM_13 : 1; - unsigned int RESPONSEMODE_13 : 1; - unsigned int RXEYEFOM_13 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE14_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_14 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_14 : 2; - unsigned int RX_TST_BSCAN_EN_14 : 1; - unsigned int RX_CFG_OVR_PWRSF_14 : 1; - unsigned int RX_TERM_EN_14__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE14_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_14 : 3; - unsigned int ELECIDLEDETEN_14 : 1; - unsigned int RXPRESETHINT_14 : 3; - unsigned int ENABLEFOM_14 : 1; - unsigned int REQUESTFOM_14 : 1; - unsigned int RESPONSEMODE_14 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE14_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_14 : 3; - unsigned int ELECIDLEDETEN_14 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_14 : 1; - unsigned int ENABLEFOM_14 : 1; - unsigned int REQUESTFOM_14 : 1; - unsigned int RESPONSEMODE_14 : 1; - unsigned int RXEYEFOM_14 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE15_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_15 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_15 : 2; - unsigned int RX_TST_BSCAN_EN_15 : 1; - unsigned int RX_CFG_OVR_PWRSF_15 : 1; - unsigned int RX_TERM_EN_15__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE15_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_15 : 3; - unsigned int ELECIDLEDETEN_15 : 1; - unsigned int RXPRESETHINT_15 : 3; - unsigned int ENABLEFOM_15 : 1; - unsigned int REQUESTFOM_15 : 1; - unsigned int RESPONSEMODE_15 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE15_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_15 : 3; - unsigned int ELECIDLEDETEN_15 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_15 : 1; - unsigned int ENABLEFOM_15 : 1; - unsigned int REQUESTFOM_15 : 1; - unsigned int RESPONSEMODE_15 : 1; - unsigned int RXEYEFOM_15 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE1_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_1 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_1 : 2; - unsigned int RX_TST_BSCAN_EN_1 : 1; - unsigned int RX_CFG_OVR_PWRSF_1 : 1; - unsigned int RX_TERM_EN_1__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE1_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_1 : 3; - unsigned int ELECIDLEDETEN_1 : 1; - unsigned int RXPRESETHINT_1 : 3; - unsigned int ENABLEFOM_1 : 1; - unsigned int REQUESTFOM_1 : 1; - unsigned int RESPONSEMODE_1 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE1_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_1 : 3; - unsigned int ELECIDLEDETEN_1 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_1 : 1; - unsigned int ENABLEFOM_1 : 1; - unsigned int REQUESTFOM_1 : 1; - unsigned int RESPONSEMODE_1 : 1; - unsigned int RXEYEFOM_1 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE2_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_2 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_2 : 2; - unsigned int RX_TST_BSCAN_EN_2 : 1; - unsigned int RX_CFG_OVR_PWRSF_2 : 1; - unsigned int RX_TERM_EN_2__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE2_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_2 : 3; - unsigned int ELECIDLEDETEN_2 : 1; - unsigned int RXPRESETHINT_2 : 3; - unsigned int ENABLEFOM_2 : 1; - unsigned int REQUESTFOM_2 : 1; - unsigned int RESPONSEMODE_2 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE2_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_2 : 3; - unsigned int ELECIDLEDETEN_2 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_2 : 1; - unsigned int ENABLEFOM_2 : 1; - unsigned int REQUESTFOM_2 : 1; - unsigned int RESPONSEMODE_2 : 1; - unsigned int RXEYEFOM_2 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE3_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_3 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_3 : 2; - unsigned int RX_TST_BSCAN_EN_3 : 1; - unsigned int RX_CFG_OVR_PWRSF_3 : 1; - unsigned int RX_TERM_EN_3__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE3_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_3 : 3; - unsigned int ELECIDLEDETEN_3 : 1; - unsigned int RXPRESETHINT_3 : 3; - unsigned int ENABLEFOM_3 : 1; - unsigned int REQUESTFOM_3 : 1; - unsigned int RESPONSEMODE_3 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE3_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_3 : 3; - unsigned int ELECIDLEDETEN_3 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_3 : 1; - unsigned int ENABLEFOM_3 : 1; - unsigned int REQUESTFOM_3 : 1; - unsigned int RESPONSEMODE_3 : 1; - unsigned int RXEYEFOM_3 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE4_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_4 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_4 : 2; - unsigned int RX_TST_BSCAN_EN_4 : 1; - unsigned int RX_CFG_OVR_PWRSF_4 : 1; - unsigned int RX_TERM_EN_4__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE4_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_4 : 3; - unsigned int ELECIDLEDETEN_4 : 1; - unsigned int RXPRESETHINT_4 : 3; - unsigned int ENABLEFOM_4 : 1; - unsigned int REQUESTFOM_4 : 1; - unsigned int RESPONSEMODE_4 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE4_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_4 : 3; - unsigned int ELECIDLEDETEN_4 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_4 : 1; - unsigned int ENABLEFOM_4 : 1; - unsigned int REQUESTFOM_4 : 1; - unsigned int RESPONSEMODE_4 : 1; - unsigned int RXEYEFOM_4 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE5_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_5 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_5 : 2; - unsigned int RX_TST_BSCAN_EN_5 : 1; - unsigned int RX_CFG_OVR_PWRSF_5 : 1; - unsigned int RX_TERM_EN_5__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE5_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_5 : 3; - unsigned int ELECIDLEDETEN_5 : 1; - unsigned int RXPRESETHINT_5 : 3; - unsigned int ENABLEFOM_5 : 1; - unsigned int REQUESTFOM_5 : 1; - unsigned int RESPONSEMODE_5 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE5_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_5 : 3; - unsigned int ELECIDLEDETEN_5 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_5 : 1; - unsigned int ENABLEFOM_5 : 1; - unsigned int REQUESTFOM_5 : 1; - unsigned int RESPONSEMODE_5 : 1; - unsigned int RXEYEFOM_5 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE6_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_6 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_6 : 2; - unsigned int RX_TST_BSCAN_EN_6 : 1; - unsigned int RX_CFG_OVR_PWRSF_6 : 1; - unsigned int RX_TERM_EN_6__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE6_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_6 : 3; - unsigned int ELECIDLEDETEN_6 : 1; - unsigned int RXPRESETHINT_6 : 3; - unsigned int ENABLEFOM_6 : 1; - unsigned int REQUESTFOM_6 : 1; - unsigned int RESPONSEMODE_6 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE6_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_6 : 3; - unsigned int ELECIDLEDETEN_6 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_6 : 1; - unsigned int ENABLEFOM_6 : 1; - unsigned int REQUESTFOM_6 : 1; - unsigned int RESPONSEMODE_6 : 1; - unsigned int RXEYEFOM_6 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE7_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_7 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_7 : 2; - unsigned int RX_TST_BSCAN_EN_7 : 1; - unsigned int RX_CFG_OVR_PWRSF_7 : 1; - unsigned int RX_TERM_EN_7__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE7_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_7 : 3; - unsigned int ELECIDLEDETEN_7 : 1; - unsigned int RXPRESETHINT_7 : 3; - unsigned int ENABLEFOM_7 : 1; - unsigned int REQUESTFOM_7 : 1; - unsigned int RESPONSEMODE_7 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE7_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_7 : 3; - unsigned int ELECIDLEDETEN_7 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_7 : 1; - unsigned int ENABLEFOM_7 : 1; - unsigned int REQUESTFOM_7 : 1; - unsigned int RESPONSEMODE_7 : 1; - unsigned int RXEYEFOM_7 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE8_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_8 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_8 : 2; - unsigned int RX_TST_BSCAN_EN_8 : 1; - unsigned int RX_CFG_OVR_PWRSF_8 : 1; - unsigned int RX_TERM_EN_8__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE8_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_8 : 3; - unsigned int ELECIDLEDETEN_8 : 1; - unsigned int RXPRESETHINT_8 : 3; - unsigned int ENABLEFOM_8 : 1; - unsigned int REQUESTFOM_8 : 1; - unsigned int RESPONSEMODE_8 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE8_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_8 : 3; - unsigned int ELECIDLEDETEN_8 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_8 : 1; - unsigned int ENABLEFOM_8 : 1; - unsigned int REQUESTFOM_8 : 1; - unsigned int RESPONSEMODE_8 : 1; - unsigned int RXEYEFOM_8 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE9_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_9 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_9 : 2; - unsigned int RX_TST_BSCAN_EN_9 : 1; - unsigned int RX_CFG_OVR_PWRSF_9 : 1; - unsigned int RX_TERM_EN_9__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE9_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_9 : 3; - unsigned int ELECIDLEDETEN_9 : 1; - unsigned int RXPRESETHINT_9 : 3; - unsigned int ENABLEFOM_9 : 1; - unsigned int REQUESTFOM_9 : 1; - unsigned int RESPONSEMODE_9 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_RX_LANE9_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_9 : 3; - unsigned int ELECIDLEDETEN_9 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_9 : 1; - unsigned int ENABLEFOM_9 : 1; - unsigned int REQUESTFOM_9 : 1; - unsigned int RESPONSEMODE_9 : 1; - unsigned int RXEYEFOM_9 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_STRAP_GLB_REG0__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_QUICK_SIM_START : 1; - unsigned int STRAP_DFT_RXBSCAN_EN_VAL : 1; - unsigned int STRAP_DFT_CALIB_BYPASS : 1; - unsigned int STRAP_FORCE_LC_PLL_ON__VI : 1; - unsigned int STRAP_CFG_IDLEDET_TH : 2; - unsigned int STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL : 5; - unsigned int STRAP_RX_CFG_OVR_PWRSF : 1; - unsigned int STRAP_RX_TRK_MODE_0_ : 1; - unsigned int STRAP_PWRGOOD_OVRD : 1; - unsigned int STRAP_DBG_RXDLL_VREG_REF_SEL : 1; - unsigned int STRAP_PLL_CFG_LC_VCO_TUNE : 4; - unsigned int STRAP_DBG_RXRDATA_GATING_DISABLE : 1; - unsigned int STRAP_DBG_RXPI_OFFSET_BYP_VAL : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_STRAP_PIN_REG0__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_TX_DEEMPH_EN : 1; - unsigned int STRAP_TX_FULL_SWING : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_STRAP_PLL_REG0__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_PLL_CFG_LC_BW_CNTRL : 3; - unsigned int STRAP_PLL_CFG_LC_LF_CNTRL : 9; - unsigned int STRAP_TX_RXDET_X1_SSF : 1; - unsigned int : 1; - unsigned int STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS : 1; - unsigned int STRAP_PLL_CFG_RO_BW_CNTRL : 8; - unsigned int STRAP_PLL_STRAP_SEL : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_STRAP_RX_REG0__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_RX_CFG_TH_LOOP_GAIN : 4; - unsigned int STRAP_RX_CFG_DLL_FLOCK_DISABLE : 1; - unsigned int STRAP_DBG_RXPI_OFFSET_BYP_EN : 1; - unsigned int STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS : 1; - unsigned int STRAP_BG_CFG_LC_REG_VREF0_SEL : 2; - unsigned int STRAP_BG_CFG_LC_REG_VREF1_SEL : 2; - unsigned int STRAP_RX_CFG_CDR_TIME : 4; - unsigned int STRAP_RX_CFG_FOM_TIME : 4; - unsigned int STRAP_RX_CFG_LEQ_TIME : 4; - unsigned int STRAP_RX_CFG_OC_TIME : 4; - unsigned int STRAP_TX_CFG_RPTR_RST_VAL : 3; - unsigned int STRAP_RX_CFG_TERM_MODE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_STRAP_RX_REG1__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_RX_CFG_CDR_PI_STPSZ : 1; - unsigned int STRAP_TX_DEEMPH_PRSHT_STNG : 3; - unsigned int STRAP_BG_CFG_RO_REG_VREF_SEL : 2; - unsigned int STRAP_RX_CFG_LEQ_POLE_BYP_DIS : 1; - unsigned int STRAP_RX_CFG_LEQ_POLE_BYP_VAL : 3; - unsigned int STRAP_RX_CFG_CDR_PH_GAIN : 4; - unsigned int STRAP_RX_CFG_ADAPT_MODE : 10; - unsigned int STRAP_RX_CFG_DFE_TIME : 4; - unsigned int STRAP_RX_CFG_LEQ_LOOP_GAIN : 2; - unsigned int STRAP_RX_CFG_LEQ_SHUNT_DIS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_STRAP_TX_REG0__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_TX_CFG_DRV0_EN : 4; - unsigned int STRAP_TX_CFG_DRV0_TAP_SEL : 4; - unsigned int STRAP_TX_CFG_DRV1_EN : 5; - unsigned int STRAP_TX_CFG_DRV1_TAP_SEL : 5; - unsigned int STRAP_TX_CFG_DRV2_EN : 4; - unsigned int STRAP_TX_CFG_DRV2_TAP_SEL : 4; - unsigned int STRAP_TX_CFG_DRVX_EN : 1; - unsigned int STRAP_TX_CFG_DRVX_TAP_SEL : 1; - unsigned int STRAP_RX_TRK_MODE_1_ : 1; - unsigned int STRAP_TX_CFG_SWING_BOOST_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI { - struct { - unsigned int ACCEPT_ENTRY_0 : 1; - unsigned int ACCEPT_ENTRY_1 : 1; - unsigned int ACCEPT_ENTRY_2 : 1; - unsigned int ACCEPT_ENTRY_3 : 1; - unsigned int ACCEPT_ENTRY_4 : 1; - unsigned int ACCEPT_ENTRY_5 : 1; - unsigned int ACCEPT_ENTRY_6 : 1; - unsigned int ACCEPT_ENTRY_7 : 1; - unsigned int ACCEPT_ENTRY_8 : 1; - unsigned int ACCEPT_ENTRY_9 : 1; - unsigned int ACCEPT_ENTRY_10 : 1; - unsigned int ACCEPT_ENTRY_11 : 1; - unsigned int ACCEPT_ENTRY_12 : 1; - unsigned int ACCEPT_ENTRY_13 : 1; - unsigned int ACCEPT_ENTRY_14 : 1; - unsigned int ACCEPT_ENTRY_15 : 1; - unsigned int ACCEPT_ENTRY_16 : 1; - unsigned int ACCEPT_ENTRY_17 : 1; - unsigned int ACCEPT_ENTRY_18 : 1; - unsigned int ACCEPT_ENTRY_19 : 1; - unsigned int ACCEPT_ENTRY_20 : 1; - unsigned int ACCEPT_ENTRY_21 : 1; - unsigned int ACCEPT_ENTRY_22 : 1; - unsigned int ACCEPT_ENTRY_23 : 1; - unsigned int ACCEPT_ENTRY_24 : 1; - unsigned int ACCEPT_ENTRY_25 : 1; - unsigned int ACCEPT_ENTRY_26 : 1; - unsigned int ACCEPT_ENTRY_27 : 1; - unsigned int ACCEPT_ENTRY_28 : 1; - unsigned int ACCEPT_ENTRY_29 : 1; - unsigned int ACCEPT_ENTRY_30 : 1; - unsigned int ACCEPT_ENTRY_31 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI { - struct { - unsigned int ACCEPT_ENTRY_32 : 1; - unsigned int ACCEPT_ENTRY_33 : 1; - unsigned int ACCEPT_ENTRY_34 : 1; - unsigned int ACCEPT_ENTRY_35 : 1; - unsigned int ACCEPT_ENTRY_36 : 1; - unsigned int ACCEPT_ENTRY_37 : 1; - unsigned int ACCEPT_ENTRY_38 : 1; - unsigned int ACCEPT_ENTRY_39 : 1; - unsigned int ACCEPT_ENTRY_40 : 1; - unsigned int ACCEPT_ENTRY_41 : 1; - unsigned int ACCEPT_ENTRY_42 : 1; - unsigned int ACCEPT_ENTRY_43 : 1; - unsigned int ACCEPT_ENTRY_44 : 1; - unsigned int ACCEPT_ENTRY_45 : 1; - unsigned int ACCEPT_ENTRY_46 : 1; - unsigned int ACCEPT_ENTRY_47 : 1; - unsigned int ACCEPT_ENTRY_48 : 1; - unsigned int ACCEPT_ENTRY_49 : 1; - unsigned int ACCEPT_ENTRY_50 : 1; - unsigned int ACCEPT_ENTRY_51 : 1; - unsigned int ACCEPT_ENTRY_52 : 1; - unsigned int ACCEPT_ENTRY_53 : 1; - unsigned int ACCEPT_ENTRY_54 : 1; - unsigned int ACCEPT_ENTRY_55 : 1; - unsigned int ACCEPT_ENTRY_56 : 1; - unsigned int ACCEPT_ENTRY_57 : 1; - unsigned int ACCEPT_ENTRY_58 : 1; - unsigned int ACCEPT_ENTRY_59 : 1; - unsigned int ACCEPT_ENTRY_60 : 1; - unsigned int ACCEPT_ENTRY_61 : 1; - unsigned int ACCEPT_ENTRY_62 : 1; - unsigned int ACCEPT_ENTRY_63 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI { - struct { - unsigned int ACCEPT_ENTRY_64 : 1; - unsigned int ACCEPT_ENTRY_65 : 1; - unsigned int ACCEPT_ENTRY_66 : 1; - unsigned int ACCEPT_ENTRY_67 : 1; - unsigned int ACCEPT_ENTRY_68 : 1; - unsigned int ACCEPT_ENTRY_69 : 1; - unsigned int ACCEPT_ENTRY_70 : 1; - unsigned int ACCEPT_ENTRY_71 : 1; - unsigned int ACCEPT_ENTRY_72 : 1; - unsigned int ACCEPT_ENTRY_73 : 1; - unsigned int ACCEPT_ENTRY_74 : 1; - unsigned int ACCEPT_ENTRY_75 : 1; - unsigned int ACCEPT_ENTRY_76 : 1; - unsigned int ACCEPT_ENTRY_77 : 1; - unsigned int ACCEPT_ENTRY_78 : 1; - unsigned int ACCEPT_ENTRY_79 : 1; - unsigned int ACCEPT_ENTRY_80 : 1; - unsigned int ACCEPT_ENTRY_81 : 1; - unsigned int ACCEPT_ENTRY_82 : 1; - unsigned int ACCEPT_ENTRY_83 : 1; - unsigned int ACCEPT_ENTRY_84 : 1; - unsigned int ACCEPT_ENTRY_85 : 1; - unsigned int ACCEPT_ENTRY_86 : 1; - unsigned int ACCEPT_ENTRY_87 : 1; - unsigned int ACCEPT_ENTRY_88 : 1; - unsigned int ACCEPT_ENTRY_89 : 1; - unsigned int ACCEPT_ENTRY_90 : 1; - unsigned int ACCEPT_ENTRY_91 : 1; - unsigned int ACCEPT_ENTRY_92 : 1; - unsigned int ACCEPT_ENTRY_93 : 1; - unsigned int ACCEPT_ENTRY_94 : 1; - unsigned int ACCEPT_ENTRY_95 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI { - struct { - unsigned int ACCEPT_ENTRY_96 : 1; - unsigned int ACCEPT_ENTRY_97 : 1; - unsigned int ACCEPT_ENTRY_98 : 1; - unsigned int ACCEPT_ENTRY_99 : 1; - unsigned int ACCEPT_ENTRY_100 : 1; - unsigned int ACCEPT_ENTRY_101 : 1; - unsigned int ACCEPT_ENTRY_102 : 1; - unsigned int ACCEPT_ENTRY_103 : 1; - unsigned int ACCEPT_ENTRY_104 : 1; - unsigned int ACCEPT_ENTRY_105 : 1; - unsigned int ACCEPT_ENTRY_106 : 1; - unsigned int ACCEPT_ENTRY_107 : 1; - unsigned int ACCEPT_ENTRY_108 : 1; - unsigned int ACCEPT_ENTRY_109 : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_CTRL_REG0__CI { - struct { - unsigned int TX_DRV_DATA_ASRT_DLY_VAL : 3; - unsigned int TX_DRV_DATA_DSRT_DLY_VAL : 3; - unsigned int : 2; - unsigned int TX_CFG_RPTR_RST_VAL_GEN1 : 3; - unsigned int TX_CFG_RPTR_RST_VAL_GEN2 : 3; - unsigned int TX_CFG_RPTR_RST_VAL_GEN3 : 3; - unsigned int TX_STAGGER_CTRL : 2; - unsigned int TX_DATA_CLK_GATING : 1; - unsigned int TX_PRESET_TABLE_BYPASS : 1; - unsigned int TX_COEFF_ROUND_EN : 1; - unsigned int TX_COEFF_ROUND_DIR_VER : 1; - unsigned int TX_DCLK_EN_LSX_ALWAYS_ON : 1; - unsigned int TX_FRONTEND_PWRON_IN_OFF : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_CTRL_REG0__VI { - struct { - unsigned int TX_DRV_DATA_ASRT_DLY_VAL : 3; - unsigned int TX_DRV_DATA_DSRT_DLY_VAL : 3; - unsigned int : 2; - unsigned int TX_CFG_RPTR_RST_VAL_GEN1 : 3; - unsigned int TX_CFG_RPTR_RST_VAL_GEN2 : 3; - unsigned int TX_CFG_RPTR_RST_VAL_GEN3 : 3; - unsigned int TX_STAGGER_CTRL : 2; - unsigned int TX_DATA_CLK_GATING : 1; - unsigned int TX_PRESET_TABLE_BYPASS : 1; - unsigned int TX_COEFF_ROUND_EN : 1; - unsigned int TX_COEFF_ROUND_DIR_VER : 1; - unsigned int TX_DCLK_EN_LSX_ALWAYS_ON : 1; - unsigned int TX_FRONTEND_PWRON_IN_PS4 : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_LANE_SKEW_CTRL__CI__VI { - struct { - unsigned int TX_CFG_GROUPX1_EN_0 : 1; - unsigned int TX_CFG_GROUPX1_EN_1 : 1; - unsigned int TX_CFG_GROUPX1_EN_2 : 1; - unsigned int TX_CFG_GROUPX1_EN_3 : 1; - unsigned int TX_CFG_GROUPX1_EN_4 : 1; - unsigned int TX_CFG_GROUPX1_EN_5 : 1; - unsigned int TX_CFG_GROUPX1_EN_6 : 1; - unsigned int TX_CFG_GROUPX1_EN_7 : 1; - unsigned int TX_CFG_GROUPX1_EN_8 : 1; - unsigned int TX_CFG_GROUPX1_EN_9 : 1; - unsigned int TX_CFG_GROUPX1_EN_10 : 1; - unsigned int TX_CFG_GROUPX1_EN_11 : 1; - unsigned int TX_CFG_GROUPX1_EN_12 : 1; - unsigned int TX_CFG_GROUPX1_EN_13 : 1; - unsigned int TX_CFG_GROUPX1_EN_14 : 1; - unsigned int TX_CFG_GROUPX1_EN_15 : 1; - unsigned int TX_CFG_GROUPX2_EN_L0T1 : 1; - unsigned int TX_CFG_GROUPX2_EN_L2T3 : 1; - unsigned int TX_CFG_GROUPX2_EN_L4T5 : 1; - unsigned int TX_CFG_GROUPX2_EN_L6T7 : 1; - unsigned int TX_CFG_GROUPX2_EN_L8T9 : 1; - unsigned int TX_CFG_GROUPX2_EN_L10T11 : 1; - unsigned int TX_CFG_GROUPX2_EN_L12T13 : 1; - unsigned int TX_CFG_GROUPX2_EN_L14T15 : 1; - unsigned int TX_CFG_GROUPX4_EN_L0T3 : 1; - unsigned int TX_CFG_GROUPX4_EN_L4T7 : 1; - unsigned int TX_CFG_GROUPX4_EN_L8T11 : 1; - unsigned int TX_CFG_GROUPX4_EN_L12T15 : 1; - unsigned int TX_CFG_GROUPX8_EN_L0T7 : 1; - unsigned int TX_CFG_GROUPX8_EN_L8T15 : 1; - unsigned int TX_CFG_GROUPX16_EN_L0T15 : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_OVRD_REG0__CI__VI { - struct { - unsigned int TX_CFG_DCLK_DIV_OVRD_VAL : 3; - unsigned int TX_CFG_DCLK_DIV_OVRD_EN : 1; - unsigned int TX_CFG_DRV0_EN_GEN1_OVRD_VAL : 4; - unsigned int TX_CFG_DRV0_EN_OVRD_EN : 1; - unsigned int TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL : 4; - unsigned int TX_CFG_DRV0_TAP_SEL_OVRD_EN : 1; - unsigned int TX_CFG_DRV1_EN_GEN1_OVRD_VAL : 5; - unsigned int TX_CFG_DRV1_EN_OVRD_EN : 1; - unsigned int TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL : 5; - unsigned int TX_CFG_DRV1_TAP_SEL_OVRD_EN : 1; - unsigned int TX_CFG_DRV2_EN_GEN1_OVRD_VAL : 4; - unsigned int TX_CFG_DRV2_EN_OVRD_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_OVRD_REG1__CI__VI { - struct { - unsigned int TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL : 4; - unsigned int TX_CFG_DRV2_TAP_SEL_OVRD_EN : 1; - unsigned int TX_CFG_DRVX_EN_GEN1_OVRD_VAL : 1; - unsigned int TX_CFG_DRVX_EN_OVRD_EN : 1; - unsigned int TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL : 1; - unsigned int TX_CFG_DRVX_TAP_SEL_OVRD_EN : 1; - unsigned int TX_CFG_PLLCLK_SEL_OVRD_VAL : 1; - unsigned int TX_CFG_PLLCLK_SEL_OVRD_EN : 1; - unsigned int TX_CFG_TCLK_DIV_OVRD_VAL : 1; - unsigned int TX_CFG_TCLK_DIV_OVRD_EN : 1; - unsigned int TX_CMDET_EN_OVRD_VAL : 1; - unsigned int TX_CMDET_EN_OVRD_EN : 1; - unsigned int TX_DATA_IN_OVRD_VAL : 10; - unsigned int TX_DATA_IN_OVRD_EN : 1; - unsigned int TX_RPTR_RSTN_OVRD_VAL : 1; - unsigned int TX_RPTR_RSTN_OVRD_EN : 1; - unsigned int TX_RXDET_EN_OVRD_VAL : 1; - unsigned int TX_RXDET_EN_OVRD_EN : 1; - unsigned int TX_WPTR_RSTN_OVRD_VAL : 1; - unsigned int TX_WPTR_RSTN_OVRD_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_OVRD_REG2__CI__VI { - struct { - unsigned int TX_WRITE_EN_OVRD_VAL : 1; - unsigned int TX_WRITE_EN_OVRD_EN : 1; - unsigned int TX_CFG_GROUPX1_EN_OVRD_VAL : 1; - unsigned int TX_CFG_GROUPX1_EN_OVRD_EN : 1; - unsigned int TX_CFG_GROUPX2_EN_OVRD_VAL : 1; - unsigned int TX_CFG_GROUPX2_EN_OVRD_EN : 1; - unsigned int TX_CFG_GROUPX4_EN_OVRD_VAL : 1; - unsigned int TX_CFG_GROUPX4_EN_OVRD_EN : 1; - unsigned int TX_CFG_GROUPX8_EN_OVRD_VAL : 1; - unsigned int TX_CFG_GROUPX8_EN_OVRD_EN : 1; - unsigned int TX_CFG_GROUPX16_EN_OVRD_VAL : 1; - unsigned int TX_CFG_GROUPX16_EN_OVRD_EN : 1; - unsigned int TX_CFG_DRV0_EN_GEN2_OVRD_VAL : 4; - unsigned int TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL : 4; - unsigned int TX_CFG_DRV1_EN_GEN2_OVRD_VAL : 5; - unsigned int TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL : 5; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_OVRD_REG3__CI__VI { - struct { - unsigned int TX_CFG_DRV2_EN_GEN2_OVRD_VAL : 4; - unsigned int TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL : 4; - unsigned int TX_CFG_DRVX_EN_GEN2_OVRD_VAL : 1; - unsigned int TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL : 1; - unsigned int TX_CFG_DRV0_EN_GEN3_OVRD_VAL : 4; - unsigned int TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL : 4; - unsigned int TX_CFG_DRV1_EN_GEN3_OVRD_VAL : 5; - unsigned int TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL : 5; - unsigned int TX_CFG_DRV2_EN_GEN3_OVRD_VAL : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_OVRD_REG4__CI__VI { - struct { - unsigned int TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL : 4; - unsigned int TX_CFG_DRVX_EN_GEN3_OVRD_VAL : 1; - unsigned int TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int IGNR_TXPWR_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_TXPWR_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_TXPWR_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_TXPWR_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_COEFFICIENT_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_COEFFICIENT_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_COEFFICIENT_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_COEFFICIENT_SCI_UPDT_L12T15 : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_GLB_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int IGNR_TXPWR_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_TXPWR_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_TXPWR_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_TXPWR_CBI_UPDT_L12T15 : 1; - unsigned int : 4; - unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_COEFFICIENT_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_COEFFICIENT_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_COEFFICIENT_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_COEFFICIENT_CBI_UPDT_L12T15 : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE0_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_0 : 1; - unsigned int TX_CFG_INV_DATA_0 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_0 : 1; - unsigned int TX_DBG_PRBS_EN_0 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE0_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_0 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_0 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_0 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_0 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_0 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_0 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_0 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_0 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_0 : 3; - unsigned int INCOHERENTCK_0__SI__CI : 1; - unsigned int TXMARG_0 : 3; - unsigned int DEEMPH_0 : 1; - unsigned int COEFFICIENTID_0 : 2; - unsigned int COEFFICIENT_0 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE10_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_10 : 1; - unsigned int TX_CFG_INV_DATA_10 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_10 : 1; - unsigned int TX_DBG_PRBS_EN_10 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE10_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_10 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_10 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_10 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_10 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_10 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_10 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_10 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_10 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_10 : 3; - unsigned int INCOHERENTCK_10__SI__CI : 1; - unsigned int TXMARG_10 : 3; - unsigned int DEEMPH_10 : 1; - unsigned int COEFFICIENTID_10 : 2; - unsigned int COEFFICIENT_10 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE11_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_11 : 1; - unsigned int TX_CFG_INV_DATA_11 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_11 : 1; - unsigned int TX_DBG_PRBS_EN_11 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE11_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_11 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_11 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_11 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_11 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_11 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_11 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_11 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_11 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_11 : 3; - unsigned int INCOHERENTCK_11__SI__CI : 1; - unsigned int TXMARG_11 : 3; - unsigned int DEEMPH_11 : 1; - unsigned int COEFFICIENTID_11 : 2; - unsigned int COEFFICIENT_11 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE12_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_12 : 1; - unsigned int TX_CFG_INV_DATA_12 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_12 : 1; - unsigned int TX_DBG_PRBS_EN_12 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE12_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_12 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_12 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_12 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_12 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_12 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_12 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_12 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_12 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_12 : 3; - unsigned int INCOHERENTCK_12__SI__CI : 1; - unsigned int TXMARG_12 : 3; - unsigned int DEEMPH_12 : 1; - unsigned int COEFFICIENTID_12 : 2; - unsigned int COEFFICIENT_12 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE13_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_13 : 1; - unsigned int TX_CFG_INV_DATA_13 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_13 : 1; - unsigned int TX_DBG_PRBS_EN_13 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE13_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_13 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_13 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_13 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_13 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_13 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_13 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_13 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_13 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_13 : 3; - unsigned int INCOHERENTCK_13__SI__CI : 1; - unsigned int TXMARG_13 : 3; - unsigned int DEEMPH_13 : 1; - unsigned int COEFFICIENTID_13 : 2; - unsigned int COEFFICIENT_13 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE14_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_14 : 1; - unsigned int TX_CFG_INV_DATA_14 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_14 : 1; - unsigned int TX_DBG_PRBS_EN_14 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE14_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_14 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_14 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_14 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_14 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_14 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_14 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_14 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_14 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_14 : 3; - unsigned int INCOHERENTCK_14__SI__CI : 1; - unsigned int TXMARG_14 : 3; - unsigned int DEEMPH_14 : 1; - unsigned int COEFFICIENTID_14 : 2; - unsigned int COEFFICIENT_14 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE15_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_15 : 1; - unsigned int TX_CFG_INV_DATA_15 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_15 : 1; - unsigned int TX_DBG_PRBS_EN_15 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE15_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_15 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_15 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_15 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_15 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_15 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_15 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_15 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_15 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_15 : 3; - unsigned int INCOHERENTCK_15__SI__CI : 1; - unsigned int TXMARG_15 : 3; - unsigned int DEEMPH_15 : 1; - unsigned int COEFFICIENTID_15 : 2; - unsigned int COEFFICIENT_15 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE1_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_1 : 1; - unsigned int TX_CFG_INV_DATA_1 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_1 : 1; - unsigned int TX_DBG_PRBS_EN_1 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE1_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_1 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_1 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_1 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_1 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_1 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_1 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_1 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_1 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_1 : 3; - unsigned int INCOHERENTCK_1__SI__CI : 1; - unsigned int TXMARG_1 : 3; - unsigned int DEEMPH_1 : 1; - unsigned int COEFFICIENTID_1 : 2; - unsigned int COEFFICIENT_1 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE2_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_2 : 1; - unsigned int TX_CFG_INV_DATA_2 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_2 : 1; - unsigned int TX_DBG_PRBS_EN_2 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE2_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_2 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_2 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_2 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_2 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_2 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_2 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_2 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_2 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_2 : 3; - unsigned int INCOHERENTCK_2__SI__CI : 1; - unsigned int TXMARG_2 : 3; - unsigned int DEEMPH_2 : 1; - unsigned int COEFFICIENTID_2 : 2; - unsigned int COEFFICIENT_2 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE3_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_3 : 1; - unsigned int TX_CFG_INV_DATA_3 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_3 : 1; - unsigned int TX_DBG_PRBS_EN_3 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE3_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_3 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_3 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_3 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_3 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_3 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_3 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_3 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_3 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_3 : 3; - unsigned int INCOHERENTCK_3__SI__CI : 1; - unsigned int TXMARG_3 : 3; - unsigned int DEEMPH_3 : 1; - unsigned int COEFFICIENTID_3 : 2; - unsigned int COEFFICIENT_3 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE4_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_4 : 1; - unsigned int TX_CFG_INV_DATA_4 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_4 : 1; - unsigned int TX_DBG_PRBS_EN_4 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE4_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_4 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_4 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_4 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_4 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_4 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_4 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_4 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_4 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_4 : 3; - unsigned int INCOHERENTCK_4__SI__CI : 1; - unsigned int TXMARG_4 : 3; - unsigned int DEEMPH_4 : 1; - unsigned int COEFFICIENTID_4 : 2; - unsigned int COEFFICIENT_4 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE5_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_5 : 1; - unsigned int TX_CFG_INV_DATA_5 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_5 : 1; - unsigned int TX_DBG_PRBS_EN_5 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE5_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_5 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_5 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_5 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_5 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_5 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_5 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_5 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_5 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_5 : 3; - unsigned int INCOHERENTCK_5__SI__CI : 1; - unsigned int TXMARG_5 : 3; - unsigned int DEEMPH_5 : 1; - unsigned int COEFFICIENTID_5 : 2; - unsigned int COEFFICIENT_5 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE6_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_6 : 1; - unsigned int TX_CFG_INV_DATA_6 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_6 : 1; - unsigned int TX_DBG_PRBS_EN_6 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE6_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_6 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_6 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_6 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_6 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_6 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_6 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_6 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_6 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_6 : 3; - unsigned int INCOHERENTCK_6__SI__CI : 1; - unsigned int TXMARG_6 : 3; - unsigned int DEEMPH_6 : 1; - unsigned int COEFFICIENTID_6 : 2; - unsigned int COEFFICIENT_6 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE7_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_7 : 1; - unsigned int TX_CFG_INV_DATA_7 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_7 : 1; - unsigned int TX_DBG_PRBS_EN_7 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE7_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_7 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_7 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_7 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_7 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_7 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_7 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_7 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_7 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_7 : 3; - unsigned int INCOHERENTCK_7__SI__CI : 1; - unsigned int TXMARG_7 : 3; - unsigned int DEEMPH_7 : 1; - unsigned int COEFFICIENTID_7 : 2; - unsigned int COEFFICIENT_7 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE8_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_8 : 1; - unsigned int TX_CFG_INV_DATA_8 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_8 : 1; - unsigned int TX_DBG_PRBS_EN_8 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE8_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_8 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_8 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_8 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_8 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_8 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_8 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_8 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_8 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_8 : 3; - unsigned int INCOHERENTCK_8__SI__CI : 1; - unsigned int TXMARG_8 : 3; - unsigned int DEEMPH_8 : 1; - unsigned int COEFFICIENTID_8 : 2; - unsigned int COEFFICIENT_8 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE9_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_9 : 1; - unsigned int TX_CFG_INV_DATA_9 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_9 : 1; - unsigned int TX_DBG_PRBS_EN_9 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE9_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_9 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_9 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_9 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_9 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_9 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_9 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_9 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_9 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_9 : 3; - unsigned int INCOHERENTCK_9__SI__CI : 1; - unsigned int TXMARG_9 : 3; - unsigned int DEEMPH_9 : 1; - unsigned int COEFFICIENTID_9 : 2; - unsigned int COEFFICIENT_9 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_DFT_DEBUG_CTRL_REG0__CI__VI { - struct { - unsigned int DFT_PHY_DEBUG_EN : 1; - unsigned int DFT_PHY_DEBUG_MODE : 5; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_DFT_JIT_INJ_REG0__CI__VI { - struct { - unsigned int DFT_NUM_STEPS : 6; - unsigned int : 1; - unsigned int DFT_DISABLE_ERR : 1; - unsigned int DFT_CLK_PER_STEP : 4; - unsigned int : 8; - unsigned int DFT_MODE_CDR_EN : 1; - unsigned int DFT_EN_RECOVERY : 1; - unsigned int DFT_INCR_SWP_EN : 1; - unsigned int DFT_DECR_SWP_EN : 1; - unsigned int DFT_RECOVERY_TIME : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_DFT_JIT_INJ_REG1__CI__VI { - struct { - unsigned int DFT_BYPASS_VALUE : 8; - unsigned int DFT_BYPASS_EN : 1; - unsigned int : 7; - unsigned int DFT_BLOCK_EN : 1; - unsigned int DFT_NUM_OF_TESTS : 3; - unsigned int DFT_CHECK_TIME : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_DFT_JIT_INJ_REG2__CI__VI { - struct { - unsigned int DFT_LANE_EN : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_DFT_JIT_INJ_STAT_REG0__CI__VI { - struct { - unsigned int DFT_STAT_DECR : 8; - unsigned int DFT_STAT_INCR : 8; - unsigned int DFT_STAT_FINISHED : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_CTRL_REG0__CI__VI { - struct { - unsigned int BACKUP : 16; - unsigned int CFG_IDLEDET_TH : 2; - unsigned int : 2; - unsigned int DBG_RX2TXBYP_SEL : 3; - unsigned int DBG_RXFEBYP_EN : 1; - unsigned int DBG_RXPRBS_CLR : 1; - unsigned int DBG_RXTOGGLE_EN : 1; - unsigned int DBG_TX2RXLBACK_EN : 1; - unsigned int : 3; - unsigned int TXCFG_CMGOOD_RANGE : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_CTRL_REG1__CI__VI { - struct { - unsigned int RXDBG_CDR_FR_BYP_EN : 1; - unsigned int RXDBG_CDR_FR_BYP_VAL : 6; - unsigned int RXDBG_CDR_PH_BYP_EN : 1; - unsigned int RXDBG_CDR_PH_BYP_VAL : 6; - unsigned int RXDBG_D0TH_BYP_EN : 1; - unsigned int RXDBG_D0TH_BYP_VAL : 7; - unsigned int RXDBG_D1TH_BYP_EN : 1; - unsigned int RXDBG_D1TH_BYP_VAL : 7; - unsigned int TST_LOSPDTST_EN : 1; - unsigned int PLL_CFG_DISPCLK_DIV : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_CTRL_REG2__CI__VI { - struct { - unsigned int RXDBG_D2TH_BYP_EN : 1; - unsigned int RXDBG_D2TH_BYP_VAL : 7; - unsigned int RXDBG_D3TH_BYP_EN : 1; - unsigned int RXDBG_D3TH_BYP_VAL : 7; - unsigned int RXDBG_DXTH_BYP_EN : 1; - unsigned int RXDBG_DXTH_BYP_VAL : 7; - unsigned int RXDBG_ETH_BYP_EN : 1; - unsigned int RXDBG_ETH_BYP_VAL : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_CTRL_REG3__CI__VI { - struct { - unsigned int RXDBG_SEL : 5; - unsigned int BG_CFG_LC_REG_VREF0_SEL : 2; - unsigned int BG_CFG_LC_REG_VREF1_SEL : 2; - unsigned int BG_CFG_RO_REG_VREF_SEL : 2; - unsigned int BG_DBG_VREFBYP_EN : 1; - unsigned int BG_DBG_IREFBYP_EN : 1; - unsigned int : 1; - unsigned int BG_DBG_ANALOG_SEL : 3; - unsigned int : 1; - unsigned int DBG_DLL_CLK_SEL : 3; - unsigned int PLL_DISPCLK_CMOS_SEL : 1; - unsigned int DBG_RXPI_OFFSET_BYP_EN : 1; - unsigned int DBG_RXPI_OFFSET_BYP_VAL : 4; - unsigned int DBG_RXSWAPDX_BYP_EN : 1; - unsigned int DBG_RXSWAPDX_BYP_VAL : 3; - unsigned int DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_CTRL_REG4__CI__VI { - struct { - unsigned int DBG_RXAPU_INST : 16; - unsigned int DBG_RXDFEMUX_BYP_VAL : 2; - unsigned int DBG_RXDFEMUX_BYP_EN : 1; - unsigned int : 3; - unsigned int DBG_RXAPU_EXEC : 4; - unsigned int DBG_RXDLL_VREG_REF_SEL : 1; - unsigned int PWRGOOD_OVRD : 1; - unsigned int DBG_RXRDATA_GATING_DISABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_CTRL_REG5__CI__VI { - struct { - unsigned int DBG_RXAPU_MODE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_OVRD_REG0__CI__VI { - struct { - unsigned int TXPDTERM_VAL_OVRD_VAL : 16; - unsigned int TXPUTERM_VAL_OVRD_VAL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_OVRD_REG1__CI__VI { - struct { - unsigned int TXPDTERM_VAL_OVRD_EN : 1; - unsigned int TXPUTERM_VAL_OVRD_EN : 1; - unsigned int TST_LOSPDTST_RST_OVRD_EN : 1; - unsigned int TST_LOSPDTST_RST_OVRD_VAL : 1; - unsigned int : 11; - unsigned int RXTERM_VAL_OVRD_EN : 1; - unsigned int RXTERM_VAL_OVRD_VAL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_OVRD_REG2__CI__VI { - struct { - unsigned int BG_PWRON_OVRD_EN : 1; - unsigned int BG_PWRON_OVRD_VAL : 1; - unsigned int PLL_DBG_LC_EXT_RESET_OVRD_EN__VI : 1; - unsigned int PLL_DBG_LC_EXT_RESET_OVRD_VAL__VI : 1; - unsigned int PLL_DBG_RO_EXT_RESET_OVRD_EN__VI : 1; - unsigned int PLL_DBG_RO_EXT_RESET_OVRD_VAL__VI : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int IGNR_ALL_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_ALL_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_ALL_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_ALL_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_IMPCAL_ACTIVE_SCI_UPDT : 1; - unsigned int : 3; - unsigned int TXNIMP : 4; - unsigned int TXPIMP : 4; - unsigned int RXIMP : 4; - unsigned int IMPCAL_ACTIVE : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int IGNR_ALL_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_ALL_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_ALL_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_ALL_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_IMPCAL_ACTIVE_CBI_UPDT : 1; - unsigned int : 3; - unsigned int TXNIMP : 4; - unsigned int TXPIMP : 4; - unsigned int RXIMP : 4; - unsigned int IMPCAL_ACTIVE : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_SCI_STAT_OVRD_REG1__CI { - struct { - unsigned int IGNR_MODE_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_FREQDIV_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_DLL_LOCK_SCI_UPDT_L0T3 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_0 : 1; - unsigned int DLL_LOCK_1 : 1; - unsigned int DLL_LOCK_2 : 1; - unsigned int DLL_LOCK_3 : 1; - unsigned int MODE_0 : 2; - unsigned int FREQDIV_0 : 2; - unsigned int MODE_1 : 2; - unsigned int FREQDIV_1 : 2; - unsigned int MODE_2 : 2; - unsigned int FREQDIV_2 : 2; - unsigned int MODE_3 : 2; - unsigned int FREQDIV_3 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_SCI_STAT_OVRD_REG1__VI { - struct { - unsigned int IGNR_LINKSPEED_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_FREQDIV_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_DLL_LOCK_CBI_UPDT_L0T3 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_0 : 1; - unsigned int DLL_LOCK_1 : 1; - unsigned int DLL_LOCK_2 : 1; - unsigned int DLL_LOCK_3 : 1; - unsigned int LINKSPEED_0 : 2; - unsigned int FREQDIV_0 : 2; - unsigned int LINKSPEED_1 : 2; - unsigned int FREQDIV_1 : 2; - unsigned int LINKSPEED_2 : 2; - unsigned int FREQDIV_2 : 2; - unsigned int LINKSPEED_3 : 2; - unsigned int FREQDIV_3 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_SCI_STAT_OVRD_REG2__CI { - struct { - unsigned int IGNR_MODE_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_FREQDIV_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_DLL_LOCK_SCI_UPDT_L4T7 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_4 : 1; - unsigned int DLL_LOCK_5 : 1; - unsigned int DLL_LOCK_6 : 1; - unsigned int DLL_LOCK_7 : 1; - unsigned int MODE_4 : 2; - unsigned int FREQDIV_4 : 2; - unsigned int MODE_5 : 2; - unsigned int FREQDIV_5 : 2; - unsigned int MODE_6 : 2; - unsigned int FREQDIV_6 : 2; - unsigned int MODE_7 : 2; - unsigned int FREQDIV_7 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_SCI_STAT_OVRD_REG2__VI { - struct { - unsigned int IGNR_LINKSPEED_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_FREQDIV_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_DLL_LOCK_CBI_UPDT_L4T7 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_4 : 1; - unsigned int DLL_LOCK_5 : 1; - unsigned int DLL_LOCK_6 : 1; - unsigned int DLL_LOCK_7 : 1; - unsigned int LINKSPEED_4 : 2; - unsigned int FREQDIV_4 : 2; - unsigned int LINKSPEED_5 : 2; - unsigned int FREQDIV_5 : 2; - unsigned int LINKSPEED_6 : 2; - unsigned int FREQDIV_6 : 2; - unsigned int LINKSPEED_7 : 2; - unsigned int FREQDIV_7 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_SCI_STAT_OVRD_REG3__CI { - struct { - unsigned int IGNR_MODE_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_FREQDIV_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_DLL_LOCK_SCI_UPDT_L8T11 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_8 : 1; - unsigned int DLL_LOCK_9 : 1; - unsigned int DLL_LOCK_10 : 1; - unsigned int DLL_LOCK_11 : 1; - unsigned int MODE_8 : 2; - unsigned int FREQDIV_8 : 2; - unsigned int MODE_9 : 2; - unsigned int FREQDIV_9 : 2; - unsigned int MODE_10 : 2; - unsigned int FREQDIV_10 : 2; - unsigned int MODE_11 : 2; - unsigned int FREQDIV_11 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_SCI_STAT_OVRD_REG3__VI { - struct { - unsigned int IGNR_LINKSPEED_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_FREQDIV_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_DLL_LOCK_CBI_UPDT_L8T11 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_8 : 1; - unsigned int DLL_LOCK_9 : 1; - unsigned int DLL_LOCK_10 : 1; - unsigned int DLL_LOCK_11 : 1; - unsigned int LINKSPEED_8 : 2; - unsigned int FREQDIV_8 : 2; - unsigned int LINKSPEED_9 : 2; - unsigned int FREQDIV_9 : 2; - unsigned int LINKSPEED_10 : 2; - unsigned int FREQDIV_10 : 2; - unsigned int LINKSPEED_11 : 2; - unsigned int FREQDIV_11 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_SCI_STAT_OVRD_REG4__CI { - struct { - unsigned int IGNR_MODE_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_FREQDIV_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_DLL_LOCK_SCI_UPDT_L12T15 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_12 : 1; - unsigned int DLL_LOCK_13 : 1; - unsigned int DLL_LOCK_14 : 1; - unsigned int DLL_LOCK_15 : 1; - unsigned int MODE_12 : 2; - unsigned int FREQDIV_12 : 2; - unsigned int MODE_13 : 2; - unsigned int FREQDIV_13 : 2; - unsigned int MODE_14 : 2; - unsigned int FREQDIV_14 : 2; - unsigned int MODE_15 : 2; - unsigned int FREQDIV_15 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_GLB_SCI_STAT_OVRD_REG4__VI { - struct { - unsigned int IGNR_LINKSPEED_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_FREQDIV_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_DLL_LOCK_CBI_UPDT_L12T15 : 1; - unsigned int : 9; - unsigned int DLL_LOCK_12 : 1; - unsigned int DLL_LOCK_13 : 1; - unsigned int DLL_LOCK_14 : 1; - unsigned int DLL_LOCK_15 : 1; - unsigned int LINKSPEED_12 : 2; - unsigned int FREQDIV_12 : 2; - unsigned int LINKSPEED_13 : 2; - unsigned int FREQDIV_13 : 2; - unsigned int LINKSPEED_14 : 2; - unsigned int FREQDIV_14 : 2; - unsigned int LINKSPEED_15 : 2; - unsigned int FREQDIV_15 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_HW_DEBUG__CI { - struct { - unsigned int PB1_HW_00_DEBUG : 1; - unsigned int PB1_HW_01_DEBUG : 1; - unsigned int PB1_HW_02_DEBUG : 1; - unsigned int PB1_HW_03_DEBUG : 1; - unsigned int PB1_HW_04_DEBUG : 1; - unsigned int PB1_HW_05_DEBUG : 1; - unsigned int PB1_HW_06_DEBUG : 1; - unsigned int PB1_HW_07_DEBUG : 1; - unsigned int PB1_HW_08_DEBUG : 1; - unsigned int PB1_HW_09_DEBUG : 1; - unsigned int PB1_HW_10_DEBUG : 1; - unsigned int PB1_HW_11_DEBUG : 1; - unsigned int PB1_HW_12_DEBUG : 1; - unsigned int PB1_HW_13_DEBUG : 1; - unsigned int PB1_HW_14_DEBUG : 1; - unsigned int PB1_HW_15_DEBUG : 1; - unsigned int PB1_HW_16_DEBUG : 1; - unsigned int PB1_HW_17_DEBUG : 1; - unsigned int PB1_HW_18_DEBUG : 1; - unsigned int PB1_HW_19_DEBUG : 1; - unsigned int PB1_HW_20_DEBUG : 1; - unsigned int PB1_HW_21_DEBUG : 1; - unsigned int PB1_HW_22_DEBUG : 1; - unsigned int PB1_HW_23_DEBUG : 1; - unsigned int PB1_HW_24_DEBUG : 1; - unsigned int PB1_HW_25_DEBUG : 1; - unsigned int PB1_HW_26_DEBUG : 1; - unsigned int PB1_HW_27_DEBUG : 1; - unsigned int PB1_HW_28_DEBUG : 1; - unsigned int PB1_HW_29_DEBUG : 1; - unsigned int PB1_HW_30_DEBUG : 1; - unsigned int PB1_HW_31_DEBUG : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_HW_DEBUG__VI { - struct { - unsigned int HW_00_DEBUG : 1; - unsigned int HW_01_DEBUG : 1; - unsigned int HW_02_DEBUG : 1; - unsigned int HW_03_DEBUG : 1; - unsigned int HW_04_DEBUG : 1; - unsigned int HW_05_DEBUG : 1; - unsigned int HW_06_DEBUG : 1; - unsigned int HW_07_DEBUG : 1; - unsigned int HW_08_DEBUG : 1; - unsigned int HW_09_DEBUG : 1; - unsigned int HW_10_DEBUG : 1; - unsigned int HW_11_DEBUG : 1; - unsigned int HW_12_DEBUG : 1; - unsigned int HW_13_DEBUG : 1; - unsigned int HW_14_DEBUG : 1; - unsigned int HW_15_DEBUG : 1; - unsigned int HW_16_DEBUG : 1; - unsigned int HW_17_DEBUG : 1; - unsigned int HW_18_DEBUG : 1; - unsigned int HW_19_DEBUG : 1; - unsigned int HW_20_DEBUG : 1; - unsigned int HW_21_DEBUG : 1; - unsigned int HW_22_DEBUG : 1; - unsigned int HW_23_DEBUG : 1; - unsigned int HW_24_DEBUG : 1; - unsigned int HW_25_DEBUG : 1; - unsigned int HW_26_DEBUG : 1; - unsigned int HW_27_DEBUG : 1; - unsigned int HW_28_DEBUG : 1; - unsigned int HW_29_DEBUG : 1; - unsigned int HW_30_DEBUG : 1; - unsigned int HW_31_DEBUG : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_CNTL2__CI { - struct { - unsigned int : 1; - unsigned int RXDETECT_SAMPL_TIME : 2; - unsigned int : 4; - unsigned int RXDETECT_OVERRIDE_EN : 1; - unsigned int RXDETECT_OVERRIDE_VAL_0 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_1 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_2 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_3 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_4 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_5 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_6 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_7 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_8 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_9 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_10 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_11 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_12 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_13 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_14 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_15 : 1; - unsigned int RXPHYSTATUS_DELAY : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_CNTL__CI { - struct { - unsigned int SERIAL_CFG_ENABLE : 1; - unsigned int DA_FIFO_RESET_0 : 1; - unsigned int PHY_CR_EN_MODE : 1; - unsigned int PHYCMD_CR_EN_MODE : 1; - unsigned int EI_DET_CYCLE_MODE : 1; - unsigned int DA_FIFO_RESET_1 : 1; - unsigned int RXDETECT_FIFO_RESET_MODE : 1; - unsigned int RXDETECT_TX_PWR_MODE : 1; - unsigned int DIVINIT_MODE : 1; - unsigned int DA_FIFO_RESET_2 : 1; - unsigned int PLL_BINDING_ENABLE : 1; - unsigned int SC_CALIB_DONE_CNTL : 1; - unsigned int : 1; - unsigned int DA_FIFO_RESET_3 : 1; - unsigned int : 2; - unsigned int TXGND_TIME : 1; - unsigned int LS2_EXIT_TIME : 3; - unsigned int EI_CYCLE_OFF_TIME : 3; - unsigned int EXIT_L0S_INIT_DIS : 1; - unsigned int RXEN_GATER : 4; - unsigned int EXTEND_WAIT_FOR_RAMPUP : 1; - unsigned int IGNORE_TxDataValid_EP_DIS : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_HW_DEBUG__CI { - struct { - unsigned int PB1_PIF_HW_00_DEBUG : 1; - unsigned int PB1_PIF_HW_01_DEBUG : 1; - unsigned int PB1_PIF_HW_02_DEBUG : 1; - unsigned int PB1_PIF_HW_03_DEBUG : 1; - unsigned int PB1_PIF_HW_04_DEBUG : 1; - unsigned int PB1_PIF_HW_05_DEBUG : 1; - unsigned int PB1_PIF_HW_06_DEBUG : 1; - unsigned int PB1_PIF_HW_07_DEBUG : 1; - unsigned int PB1_PIF_HW_08_DEBUG : 1; - unsigned int PB1_PIF_HW_09_DEBUG : 1; - unsigned int PB1_PIF_HW_10_DEBUG : 1; - unsigned int PB1_PIF_HW_11_DEBUG : 1; - unsigned int PB1_PIF_HW_12_DEBUG : 1; - unsigned int PB1_PIF_HW_13_DEBUG : 1; - unsigned int PB1_PIF_HW_14_DEBUG : 1; - unsigned int PB1_PIF_HW_15_DEBUG : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_HW_DEBUG__VI { - struct { - unsigned int HW_00_DEBUG : 1; - unsigned int HW_01_DEBUG : 1; - unsigned int HW_02_DEBUG : 1; - unsigned int HW_03_DEBUG : 1; - unsigned int HW_04_DEBUG : 1; - unsigned int HW_05_DEBUG : 1; - unsigned int HW_06_DEBUG : 1; - unsigned int HW_07_DEBUG : 1; - unsigned int HW_08_DEBUG : 1; - unsigned int HW_09_DEBUG : 1; - unsigned int HW_10_DEBUG : 1; - unsigned int HW_11_DEBUG : 1; - unsigned int HW_12_DEBUG : 1; - unsigned int HW_13_DEBUG : 1; - unsigned int HW_14_DEBUG : 1; - unsigned int HW_15_DEBUG : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PAIRING__CI { - struct { - unsigned int X2_LANE_1_0 : 1; - unsigned int X2_LANE_3_2 : 1; - unsigned int X2_LANE_5_4 : 1; - unsigned int X2_LANE_7_6 : 1; - unsigned int X2_LANE_9_8 : 1; - unsigned int X2_LANE_11_10 : 1; - unsigned int X2_LANE_13_12 : 1; - unsigned int X2_LANE_15_14 : 1; - unsigned int X4_LANE_3_0 : 1; - unsigned int X4_LANE_7_4 : 1; - unsigned int X4_LANE_11_8 : 1; - unsigned int X4_LANE_15_12 : 1; - unsigned int : 4; - unsigned int X8_LANE_7_0 : 1; - unsigned int X8_LANE_15_8 : 1; - unsigned int : 2; - unsigned int X16_LANE_15_0 : 1; - unsigned int : 4; - unsigned int MULTI_PIF : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_0__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_0 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_0 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_0 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_0 : 3; - unsigned int RXEN_OVERRIDE_EN_0 : 1; - unsigned int RXEN_OVERRIDE_VAL_0 : 1; - unsigned int TXPWR_OVERRIDE_EN_0 : 1; - unsigned int TXPWR_OVERRIDE_VAL_0 : 3; - unsigned int RXPWR_OVERRIDE_EN_0 : 1; - unsigned int RXPWR_OVERRIDE_VAL_0 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_10__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_10 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_10 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_10 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_10 : 3; - unsigned int RXEN_OVERRIDE_EN_10 : 1; - unsigned int RXEN_OVERRIDE_VAL_10 : 1; - unsigned int TXPWR_OVERRIDE_EN_10 : 1; - unsigned int TXPWR_OVERRIDE_VAL_10 : 3; - unsigned int RXPWR_OVERRIDE_EN_10 : 1; - unsigned int RXPWR_OVERRIDE_VAL_10 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_11__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_11 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_11 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_11 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_11 : 3; - unsigned int RXEN_OVERRIDE_EN_11 : 1; - unsigned int RXEN_OVERRIDE_VAL_11 : 1; - unsigned int TXPWR_OVERRIDE_EN_11 : 1; - unsigned int TXPWR_OVERRIDE_VAL_11 : 3; - unsigned int RXPWR_OVERRIDE_EN_11 : 1; - unsigned int RXPWR_OVERRIDE_VAL_11 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_12__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_12 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_12 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_12 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_12 : 3; - unsigned int RXEN_OVERRIDE_EN_12 : 1; - unsigned int RXEN_OVERRIDE_VAL_12 : 1; - unsigned int TXPWR_OVERRIDE_EN_12 : 1; - unsigned int TXPWR_OVERRIDE_VAL_12 : 3; - unsigned int RXPWR_OVERRIDE_EN_12 : 1; - unsigned int RXPWR_OVERRIDE_VAL_12 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_13__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_13 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_13 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_13 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_13 : 3; - unsigned int RXEN_OVERRIDE_EN_13 : 1; - unsigned int RXEN_OVERRIDE_VAL_13 : 1; - unsigned int TXPWR_OVERRIDE_EN_13 : 1; - unsigned int TXPWR_OVERRIDE_VAL_13 : 3; - unsigned int RXPWR_OVERRIDE_EN_13 : 1; - unsigned int RXPWR_OVERRIDE_VAL_13 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_14__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_14 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_14 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_14 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_14 : 3; - unsigned int RXEN_OVERRIDE_EN_14 : 1; - unsigned int RXEN_OVERRIDE_VAL_14 : 1; - unsigned int TXPWR_OVERRIDE_EN_14 : 1; - unsigned int TXPWR_OVERRIDE_VAL_14 : 3; - unsigned int RXPWR_OVERRIDE_EN_14 : 1; - unsigned int RXPWR_OVERRIDE_VAL_14 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_15__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_15 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_15 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_15 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_15 : 3; - unsigned int RXEN_OVERRIDE_EN_15 : 1; - unsigned int RXEN_OVERRIDE_VAL_15 : 1; - unsigned int TXPWR_OVERRIDE_EN_15 : 1; - unsigned int TXPWR_OVERRIDE_VAL_15 : 3; - unsigned int RXPWR_OVERRIDE_EN_15 : 1; - unsigned int RXPWR_OVERRIDE_VAL_15 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_1__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_1 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_1 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_1 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_1 : 3; - unsigned int RXEN_OVERRIDE_EN_1 : 1; - unsigned int RXEN_OVERRIDE_VAL_1 : 1; - unsigned int TXPWR_OVERRIDE_EN_1 : 1; - unsigned int TXPWR_OVERRIDE_VAL_1 : 3; - unsigned int RXPWR_OVERRIDE_EN_1 : 1; - unsigned int RXPWR_OVERRIDE_VAL_1 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_2__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_2 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_2 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_2 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_2 : 3; - unsigned int RXEN_OVERRIDE_EN_2 : 1; - unsigned int RXEN_OVERRIDE_VAL_2 : 1; - unsigned int TXPWR_OVERRIDE_EN_2 : 1; - unsigned int TXPWR_OVERRIDE_VAL_2 : 3; - unsigned int RXPWR_OVERRIDE_EN_2 : 1; - unsigned int RXPWR_OVERRIDE_VAL_2 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_3__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_3 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_3 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_3 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_3 : 3; - unsigned int RXEN_OVERRIDE_EN_3 : 1; - unsigned int RXEN_OVERRIDE_VAL_3 : 1; - unsigned int TXPWR_OVERRIDE_EN_3 : 1; - unsigned int TXPWR_OVERRIDE_VAL_3 : 3; - unsigned int RXPWR_OVERRIDE_EN_3 : 1; - unsigned int RXPWR_OVERRIDE_VAL_3 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_4__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_4 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_4 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_4 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_4 : 3; - unsigned int RXEN_OVERRIDE_EN_4 : 1; - unsigned int RXEN_OVERRIDE_VAL_4 : 1; - unsigned int TXPWR_OVERRIDE_EN_4 : 1; - unsigned int TXPWR_OVERRIDE_VAL_4 : 3; - unsigned int RXPWR_OVERRIDE_EN_4 : 1; - unsigned int RXPWR_OVERRIDE_VAL_4 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_5__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_5 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_5 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_5 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_5 : 3; - unsigned int RXEN_OVERRIDE_EN_5 : 1; - unsigned int RXEN_OVERRIDE_VAL_5 : 1; - unsigned int TXPWR_OVERRIDE_EN_5 : 1; - unsigned int TXPWR_OVERRIDE_VAL_5 : 3; - unsigned int RXPWR_OVERRIDE_EN_5 : 1; - unsigned int RXPWR_OVERRIDE_VAL_5 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_6__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_6 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_6 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_6 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_6 : 3; - unsigned int RXEN_OVERRIDE_EN_6 : 1; - unsigned int RXEN_OVERRIDE_VAL_6 : 1; - unsigned int TXPWR_OVERRIDE_EN_6 : 1; - unsigned int TXPWR_OVERRIDE_VAL_6 : 3; - unsigned int RXPWR_OVERRIDE_EN_6 : 1; - unsigned int RXPWR_OVERRIDE_VAL_6 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_7__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_7 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_7 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_7 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_7 : 3; - unsigned int RXEN_OVERRIDE_EN_7 : 1; - unsigned int RXEN_OVERRIDE_VAL_7 : 1; - unsigned int TXPWR_OVERRIDE_EN_7 : 1; - unsigned int TXPWR_OVERRIDE_VAL_7 : 3; - unsigned int RXPWR_OVERRIDE_EN_7 : 1; - unsigned int RXPWR_OVERRIDE_VAL_7 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_8__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_8 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_8 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_8 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_8 : 3; - unsigned int RXEN_OVERRIDE_EN_8 : 1; - unsigned int RXEN_OVERRIDE_VAL_8 : 1; - unsigned int TXPWR_OVERRIDE_EN_8 : 1; - unsigned int TXPWR_OVERRIDE_VAL_8 : 3; - unsigned int RXPWR_OVERRIDE_EN_8 : 1; - unsigned int RXPWR_OVERRIDE_VAL_8 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PDNB_OVERRIDE_9__CI { - struct { - unsigned int TX_PDNB_OVERRIDE_EN_9 : 1; - unsigned int TX_PDNB_OVERRIDE_VAL_9 : 3; - unsigned int RX_PDNB_OVERRIDE_EN_9 : 1; - unsigned int RX_PDNB_OVERRIDE_VAL_9 : 3; - unsigned int RXEN_OVERRIDE_EN_9 : 1; - unsigned int RXEN_OVERRIDE_VAL_9 : 1; - unsigned int TXPWR_OVERRIDE_EN_9 : 1; - unsigned int TXPWR_OVERRIDE_VAL_9 : 3; - unsigned int RXPWR_OVERRIDE_EN_9 : 1; - unsigned int RXPWR_OVERRIDE_VAL_9 : 3; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PWRDOWN_0__CI { - struct { - unsigned int TX_POWER_STATE_IN_TXS2_0 : 3; - unsigned int FORCE_RXEN_IN_L0s_0 : 1; - unsigned int RX_POWER_STATE_IN_RXS2_0 : 3; - unsigned int PLL_POWER_STATE_IN_TXS2_0 : 3; - unsigned int PLL_POWER_STATE_IN_OFF_0 : 3; - unsigned int : 3; - unsigned int TX2P5CLK_CLOCK_GATING_EN_0 : 1; - unsigned int : 7; - unsigned int PLL_RAMP_UP_TIME_0 : 3; - unsigned int : 1; - unsigned int PLLPWR_OVERRIDE_EN_0 : 1; - unsigned int PLLPWR_OVERRIDE_VAL_0 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PWRDOWN_1__CI { - struct { - unsigned int TX_POWER_STATE_IN_TXS2_1 : 3; - unsigned int FORCE_RXEN_IN_L0s_1 : 1; - unsigned int RX_POWER_STATE_IN_RXS2_1 : 3; - unsigned int PLL_POWER_STATE_IN_TXS2_1 : 3; - unsigned int PLL_POWER_STATE_IN_OFF_1 : 3; - unsigned int : 3; - unsigned int TX2P5CLK_CLOCK_GATING_EN_1 : 1; - unsigned int : 7; - unsigned int PLL_RAMP_UP_TIME_1 : 3; - unsigned int : 1; - unsigned int PLLPWR_OVERRIDE_EN_1 : 1; - unsigned int PLLPWR_OVERRIDE_VAL_1 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PWRDOWN_2__CI { - struct { - unsigned int TX_POWER_STATE_IN_TXS2_2 : 3; - unsigned int FORCE_RXEN_IN_L0s_2 : 1; - unsigned int RX_POWER_STATE_IN_RXS2_2 : 3; - unsigned int PLL_POWER_STATE_IN_TXS2_2 : 3; - unsigned int PLL_POWER_STATE_IN_OFF_2 : 3; - unsigned int : 3; - unsigned int TX2P5CLK_CLOCK_GATING_EN_2 : 1; - unsigned int : 7; - unsigned int PLL_RAMP_UP_TIME_2 : 3; - unsigned int : 1; - unsigned int PLLPWR_OVERRIDE_EN_2 : 1; - unsigned int PLLPWR_OVERRIDE_VAL_2 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_PWRDOWN_3__CI { - struct { - unsigned int TX_POWER_STATE_IN_TXS2_3 : 3; - unsigned int FORCE_RXEN_IN_L0s_3 : 1; - unsigned int RX_POWER_STATE_IN_RXS2_3 : 3; - unsigned int PLL_POWER_STATE_IN_TXS2_3 : 3; - unsigned int PLL_POWER_STATE_IN_OFF_3 : 3; - unsigned int : 3; - unsigned int TX2P5CLK_CLOCK_GATING_EN_3 : 1; - unsigned int : 7; - unsigned int PLL_RAMP_UP_TIME_3 : 3; - unsigned int : 1; - unsigned int PLLPWR_OVERRIDE_EN_3 : 1; - unsigned int PLLPWR_OVERRIDE_VAL_3 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SCRATCH__CI__VI { - struct { - unsigned int PIF_SCRATCH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SC_CTL__CI { - struct { - unsigned int SC_CALIBRATION : 1; - unsigned int SC_RXDETECT : 1; - unsigned int SC_EXIT_L1_TO_L0S : 1; - unsigned int SC_EXIT_L1_TO_L0 : 1; - unsigned int SC_ENTER_L1_FROM_L0S : 1; - unsigned int SC_ENTER_L1_FROM_L0 : 1; - unsigned int SC_SPEED_CHANGE : 1; - unsigned int : 1; - unsigned int SC_PHASE_1 : 1; - unsigned int SC_PHASE_2 : 1; - unsigned int SC_PHASE_3 : 1; - unsigned int SC_PHASE_4 : 1; - unsigned int SC_PHASE_5 : 1; - unsigned int SC_PHASE_6 : 1; - unsigned int SC_PHASE_7 : 1; - unsigned int SC_PHASE_8 : 1; - unsigned int SC_LANE_0_RESUME : 1; - unsigned int SC_LANE_1_RESUME : 1; - unsigned int SC_LANE_2_RESUME : 1; - unsigned int SC_LANE_3_RESUME : 1; - unsigned int SC_LANE_4_RESUME : 1; - unsigned int SC_LANE_5_RESUME : 1; - unsigned int SC_LANE_6_RESUME : 1; - unsigned int SC_LANE_7_RESUME : 1; - unsigned int SC_LANE_8_RESUME : 1; - unsigned int SC_LANE_9_RESUME : 1; - unsigned int SC_LANE_10_RESUME : 1; - unsigned int SC_LANE_11_RESUME : 1; - unsigned int SC_LANE_12_RESUME : 1; - unsigned int SC_LANE_13_RESUME : 1; - unsigned int SC_LANE_14_RESUME : 1; - unsigned int SC_LANE_15_RESUME : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_0__CI { - struct { - unsigned int SEQ_CALIBRATION_0 : 1; - unsigned int SEQ_RXDETECT_0 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_0 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_0 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_0 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_0 : 1; - unsigned int SEQ_SPEED_CHANGE_0 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_0 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_10__CI { - struct { - unsigned int SEQ_CALIBRATION_10 : 1; - unsigned int SEQ_RXDETECT_10 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_10 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_10 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_10 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_10 : 1; - unsigned int SEQ_SPEED_CHANGE_10 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_10 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_11__CI { - struct { - unsigned int SEQ_CALIBRATION_11 : 1; - unsigned int SEQ_RXDETECT_11 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_11 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_11 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_11 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_11 : 1; - unsigned int SEQ_SPEED_CHANGE_11 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_11 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_12__CI { - struct { - unsigned int SEQ_CALIBRATION_12 : 1; - unsigned int SEQ_RXDETECT_12 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_12 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_12 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_12 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_12 : 1; - unsigned int SEQ_SPEED_CHANGE_12 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_12 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_13__CI { - struct { - unsigned int SEQ_CALIBRATION_13 : 1; - unsigned int SEQ_RXDETECT_13 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_13 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_13 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_13 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_13 : 1; - unsigned int SEQ_SPEED_CHANGE_13 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_13 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_14__CI { - struct { - unsigned int SEQ_CALIBRATION_14 : 1; - unsigned int SEQ_RXDETECT_14 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_14 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_14 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_14 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_14 : 1; - unsigned int SEQ_SPEED_CHANGE_14 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_14 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_15__CI { - struct { - unsigned int SEQ_CALIBRATION_15 : 1; - unsigned int SEQ_RXDETECT_15 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_15 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_15 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_15 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_15 : 1; - unsigned int SEQ_SPEED_CHANGE_15 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_15 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_1__CI { - struct { - unsigned int SEQ_CALIBRATION_1 : 1; - unsigned int SEQ_RXDETECT_1 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_1 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_1 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_1 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_1 : 1; - unsigned int SEQ_SPEED_CHANGE_1 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_1 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_2__CI { - struct { - unsigned int SEQ_CALIBRATION_2 : 1; - unsigned int SEQ_RXDETECT_2 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_2 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_2 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_2 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_2 : 1; - unsigned int SEQ_SPEED_CHANGE_2 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_2 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_3__CI { - struct { - unsigned int SEQ_CALIBRATION_3 : 1; - unsigned int SEQ_RXDETECT_3 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_3 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_3 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_3 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_3 : 1; - unsigned int SEQ_SPEED_CHANGE_3 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_3 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_4__CI { - struct { - unsigned int SEQ_CALIBRATION_4 : 1; - unsigned int SEQ_RXDETECT_4 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_4 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_4 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_4 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_4 : 1; - unsigned int SEQ_SPEED_CHANGE_4 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_4 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_5__CI { - struct { - unsigned int SEQ_CALIBRATION_5 : 1; - unsigned int SEQ_RXDETECT_5 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_5 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_5 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_5 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_5 : 1; - unsigned int SEQ_SPEED_CHANGE_5 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_5 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_6__CI { - struct { - unsigned int SEQ_CALIBRATION_6 : 1; - unsigned int SEQ_RXDETECT_6 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_6 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_6 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_6 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_6 : 1; - unsigned int SEQ_SPEED_CHANGE_6 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_6 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_7__CI { - struct { - unsigned int SEQ_CALIBRATION_7 : 1; - unsigned int SEQ_RXDETECT_7 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_7 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_7 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_7 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_7 : 1; - unsigned int SEQ_SPEED_CHANGE_7 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_7 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_8__CI { - struct { - unsigned int SEQ_CALIBRATION_8 : 1; - unsigned int SEQ_RXDETECT_8 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_8 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_8 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_8 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_8 : 1; - unsigned int SEQ_SPEED_CHANGE_8 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_8 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_SEQ_STATUS_9__CI { - struct { - unsigned int SEQ_CALIBRATION_9 : 1; - unsigned int SEQ_RXDETECT_9 : 1; - unsigned int SEQ_EXIT_L1_TO_L0S_9 : 1; - unsigned int SEQ_EXIT_L1_TO_L0_9 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0S_9 : 1; - unsigned int SEQ_ENTER_L1_FROM_L0_9 : 1; - unsigned int SEQ_SPEED_CHANGE_9 : 1; - unsigned int : 1; - unsigned int SEQ_PHASE_9 : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_TXPHYSTATUS__CI { - struct { - unsigned int TXPHYSTATUS_0 : 1; - unsigned int TXPHYSTATUS_1 : 1; - unsigned int TXPHYSTATUS_2 : 1; - unsigned int TXPHYSTATUS_3 : 1; - unsigned int TXPHYSTATUS_4 : 1; - unsigned int TXPHYSTATUS_5 : 1; - unsigned int TXPHYSTATUS_6 : 1; - unsigned int TXPHYSTATUS_7 : 1; - unsigned int TXPHYSTATUS_8 : 1; - unsigned int TXPHYSTATUS_9 : 1; - unsigned int TXPHYSTATUS_10 : 1; - unsigned int TXPHYSTATUS_11 : 1; - unsigned int TXPHYSTATUS_12 : 1; - unsigned int TXPHYSTATUS_13 : 1; - unsigned int TXPHYSTATUS_14 : 1; - unsigned int TXPHYSTATUS_15 : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_LC0_CTRL_REG0__CI__VI { - struct { - unsigned int PLL_DBG_LC_ANALOG_SEL_0 : 2; - unsigned int PLL_DBG_LC_EXT_RESET_EN_0 : 1; - unsigned int PLL_DBG_LC_VCTL_ADC_EN_0 : 1; - unsigned int PLL_TST_LC_USAMPLE_EN_0 : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_LC0_OVRD_REG0__CI__VI { - struct { - unsigned int PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 : 3; - unsigned int PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 : 1; - unsigned int PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0 : 3; - unsigned int PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 : 1; - unsigned int PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 : 1; - unsigned int PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 : 1; - unsigned int PLL_CFG_LC_FBDIV_OVRD_VAL_0 : 8; - unsigned int PLL_CFG_LC_FBDIV_OVRD_EN_0 : 1; - unsigned int PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 : 9; - unsigned int PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 : 1; - unsigned int PLL_CFG_LC_REFDIV_OVRD_VAL_0 : 2; - unsigned int PLL_CFG_LC_REFDIV_OVRD_EN_0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_LC0_OVRD_REG1__CI__VI { - struct { - unsigned int PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0 : 3; - unsigned int PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 : 1; - unsigned int PLL_LC_PWRON_OVRD_VAL_0 : 1; - unsigned int PLL_LC_PWRON_OVRD_EN_0 : 1; - unsigned int : 4; - unsigned int PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 : 4; - unsigned int PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_LC0_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_LC0_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_LC0_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_LC0_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_LC0_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_LC0_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_LC0_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int : 3; - unsigned int PLL_LC0_PLLPWR : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_LC1_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_LC1_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_LC1_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_LC1_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_LC1_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_LC1_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_LC1_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int : 3; - unsigned int PLL_LC1_PLLPWR : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_LC2_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_LC2_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_LC2_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_LC2_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_LC2_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_LC2_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_LC2_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int : 3; - unsigned int PLL_LC2_PLLPWR : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_LC3_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_LC3_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_LC3_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_LC3_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_LC3_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_LC3_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_LC3_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int : 3; - unsigned int PLL_LC3_PLLPWR : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO0_CTRL_REG0__CI__VI { - struct { - unsigned int PLL_DBG_RO_ANALOG_SEL_0 : 2; - unsigned int PLL_DBG_RO_EXT_RESET_EN_0 : 1; - unsigned int PLL_DBG_RO_VCTL_ADC_EN_0 : 1; - unsigned int PLL_DBG_RO_LF_CNTRL_0 : 7; - unsigned int PLL_TST_RO_USAMPLE_EN_0 : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO0_OVRD_REG0__CI__VI { - struct { - unsigned int PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 : 8; - unsigned int PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 : 1; - unsigned int PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 : 3; - unsigned int PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 : 1; - unsigned int PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 : 1; - unsigned int PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 : 1; - unsigned int PLL_CFG_RO_FBDIV_OVRD_VAL_0 : 13; - unsigned int PLL_CFG_RO_FBDIV_OVRD_EN_0 : 1; - unsigned int : 1; - unsigned int PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0 : 1; - unsigned int PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO0_OVRD_REG1__CI__VI { - struct { - unsigned int PLL_CFG_RO_REFDIV_OVRD_VAL_0 : 5; - unsigned int PLL_CFG_RO_REFDIV_OVRD_EN_0 : 1; - unsigned int PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 : 2; - unsigned int PLL_CFG_RO_VCO_MODE_OVRD_EN_0 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 : 1; - unsigned int PLL_RO_PWRON_OVRD_VAL_0 : 1; - unsigned int PLL_RO_PWRON_OVRD_EN_0 : 1; - unsigned int : 4; - unsigned int PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0 : 3; - unsigned int PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO0_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_RO0_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_RO0_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO0_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO0_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO0_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_RO0_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int PLL_RO0_IGNR_PLLFREQ_CBI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO0_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO0_PLLFREQ : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO1_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_RO1_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_RO1_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO1_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO1_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO1_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_RO1_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int PLL_RO1_IGNR_PLLFREQ_CBI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO1_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO1_PLLFREQ : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO2_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_RO2_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_RO2_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO2_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO2_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO2_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_RO2_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int PLL_RO2_IGNR_PLLFREQ_CBI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO2_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO2_PLLFREQ : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO3_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int PLL_RO3_IGNR_PLLPWR_SCI_UPDT : 1; - unsigned int PLL_RO3_IGNR_FREQMODE_SCI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO3_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO3_FREQMODE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO3_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int PLL_RO3_IGNR_PLLPWR_CBI_UPDT : 1; - unsigned int PLL_RO3_IGNR_PLLFREQ_CBI_UPDT : 1; - unsigned int : 2; - unsigned int PLL_RO3_PLLPWR : 3; - unsigned int : 1; - unsigned int PLL_RO3_PLLFREQ : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO_GLB_CTRL_REG0__CI { - struct { - unsigned int PLL_TST_LOSPDTST_SRC : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_RO_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1; - unsigned int : 1; - unsigned int PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN : 1; - unsigned int PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN : 1; - unsigned int PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN : 1; - unsigned int PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PLL_RO_GLB_CTRL_REG0__VI { - struct { - unsigned int PLL_TST_LOSPDTST_SRC : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_RO_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 : 1; - unsigned int PLL_RO_HSCLK_LEFT_EN_GATING_EN : 1; - unsigned int PLL_RO_HSCLK_RIGHT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_LEFT_EN_GATING_EN : 1; - unsigned int PLL_LC_HSCLK_RIGHT_EN_GATING_EN : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_CTRL_REG0__CI__VI { - struct { - unsigned int RX_CFG_ADAPT_MODE_GEN1 : 10; - unsigned int RX_CFG_ADAPT_MODE_GEN2 : 10; - unsigned int RX_CFG_ADAPT_MODE_GEN3 : 10; - unsigned int RX_CFG_ADAPT_RST_MODE : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_CTRL_REG1__CI__VI { - struct { - unsigned int RX_CFG_CDR_FR_GAIN_GEN1 : 4; - unsigned int RX_CFG_CDR_FR_GAIN_GEN2 : 4; - unsigned int RX_CFG_CDR_FR_GAIN_GEN3 : 4; - unsigned int RX_CFG_CDR_PH_GAIN_GEN1 : 4; - unsigned int RX_CFG_CDR_PH_GAIN_GEN2 : 4; - unsigned int RX_CFG_CDR_PH_GAIN_GEN3 : 4; - unsigned int RX_CFG_CDR_PI_STPSZ_GEN1 : 1; - unsigned int RX_CFG_CDR_PI_STPSZ_GEN2 : 1; - unsigned int RX_CFG_CDR_PI_STPSZ_GEN3 : 1; - unsigned int RX_CFG_LEQ_DCATTN_BYP_EN_GEN1 : 1; - unsigned int RX_CFG_LEQ_DCATTN_BYP_EN_GEN2 : 1; - unsigned int RX_CFG_LEQ_DCATTN_BYP_EN_GEN3 : 1; - unsigned int RX_ADAPT_HLD_ASRT_TO_DCLK_EN : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_CTRL_REG2__CI__VI { - struct { - unsigned int : 12; - unsigned int RX_CFG_CDR_TIME_GEN1 : 4; - unsigned int RX_CFG_CDR_TIME_GEN2 : 4; - unsigned int RX_CFG_CDR_TIME_GEN3 : 4; - unsigned int RX_CFG_LEQ_LOOP_GAIN_GEN1 : 2; - unsigned int RX_CFG_LEQ_LOOP_GAIN_GEN2 : 2; - unsigned int RX_CFG_LEQ_LOOP_GAIN_GEN3 : 2; - unsigned int RX_DCLK_EN_ASRT_TO_ADAPT_HLD : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_CTRL_REG3__CI__VI { - struct { - unsigned int RX_CFG_CDR_FR_EN_GEN1 : 1; - unsigned int RX_CFG_CDR_FR_EN_GEN2 : 1; - unsigned int RX_CFG_CDR_FR_EN_GEN3 : 1; - unsigned int RX_ADAPT_RST_MODE_GEN1__VI : 2; - unsigned int RX_ADAPT_RST_MODE_GEN2__VI : 2; - unsigned int RX_ADAPT_RST_MODE_GEN3__VI : 2; - unsigned int RX_ADAPT_RST_SUB_MODE__VI : 3; - unsigned int RX_L0_ENTRY_MODE_GEN1__VI : 2; - unsigned int RX_L0_ENTRY_MODE_GEN2__VI : 2; - unsigned int RX_L0_ENTRY_MODE_GEN3__VI : 2; - unsigned int : 2; - unsigned int RX_CFG_DFE_TIME_GEN1 : 4; - unsigned int RX_CFG_DFE_TIME_GEN2 : 4; - unsigned int RX_CFG_DFE_TIME_GEN3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_CTRL_REG4__CI__VI { - struct { - unsigned int RX_CFG_FOM_BER_GEN1 : 3; - unsigned int RX_CFG_FOM_BER_GEN2 : 3; - unsigned int RX_CFG_FOM_BER_GEN3 : 3; - unsigned int RX_CFG_LEQ_POLE_BYP_VAL_GEN1 : 3; - unsigned int RX_CFG_LEQ_POLE_BYP_VAL_GEN2 : 3; - unsigned int RX_CFG_LEQ_POLE_BYP_VAL_GEN3 : 3; - unsigned int : 2; - unsigned int RX_CFG_FOM_TIME_GEN1 : 4; - unsigned int RX_CFG_FOM_TIME_GEN2 : 4; - unsigned int RX_CFG_FOM_TIME_GEN3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_CTRL_REG5__CI__VI { - struct { - unsigned int RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 : 5; - unsigned int RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 : 5; - unsigned int RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 : 5; - unsigned int RX_CFG_LEQ_POLE_BYP_EN_GEN1 : 1; - unsigned int RX_CFG_LEQ_POLE_BYP_EN_GEN2 : 1; - unsigned int RX_CFG_LEQ_POLE_BYP_EN_GEN3 : 1; - unsigned int RX_CFG_LEQ_SHUNT_EN_GEN1 : 1; - unsigned int RX_CFG_LEQ_SHUNT_EN_GEN2 : 1; - unsigned int RX_CFG_LEQ_SHUNT_EN_GEN3 : 1; - unsigned int : 6; - unsigned int RX_CFG_TERM_MODE_GEN1 : 1; - unsigned int RX_CFG_TERM_MODE_GEN2 : 1; - unsigned int RX_CFG_TERM_MODE_GEN3 : 1; - unsigned int RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0 : 1; - unsigned int RX_ADAPT_AUX_PWRON_MODE__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_CTRL_REG6__CI__VI { - struct { - unsigned int RX_CFG_LEQ_TIME_GEN1 : 4; - unsigned int RX_CFG_LEQ_TIME_GEN2 : 4; - unsigned int RX_CFG_LEQ_TIME_GEN3 : 4; - unsigned int RX_CFG_OC_TIME_GEN1 : 4; - unsigned int RX_CFG_OC_TIME_GEN2 : 4; - unsigned int RX_CFG_OC_TIME_GEN3 : 4; - unsigned int RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0 : 1; - unsigned int : 1; - unsigned int RX_FRONTEND_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int RX_AUX_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__VI : 1; - unsigned int RX_ADAPT_HLD_L1_DLL_OFF__VI : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_CTRL_REG7__CI { - struct { - unsigned int RX_CFG_TH_LOOP_GAIN_GEN1 : 4; - unsigned int RX_CFG_TH_LOOP_GAIN_GEN2 : 4; - unsigned int RX_CFG_TH_LOOP_GAIN_GEN3 : 4; - unsigned int RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 : 1; - unsigned int RX_DCLK_EN_LUT_ENTRY_LS2 : 1; - unsigned int : 3; - unsigned int RX_DLL_PWRON_LUT_ENTRY_LS2 : 1; - unsigned int RX_CFG_DLL_CPI_SEL_GEN1 : 3; - unsigned int RX_CFG_DLL_CPI_SEL_GEN2 : 3; - unsigned int RX_CFG_DLL_CPI_SEL_GEN3 : 3; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN1 : 1; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN2 : 1; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN3 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_CTRL_REG7__VI { - struct { - unsigned int RX_CFG_TH_LOOP_GAIN_GEN1 : 4; - unsigned int RX_CFG_TH_LOOP_GAIN_GEN2 : 4; - unsigned int RX_CFG_TH_LOOP_GAIN_GEN3 : 4; - unsigned int RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 : 1; - unsigned int RX_DCLK_EN_LUT_ENTRY_LS2 : 1; - unsigned int RX_DCLK_EN_AFTER_DLL_LOCK : 1; - unsigned int : 1; - unsigned int RX_DLL_PWRON_LUT_ENTRY_PS3 : 1; - unsigned int RX_DLL_PWRON_LUT_ENTRY_PS2 : 1; - unsigned int RX_CFG_DLL_CPI_SEL_GEN1 : 3; - unsigned int RX_CFG_DLL_CPI_SEL_GEN2 : 3; - unsigned int RX_CFG_DLL_CPI_SEL_GEN3 : 3; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN1 : 1; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN2 : 1; - unsigned int RX_CFG_DLL_FLOCK_DISABLE_GEN3 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_CTRL_REG8__CI__VI { - struct { - unsigned int RX_DLL_LOCK_TIME__VI : 2; - unsigned int RX_DLL_SPEEDCHANGE_RESET_TIME__VI : 2; - unsigned int RX_DLL_PWRON_IN_RAMPDOWN__VI : 1; - unsigned int RX_FSM_L0S_IF_RX_RDY__VI : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_OVRD_REG0__CI__VI { - struct { - unsigned int RX_ADAPT_HLD_OVRD_VAL : 1; - unsigned int RX_ADAPT_HLD_OVRD_EN : 1; - unsigned int RX_ADAPT_RST_OVRD_VAL : 1; - unsigned int RX_ADAPT_RST_OVRD_EN : 1; - unsigned int : 2; - unsigned int RX_CFG_DCLK_DIV_OVRD_VAL : 2; - unsigned int RX_CFG_DCLK_DIV_OVRD_EN : 1; - unsigned int RX_CFG_DLL_FREQ_MODE_OVRD_VAL : 1; - unsigned int RX_CFG_DLL_FREQ_MODE_OVRD_EN : 1; - unsigned int RX_CFG_PLLCLK_SEL_OVRD_VAL : 1; - unsigned int RX_CFG_PLLCLK_SEL_OVRD_EN : 1; - unsigned int RX_CFG_RCLK_DIV_OVRD_VAL : 1; - unsigned int RX_CFG_RCLK_DIV_OVRD_EN : 1; - unsigned int RX_DCLK_EN_OVRD_VAL : 1; - unsigned int RX_DCLK_EN_OVRD_EN : 1; - unsigned int RX_DLL_PWRON_OVRD_VAL : 1; - unsigned int RX_DLL_PWRON_OVRD_EN : 1; - unsigned int RX_FRONTEND_PWRON_OVRD_VAL : 1; - unsigned int RX_FRONTEND_PWRON_OVRD_EN : 1; - unsigned int RX_IDLEDET_PWRON_OVRD_VAL : 1; - unsigned int RX_IDLEDET_PWRON_OVRD_EN : 1; - unsigned int RX_TERM_EN_OVRD_VAL : 1; - unsigned int RX_TERM_EN_OVRD_EN : 1; - unsigned int : 3; - unsigned int RX_AUX_PWRON_OVRD_VAL : 1; - unsigned int RX_AUX_PWRON_OVRD_EN : 1; - unsigned int RX_ADAPT_FOM_OVRD_VAL : 1; - unsigned int RX_ADAPT_FOM_OVRD_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_OVRD_REG1__CI__VI { - struct { - unsigned int RX_ADAPT_TRK_OVRD_VAL : 1; - unsigned int RX_ADAPT_TRK_OVRD_EN : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int IGNR_RXPWR_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_RXPWR_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_RXPWR_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_RXPWR_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_RXPRESETHINT_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_ENABLEFOM_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_ENABLEFOM_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_ENABLEFOM_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_ENABLEFOM_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_REQUESTFOM_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_REQUESTFOM_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_REQUESTFOM_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_REQUESTFOM_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_RESPONSEMODE_SCI_UPDT_L12T15 : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_GLB_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int IGNR_RXPWR_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_RXPWR_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_RXPWR_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_RXPWR_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_REQUESTTRK_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_REQUESTTRK_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_REQUESTTRK_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_REQUESTTRK_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_ENABLEFOM_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_ENABLEFOM_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_ENABLEFOM_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_ENABLEFOM_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_REQUESTFOM_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_REQUESTFOM_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_REQUESTFOM_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_REQUESTFOM_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_RESPONSEMODE_CBI_UPDT_L12T15 : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE0_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_0 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_0 : 2; - unsigned int RX_TST_BSCAN_EN_0 : 1; - unsigned int RX_CFG_OVR_PWRSF_0 : 1; - unsigned int RX_TERM_EN_0__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE0_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_0 : 3; - unsigned int ELECIDLEDETEN_0 : 1; - unsigned int RXPRESETHINT_0 : 3; - unsigned int ENABLEFOM_0 : 1; - unsigned int REQUESTFOM_0 : 1; - unsigned int RESPONSEMODE_0 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE0_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_0 : 3; - unsigned int ELECIDLEDETEN_0 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_0 : 1; - unsigned int ENABLEFOM_0 : 1; - unsigned int REQUESTFOM_0 : 1; - unsigned int RESPONSEMODE_0 : 1; - unsigned int RXEYEFOM_0 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE10_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_10 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_10 : 2; - unsigned int RX_TST_BSCAN_EN_10 : 1; - unsigned int RX_CFG_OVR_PWRSF_10 : 1; - unsigned int RX_TERM_EN_10__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE10_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_10 : 3; - unsigned int ELECIDLEDETEN_10 : 1; - unsigned int RXPRESETHINT_10 : 3; - unsigned int ENABLEFOM_10 : 1; - unsigned int REQUESTFOM_10 : 1; - unsigned int RESPONSEMODE_10 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE10_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_10 : 3; - unsigned int ELECIDLEDETEN_10 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_10 : 1; - unsigned int ENABLEFOM_10 : 1; - unsigned int REQUESTFOM_10 : 1; - unsigned int RESPONSEMODE_10 : 1; - unsigned int RXEYEFOM_10 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE11_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_11 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_11 : 2; - unsigned int RX_TST_BSCAN_EN_11 : 1; - unsigned int RX_CFG_OVR_PWRSF_11 : 1; - unsigned int RX_TERM_EN_11__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE11_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_11 : 3; - unsigned int ELECIDLEDETEN_11 : 1; - unsigned int RXPRESETHINT_11 : 3; - unsigned int ENABLEFOM_11 : 1; - unsigned int REQUESTFOM_11 : 1; - unsigned int RESPONSEMODE_11 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE11_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_11 : 3; - unsigned int ELECIDLEDETEN_11 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_11 : 1; - unsigned int ENABLEFOM_11 : 1; - unsigned int REQUESTFOM_11 : 1; - unsigned int RESPONSEMODE_11 : 1; - unsigned int RXEYEFOM_11 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE12_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_12 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_12 : 2; - unsigned int RX_TST_BSCAN_EN_12 : 1; - unsigned int RX_CFG_OVR_PWRSF_12 : 1; - unsigned int RX_TERM_EN_12__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE12_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_12 : 3; - unsigned int ELECIDLEDETEN_12 : 1; - unsigned int RXPRESETHINT_12 : 3; - unsigned int ENABLEFOM_12 : 1; - unsigned int REQUESTFOM_12 : 1; - unsigned int RESPONSEMODE_12 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE12_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_12 : 3; - unsigned int ELECIDLEDETEN_12 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_12 : 1; - unsigned int ENABLEFOM_12 : 1; - unsigned int REQUESTFOM_12 : 1; - unsigned int RESPONSEMODE_12 : 1; - unsigned int RXEYEFOM_12 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE13_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_13 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_13 : 2; - unsigned int RX_TST_BSCAN_EN_13 : 1; - unsigned int RX_CFG_OVR_PWRSF_13 : 1; - unsigned int RX_TERM_EN_13__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE13_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_13 : 3; - unsigned int ELECIDLEDETEN_13 : 1; - unsigned int RXPRESETHINT_13 : 3; - unsigned int ENABLEFOM_13 : 1; - unsigned int REQUESTFOM_13 : 1; - unsigned int RESPONSEMODE_13 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE13_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_13 : 3; - unsigned int ELECIDLEDETEN_13 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_13 : 1; - unsigned int ENABLEFOM_13 : 1; - unsigned int REQUESTFOM_13 : 1; - unsigned int RESPONSEMODE_13 : 1; - unsigned int RXEYEFOM_13 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE14_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_14 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_14 : 2; - unsigned int RX_TST_BSCAN_EN_14 : 1; - unsigned int RX_CFG_OVR_PWRSF_14 : 1; - unsigned int RX_TERM_EN_14__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE14_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_14 : 3; - unsigned int ELECIDLEDETEN_14 : 1; - unsigned int RXPRESETHINT_14 : 3; - unsigned int ENABLEFOM_14 : 1; - unsigned int REQUESTFOM_14 : 1; - unsigned int RESPONSEMODE_14 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE14_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_14 : 3; - unsigned int ELECIDLEDETEN_14 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_14 : 1; - unsigned int ENABLEFOM_14 : 1; - unsigned int REQUESTFOM_14 : 1; - unsigned int RESPONSEMODE_14 : 1; - unsigned int RXEYEFOM_14 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE15_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_15 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_15 : 2; - unsigned int RX_TST_BSCAN_EN_15 : 1; - unsigned int RX_CFG_OVR_PWRSF_15 : 1; - unsigned int RX_TERM_EN_15__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE15_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_15 : 3; - unsigned int ELECIDLEDETEN_15 : 1; - unsigned int RXPRESETHINT_15 : 3; - unsigned int ENABLEFOM_15 : 1; - unsigned int REQUESTFOM_15 : 1; - unsigned int RESPONSEMODE_15 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE15_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_15 : 3; - unsigned int ELECIDLEDETEN_15 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_15 : 1; - unsigned int ENABLEFOM_15 : 1; - unsigned int REQUESTFOM_15 : 1; - unsigned int RESPONSEMODE_15 : 1; - unsigned int RXEYEFOM_15 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE1_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_1 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_1 : 2; - unsigned int RX_TST_BSCAN_EN_1 : 1; - unsigned int RX_CFG_OVR_PWRSF_1 : 1; - unsigned int RX_TERM_EN_1__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE1_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_1 : 3; - unsigned int ELECIDLEDETEN_1 : 1; - unsigned int RXPRESETHINT_1 : 3; - unsigned int ENABLEFOM_1 : 1; - unsigned int REQUESTFOM_1 : 1; - unsigned int RESPONSEMODE_1 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE1_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_1 : 3; - unsigned int ELECIDLEDETEN_1 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_1 : 1; - unsigned int ENABLEFOM_1 : 1; - unsigned int REQUESTFOM_1 : 1; - unsigned int RESPONSEMODE_1 : 1; - unsigned int RXEYEFOM_1 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE2_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_2 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_2 : 2; - unsigned int RX_TST_BSCAN_EN_2 : 1; - unsigned int RX_CFG_OVR_PWRSF_2 : 1; - unsigned int RX_TERM_EN_2__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE2_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_2 : 3; - unsigned int ELECIDLEDETEN_2 : 1; - unsigned int RXPRESETHINT_2 : 3; - unsigned int ENABLEFOM_2 : 1; - unsigned int REQUESTFOM_2 : 1; - unsigned int RESPONSEMODE_2 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE2_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_2 : 3; - unsigned int ELECIDLEDETEN_2 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_2 : 1; - unsigned int ENABLEFOM_2 : 1; - unsigned int REQUESTFOM_2 : 1; - unsigned int RESPONSEMODE_2 : 1; - unsigned int RXEYEFOM_2 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE3_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_3 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_3 : 2; - unsigned int RX_TST_BSCAN_EN_3 : 1; - unsigned int RX_CFG_OVR_PWRSF_3 : 1; - unsigned int RX_TERM_EN_3__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE3_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_3 : 3; - unsigned int ELECIDLEDETEN_3 : 1; - unsigned int RXPRESETHINT_3 : 3; - unsigned int ENABLEFOM_3 : 1; - unsigned int REQUESTFOM_3 : 1; - unsigned int RESPONSEMODE_3 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE3_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_3 : 3; - unsigned int ELECIDLEDETEN_3 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_3 : 1; - unsigned int ENABLEFOM_3 : 1; - unsigned int REQUESTFOM_3 : 1; - unsigned int RESPONSEMODE_3 : 1; - unsigned int RXEYEFOM_3 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE4_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_4 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_4 : 2; - unsigned int RX_TST_BSCAN_EN_4 : 1; - unsigned int RX_CFG_OVR_PWRSF_4 : 1; - unsigned int RX_TERM_EN_4__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE4_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_4 : 3; - unsigned int ELECIDLEDETEN_4 : 1; - unsigned int RXPRESETHINT_4 : 3; - unsigned int ENABLEFOM_4 : 1; - unsigned int REQUESTFOM_4 : 1; - unsigned int RESPONSEMODE_4 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE4_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_4 : 3; - unsigned int ELECIDLEDETEN_4 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_4 : 1; - unsigned int ENABLEFOM_4 : 1; - unsigned int REQUESTFOM_4 : 1; - unsigned int RESPONSEMODE_4 : 1; - unsigned int RXEYEFOM_4 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE5_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_5 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_5 : 2; - unsigned int RX_TST_BSCAN_EN_5 : 1; - unsigned int RX_CFG_OVR_PWRSF_5 : 1; - unsigned int RX_TERM_EN_5__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE5_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_5 : 3; - unsigned int ELECIDLEDETEN_5 : 1; - unsigned int RXPRESETHINT_5 : 3; - unsigned int ENABLEFOM_5 : 1; - unsigned int REQUESTFOM_5 : 1; - unsigned int RESPONSEMODE_5 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE5_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_5 : 3; - unsigned int ELECIDLEDETEN_5 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_5 : 1; - unsigned int ENABLEFOM_5 : 1; - unsigned int REQUESTFOM_5 : 1; - unsigned int RESPONSEMODE_5 : 1; - unsigned int RXEYEFOM_5 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE6_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_6 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_6 : 2; - unsigned int RX_TST_BSCAN_EN_6 : 1; - unsigned int RX_CFG_OVR_PWRSF_6 : 1; - unsigned int RX_TERM_EN_6__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE6_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_6 : 3; - unsigned int ELECIDLEDETEN_6 : 1; - unsigned int RXPRESETHINT_6 : 3; - unsigned int ENABLEFOM_6 : 1; - unsigned int REQUESTFOM_6 : 1; - unsigned int RESPONSEMODE_6 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE6_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_6 : 3; - unsigned int ELECIDLEDETEN_6 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_6 : 1; - unsigned int ENABLEFOM_6 : 1; - unsigned int REQUESTFOM_6 : 1; - unsigned int RESPONSEMODE_6 : 1; - unsigned int RXEYEFOM_6 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE7_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_7 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_7 : 2; - unsigned int RX_TST_BSCAN_EN_7 : 1; - unsigned int RX_CFG_OVR_PWRSF_7 : 1; - unsigned int RX_TERM_EN_7__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE7_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_7 : 3; - unsigned int ELECIDLEDETEN_7 : 1; - unsigned int RXPRESETHINT_7 : 3; - unsigned int ENABLEFOM_7 : 1; - unsigned int REQUESTFOM_7 : 1; - unsigned int RESPONSEMODE_7 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE7_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_7 : 3; - unsigned int ELECIDLEDETEN_7 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_7 : 1; - unsigned int ENABLEFOM_7 : 1; - unsigned int REQUESTFOM_7 : 1; - unsigned int RESPONSEMODE_7 : 1; - unsigned int RXEYEFOM_7 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE8_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_8 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_8 : 2; - unsigned int RX_TST_BSCAN_EN_8 : 1; - unsigned int RX_CFG_OVR_PWRSF_8 : 1; - unsigned int RX_TERM_EN_8__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE8_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_8 : 3; - unsigned int ELECIDLEDETEN_8 : 1; - unsigned int RXPRESETHINT_8 : 3; - unsigned int ENABLEFOM_8 : 1; - unsigned int REQUESTFOM_8 : 1; - unsigned int RESPONSEMODE_8 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE8_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_8 : 3; - unsigned int ELECIDLEDETEN_8 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_8 : 1; - unsigned int ENABLEFOM_8 : 1; - unsigned int REQUESTFOM_8 : 1; - unsigned int RESPONSEMODE_8 : 1; - unsigned int RXEYEFOM_8 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE9_CTRL_REG0__CI__VI { - struct { - unsigned int RX_BACKUP_9 : 8; - unsigned int : 2; - unsigned int RX_DBG_ANALOG_SEL_9 : 2; - unsigned int RX_TST_BSCAN_EN_9 : 1; - unsigned int RX_CFG_OVR_PWRSF_9 : 1; - unsigned int RX_TERM_EN_9__VI : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE9_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int RXPWR_9 : 3; - unsigned int ELECIDLEDETEN_9 : 1; - unsigned int RXPRESETHINT_9 : 3; - unsigned int ENABLEFOM_9 : 1; - unsigned int REQUESTFOM_9 : 1; - unsigned int RESPONSEMODE_9 : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_RX_LANE9_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int RXPWR_9 : 3; - unsigned int ELECIDLEDETEN_9 : 1; - unsigned int : 2; - unsigned int REQUESTTRK_9 : 1; - unsigned int ENABLEFOM_9 : 1; - unsigned int REQUESTFOM_9 : 1; - unsigned int RESPONSEMODE_9 : 1; - unsigned int RXEYEFOM_9 : 8; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_STRAP_GLB_REG0__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_QUICK_SIM_START : 1; - unsigned int STRAP_DFT_RXBSCAN_EN_VAL : 1; - unsigned int STRAP_DFT_CALIB_BYPASS : 1; - unsigned int STRAP_FORCE_LC_PLL_ON__VI : 1; - unsigned int STRAP_CFG_IDLEDET_TH : 2; - unsigned int STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL : 5; - unsigned int STRAP_RX_CFG_OVR_PWRSF : 1; - unsigned int STRAP_RX_TRK_MODE_0_ : 1; - unsigned int STRAP_PWRGOOD_OVRD : 1; - unsigned int STRAP_DBG_RXDLL_VREG_REF_SEL : 1; - unsigned int STRAP_PLL_CFG_LC_VCO_TUNE : 4; - unsigned int STRAP_DBG_RXRDATA_GATING_DISABLE : 1; - unsigned int STRAP_DBG_RXPI_OFFSET_BYP_VAL : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_STRAP_PIN_REG0__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_TX_DEEMPH_EN : 1; - unsigned int STRAP_TX_FULL_SWING : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_STRAP_PLL_REG0__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_PLL_CFG_LC_BW_CNTRL : 3; - unsigned int STRAP_PLL_CFG_LC_LF_CNTRL : 9; - unsigned int STRAP_TX_RXDET_X1_SSF : 1; - unsigned int : 1; - unsigned int STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS : 1; - unsigned int STRAP_PLL_CFG_RO_BW_CNTRL : 8; - unsigned int STRAP_PLL_STRAP_SEL : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_STRAP_RX_REG0__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_RX_CFG_TH_LOOP_GAIN : 4; - unsigned int STRAP_RX_CFG_DLL_FLOCK_DISABLE : 1; - unsigned int STRAP_DBG_RXPI_OFFSET_BYP_EN : 1; - unsigned int STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS : 1; - unsigned int STRAP_BG_CFG_LC_REG_VREF0_SEL : 2; - unsigned int STRAP_BG_CFG_LC_REG_VREF1_SEL : 2; - unsigned int STRAP_RX_CFG_CDR_TIME : 4; - unsigned int STRAP_RX_CFG_FOM_TIME : 4; - unsigned int STRAP_RX_CFG_LEQ_TIME : 4; - unsigned int STRAP_RX_CFG_OC_TIME : 4; - unsigned int STRAP_TX_CFG_RPTR_RST_VAL : 3; - unsigned int STRAP_RX_CFG_TERM_MODE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_STRAP_RX_REG1__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_RX_CFG_CDR_PI_STPSZ : 1; - unsigned int STRAP_TX_DEEMPH_PRSHT_STNG : 3; - unsigned int STRAP_BG_CFG_RO_REG_VREF_SEL : 2; - unsigned int STRAP_RX_CFG_LEQ_POLE_BYP_DIS : 1; - unsigned int STRAP_RX_CFG_LEQ_POLE_BYP_VAL : 3; - unsigned int STRAP_RX_CFG_CDR_PH_GAIN : 4; - unsigned int STRAP_RX_CFG_ADAPT_MODE : 10; - unsigned int STRAP_RX_CFG_DFE_TIME : 4; - unsigned int STRAP_RX_CFG_LEQ_LOOP_GAIN : 2; - unsigned int STRAP_RX_CFG_LEQ_SHUNT_DIS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_STRAP_TX_REG0__CI__VI { - struct { - unsigned int : 1; - unsigned int STRAP_TX_CFG_DRV0_EN : 4; - unsigned int STRAP_TX_CFG_DRV0_TAP_SEL : 4; - unsigned int STRAP_TX_CFG_DRV1_EN : 5; - unsigned int STRAP_TX_CFG_DRV1_TAP_SEL : 5; - unsigned int STRAP_TX_CFG_DRV2_EN : 4; - unsigned int STRAP_TX_CFG_DRV2_TAP_SEL : 4; - unsigned int STRAP_TX_CFG_DRVX_EN : 1; - unsigned int STRAP_TX_CFG_DRVX_TAP_SEL : 1; - unsigned int STRAP_RX_TRK_MODE_1_ : 1; - unsigned int STRAP_TX_CFG_SWING_BOOST_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI { - struct { - unsigned int ACCEPT_ENTRY_0 : 1; - unsigned int ACCEPT_ENTRY_1 : 1; - unsigned int ACCEPT_ENTRY_2 : 1; - unsigned int ACCEPT_ENTRY_3 : 1; - unsigned int ACCEPT_ENTRY_4 : 1; - unsigned int ACCEPT_ENTRY_5 : 1; - unsigned int ACCEPT_ENTRY_6 : 1; - unsigned int ACCEPT_ENTRY_7 : 1; - unsigned int ACCEPT_ENTRY_8 : 1; - unsigned int ACCEPT_ENTRY_9 : 1; - unsigned int ACCEPT_ENTRY_10 : 1; - unsigned int ACCEPT_ENTRY_11 : 1; - unsigned int ACCEPT_ENTRY_12 : 1; - unsigned int ACCEPT_ENTRY_13 : 1; - unsigned int ACCEPT_ENTRY_14 : 1; - unsigned int ACCEPT_ENTRY_15 : 1; - unsigned int ACCEPT_ENTRY_16 : 1; - unsigned int ACCEPT_ENTRY_17 : 1; - unsigned int ACCEPT_ENTRY_18 : 1; - unsigned int ACCEPT_ENTRY_19 : 1; - unsigned int ACCEPT_ENTRY_20 : 1; - unsigned int ACCEPT_ENTRY_21 : 1; - unsigned int ACCEPT_ENTRY_22 : 1; - unsigned int ACCEPT_ENTRY_23 : 1; - unsigned int ACCEPT_ENTRY_24 : 1; - unsigned int ACCEPT_ENTRY_25 : 1; - unsigned int ACCEPT_ENTRY_26 : 1; - unsigned int ACCEPT_ENTRY_27 : 1; - unsigned int ACCEPT_ENTRY_28 : 1; - unsigned int ACCEPT_ENTRY_29 : 1; - unsigned int ACCEPT_ENTRY_30 : 1; - unsigned int ACCEPT_ENTRY_31 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI { - struct { - unsigned int ACCEPT_ENTRY_32 : 1; - unsigned int ACCEPT_ENTRY_33 : 1; - unsigned int ACCEPT_ENTRY_34 : 1; - unsigned int ACCEPT_ENTRY_35 : 1; - unsigned int ACCEPT_ENTRY_36 : 1; - unsigned int ACCEPT_ENTRY_37 : 1; - unsigned int ACCEPT_ENTRY_38 : 1; - unsigned int ACCEPT_ENTRY_39 : 1; - unsigned int ACCEPT_ENTRY_40 : 1; - unsigned int ACCEPT_ENTRY_41 : 1; - unsigned int ACCEPT_ENTRY_42 : 1; - unsigned int ACCEPT_ENTRY_43 : 1; - unsigned int ACCEPT_ENTRY_44 : 1; - unsigned int ACCEPT_ENTRY_45 : 1; - unsigned int ACCEPT_ENTRY_46 : 1; - unsigned int ACCEPT_ENTRY_47 : 1; - unsigned int ACCEPT_ENTRY_48 : 1; - unsigned int ACCEPT_ENTRY_49 : 1; - unsigned int ACCEPT_ENTRY_50 : 1; - unsigned int ACCEPT_ENTRY_51 : 1; - unsigned int ACCEPT_ENTRY_52 : 1; - unsigned int ACCEPT_ENTRY_53 : 1; - unsigned int ACCEPT_ENTRY_54 : 1; - unsigned int ACCEPT_ENTRY_55 : 1; - unsigned int ACCEPT_ENTRY_56 : 1; - unsigned int ACCEPT_ENTRY_57 : 1; - unsigned int ACCEPT_ENTRY_58 : 1; - unsigned int ACCEPT_ENTRY_59 : 1; - unsigned int ACCEPT_ENTRY_60 : 1; - unsigned int ACCEPT_ENTRY_61 : 1; - unsigned int ACCEPT_ENTRY_62 : 1; - unsigned int ACCEPT_ENTRY_63 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI { - struct { - unsigned int ACCEPT_ENTRY_64 : 1; - unsigned int ACCEPT_ENTRY_65 : 1; - unsigned int ACCEPT_ENTRY_66 : 1; - unsigned int ACCEPT_ENTRY_67 : 1; - unsigned int ACCEPT_ENTRY_68 : 1; - unsigned int ACCEPT_ENTRY_69 : 1; - unsigned int ACCEPT_ENTRY_70 : 1; - unsigned int ACCEPT_ENTRY_71 : 1; - unsigned int ACCEPT_ENTRY_72 : 1; - unsigned int ACCEPT_ENTRY_73 : 1; - unsigned int ACCEPT_ENTRY_74 : 1; - unsigned int ACCEPT_ENTRY_75 : 1; - unsigned int ACCEPT_ENTRY_76 : 1; - unsigned int ACCEPT_ENTRY_77 : 1; - unsigned int ACCEPT_ENTRY_78 : 1; - unsigned int ACCEPT_ENTRY_79 : 1; - unsigned int ACCEPT_ENTRY_80 : 1; - unsigned int ACCEPT_ENTRY_81 : 1; - unsigned int ACCEPT_ENTRY_82 : 1; - unsigned int ACCEPT_ENTRY_83 : 1; - unsigned int ACCEPT_ENTRY_84 : 1; - unsigned int ACCEPT_ENTRY_85 : 1; - unsigned int ACCEPT_ENTRY_86 : 1; - unsigned int ACCEPT_ENTRY_87 : 1; - unsigned int ACCEPT_ENTRY_88 : 1; - unsigned int ACCEPT_ENTRY_89 : 1; - unsigned int ACCEPT_ENTRY_90 : 1; - unsigned int ACCEPT_ENTRY_91 : 1; - unsigned int ACCEPT_ENTRY_92 : 1; - unsigned int ACCEPT_ENTRY_93 : 1; - unsigned int ACCEPT_ENTRY_94 : 1; - unsigned int ACCEPT_ENTRY_95 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI { - struct { - unsigned int ACCEPT_ENTRY_96 : 1; - unsigned int ACCEPT_ENTRY_97 : 1; - unsigned int ACCEPT_ENTRY_98 : 1; - unsigned int ACCEPT_ENTRY_99 : 1; - unsigned int ACCEPT_ENTRY_100 : 1; - unsigned int ACCEPT_ENTRY_101 : 1; - unsigned int ACCEPT_ENTRY_102 : 1; - unsigned int ACCEPT_ENTRY_103 : 1; - unsigned int ACCEPT_ENTRY_104 : 1; - unsigned int ACCEPT_ENTRY_105 : 1; - unsigned int ACCEPT_ENTRY_106 : 1; - unsigned int ACCEPT_ENTRY_107 : 1; - unsigned int ACCEPT_ENTRY_108 : 1; - unsigned int ACCEPT_ENTRY_109 : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_CTRL_REG0__CI { - struct { - unsigned int TX_DRV_DATA_ASRT_DLY_VAL : 3; - unsigned int TX_DRV_DATA_DSRT_DLY_VAL : 3; - unsigned int : 2; - unsigned int TX_CFG_RPTR_RST_VAL_GEN1 : 3; - unsigned int TX_CFG_RPTR_RST_VAL_GEN2 : 3; - unsigned int TX_CFG_RPTR_RST_VAL_GEN3 : 3; - unsigned int TX_STAGGER_CTRL : 2; - unsigned int TX_DATA_CLK_GATING : 1; - unsigned int TX_PRESET_TABLE_BYPASS : 1; - unsigned int TX_COEFF_ROUND_EN : 1; - unsigned int TX_COEFF_ROUND_DIR_VER : 1; - unsigned int TX_DCLK_EN_LSX_ALWAYS_ON : 1; - unsigned int TX_FRONTEND_PWRON_IN_OFF : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_CTRL_REG0__VI { - struct { - unsigned int TX_DRV_DATA_ASRT_DLY_VAL : 3; - unsigned int TX_DRV_DATA_DSRT_DLY_VAL : 3; - unsigned int : 2; - unsigned int TX_CFG_RPTR_RST_VAL_GEN1 : 3; - unsigned int TX_CFG_RPTR_RST_VAL_GEN2 : 3; - unsigned int TX_CFG_RPTR_RST_VAL_GEN3 : 3; - unsigned int TX_STAGGER_CTRL : 2; - unsigned int TX_DATA_CLK_GATING : 1; - unsigned int TX_PRESET_TABLE_BYPASS : 1; - unsigned int TX_COEFF_ROUND_EN : 1; - unsigned int TX_COEFF_ROUND_DIR_VER : 1; - unsigned int TX_DCLK_EN_LSX_ALWAYS_ON : 1; - unsigned int TX_FRONTEND_PWRON_IN_PS4 : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_LANE_SKEW_CTRL__CI__VI { - struct { - unsigned int TX_CFG_GROUPX1_EN_0 : 1; - unsigned int TX_CFG_GROUPX1_EN_1 : 1; - unsigned int TX_CFG_GROUPX1_EN_2 : 1; - unsigned int TX_CFG_GROUPX1_EN_3 : 1; - unsigned int TX_CFG_GROUPX1_EN_4 : 1; - unsigned int TX_CFG_GROUPX1_EN_5 : 1; - unsigned int TX_CFG_GROUPX1_EN_6 : 1; - unsigned int TX_CFG_GROUPX1_EN_7 : 1; - unsigned int TX_CFG_GROUPX1_EN_8 : 1; - unsigned int TX_CFG_GROUPX1_EN_9 : 1; - unsigned int TX_CFG_GROUPX1_EN_10 : 1; - unsigned int TX_CFG_GROUPX1_EN_11 : 1; - unsigned int TX_CFG_GROUPX1_EN_12 : 1; - unsigned int TX_CFG_GROUPX1_EN_13 : 1; - unsigned int TX_CFG_GROUPX1_EN_14 : 1; - unsigned int TX_CFG_GROUPX1_EN_15 : 1; - unsigned int TX_CFG_GROUPX2_EN_L0T1 : 1; - unsigned int TX_CFG_GROUPX2_EN_L2T3 : 1; - unsigned int TX_CFG_GROUPX2_EN_L4T5 : 1; - unsigned int TX_CFG_GROUPX2_EN_L6T7 : 1; - unsigned int TX_CFG_GROUPX2_EN_L8T9 : 1; - unsigned int TX_CFG_GROUPX2_EN_L10T11 : 1; - unsigned int TX_CFG_GROUPX2_EN_L12T13 : 1; - unsigned int TX_CFG_GROUPX2_EN_L14T15 : 1; - unsigned int TX_CFG_GROUPX4_EN_L0T3 : 1; - unsigned int TX_CFG_GROUPX4_EN_L4T7 : 1; - unsigned int TX_CFG_GROUPX4_EN_L8T11 : 1; - unsigned int TX_CFG_GROUPX4_EN_L12T15 : 1; - unsigned int TX_CFG_GROUPX8_EN_L0T7 : 1; - unsigned int TX_CFG_GROUPX8_EN_L8T15 : 1; - unsigned int TX_CFG_GROUPX16_EN_L0T15 : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_OVRD_REG0__CI__VI { - struct { - unsigned int TX_CFG_DCLK_DIV_OVRD_VAL : 3; - unsigned int TX_CFG_DCLK_DIV_OVRD_EN : 1; - unsigned int TX_CFG_DRV0_EN_GEN1_OVRD_VAL : 4; - unsigned int TX_CFG_DRV0_EN_OVRD_EN : 1; - unsigned int TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL : 4; - unsigned int TX_CFG_DRV0_TAP_SEL_OVRD_EN : 1; - unsigned int TX_CFG_DRV1_EN_GEN1_OVRD_VAL : 5; - unsigned int TX_CFG_DRV1_EN_OVRD_EN : 1; - unsigned int TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL : 5; - unsigned int TX_CFG_DRV1_TAP_SEL_OVRD_EN : 1; - unsigned int TX_CFG_DRV2_EN_GEN1_OVRD_VAL : 4; - unsigned int TX_CFG_DRV2_EN_OVRD_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_OVRD_REG1__CI__VI { - struct { - unsigned int TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL : 4; - unsigned int TX_CFG_DRV2_TAP_SEL_OVRD_EN : 1; - unsigned int TX_CFG_DRVX_EN_GEN1_OVRD_VAL : 1; - unsigned int TX_CFG_DRVX_EN_OVRD_EN : 1; - unsigned int TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL : 1; - unsigned int TX_CFG_DRVX_TAP_SEL_OVRD_EN : 1; - unsigned int TX_CFG_PLLCLK_SEL_OVRD_VAL : 1; - unsigned int TX_CFG_PLLCLK_SEL_OVRD_EN : 1; - unsigned int TX_CFG_TCLK_DIV_OVRD_VAL : 1; - unsigned int TX_CFG_TCLK_DIV_OVRD_EN : 1; - unsigned int TX_CMDET_EN_OVRD_VAL : 1; - unsigned int TX_CMDET_EN_OVRD_EN : 1; - unsigned int TX_DATA_IN_OVRD_VAL : 10; - unsigned int TX_DATA_IN_OVRD_EN : 1; - unsigned int TX_RPTR_RSTN_OVRD_VAL : 1; - unsigned int TX_RPTR_RSTN_OVRD_EN : 1; - unsigned int TX_RXDET_EN_OVRD_VAL : 1; - unsigned int TX_RXDET_EN_OVRD_EN : 1; - unsigned int TX_WPTR_RSTN_OVRD_VAL : 1; - unsigned int TX_WPTR_RSTN_OVRD_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_OVRD_REG2__CI__VI { - struct { - unsigned int TX_WRITE_EN_OVRD_VAL : 1; - unsigned int TX_WRITE_EN_OVRD_EN : 1; - unsigned int TX_CFG_GROUPX1_EN_OVRD_VAL : 1; - unsigned int TX_CFG_GROUPX1_EN_OVRD_EN : 1; - unsigned int TX_CFG_GROUPX2_EN_OVRD_VAL : 1; - unsigned int TX_CFG_GROUPX2_EN_OVRD_EN : 1; - unsigned int TX_CFG_GROUPX4_EN_OVRD_VAL : 1; - unsigned int TX_CFG_GROUPX4_EN_OVRD_EN : 1; - unsigned int TX_CFG_GROUPX8_EN_OVRD_VAL : 1; - unsigned int TX_CFG_GROUPX8_EN_OVRD_EN : 1; - unsigned int TX_CFG_GROUPX16_EN_OVRD_VAL : 1; - unsigned int TX_CFG_GROUPX16_EN_OVRD_EN : 1; - unsigned int TX_CFG_DRV0_EN_GEN2_OVRD_VAL : 4; - unsigned int TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL : 4; - unsigned int TX_CFG_DRV1_EN_GEN2_OVRD_VAL : 5; - unsigned int TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL : 5; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_OVRD_REG3__CI__VI { - struct { - unsigned int TX_CFG_DRV2_EN_GEN2_OVRD_VAL : 4; - unsigned int TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL : 4; - unsigned int TX_CFG_DRVX_EN_GEN2_OVRD_VAL : 1; - unsigned int TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL : 1; - unsigned int TX_CFG_DRV0_EN_GEN3_OVRD_VAL : 4; - unsigned int TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL : 4; - unsigned int TX_CFG_DRV1_EN_GEN3_OVRD_VAL : 5; - unsigned int TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL : 5; - unsigned int TX_CFG_DRV2_EN_GEN3_OVRD_VAL : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_OVRD_REG4__CI__VI { - struct { - unsigned int TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL : 4; - unsigned int TX_CFG_DRVX_EN_GEN3_OVRD_VAL : 1; - unsigned int TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_SCI_STAT_OVRD_REG0__CI { - struct { - unsigned int IGNR_TXPWR_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_TXPWR_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_TXPWR_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_TXPWR_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_INCOHERENTCK_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_COEFFICIENTID_SCI_UPDT_L12T15 : 1; - unsigned int IGNR_COEFFICIENT_SCI_UPDT_L0T3 : 1; - unsigned int IGNR_COEFFICIENT_SCI_UPDT_L4T7 : 1; - unsigned int IGNR_COEFFICIENT_SCI_UPDT_L8T11 : 1; - unsigned int IGNR_COEFFICIENT_SCI_UPDT_L12T15 : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_GLB_SCI_STAT_OVRD_REG0__VI { - struct { - unsigned int IGNR_TXPWR_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_TXPWR_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_TXPWR_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_TXPWR_CBI_UPDT_L12T15 : 1; - unsigned int : 4; - unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_COEFFICIENTID_CBI_UPDT_L12T15 : 1; - unsigned int IGNR_COEFFICIENT_CBI_UPDT_L0T3 : 1; - unsigned int IGNR_COEFFICIENT_CBI_UPDT_L4T7 : 1; - unsigned int IGNR_COEFFICIENT_CBI_UPDT_L8T11 : 1; - unsigned int IGNR_COEFFICIENT_CBI_UPDT_L12T15 : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE0_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_0 : 1; - unsigned int TX_CFG_INV_DATA_0 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_0 : 1; - unsigned int TX_DBG_PRBS_EN_0 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE0_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_0 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_0 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_0 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_0 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_0 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_0 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_0 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_0 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_0 : 3; - unsigned int INCOHERENTCK_0__SI__CI : 1; - unsigned int TXMARG_0 : 3; - unsigned int DEEMPH_0 : 1; - unsigned int COEFFICIENTID_0 : 2; - unsigned int COEFFICIENT_0 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE10_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_10 : 1; - unsigned int TX_CFG_INV_DATA_10 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_10 : 1; - unsigned int TX_DBG_PRBS_EN_10 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE10_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_10 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_10 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_10 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_10 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_10 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_10 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_10 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_10 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_10 : 3; - unsigned int INCOHERENTCK_10__SI__CI : 1; - unsigned int TXMARG_10 : 3; - unsigned int DEEMPH_10 : 1; - unsigned int COEFFICIENTID_10 : 2; - unsigned int COEFFICIENT_10 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE11_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_11 : 1; - unsigned int TX_CFG_INV_DATA_11 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_11 : 1; - unsigned int TX_DBG_PRBS_EN_11 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE11_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_11 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_11 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_11 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_11 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_11 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_11 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_11 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_11 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_11 : 3; - unsigned int INCOHERENTCK_11__SI__CI : 1; - unsigned int TXMARG_11 : 3; - unsigned int DEEMPH_11 : 1; - unsigned int COEFFICIENTID_11 : 2; - unsigned int COEFFICIENT_11 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE12_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_12 : 1; - unsigned int TX_CFG_INV_DATA_12 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_12 : 1; - unsigned int TX_DBG_PRBS_EN_12 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE12_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_12 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_12 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_12 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_12 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_12 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_12 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_12 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_12 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_12 : 3; - unsigned int INCOHERENTCK_12__SI__CI : 1; - unsigned int TXMARG_12 : 3; - unsigned int DEEMPH_12 : 1; - unsigned int COEFFICIENTID_12 : 2; - unsigned int COEFFICIENT_12 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE13_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_13 : 1; - unsigned int TX_CFG_INV_DATA_13 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_13 : 1; - unsigned int TX_DBG_PRBS_EN_13 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE13_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_13 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_13 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_13 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_13 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_13 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_13 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_13 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_13 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_13 : 3; - unsigned int INCOHERENTCK_13__SI__CI : 1; - unsigned int TXMARG_13 : 3; - unsigned int DEEMPH_13 : 1; - unsigned int COEFFICIENTID_13 : 2; - unsigned int COEFFICIENT_13 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE14_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_14 : 1; - unsigned int TX_CFG_INV_DATA_14 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_14 : 1; - unsigned int TX_DBG_PRBS_EN_14 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE14_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_14 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_14 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_14 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_14 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_14 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_14 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_14 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_14 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_14 : 3; - unsigned int INCOHERENTCK_14__SI__CI : 1; - unsigned int TXMARG_14 : 3; - unsigned int DEEMPH_14 : 1; - unsigned int COEFFICIENTID_14 : 2; - unsigned int COEFFICIENT_14 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE15_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_15 : 1; - unsigned int TX_CFG_INV_DATA_15 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_15 : 1; - unsigned int TX_DBG_PRBS_EN_15 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE15_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_15 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_15 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_15 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_15 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_15 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_15 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_15 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_15 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_15 : 3; - unsigned int INCOHERENTCK_15__SI__CI : 1; - unsigned int TXMARG_15 : 3; - unsigned int DEEMPH_15 : 1; - unsigned int COEFFICIENTID_15 : 2; - unsigned int COEFFICIENT_15 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE1_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_1 : 1; - unsigned int TX_CFG_INV_DATA_1 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_1 : 1; - unsigned int TX_DBG_PRBS_EN_1 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE1_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_1 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_1 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_1 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_1 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_1 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_1 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_1 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_1 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_1 : 3; - unsigned int INCOHERENTCK_1__SI__CI : 1; - unsigned int TXMARG_1 : 3; - unsigned int DEEMPH_1 : 1; - unsigned int COEFFICIENTID_1 : 2; - unsigned int COEFFICIENT_1 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE2_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_2 : 1; - unsigned int TX_CFG_INV_DATA_2 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_2 : 1; - unsigned int TX_DBG_PRBS_EN_2 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE2_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_2 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_2 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_2 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_2 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_2 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_2 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_2 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_2 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_2 : 3; - unsigned int INCOHERENTCK_2__SI__CI : 1; - unsigned int TXMARG_2 : 3; - unsigned int DEEMPH_2 : 1; - unsigned int COEFFICIENTID_2 : 2; - unsigned int COEFFICIENT_2 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE3_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_3 : 1; - unsigned int TX_CFG_INV_DATA_3 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_3 : 1; - unsigned int TX_DBG_PRBS_EN_3 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE3_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_3 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_3 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_3 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_3 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_3 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_3 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_3 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_3 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_3 : 3; - unsigned int INCOHERENTCK_3__SI__CI : 1; - unsigned int TXMARG_3 : 3; - unsigned int DEEMPH_3 : 1; - unsigned int COEFFICIENTID_3 : 2; - unsigned int COEFFICIENT_3 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE4_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_4 : 1; - unsigned int TX_CFG_INV_DATA_4 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_4 : 1; - unsigned int TX_DBG_PRBS_EN_4 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE4_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_4 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_4 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_4 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_4 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_4 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_4 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_4 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_4 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_4 : 3; - unsigned int INCOHERENTCK_4__SI__CI : 1; - unsigned int TXMARG_4 : 3; - unsigned int DEEMPH_4 : 1; - unsigned int COEFFICIENTID_4 : 2; - unsigned int COEFFICIENT_4 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE5_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_5 : 1; - unsigned int TX_CFG_INV_DATA_5 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_5 : 1; - unsigned int TX_DBG_PRBS_EN_5 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE5_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_5 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_5 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_5 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_5 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_5 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_5 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_5 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_5 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_5 : 3; - unsigned int INCOHERENTCK_5__SI__CI : 1; - unsigned int TXMARG_5 : 3; - unsigned int DEEMPH_5 : 1; - unsigned int COEFFICIENTID_5 : 2; - unsigned int COEFFICIENT_5 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE6_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_6 : 1; - unsigned int TX_CFG_INV_DATA_6 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_6 : 1; - unsigned int TX_DBG_PRBS_EN_6 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE6_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_6 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_6 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_6 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_6 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_6 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_6 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_6 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_6 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_6 : 3; - unsigned int INCOHERENTCK_6__SI__CI : 1; - unsigned int TXMARG_6 : 3; - unsigned int DEEMPH_6 : 1; - unsigned int COEFFICIENTID_6 : 2; - unsigned int COEFFICIENT_6 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE7_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_7 : 1; - unsigned int TX_CFG_INV_DATA_7 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_7 : 1; - unsigned int TX_DBG_PRBS_EN_7 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE7_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_7 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_7 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_7 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_7 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_7 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_7 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_7 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_7 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_7 : 3; - unsigned int INCOHERENTCK_7__SI__CI : 1; - unsigned int TXMARG_7 : 3; - unsigned int DEEMPH_7 : 1; - unsigned int COEFFICIENTID_7 : 2; - unsigned int COEFFICIENT_7 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE8_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_8 : 1; - unsigned int TX_CFG_INV_DATA_8 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_8 : 1; - unsigned int TX_DBG_PRBS_EN_8 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE8_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_8 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_8 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_8 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_8 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_8 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_8 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_8 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_8 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_8 : 3; - unsigned int INCOHERENTCK_8__SI__CI : 1; - unsigned int TXMARG_8 : 3; - unsigned int DEEMPH_8 : 1; - unsigned int COEFFICIENTID_8 : 2; - unsigned int COEFFICIENT_8 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE9_CTRL_REG0__CI__VI { - struct { - unsigned int TX_CFG_DISPCLK_MODE_9 : 1; - unsigned int TX_CFG_INV_DATA_9 : 1; - unsigned int TX_CFG_SWING_BOOST_EN_9 : 1; - unsigned int TX_DBG_PRBS_EN_9 : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE9_OVRD_REG0__CI__VI { - struct { - unsigned int TX_DCLK_EN_OVRD_VAL_9 : 1; - unsigned int TX_DCLK_EN_OVRD_EN_9 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_VAL_9 : 1; - unsigned int TX_DRV_DATA_EN_OVRD_EN_9 : 1; - unsigned int TX_DRV_PWRON_OVRD_VAL_9 : 1; - unsigned int TX_DRV_PWRON_OVRD_EN_9 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_VAL_9 : 1; - unsigned int TX_FRONTEND_PWRON_OVRD_EN_9 : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI { - struct { - unsigned int TXPWR_9 : 3; - unsigned int INCOHERENTCK_9__SI__CI : 1; - unsigned int TXMARG_9 : 3; - unsigned int DEEMPH_9 : 1; - unsigned int COEFFICIENTID_9 : 2; - unsigned int COEFFICIENT_9 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_BCH_ECC_CNTL__CI__VI { - struct { - unsigned int STRAP_BCH_ECC_EN : 1; - unsigned int : 7; - unsigned int BCH_ECC_ERROR_THRESHOLD : 8; - unsigned int BCH_ECC_ERROR_STATUS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_HW_DEBUG { - struct { - unsigned int HW_00_DEBUG : 1; - unsigned int HW_01_DEBUG : 1; - unsigned int HW_02_DEBUG : 1; - unsigned int HW_03_DEBUG : 1; - unsigned int HW_04_DEBUG : 1; - unsigned int HW_05_DEBUG : 1; - unsigned int HW_06_DEBUG : 1; - unsigned int HW_07_DEBUG : 1; - unsigned int HW_08_DEBUG : 1; - unsigned int HW_09_DEBUG : 1; - unsigned int HW_10_DEBUG : 1; - unsigned int HW_11_DEBUG : 1; - unsigned int HW_12_DEBUG : 1; - unsigned int HW_13_DEBUG : 1; - unsigned int HW_14_DEBUG : 1; - unsigned int HW_15_DEBUG : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_PORT_CNTL__CI__VI { - struct { - unsigned int SLV_PORT_REQ_EN : 1; - unsigned int CI_SNOOP_OVERRIDE : 1; - unsigned int HOTPLUG_MSG_EN : 1; - unsigned int NATIVE_PME_EN : 1; - unsigned int PWR_FAULT_EN : 1; - unsigned int PMI_BM_DIS : 1; - unsigned int SEQNUM_DEBUG_MODE : 1; - unsigned int : 1; - unsigned int CI_SLV_CPL_STATIC_ALLOC_LIMIT_S : 7; - unsigned int : 1; - unsigned int CI_MAX_CPL_PAYLOAD_SIZE_MODE : 2; - unsigned int CI_PRIV_MAX_CPL_PAYLOAD_SIZE : 3; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_PORT_CNTL__SI { - struct { - unsigned int SLV_PORT_REQ_EN : 1; - unsigned int CI_SNOOP_OVERRIDE : 1; - unsigned int HOTPLUG_MSG_EN : 1; - unsigned int NATIVE_PME_EN : 1; - unsigned int SEQNUM_DEBUG_MODE : 1; - unsigned int PMI_BM_DIS : 1; - unsigned int : 2; - unsigned int CI_SLV_CPL_STATIC_ALLOC_LIMIT_S : 7; - unsigned int : 1; - unsigned int : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_RESERVED { - struct { - unsigned int PCIEP_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_SCRATCH { - struct { - unsigned int PCIEP_SCRATCH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_STRAP_LC { - struct { - unsigned int STRAP_FTS_yTSx_COUNT : 2; - unsigned int STRAP_LONG_yTSx_COUNT : 2; - unsigned int STRAP_MED_yTSx_COUNT : 2; - unsigned int STRAP_SHORT_yTSx_COUNT : 2; - unsigned int STRAP_SKIP_INTERVAL : 3; - unsigned int STRAP_BYPASS_RCVR_DET : 1; - unsigned int STRAP_COMPLIANCE_DIS : 1; - unsigned int STRAP_FORCE_COMPLIANCE : 1; - unsigned int STRAP_REVERSE_LC_LANES : 1; - unsigned int STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS : 1; - unsigned int STRAP_LANE_NEGOTIATION : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_STRAP_MISC__CI__VI { - struct { - unsigned int STRAP_REVERSE_LANES : 1; - unsigned int STRAP_E2E_PREFIX_EN : 1; - unsigned int STRAP_EXTENDED_FMT_SUPPORTED : 1; - unsigned int STRAP_OBFF_SUPPORTED : 2; - unsigned int STRAP_LTR_SUPPORTED : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_STRAP_MISC__SI { - struct { - unsigned int : 4; - unsigned int STRAP_REVERSE_LANES : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ACS_CAP__CI__VI { - struct { - unsigned int SOURCE_VALIDATION : 1; - unsigned int TRANSLATION_BLOCKING : 1; - unsigned int P2P_REQUEST_REDIRECT : 1; - unsigned int P2P_COMPLETION_REDIRECT : 1; - unsigned int UPSTREAM_FORWARDING : 1; - unsigned int P2P_EGRESS_CONTROL : 1; - unsigned int DIRECT_TRANSLATED_P2P : 1; - unsigned int : 1; - unsigned int EGRESS_CONTROL_VECTOR_SIZE : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ACS_CNTL__CI__VI { - struct { - unsigned int SOURCE_VALIDATION_EN : 1; - unsigned int TRANSLATION_BLOCKING_EN : 1; - unsigned int P2P_REQUEST_REDIRECT_EN : 1; - unsigned int P2P_COMPLETION_REDIRECT_EN : 1; - unsigned int UPSTREAM_FORWARDING_EN : 1; - unsigned int P2P_EGRESS_CONTROL_EN : 1; - unsigned int DIRECT_TRANSLATED_P2P_EN : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ACS_ENH_CAP_LIST__CI__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ADV_ERR_CAP_CNTL__SI__CI { - struct { - unsigned int FIRST_ERR_PTR : 5; - unsigned int ECRC_GEN_CAP : 1; - unsigned int ECRC_GEN_EN : 1; - unsigned int ECRC_CHECK_CAP : 1; - unsigned int ECRC_CHECK_EN : 1; - unsigned int MULTI_HDR_RECD_CAP__CI : 1; - unsigned int MULTI_HDR_RECD_EN__CI : 1; - unsigned int : 4; - unsigned int TLP_PREFIX_LOG_PRESENT__CI : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ADV_ERR_CAP_CNTL__VI { - struct { - unsigned int FIRST_ERR_PTR : 5; - unsigned int ECRC_GEN_CAP : 1; - unsigned int ECRC_GEN_EN : 1; - unsigned int ECRC_CHECK_CAP : 1; - unsigned int ECRC_CHECK_EN : 1; - unsigned int MULTI_HDR_RECD_CAP : 1; - unsigned int MULTI_HDR_RECD_EN : 1; - unsigned int TLP_PREFIX_LOG_PRESENT : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ADV_ERR_RPT_ENH_CAP_LIST { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ATS_CAP__CI { - struct { - unsigned int INVALIDATE_Q_DEPTH : 5; - unsigned int PAGE_ALIGNED_REQUEST : 1; - unsigned int : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ATS_CAP__VI { - struct { - unsigned int INVALIDATE_Q_DEPTH : 5; - unsigned int PAGE_ALIGNED_REQUEST : 1; - unsigned int GLOBAL_INVALIDATE_SUPPORTED : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ATS_CNTL__CI__VI { - struct { - unsigned int STU : 5; - unsigned int : 10; - unsigned int ATC_ENABLE : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ATS_ENH_CAP_LIST__CI__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR1_CAP__CI__VI { - struct { - unsigned int : 4; - unsigned int BAR_SIZE_SUPPORTED : 20; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR1_CNTL__CI__VI { - struct { - unsigned int BAR_INDEX : 3; - unsigned int : 2; - unsigned int BAR_TOTAL_NUM : 3; - unsigned int BAR_SIZE : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR2_CAP__CI__VI { - struct { - unsigned int : 4; - unsigned int BAR_SIZE_SUPPORTED : 20; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR2_CNTL__CI__VI { - struct { - unsigned int BAR_INDEX : 3; - unsigned int : 2; - unsigned int BAR_TOTAL_NUM : 3; - unsigned int BAR_SIZE : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR3_CAP__CI__VI { - struct { - unsigned int : 4; - unsigned int BAR_SIZE_SUPPORTED : 20; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR3_CNTL__CI__VI { - struct { - unsigned int BAR_INDEX : 3; - unsigned int : 2; - unsigned int BAR_TOTAL_NUM : 3; - unsigned int BAR_SIZE : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR4_CAP__CI__VI { - struct { - unsigned int : 4; - unsigned int BAR_SIZE_SUPPORTED : 20; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR4_CNTL__CI__VI { - struct { - unsigned int BAR_INDEX : 3; - unsigned int : 2; - unsigned int BAR_TOTAL_NUM : 3; - unsigned int BAR_SIZE : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR5_CAP__CI__VI { - struct { - unsigned int : 4; - unsigned int BAR_SIZE_SUPPORTED : 20; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR5_CNTL__CI__VI { - struct { - unsigned int BAR_INDEX : 3; - unsigned int : 2; - unsigned int BAR_TOTAL_NUM : 3; - unsigned int BAR_SIZE : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR6_CAP__CI__VI { - struct { - unsigned int : 4; - unsigned int BAR_SIZE_SUPPORTED : 20; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR6_CNTL__CI__VI { - struct { - unsigned int BAR_INDEX : 3; - unsigned int : 2; - unsigned int BAR_TOTAL_NUM : 3; - unsigned int BAR_SIZE : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BAR_ENH_CAP_LIST__CI__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_BUS_CNTL { - struct { - unsigned int : 1; - unsigned int : 5; - unsigned int PMI_INT_DIS : 1; - unsigned int IMMEDIATE_PMI_DIS : 1; - unsigned int : 4; - unsigned int TRUE_PM_STATUS_EN__CI__VI : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CAP { - struct { - unsigned int VERSION : 4; - unsigned int DEVICE_TYPE : 4; - unsigned int SLOT_IMPLEMENTED : 1; - unsigned int INT_MESSAGE_NUM : 5; - unsigned int : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CAP_LIST { - struct { - unsigned int CAP_ID : 8; - unsigned int NEXT_PTR : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CFG_CNTL__CI__VI { - struct { - unsigned int CFG_EN_DEC_TO_HIDDEN_REG : 1; - unsigned int CFG_EN_DEC_TO_GEN2_HIDDEN_REG : 1; - unsigned int CFG_EN_DEC_TO_GEN3_HIDDEN_REG : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CFG_CNTL__SI { - struct { - unsigned int CFG_EN_DEC_TO_GEN2_HIDDEN_REG : 1; - unsigned int CFG_EN_DEC_TO_HIDDEN_REG : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CI_CNTL__CI__VI { - struct { - unsigned int : 2; - unsigned int CI_SLAVE_SPLIT_MODE : 1; - unsigned int CI_SLAVE_GEN_USR_DIS : 1; - unsigned int CI_MST_CMPL_DUMMY_DATA : 1; - unsigned int : 1; - unsigned int CI_SLV_RC_RD_REQ_SIZE : 2; - unsigned int CI_SLV_ORDERING_DIS : 1; - unsigned int CI_RC_ORDERING_DIS : 1; - unsigned int CI_SLV_CPL_ALLOC_DIS : 1; - unsigned int CI_SLV_CPL_ALLOC_MODE : 1; - unsigned int CI_SLV_CPL_ALLOC_SOR : 1; - unsigned int CI_MST_IGNORE_PAGE_ALIGNED_REQUEST : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CI_CNTL__SI { - struct { - unsigned int : 2; - unsigned int CI_SLAVE_SPLIT_MODE : 1; - unsigned int CI_SLAVE_GEN_USR_DIS : 1; - unsigned int CI_MST_CMPL_DUMMY_DATA : 1; - unsigned int : 1; - unsigned int CI_SLV_RC_RD_REQ_SIZE : 2; - unsigned int CI_SLV_ORDERING_DIS : 1; - unsigned int CI_RC_ORDERING_DIS : 1; - unsigned int CI_SLV_CPL_ALLOC_DIS : 1; - unsigned int CI_SLV_CPL_ALLOC_MODE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 10; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CNTL2 { - struct { - unsigned int TX_ARB_ROUND_ROBIN_EN : 1; - unsigned int TX_ARB_SLV_LIMIT : 5; - unsigned int TX_ARB_MST_LIMIT : 5; - unsigned int TX_BLOCK_TLP_ON_PM_DIS__VI : 1; - unsigned int TX_NP_MEM_WRITE_SWP_ENCODING__VI : 1; - unsigned int TX_ATOMIC_OPS_DISABLE__VI : 1; - unsigned int TX_ATOMIC_ORDERING_DIS__VI : 1; - unsigned int : 1; - unsigned int SLV_MEM_LS_EN__CI__VI : 1; - unsigned int SLV_MEM_AGGRESSIVE_LS_EN__CI__VI : 1; - unsigned int MST_MEM_LS_EN__CI__VI : 1; - unsigned int REPLAY_MEM_LS_EN__CI__VI : 1; - unsigned int SLV_MEM_SD_EN__CI__VI : 1; - unsigned int SLV_MEM_AGGRESSIVE_SD_EN__CI__VI : 1; - unsigned int MST_MEM_SD_EN__CI__VI : 1; - unsigned int REPLAY_MEM_SD_EN__CI__VI : 1; - unsigned int RX_NP_MEM_WRITE_ENCODING__CI__VI : 5; - unsigned int SLV_MEM_DS_EN__VI : 1; - unsigned int MST_MEM_DS_EN__VI : 1; - unsigned int REPLAY_MEM_DS_EN__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CNTL__CI { - struct { - unsigned int HWINIT_WR_LOCK : 1; - unsigned int LC_HOT_PLUG_DELAY_SEL : 3; - unsigned int : 3; - unsigned int UR_ERR_REPORT_DIS : 1; - unsigned int PCIE_MALFORM_ATOMIC_OPS : 1; - unsigned int PCIE_HT_NP_MEM_WRITE : 1; - unsigned int RX_SB_ADJ_PAYLOAD_SIZE : 3; - unsigned int : 2; - unsigned int RX_RCB_ATS_UC_DIS : 1; - unsigned int RX_RCB_REORDER_EN : 1; - unsigned int RX_RCB_INVALID_SIZE_DIS : 1; - unsigned int RX_RCB_UNEXP_CPL_DIS : 1; - unsigned int RX_RCB_CPL_TIMEOUT_TEST_MODE : 1; - unsigned int RX_RCB_CHANNEL_ORDERING : 1; - unsigned int RX_RCB_WRONG_ATTR_DIS : 1; - unsigned int RX_RCB_WRONG_FUNCNUM_DIS : 1; - unsigned int RX_ATS_TRAN_CPL_SPLIT_DIS : 1; - unsigned int TX_CPL_DEBUG : 6; - unsigned int RX_IGNORE_LTR_MSG_UR : 1; - unsigned int RX_CPL_POSTED_REQ_ORD_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CNTL__VI { - struct { - unsigned int HWINIT_WR_LOCK : 1; - unsigned int LC_HOT_PLUG_DELAY_SEL : 3; - unsigned int : 3; - unsigned int UR_ERR_REPORT_DIS : 1; - unsigned int PCIE_MALFORM_ATOMIC_OPS : 1; - unsigned int PCIE_HT_NP_MEM_WRITE : 1; - unsigned int RX_SB_ADJ_PAYLOAD_SIZE : 3; - unsigned int : 2; - unsigned int RX_RCB_ATS_UC_DIS : 1; - unsigned int RX_RCB_REORDER_EN : 1; - unsigned int RX_RCB_INVALID_SIZE_DIS : 1; - unsigned int RX_RCB_UNEXP_CPL_DIS : 1; - unsigned int RX_RCB_CPL_TIMEOUT_TEST_MODE : 1; - unsigned int RX_RCB_WRONG_PREFIX_DIS : 1; - unsigned int RX_RCB_WRONG_ATTR_DIS : 1; - unsigned int RX_RCB_WRONG_FUNCNUM_DIS : 1; - unsigned int RX_ATS_TRAN_CPL_SPLIT_DIS : 1; - unsigned int TX_CPL_DEBUG : 6; - unsigned int RX_IGNORE_LTR_MSG_UR : 1; - unsigned int RX_CPL_POSTED_REQ_ORD_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CNTL__SI { - struct { - unsigned int HWINIT_WR_LOCK : 1; - unsigned int : 6; - unsigned int UR_ERR_REPORT_DIS : 1; - unsigned int : 1; - unsigned int PCIE_HT_NP_MEM_WRITE : 1; - unsigned int RX_SB_ADJ_PAYLOAD_SIZE : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int RX_RCB_REORDER_EN : 1; - unsigned int RX_RCB_INVALID_SIZE_DIS : 1; - unsigned int RX_RCB_UNEXP_CPL_DIS : 1; - unsigned int RX_RCB_CPL_TIMEOUT_TEST_MODE : 1; - unsigned int RX_RCB_CHANNEL_ORDERING : 1; - unsigned int RX_RCB_WRONG_ATTR_DIS : 1; - unsigned int RX_RCB_WRONG_FUNCNUM_DIS : 1; - unsigned int : 1; - unsigned int TX_CPL_DEBUG : 6; - unsigned int : 1; - unsigned int RX_CPL_POSTED_REQ_ORD_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CONFIG_CNTL { - struct { - unsigned int DYN_CLK_LATENCY : 4; - unsigned int : 12; - unsigned int CI_MAX_PAYLOAD_SIZE_MODE__CI__VI : 1; - unsigned int CI_PRIV_MAX_PAYLOAD_SIZE__CI__VI : 3; - unsigned int CI_MAX_READ_REQUEST_SIZE_MODE__CI__VI : 1; - unsigned int CI_PRIV_MAX_READ_REQUEST_SIZE__CI__VI : 3; - unsigned int CI_MAX_READ_SAFE_MODE__CI__VI : 1; - unsigned int CI_EXTENDED_TAG_EN_OVERRIDE__CI__VI : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CORR_ERR_MASK { - struct { - unsigned int RCV_ERR_MASK : 1; - unsigned int : 5; - unsigned int BAD_TLP_MASK : 1; - unsigned int BAD_DLLP_MASK : 1; - unsigned int REPLAY_NUM_ROLLOVER_MASK : 1; - unsigned int : 3; - unsigned int REPLAY_TIMER_TIMEOUT_MASK : 1; - unsigned int ADVISORY_NONFATAL_ERR_MASK : 1; - unsigned int CORR_INT_ERR_MASK__CI__VI : 1; - unsigned int HDR_LOG_OVFL_MASK__CI__VI : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_CORR_ERR_STATUS { - struct { - unsigned int RCV_ERR_STATUS : 1; - unsigned int : 5; - unsigned int BAD_TLP_STATUS : 1; - unsigned int BAD_DLLP_STATUS : 1; - unsigned int REPLAY_NUM_ROLLOVER_STATUS : 1; - unsigned int : 3; - unsigned int REPLAY_TIMER_TIMEOUT_STATUS : 1; - unsigned int ADVISORY_NONFATAL_ERR_STATUS : 1; - unsigned int CORR_INT_ERR_STATUS__CI__VI : 1; - unsigned int HDR_LOG_OVFL_STATUS__CI__VI : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DATA { - struct { - unsigned int PCIE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DATA_2__CI__VI { - struct { - unsigned int PCIE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DEBUG_CNTL { - struct { - unsigned int DEBUG_PORT_EN : 8; - unsigned int DEBUG_SELECT : 1; - unsigned int : 7; - unsigned int DEBUG_LANE_EN : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DEV_SERIAL_NUM_DW1 { - struct { - unsigned int SERIAL_NUMBER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DEV_SERIAL_NUM_DW2 { - struct { - unsigned int SERIAL_NUMBER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_CAP__CI__VI { - struct { - unsigned int SUBSTATE_MAX : 5; - unsigned int : 3; - unsigned int TRANS_LAT_UNIT : 2; - unsigned int : 2; - unsigned int PWR_ALLOC_SCALE : 2; - unsigned int : 2; - unsigned int TRANS_LAT_VAL_0 : 8; - unsigned int TRANS_LAT_VAL_1 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_CNTL__CI__VI { - struct { - unsigned int SUBSTATE_CNTL : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_ENH_CAP_LIST__CI__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_LATENCY_INDICATOR__CI__VI { - struct { - unsigned int TRANS_LAT_INDICATOR_BITS : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_STATUS__CI__VI { - struct { - unsigned int SUBSTATE_STATUS : 5; - unsigned int : 3; - unsigned int SUBSTATE_CNTL_ENABLED : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ERR_CNTL__CI__VI { - struct { - unsigned int ERR_REPORTING_DIS : 1; - unsigned int STRAP_FIRST_RCVD_ERR_LOG : 1; - unsigned int RX_DROP_ECRC_FAILURES : 1; - unsigned int : 1; - unsigned int TX_GENERATE_LCRC_ERR : 1; - unsigned int RX_GENERATE_LCRC_ERR : 1; - unsigned int TX_GENERATE_ECRC_ERR : 1; - unsigned int RX_GENERATE_ECRC_ERR : 1; - unsigned int AER_HDR_LOG_TIMEOUT : 3; - unsigned int AER_HDR_LOG_F0_TIMER_EXPIRED : 1; - unsigned int AER_HDR_LOG_F1_TIMER_EXPIRED : 1; - unsigned int AER_HDR_LOG_F2_TIMER_EXPIRED : 1; - unsigned int CI_P_SLV_BUF_RD_HALT_STATUS : 1; - unsigned int CI_NP_SLV_BUF_RD_HALT_STATUS : 1; - unsigned int CI_SLV_BUF_HALT_RESET : 1; - unsigned int SEND_ERR_MSG_IMMEDIATELY__VI : 1; - unsigned int STRAP_POISONED_ADVISORY_NONFATAL__VI : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ERR_CNTL__SI { - struct { - unsigned int ERR_REPORTING_DIS : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_F0_DPA_CAP__CI__VI { - struct { - unsigned int : 8; - unsigned int TRANS_LAT_UNIT : 2; - unsigned int : 2; - unsigned int PWR_ALLOC_SCALE : 2; - unsigned int : 2; - unsigned int TRANS_LAT_VAL_0 : 8; - unsigned int TRANS_LAT_VAL_1 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_F0_DPA_CNTL__CI__VI { - struct { - unsigned int SUBSTATE_STATUS : 5; - unsigned int : 3; - unsigned int DPA_COMPLIANCE_MODE__VI : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_F0_DPA_LATENCY_INDICATOR__CI__VI { - struct { - unsigned int TRANS_LAT_INDICATOR_BITS : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI { - struct { - unsigned int SUBSTATE_PWR_ALLOC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_FC_CPL { - struct { - unsigned int CPLD_CREDITS : 8; - unsigned int CPLH_CREDITS : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_FC_NP { - struct { - unsigned int NPD_CREDITS : 8; - unsigned int NPH_CREDITS : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_FC_P { - struct { - unsigned int PD_CREDITS : 8; - unsigned int PH_CREDITS : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_HDR_LOG0 { - struct { - unsigned int TLP_HDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_HDR_LOG1 { - struct { - unsigned int TLP_HDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_HDR_LOG2 { - struct { - unsigned int TLP_HDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_HDR_LOG3 { - struct { - unsigned int TLP_HDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_HW_DEBUG { - struct { - unsigned int HW_00_DEBUG : 1; - unsigned int HW_01_DEBUG : 1; - unsigned int HW_02_DEBUG : 1; - unsigned int HW_03_DEBUG : 1; - unsigned int HW_04_DEBUG : 1; - unsigned int HW_05_DEBUG : 1; - unsigned int HW_06_DEBUG : 1; - unsigned int HW_07_DEBUG : 1; - unsigned int HW_08_DEBUG : 1; - unsigned int HW_09_DEBUG : 1; - unsigned int HW_10_DEBUG : 1; - unsigned int HW_11_DEBUG : 1; - unsigned int HW_12_DEBUG : 1; - unsigned int HW_13_DEBUG : 1; - unsigned int HW_14_DEBUG : 1; - unsigned int HW_15_DEBUG : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_I2C_REG_ADDR_EXPAND { - struct { - unsigned int I2C_REG_ADDR : 17; - unsigned int : 4; - unsigned int : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_I2C_REG_DATA { - struct { - unsigned int I2C_REG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_INDEX_2__CI__VI { - struct { - unsigned int PCIE_INDEX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_INDEX__CI__VI { - struct { - unsigned int PCIE_INDEX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_INDEX__SI { - struct { - unsigned int PCIE_INDEX : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_INT_CNTL { - struct { - unsigned int CORR_ERR_INT_EN : 1; - unsigned int NON_FATAL_ERR_INT_EN : 1; - unsigned int FATAL_ERR_INT_EN : 1; - unsigned int USR_DETECTED_INT_EN : 1; - unsigned int MISC_ERR_INT_EN : 1; - unsigned int : 1; - unsigned int POWER_STATE_CHG_INT_EN : 1; - unsigned int LINK_BW_INT_EN : 1; - unsigned int QUIESCE_RCVD_INT_EN__CI__VI : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_INT_STATUS { - struct { - unsigned int CORR_ERR_INT_STATUS : 1; - unsigned int NON_FATAL_ERR_INT_STATUS : 1; - unsigned int FATAL_ERR_INT_STATUS : 1; - unsigned int USR_DETECTED_INT_STATUS : 1; - unsigned int MISC_ERR_INT_STATUS : 1; - unsigned int : 1; - unsigned int POWER_STATE_CHG_INT_STATUS : 1; - unsigned int LINK_BW_INT_STATUS : 1; - unsigned int QUIESCE_RCVD_INT_STATUS__CI__VI : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_0_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_10_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_11_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_12_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_13_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_14_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_15_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_1_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_2_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_3_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_4_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_5_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_6_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_7_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_8_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_9_EQUALIZATION_CNTL__CI__VI { - struct { - unsigned int DOWNSTREAM_PORT_TX_PRESET : 4; - unsigned int DOWNSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 1; - unsigned int UPSTREAM_PORT_TX_PRESET : 4; - unsigned int UPSTREAM_PORT_RX_PRESET_HINT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LANE_ERROR_STATUS__CI__VI { - struct { - unsigned int LANE_ERROR_STATUS_BITS : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_BW_CHANGE_CNTL { - struct { - unsigned int LC_BW_CHANGE_INT_EN : 1; - unsigned int LC_HW_INIT_SPEED_CHANGE : 1; - unsigned int LC_SW_INIT_SPEED_CHANGE : 1; - unsigned int LC_OTHER_INIT_SPEED_CHANGE : 1; - unsigned int LC_RELIABILITY_SPEED_CHANGE : 1; - unsigned int LC_FAILED_SPEED_NEG : 1; - unsigned int LC_LONG_LW_CHANGE : 1; - unsigned int LC_SHORT_LW_CHANGE : 1; - unsigned int LC_LW_CHANGE_OTHER : 1; - unsigned int LC_LW_CHANGE_FAILED : 1; - unsigned int LC_LINK_BW_NOTIFICATION_DETECT_MODE : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_CDR_CNTL { - struct { - unsigned int LC_CDR_TEST_OFF : 12; - unsigned int LC_CDR_TEST_SETS : 12; - unsigned int LC_CDR_SET_TYPE : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_CNTL { - struct { - unsigned int : 1; - unsigned int LC_DONT_ENTER_L23_IN_D0 : 1; - unsigned int LC_RESET_L_IDLE_COUNT_EN : 1; - unsigned int LC_RESET_LINK : 1; - unsigned int LC_16X_CLEAR_TX_PIPE : 4; - unsigned int LC_L0S_INACTIVITY : 4; - unsigned int LC_L1_INACTIVITY : 4; - unsigned int LC_PMI_TO_L1_DIS : 1; - unsigned int LC_INC_N_FTS_EN : 1; - unsigned int LC_LOOK_FOR_IDLE_IN_L1L23 : 2; - unsigned int LC_FACTOR_IN_EXT_SYNC : 1; - unsigned int LC_WAIT_FOR_PM_ACK_DIS : 1; - unsigned int LC_WAKE_FROM_L23 : 1; - unsigned int LC_L1_IMMEDIATE_ACK : 1; - unsigned int LC_ASPM_TO_L1_DIS : 1; - unsigned int LC_DELAY_COUNT : 2; - unsigned int LC_DELAY_L0S_EXIT : 1; - unsigned int LC_DELAY_L1_EXIT : 1; - unsigned int LC_EXTEND_WAIT_FOR_EL_IDLE : 1; - unsigned int LC_ESCAPE_L1L23_EN : 1; - unsigned int LC_GATE_RCVR_IDLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_CNTL2__CI__VI { - struct { - unsigned int LC_TIMED_OUT_STATE : 6; - unsigned int LC_STATE_TIMED_OUT : 1; - unsigned int LC_LOOK_FOR_BW_REDUCTION : 1; - unsigned int LC_MORE_TS2_EN : 1; - unsigned int LC_X12_NEGOTIATION_DIS : 1; - unsigned int LC_LINK_UP_REVERSAL_EN : 1; - unsigned int LC_ILLEGAL_STATE : 1; - unsigned int LC_ILLEGAL_STATE_RESTART_EN : 1; - unsigned int LC_WAIT_FOR_OTHER_LANES_MODE : 1; - unsigned int LC_ELEC_IDLE_MODE : 2; - unsigned int LC_DISABLE_INFERRED_ELEC_IDLE_DET : 1; - unsigned int LC_ALLOW_PDWN_IN_L1 : 1; - unsigned int LC_ALLOW_PDWN_IN_L23 : 1; - unsigned int LC_DEASSERT_RX_EN_IN_L0S : 1; - unsigned int LC_BLOCK_EL_IDLE_IN_L0 : 1; - unsigned int LC_RCV_L0_TO_RCV_L0S_DIS : 1; - unsigned int LC_ASSERT_INACTIVE_DURING_HOLD : 1; - unsigned int LC_WAIT_FOR_LANES_IN_LW_NEG : 2; - unsigned int LC_PWR_DOWN_NEG_OFF_LANES : 1; - unsigned int LC_DISABLE_LOST_SYM_LOCK_ARCS : 1; - unsigned int LC_LINK_BW_NOTIFICATION_DIS : 1; - unsigned int LC_PMI_L1_WAIT_FOR_SLV_IDLE : 1; - unsigned int LC_TEST_TIMER_SEL : 2; - unsigned int LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_CNTL2__SI { - struct { - unsigned int LC_TIMED_OUT_STATE : 6; - unsigned int LC_STATE_TIMED_OUT : 1; - unsigned int LC_LOOK_FOR_BW_REDUCTION : 1; - unsigned int LC_MORE_TS2_EN : 1; - unsigned int LC_X12_NEGOTIATION_DIS : 1; - unsigned int LC_LINK_UP_REVERSAL_EN : 1; - unsigned int LC_ILLEGAL_STATE : 1; - unsigned int LC_ILLEGAL_STATE_RESTART_EN : 1; - unsigned int LC_WAIT_FOR_OTHER_LANES_MODE : 1; - unsigned int LC_ELEC_IDLE_MODE : 2; - unsigned int LC_DISABLE_INFERRED_ELEC_IDLE_DET : 1; - unsigned int LC_ALLOW_PDWN_IN_L1 : 1; - unsigned int LC_ALLOW_PDWN_IN_L23 : 1; - unsigned int LC_DEASSERT_RX_EN_IN_L0S : 1; - unsigned int LC_BLOCK_EL_IDLE_IN_L0 : 1; - unsigned int LC_RCV_L0_TO_RCV_L0S_DIS : 1; - unsigned int LC_ASSERT_INACTIVE_DURING_HOLD : 1; - unsigned int LC_WAIT_FOR_LANES_IN_LW_NEG : 2; - unsigned int LC_PWR_DOWN_NEG_OFF_LANES : 1; - unsigned int LC_DISABLE_LOST_SYM_LOCK_ARCS : 1; - unsigned int LC_LINK_BW_NOTIFICATION_DIS : 1; - unsigned int : 1; - unsigned int LC_TEST_TIMER_SEL : 2; - unsigned int LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_CNTL3 { - struct { - unsigned int LC_SELECT_DEEMPHASIS : 1; - unsigned int LC_SELECT_DEEMPHASIS_CNTL : 2; - unsigned int LC_RCVD_DEEMPHASIS : 1; - unsigned int LC_COMP_TO_DETECT : 1; - unsigned int LC_RESET_TSX_CNT_IN_RLOCK_EN : 1; - unsigned int LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__CI__VI : 2; - unsigned int LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__CI__VI : 1; - unsigned int LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__CI__VI : 1; - unsigned int LC_ENHANCED_HOT_PLUG_EN__CI__VI : 1; - unsigned int LC_RCVR_DET_EN_OVERRIDE__CI__VI : 1; - unsigned int LC_EHP_RX_PHY_CMD__CI__VI : 2; - unsigned int LC_EHP_TX_PHY_CMD__CI__VI : 2; - unsigned int LC_CHIP_BIF_USB_IDLE_EN__CI__VI : 1; - unsigned int LC_L1_BLOCK_RECONFIG_EN__CI__VI : 1; - unsigned int LC_AUTO_DISABLE_SPEED_SUPPORT_EN__CI__VI : 1; - unsigned int LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__CI__VI : 2; - unsigned int LC_FAST_L1_ENTRY_EXIT_EN__CI__VI : 1; - unsigned int LC_RXPHYCMD_INACTIVE_EN_MODE__CI__VI : 1; - unsigned int LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__CI__VI : 1; - unsigned int LC_HW_VOLTAGE_IF_CONTROL__CI__VI : 2; - unsigned int LC_VOLTAGE_TIMER_SEL__CI__VI : 4; - unsigned int LC_GO_TO_RECOVERY__CI__VI : 1; - unsigned int LC_N_EIE_SEL__CI__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_CNTL4__CI { - struct { - unsigned int LC_TX_ENABLE_BEHAVIOUR : 2; - unsigned int : 2; - unsigned int LC_BYPASS_EQ : 1; - unsigned int LC_REDO_EQ : 1; - unsigned int LC_EXTEND_EIEOS : 1; - unsigned int LC_IGNORE_PARITY : 1; - unsigned int LC_EQ_SEARCH_MODE : 2; - unsigned int : 1; - unsigned int LC_USC_EQ_NOT_REQD : 1; - unsigned int LC_USC_GO_TO_EQ : 1; - unsigned int LC_SET_QUIESCE : 1; - unsigned int LC_QUIESCE_RCVD : 1; - unsigned int LC_UNEXPECTED_COEFFS_RCVD : 1; - unsigned int LC_BYPASS_EQ_REQ_PHASE : 1; - unsigned int LC_FORCE_PRESET_IN_EQ_REQ_PHASE : 1; - unsigned int LC_FORCE_PRESET_VALUE : 4; - unsigned int LC_USC_DELAY_DLLPS : 1; - unsigned int LC_PCIE_TX_FULL_SWING : 1; - unsigned int LC_EQ_WAIT_FOR_EVAL_DONE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_CNTL4__VI { - struct { - unsigned int LC_TX_ENABLE_BEHAVIOUR : 2; - unsigned int LC_DIS_CONTIG_END_SET_CHECK : 1; - unsigned int LC_DIS_ASPM_L1_IN_SPEED_CHANGE : 1; - unsigned int LC_BYPASS_EQ : 1; - unsigned int LC_REDO_EQ : 1; - unsigned int LC_EXTEND_EIEOS : 1; - unsigned int LC_IGNORE_PARITY : 1; - unsigned int LC_EQ_SEARCH_MODE : 2; - unsigned int LC_DSC_CHECK_COEFFS_IN_RLOCK : 1; - unsigned int LC_USC_EQ_NOT_REQD : 1; - unsigned int LC_USC_GO_TO_EQ : 1; - unsigned int LC_SET_QUIESCE : 1; - unsigned int LC_QUIESCE_RCVD : 1; - unsigned int LC_UNEXPECTED_COEFFS_RCVD : 1; - unsigned int LC_BYPASS_EQ_REQ_PHASE : 1; - unsigned int LC_FORCE_PRESET_IN_EQ_REQ_PHASE : 1; - unsigned int LC_FORCE_PRESET_VALUE : 4; - unsigned int LC_USC_DELAY_DLLPS : 1; - unsigned int LC_PCIE_TX_FULL_SWING : 1; - unsigned int LC_EQ_WAIT_FOR_EVAL_DONE : 1; - unsigned int LC_8GT_SKIP_ORDER_EN : 1; - unsigned int LC_WAIT_FOR_MORE_TS_IN_RLOCK : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_CNTL5__CI__VI { - struct { - unsigned int LC_EQ_FS_0 : 6; - unsigned int LC_EQ_FS_8 : 6; - unsigned int LC_EQ_LF_0 : 6; - unsigned int LC_EQ_LF_8 : 6; - unsigned int LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__VI : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_FORCE_COEFF__CI__VI { - struct { - unsigned int LC_FORCE_COEFF : 1; - unsigned int LC_FORCE_PRE_CURSOR : 6; - unsigned int LC_FORCE_CURSOR : 6; - unsigned int LC_FORCE_POST_CURSOR : 6; - unsigned int LC_3X3_COEFF_SEARCH_EN__VI : 1; - unsigned int LC_PRESET_10_EN__VI : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_LANE_CNTL { - struct { - unsigned int LC_CORRUPTED_LANES : 16; - unsigned int LC_LANE_DIS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_LINK_WIDTH_CNTL { - struct { - unsigned int LC_LINK_WIDTH : 3; - unsigned int : 1; - unsigned int LC_LINK_WIDTH_RD : 3; - unsigned int LC_RECONFIG_ARC_MISSING_ESCAPE : 1; - unsigned int LC_RECONFIG_NOW : 1; - unsigned int LC_RENEGOTIATION_SUPPORT : 1; - unsigned int LC_RENEGOTIATE_EN : 1; - unsigned int LC_SHORT_RECONFIG_EN : 1; - unsigned int LC_UPCONFIGURE_SUPPORT : 1; - unsigned int LC_UPCONFIGURE_DIS : 1; - unsigned int LC_UPCFG_WAIT_FOR_RCVR_DIS : 1; - unsigned int LC_UPCFG_TIMER_SEL : 1; - unsigned int LC_DEASSERT_TX_PDNB : 1; - unsigned int LC_L1_RECONFIG_EN : 1; - unsigned int LC_DYNLINK_MST_EN__CI__VI : 1; - unsigned int LC_DUAL_END_RECONFIG_EN__CI__VI : 1; - unsigned int LC_UPCONFIGURE_CAPABLE__CI__VI : 1; - unsigned int LC_DYN_LANES_PWR_STATE__CI__VI : 2; - unsigned int LC_EQ_REVERSAL_LOGIC_EN__CI__VI : 1; - unsigned int LC_MULT_REVERSE_ATTEMP_EN__VI : 1; - unsigned int LC_RESET_TSX_CNT_IN_RCONFIG_EN__VI : 1; - unsigned int LC_WAIT_FOR_L_IDLE_IN_R_IDLE__VI : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_N_FTS_CNTL { - struct { - unsigned int LC_XMIT_N_FTS : 8; - unsigned int LC_XMIT_N_FTS_OVERRIDE_EN : 1; - unsigned int LC_XMIT_FTS_BEFORE_RECOVERY : 1; - unsigned int : 6; - unsigned int LC_XMIT_N_FTS_LIMIT : 8; - unsigned int LC_N_FTS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_SPEED_CNTL__CI__VI { - struct { - unsigned int LC_GEN2_EN_STRAP : 1; - unsigned int LC_GEN3_EN_STRAP : 1; - unsigned int LC_TARGET_LINK_SPEED_OVERRIDE_EN : 1; - unsigned int LC_TARGET_LINK_SPEED_OVERRIDE : 2; - unsigned int LC_FORCE_EN_SW_SPEED_CHANGE : 1; - unsigned int LC_FORCE_DIS_SW_SPEED_CHANGE : 1; - unsigned int LC_FORCE_EN_HW_SPEED_CHANGE : 1; - unsigned int LC_FORCE_DIS_HW_SPEED_CHANGE : 1; - unsigned int LC_INITIATE_LINK_SPEED_CHANGE : 1; - unsigned int LC_SPEED_CHANGE_ATTEMPTS_ALLOWED : 2; - unsigned int LC_SPEED_CHANGE_ATTEMPT_FAILED : 1; - unsigned int LC_CURRENT_DATA_RATE : 2; - unsigned int LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS : 1; - unsigned int LC_CLR_FAILED_SPD_CHANGE_CNT : 1; - unsigned int LC_1_OR_MORE_TS2_SPEED_ARC_EN : 1; - unsigned int LC_OTHER_SIDE_EVER_SENT_GEN2 : 1; - unsigned int LC_OTHER_SIDE_SUPPORTS_GEN2 : 1; - unsigned int LC_OTHER_SIDE_EVER_SENT_GEN3 : 1; - unsigned int LC_OTHER_SIDE_SUPPORTS_GEN3 : 1; - unsigned int LC_AUTO_RECOVERY_DIS : 1; - unsigned int LC_SPEED_CHANGE_STATUS : 1; - unsigned int LC_DATA_RATE_ADVERTISED : 2; - unsigned int LC_CHECK_DATA_RATE : 1; - unsigned int LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN : 1; - unsigned int LC_INIT_SPEED_NEG_IN_L0s_EN : 1; - unsigned int LC_INIT_SPEED_NEG_IN_L1_EN : 1; - unsigned int LC_DONT_CHECK_EQTS_IN_RCFG : 1; - unsigned int LC_DELAY_COEFF_UPDATE_DIS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_SPEED_CNTL__SI { - struct { - unsigned int LC_GEN2_EN_STRAP : 1; - unsigned int LC_TARGET_LINK_SPEED_OVERRIDE_EN : 1; - unsigned int LC_TARGET_LINK_SPEED_OVERRIDE : 1; - unsigned int LC_FORCE_EN_SW_SPEED_CHANGE : 1; - unsigned int LC_FORCE_DIS_SW_SPEED_CHANGE : 1; - unsigned int LC_FORCE_EN_HW_SPEED_CHANGE : 1; - unsigned int LC_FORCE_DIS_HW_SPEED_CHANGE : 1; - unsigned int LC_INITIATE_LINK_SPEED_CHANGE : 1; - unsigned int LC_SPEED_CHANGE_ATTEMPTS_ALLOWED : 2; - unsigned int LC_SPEED_CHANGE_ATTEMPT_FAILED : 1; - unsigned int LC_CURRENT_DATA_RATE : 1; - unsigned int : 2; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS : 1; - unsigned int LC_CLR_FAILED_SPD_CHANGE_CNT : 1; - unsigned int LC_1_OR_MORE_TS2_SPEED_ARC_EN : 1; - unsigned int LC_OTHER_SIDE_EVER_SENT_GEN2 : 1; - unsigned int LC_OTHER_SIDE_SUPPORTS_GEN2 : 1; - unsigned int LC_AUTO_RECOVERY_DIS : 1; - unsigned int LC_SPEED_CHANGE_STATUS : 1; - unsigned int LC_DATA_RATE_ADVERTISED : 1; - unsigned int LC_CHECK_DATA_RATE : 1; - unsigned int LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN : 1; - unsigned int LC_INIT_SPEED_NEG_IN_L0s_EN : 1; - unsigned int LC_INIT_SPEED_NEG_IN_L1_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE0 { - struct { - unsigned int LC_CURRENT_STATE : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE1 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE2 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE3 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE1 { - struct { - unsigned int LC_PREV_STATE4 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE5 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE6 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE7 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE10 { - struct { - unsigned int LC_PREV_STATE40 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE41 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE42 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE43 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE11 { - struct { - unsigned int LC_PREV_STATE44 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE45 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE46 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE47 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE2 { - struct { - unsigned int LC_PREV_STATE8 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE9 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE10 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE11 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE3 { - struct { - unsigned int LC_PREV_STATE12 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE13 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE14 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE15 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE4 { - struct { - unsigned int LC_PREV_STATE16 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE17 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE18 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE19 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE5 { - struct { - unsigned int LC_PREV_STATE20 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE21 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE22 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE23 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE6 { - struct { - unsigned int LC_PREV_STATE24 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE25 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE26 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE27 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE7 { - struct { - unsigned int LC_PREV_STATE28 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE29 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE30 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE31 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE8 { - struct { - unsigned int LC_PREV_STATE32 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE33 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE34 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE35 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATE9 { - struct { - unsigned int LC_PREV_STATE36 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE37 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE38 : 6; - unsigned int : 2; - unsigned int LC_PREV_STATE39 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATUS1 { - struct { - unsigned int LC_REVERSE_RCVR : 1; - unsigned int LC_REVERSE_XMIT : 1; - unsigned int LC_OPERATING_LINK_WIDTH : 3; - unsigned int LC_DETECTED_LINK_WIDTH : 3; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_STATUS2 { - struct { - unsigned int LC_TOTAL_INACTIVE_LANES : 16; - unsigned int LC_TURN_ON_LANE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_TRAINING_CNTL__CI { - struct { - unsigned int LC_TRAINING_CNTL : 4; - unsigned int LC_COMPLIANCE_RECEIVE : 1; - unsigned int LC_LOOK_FOR_MORE_NON_MATCHING_TS1 : 1; - unsigned int LC_L0S_L1_TRAINING_CNTL_EN : 1; - unsigned int LC_L1_LONG_WAKE_FIX_EN : 1; - unsigned int LC_POWER_STATE : 3; - unsigned int LC_DONT_GO_TO_L0S_IF_L1_ARMED : 1; - unsigned int LC_INIT_SPD_CHG_WITH_CSR_EN : 1; - unsigned int LC_DISABLE_TRAINING_BIT_ARCH : 1; - unsigned int : 2; - unsigned int LC_EXTEND_WAIT_FOR_SKP : 1; - unsigned int LC_AUTONOMOUS_CHANGE_OFF : 1; - unsigned int LC_UPCONFIGURE_CAP_OFF : 1; - unsigned int LC_HW_LINK_DIS_EN : 1; - unsigned int LC_LINK_DIS_BY_HW : 1; - unsigned int LC_STATIC_TX_PIPE_COUNT_EN : 1; - unsigned int LC_ASPM_L1_NAK_TIMER_SEL : 2; - unsigned int LC_DONT_DEASSERT_RX_EN_IN_R_SPEED : 1; - unsigned int LC_DONT_DEASSERT_RX_EN_IN_TEST : 1; - unsigned int LC_RESET_ASPM_L1_NAK_TIMER : 1; - unsigned int LC_SHORT_RCFG_TIMEOUT : 1; - unsigned int LC_ALLOW_TX_L1_CONTROL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_TRAINING_CNTL__VI { - struct { - unsigned int LC_TRAINING_CNTL : 4; - unsigned int LC_COMPLIANCE_RECEIVE : 1; - unsigned int LC_LOOK_FOR_MORE_NON_MATCHING_TS1 : 1; - unsigned int LC_L0S_L1_TRAINING_CNTL_EN : 1; - unsigned int LC_L1_LONG_WAKE_FIX_EN : 1; - unsigned int LC_POWER_STATE : 3; - unsigned int LC_DONT_GO_TO_L0S_IF_L1_ARMED : 1; - unsigned int LC_INIT_SPD_CHG_WITH_CSR_EN : 1; - unsigned int LC_DISABLE_TRAINING_BIT_ARCH : 1; - unsigned int LC_WAIT_FOR_SETS_IN_RCFG : 1; - unsigned int LC_HOT_RESET_QUICK_EXIT_EN : 1; - unsigned int LC_EXTEND_WAIT_FOR_SKP : 1; - unsigned int LC_AUTONOMOUS_CHANGE_OFF : 1; - unsigned int LC_UPCONFIGURE_CAP_OFF : 1; - unsigned int LC_HW_LINK_DIS_EN : 1; - unsigned int LC_LINK_DIS_BY_HW : 1; - unsigned int LC_STATIC_TX_PIPE_COUNT_EN : 1; - unsigned int LC_ASPM_L1_NAK_TIMER_SEL : 2; - unsigned int LC_DONT_DEASSERT_RX_EN_IN_R_SPEED : 1; - unsigned int LC_DONT_DEASSERT_RX_EN_IN_TEST : 1; - unsigned int LC_RESET_ASPM_L1_NAK_TIMER : 1; - unsigned int LC_SHORT_RCFG_TIMEOUT : 1; - unsigned int LC_ALLOW_TX_L1_CONTROL : 1; - unsigned int LC_WAIT_FOR_FOM_VALID_AFTER_TRACK : 1; - unsigned int LC_EXTEND_EQ_REQ_TIME : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_TRAINING_CNTL__SI { - struct { - unsigned int LC_TRAINING_CNTL : 4; - unsigned int LC_COMPLIANCE_RECEIVE : 1; - unsigned int LC_LOOK_FOR_MORE_NON_MATCHING_TS1 : 1; - unsigned int LC_L0S_L1_TRAINING_CNTL_EN : 1; - unsigned int LC_L1_LONG_WAKE_FIX_EN : 1; - unsigned int LC_POWER_STATE : 3; - unsigned int LC_DONT_GO_TO_L0S_IF_L1_ARMED : 1; - unsigned int LC_INIT_SPD_CHG_WITH_CSR_EN : 1; - unsigned int : 3; - unsigned int LC_EXTEND_WAIT_FOR_SKP : 1; - unsigned int LC_AUTONOMOUS_CHANGE_OFF : 1; - unsigned int LC_UPCONFIGURE_CAP_OFF : 1; - unsigned int : 2; - unsigned int LC_STATIC_TX_PIPE_COUNT_EN : 1; - unsigned int LC_ASPM_L1_NAK_TIMER_SEL : 2; - unsigned int LC_DONT_DEASSERT_RX_EN_IN_R_SPEED : 1; - unsigned int LC_DONT_DEASSERT_RX_EN_IN_TEST : 1; - unsigned int LC_RESET_ASPM_L1_NAK_TIMER : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LINK_CNTL3__CI__VI { - struct { - unsigned int PERFORM_EQUALIZATION : 1; - unsigned int LINK_EQUALIZATION_REQ_INT_EN : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI { - struct { - unsigned int OUTSTAND_PAGE_REQ_ALLOC : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI { - struct { - unsigned int OUTSTAND_PAGE_REQ_CAPACITY : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PAGE_REQ_CNTL__CI__VI { - struct { - unsigned int PRI_ENABLE : 1; - unsigned int PRI_RESET : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PAGE_REQ_STATUS__CI__VI { - struct { - unsigned int RESPONSE_FAILURE : 1; - unsigned int UNEXPECTED_PAGE_REQ_GRP_INDEX : 1; - unsigned int : 6; - unsigned int STOPPED : 1; - unsigned int : 6; - unsigned int PRG_RESPONSE_PASID_REQUIRED__VI : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PASID_CAP__CI__VI { - struct { - unsigned int : 1; - unsigned int PASID_EXE_PERMISSION_SUPPORTED : 1; - unsigned int PASID_PRIV_MODE_SUPPORTED : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int MAX_PASID_WIDTH : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PASID_CNTL__CI__VI { - struct { - unsigned int PASID_ENABLE : 1; - unsigned int PASID_EXE_PERMISSION_ENABLE : 1; - unsigned int PASID_PRIV_MODE_SUPPORTED_ENABLE : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PASID_ENH_CAP_LIST__CI__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_CNTL_EVENT0_PORT_SEL { - struct { - unsigned int PERF0_PORT_SEL_TXCLK : 4; - unsigned int PERF0_PORT_SEL_MST_R_CLK : 4; - unsigned int PERF0_PORT_SEL_MST_C_CLK : 4; - unsigned int PERF0_PORT_SEL_SLV_R_CLK : 4; - unsigned int PERF0_PORT_SEL_SLV_S_C_CLK : 4; - unsigned int PERF0_PORT_SEL_SLV_NS_C_CLK : 4; - unsigned int PERF0_PORT_SEL_TXCLK2 : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_CNTL_EVENT1_PORT_SEL { - struct { - unsigned int PERF1_PORT_SEL_TXCLK : 4; - unsigned int PERF1_PORT_SEL_MST_R_CLK : 4; - unsigned int PERF1_PORT_SEL_MST_C_CLK : 4; - unsigned int PERF1_PORT_SEL_SLV_R_CLK : 4; - unsigned int PERF1_PORT_SEL_SLV_S_C_CLK : 4; - unsigned int PERF1_PORT_SEL_SLV_NS_C_CLK : 4; - unsigned int PERF1_PORT_SEL_TXCLK2 : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_CNTL_MST_C_CLK { - struct { - unsigned int EVENT0_SEL : 8; - unsigned int EVENT1_SEL : 8; - unsigned int COUNTER0_UPPER : 8; - unsigned int COUNTER1_UPPER : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_CNTL_MST_R_CLK { - struct { - unsigned int EVENT0_SEL : 8; - unsigned int EVENT1_SEL : 8; - unsigned int COUNTER0_UPPER : 8; - unsigned int COUNTER1_UPPER : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_CNTL_SLV_NS_C_CLK { - struct { - unsigned int EVENT0_SEL : 8; - unsigned int EVENT1_SEL : 8; - unsigned int COUNTER0_UPPER : 8; - unsigned int COUNTER1_UPPER : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_CNTL_SLV_R_CLK { - struct { - unsigned int EVENT0_SEL : 8; - unsigned int EVENT1_SEL : 8; - unsigned int COUNTER0_UPPER : 8; - unsigned int COUNTER1_UPPER : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_CNTL_SLV_S_C_CLK { - struct { - unsigned int EVENT0_SEL : 8; - unsigned int EVENT1_SEL : 8; - unsigned int COUNTER0_UPPER : 8; - unsigned int COUNTER1_UPPER : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_CNTL_TXCLK { - struct { - unsigned int EVENT0_SEL : 8; - unsigned int EVENT1_SEL : 8; - unsigned int COUNTER0_UPPER : 8; - unsigned int COUNTER1_UPPER : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_CNTL_TXCLK2 { - struct { - unsigned int EVENT0_SEL : 8; - unsigned int EVENT1_SEL : 8; - unsigned int COUNTER0_UPPER : 8; - unsigned int COUNTER1_UPPER : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT0_MST_C_CLK { - struct { - unsigned int COUNTER0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT0_MST_R_CLK { - struct { - unsigned int COUNTER0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT0_SLV_NS_C_CLK { - struct { - unsigned int COUNTER0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT0_SLV_R_CLK { - struct { - unsigned int COUNTER0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT0_SLV_S_C_CLK { - struct { - unsigned int COUNTER0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT0_TXCLK { - struct { - unsigned int COUNTER0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT0_TXCLK2 { - struct { - unsigned int COUNTER0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT1_MST_C_CLK { - struct { - unsigned int COUNTER1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT1_MST_R_CLK { - struct { - unsigned int COUNTER1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT1_SLV_NS_C_CLK { - struct { - unsigned int COUNTER1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT1_SLV_R_CLK { - struct { - unsigned int COUNTER1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT1_SLV_S_C_CLK { - struct { - unsigned int COUNTER1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT1_TXCLK { - struct { - unsigned int COUNTER1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT1_TXCLK2 { - struct { - unsigned int COUNTER1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PERF_COUNT_CNTL { - struct { - unsigned int GLOBAL_COUNT_EN : 1; - unsigned int GLOBAL_SHADOW_WR : 1; - unsigned int GLOBAL_COUNT_RESET : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PORT_DATA__SI { - struct { - unsigned int PCIE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PORT_INDEX__SI { - struct { - unsigned int PCIE_INDEX : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PORT_VC_CAP_REG1 { - struct { - unsigned int EXT_VC_COUNT : 3; - unsigned int : 1; - unsigned int LOW_PRIORITY_EXT_VC_COUNT : 3; - unsigned int : 1; - unsigned int REF_CLK : 2; - unsigned int PORT_ARB_TABLE_ENTRY_SIZE : 2; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PORT_VC_CAP_REG2 { - struct { - unsigned int VC_ARB_CAP : 8; - unsigned int : 16; - unsigned int VC_ARB_TABLE_OFFSET : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PORT_VC_CNTL { - struct { - unsigned int LOAD_VC_ARB_TABLE : 1; - unsigned int VC_ARB_SELECT : 3; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PORT_VC_STATUS { - struct { - unsigned int VC_ARB_TABLE_STATUS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_CLR { - struct { - unsigned int PRBS_CLR : 16; - unsigned int PRBS_CHECKER_DEBUG_BUS_SELECT : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_0 { - struct { - unsigned int PRBS_ERRCNT_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_1 { - struct { - unsigned int PRBS_ERRCNT_1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_10 { - struct { - unsigned int PRBS_ERRCNT_10 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_11 { - struct { - unsigned int PRBS_ERRCNT_11 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_12 { - struct { - unsigned int PRBS_ERRCNT_12 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_13 { - struct { - unsigned int PRBS_ERRCNT_13 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_14 { - struct { - unsigned int PRBS_ERRCNT_14 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_15 { - struct { - unsigned int PRBS_ERRCNT_15 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_2 { - struct { - unsigned int PRBS_ERRCNT_2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_3 { - struct { - unsigned int PRBS_ERRCNT_3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_4 { - struct { - unsigned int PRBS_ERRCNT_4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_5 { - struct { - unsigned int PRBS_ERRCNT_5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_6 { - struct { - unsigned int PRBS_ERRCNT_6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_7 { - struct { - unsigned int PRBS_ERRCNT_7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_8 { - struct { - unsigned int PRBS_ERRCNT_8 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_ERRCNT_9 { - struct { - unsigned int PRBS_ERRCNT_9 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_FREERUN { - struct { - unsigned int PRBS_FREERUN : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_HI_BITCNT { - struct { - unsigned int PRBS_HI_BITCNT : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_LO_BITCNT { - struct { - unsigned int PRBS_LO_BITCNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_MISC__CI { - struct { - unsigned int PRBS_EN : 1; - unsigned int PRBS_TEST_MODE : 2; - unsigned int PRBS_USER_PATTERN_TOGGLE : 1; - unsigned int PRBS_8BIT_SEL : 1; - unsigned int PRBS_COMMA_NUM : 2; - unsigned int PRBS_LOCK_CNT : 5; - unsigned int : 2; - unsigned int PRBS_DATA_RATE : 2; - unsigned int PRBS_CHK_ERR_MASK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_MISC__VI { - struct { - unsigned int PRBS_EN : 1; - unsigned int PRBS_TEST_MODE : 3; - unsigned int PRBS_USER_PATTERN_TOGGLE : 1; - unsigned int PRBS_8BIT_SEL : 1; - unsigned int PRBS_COMMA_NUM : 2; - unsigned int PRBS_LOCK_CNT : 5; - unsigned int : 1; - unsigned int PRBS_DATA_RATE : 2; - unsigned int PRBS_CHK_ERR_MASK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_MISC__SI { - struct { - unsigned int PRBS_EN : 1; - unsigned int PRBS_TEST_MODE : 2; - unsigned int PRBS_USER_PATTERN_TOGGLE : 1; - unsigned int PRBS_8BIT_SEL : 1; - unsigned int PRBS_COMMA_NUM : 2; - unsigned int PRBS_LOCK_CNT : 5; - unsigned int : 3; - unsigned int : 1; - unsigned int PRBS_CHK_ERR_MASK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_STATUS1 { - struct { - unsigned int PRBS_ERRSTAT : 16; - unsigned int PRBS_LOCKED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_STATUS2 { - struct { - unsigned int PRBS_BITCNT_DONE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_USER_PATTERN__CI__VI { - struct { - unsigned int PRBS_USER_PATTERN : 30; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PRBS_USER_PATTERN__SI { - struct { - unsigned int : 30; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PWR_BUDGET_CAP__CI__VI { - struct { - unsigned int SYSTEM_ALLOCATED : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PWR_BUDGET_DATA_SELECT__CI__VI { - struct { - unsigned int DATA_SELECT : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PWR_BUDGET_DATA__CI__VI { - struct { - unsigned int BASE_POWER : 8; - unsigned int DATA_SCALE : 2; - unsigned int PM_SUB_STATE : 3; - unsigned int PM_STATE : 2; - unsigned int TYPE : 3; - unsigned int POWER_RAIL : 3; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_P_BUF_STATUS__CI__VI { - struct { - unsigned int P_OVERFLOW_ERR : 16; - unsigned int P_UNDERFLOW_ERR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_P_BUF_STATUS__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_P_CNTL__CI__VI { - struct { - unsigned int P_PWRDN_EN : 1; - unsigned int P_SYMALIGN_MODE : 1; - unsigned int P_SYMALIGN_HW_DEBUG : 1; - unsigned int P_ELASTDESKEW_HW_DEBUG : 1; - unsigned int P_IGNORE_CRC_ERR : 1; - unsigned int P_IGNORE_LEN_ERR : 1; - unsigned int P_IGNORE_EDB_ERR : 1; - unsigned int P_IGNORE_IDL_ERR : 1; - unsigned int P_IGNORE_TOK_ERR : 1; - unsigned int : 3; - unsigned int P_BLK_LOCK_MODE : 1; - unsigned int P_ALWAYS_USE_FAST_TXCLK : 1; - unsigned int P_ELEC_IDLE_MODE : 2; - unsigned int DLP_IGNORE_IN_L1_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_P_CNTL__SI { - struct { - unsigned int P_PWRDN_EN : 1; - unsigned int P_SYMALIGN_MODE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int P_ALWAYS_USE_FAST_TXCLK : 1; - unsigned int P_ELEC_IDLE_MODE : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_P_DECODER_STATUS__CI__VI { - struct { - unsigned int P_DECODE_ERR : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_P_DECODER_STATUS__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_P_MISC_STATUS__CI__VI { - struct { - unsigned int P_DESKEW_ERR : 8; - unsigned int : 8; - unsigned int P_SYMUNLOCK_ERR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_P_PORT_LANE_STATUS { - struct { - unsigned int PORT_LANE_REVERSAL : 1; - unsigned int PHY_LINK_WIDTH : 6; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_P_RCV_L0S_FTS_DET__CI__VI { - struct { - unsigned int P_RCV_L0S_FTS_DET_MIN : 8; - unsigned int P_RCV_L0S_FTS_DET_MAX : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RESERVED { - struct { - unsigned int PCIE_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_CNTL2__CI__VI { - struct { - unsigned int RX_IGNORE_EP_INVALIDPASID_UR : 1; - unsigned int RX_IGNORE_EP_TRANSMRD_UR : 1; - unsigned int RX_IGNORE_EP_TRANSMWR_UR : 1; - unsigned int RX_IGNORE_EP_ATSTRANSREQ_UR : 1; - unsigned int RX_IGNORE_EP_PAGEREQMSG_UR : 1; - unsigned int RX_IGNORE_EP_INVCPL_UR : 1; - unsigned int : 2; - unsigned int RX_RCB_LATENCY_EN__VI : 1; - unsigned int RX_RCB_LATENCY_SCALE__VI : 3; - unsigned int : 4; - unsigned int RX_RCB_LATENCY_MAX_COUNT__VI : 10; - unsigned int : 2; - unsigned int FLR_EXTEND_MODE__VI : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_CNTL3__CI__VI { - struct { - unsigned int RX_IGNORE_RC_TRANSMRDPASID_UR : 1; - unsigned int RX_IGNORE_RC_TRANSMWRPASID_UR : 1; - unsigned int RX_IGNORE_RC_PRGRESPMSG_UR : 1; - unsigned int RX_IGNORE_RC_INVREQ_UR : 1; - unsigned int RX_IGNORE_RC_INVCPLPASID_UR : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_CNTL__CI__VI { - struct { - unsigned int RX_IGNORE_IO_ERR : 1; - unsigned int RX_IGNORE_BE_ERR : 1; - unsigned int RX_IGNORE_MSG_ERR : 1; - unsigned int RX_IGNORE_CRC_ERR : 1; - unsigned int RX_IGNORE_CFG_ERR : 1; - unsigned int RX_IGNORE_CPL_ERR : 1; - unsigned int RX_IGNORE_EP_ERR : 1; - unsigned int RX_IGNORE_LEN_MISMATCH_ERR : 1; - unsigned int RX_IGNORE_MAX_PAYLOAD_ERR : 1; - unsigned int RX_IGNORE_TC_ERR : 1; - unsigned int RX_IGNORE_CFG_UR : 1; - unsigned int RX_IGNORE_IO_UR : 1; - unsigned int RX_IGNORE_AT_ERR : 1; - unsigned int RX_NAK_IF_FIFO_FULL : 1; - unsigned int RX_GEN_ONE_NAK : 1; - unsigned int RX_FC_INIT_FROM_REG : 1; - unsigned int RX_RCB_CPL_TIMEOUT : 3; - unsigned int RX_RCB_CPL_TIMEOUT_MODE : 1; - unsigned int RX_PCIE_CPL_TIMEOUT_DIS : 1; - unsigned int RX_IGNORE_SHORTPREFIX_ERR : 1; - unsigned int RX_IGNORE_MAXPREFIX_ERR : 1; - unsigned int RX_IGNORE_CPLPREFIX_ERR : 1; - unsigned int RX_IGNORE_INVALIDPASID_ERR : 1; - unsigned int RX_IGNORE_NOT_PASID_UR : 1; - unsigned int RX_TPH_DIS__VI : 1; - unsigned int RX_RCB_FLR_TIMEOUT_DIS__VI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_CNTL__SI { - struct { - unsigned int RX_IGNORE_IO_ERR : 1; - unsigned int RX_IGNORE_BE_ERR : 1; - unsigned int RX_IGNORE_MSG_ERR : 1; - unsigned int RX_IGNORE_CRC_ERR : 1; - unsigned int RX_IGNORE_CFG_ERR : 1; - unsigned int RX_IGNORE_CPL_ERR : 1; - unsigned int RX_IGNORE_EP_ERR : 1; - unsigned int RX_IGNORE_LEN_MISMATCH_ERR : 1; - unsigned int RX_IGNORE_MAX_PAYLOAD_ERR : 1; - unsigned int RX_IGNORE_TC_ERR : 1; - unsigned int RX_IGNORE_CFG_UR : 1; - unsigned int RX_IGNORE_IO_UR : 1; - unsigned int : 1; - unsigned int RX_NAK_IF_FIFO_FULL : 1; - unsigned int RX_GEN_ONE_NAK : 1; - unsigned int RX_FC_INIT_FROM_REG : 1; - unsigned int RX_RCB_CPL_TIMEOUT : 3; - unsigned int RX_RCB_CPL_TIMEOUT_MODE : 1; - unsigned int RX_PCIE_CPL_TIMEOUT_DIS : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_CREDITS_ALLOCATED_CPL { - struct { - unsigned int RX_CREDITS_ALLOCATED_CPLD : 12; - unsigned int : 4; - unsigned int RX_CREDITS_ALLOCATED_CPLH : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_CREDITS_ALLOCATED_NP { - struct { - unsigned int RX_CREDITS_ALLOCATED_NPD : 12; - unsigned int : 4; - unsigned int RX_CREDITS_ALLOCATED_NPH : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_CREDITS_ALLOCATED_P { - struct { - unsigned int RX_CREDITS_ALLOCATED_PD : 12; - unsigned int : 4; - unsigned int RX_CREDITS_ALLOCATED_PH : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_EXPECTED_SEQNUM__CI__VI { - struct { - unsigned int RX_EXPECTED_SEQNUM : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_LAST_TLP0 { - struct { - unsigned int RX_LAST_TLP0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_LAST_TLP1 { - struct { - unsigned int RX_LAST_TLP1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_LAST_TLP2 { - struct { - unsigned int RX_LAST_TLP2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_LAST_TLP3 { - struct { - unsigned int RX_LAST_TLP3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_NUM_NAK_GENERATED__CI__VI { - struct { - unsigned int RX_NUM_NAK_GENERATED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_NUM_NAK__CI__VI { - struct { - unsigned int RX_NUM_NAK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RX_VENDOR_SPECIFIC { - struct { - unsigned int RX_VENDOR_DATA : 24; - unsigned int RX_VENDOR_STATUS : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SCRATCH { - struct { - unsigned int PCIE_SCRATCH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SECONDARY_ENH_CAP_LIST__CI__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_F0__CI { - struct { - unsigned int STRAP_F0_EN : 1; - unsigned int STRAP_F0_LEGACY_DEVICE_TYPE_EN : 1; - unsigned int STRAP_F0_MSI_EN : 1; - unsigned int STRAP_F0_VC_EN : 1; - unsigned int STRAP_F0_DSN_EN : 1; - unsigned int STRAP_F0_AER_EN : 1; - unsigned int STRAP_F0_ACS_EN : 1; - unsigned int STRAP_F0_BAR_EN : 1; - unsigned int STRAP_F0_PWR_EN : 1; - unsigned int STRAP_F0_DPA_EN : 1; - unsigned int STRAP_F0_ATS_EN : 1; - unsigned int STRAP_F0_PAGE_REQ_EN : 1; - unsigned int STRAP_F0_PASID_EN : 1; - unsigned int STRAP_F0_MC_EN : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_F0__VI { - struct { - unsigned int STRAP_F0_EN : 1; - unsigned int STRAP_F0_LEGACY_DEVICE_TYPE_EN : 1; - unsigned int STRAP_F0_MSI_EN : 1; - unsigned int STRAP_F0_VC_EN : 1; - unsigned int STRAP_F0_DSN_EN : 1; - unsigned int STRAP_F0_AER_EN : 1; - unsigned int STRAP_F0_ACS_EN : 1; - unsigned int STRAP_F0_BAR_EN : 1; - unsigned int STRAP_F0_PWR_EN : 1; - unsigned int STRAP_F0_DPA_EN : 1; - unsigned int STRAP_F0_ATS_EN : 1; - unsigned int STRAP_F0_PAGE_REQ_EN : 1; - unsigned int STRAP_F0_PASID_EN : 1; - unsigned int STRAP_F0_ECRC_CHECK_EN : 1; - unsigned int STRAP_F0_ECRC_GEN_EN : 1; - unsigned int STRAP_F0_CPL_ABORT_ERR_EN : 1; - unsigned int STRAP_F0_POISONED_ADVISORY_NONFATAL : 1; - unsigned int STRAP_F0_MC_EN : 1; - unsigned int STRAP_F0_ATOMIC_EN : 1; - unsigned int STRAP_F0_ATOMIC_64BIT_EN : 1; - unsigned int STRAP_F0_ATOMIC_ROUTING_EN : 1; - unsigned int STRAP_F0_MSI_MULTI_CAP : 3; - unsigned int STRAP_F0_VFn_MSI_MULTI_CAP : 3; - unsigned int STRAP_F0_MSI_PERVECTOR_MASK_CAP : 1; - unsigned int STRAP_F0_NO_RO_ENABLED_P2P_PASSING : 1; - unsigned int STRAP_F0_ARI_EN : 1; - unsigned int STRAP_F0_SRIOV_EN : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_F1__CI__VI { - struct { - unsigned int STRAP_F1_EN__SI__CI : 1; - unsigned int STRAP_F1_LEGACY_DEVICE_TYPE_EN : 1; - unsigned int STRAP_F1_MSI_EN : 1; - unsigned int STRAP_F1_VC_EN : 1; - unsigned int STRAP_F1_DSN_EN : 1; - unsigned int STRAP_F1_AER_EN : 1; - unsigned int STRAP_F1_ACS_EN : 1; - unsigned int STRAP_F1_BAR_EN : 1; - unsigned int STRAP_F1_PWR_EN : 1; - unsigned int STRAP_F1_DPA_EN : 1; - unsigned int STRAP_F1_ATS_EN : 1; - unsigned int STRAP_F1_PAGE_REQ_EN : 1; - unsigned int STRAP_F1_PASID_EN : 1; - unsigned int STRAP_F1_ECRC_CHECK_EN__VI : 1; - unsigned int STRAP_F1_ECRC_GEN_EN__VI : 1; - unsigned int STRAP_F1_CPL_ABORT_ERR_EN__VI : 1; - unsigned int STRAP_F1_POISONED_ADVISORY_NONFATAL__VI : 1; - unsigned int : 1; - unsigned int STRAP_F1_ATOMIC_EN__VI : 1; - unsigned int STRAP_F1_ATOMIC_64BIT_EN__VI : 1; - unsigned int STRAP_F1_ATOMIC_ROUTING_EN__VI : 1; - unsigned int STRAP_F1_MSI_MULTI_CAP__VI : 3; - unsigned int : 3; - unsigned int STRAP_F1_MSI_PERVECTOR_MASK_CAP__VI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_F2__CI__VI { - struct { - unsigned int STRAP_F2_EN__SI__CI : 1; - unsigned int STRAP_F2_LEGACY_DEVICE_TYPE_EN : 1; - unsigned int STRAP_F2_MSI_EN : 1; - unsigned int STRAP_F2_VC_EN : 1; - unsigned int STRAP_F2_DSN_EN : 1; - unsigned int STRAP_F2_AER_EN : 1; - unsigned int STRAP_F2_ACS_EN : 1; - unsigned int STRAP_F2_BAR_EN : 1; - unsigned int STRAP_F2_PWR_EN : 1; - unsigned int STRAP_F2_DPA_EN : 1; - unsigned int STRAP_F2_ATS_EN : 1; - unsigned int STRAP_F2_PAGE_REQ_EN : 1; - unsigned int STRAP_F2_PASID_EN : 1; - unsigned int STRAP_F2_ECRC_CHECK_EN__VI : 1; - unsigned int STRAP_F2_ECRC_GEN_EN__VI : 1; - unsigned int STRAP_F2_CPL_ABORT_ERR_EN__VI : 1; - unsigned int STRAP_F2_POISONED_ADVISORY_NONFATAL__VI : 1; - unsigned int : 1; - unsigned int STRAP_F2_ATOMIC_EN__VI : 1; - unsigned int STRAP_F2_ATOMIC_64BIT_EN__VI : 1; - unsigned int STRAP_F2_ATOMIC_ROUTING_EN__VI : 1; - unsigned int STRAP_F2_MSI_MULTI_CAP__VI : 3; - unsigned int : 3; - unsigned int STRAP_F2_MSI_PERVECTOR_MASK_CAP__VI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_F3__CI__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_F4__CI__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_F5__CI__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_F6__CI__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_F7__CI__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_I2C_BD { - struct { - unsigned int STRAP_BIF_I2C_SLV_ADR : 7; - unsigned int STRAP_BIF_DBG_I2C_EN : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_MISC2 { - struct { - unsigned int : 1; - unsigned int STRAP_GEN2_COMPLIANCE : 1; - unsigned int STRAP_MSTCPL_TIMEOUT_EN : 1; - unsigned int STRAP_GEN3_COMPLIANCE__CI__VI : 1; - unsigned int STRAP_TPH_SUPPORTED__CI__VI : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_MISC__CI__VI { - struct { - unsigned int STRAP_LINK_CONFIG__SI__CI : 4; - unsigned int STRAP_TL_ALT_BUF_EN : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int STRAP_MAX_PASID_WIDTH : 5; - unsigned int STRAP_PASID_EXE_PERMISSION_SUPPORTED : 1; - unsigned int STRAP_PASID_PRIV_MODE_SUPPORTED : 1; - unsigned int STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED : 1; - unsigned int : 8; - unsigned int STRAP_CLK_PM_EN : 1; - unsigned int STRAP_ECN1P1_EN : 1; - unsigned int STRAP_EXT_VC_COUNT : 1; - unsigned int : 1; - unsigned int STRAP_REVERSE_ALL : 1; - unsigned int STRAP_MST_ADR64_EN : 1; - unsigned int STRAP_FLR_EN : 1; - unsigned int STRAP_INTERNAL_ERR_EN__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_MISC__SI { - struct { - unsigned int STRAP_LINK_CONFIG : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int STRAP_CLK_PM_EN : 1; - unsigned int STRAP_ECN1P1_EN : 1; - unsigned int STRAP_EXT_VC_COUNT : 1; - unsigned int : 1; - unsigned int STRAP_REVERSE_ALL : 1; - unsigned int STRAP_MST_ADR64_EN : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_STRAP_PI { - struct { - unsigned int STRAP_QUICKSIM_START : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int : 4; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 4; - unsigned int : 1; - unsigned int : 2; - unsigned int STRAP_TEST_TOGGLE_PATTERN : 1; - unsigned int STRAP_TEST_TOGGLE_MODE : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TLP_PREFIX_LOG0__CI__VI { - struct { - unsigned int TLP_PREFIX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TLP_PREFIX_LOG1__CI__VI { - struct { - unsigned int TLP_PREFIX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TLP_PREFIX_LOG2__CI__VI { - struct { - unsigned int TLP_PREFIX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TLP_PREFIX_LOG3__CI__VI { - struct { - unsigned int TLP_PREFIX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_ACK_LATENCY_LIMIT__CI__VI { - struct { - unsigned int TX_ACK_LATENCY_LIMIT : 12; - unsigned int TX_ACK_LATENCY_LIMIT_OVERWRITE : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_ACK_LATENCY_LIMIT__SI { - struct { - unsigned int TX_ACK_LATENCY_LIMIT : 8; - unsigned int TX_ACK_LATENCY_LIMIT_OVERWRITE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_CNTL__CI__VI { - struct { - unsigned int : 10; - unsigned int TX_SNR_OVERRIDE : 2; - unsigned int TX_RO_OVERRIDE : 2; - unsigned int TX_PACK_PACKET_DIS : 1; - unsigned int TX_FLUSH_TLP_DIS : 1; - unsigned int : 4; - unsigned int TX_CPL_PASS_P : 1; - unsigned int TX_NP_PASS_P : 1; - unsigned int TX_CLEAR_EXTRA_PM_REQS : 1; - unsigned int TX_FC_UPDATE_TIMEOUT_DIS : 1; - unsigned int TX_F0_TPH_DIS : 1; - unsigned int TX_F1_TPH_DIS : 1; - unsigned int TX_F2_TPH_DIS : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_CNTL__SI { - struct { - unsigned int : 10; - unsigned int TX_SNR_OVERRIDE : 2; - unsigned int TX_RO_OVERRIDE : 2; - unsigned int TX_PACK_PACKET_DIS : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int TX_FLUSH_TLP_DIS : 1; - unsigned int TX_CPL_PASS_P : 1; - unsigned int TX_NP_PASS_P : 1; - unsigned int TX_CLEAR_EXTRA_PM_REQS : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int TX_FC_UPDATE_TIMEOUT : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_CREDITS_ADVT_CPL { - struct { - unsigned int TX_CREDITS_ADVT_CPLD : 12; - unsigned int : 4; - unsigned int TX_CREDITS_ADVT_CPLH : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_CREDITS_ADVT_NP { - struct { - unsigned int TX_CREDITS_ADVT_NPD : 12; - unsigned int : 4; - unsigned int TX_CREDITS_ADVT_NPH : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_CREDITS_ADVT_P { - struct { - unsigned int TX_CREDITS_ADVT_PD : 12; - unsigned int : 4; - unsigned int TX_CREDITS_ADVT_PH : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_CREDITS_FCU_THRESHOLD__CI__VI { - struct { - unsigned int TX_FCU_THRESHOLD_P_VC0 : 3; - unsigned int : 1; - unsigned int TX_FCU_THRESHOLD_NP_VC0 : 3; - unsigned int : 1; - unsigned int TX_FCU_THRESHOLD_CPL_VC0 : 3; - unsigned int : 5; - unsigned int TX_FCU_THRESHOLD_P_VC1 : 3; - unsigned int : 1; - unsigned int TX_FCU_THRESHOLD_NP_VC1 : 3; - unsigned int : 1; - unsigned int TX_FCU_THRESHOLD_CPL_VC1 : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_CREDITS_INIT_CPL { - struct { - unsigned int TX_CREDITS_INIT_CPLD : 12; - unsigned int : 4; - unsigned int TX_CREDITS_INIT_CPLH : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_CREDITS_INIT_NP { - struct { - unsigned int TX_CREDITS_INIT_NPD : 12; - unsigned int : 4; - unsigned int TX_CREDITS_INIT_NPH : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_CREDITS_INIT_P { - struct { - unsigned int TX_CREDITS_INIT_PD : 12; - unsigned int : 4; - unsigned int TX_CREDITS_INIT_PH : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_CREDITS_STATUS { - struct { - unsigned int TX_CREDITS_ERR_PD : 1; - unsigned int TX_CREDITS_ERR_PH : 1; - unsigned int TX_CREDITS_ERR_NPD : 1; - unsigned int TX_CREDITS_ERR_NPH : 1; - unsigned int TX_CREDITS_ERR_CPLD : 1; - unsigned int TX_CREDITS_ERR_CPLH : 1; - unsigned int : 10; - unsigned int TX_CREDITS_CUR_STATUS_PD : 1; - unsigned int TX_CREDITS_CUR_STATUS_PH : 1; - unsigned int TX_CREDITS_CUR_STATUS_NPD : 1; - unsigned int TX_CREDITS_CUR_STATUS_NPH : 1; - unsigned int TX_CREDITS_CUR_STATUS_CPLD : 1; - unsigned int TX_CREDITS_CUR_STATUS_CPLH : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_F0_ATTR_CNTL__CI__VI { - struct { - unsigned int TX_F0_IDO_OVERRIDE_P : 2; - unsigned int TX_F0_IDO_OVERRIDE_NP : 2; - unsigned int TX_F0_IDO_OVERRIDE_CPL : 2; - unsigned int TX_F0_RO_OVERRIDE_P : 2; - unsigned int TX_F0_RO_OVERRIDE_NP : 2; - unsigned int TX_F0_SNR_OVERRIDE_P : 2; - unsigned int TX_F0_SNR_OVERRIDE_NP : 2; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_F1_F2_ATTR_CNTL__CI__VI { - struct { - unsigned int TX_F1_IDO_OVERRIDE_P : 2; - unsigned int TX_F1_IDO_OVERRIDE_NP : 2; - unsigned int TX_F1_IDO_OVERRIDE_CPL : 2; - unsigned int TX_F1_RO_OVERRIDE_P : 2; - unsigned int TX_F1_RO_OVERRIDE_NP : 2; - unsigned int TX_F1_SNR_OVERRIDE_P : 2; - unsigned int TX_F1_SNR_OVERRIDE_NP : 2; - unsigned int : 2; - unsigned int TX_F2_IDO_OVERRIDE_P : 2; - unsigned int TX_F2_IDO_OVERRIDE_NP : 2; - unsigned int TX_F2_IDO_OVERRIDE_CPL : 2; - unsigned int TX_F2_RO_OVERRIDE_P : 2; - unsigned int TX_F2_RO_OVERRIDE_NP : 2; - unsigned int TX_F2_SNR_OVERRIDE_P : 2; - unsigned int TX_F2_SNR_OVERRIDE_NP : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_LAST_TLP0 { - struct { - unsigned int TX_LAST_TLP0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_LAST_TLP1 { - struct { - unsigned int TX_LAST_TLP1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_LAST_TLP2 { - struct { - unsigned int TX_LAST_TLP2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_LAST_TLP3 { - struct { - unsigned int TX_LAST_TLP3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_REPLAY { - struct { - unsigned int TX_REPLAY_NUM : 10; - unsigned int : 5; - unsigned int TX_REPLAY_TIMER_OVERWRITE : 1; - unsigned int TX_REPLAY_TIMER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_REQUESTER_ID { - struct { - unsigned int TX_REQUESTER_ID_FUNCTION : 3; - unsigned int TX_REQUESTER_ID_DEVICE : 5; - unsigned int TX_REQUESTER_ID_BUS : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_REQUEST_NUM_CNTL { - struct { - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int TX_NUM_OUTSTANDING_NP : 6; - unsigned int TX_NUM_OUTSTANDING_NP_VC1_EN : 1; - unsigned int TX_NUM_OUTSTANDING_NP_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_SEQ { - struct { - unsigned int TX_NEXT_TRANSMIT_SEQ : 12; - unsigned int : 4; - unsigned int TX_ACKD_SEQ : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_VENDOR_SPECIFIC { - struct { - unsigned int TX_VENDOR_DATA : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_UNCORR_ERR_MASK { - struct { - unsigned int : 4; - unsigned int DLP_ERR_MASK : 1; - unsigned int SURPDN_ERR_MASK : 1; - unsigned int : 6; - unsigned int PSN_ERR_MASK : 1; - unsigned int FC_ERR_MASK : 1; - unsigned int CPL_TIMEOUT_MASK : 1; - unsigned int CPL_ABORT_ERR_MASK : 1; - unsigned int UNEXP_CPL_MASK : 1; - unsigned int RCV_OVFL_MASK : 1; - unsigned int MAL_TLP_MASK : 1; - unsigned int ECRC_ERR_MASK : 1; - unsigned int UNSUPP_REQ_ERR_MASK : 1; - unsigned int ACS_VIOLATION_MASK : 1; - unsigned int UNCORR_INT_ERR_MASK__CI__VI : 1; - unsigned int MC_BLOCKED_TLP_MASK__CI__VI : 1; - unsigned int ATOMICOP_EGRESS_BLOCKED_MASK__CI__VI : 1; - unsigned int TLP_PREFIX_BLOCKED_ERR_MASK__CI__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_UNCORR_ERR_SEVERITY { - struct { - unsigned int : 4; - unsigned int DLP_ERR_SEVERITY : 1; - unsigned int SURPDN_ERR_SEVERITY : 1; - unsigned int : 6; - unsigned int PSN_ERR_SEVERITY : 1; - unsigned int FC_ERR_SEVERITY : 1; - unsigned int CPL_TIMEOUT_SEVERITY : 1; - unsigned int CPL_ABORT_ERR_SEVERITY : 1; - unsigned int UNEXP_CPL_SEVERITY : 1; - unsigned int RCV_OVFL_SEVERITY : 1; - unsigned int MAL_TLP_SEVERITY : 1; - unsigned int ECRC_ERR_SEVERITY : 1; - unsigned int UNSUPP_REQ_ERR_SEVERITY : 1; - unsigned int ACS_VIOLATION_SEVERITY : 1; - unsigned int UNCORR_INT_ERR_SEVERITY__CI__VI : 1; - unsigned int MC_BLOCKED_TLP_SEVERITY__CI__VI : 1; - unsigned int ATOMICOP_EGRESS_BLOCKED_SEVERITY__CI__VI : 1; - unsigned int TLP_PREFIX_BLOCKED_ERR_SEVERITY__CI__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_UNCORR_ERR_STATUS { - struct { - unsigned int : 4; - unsigned int DLP_ERR_STATUS : 1; - unsigned int SURPDN_ERR_STATUS : 1; - unsigned int : 6; - unsigned int PSN_ERR_STATUS : 1; - unsigned int FC_ERR_STATUS : 1; - unsigned int CPL_TIMEOUT_STATUS : 1; - unsigned int CPL_ABORT_ERR_STATUS : 1; - unsigned int UNEXP_CPL_STATUS : 1; - unsigned int RCV_OVFL_STATUS : 1; - unsigned int MAL_TLP_STATUS : 1; - unsigned int ECRC_ERR_STATUS : 1; - unsigned int UNSUPP_REQ_ERR_STATUS : 1; - unsigned int ACS_VIOLATION_STATUS : 1; - unsigned int UNCORR_INT_ERR_STATUS__CI__VI : 1; - unsigned int MC_BLOCKED_TLP_STATUS__CI__VI : 1; - unsigned int ATOMICOP_EGRESS_BLOCKED_STATUS__CI__VI : 1; - unsigned int TLP_PREFIX_BLOCKED_ERR_STATUS__CI__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VC0_RESOURCE_CAP { - struct { - unsigned int PORT_ARB_CAP : 8; - unsigned int : 7; - unsigned int REJECT_SNOOP_TRANS : 1; - unsigned int MAX_TIME_SLOTS : 6; - unsigned int : 2; - unsigned int PORT_ARB_TABLE_OFFSET : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VC0_RESOURCE_CNTL { - struct { - unsigned int TC_VC_MAP_TC0 : 1; - unsigned int TC_VC_MAP_TC1_7 : 7; - unsigned int : 8; - unsigned int LOAD_PORT_ARB_TABLE : 1; - unsigned int PORT_ARB_SELECT : 3; - unsigned int : 4; - unsigned int VC_ID : 3; - unsigned int : 4; - unsigned int VC_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VC0_RESOURCE_STATUS { - struct { - unsigned int PORT_ARB_TABLE_STATUS : 1; - unsigned int VC_NEGOTIATION_PENDING : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VC1_RESOURCE_CAP { - struct { - unsigned int PORT_ARB_CAP : 8; - unsigned int : 7; - unsigned int REJECT_SNOOP_TRANS : 1; - unsigned int MAX_TIME_SLOTS : 6; - unsigned int : 2; - unsigned int PORT_ARB_TABLE_OFFSET : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VC1_RESOURCE_CNTL { - struct { - unsigned int TC_VC_MAP_TC0 : 1; - unsigned int TC_VC_MAP_TC1_7 : 7; - unsigned int : 8; - unsigned int LOAD_PORT_ARB_TABLE : 1; - unsigned int PORT_ARB_SELECT : 3; - unsigned int : 4; - unsigned int VC_ID : 3; - unsigned int : 4; - unsigned int VC_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VC1_RESOURCE_STATUS { - struct { - unsigned int PORT_ARB_TABLE_STATUS : 1; - unsigned int VC_NEGOTIATION_PENDING : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VC_ENH_CAP_LIST { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VENDOR_SPECIFIC1 { - struct { - unsigned int SCRATCH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VENDOR_SPECIFIC2 { - struct { - unsigned int SCRATCH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VENDOR_SPECIFIC_HDR { - struct { - unsigned int VSEC_ID : 16; - unsigned int VSEC_REV : 4; - unsigned int VSEC_LENGTH : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_WPR_CNTL { - struct { - unsigned int WPR_RESET_HOT_RST_EN : 1; - unsigned int WPR_RESET_LNK_DWN_EN : 1; - unsigned int WPR_RESET_LNK_DIS_EN : 1; - unsigned int WPR_RESET_COR_EN : 1; - unsigned int WPR_RESET_REG_EN : 1; - unsigned int WPR_RESET_STY_EN : 1; - unsigned int WPR_RESET_PHY_EN : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PEER0_FB_OFFSET_HI__CI__VI { - struct { - unsigned int PEER0_FB_OFFSET_HI : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PEER0_FB_OFFSET_LO__CI__VI { - struct { - unsigned int PEER0_FB_OFFSET_LO : 20; - unsigned int : 11; - unsigned int PEER0_FB_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PEER1_FB_OFFSET_HI__CI__VI { - struct { - unsigned int PEER1_FB_OFFSET_HI : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PEER1_FB_OFFSET_LO__CI__VI { - struct { - unsigned int PEER1_FB_OFFSET_LO : 20; - unsigned int : 11; - unsigned int PEER1_FB_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PEER2_FB_OFFSET_HI__CI__VI { - struct { - unsigned int PEER2_FB_OFFSET_HI : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PEER2_FB_OFFSET_LO__CI__VI { - struct { - unsigned int PEER2_FB_OFFSET_LO : 20; - unsigned int : 11; - unsigned int PEER2_FB_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PEER3_FB_OFFSET_HI__CI__VI { - struct { - unsigned int PEER3_FB_OFFSET_HI : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PEER3_FB_OFFSET_LO__CI__VI { - struct { - unsigned int PEER3_FB_OFFSET_LO : 20; - unsigned int : 11; - unsigned int PEER3_FB_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PEER_REG_RANGE0 { - struct { - unsigned int START_ADDR : 16; - unsigned int END_ADDR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PEER_REG_RANGE1 { - struct { - unsigned int START_ADDR : 16; - unsigned int END_ADDR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PHY_AUX_CNTL__SI__VI { - struct { - unsigned int AUXSLAVE_PAD_SLEWN__VI : 1; - unsigned int AUXSLAVE_PAD_WAKE__VI : 1; - unsigned int AUXSLAVE_PAD_RXSEL__VI : 1; - unsigned int AUXSLAVE_PAD_MODE__VI : 1; - unsigned int DDCSLAVE_DATA_PD_EN__VI : 1; - unsigned int DDCSLAVE_DATA_EN__VI : 1; - unsigned int DDCSLAVE_CLK_PD_EN__VI : 1; - unsigned int DDCSLAVE_CLK_EN__VI : 1; - unsigned int : 4; - unsigned int AUX_PAD_SLEWN : 1; - unsigned int AUXSLAVE_CLK_PD_EN__VI : 1; - unsigned int AUX_PAD_WAKE : 1; - unsigned int : 1; - unsigned int AUX_PAD_RXSEL : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE0_ARBITRATION_CONTROL3__SI__VI { - struct { - unsigned int EFFICIENCY_WEIGHT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE1_ARBITRATION_CONTROL3__SI__VI { - struct { - unsigned int EFFICIENCY_WEIGHT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE2_ARBITRATION_CONTROL3__SI__VI { - struct { - unsigned int EFFICIENCY_WEIGHT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE3_ARBITRATION_CONTROL3__SI__VI { - struct { - unsigned int EFFICIENCY_WEIGHT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE4_ARBITRATION_CONTROL3__SI__VI { - struct { - unsigned int EFFICIENCY_WEIGHT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE5_ARBITRATION_CONTROL3__SI__VI { - struct { - unsigned int EFFICIENCY_WEIGHT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIXCLK1_RESYNC_CNTL__SI__VI { - struct { - unsigned int PIXCLK1_RESYNC_ENABLE : 1; - unsigned int : 3; - unsigned int DCCG_DEEP_COLOR_CNTL1 : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIXCLK2_RESYNC_CNTL__SI__VI { - struct { - unsigned int PIXCLK2_RESYNC_ENABLE : 1; - unsigned int : 3; - unsigned int DCCG_DEEP_COLOR_CNTL2 : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_TEST_CNTL { - struct { - unsigned int TST_SRC_SEL : 4; - unsigned int TST_REF_SEL : 4; - unsigned int REF_TEST_COUNT : 7; - unsigned int TST_RESET : 1; - unsigned int : 1; - unsigned int TEST_COUNT : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PMI_CAP { - struct { - unsigned int VERSION : 3; - unsigned int PME_CLOCK : 1; - unsigned int : 1; - unsigned int DEV_SPECIFIC_INIT : 1; - unsigned int AUX_CURRENT : 3; - unsigned int D1_SUPPORT : 1; - unsigned int D2_SUPPORT : 1; - unsigned int PME_SUPPORT : 5; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PMI_CAP_LIST { - struct { - unsigned int CAP_ID : 8; - unsigned int NEXT_PTR : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PMI_STATUS_CNTL { - struct { - unsigned int POWER_STATE : 2; - unsigned int : 1; - unsigned int NO_SOFT_RESET : 1; - unsigned int : 4; - unsigned int PME_EN : 1; - unsigned int DATA_SELECT : 4; - unsigned int DATA_SCALE : 2; - unsigned int PME_STATUS : 1; - unsigned int : 6; - unsigned int B2_B3_SUPPORT : 1; - unsigned int BUS_PWR_EN : 1; - unsigned int PMI_DATA : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PROG_INTERFACE { - struct { - unsigned int PROG_INTERFACE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_BCI_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_BCI_SIGNATURE1 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_CB_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_DB_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_IA_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_IA_SIGNATURE1 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_PA_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SC_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SC_SIGNATURE1 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SC_SIGNATURE2 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SC_SIGNATURE3 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SC_SIGNATURE4 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SC_SIGNATURE5 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SC_SIGNATURE6 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SC_SIGNATURE7 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SIGNATURE_CONTROL { - struct { - unsigned int ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SIGNATURE_MASK { - struct { - unsigned int INPUT_BUS_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SPI_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SPI_SIGNATURE1 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SQ_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SX_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SX_SIGNATURE1 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SX_SIGNATURE2 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_SX_SIGNATURE3 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_TA_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_TD_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_VGT_SIGNATURE0 { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RCU_MISC_CTRL__CI__VI { - struct { - unsigned int : 1; - unsigned int REG_DRV_RST_MODE : 1; - unsigned int : 1; - unsigned int REG_RCU_MEMREP_DIS : 1; - unsigned int REG_CC_FUSE_DISABLE : 1; - unsigned int REG_SAMU_FUSE_DISABLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int REG_CC_SRBM_RD_DISABLE : 1; - unsigned int : 7; - unsigned int BREAK_PT1_DONE : 1; - unsigned int BREAK_PT2_DONE : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int SAMU_START : 1; - unsigned int RST_PULSE_WIDTH : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RCU_MISC_CTRL__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int RST_PULSE_WIDTH : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RCU_UC_EVENTS__CI__VI { - struct { - unsigned int RCU_TST_jpc_rep_req : 1; - unsigned int TST_RCU_jpc_rep_done : 1; - unsigned int drv_rst_mode : 1; - unsigned int SMU_DC_efuse_status_invalid : 1; - unsigned int : 2; - unsigned int TP_Tester : 1; - unsigned int boot_seq_done : 1; - unsigned int sclk_deep_sleep_exit : 1; - unsigned int BREAK_PT1_ACTIVE : 1; - unsigned int BREAK_PT2_ACTIVE : 1; - unsigned int FCH_HALT : 1; - unsigned int : 1; - unsigned int RCU_GIO_fch_lockdown : 1; - unsigned int : 2; - unsigned int INTERRUPTS_ENABLED : 1; - unsigned int RCU_DtmCnt0_Done : 1; - unsigned int RCU_DtmCnt1_Done : 1; - unsigned int RCU_DtmCnt2_Done : 1; - unsigned int : 4; - unsigned int : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RCU_UC_EVENTS__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 7; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RESPONSE_INTERRUPT_COUNT__SI__VI { - struct { - unsigned int N_RESPONSE_INTERRUPT_COUNT : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REVISION_ID { - struct { - unsigned int MINOR_REV_ID : 4; - unsigned int MAJOR_REV_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RE_STAT__SI__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RINGOSC_MASK { - struct { - unsigned int MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RIRB_CONTROL__SI__VI { - struct { - unsigned int RESPONSE_INTERRUPT_CONTROL : 1; - unsigned int RIRB_DMA_ENABLE : 1; - unsigned int RESPONSE_OVERRUN_INTERRUPT_CONTROL : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RIRB_LOWER_BASE_ADDRESS__SI__VI { - struct { - unsigned int RIRB_LOWER_BASE_UNIMPLEMENTED_BITS : 7; - unsigned int RIRB_LOWER_BASE_ADDRESS : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RIRB_SIZE__SI__VI { - struct { - unsigned int RIRB_SIZE : 2; - unsigned int : 2; - unsigned int RIRB_SIZE_CAPABILITY : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RIRB_STATUS__SI__VI { - struct { - unsigned int RESPONSE_INTERRUPT : 1; - unsigned int : 1; - unsigned int RESPONSE_OVERRUN_INTERRUPT_STATUS : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RIRB_UPPER_BASE_ADDRESS__SI__VI { - struct { - unsigned int RIRB_UPPER_BASE_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RIRB_WRITE_POINTER__SI__VI { - struct { - unsigned int RIRB_WRITE_POINTER : 8; - unsigned int : 7; - unsigned int RIRB_WRITE_POINTER_RESET : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_AUTO_PG_CTRL { - struct { - unsigned int AUTO_PG_EN : 1; - unsigned int AUTO_GRBM_REG_SAVE_ON_IDLE_EN : 1; - unsigned int AUTO_WAKE_UP_EN : 1; - unsigned int GRBM_REG_SAVE_GFX_IDLE_THRESHOLD : 16; - unsigned int PG_AFTER_GRBM_REG_SAVE_THRESHOLD : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CAPTURE_GPU_CLOCK_COUNT { - struct { - unsigned int CAPTURE : 1; - unsigned int RESERVED : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CGCG_CGLS_CTRL__CI { - struct { - unsigned int CGCG_EN : 1; - unsigned int CGLS_EN : 1; - unsigned int CGLS_REP_COMPANSAT_DELAY : 6; - unsigned int CGCG_GFX_IDLE_THRESHOLD : 19; - unsigned int CGCG_CONTROLLER : 1; - unsigned int CGCG_REG_CTRL : 1; - unsigned int SLEEP_MODE : 2; - unsigned int SPARE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CGCG_CGLS_CTRL__VI { - struct { - unsigned int CGCG_EN : 1; - unsigned int CGLS_EN : 1; - unsigned int CGLS_REP_COMPANSAT_DELAY : 6; - unsigned int CGCG_GFX_IDLE_THRESHOLD : 19; - unsigned int CGCG_CONTROLLER : 1; - unsigned int CGCG_REG_CTRL : 1; - unsigned int SLEEP_MODE : 2; - unsigned int SIM_SILICON_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CGCG_CGLS_CTRL__SI { - struct { - unsigned int CGCG_EN : 1; - unsigned int CGLS_EN : 1; - unsigned int CGLS_REP_COMPANSAT_DELAY : 6; - unsigned int CGCG_GFX_IDLE_THRESHOLD : 8; - unsigned int : 11; - unsigned int CGCG_CONTROLLER : 1; - unsigned int CGCG_REG_CTRL : 1; - unsigned int SLEEP_MODE : 2; - unsigned int SPARE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CGCG_RAMP_CTRL { - struct { - unsigned int DOWN_DIV_START_UNIT : 4; - unsigned int DOWN_DIV_STEP_UNIT : 4; - unsigned int UP_DIV_START_UNIT : 4; - unsigned int UP_DIV_STEP_UNIT : 4; - unsigned int STEP_DELAY_CNT : 12; - unsigned int STEP_DELAY_UNIT : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CGTT_MGCG_OVERRIDE { - struct { - unsigned int OVERRIDE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CNTL { - struct { - unsigned int RLC_ENABLE_F32 : 1; - unsigned int FORCE_RETRY : 1; - unsigned int READ_CACHE_DISABLE : 1; - unsigned int RLC_STEP_F32 : 1; - unsigned int SOFT_RESET_DEBUG_MODE : 1; - unsigned int : 3; - unsigned int RESERVED : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CU_STATUS__CI__VI { - struct { - unsigned int WORK_PENDING : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CU_STATUS__SI { - struct { - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_DEBUG { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_DEBUG_SELECT { - struct { - unsigned int SELECT : 8; - unsigned int : 6; - unsigned int : 1; - unsigned int RESERVED : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_DRIVER_CPDMA_STATUS { - struct { - unsigned int DRIVER_REQUEST : 1; - unsigned int RESERVED1 : 3; - unsigned int DRIVER_ACK : 1; - unsigned int RESERVED : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_DYN_PG_REQUEST__CI__VI { - struct { - unsigned int PG_REQUEST_CU_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_DYN_PG_REQUEST__SI { - struct { - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_DYN_PG_STATUS__CI__VI { - struct { - unsigned int PG_STATUS_CU_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_DYN_PG_STATUS__SI { - struct { - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_CU_PD_TIMEOUT__CI__VI { - struct { - unsigned int TIMEOUT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_DEBUG_SELECT__CI__VI { - struct { - unsigned int SELECT : 8; - unsigned int F32_DEBUG_SELECT__VI : 2; - unsigned int RESERVED__VI : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_DEBUG__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_GENERAL_0__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_GENERAL_1__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_GENERAL_2__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_GENERAL_3__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_GENERAL_4__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_GENERAL_5__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_GENERAL_6__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_GENERAL_7__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_LOG_ADDR__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_LOG_CONT__CI__VI { - struct { - unsigned int CONT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_LOG_SIZE__CI__VI { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_PERF_COUNT_0__CI__VI { - struct { - unsigned int FEATURE_SEL : 4; - unsigned int SE_INDEX : 4; - unsigned int SH_INDEX : 4; - unsigned int CU_INDEX : 4; - unsigned int EVENT_SEL : 2; - unsigned int : 2; - unsigned int ENABLE : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_PERF_COUNT_1__CI__VI { - struct { - unsigned int FEATURE_SEL : 4; - unsigned int SE_INDEX : 4; - unsigned int SH_INDEX : 4; - unsigned int CU_INDEX : 4; - unsigned int EVENT_SEL : 2; - unsigned int : 2; - unsigned int ENABLE : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_SCRATCH_ADDR__CI__VI { - struct { - unsigned int ADDR : 9; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_SCRATCH_DATA__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_STAT__CI__VI { - struct { - unsigned int RLC_BUSY : 1; - unsigned int GFX_POWER_STATUS : 1; - unsigned int GFX_CLOCK_STATUS : 1; - unsigned int GFX_LS_STATUS : 1; - unsigned int GFX_PIPELINE_POWER_STATUS__VI : 1; - unsigned int CNTX_IDLE_BEING_PROCESSED__VI : 1; - unsigned int CNTX_BUSY_BEING_PROCESSED__VI : 1; - unsigned int GFX_IDLE_BEING_PROCESSED__VI : 1; - unsigned int CMP_BUSY_BEING_PROCESSED__VI : 1; - unsigned int SAVING_REGISTERS__VI : 1; - unsigned int RESTORING_REGISTERS__VI : 1; - unsigned int GFX3D_BLOCKS_CHANGING_POWER_STATE__VI : 1; - unsigned int CMP_BLOCKS_CHANGING_POWER_STATE__VI : 1; - unsigned int STATIC_CU_POWERING_UP__VI : 1; - unsigned int STATIC_CU_POWERING_DOWN__VI : 1; - unsigned int DYN_CU_POWERING_UP__VI : 1; - unsigned int DYN_CU_POWERING_DOWN__VI : 1; - unsigned int ABORTED_PD_SEQUENCE__VI : 1; - unsigned int RESERVED__VI : 6; - unsigned int PG_ERROR_STATUS__VI : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_THREAD_ENABLE__CI__VI { - struct { - unsigned int THREAD0_ENABLE : 1; - unsigned int THREAD1_ENABLE : 1; - unsigned int THREAD2_ENABLE : 1; - unsigned int THREAD3_ENABLE : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_THREAD_PRIORITY__CI__VI { - struct { - unsigned int THREAD0_PRIORITY : 8; - unsigned int THREAD1_PRIORITY : 8; - unsigned int THREAD2_PRIORITY : 8; - unsigned int THREAD3_PRIORITY : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_UCODE_ADDR__CI__VI { - struct { - unsigned int UCODE_ADDR : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_UCODE_DATA__CI__VI { - struct { - unsigned int UCODE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_VMID_THREAD0__CI__VI { - struct { - unsigned int RLC_VMID : 4; - unsigned int : 4; - unsigned int RLC_QUEUEID__VI : 3; - unsigned int RESERVED1__VI : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_VMID_THREAD1__CI__VI { - struct { - unsigned int RLC_VMID : 4; - unsigned int : 4; - unsigned int RLC_QUEUEID__VI : 3; - unsigned int RESERVED1__VI : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPR_REG1__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPR_REG2__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_CLOCK_32 { - struct { - unsigned int GPU_CLOCK_32 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_CLOCK_32_RES_SEL { - struct { - unsigned int RES_SEL : 6; - unsigned int RESERVED : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_CLOCK_COUNT_LSB { - struct { - unsigned int GPU_CLOCKS_LSB : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_CLOCK_COUNT_MSB { - struct { - unsigned int GPU_CLOCKS_MSB : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_JUMP_TABLE_RESTORE__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_LB_ALWAYS_ACTIVE_CU_MASK__CI__VI { - struct { - unsigned int ALWAYS_ACTIVE_CU_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_LB_ALWAYS_ACTIVE_CU_MASK__SI { - struct { - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_LB_CNTL { - struct { - unsigned int LOAD_BALANCE_ENABLE : 1; - unsigned int LB_CNT_CP_BUSY : 1; - unsigned int LB_CNT_SPIM_ACTIVE : 1; - unsigned int LB_CNT_REG_INC : 1; - unsigned int CU_MASK_USED_OFF_HYST__CI__VI : 8; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_LB_CNTR_INIT { - struct { - unsigned int LB_CNTR_INIT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_LB_CNTR_MAX { - struct { - unsigned int LB_CNTR_MAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_LB_INIT_CU_MASK__CI__VI { - struct { - unsigned int INIT_CU_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_LB_INIT_CU_MASK__SI { - struct { - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_LB_PARAMS { - struct { - unsigned int SKIP_L2_CHECK : 1; - unsigned int FIFO_SAMPLES : 7; - unsigned int PG_IDLE_SAMPLES : 8; - unsigned int PG_IDLE_SAMPLE_INTERVAL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_LOAD_BALANCE_CNTR { - struct { - unsigned int RLC_LOAD_BALANCE_CNTR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_MAX_PG_CU { - struct { - unsigned int MAX_POWERED_UP_CU : 8; - unsigned int SPARE : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_MC_CNTL { - struct { - unsigned int WRREQ_SWAP : 2; - unsigned int WRREQ_TRAN : 1; - unsigned int WRREQ_PRIV : 1; - unsigned int WRNFO_STALL : 1; - unsigned int WRNFO_URG : 4; - unsigned int WRREQ_DW_IMASK : 4; - unsigned int RESERVED_B : 7; - unsigned int RDNFO_URG : 4; - unsigned int RDREQ_SWAP : 2; - unsigned int RDREQ_TRAN : 1; - unsigned int RDREQ_PRIV : 1; - unsigned int RDNFO_STALL : 1; - unsigned int RESERVED : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_MEM_SLP_CNTL { - struct { - unsigned int RLC_MEM_LS_EN : 1; - unsigned int RLC_MEM_DS_EN : 1; - unsigned int RESERVED__VI : 5; - unsigned int RLC_LS_DS_BUSY_OVERRIDE__VI : 1; - unsigned int RLC_MEM_LS_ON_DELAY : 8; - unsigned int RLC_MEM_LS_OFF_DELAY : 8; - unsigned int RESERVED1 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PERFCOUNTER0_SELECT { - struct { - unsigned int PERFCOUNTER_SELECT : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PERFCOUNTER1_SELECT { - struct { - unsigned int PERFCOUNTER_SELECT : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PERFMON_CNTL { - struct { - unsigned int PERFMON_STATE : 3; - unsigned int : 7; - unsigned int PERFMON_SAMPLE_ENABLE : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PG_ALWAYS_ON_CU_MASK__CI__VI { - struct { - unsigned int AON_CU_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PG_ALWAYS_ON_CU_MASK__SI { - struct { - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PG_CNTL { - struct { - unsigned int GFX_POWER_GATING_ENABLE : 1; - unsigned int GFX_POWER_GATING_SRC : 1; - unsigned int DYN_PER_CU_PG_ENABLE : 1; - unsigned int STATIC_PER_CU_PG_ENABLE : 1; - unsigned int GFX_PIPELINE_PG_ENABLE__VI : 1; - unsigned int RESERVED__VI : 9; - unsigned int PG_OVERRIDE__VI : 1; - unsigned int CP_PG_DISABLE__VI : 1; - unsigned int CHUB_HANDSHAKE_ENABLE__CI__VI : 1; - unsigned int SMU_CLK_SLOWDOWN_ON_PU_ENABLE__CI__VI : 1; - unsigned int SMU_CLK_SLOWDOWN_ON_PD_ENABLE__CI__VI : 1; - unsigned int SMU_HANDSHAKE_ENABLE__VI : 1; - unsigned int RESERVED1__VI : 4; - unsigned int PG_ERROR_STATUS__CI : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PG_DELAY_2__CI__VI { - struct { - unsigned int SERDES_TIMEOUT_VALUE : 8; - unsigned int SERDES_CMD_DELAY : 8; - unsigned int PERCU_TIMEOUT_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PG_DELAY__CI__VI { - struct { - unsigned int POWER_UP_DELAY : 8; - unsigned int POWER_DOWN_DELAY : 8; - unsigned int CMD_PROPAGATE_DELAY : 8; - unsigned int MEM_SLEEP_DELAY : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SAFE_MODE__CI { - struct { - unsigned int REQ : 1; - unsigned int MESSAGE : 4; - unsigned int RESERVED : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SAFE_MODE__VI { - struct { - unsigned int CMD : 1; - unsigned int MESSAGE : 4; - unsigned int RESERVED1 : 3; - unsigned int RESPONSE : 4; - unsigned int RESERVED : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SAVE_AND_RESTORE_BASE { - struct { - unsigned int BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_CU_MASTER_BUSY__CI__VI { - struct { - unsigned int BUSY_BUSY : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_NONCU_MASTER_BUSY__CI { - struct { - unsigned int SE_MASTER_BUSY : 16; - unsigned int GC_MASTER_BUSY : 1; - unsigned int TC0_MASTER_BUSY : 1; - unsigned int TC1_MASTER_BUSY : 1; - unsigned int SPARE0_MASTER_BUSY : 1; - unsigned int SPARE1_MASTER_BUSY : 1; - unsigned int SPARE2_MASTER_BUSY : 1; - unsigned int SPARE3_MASTER_BUSY : 1; - unsigned int RESERVED : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_NONCU_MASTER_BUSY__VI { - struct { - unsigned int SE_MASTER_BUSY : 16; - unsigned int GC_MASTER_BUSY : 1; - unsigned int GC_GFX_MASTER_BUSY : 1; - unsigned int TC0_MASTER_BUSY : 1; - unsigned int TC1_MASTER_BUSY : 1; - unsigned int SPARE0_MASTER_BUSY : 1; - unsigned int SPARE1_MASTER_BUSY : 1; - unsigned int SPARE2_MASTER_BUSY : 1; - unsigned int SPARE3_MASTER_BUSY : 1; - unsigned int RESERVED : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_RD_DATA_0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_RD_DATA_1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_RD_DATA_2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_RD_MASTER_INDEX__CI { - struct { - unsigned int CU_ID : 4; - unsigned int SH_ID : 2; - unsigned int SE_ID : 3; - unsigned int SE_NONCU_ID : 1; - unsigned int SE_NONCU : 1; - unsigned int NON_SE : 3; - unsigned int DATA_REG_ID : 2; - unsigned int SPARE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_RD_MASTER_INDEX__VI { - struct { - unsigned int CU_ID : 4; - unsigned int SH_ID : 2; - unsigned int SE_ID : 3; - unsigned int SE_NONCU_ID : 1; - unsigned int SE_NONCU : 1; - unsigned int NON_SE : 4; - unsigned int DATA_REG_ID : 2; - unsigned int SPARE : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_RD_MASTER_INDEX__SI { - struct { - unsigned int : 6; - unsigned int : 6; - unsigned int : 2; - unsigned int SPARE : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_WR_CTRL__CI { - struct { - unsigned int BPM_ADDR : 8; - unsigned int POWER_DOWN : 1; - unsigned int POWER_UP : 1; - unsigned int P1_SELECT : 1; - unsigned int P2_SELECT : 1; - unsigned int WRITE_COMMAND : 1; - unsigned int READ_COMMAND : 1; - unsigned int RESERVED_1 : 2; - unsigned int CGLS_ENABLE : 1; - unsigned int CGLS_DISABLE : 1; - unsigned int CGLS_ON : 1; - unsigned int CGLS_OFF : 1; - unsigned int CGCG_OVERRIDE_0 : 1; - unsigned int CGCG_OVERRIDE_1 : 1; - unsigned int MGCG_OVERRIDE_0 : 1; - unsigned int MGCG_OVERRIDE_1 : 1; - unsigned int RESERVED_2 : 4; - unsigned int REG_ADDR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_WR_CTRL__VI { - struct { - unsigned int BPM_ADDR : 8; - unsigned int POWER_DOWN : 1; - unsigned int POWER_UP : 1; - unsigned int P1_SELECT : 1; - unsigned int P2_SELECT : 1; - unsigned int WRITE_COMMAND : 1; - unsigned int READ_COMMAND : 1; - unsigned int RDDATA_RESET : 1; - unsigned int SHORT_FORMAT : 1; - unsigned int BPM_DATA : 10; - unsigned int SRBM_OVERRIDE : 1; - unsigned int RSVD_BPM_ADDR : 1; - unsigned int REG_ADDR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_WR_CTRL__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_WR_CU_MASTER_MASK__CI__VI { - struct { - unsigned int MASTER_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_WR_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_WR_NONCU_MASTER_MASK__CI { - struct { - unsigned int SE_MASTER_MASK : 16; - unsigned int GC_MASTER_MASK : 1; - unsigned int TC0_MASTER_MASK : 1; - unsigned int TC1_MASTER_MASK : 1; - unsigned int SPARE0_MASTER_MASK : 1; - unsigned int SPARE1_MASTER_MASK : 1; - unsigned int SPARE2_MASTER_MASK : 1; - unsigned int SPARE3_MASTER_MASK : 1; - unsigned int RESERVED : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SERDES_WR_NONCU_MASTER_MASK__VI { - struct { - unsigned int SE_MASTER_MASK : 16; - unsigned int GC_MASTER_MASK : 1; - unsigned int GC_GFX_MASTER_MASK : 1; - unsigned int TC0_MASTER_MASK : 1; - unsigned int TC1_MASTER_MASK : 1; - unsigned int SPARE0_MASTER_MASK : 1; - unsigned int SPARE1_MASTER_MASK : 1; - unsigned int SPARE2_MASTER_MASK : 1; - unsigned int SPARE3_MASTER_MASK : 1; - unsigned int RESERVED : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SMU_GRBM_REG_SAVE_CTRL { - struct { - unsigned int START_GRBM_REG_SAVE : 1; - unsigned int SPARE : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SMU_PG_CTRL { - struct { - unsigned int START_PG : 1; - unsigned int SPARE : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SMU_PG_WAKE_UP_CTRL { - struct { - unsigned int START_PG_WAKE_UP : 1; - unsigned int SPARE : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SOFT_RESET_GPU { - struct { - unsigned int SOFT_RESET_GPU : 1; - unsigned int RESERVED : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_CB_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_DB_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_DEBUG_SELECT__CI__VI { - struct { - unsigned int SELECT : 8; - unsigned int : 7; - unsigned int RLC_SPM_DEBUG_MODE : 1; - unsigned int RLC_SPM_NUM_SAMPLE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_DEBUG__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_GLOBAL_MUXSEL_ADDR__CI__VI { - struct { - unsigned int PERFMON_SEL_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_GLOBAL_MUXSEL_DATA__CI__VI { - struct { - unsigned int PERFMON_SEL_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_IA_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_INT_CNTL__CI__VI { - struct { - unsigned int RLC_SPM_INT_CNTL : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_INT_STATUS__CI__VI { - struct { - unsigned int RLC_SPM_INT_STATUS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_PA_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_PERFMON_CNTL__CI__VI { - struct { - unsigned int RESERVED1 : 12; - unsigned int PERFMON_RING_MODE : 2; - unsigned int : 2; - unsigned int PERFMON_SAMPLE_INTERVAL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_PERFMON_RING_BASE_HI__CI__VI { - struct { - unsigned int RING_BASE_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_PERFMON_RING_BASE_LO__CI__VI { - struct { - unsigned int RING_BASE_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_PERFMON_RING_SIZE__CI__VI { - struct { - unsigned int RING_BASE_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_PERFMON_SEGMENT_SIZE__CI__VI { - struct { - unsigned int PERFMON_SEGMENT_SIZE : 8; - unsigned int : 3; - unsigned int GLOBAL_NUM_LINE : 5; - unsigned int SE0_NUM_LINE : 5; - unsigned int SE1_NUM_LINE : 5; - unsigned int SE2_NUM_LINE : 5; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_RING_RDPTR__CI__VI { - struct { - unsigned int PERFMON_RING_RDPTR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_SC_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_SEGMENT_THRESHOLD__CI__VI { - struct { - unsigned int NUM_SEGMENT_THRESHOLD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_SE_MUXSEL_ADDR__CI__VI { - struct { - unsigned int PERFMON_SEL_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_SE_MUXSEL_DATA__CI__VI { - struct { - unsigned int PERFMON_SEL_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_SX_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_TA_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__CI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int RESERVED : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_TD_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__CI__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_VMID__CI__VI { - struct { - unsigned int RLC_SPM_VMID : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_STATIC_PG_STATUS__CI__VI { - struct { - unsigned int PG_STATUS_CU_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_STAT__CI__VI { - struct { - unsigned int RLC_BUSY : 1; - unsigned int RLC_GPM_BUSY : 1; - unsigned int RLC_SPM_BUSY : 1; - unsigned int RLC_SRM_BUSY__VI : 1; - unsigned int RESERVED__VI : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_STAT__SI { - struct { - unsigned int RLC_BUSY : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int RESERVED : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_THREAD1_DELAY { - struct { - unsigned int CU_IDEL_DELAY : 8; - unsigned int LBPW_INNER_LOOP_DELAY : 8; - unsigned int LBPW_OUTER_LOOP_DELAY : 8; - unsigned int SPARE : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_UCODE_CNTL { - struct { - unsigned int RLC_UCODE_FLAGS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_VMID__SI { - struct { - unsigned int : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_BASE_ADDR { - struct { - unsigned int BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_CNTL { - struct { - unsigned int : 1; - unsigned int SCK_OVERWRITE : 1; - unsigned int CLOCK_GATING_EN : 1; - unsigned int : 5; - unsigned int CSB_ACTIVE_TO_SCK_SETUP_TIME : 8; - unsigned int CSB_ACTIVE_TO_SCK_HOLD_TIME : 8; - unsigned int SCK_PRESCALE_REFCLK : 4; - unsigned int SCK_PRESCALE_CRYSTAL_CLK : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_DATA { - struct { - unsigned int ROM_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_INDEX { - struct { - unsigned int ROM_INDEX : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SMC_IND_DATA__CI__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SMC_IND_INDEX__CI__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_START { - struct { - unsigned int ROM_START : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_STATUS { - struct { - unsigned int ROM_BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_CNTL { - struct { - unsigned int DATA_SIZE : 16; - unsigned int COMMAND_SIZE : 2; - unsigned int ROM_SW_RETURN_DATA_ENABLE : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_COMMAND { - struct { - unsigned int ROM_SW_INSTRUCTION : 8; - unsigned int ROM_SW_ADDRESS : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_1 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_10 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_11 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_12 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_13 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_14 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_15 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_16 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_17 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_18 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_19 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_2 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_20 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_21 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_22 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_23 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_24 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_25 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_26 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_27 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_28 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_29 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_3 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_30 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_31 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_32 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_33 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_34 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_35 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_36 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_37 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_38 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_39 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_4 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_40 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_41 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_42 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_43 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_44 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_45 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_46 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_47 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_48 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_49 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_5 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_50 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_51 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_52 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_53 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_54 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_55 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_56 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_57 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_58 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_59 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_6 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_60 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_61 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_62 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_63 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_64 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_7 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_8 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_DATA_9 { - struct { - unsigned int ROM_SW_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ROM_SW_STATUS { - struct { - unsigned int ROM_SW_DONE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLK_CGTT_BLK_CTRL_REG__SI__VI { - struct { - unsigned int SCLK_TURN_ON_DELAY : 4; - unsigned int SCLK_TURN_OFF_DELAY : 8; - unsigned int CGTT_SCLK_OVERRIDE__VI : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLK_DEEP_SLEEP_CNTL2__CI { - struct { - unsigned int RLC_BUSY_MASK : 1; - unsigned int HDP_BUSY_MASK : 1; - unsigned int ROM_BUSY_MASK : 1; - unsigned int IH_SEM_BUSY_MASK : 1; - unsigned int PDMA_BUSY_MASK : 1; - unsigned int : 1; - unsigned int IDCT_BUSY_MASK : 1; - unsigned int SDMA_BUSY_MASK : 1; - unsigned int DC_AZ_BUSY_MASK : 1; - unsigned int ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK : 1; - unsigned int UVD_CG_MC_STAT_BUSY_MASK : 1; - unsigned int VCE_CG_MC_STAT_BUSY_MASK : 1; - unsigned int SAM_CG_MC_STAT_BUSY_MASK : 1; - unsigned int SAM_CG_STATUS_BUSY_MASK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int : 1; - unsigned int SHALLOW_DIV_ID : 3; - unsigned int INOUT_CUSHION : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLK_DEEP_SLEEP_CNTL2__VI { - struct { - unsigned int RLC_BUSY_MASK : 1; - unsigned int HDP_BUSY_MASK : 1; - unsigned int ROM_BUSY_MASK : 1; - unsigned int IH_SEM_BUSY_MASK : 1; - unsigned int PDMA_BUSY_MASK : 1; - unsigned int : 1; - unsigned int IDCT_BUSY_MASK : 1; - unsigned int SDMA_BUSY_MASK : 1; - unsigned int DC_AZ_BUSY_MASK : 1; - unsigned int ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK : 1; - unsigned int UVD_CG_MC_STAT_BUSY_MASK : 1; - unsigned int VCE_CG_MC_STAT_BUSY_MASK : 1; - unsigned int SAM_CG_MC_STAT_BUSY_MASK : 1; - unsigned int SAM_CG_STATUS_BUSY_MASK : 1; - unsigned int RLC_SMU_GFXCLK_OFF_MASK : 1; - unsigned int : 5; - unsigned int : 1; - unsigned int SHALLOW_DIV_ID : 3; - unsigned int INOUT_CUSHION : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLK_DEEP_SLEEP_CNTL3__CI__VI { - struct { - unsigned int GRBM_0_SMU_BUSY_MASK : 1; - unsigned int GRBM_1_SMU_BUSY_MASK : 1; - unsigned int GRBM_2_SMU_BUSY_MASK : 1; - unsigned int GRBM_3_SMU_BUSY_MASK : 1; - unsigned int GRBM_4_SMU_BUSY_MASK : 1; - unsigned int GRBM_5_SMU_BUSY_MASK : 1; - unsigned int GRBM_6_SMU_BUSY_MASK : 1; - unsigned int GRBM_7_SMU_BUSY_MASK : 1; - unsigned int GRBM_8_SMU_BUSY_MASK : 1; - unsigned int GRBM_9_SMU_BUSY_MASK : 1; - unsigned int GRBM_10_SMU_BUSY_MASK : 1; - unsigned int GRBM_11_SMU_BUSY_MASK : 1; - unsigned int GRBM_12_SMU_BUSY_MASK : 1; - unsigned int GRBM_13_SMU_BUSY_MASK : 1; - unsigned int GRBM_14_SMU_BUSY_MASK : 1; - unsigned int GRBM_15_SMU_BUSY_MASK : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLK_DEEP_SLEEP_CNTL__CI__VI { - struct { - unsigned int DIV_ID : 3; - unsigned int RAMP_DIS : 1; - unsigned int HYSTERESIS : 12; - unsigned int SCLK_RUNNING_MASK : 1; - unsigned int SELF_REFRESH_MASK : 1; - unsigned int ALLOW_NBPSTATE_MASK : 1; - unsigned int BIF_BUSY_MASK : 1; - unsigned int UVD_BUSY_MASK : 1; - unsigned int MC0SRBM_BUSY_MASK : 1; - unsigned int MC1SRBM_BUSY_MASK : 1; - unsigned int MC_ALLOW_MASK : 1; - unsigned int SMU_BUSY_MASK : 1; - unsigned int SELF_REFRESH_NLC_MASK : 1; - unsigned int FAST_EXIT_REQ_NBPSTATE : 1; - unsigned int DEEP_SLEEP_ENTRY_MODE : 1; - unsigned int MBUS2_ACTIVE_MASK : 1; - unsigned int VCE_BUSY_MASK : 1; - unsigned int AZ_BUSY_MASK : 1; - unsigned int ENABLE_DS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLK_DEEP_SLEEP_MISC_CNTL__CI__VI { - struct { - unsigned int DPM_DS_DIV_ID : 3; - unsigned int DPM_SS_DIV_ID : 3; - unsigned int : 10; - unsigned int OCP_ENABLE : 1; - unsigned int OCP_DS_DIV_ID : 3; - unsigned int OCP_SS_DIV_ID : 3; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLK_MIN_DIV__CI__VI { - struct { - unsigned int FRACV : 12; - unsigned int INTV : 7; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLK_PWRMGT_CNTL__CI__VI { - struct { - unsigned int SCLK_PWRMGT_OFF : 1; - unsigned int SCLK_LOW_D1 : 1; - unsigned int DYN_PWR_DOWN_EN : 1; - unsigned int : 1; - unsigned int RESET_BUSY_CNT : 1; - unsigned int RESET_SCLK_CNT : 1; - unsigned int : 1; - unsigned int DYN_GFX_CLK_OFF_EN : 1; - unsigned int GFX_CLK_FORCE_ON : 1; - unsigned int GFX_CLK_REQUEST_OFF : 1; - unsigned int GFX_CLK_FORCE_OFF : 1; - unsigned int GFX_CLK_OFF_ACPI_D1 : 1; - unsigned int GFX_CLK_OFF_ACPI_D2 : 1; - unsigned int GFX_CLK_OFF_ACPI_D3 : 1; - unsigned int DYN_LIGHT_SLEEP_EN : 1; - unsigned int AUTO_SCLK_PULSE_SKIP : 1; - unsigned int LIGHT_SLEEP_COUNTER : 5; - unsigned int DYNAMIC_PM_EN : 1; - unsigned int DPM_DYN_PWR_DOWN_CNTL : 1; - unsigned int DPM_DYN_PWR_DOWN_EN : 1; - unsigned int : 1; - unsigned int VOLTAGE_UPDATE_EN : 1; - unsigned int : 2; - unsigned int FORCE_PM0_INTERRUPT : 1; - unsigned int FORCE_PM1_INTERRUPT : 1; - unsigned int GFX_VOLTAGE_CHANGE_EN : 1; - unsigned int GFX_VOLTAGE_CHANGE_MODE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLK_PWRMGT_CNTL__SI { - struct { - unsigned int SCLK_PWRMGT_OFF : 1; - unsigned int SCLK_LOW_D1 : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DYN_GFX_CLK_OFF_EN : 1; - unsigned int GFX_CLK_FORCE_ON : 1; - unsigned int GFX_CLK_REQUEST_OFF : 1; - unsigned int GFX_CLK_FORCE_OFF : 1; - unsigned int GFX_CLK_OFF_ACPI_D1 : 1; - unsigned int GFX_CLK_OFF_ACPI_D2 : 1; - unsigned int GFX_CLK_OFF_ACPI_D3 : 1; - unsigned int DYN_LIGHT_SLEEP_EN : 1; - unsigned int : 1; - unsigned int LIGHT_SLEEP_COUNTER : 5; - unsigned int : 7; - unsigned int FORCE_PM0_INTERRUPT : 1; - unsigned int FORCE_PM1_INTERRUPT : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_ALU_CONTROL__SI__VI { - struct { - unsigned int SCL_ALU_DISABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_AUTOMATIC_MODE_CONTROL__SI { - struct { - unsigned int : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_AUTOMATIC_MODE_CONTROL__VI { - struct { - unsigned int SCL_V_CALC_AUTO_RATIO_EN : 1; - unsigned int : 15; - unsigned int SCL_H_CALC_AUTO_RATIO_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_BYPASS_CONTROL__SI__VI { - struct { - unsigned int SCL_BYPASS_MODE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_COEF_RAM_CONFLICT_STATUS__SI__VI { - struct { - unsigned int SCL_HOST_CONFLICT_FLAG : 1; - unsigned int : 7; - unsigned int SCL_HOST_CONFLICT_ACK : 1; - unsigned int : 3; - unsigned int SCL_HOST_CONFLICT_MASK : 1; - unsigned int : 3; - unsigned int SCL_HOST_CONFLICT_INT_STATUS : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_COEF_RAM_SELECT__SI__VI { - struct { - unsigned int SCL_C_RAM_TAP_PAIR_IDX : 4; - unsigned int : 4; - unsigned int SCL_C_RAM_PHASE : 4; - unsigned int : 4; - unsigned int SCL_C_RAM_FILTER_TYPE : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_COEF_RAM_TAP_DATA__SI__VI { - struct { - unsigned int SCL_C_RAM_EVEN_TAP_COEF : 14; - unsigned int : 1; - unsigned int SCL_C_RAM_EVEN_TAP_COEF_EN : 1; - unsigned int SCL_C_RAM_ODD_TAP_COEF : 14; - unsigned int : 1; - unsigned int SCL_C_RAM_ODD_TAP_COEF_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_CONTROL__SI { - struct { - unsigned int : 16; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_CONTROL__VI { - struct { - unsigned int SCL_BOUNDARY_MODE : 1; - unsigned int : 3; - unsigned int SCL_EARLY_EOL_MODE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_DEBUG__SI__VI { - struct { - unsigned int SCL_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_F_SHARP_CONTROL__SI__VI { - struct { - unsigned int SCL_HF_SHARP_SCALE_FACTOR : 3; - unsigned int : 1; - unsigned int SCL_HF_SHARP_EN : 1; - unsigned int : 3; - unsigned int SCL_VF_SHARP_SCALE_FACTOR : 3; - unsigned int : 1; - unsigned int SCL_VF_SHARP_EN : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_HORZ_FILTER_CONTROL__SI { - struct { - unsigned int SCL_H_FILTER_PICK_NEAREST : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 7; - unsigned int : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_HORZ_FILTER_CONTROL__VI { - struct { - unsigned int SCL_H_FILTER_PICK_NEAREST : 1; - unsigned int : 7; - unsigned int SCL_H_2TAP_HARDCODE_COEF_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_HORZ_FILTER_SCALE_RATIO__SI__VI { - struct { - unsigned int SCL_H_SCALE_RATIO : 26; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_MANUAL_REPLICATE_CONTROL__SI__VI { - struct { - unsigned int SCL_V_MANUAL_REPLICATE_FACTOR : 4; - unsigned int : 4; - unsigned int SCL_H_MANUAL_REPLICATE_FACTOR : 4; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_MODE_CHANGE_DET1__SI__VI { - struct { - unsigned int SCL_MODE_CHANGE : 1; - unsigned int : 3; - unsigned int SCL_MODE_CHANGE_ACK : 1; - unsigned int : 2; - unsigned int SCL_ALU_H_SCALE_RATIO : 21; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_MODE_CHANGE_DET2__SI__VI { - struct { - unsigned int SCL_ALU_V_SCALE_RATIO : 21; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_MODE_CHANGE_DET3__SI__VI { - struct { - unsigned int SCL_ALU_SOURCE_HEIGHT : 14; - unsigned int : 2; - unsigned int SCL_ALU_SOURCE_WIDTH : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_MODE_CHANGE_MASK__SI__VI { - struct { - unsigned int SCL_MODE_CHANGE_MASK : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_TAP_CONTROL__SI { - struct { - unsigned int : 3; - unsigned int : 5; - unsigned int : 4; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_TAP_CONTROL__VI { - struct { - unsigned int SCL_V_NUM_OF_TAPS : 3; - unsigned int : 5; - unsigned int SCL_H_NUM_OF_TAPS : 4; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int SCL_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int SCL_TEST_DEBUG_INDEX : 8; - unsigned int SCL_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_UPDATE__SI__VI { - struct { - unsigned int SCL_UPDATE_PENDING : 1; - unsigned int : 7; - unsigned int SCL_UPDATE_TAKEN : 1; - unsigned int : 7; - unsigned int SCL_UPDATE_LOCK : 1; - unsigned int : 7; - unsigned int SCL_COEF_UPDATE_COMPLETE__VI : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_VERT_FILTER_CONTROL__SI { - struct { - unsigned int SCL_V_FILTER_PICK_NEAREST : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 7; - unsigned int : 2; - unsigned int : 6; - unsigned int : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_VERT_FILTER_CONTROL__VI { - struct { - unsigned int SCL_V_FILTER_PICK_NEAREST : 1; - unsigned int : 7; - unsigned int SCL_V_2TAP_HARDCODE_COEF_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_VERT_FILTER_INIT_BOT__SI { - struct { - unsigned int SCL_V_INIT_FRAC_BOT : 16; - unsigned int SCL_V_INIT_INT_BOT : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_VERT_FILTER_INIT_BOT__VI { - struct { - unsigned int SCL_V_INIT_FRAC_BOT : 24; - unsigned int SCL_V_INIT_INT_BOT : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_VERT_FILTER_INIT__SI { - struct { - unsigned int SCL_V_INIT_FRAC : 16; - unsigned int SCL_V_INIT_INT : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_VERT_FILTER_INIT__VI { - struct { - unsigned int SCL_V_INIT_FRAC : 24; - unsigned int SCL_V_INIT_INT : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_VERT_FILTER_SCALE_RATIO__SI__VI { - struct { - unsigned int SCL_V_SCALE_RATIO : 26; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_ADDR__CI__VI { - struct { - unsigned int OBSOLETE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_ADDR__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_REG0 { - struct { - unsigned int SCRATCH_REG0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_REG1 { - struct { - unsigned int SCRATCH_REG1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_REG2 { - struct { - unsigned int SCRATCH_REG2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_REG3 { - struct { - unsigned int SCRATCH_REG3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_REG4 { - struct { - unsigned int SCRATCH_REG4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_REG5 { - struct { - unsigned int SCRATCH_REG5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_REG6 { - struct { - unsigned int SCRATCH_REG6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_REG7 { - struct { - unsigned int SCRATCH_REG7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_UMSK__CI__VI { - struct { - unsigned int OBSOLETE_UMSK : 8; - unsigned int : 8; - unsigned int OBSOLETE_SWAP : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCRATCH_UMSK__SI { - struct { - unsigned int : 8; - unsigned int : 8; - unsigned int : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_CHICKEN_BITS__CI__VI { - struct { - unsigned int COPY_EFFICIENCY_ENABLE : 1; - unsigned int STALL_ON_TRANS_FULL_ENABLE__VI : 1; - unsigned int STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__VI : 1; - unsigned int : 13; - unsigned int COPY_OVERLAP_ENABLE : 1; - unsigned int : 3; - unsigned int SRBM_POLL_RETRYING : 1; - unsigned int : 2; - unsigned int CG_STATUS_OUTPUT : 1; - unsigned int : 2; - unsigned int CE_AFIFO_WATERMARK__VI : 2; - unsigned int CE_DFIFO_WATERMARK__VI : 2; - unsigned int CE_LFIFO_WATERMARK__VI : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_CLK_CTRL__CI__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_CNTL__CI { - struct { - unsigned int TRAP_ENABLE : 1; - unsigned int SEM_INCOMPLETE_INT_ENABLE : 1; - unsigned int SEM_WAIT_INT_ENABLE : 1; - unsigned int DATA_SWAP_ENABLE : 1; - unsigned int FENCE_SWAP_ENABLE : 1; - unsigned int : 1; - unsigned int : 5; - unsigned int MC_WRREQ_CREDIT : 6; - unsigned int : 1; - unsigned int AUTO_CTXSW_ENABLE : 1; - unsigned int : 3; - unsigned int MC_RDREQ_CREDIT : 6; - unsigned int CTXEMPTY_INT_ENABLE : 1; - unsigned int FROZEN_INT_ENABLE : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_CNTL__VI { - struct { - unsigned int TRAP_ENABLE : 1; - unsigned int ATC_L1_ENABLE : 1; - unsigned int SEM_WAIT_INT_ENABLE : 1; - unsigned int DATA_SWAP_ENABLE : 1; - unsigned int FENCE_SWAP_ENABLE : 1; - unsigned int MIDCMD_PREEMPT_ENABLE : 1; - unsigned int : 5; - unsigned int MC_WRREQ_CREDIT : 6; - unsigned int MIDCMD_WORLDSWITCH_ENABLE : 1; - unsigned int AUTO_CTXSW_ENABLE : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int MC_RDREQ_CREDIT : 6; - unsigned int CTXEMPTY_INT_ENABLE : 1; - unsigned int FROZEN_INT_ENABLE : 1; - unsigned int IB_PREEMPT_INT_ENABLE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_F32_CNTL__CI__VI { - struct { - unsigned int HALT : 1; - unsigned int STEP : 1; - unsigned int DBG_SELECT_BITS__VI : 6; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_FREEZE__CI__VI { - struct { - unsigned int : 1; - unsigned int : 3; - unsigned int FREEZE : 1; - unsigned int FROZEN : 1; - unsigned int F32_FREEZE__VI : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_APE1_CNTL__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int LIMIT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_CONTEXT_CNTL__CI__VI { - struct { - unsigned int : 16; - unsigned int RESUME_CTX : 1; - unsigned int : 7; - unsigned int SESSION_SEL : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_CONTEXT_STATUS__CI__VI { - struct { - unsigned int SELECTED : 1; - unsigned int : 1; - unsigned int IDLE : 1; - unsigned int EXPIRED : 1; - unsigned int EXCEPTION : 3; - unsigned int CTXSW_ABLE : 1; - unsigned int CTXSW_READY : 1; - unsigned int PREEMPTED__VI : 1; - unsigned int PREEMPT_DISABLE__VI : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_IB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_IB_BASE_LO__CI__VI { - struct { - unsigned int : 5; - unsigned int ADDR : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_IB_CNTL__CI__VI { - struct { - unsigned int IB_ENABLE : 1; - unsigned int : 3; - unsigned int IB_SWAP_ENABLE : 1; - unsigned int : 3; - unsigned int SWITCH_INSIDE_IB : 1; - unsigned int : 7; - unsigned int CMD_VMID : 4; - unsigned int : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_IB_OFFSET__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_IB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_IB_SIZE__CI__VI { - struct { - unsigned int SIZE : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_RB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_RB_BASE__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_RB_CNTL__CI__VI { - struct { - unsigned int RB_ENABLE : 1; - unsigned int RB_SIZE : 5; - unsigned int : 3; - unsigned int RB_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_ENABLE : 1; - unsigned int RPTR_WRITEBACK_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_TIMER : 5; - unsigned int : 2; - unsigned int RB_PRIV : 1; - unsigned int RB_VMID : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_RB_RPTR_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_RB_RPTR_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_RB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_RB_WPTR_POLL_CNTL__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int SWAP_ENABLE : 1; - unsigned int F32_POLL_ENABLE__VI : 1; - unsigned int : 1; - unsigned int FREQUENCY : 12; - unsigned int IDLE_POLL_COUNT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_RB_WPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_SKIP_CNTL__CI__VI { - struct { - unsigned int SKIP_COUNT : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_VIRTUAL_ADDR__CI__VI { - struct { - unsigned int ATC : 1; - unsigned int INVAL__VI : 1; - unsigned int : 2; - unsigned int PTR32 : 1; - unsigned int : 3; - unsigned int SHARED_BASE : 3; - unsigned int : 19; - unsigned int VM_HOLE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_HASH__CI__VI { - struct { - unsigned int CHANNEL_BITS : 3; - unsigned int : 1; - unsigned int BANK_BITS : 3; - unsigned int : 1; - unsigned int CHANNEL_XOR_COUNT : 3; - unsigned int : 1; - unsigned int BANK_XOR_COUNT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_IB_OFFSET_FETCH__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_PERFCOUNTER0_RESULT__CI__VI { - struct { - unsigned int PERF_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_PERFCOUNTER1_RESULT__CI__VI { - struct { - unsigned int PERF_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_PERFMON_CNTL__CI__VI { - struct { - unsigned int PERF_ENABLE0 : 1; - unsigned int PERF_CLEAR0 : 1; - unsigned int PERF_SEL0 : 6; - unsigned int PERF_ENABLE1 : 1; - unsigned int PERF_CLEAR1 : 1; - unsigned int PERF_SEL1 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_PHASE0_QUANTUM__CI__VI { - struct { - unsigned int UNIT : 4; - unsigned int : 4; - unsigned int VALUE : 16; - unsigned int : 6; - unsigned int PREFER : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_PHASE1_QUANTUM__CI__VI { - struct { - unsigned int UNIT : 4; - unsigned int : 4; - unsigned int VALUE : 16; - unsigned int : 6; - unsigned int PREFER : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_POWER_CNTL__CI__VI { - struct { - unsigned int : 8; - unsigned int MEM_POWER_OVERRIDE : 1; - unsigned int MEM_POWER_LS_EN__VI : 1; - unsigned int MEM_POWER_DS_EN__VI : 1; - unsigned int MEM_POWER_SD_EN__VI : 1; - unsigned int : 6; - unsigned int : 4; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_PROGRAM__CI__VI { - struct { - unsigned int STREAM : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RB_RPTR_FETCH__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_APE1_CNTL__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int LIMIT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_CONTEXT_STATUS__CI__VI { - struct { - unsigned int SELECTED : 1; - unsigned int : 1; - unsigned int IDLE : 1; - unsigned int EXPIRED : 1; - unsigned int EXCEPTION : 3; - unsigned int CTXSW_ABLE : 1; - unsigned int CTXSW_READY : 1; - unsigned int PREEMPTED__VI : 1; - unsigned int PREEMPT_DISABLE__VI : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_DOORBELL_LOG__CI__VI { - struct { - unsigned int BE_ERROR : 1; - unsigned int : 1; - unsigned int DATA : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_DOORBELL__CI__VI { - struct { - unsigned int OFFSET : 21; - unsigned int : 7; - unsigned int ENABLE : 1; - unsigned int : 1; - unsigned int CAPTURED : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_IB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_IB_BASE_LO__CI__VI { - struct { - unsigned int : 5; - unsigned int ADDR : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_IB_CNTL__CI__VI { - struct { - unsigned int IB_ENABLE : 1; - unsigned int : 3; - unsigned int IB_SWAP_ENABLE : 1; - unsigned int : 3; - unsigned int SWITCH_INSIDE_IB : 1; - unsigned int : 7; - unsigned int CMD_VMID : 4; - unsigned int : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_IB_OFFSET__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_IB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_IB_SIZE__CI__VI { - struct { - unsigned int SIZE : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_RB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_RB_BASE__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_RB_CNTL__CI__VI { - struct { - unsigned int RB_ENABLE : 1; - unsigned int RB_SIZE : 5; - unsigned int : 3; - unsigned int RB_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_ENABLE : 1; - unsigned int RPTR_WRITEBACK_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_TIMER : 5; - unsigned int : 2; - unsigned int RB_PRIV : 1; - unsigned int RB_VMID : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_RB_RPTR_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_RB_RPTR_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_RB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_RB_WPTR_POLL_CNTL__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int SWAP_ENABLE : 1; - unsigned int F32_POLL_ENABLE__VI : 1; - unsigned int : 1; - unsigned int FREQUENCY : 12; - unsigned int IDLE_POLL_COUNT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_RB_WPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_SKIP_CNTL__CI__VI { - struct { - unsigned int SKIP_COUNT : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_VIRTUAL_ADDR__CI__VI { - struct { - unsigned int ATC : 1; - unsigned int INVAL__VI : 1; - unsigned int : 2; - unsigned int PTR32 : 1; - unsigned int : 3; - unsigned int SHARED_BASE : 3; - unsigned int : 19; - unsigned int VM_HOLE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_APE1_CNTL__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int LIMIT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_CONTEXT_STATUS__CI__VI { - struct { - unsigned int SELECTED : 1; - unsigned int : 1; - unsigned int IDLE : 1; - unsigned int EXPIRED : 1; - unsigned int EXCEPTION : 3; - unsigned int CTXSW_ABLE : 1; - unsigned int CTXSW_READY : 1; - unsigned int PREEMPTED__VI : 1; - unsigned int PREEMPT_DISABLE__VI : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_DOORBELL_LOG__CI__VI { - struct { - unsigned int BE_ERROR : 1; - unsigned int : 1; - unsigned int DATA : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_DOORBELL__CI__VI { - struct { - unsigned int OFFSET : 21; - unsigned int : 7; - unsigned int ENABLE : 1; - unsigned int : 1; - unsigned int CAPTURED : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_IB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_IB_BASE_LO__CI__VI { - struct { - unsigned int : 5; - unsigned int ADDR : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_IB_CNTL__CI__VI { - struct { - unsigned int IB_ENABLE : 1; - unsigned int : 3; - unsigned int IB_SWAP_ENABLE : 1; - unsigned int : 3; - unsigned int SWITCH_INSIDE_IB : 1; - unsigned int : 7; - unsigned int CMD_VMID : 4; - unsigned int : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_IB_OFFSET__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_IB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_IB_SIZE__CI__VI { - struct { - unsigned int SIZE : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_RB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_RB_BASE__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_RB_CNTL__CI__VI { - struct { - unsigned int RB_ENABLE : 1; - unsigned int RB_SIZE : 5; - unsigned int : 3; - unsigned int RB_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_ENABLE : 1; - unsigned int RPTR_WRITEBACK_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_TIMER : 5; - unsigned int : 2; - unsigned int RB_PRIV : 1; - unsigned int RB_VMID : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_RB_RPTR_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_RB_RPTR_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_RB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_RB_WPTR_POLL_CNTL__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int SWAP_ENABLE : 1; - unsigned int F32_POLL_ENABLE__VI : 1; - unsigned int : 1; - unsigned int FREQUENCY : 12; - unsigned int IDLE_POLL_COUNT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_RB_WPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_SKIP_CNTL__CI__VI { - struct { - unsigned int SKIP_COUNT : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_VIRTUAL_ADDR__CI__VI { - struct { - unsigned int ATC : 1; - unsigned int INVAL__VI : 1; - unsigned int : 2; - unsigned int PTR32 : 1; - unsigned int : 3; - unsigned int SHARED_BASE : 3; - unsigned int : 19; - unsigned int VM_HOLE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_SEM_INCOMPLETE_TIMER_CNTL__CI { - struct { - unsigned int TIMER : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI { - struct { - unsigned int TIMER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_STATUS1_REG__CI__VI { - struct { - unsigned int CE_WREQ_IDLE : 1; - unsigned int CE_WR_IDLE : 1; - unsigned int CE_SPLIT_IDLE : 1; - unsigned int CE_RREQ_IDLE : 1; - unsigned int CE_OUT_IDLE : 1; - unsigned int CE_IN_IDLE : 1; - unsigned int CE_DST_IDLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int CE_CMD_IDLE__VI : 1; - unsigned int CE_AFIFO_FULL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int CE_INFO_FULL : 1; - unsigned int CE_INFO1_FULL : 1; - unsigned int : 2; - unsigned int CE_RD_STALL : 1; - unsigned int CE_WR_STALL : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_STATUS_REG__CI { - struct { - unsigned int IDLE : 1; - unsigned int REG_IDLE : 1; - unsigned int RB_EMPTY : 1; - unsigned int RB_FULL : 1; - unsigned int RB_CMD_IDLE : 1; - unsigned int RB_CMD_FULL : 1; - unsigned int IB_CMD_IDLE : 1; - unsigned int IB_CMD_FULL : 1; - unsigned int BLOCK_IDLE : 1; - unsigned int INSIDE_IB : 1; - unsigned int EX_IDLE : 1; - unsigned int EX_IDLE_POLL_TIMER_EXPIRE : 1; - unsigned int PACKET_READY : 1; - unsigned int MC_WR_IDLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int RB_MC_RREQ_IDLE : 1; - unsigned int IB_MC_RREQ_IDLE : 1; - unsigned int MC_RD_IDLE : 1; - unsigned int : 1; - unsigned int MC_RD_RET_STALL : 1; - unsigned int MC_RD_NO_POLL_IDLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int PREV_CMD_IDLE : 1; - unsigned int SEM_IDLE : 1; - unsigned int SEM_REQ_STALL : 1; - unsigned int SEM_RESP_STATE : 2; - unsigned int INT_IDLE : 1; - unsigned int INT_REQ_STALL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_STATUS_REG__VI { - struct { - unsigned int IDLE : 1; - unsigned int REG_IDLE : 1; - unsigned int RB_EMPTY : 1; - unsigned int RB_FULL : 1; - unsigned int RB_CMD_IDLE : 1; - unsigned int RB_CMD_FULL : 1; - unsigned int IB_CMD_IDLE : 1; - unsigned int IB_CMD_FULL : 1; - unsigned int BLOCK_IDLE : 1; - unsigned int INSIDE_IB : 1; - unsigned int EX_IDLE : 1; - unsigned int EX_IDLE_POLL_TIMER_EXPIRE : 1; - unsigned int PACKET_READY : 1; - unsigned int MC_WR_IDLE : 1; - unsigned int SRBM_IDLE : 1; - unsigned int CONTEXT_EMPTY : 1; - unsigned int DELTA_RPTR_FULL : 1; - unsigned int RB_MC_RREQ_IDLE : 1; - unsigned int IB_MC_RREQ_IDLE : 1; - unsigned int MC_RD_IDLE : 1; - unsigned int DELTA_RPTR_EMPTY : 1; - unsigned int MC_RD_RET_STALL : 1; - unsigned int MC_RD_NO_POLL_IDLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int PREV_CMD_IDLE : 1; - unsigned int SEM_IDLE : 1; - unsigned int SEM_REQ_STALL : 1; - unsigned int SEM_RESP_STATE : 2; - unsigned int INT_IDLE : 1; - unsigned int INT_REQ_STALL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_TILING_CONFIG__CI__VI { - struct { - unsigned int : 4; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_UCODE_ADDR__CI__VI { - struct { - unsigned int VALUE : 13; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_UCODE_DATA__CI__VI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_CHICKEN_BITS__CI__VI { - struct { - unsigned int COPY_EFFICIENCY_ENABLE : 1; - unsigned int STALL_ON_TRANS_FULL_ENABLE__VI : 1; - unsigned int STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__VI : 1; - unsigned int : 13; - unsigned int COPY_OVERLAP_ENABLE : 1; - unsigned int : 3; - unsigned int SRBM_POLL_RETRYING : 1; - unsigned int : 2; - unsigned int CG_STATUS_OUTPUT : 1; - unsigned int : 2; - unsigned int CE_AFIFO_WATERMARK__VI : 2; - unsigned int CE_DFIFO_WATERMARK__VI : 2; - unsigned int CE_LFIFO_WATERMARK__VI : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_CLK_CTRL__CI__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_CNTL__CI { - struct { - unsigned int TRAP_ENABLE : 1; - unsigned int SEM_INCOMPLETE_INT_ENABLE : 1; - unsigned int SEM_WAIT_INT_ENABLE : 1; - unsigned int DATA_SWAP_ENABLE : 1; - unsigned int FENCE_SWAP_ENABLE : 1; - unsigned int : 1; - unsigned int : 5; - unsigned int MC_WRREQ_CREDIT : 6; - unsigned int : 1; - unsigned int AUTO_CTXSW_ENABLE : 1; - unsigned int : 3; - unsigned int MC_RDREQ_CREDIT : 6; - unsigned int CTXEMPTY_INT_ENABLE : 1; - unsigned int FROZEN_INT_ENABLE : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_CNTL__VI { - struct { - unsigned int TRAP_ENABLE : 1; - unsigned int ATC_L1_ENABLE : 1; - unsigned int SEM_WAIT_INT_ENABLE : 1; - unsigned int DATA_SWAP_ENABLE : 1; - unsigned int FENCE_SWAP_ENABLE : 1; - unsigned int MIDCMD_PREEMPT_ENABLE : 1; - unsigned int : 5; - unsigned int MC_WRREQ_CREDIT : 6; - unsigned int MIDCMD_WORLDSWITCH_ENABLE : 1; - unsigned int AUTO_CTXSW_ENABLE : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int MC_RDREQ_CREDIT : 6; - unsigned int CTXEMPTY_INT_ENABLE : 1; - unsigned int FROZEN_INT_ENABLE : 1; - unsigned int IB_PREEMPT_INT_ENABLE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_CONFIG__CI__VI { - struct { - unsigned int : 8; - unsigned int SDMA_RDREQ_URG : 4; - unsigned int : 4; - unsigned int SDMA_REQ_TRAN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_F32_CNTL__CI__VI { - struct { - unsigned int HALT : 1; - unsigned int STEP : 1; - unsigned int DBG_SELECT_BITS__VI : 6; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_FREEZE__CI__VI { - struct { - unsigned int : 1; - unsigned int : 3; - unsigned int FREEZE : 1; - unsigned int FROZEN : 1; - unsigned int F32_FREEZE__VI : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_APE1_CNTL__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int LIMIT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_CONTEXT_CNTL__CI__VI { - struct { - unsigned int : 16; - unsigned int RESUME_CTX : 1; - unsigned int : 7; - unsigned int SESSION_SEL : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_CONTEXT_STATUS__CI__VI { - struct { - unsigned int SELECTED : 1; - unsigned int : 1; - unsigned int IDLE : 1; - unsigned int EXPIRED : 1; - unsigned int EXCEPTION : 3; - unsigned int CTXSW_ABLE : 1; - unsigned int CTXSW_READY : 1; - unsigned int PREEMPTED__VI : 1; - unsigned int PREEMPT_DISABLE__VI : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_IB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_IB_BASE_LO__CI__VI { - struct { - unsigned int : 5; - unsigned int ADDR : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_IB_CNTL__CI__VI { - struct { - unsigned int IB_ENABLE : 1; - unsigned int : 3; - unsigned int IB_SWAP_ENABLE : 1; - unsigned int : 3; - unsigned int SWITCH_INSIDE_IB : 1; - unsigned int : 7; - unsigned int CMD_VMID : 4; - unsigned int : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_IB_OFFSET__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_IB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_IB_SIZE__CI__VI { - struct { - unsigned int SIZE : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_RB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_RB_BASE__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_RB_CNTL__CI__VI { - struct { - unsigned int RB_ENABLE : 1; - unsigned int RB_SIZE : 5; - unsigned int : 3; - unsigned int RB_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_ENABLE : 1; - unsigned int RPTR_WRITEBACK_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_TIMER : 5; - unsigned int : 2; - unsigned int RB_PRIV : 1; - unsigned int RB_VMID : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_RB_RPTR_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_RB_RPTR_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_RB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_RB_WPTR_POLL_CNTL__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int SWAP_ENABLE : 1; - unsigned int F32_POLL_ENABLE__VI : 1; - unsigned int : 1; - unsigned int FREQUENCY : 12; - unsigned int IDLE_POLL_COUNT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_RB_WPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_SKIP_CNTL__CI__VI { - struct { - unsigned int SKIP_COUNT : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_VIRTUAL_ADDR__CI__VI { - struct { - unsigned int ATC : 1; - unsigned int INVAL__VI : 1; - unsigned int : 2; - unsigned int PTR32 : 1; - unsigned int : 3; - unsigned int SHARED_BASE : 3; - unsigned int : 19; - unsigned int VM_HOLE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_HASH__CI__VI { - struct { - unsigned int CHANNEL_BITS : 3; - unsigned int : 1; - unsigned int BANK_BITS : 3; - unsigned int : 1; - unsigned int CHANNEL_XOR_COUNT : 3; - unsigned int : 1; - unsigned int BANK_XOR_COUNT : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_IB_OFFSET_FETCH__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_PERFCOUNTER0_RESULT__CI__VI { - struct { - unsigned int PERF_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_PERFCOUNTER1_RESULT__CI__VI { - struct { - unsigned int PERF_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_PERFMON_CNTL__CI__VI { - struct { - unsigned int PERF_ENABLE0 : 1; - unsigned int PERF_CLEAR0 : 1; - unsigned int PERF_SEL0 : 6; - unsigned int PERF_ENABLE1 : 1; - unsigned int PERF_CLEAR1 : 1; - unsigned int PERF_SEL1 : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_PHASE0_QUANTUM__CI__VI { - struct { - unsigned int UNIT : 4; - unsigned int : 4; - unsigned int VALUE : 16; - unsigned int : 6; - unsigned int PREFER : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_PHASE1_QUANTUM__CI__VI { - struct { - unsigned int UNIT : 4; - unsigned int : 4; - unsigned int VALUE : 16; - unsigned int : 6; - unsigned int PREFER : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_POWER_CNTL__CI__VI { - struct { - unsigned int : 8; - unsigned int MEM_POWER_OVERRIDE : 1; - unsigned int MEM_POWER_LS_EN__VI : 1; - unsigned int MEM_POWER_DS_EN__VI : 1; - unsigned int MEM_POWER_SD_EN__VI : 1; - unsigned int : 6; - unsigned int : 4; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_PROGRAM__CI__VI { - struct { - unsigned int STREAM : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RB_RPTR_FETCH__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_APE1_CNTL__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int LIMIT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_CONTEXT_STATUS__CI__VI { - struct { - unsigned int SELECTED : 1; - unsigned int : 1; - unsigned int IDLE : 1; - unsigned int EXPIRED : 1; - unsigned int EXCEPTION : 3; - unsigned int CTXSW_ABLE : 1; - unsigned int CTXSW_READY : 1; - unsigned int PREEMPTED__VI : 1; - unsigned int PREEMPT_DISABLE__VI : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_DOORBELL_LOG__CI__VI { - struct { - unsigned int BE_ERROR : 1; - unsigned int : 1; - unsigned int DATA : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_DOORBELL__CI__VI { - struct { - unsigned int OFFSET : 21; - unsigned int : 7; - unsigned int ENABLE : 1; - unsigned int : 1; - unsigned int CAPTURED : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_IB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_IB_BASE_LO__CI__VI { - struct { - unsigned int : 5; - unsigned int ADDR : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_IB_CNTL__CI__VI { - struct { - unsigned int IB_ENABLE : 1; - unsigned int : 3; - unsigned int IB_SWAP_ENABLE : 1; - unsigned int : 3; - unsigned int SWITCH_INSIDE_IB : 1; - unsigned int : 7; - unsigned int CMD_VMID : 4; - unsigned int : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_IB_OFFSET__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_IB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_IB_SIZE__CI__VI { - struct { - unsigned int SIZE : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_RB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_RB_BASE__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_RB_CNTL__CI__VI { - struct { - unsigned int RB_ENABLE : 1; - unsigned int RB_SIZE : 5; - unsigned int : 3; - unsigned int RB_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_ENABLE : 1; - unsigned int RPTR_WRITEBACK_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_TIMER : 5; - unsigned int : 2; - unsigned int RB_PRIV : 1; - unsigned int RB_VMID : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_RB_RPTR_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_RB_RPTR_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_RB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_RB_WPTR_POLL_CNTL__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int SWAP_ENABLE : 1; - unsigned int F32_POLL_ENABLE__VI : 1; - unsigned int : 1; - unsigned int FREQUENCY : 12; - unsigned int IDLE_POLL_COUNT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_RB_WPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_SKIP_CNTL__CI__VI { - struct { - unsigned int SKIP_COUNT : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_VIRTUAL_ADDR__CI__VI { - struct { - unsigned int ATC : 1; - unsigned int INVAL__VI : 1; - unsigned int : 2; - unsigned int PTR32 : 1; - unsigned int : 3; - unsigned int SHARED_BASE : 3; - unsigned int : 19; - unsigned int VM_HOLE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_APE1_CNTL__CI__VI { - struct { - unsigned int BASE : 16; - unsigned int LIMIT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_CONTEXT_STATUS__CI__VI { - struct { - unsigned int SELECTED : 1; - unsigned int : 1; - unsigned int IDLE : 1; - unsigned int EXPIRED : 1; - unsigned int EXCEPTION : 3; - unsigned int CTXSW_ABLE : 1; - unsigned int CTXSW_READY : 1; - unsigned int PREEMPTED__VI : 1; - unsigned int PREEMPT_DISABLE__VI : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_DOORBELL_LOG__CI__VI { - struct { - unsigned int BE_ERROR : 1; - unsigned int : 1; - unsigned int DATA : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_DOORBELL__CI__VI { - struct { - unsigned int OFFSET : 21; - unsigned int : 7; - unsigned int ENABLE : 1; - unsigned int : 1; - unsigned int CAPTURED : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_IB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_IB_BASE_LO__CI__VI { - struct { - unsigned int : 5; - unsigned int ADDR : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_IB_CNTL__CI__VI { - struct { - unsigned int IB_ENABLE : 1; - unsigned int : 3; - unsigned int IB_SWAP_ENABLE : 1; - unsigned int : 3; - unsigned int SWITCH_INSIDE_IB : 1; - unsigned int : 7; - unsigned int CMD_VMID : 4; - unsigned int : 11; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_IB_OFFSET__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_IB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 20; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_IB_SIZE__CI__VI { - struct { - unsigned int SIZE : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_RB_BASE_HI__CI__VI { - struct { - unsigned int ADDR : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_RB_BASE__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_RB_CNTL__CI__VI { - struct { - unsigned int RB_ENABLE : 1; - unsigned int RB_SIZE : 5; - unsigned int : 3; - unsigned int RB_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_ENABLE : 1; - unsigned int RPTR_WRITEBACK_SWAP_ENABLE : 1; - unsigned int : 2; - unsigned int RPTR_WRITEBACK_TIMER : 5; - unsigned int : 2; - unsigned int RB_PRIV : 1; - unsigned int RB_VMID : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_RB_RPTR_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_RB_RPTR_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_RB_RPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_RB_WPTR_POLL_CNTL__CI__VI { - struct { - unsigned int ENABLE : 1; - unsigned int SWAP_ENABLE : 1; - unsigned int F32_POLL_ENABLE__VI : 1; - unsigned int : 1; - unsigned int FREQUENCY : 12; - unsigned int IDLE_POLL_COUNT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_RB_WPTR__CI__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_SKIP_CNTL__CI__VI { - struct { - unsigned int SKIP_COUNT : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_VIRTUAL_ADDR__CI__VI { - struct { - unsigned int ATC : 1; - unsigned int INVAL__VI : 1; - unsigned int : 2; - unsigned int PTR32 : 1; - unsigned int : 3; - unsigned int SHARED_BASE : 3; - unsigned int : 19; - unsigned int VM_HOLE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_SEM_INCOMPLETE_TIMER_CNTL__CI { - struct { - unsigned int TIMER : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI { - struct { - unsigned int TIMER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_STATUS1_REG__CI__VI { - struct { - unsigned int CE_WREQ_IDLE : 1; - unsigned int CE_WR_IDLE : 1; - unsigned int CE_SPLIT_IDLE : 1; - unsigned int CE_RREQ_IDLE : 1; - unsigned int CE_OUT_IDLE : 1; - unsigned int CE_IN_IDLE : 1; - unsigned int CE_DST_IDLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int CE_CMD_IDLE__VI : 1; - unsigned int CE_AFIFO_FULL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int CE_INFO_FULL : 1; - unsigned int CE_INFO1_FULL : 1; - unsigned int : 2; - unsigned int CE_RD_STALL : 1; - unsigned int CE_WR_STALL : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_STATUS_REG__CI { - struct { - unsigned int IDLE : 1; - unsigned int REG_IDLE : 1; - unsigned int RB_EMPTY : 1; - unsigned int RB_FULL : 1; - unsigned int RB_CMD_IDLE : 1; - unsigned int RB_CMD_FULL : 1; - unsigned int IB_CMD_IDLE : 1; - unsigned int IB_CMD_FULL : 1; - unsigned int BLOCK_IDLE : 1; - unsigned int INSIDE_IB : 1; - unsigned int EX_IDLE : 1; - unsigned int EX_IDLE_POLL_TIMER_EXPIRE : 1; - unsigned int PACKET_READY : 1; - unsigned int MC_WR_IDLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int RB_MC_RREQ_IDLE : 1; - unsigned int IB_MC_RREQ_IDLE : 1; - unsigned int MC_RD_IDLE : 1; - unsigned int : 1; - unsigned int MC_RD_RET_STALL : 1; - unsigned int MC_RD_NO_POLL_IDLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int PREV_CMD_IDLE : 1; - unsigned int SEM_IDLE : 1; - unsigned int SEM_REQ_STALL : 1; - unsigned int SEM_RESP_STATE : 2; - unsigned int INT_IDLE : 1; - unsigned int INT_REQ_STALL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_STATUS_REG__VI { - struct { - unsigned int IDLE : 1; - unsigned int REG_IDLE : 1; - unsigned int RB_EMPTY : 1; - unsigned int RB_FULL : 1; - unsigned int RB_CMD_IDLE : 1; - unsigned int RB_CMD_FULL : 1; - unsigned int IB_CMD_IDLE : 1; - unsigned int IB_CMD_FULL : 1; - unsigned int BLOCK_IDLE : 1; - unsigned int INSIDE_IB : 1; - unsigned int EX_IDLE : 1; - unsigned int EX_IDLE_POLL_TIMER_EXPIRE : 1; - unsigned int PACKET_READY : 1; - unsigned int MC_WR_IDLE : 1; - unsigned int SRBM_IDLE : 1; - unsigned int CONTEXT_EMPTY : 1; - unsigned int DELTA_RPTR_FULL : 1; - unsigned int RB_MC_RREQ_IDLE : 1; - unsigned int IB_MC_RREQ_IDLE : 1; - unsigned int MC_RD_IDLE : 1; - unsigned int DELTA_RPTR_EMPTY : 1; - unsigned int MC_RD_RET_STALL : 1; - unsigned int MC_RD_NO_POLL_IDLE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int PREV_CMD_IDLE : 1; - unsigned int SEM_IDLE : 1; - unsigned int SEM_REQ_STALL : 1; - unsigned int SEM_RESP_STATE : 2; - unsigned int INT_IDLE : 1; - unsigned int INT_REQ_STALL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_TILING_CONFIG__CI__VI { - struct { - unsigned int : 4; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_UCODE_ADDR__CI__VI { - struct { - unsigned int VALUE : 13; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_UCODE_DATA__CI__VI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA_CONFIG__CI__VI { - struct { - unsigned int : 8; - unsigned int SDMA_RDREQ_URG : 4; - unsigned int : 4; - unsigned int SDMA_REQ_TRAN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA_PGFSM_CONFIG__CI__VI { - struct { - unsigned int FSM_ADDR : 8; - unsigned int POWER_DOWN : 1; - unsigned int POWER_UP : 1; - unsigned int P1_SELECT : 1; - unsigned int P2_SELECT : 1; - unsigned int WRITE : 1; - unsigned int READ : 1; - unsigned int : 13; - unsigned int SRBM_OVERRIDE : 1; - unsigned int REG_ADDR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA_PGFSM_READ__CI__VI { - struct { - unsigned int VALUE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA_PGFSM_WRITE__CI__VI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA_POWER_GATING__CI__VI { - struct { - unsigned int PG_CNTL_ENABLE : 1; - unsigned int AUTOMATIC_STATUS_ENABLE : 1; - unsigned int PG_STATE_VALID : 1; - unsigned int : 1; - unsigned int PG_CNTL_STATUS : 2; - unsigned int SDMA0_ON_CONDITION : 1; - unsigned int SDMA1_ON_CONDITION : 1; - unsigned int POWER_OFF_DELAY : 12; - unsigned int POWER_ON_DELAY : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_CHICKEN_BITS__CI__VI { - struct { - unsigned int VMID_PIPELINE_EN : 1; - unsigned int ENTRY_PIPELINE_EN : 1; - unsigned int CHECK_COUNTER_EN__VI : 1; - unsigned int ECC_BEHAVIOR__VI : 2; - unsigned int SIGNAL_FAIL__VI : 1; - unsigned int PHY_TRAN_EN__VI : 1; - unsigned int ADDR_CMP_UNTRAN_EN__VI : 1; - unsigned int IDLE_COUNTER_INDEX__VI : 4; - unsigned int ATCL2_BUS_ID__VI : 2; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_EDC_CONFIG__CI__VI { - struct { - unsigned int : 1; - unsigned int DIS_EDC : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_MAILBOX { - struct { - unsigned int SIDEPORT : 8; - unsigned int HOSTPORT : 8; - unsigned int SIDEPORT_EXTRA__VI : 8; - unsigned int HOSTPORT_EXTRA__VI : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_MAILBOX_CLIENTCONFIG__CI__VI { - struct { - unsigned int CP_CLIENT0 : 3; - unsigned int CP_CLIENT1 : 3; - unsigned int CP_CLIENT2 : 3; - unsigned int CP_CLIENT3 : 3; - unsigned int SDMA_CLIENT0 : 3; - unsigned int UVD_CLIENT0 : 3; - unsigned int SDMA1_CLIENT0 : 3; - unsigned int VCE_CLIENT0 : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_MAILBOX_CLIENTCONFIG__SI { - struct { - unsigned int CP_CLIENT0 : 3; - unsigned int CP_CLIENT1 : 3; - unsigned int CP_CLIENT2 : 3; - unsigned int CP_CLIENT3 : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_MAILBOX_CONTROL { - struct { - unsigned int SIDEPORT_ENABLE : 8; - unsigned int HOSTPORT_ENABLE : 8; - unsigned int SIDEPORT_ENABLE_EXTRA__VI : 8; - unsigned int HOSTPORT_ENABLE_EXTRA__VI : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_MCIF_CONFIG { - struct { - unsigned int MC_REQ_SWAP : 2; - unsigned int MC_WRREQ_CREDIT__CI__VI : 6; - unsigned int MC_RDREQ_CREDIT__CI__VI : 6; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_STATUS__CI__VI { - struct { - unsigned int SEM_IDLE : 1; - unsigned int SEM_INTERNAL_IDLE : 1; - unsigned int MC_RDREQ_FIFO_FULL : 1; - unsigned int MC_WRREQ_FIFO_FULL : 1; - unsigned int WRITE1_FIFO_FULL : 1; - unsigned int CHECK0_FIFO_FULL : 1; - unsigned int MC_RDREQ_PENDING : 1; - unsigned int MC_WRREQ_PENDING : 1; - unsigned int SDMA0_MAILBOX_PENDING : 1; - unsigned int SDMA1_MAILBOX_PENDING : 1; - unsigned int UVD_MAILBOX_PENDING : 1; - unsigned int VCE_MAILBOX_PENDING : 1; - unsigned int CPG1_MAILBOX_PENDING : 1; - unsigned int CPG2_MAILBOX_PENDING : 1; - unsigned int VCE1_MAILBOX_PENDING__VI : 1; - unsigned int ATC_REQ_PENDING__VI : 1; - unsigned int : 15; - unsigned int SWITCH_READY__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEQ00__SI__VI { - struct { - unsigned int SEQ_RST0B : 1; - unsigned int SEQ_RST1B : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEQ01__SI__VI { - struct { - unsigned int SEQ_DOT8 : 1; - unsigned int : 1; - unsigned int SEQ_SHIFT2 : 1; - unsigned int SEQ_PCLKBY2 : 1; - unsigned int SEQ_SHIFT4 : 1; - unsigned int SEQ_MAXBW : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEQ02__SI__VI { - struct { - unsigned int SEQ_MAP0_EN : 1; - unsigned int SEQ_MAP1_EN : 1; - unsigned int SEQ_MAP2_EN : 1; - unsigned int SEQ_MAP3_EN : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEQ03__SI__VI { - struct { - unsigned int SEQ_FONT_B1 : 1; - unsigned int SEQ_FONT_B2 : 1; - unsigned int SEQ_FONT_A1 : 1; - unsigned int SEQ_FONT_A2 : 1; - unsigned int SEQ_FONT_B0 : 1; - unsigned int SEQ_FONT_A0 : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEQ04__SI__VI { - struct { - unsigned int : 1; - unsigned int SEQ_256K : 1; - unsigned int SEQ_ODDEVEN : 1; - unsigned int SEQ_CHAIN : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEQ8_DATA__SI__VI { - struct { - unsigned int SEQ_DATA : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEQ8_IDX__SI__VI { - struct { - unsigned int SEQ_IDX : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SETUP_DEBUG_REG0 { - struct { - unsigned int su_baryc_cntl_state : 2; - unsigned int su_cntl_state : 4; - unsigned int : 2; - unsigned int pmode_state : 6; - unsigned int ge_stallb : 1; - unsigned int geom_enable : 1; - unsigned int su_clip_baryc_free : 2; - unsigned int su_clip_rtr : 1; - unsigned int pfifo_busy : 1; - unsigned int su_cntl_busy : 1; - unsigned int geom_busy : 1; - unsigned int event_id_gated : 6; - unsigned int event_gated : 1; - unsigned int pmode_prim_gated : 1; - unsigned int su_dyn_sclk_vld : 1; - unsigned int cl_dyn_sclk_vld : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SETUP_DEBUG_REG1 { - struct { - unsigned int y_sort0_gated_23_8 : 16; - unsigned int x_sort0_gated_23_8 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SETUP_DEBUG_REG2 { - struct { - unsigned int y_sort1_gated_23_8 : 16; - unsigned int x_sort1_gated_23_8 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SETUP_DEBUG_REG3 { - struct { - unsigned int y_sort2_gated_23_8 : 16; - unsigned int x_sort2_gated_23_8 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SETUP_DEBUG_REG4 { - struct { - unsigned int attr_indx_sort0_gated : 14; - unsigned int null_prim_gated : 1; - unsigned int backfacing_gated : 1; - unsigned int st_indx_gated : 3; - unsigned int clipped_gated : 1; - unsigned int dealloc_slot_gated : 3; - unsigned int xmajor_gated : 1; - unsigned int diamond_rule_gated : 2; - unsigned int type_gated : 3; - unsigned int fpov_gated : 2; - unsigned int eop_gated : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SETUP_DEBUG_REG5 { - struct { - unsigned int attr_indx_sort2_gated : 14; - unsigned int attr_indx_sort1_gated : 14; - unsigned int provoking_vtx_gated : 2; - unsigned int valid_prim_gated : 1; - unsigned int pa_reg_sclk_vld : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SH_HIDDEN_PRIVATE_BASE_VMID__CI__VI { - struct { - unsigned int ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SH_MEM_APE1_BASE__CI__VI { - struct { - unsigned int BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SH_MEM_APE1_LIMIT__CI__VI { - struct { - unsigned int LIMIT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SH_MEM_BASES__CI__VI { - struct { - unsigned int PRIVATE_BASE : 16; - unsigned int SHARED_BASE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SH_MEM_CONFIG__CI { - struct { - unsigned int PTR32 : 1; - unsigned int PRIVATE_ATC : 1; - unsigned int ALIGNMENT_MODE : 2; - unsigned int DEFAULT_MTYPE : 3; - unsigned int APE1_MTYPE : 3; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SH_MEM_CONFIG__VI { - struct { - unsigned int ADDRESS_MODE : 2; - unsigned int PRIVATE_ATC : 1; - unsigned int ALIGNMENT_MODE : 2; - unsigned int DEFAULT_MTYPE : 3; - unsigned int APE1_MTYPE : 3; - unsigned int APE1_ATC : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SH_STATIC_MEM_CONFIG__CI__VI { - struct { - unsigned int SWIZZLE_ENABLE : 1; - unsigned int ELEMENT_SIZE : 2; - unsigned int INDEX_STRIDE : 2; - unsigned int PRIVATE_MTYPE : 3; - unsigned int READ_ONLY_CNTL : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SLAVE_COMM_CMD_REG__SI__VI { - struct { - unsigned int SLAVE_COMM_CMD_REG_BYTE0 : 8; - unsigned int SLAVE_COMM_CMD_REG_BYTE1 : 8; - unsigned int SLAVE_COMM_CMD_REG_BYTE2 : 8; - unsigned int SLAVE_COMM_CMD_REG_BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SLAVE_COMM_CNTL_REG__SI__VI { - struct { - unsigned int SLAVE_COMM_INTERRUPT : 1; - unsigned int : 7; - unsigned int COMM_PORT_MSG_TO_HOST_IN_PROGRESS : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SLAVE_COMM_DATA_REG1__SI__VI { - struct { - unsigned int SLAVE_COMM_DATA_REG1_BYTE0 : 8; - unsigned int SLAVE_COMM_DATA_REG1_BYTE1 : 8; - unsigned int SLAVE_COMM_DATA_REG1_BYTE2 : 8; - unsigned int SLAVE_COMM_DATA_REG1_BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SLAVE_COMM_DATA_REG2__SI__VI { - struct { - unsigned int SLAVE_COMM_DATA_REG2_BYTE0 : 8; - unsigned int SLAVE_COMM_DATA_REG2_BYTE1 : 8; - unsigned int SLAVE_COMM_DATA_REG2_BYTE2 : 8; - unsigned int SLAVE_COMM_DATA_REG2_BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SLAVE_COMM_DATA_REG3__SI__VI { - struct { - unsigned int SLAVE_COMM_DATA_REG3_BYTE0 : 8; - unsigned int SLAVE_COMM_DATA_REG3_BYTE1 : 8; - unsigned int SLAVE_COMM_DATA_REG3_BYTE2 : 8; - unsigned int SLAVE_COMM_DATA_REG3_BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SLAVE_HANG_ERROR { - struct { - unsigned int SRBM_HANG_ERROR : 1; - unsigned int HDP_HANG_ERROR : 1; - unsigned int VGA_HANG_ERROR : 1; - unsigned int ROM_HANG_ERROR : 1; - unsigned int AUDIO_HANG_ERROR : 1; - unsigned int CEC_HANG_ERROR__CI__VI : 1; - unsigned int : 1; - unsigned int XDMA_HANG_ERROR__CI__VI : 1; - unsigned int DOORBELL_HANG_ERROR__CI__VI : 1; - unsigned int GARLIC_HANG_ERROR__CI__VI : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SLAVE_HANG_PROTECTION_CNTL { - struct { - unsigned int : 1; - unsigned int HANG_PROTECTION_TIMER_SEL : 3; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SLAVE_REQ_CREDIT_CNTL { - struct { - unsigned int BIF_SRBM_REQ_CREDIT : 5; - unsigned int BIF_VGA_REQ_CREDIT : 4; - unsigned int : 1; - unsigned int BIF_HDP_REQ_CREDIT : 5; - unsigned int BIF_ROM_REQ_CREDIT : 1; - unsigned int : 4; - unsigned int BIF_AZ_REQ_CREDIT : 1; - unsigned int : 4; - unsigned int BIF_XDMA_REQ_CREDIT__VI : 6; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMBCLK_PAD_CNTL__CI { - struct { - unsigned int SMBCLK_PAD_A : 1; - unsigned int SMBCLK_PAD_SEL : 1; - unsigned int SMBCLK_PAD_MODE : 1; - unsigned int SMBCLK_PAD_SPARE : 2; - unsigned int SMBCLK_PAD_SN0 : 1; - unsigned int SMBCLK_PAD_SN1 : 1; - unsigned int SMBCLK_PAD_SN2 : 1; - unsigned int SMBCLK_PAD_SN3 : 1; - unsigned int SMBCLK_PAD_SLEWN : 1; - unsigned int SMBCLK_PAD_WAKE : 1; - unsigned int SMBCLK_PAD_SCHMEN : 1; - unsigned int SMBCLK_PAD_CNTL_EN : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMBCLK_PAD_CNTL__VI { - struct { - unsigned int SMBCLK_PAD_A : 1; - unsigned int SMBCLK_PAD_SEL : 1; - unsigned int SMBCLK_PAD_MODE : 1; - unsigned int SMBCLK_PAD_SPARE : 2; - unsigned int SMBCLK_PAD_SN0 : 1; - unsigned int SMBCLK_PAD_SN1 : 1; - unsigned int SMBCLK_PAD_SN2 : 1; - unsigned int SMBCLK_PAD_SN3 : 1; - unsigned int SMBCLK_PAD_SLEW : 1; - unsigned int SMBCLK_PAD_WAKE : 1; - unsigned int SMBCLK_PAD_SCHMEN : 1; - unsigned int SMBCLK_PAD_CNTL_EN : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMBDAT_PAD_CNTL__CI { - struct { - unsigned int SMBDAT_PAD_A : 1; - unsigned int SMBDAT_PAD_SEL : 1; - unsigned int SMBDAT_PAD_MODE : 1; - unsigned int SMBDAT_PAD_SPARE : 2; - unsigned int SMBDAT_PAD_SN0 : 1; - unsigned int SMBDAT_PAD_SN1 : 1; - unsigned int SMBDAT_PAD_SN2 : 1; - unsigned int SMBDAT_PAD_SN3 : 1; - unsigned int SMBDAT_PAD_SLEWN : 1; - unsigned int SMBDAT_PAD_WAKE : 1; - unsigned int SMBDAT_PAD_SCHMEN : 1; - unsigned int SMBDAT_PAD_CNTL_EN : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMBDAT_PAD_CNTL__VI { - struct { - unsigned int SMBDAT_PAD_A : 1; - unsigned int SMBDAT_PAD_SEL : 1; - unsigned int SMBDAT_PAD_MODE : 1; - unsigned int SMBDAT_PAD_SPARE : 2; - unsigned int SMBDAT_PAD_SN0 : 1; - unsigned int SMBDAT_PAD_SN1 : 1; - unsigned int SMBDAT_PAD_SN2 : 1; - unsigned int SMBDAT_PAD_SN3 : 1; - unsigned int SMBDAT_PAD_SLEW : 1; - unsigned int SMBDAT_PAD_WAKE : 1; - unsigned int SMBDAT_PAD_SCHMEN : 1; - unsigned int SMBDAT_PAD_CNTL_EN : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMBUS_SLV_CNTL__CI { - struct { - unsigned int SMB_SOFT_RESET : 1; - unsigned int SMB_SLV_ADR : 7; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_ACCESS_CNTL__SI__CI { - struct { - unsigned int AUTO_INCREMENT_IND_0 : 1; - unsigned int AUTO_INCREMENT_IND_1__CI : 1; - unsigned int AUTO_INCREMENT_IND_2__CI : 1; - unsigned int AUTO_INCREMENT_IND_3__CI : 1; - unsigned int AUTO_INCREMENT_IND_4__CI : 1; - unsigned int AUTO_INCREMENT_IND_5__CI : 1; - unsigned int AUTO_INCREMENT_IND_6__CI : 1; - unsigned int AUTO_INCREMENT_IND_7__CI : 1; - unsigned int AUTO_INCREMENT_IND_1__SI : 1; - unsigned int : 7; - unsigned int AUTO_INCREMENT_IND_2__SI : 1; - unsigned int : 7; - unsigned int AUTO_INCREMENT_IND_3__SI : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_ACCESS_CNTL__VI { - struct { - unsigned int AUTO_INCREMENT_IND_0 : 1; - unsigned int AUTO_INCREMENT_IND_1 : 1; - unsigned int AUTO_INCREMENT_IND_2 : 1; - unsigned int AUTO_INCREMENT_IND_3 : 1; - unsigned int AUTO_INCREMENT_IND_4 : 1; - unsigned int AUTO_INCREMENT_IND_5 : 1; - unsigned int AUTO_INCREMENT_IND_6 : 1; - unsigned int AUTO_INCREMENT_IND_7 : 1; - unsigned int AUTO_INCREMENT_IND_8 : 1; - unsigned int AUTO_INCREMENT_IND_9 : 1; - unsigned int AUTO_INCREMENT_IND_10 : 1; - unsigned int AUTO_INCREMENT_IND_11 : 1; - unsigned int AUTO_INCREMENT_IND_12 : 1; - unsigned int AUTO_INCREMENT_IND_13 : 1; - unsigned int AUTO_INCREMENT_IND_14 : 1; - unsigned int AUTO_INCREMENT_IND_15 : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_DATA { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_DATA_0__CI__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_DATA_1__CI__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_DATA_2__CI__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_DATA_3__CI__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_DATA_4__CI__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_DATA_5__CI__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_DATA_6__CI__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_DATA_7__CI__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_INDEX { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_INDEX_0__CI__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_INDEX_1__CI__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_INDEX_2__CI__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_INDEX_3__CI__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_INDEX_4__CI__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_INDEX_5__CI__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_INDEX_6__CI__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_IND_INDEX_7__CI__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_0__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_0__SI { - struct { - unsigned int SMC_MSG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_10__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_11__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_1__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_1__SI { - struct { - unsigned int SMC_MSG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_2__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_3__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_4__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_5__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_6__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_7__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_8__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MESSAGE_9__CI__VI { - struct { - unsigned int SMC_MSG : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_0__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_10__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_11__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_1__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_2__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_3__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_4__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_5__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_6__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_7__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_8__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_MSG_ARG_9__CI__VI { - struct { - unsigned int SMC_MSG_ARG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_PC_C__CI__VI { - struct { - unsigned int smc_pc_c : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_PC__SI { - struct { - unsigned int : 30; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_0__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_0__SI { - struct { - unsigned int SMC_RESP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_10__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_11__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_1__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_1__SI { - struct { - unsigned int SMC_RESP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_2__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_3__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_4__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_5__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_6__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_7__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_8__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_RESP_9__CI__VI { - struct { - unsigned int SMC_RESP : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_SCRATCH9 { - struct { - unsigned int SCRATCH_VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_SYSCON_MISC_CNTL__CI__VI { - struct { - unsigned int : 1; - unsigned int dma_no_outstanding__VI : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMC_SYSCON_MSG_ARG_0__CI__VI { - struct { - unsigned int smc_msg_arg : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_EFUSE_0__CI__VI { - struct { - unsigned int EFUSE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_MAIN_PLL_OP_FREQ__CI__VI { - struct { - unsigned int PLL_OP_FREQ : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_SMC_IND_DATA__CI__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_SMC_IND_INDEX__CI__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SNAPSHOT_V_COUNTER__SI { - struct { - unsigned int : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_ARB_CYCLES_0 { - struct { - unsigned int TS0_DURATION : 16; - unsigned int TS1_DURATION : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_ARB_CYCLES_1 { - struct { - unsigned int TS2_DURATION : 16; - unsigned int TS3_DURATION__CI__VI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_ARB_PRIORITY__CI__VI { - struct { - unsigned int PIPE_ORDER_TS0 : 3; - unsigned int PIPE_ORDER_TS1 : 3; - unsigned int PIPE_ORDER_TS2 : 3; - unsigned int PIPE_ORDER_TS3 : 3; - unsigned int TS0_DUR_MULT : 2; - unsigned int TS1_DUR_MULT : 2; - unsigned int TS2_DUR_MULT : 2; - unsigned int TS3_DUR_MULT : 2; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_ARB_PRIORITY__SI { - struct { - unsigned int : 3; - unsigned int : 3; - unsigned int : 3; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_BARYC_CNTL { - struct { - unsigned int PERSP_CENTER_CNTL : 1; - unsigned int : 3; - unsigned int PERSP_CENTROID_CNTL : 1; - unsigned int : 3; - unsigned int LINEAR_CENTER_CNTL : 1; - unsigned int : 3; - unsigned int LINEAR_CENTROID_CNTL : 1; - unsigned int : 3; - unsigned int POS_FLOAT_LOCATION : 2; - unsigned int : 2; - unsigned int POS_FLOAT_ULC : 1; - unsigned int : 3; - unsigned int FRONT_FACE_ALL_BITS : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CDBG_SYS_CS0__CI__VI { - struct { - unsigned int PIPE0 : 8; - unsigned int PIPE1 : 8; - unsigned int PIPE2 : 8; - unsigned int PIPE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CDBG_SYS_CS1__CI__VI { - struct { - unsigned int PIPE0 : 8; - unsigned int PIPE1 : 8; - unsigned int PIPE2 : 8; - unsigned int PIPE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CDBG_SYS_GFX__CI__VI { - struct { - unsigned int PS_EN : 1; - unsigned int VS_EN : 1; - unsigned int GS_EN : 1; - unsigned int ES_EN : 1; - unsigned int HS_EN : 1; - unsigned int LS_EN : 1; - unsigned int CS_EN : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CDBG_SYS_HP3D__CI__VI { - struct { - unsigned int PS_EN : 1; - unsigned int VS_EN : 1; - unsigned int GS_EN : 1; - unsigned int ES_EN : 1; - unsigned int HS_EN : 1; - unsigned int LS_EN : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_COMPUTE_QUEUE_RESET__CI__VI { - struct { - unsigned int RESET : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CONFIG_CNTL { - struct { - unsigned int GPR_WRITE_PRIORITY : 21; - unsigned int EXP_PRIORITY_ORDER : 3; - unsigned int ENABLE_SQG_TOP_EVENTS : 1; - unsigned int ENABLE_SQG_BOP_EVENTS : 1; - unsigned int RSRC_MGMT_RESET : 1; - unsigned int TTRACE_STALL_ALL__CI__VI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CONFIG_CNTL_1 { - struct { - unsigned int VTX_DONE_DELAY : 4; - unsigned int INTERP_ONE_PRIM_PER_ROW : 1; - unsigned int : 1; - unsigned int PC_LIMIT_ENABLE : 1; - unsigned int PC_LIMIT_STRICT : 1; - unsigned int CRC_SIMD_ID_WADDR_DISABLE : 1; - unsigned int LBPW_CU_CHK_MODE__CI__VI : 1; - unsigned int LBPW_CU_CHK_CNT__CI__VI : 4; - unsigned int : 2; - unsigned int PC_LIMIT_SIZE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CSQ_WF_ACTIVE_COUNT_0__CI__VI { - struct { - unsigned int COUNT : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CSQ_WF_ACTIVE_COUNT_1__CI__VI { - struct { - unsigned int COUNT : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CSQ_WF_ACTIVE_COUNT_2__CI__VI { - struct { - unsigned int COUNT : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CSQ_WF_ACTIVE_COUNT_3__CI__VI { - struct { - unsigned int COUNT : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CSQ_WF_ACTIVE_COUNT_4__CI__VI { - struct { - unsigned int COUNT : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CSQ_WF_ACTIVE_COUNT_5__CI__VI { - struct { - unsigned int COUNT : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CSQ_WF_ACTIVE_COUNT_6__CI__VI { - struct { - unsigned int COUNT : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CSQ_WF_ACTIVE_COUNT_7__CI__VI { - struct { - unsigned int COUNT : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CSQ_WF_ACTIVE_STATUS__CI__VI { - struct { - unsigned int ACTIVE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_DEBUG_BUSY__CI__VI { - struct { - unsigned int LS_BUSY : 1; - unsigned int HS_BUSY : 1; - unsigned int ES_BUSY : 1; - unsigned int GS_BUSY : 1; - unsigned int VS_BUSY : 1; - unsigned int PS0_BUSY : 1; - unsigned int PS1_BUSY : 1; - unsigned int CSG_BUSY : 1; - unsigned int CS0_BUSY : 1; - unsigned int CS1_BUSY : 1; - unsigned int CS2_BUSY : 1; - unsigned int CS3_BUSY : 1; - unsigned int CS4_BUSY : 1; - unsigned int CS5_BUSY : 1; - unsigned int CS6_BUSY : 1; - unsigned int CS7_BUSY : 1; - unsigned int LDS_WR_CTL0_BUSY : 1; - unsigned int LDS_WR_CTL1_BUSY : 1; - unsigned int RSRC_ALLOC0_BUSY : 1; - unsigned int RSRC_ALLOC1_BUSY : 1; - unsigned int PC_DEALLOC_BUSY : 1; - unsigned int EVENT_CLCTR_BUSY : 1; - unsigned int GRBM_BUSY : 1; - unsigned int SPIS_BUSY : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_DEBUG_BUSY__SI { - struct { - unsigned int LS_BUSY : 1; - unsigned int HS_BUSY : 1; - unsigned int ES_BUSY : 1; - unsigned int GS_BUSY : 1; - unsigned int VS_BUSY : 1; - unsigned int PS0_BUSY : 1; - unsigned int PS1_BUSY : 1; - unsigned int CS0_BUSY : 1; - unsigned int CS1_BUSY : 1; - unsigned int CS2_BUSY : 1; - unsigned int LDS_WR_CTL0_BUSY : 1; - unsigned int LDS_WR_CTL1_BUSY : 1; - unsigned int RSRC_ALLOC0_BUSY : 1; - unsigned int RSRC_ALLOC1_BUSY : 1; - unsigned int : 1; - unsigned int EVENT_CLCTR_BUSY : 1; - unsigned int GRBM_BUSY : 1; - unsigned int SPIS_BUSY : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_DEBUG_CNTL__CI__VI { - struct { - unsigned int DEBUG_GRBM_OVERRIDE : 1; - unsigned int DEBUG_THREAD_TYPE_SEL : 3; - unsigned int DEBUG_GROUP_SEL : 6; - unsigned int DEBUG_SIMD_SEL : 6; - unsigned int DEBUG_SH_SEL : 1; - unsigned int SPI_ECO_SPARE_0 : 1; - unsigned int SPI_ECO_SPARE_1 : 1; - unsigned int SPI_ECO_SPARE_2 : 1; - unsigned int SPI_ECO_SPARE_3 : 1; - unsigned int SPI_ECO_SPARE_4 : 1; - unsigned int SPI_ECO_SPARE_5 : 1; - unsigned int SPI_ECO_SPARE_6 : 1; - unsigned int SPI_ECO_SPARE_7 : 1; - unsigned int DEBUG_PIPE_SEL : 3; - unsigned int : 3; - unsigned int DEBUG_REG_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_DEBUG_CNTL__SI { - struct { - unsigned int DEBUG_GRBM_OVERRIDE : 1; - unsigned int DEBUG_THREAD_TYPE_SEL : 4; - unsigned int DEBUG_GROUP_SEL : 5; - unsigned int DEBUG_SIMD_SEL : 6; - unsigned int DEBUG_SH_SEL : 1; - unsigned int SPI_ECO_SPARE_0 : 1; - unsigned int SPI_ECO_SPARE_1 : 1; - unsigned int SPI_ECO_SPARE_2 : 1; - unsigned int SPI_ECO_SPARE_3 : 1; - unsigned int SPI_ECO_SPARE_4 : 1; - unsigned int SPI_ECO_SPARE_5 : 1; - unsigned int SPI_ECO_SPARE_6 : 1; - unsigned int SPI_ECO_SPARE_7 : 1; - unsigned int : 6; - unsigned int DEBUG_REG_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_DEBUG_READ { - struct { - unsigned int DATA : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_GDBG_TBA_HI__CI__VI { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_GDBG_TBA_LO__CI__VI { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_GDBG_TMA_HI__CI__VI { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_GDBG_TMA_LO__CI__VI { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_GDBG_TRAP_CONFIG__CI__VI { - struct { - unsigned int ME_SEL : 2; - unsigned int PIPE_SEL : 2; - unsigned int QUEUE_SEL : 3; - unsigned int ME_MATCH : 1; - unsigned int PIPE_MATCH : 1; - unsigned int QUEUE_MATCH : 1; - unsigned int : 5; - unsigned int TRAP_EN : 1; - unsigned int VMID_SEL : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_GDBG_TRAP_DATA0__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_GDBG_TRAP_DATA1__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_GDBG_TRAP_MASK__CI__VI { - struct { - unsigned int EXCP_EN : 9; - unsigned int REPLACE : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_GDBG_WAVE_CNTL__CI__VI { - struct { - unsigned int STALL_RA : 1; - unsigned int STALL_VMID__VI : 16; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_GDS_CREDITS { - struct { - unsigned int DS_DATA_CREDITS : 8; - unsigned int DS_CMD_CREDITS : 8; - unsigned int UNUSED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_INTERP_CONTROL_0 { - struct { - unsigned int FLAT_SHADE_ENA : 1; - unsigned int PNT_SPRITE_ENA : 1; - unsigned int PNT_SPRITE_OVRD_X : 3; - unsigned int PNT_SPRITE_OVRD_Y : 3; - unsigned int PNT_SPRITE_OVRD_Z : 3; - unsigned int PNT_SPRITE_OVRD_W : 3; - unsigned int PNT_SPRITE_TOP_1 : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_LB_CTR_CTRL { - struct { - unsigned int LOAD : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_LB_CU_MASK { - struct { - unsigned int CU_MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_LB_DATA_REG { - struct { - unsigned int CNT_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_P0_TRAP_SCREEN_GPR_MIN__CI__VI { - struct { - unsigned int VGPR_MIN : 6; - unsigned int SGPR_MIN : 4; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_P0_TRAP_SCREEN_PSBA_HI__CI__VI { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_P0_TRAP_SCREEN_PSBA_LO__CI__VI { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_P0_TRAP_SCREEN_PSMA_HI__CI__VI { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_P0_TRAP_SCREEN_PSMA_LO__CI__VI { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_P1_TRAP_SCREEN_GPR_MIN__CI__VI { - struct { - unsigned int VGPR_MIN : 6; - unsigned int SGPR_MIN : 4; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_P1_TRAP_SCREEN_PSBA_HI__CI__VI { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_P1_TRAP_SCREEN_PSBA_LO__CI__VI { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_P1_TRAP_SCREEN_PSMA_HI__CI__VI { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_P1_TRAP_SCREEN_PSMA_LO__CI__VI { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER0_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER1_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER1_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER2_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER2_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER3_SELECT { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER3_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER4_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER4_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER4_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER5_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER5_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER5_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PERFCOUNTER_BINS { - struct { - unsigned int BIN0_MIN : 4; - unsigned int BIN0_MAX : 4; - unsigned int BIN1_MIN : 4; - unsigned int BIN1_MAX : 4; - unsigned int BIN2_MIN : 4; - unsigned int BIN2_MAX : 4; - unsigned int BIN3_MIN : 4; - unsigned int BIN3_MAX : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PG_ENABLE_STATIC_CU_MASK { - struct { - unsigned int CU_MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_ADDR { - struct { - unsigned int PERSP_SAMPLE_ENA : 1; - unsigned int PERSP_CENTER_ENA : 1; - unsigned int PERSP_CENTROID_ENA : 1; - unsigned int PERSP_PULL_MODEL_ENA : 1; - unsigned int LINEAR_SAMPLE_ENA : 1; - unsigned int LINEAR_CENTER_ENA : 1; - unsigned int LINEAR_CENTROID_ENA : 1; - unsigned int LINE_STIPPLE_TEX_ENA : 1; - unsigned int POS_X_FLOAT_ENA : 1; - unsigned int POS_Y_FLOAT_ENA : 1; - unsigned int POS_Z_FLOAT_ENA : 1; - unsigned int POS_W_FLOAT_ENA : 1; - unsigned int FRONT_FACE_ENA : 1; - unsigned int ANCILLARY_ENA : 1; - unsigned int SAMPLE_COVERAGE_ENA : 1; - unsigned int POS_FIXED_PT_ENA : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_0 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_1 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_10 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_11 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_12 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_13 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_14 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_15 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_16 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_17 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_18 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_19 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_2 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_20 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_21 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_22 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_23 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_24 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_25 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_26 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_27 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_28 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_29 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_3 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_30 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_31 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 7; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_4 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_5 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_6 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_7 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_8 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_CNTL_9 { - struct { - unsigned int OFFSET : 6; - unsigned int : 2; - unsigned int DEFAULT_VAL : 2; - unsigned int FLAT_SHADE : 1; - unsigned int : 2; - unsigned int CYL_WRAP : 4; - unsigned int PT_SPRITE_TEX : 1; - unsigned int DUP__CI__VI : 1; - unsigned int FP16_INTERP_MODE__VI : 1; - unsigned int USE_DEFAULT_ATTR1__VI : 1; - unsigned int DEFAULT_VAL_ATTR1__VI : 2; - unsigned int PT_SPRITE_TEX_ATTR1__VI : 1; - unsigned int ATTR0_VALID__VI : 1; - unsigned int ATTR1_VALID__VI : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_INPUT_ENA { - struct { - unsigned int PERSP_SAMPLE_ENA : 1; - unsigned int PERSP_CENTER_ENA : 1; - unsigned int PERSP_CENTROID_ENA : 1; - unsigned int PERSP_PULL_MODEL_ENA : 1; - unsigned int LINEAR_SAMPLE_ENA : 1; - unsigned int LINEAR_CENTER_ENA : 1; - unsigned int LINEAR_CENTROID_ENA : 1; - unsigned int LINE_STIPPLE_TEX_ENA : 1; - unsigned int POS_X_FLOAT_ENA : 1; - unsigned int POS_Y_FLOAT_ENA : 1; - unsigned int POS_Z_FLOAT_ENA : 1; - unsigned int POS_W_FLOAT_ENA : 1; - unsigned int FRONT_FACE_ENA : 1; - unsigned int ANCILLARY_ENA : 1; - unsigned int SAMPLE_COVERAGE_ENA : 1; - unsigned int POS_FIXED_PT_ENA : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_IN_CONTROL { - struct { - unsigned int NUM_INTERP : 6; - unsigned int PARAM_GEN : 1; - unsigned int : 7; - unsigned int BC_OPTIMIZE_DISABLE : 1; - unsigned int : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_PS_MAX_WAVE_ID { - struct { - unsigned int MAX_WAVE_ID : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESET_DEBUG__CI__VI { - struct { - unsigned int DISABLE_GFX_RESET : 1; - unsigned int DISABLE_GFX_RESET_PER_VMID : 1; - unsigned int DISABLE_GFX_RESET_ALL_VMID : 1; - unsigned int DISABLE_GFX_RESET_RESOURCE : 1; - unsigned int DISABLE_GFX_RESET_PRIORITY : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_0__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_10__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_11__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_1__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_2__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_3__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_4__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_5__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_6__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_7__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_8__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_9__CI__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_0__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_10__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_11__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_1__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_2__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_3__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_4__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_5__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_6__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_7__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_8__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_9__CI__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_COL_FORMAT { - struct { - unsigned int COL0_EXPORT_FORMAT : 4; - unsigned int COL1_EXPORT_FORMAT : 4; - unsigned int COL2_EXPORT_FORMAT : 4; - unsigned int COL3_EXPORT_FORMAT : 4; - unsigned int COL4_EXPORT_FORMAT : 4; - unsigned int COL5_EXPORT_FORMAT : 4; - unsigned int COL6_EXPORT_FORMAT : 4; - unsigned int COL7_EXPORT_FORMAT : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_LATE_ALLOC_VS__CI__VI { - struct { - unsigned int LIMIT : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_HI_ES { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_HI_GS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_HI_HS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_HI_LS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_HI_PS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_HI_VS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_LO_ES { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_LO_GS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_LO_HS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_LO_LS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_LO_PS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_LO_VS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC1_ES { - struct { - unsigned int VGPRS : 6; - unsigned int SGPRS : 4; - unsigned int PRIORITY : 2; - unsigned int FLOAT_MODE : 8; - unsigned int PRIV : 1; - unsigned int DX10_CLAMP : 1; - unsigned int DEBUG_MODE : 1; - unsigned int IEEE_MODE : 1; - unsigned int VGPR_COMP_CNT : 2; - unsigned int CU_GROUP_ENABLE : 1; - unsigned int CACHE_CTL__CI__VI : 3; - unsigned int CDBG_USER__CI__VI : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC1_GS { - struct { - unsigned int VGPRS : 6; - unsigned int SGPRS : 4; - unsigned int PRIORITY : 2; - unsigned int FLOAT_MODE : 8; - unsigned int PRIV : 1; - unsigned int DX10_CLAMP : 1; - unsigned int DEBUG_MODE : 1; - unsigned int IEEE_MODE : 1; - unsigned int CU_GROUP_ENABLE : 1; - unsigned int CACHE_CTL__CI__VI : 3; - unsigned int CDBG_USER__CI__VI : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC1_HS { - struct { - unsigned int VGPRS : 6; - unsigned int SGPRS : 4; - unsigned int PRIORITY : 2; - unsigned int FLOAT_MODE : 8; - unsigned int PRIV : 1; - unsigned int DX10_CLAMP : 1; - unsigned int DEBUG_MODE : 1; - unsigned int IEEE_MODE : 1; - unsigned int CACHE_CTL__CI__VI : 3; - unsigned int CDBG_USER__CI__VI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC1_LS { - struct { - unsigned int VGPRS : 6; - unsigned int SGPRS : 4; - unsigned int PRIORITY : 2; - unsigned int FLOAT_MODE : 8; - unsigned int PRIV : 1; - unsigned int DX10_CLAMP : 1; - unsigned int DEBUG_MODE : 1; - unsigned int IEEE_MODE : 1; - unsigned int VGPR_COMP_CNT : 2; - unsigned int CACHE_CTL__CI__VI : 3; - unsigned int CDBG_USER__CI__VI : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC1_PS { - struct { - unsigned int VGPRS : 6; - unsigned int SGPRS : 4; - unsigned int PRIORITY : 2; - unsigned int FLOAT_MODE : 8; - unsigned int PRIV : 1; - unsigned int DX10_CLAMP : 1; - unsigned int DEBUG_MODE : 1; - unsigned int IEEE_MODE : 1; - unsigned int CU_GROUP_DISABLE : 1; - unsigned int CACHE_CTL__CI__VI : 3; - unsigned int CDBG_USER__CI__VI : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC1_VS { - struct { - unsigned int VGPRS : 6; - unsigned int SGPRS : 4; - unsigned int PRIORITY : 2; - unsigned int FLOAT_MODE : 8; - unsigned int PRIV : 1; - unsigned int DX10_CLAMP : 1; - unsigned int DEBUG_MODE : 1; - unsigned int IEEE_MODE : 1; - unsigned int VGPR_COMP_CNT : 2; - unsigned int CU_GROUP_ENABLE : 1; - unsigned int CACHE_CTL__CI__VI : 3; - unsigned int CDBG_USER__CI__VI : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC2_ES { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int OC_LDS_EN : 1; - unsigned int EXCP_EN : 9; - unsigned int : 3; - unsigned int LDS_SIZE__CI__VI : 9; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC2_ES_GS__CI__VI { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int OC_LDS_EN : 1; - unsigned int EXCP_EN : 9; - unsigned int : 3; - unsigned int LDS_SIZE : 9; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC2_ES_VS__CI__VI { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int OC_LDS_EN : 1; - unsigned int EXCP_EN : 9; - unsigned int : 3; - unsigned int LDS_SIZE : 9; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC2_GS { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int EXCP_EN : 9; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC2_HS { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int OC_LDS_EN : 1; - unsigned int TG_SIZE_EN : 1; - unsigned int EXCP_EN : 9; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC2_LS { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int LDS_SIZE : 9; - unsigned int EXCP_EN : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC2_LS_ES__CI__VI { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int LDS_SIZE : 9; - unsigned int EXCP_EN : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC2_LS_HS__CI__VI { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int LDS_SIZE : 9; - unsigned int EXCP_EN : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC2_LS_VS__CI__VI { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int LDS_SIZE : 9; - unsigned int EXCP_EN : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC2_PS { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int WAVE_CNT_EN : 1; - unsigned int EXTRA_LDS_SIZE : 8; - unsigned int EXCP_EN : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC2_VS { - struct { - unsigned int SCRATCH_EN : 1; - unsigned int USER_SGPR : 5; - unsigned int TRAP_PRESENT : 1; - unsigned int OC_LDS_EN : 1; - unsigned int SO_BASE0_EN : 1; - unsigned int SO_BASE1_EN : 1; - unsigned int SO_BASE2_EN : 1; - unsigned int SO_BASE3_EN : 1; - unsigned int SO_EN : 1; - unsigned int EXCP_EN : 9; - unsigned int : 2; - unsigned int DISPATCH_DRAW_EN__VI : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC3_ES__CI__VI { - struct { - unsigned int CU_EN : 16; - unsigned int WAVE_LIMIT : 6; - unsigned int LOCK_LOW_THRESHOLD : 4; - unsigned int GROUP_FIFO_DEPTH__VI : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC3_GS__CI__VI { - struct { - unsigned int CU_EN : 16; - unsigned int WAVE_LIMIT : 6; - unsigned int LOCK_LOW_THRESHOLD : 4; - unsigned int GROUP_FIFO_DEPTH__VI : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC3_HS__CI__VI { - struct { - unsigned int WAVE_LIMIT : 6; - unsigned int LOCK_LOW_THRESHOLD : 4; - unsigned int GROUP_FIFO_DEPTH__VI : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC3_LS__CI__VI { - struct { - unsigned int CU_EN : 16; - unsigned int WAVE_LIMIT : 6; - unsigned int LOCK_LOW_THRESHOLD : 4; - unsigned int GROUP_FIFO_DEPTH__VI : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC3_PS__CI__VI { - struct { - unsigned int CU_EN : 16; - unsigned int WAVE_LIMIT : 6; - unsigned int LOCK_LOW_THRESHOLD : 4; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_PGM_RSRC3_VS__CI__VI { - struct { - unsigned int CU_EN : 16; - unsigned int WAVE_LIMIT : 6; - unsigned int LOCK_LOW_THRESHOLD : 4; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_POS_FORMAT { - struct { - unsigned int POS0_EXPORT_FORMAT : 4; - unsigned int POS1_EXPORT_FORMAT : 4; - unsigned int POS2_EXPORT_FORMAT : 4; - unsigned int POS3_EXPORT_FORMAT : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_HI_ES { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_HI_GS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_HI_HS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_HI_LS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_HI_PS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_HI_VS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_LO_ES { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_LO_GS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_LO_HS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_LO_LS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_LO_PS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TBA_LO_VS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_HI_ES { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_HI_GS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_HI_HS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_HI_LS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_HI_PS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_HI_VS { - struct { - unsigned int MEM_BASE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_LO_ES { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_LO_GS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_LO_HS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_LO_LS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_LO_PS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_TMA_LO_VS { - struct { - unsigned int MEM_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_10 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_11 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_12 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_13 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_14 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_15 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_3 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_4 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_5 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_6 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_7 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_8 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_ES_9 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_10 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_11 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_12 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_13 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_14 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_15 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_3 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_4 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_5 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_6 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_7 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_8 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_GS_9 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_10 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_11 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_12 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_13 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_14 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_15 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_3 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_4 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_5 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_6 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_7 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_8 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_HS_9 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_10 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_11 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_12 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_13 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_14 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_15 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_3 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_4 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_5 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_6 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_7 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_8 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_LS_9 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_10 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_11 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_12 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_13 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_14 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_15 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_3 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_4 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_5 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_6 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_7 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_8 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_PS_9 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_10 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_11 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_12 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_13 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_14 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_15 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_3 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_4 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_5 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_6 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_7 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_8 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_USER_DATA_VS_9 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SHADER_Z_FORMAT { - struct { - unsigned int Z_EXPORT_FORMAT : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SLAVE_DEBUG_BUSY { - struct { - unsigned int LS_VTX_BUSY : 1; - unsigned int HS_VTX_BUSY : 1; - unsigned int ES_VTX_BUSY : 1; - unsigned int GS_VTX_BUSY : 1; - unsigned int VS_VTX_BUSY : 1; - unsigned int VGPR_WC00_BUSY : 1; - unsigned int VGPR_WC01_BUSY : 1; - unsigned int VGPR_WC10_BUSY : 1; - unsigned int VGPR_WC11_BUSY : 1; - unsigned int SGPR_WC00_BUSY : 1; - unsigned int SGPR_WC01_BUSY : 1; - unsigned int SGPR_WC02_BUSY : 1; - unsigned int SGPR_WC03_BUSY : 1; - unsigned int SGPR_WC10_BUSY : 1; - unsigned int SGPR_WC11_BUSY : 1; - unsigned int SGPR_WC12_BUSY : 1; - unsigned int SGPR_WC13_BUSY : 1; - unsigned int WAVEBUFFER0_BUSY : 1; - unsigned int WAVEBUFFER1_BUSY : 1; - unsigned int WAVE_WC0_BUSY : 1; - unsigned int WAVE_WC1_BUSY : 1; - unsigned int EVENT_CNTL_BUSY : 1; - unsigned int SAVE_CTX_BUSY__VI : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_STATIC_THREAD_MGMT_1__SI { - struct { - unsigned int : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_STATIC_THREAD_MGMT_2__SI { - struct { - unsigned int : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_STATIC_THREAD_MGMT_3__SI { - struct { - unsigned int LSHS_CU_EN : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SX_EXPORT_BUFFER_SIZES { - struct { - unsigned int COLOR_BUFFER_SIZE : 16; - unsigned int POSITION_BUFFER_SIZE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_SX_SCOREBOARD_BUFFER_SIZES { - struct { - unsigned int COLOR_SCOREBOARD_SIZE : 16; - unsigned int POSITION_SCOREBOARD_SIZE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_TMPRING_SIZE { - struct { - unsigned int WAVES : 12; - unsigned int WAVESIZE : 13; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_VS_OUT_CONFIG { - struct { - unsigned int : 1; - unsigned int VS_EXPORT_COUNT : 5; - unsigned int VS_HALF_PACK : 1; - unsigned int : 1; - unsigned int : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WCL_PIPE_PERCENT_CS0__CI__VI { - struct { - unsigned int VALUE : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WCL_PIPE_PERCENT_CS1__CI__VI { - struct { - unsigned int VALUE : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WCL_PIPE_PERCENT_CS2__CI__VI { - struct { - unsigned int VALUE : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WCL_PIPE_PERCENT_CS3__CI__VI { - struct { - unsigned int VALUE : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WCL_PIPE_PERCENT_CS4__CI__VI { - struct { - unsigned int VALUE : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WCL_PIPE_PERCENT_CS5__CI__VI { - struct { - unsigned int VALUE : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WCL_PIPE_PERCENT_CS6__CI__VI { - struct { - unsigned int VALUE : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WCL_PIPE_PERCENT_CS7__CI__VI { - struct { - unsigned int VALUE : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WCL_PIPE_PERCENT_GFX__CI__VI { - struct { - unsigned int VALUE : 7; - unsigned int LS_GRP_VALUE__VI : 5; - unsigned int HS_GRP_VALUE__VI : 5; - unsigned int ES_GRP_VALUE__VI : 5; - unsigned int GS_GRP_VALUE__VI : 5; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WCL_PIPE_PERCENT_HP3D__CI__VI { - struct { - unsigned int VALUE : 7; - unsigned int LS_GRP_VALUE__VI : 5; - unsigned int HS_GRP_VALUE__VI : 5; - unsigned int ES_GRP_VALUE__VI : 5; - unsigned int GS_GRP_VALUE__VI : 5; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_CNTL__CI__VI { - struct { - unsigned int SAMPLE_PERIOD : 4; - unsigned int EN : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_DEBUG__CI__VI { - struct { - unsigned int START_VALUE : 31; - unsigned int OVERRIDE_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_LIMIT_0__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int EN_WARN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_LIMIT_1__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int EN_WARN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_LIMIT_2__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int EN_WARN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_LIMIT_3__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int EN_WARN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_LIMIT_4__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int EN_WARN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_LIMIT_5__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int EN_WARN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_LIMIT_6__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int EN_WARN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_LIMIT_7__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int EN_WARN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_LIMIT_8__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int EN_WARN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_LIMIT_9__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int EN_WARN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_0__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_10__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_11__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_12__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_13__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_14__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_15__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_16__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_17__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_18__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_19__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_1__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_20__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_2__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_3__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_4__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_5__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_6__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_7__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_8__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_WF_LIFETIME_STATUS_9__CI__VI { - struct { - unsigned int MAX_CNT : 31; - unsigned int INT_SENT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPLL_CNTL_MODE__CI__VI { - struct { - unsigned int SPLL_SW_DIR_CONTROL : 1; - unsigned int SPLL_LEGACY_PDIV : 1; - unsigned int SPLL_TEST : 1; - unsigned int SPLL_FASTEN : 1; - unsigned int SPLL_ENSAT : 1; - unsigned int : 5; - unsigned int SPLL_TEST_CLK_EXT_DIV : 2; - unsigned int SPLL_CTLREQ_DLY_CNT : 8; - unsigned int : 8; - unsigned int SPLL_RESET_EN : 1; - unsigned int SPLL_VCO_MODE : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPLL_CNTL_MODE__SI { - struct { - unsigned int SPLL_SW_DIR_CONTROL : 1; - unsigned int SPLL_LEGACY_PDIV : 1; - unsigned int SPLL_TEST : 1; - unsigned int SPLL_FASTEN : 1; - unsigned int SPLL_ENSAT : 1; - unsigned int : 5; - unsigned int SPLL_TEST_CLK_EXT_DIV : 2; - unsigned int SPLL_CTLREQ_DLY_CNT : 8; - unsigned int : 6; - unsigned int : 2; - unsigned int SPLL_RESET_EN : 1; - unsigned int SPLL_VCO_MODE : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_C6_STATE_0__CI__VI { - struct { - unsigned int SPMI_IF_C6_STATE_ENTERED : 1; - unsigned int SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY : 1; - unsigned int SPMI_IF_COUNTER_ADDRESS_C6 : 15; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_C6_STATE_1__CI { - struct { - unsigned int SPMI_IF_C6_STATE_ENTERED : 1; - unsigned int SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY : 1; - unsigned int SPMI_IF_COUNTER_ADDRESS_C6 : 15; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_FSM_BUSY_0__CI__VI { - struct { - unsigned int FSM_BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_FSM_BUSY_1__CI { - struct { - unsigned int FSM_BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_FSM_READ_TRIGGER_0__CI__VI { - struct { - unsigned int FSM_READ_TRIGGER : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_FSM_READ_TRIGGER_1__CI { - struct { - unsigned int FSM_READ_TRIGGER : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_FSM_RESET_TRIGGER_0__CI__VI { - struct { - unsigned int FSM_RESET_TRIGGER : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_FSM_RESET_TRIGGER_1__CI { - struct { - unsigned int FSM_RESET_TRIGGER : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_FSM_WRITE_TRIGGER_0__CI__VI { - struct { - unsigned int FSM_WRITE_TRIGGER : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_FSM_WRITE_TRIGGER_1__CI { - struct { - unsigned int FSM_WRITE_TRIGGER : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_JTAG_OVER_0__CI__VI { - struct { - unsigned int SPMI_IF_JTAG_OVER_HAPPENED : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_JTAG_OVER_1__CI { - struct { - unsigned int SPMI_IF_JTAG_OVER_HAPPENED : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_PATH_0__CI__VI { - struct { - unsigned int PATH_ENABLE_REQ : 1; - unsigned int PATH_ENABLE_ACK : 1; - unsigned int : 2; - unsigned int PATH_ENABLE_REQ_auto_clear : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_PATH_1__CI { - struct { - unsigned int PATH_ENABLE_REQ : 1; - unsigned int PATH_ENABLE_ACK : 1; - unsigned int : 2; - unsigned int PATH_ENABLE_REQ_auto_clear : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_RESET__CI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_RESET__VI { - struct { - unsigned int : 1; - unsigned int : 30; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_SRAM_ADDRESS__CI__VI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_SRAM_DATA__CI__VI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQC_CACHES__SI__CI { - struct { - unsigned int INST_INVALIDATE : 1; - unsigned int DATA_INVALIDATE : 1; - unsigned int INVALIDATE_VOLATILE__CI : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQC_CACHES__VI { - struct { - unsigned int TARGET_INST : 1; - unsigned int TARGET_DATA : 1; - unsigned int INVALIDATE : 1; - unsigned int WRITEBACK : 1; - unsigned int VOL : 1; - unsigned int : 11; - unsigned int COMPLETE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQC_CONFIG { - struct { - unsigned int INST_CACHE_SIZE : 2; - unsigned int DATA_CACHE_SIZE : 2; - unsigned int MISS_FIFO_DEPTH : 2; - unsigned int HIT_FIFO_DEPTH : 1; - unsigned int FORCE_ALWAYS_MISS : 1; - unsigned int FORCE_IN_ORDER : 1; - unsigned int IDENTITY_HASH_BANK : 1; - unsigned int IDENTITY_HASH_SET : 1; - unsigned int PER_VMID_INV_DISABLE__CI__VI : 1; - unsigned int EVICT_LRU__VI : 2; - unsigned int FORCE_2_BANK__VI : 1; - unsigned int FORCE_1_BANK__VI : 1; - unsigned int LS_DISABLE_CLOCKS__VI : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQC_POLICY__CI { - struct { - unsigned int DATA_L1_POLICY_0 : 1; - unsigned int DATA_L1_POLICY_1 : 1; - unsigned int DATA_L1_POLICY_2 : 1; - unsigned int DATA_L1_POLICY_3 : 1; - unsigned int DATA_L1_POLICY_4 : 1; - unsigned int DATA_L1_POLICY_5 : 1; - unsigned int DATA_L1_POLICY_6 : 1; - unsigned int DATA_L1_POLICY_7 : 1; - unsigned int DATA_L2_POLICY_0 : 2; - unsigned int DATA_L2_POLICY_1 : 2; - unsigned int DATA_L2_POLICY_2 : 2; - unsigned int DATA_L2_POLICY_3 : 2; - unsigned int DATA_L2_POLICY_4 : 2; - unsigned int DATA_L2_POLICY_5 : 2; - unsigned int DATA_L2_POLICY_6 : 2; - unsigned int DATA_L2_POLICY_7 : 2; - unsigned int INST_L2_POLICY : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQC_SECDED_CNT__SI__CI { - struct { - unsigned int INST_SEC : 8; - unsigned int INST_DED : 8; - unsigned int DATA_SEC : 8; - unsigned int DATA_DED : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQC_VOLATILE__CI { - struct { - unsigned int DATA_L1 : 4; - unsigned int DATA_L2 : 4; - unsigned int INST_L2 : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_ALU_CLK_CTRL { - struct { - unsigned int FORCE_CU_ON_SH0 : 16; - unsigned int FORCE_CU_ON_SH1 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_BUF_RSRC_WORD0 { - struct { - unsigned int BASE_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_BUF_RSRC_WORD1 { - struct { - unsigned int BASE_ADDRESS_HI : 16; - unsigned int STRIDE : 14; - unsigned int CACHE_SWIZZLE : 1; - unsigned int SWIZZLE_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_BUF_RSRC_WORD2 { - struct { - unsigned int NUM_RECORDS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_BUF_RSRC_WORD3 { - struct { - unsigned int DST_SEL_X : 3; - unsigned int DST_SEL_Y : 3; - unsigned int DST_SEL_Z : 3; - unsigned int DST_SEL_W : 3; - unsigned int NUM_FORMAT : 3; - unsigned int DATA_FORMAT : 4; - unsigned int ELEMENT_SIZE : 2; - unsigned int INDEX_STRIDE : 2; - unsigned int ADD_TID_ENABLE : 1; - unsigned int ATC__CI__VI : 1; - unsigned int HASH_ENABLE : 1; - unsigned int HEAP : 1; - unsigned int MTYPE__CI__VI : 3; - unsigned int TYPE : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_CMD_TIMESTAMP__CI__VI { - struct { - unsigned int TIMESTAMP : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_CMD__CI { - struct { - unsigned int CMD : 3; - unsigned int : 1; - unsigned int MODE : 3; - unsigned int CHECK_VMID : 1; - unsigned int TRAP_ID : 3; - unsigned int : 5; - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int : 2; - unsigned int QUEUE_ID : 3; - unsigned int : 1; - unsigned int VM_ID : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_CMD__VI { - struct { - unsigned int CMD : 3; - unsigned int : 1; - unsigned int MODE : 3; - unsigned int CHECK_VMID : 1; - unsigned int DATA : 3; - unsigned int : 5; - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int : 2; - unsigned int QUEUE_ID : 3; - unsigned int : 1; - unsigned int VM_ID : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_CONFIG__SI__CI { - struct { - unsigned int UNUSED : 8; - unsigned int DEBUG_EN : 1; - unsigned int DISABLE_SCA_BYPASS : 1; - unsigned int DISABLE_IB_DEP_CHECK : 1; - unsigned int ENABLE_SOFT_CLAUSE__CI : 1; - unsigned int EARLY_TA_DONE_DISABLE__CI : 1; - unsigned int DUA_FLAT_LOCK_ENABLE__CI : 1; - unsigned int DUA_LDS_BYPASS_DISABLE__CI : 1; - unsigned int DUA_FLAT_LDS_PINGPONG_DISABLE__CI : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_CONFIG__VI { - struct { - unsigned int UNUSED : 8; - unsigned int DEBUG_EN : 1; - unsigned int DEBUG_SINGLE_MEMOP : 1; - unsigned int DEBUG_ONE_INST_CLAUSE : 1; - unsigned int : 1; - unsigned int EARLY_TA_DONE_DISABLE : 1; - unsigned int DUA_FLAT_LOCK_ENABLE : 1; - unsigned int DUA_LDS_BYPASS_DISABLE : 1; - unsigned int DUA_FLAT_LDS_PINGPONG_DISABLE : 1; - unsigned int DISABLE_VMEM_SOFT_CLAUSE : 1; - unsigned int DISABLE_SMEM_SOFT_CLAUSE : 1; - unsigned int ENABLE_HIPRIO_ON_EXP_RDY_VS : 1; - unsigned int PRIO_VAL_ON_EXP_RDY_VS : 2; - unsigned int REPLAY_SLEEP_CNT : 4; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_DEBUG_CTRL_LOCAL { - struct { - unsigned int UNUSED : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_DEBUG_STS_GLOBAL { - struct { - unsigned int BUSY : 1; - unsigned int INTERRUPT_MSG_BUSY__CI__VI : 1; - unsigned int : 2; - unsigned int WAVE_LEVEL_SH0 : 12; - unsigned int WAVE_LEVEL_SH1 : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_DEBUG_STS_GLOBAL2__CI__VI { - struct { - unsigned int FIFO_LEVEL_GFX0 : 8; - unsigned int FIFO_LEVEL_GFX1 : 8; - unsigned int FIFO_LEVEL_IMMED : 8; - unsigned int FIFO_LEVEL_HOST : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_DEBUG_STS_GLOBAL3__CI__VI { - struct { - unsigned int FIFO_LEVEL_HOST_CMD : 4; - unsigned int FIFO_LEVEL_HOST_REG : 6; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_DEBUG_STS_LOCAL { - struct { - unsigned int BUSY : 1; - unsigned int : 3; - unsigned int WAVE_LEVEL : 6; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_DED_CNT__SI__CI { - struct { - unsigned int LDS_DED : 6; - unsigned int : 2; - unsigned int SGPR_DED : 5; - unsigned int : 3; - unsigned int VGPR_DED : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_DED_INFO__SI__CI { - struct { - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int SOURCE : 3; - unsigned int VM_ID : 4; - unsigned int : 3; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_DS_0__SI__CI { - struct { - unsigned int OFFSET0 : 8; - unsigned int OFFSET1 : 8; - unsigned int : 1; - unsigned int GDS : 1; - unsigned int OP : 8; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_DS_0__VI { - struct { - unsigned int OFFSET0 : 8; - unsigned int OFFSET1 : 8; - unsigned int GDS : 1; - unsigned int OP : 8; - unsigned int : 1; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_DS_1 { - struct { - unsigned int ADDR : 8; - unsigned int DATA0 : 8; - unsigned int DATA1 : 8; - unsigned int VDST : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_EXP_0 { - struct { - unsigned int EN : 4; - unsigned int TGT : 6; - unsigned int COMPR : 1; - unsigned int DONE : 1; - unsigned int VM : 1; - unsigned int : 13; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_EXP_1 { - struct { - unsigned int VSRC0 : 8; - unsigned int VSRC1 : 8; - unsigned int VSRC2 : 8; - unsigned int VSRC3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_FIFO_SIZES { - struct { - unsigned int INTERRUPT_FIFO_SIZE : 4; - unsigned int : 4; - unsigned int TTRACE_FIFO_SIZE : 4; - unsigned int : 4; - unsigned int EXPORT_BUF_SIZE : 2; - unsigned int VMEM_DATA_FIFO_SIZE : 2; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_FLAT_0__CI__VI { - struct { - unsigned int : 16; - unsigned int GLC : 1; - unsigned int SLC : 1; - unsigned int OP : 7; - unsigned int : 1; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_FLAT_1__CI__VI { - struct { - unsigned int ADDR : 8; - unsigned int DATA : 8; - unsigned int : 7; - unsigned int TFE : 1; - unsigned int VDST : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_FLAT_SCRATCH_WORD0__CI__VI { - struct { - unsigned int SIZE : 19; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_FLAT_SCRATCH_WORD1__CI__VI { - struct { - unsigned int OFFSET : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_HV_VMID_CTRL__CI__VI { - struct { - unsigned int DEFAULT_VMID : 4; - unsigned int ALLOWED_VMID_MASK : 16; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_RSRC_WORD0 { - struct { - unsigned int BASE_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_RSRC_WORD1 { - struct { - unsigned int BASE_ADDRESS_HI : 8; - unsigned int MIN_LOD : 12; - unsigned int DATA_FORMAT : 6; - unsigned int NUM_FORMAT : 4; - unsigned int MTYPE__CI__VI : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_RSRC_WORD2 { - struct { - unsigned int WIDTH : 14; - unsigned int HEIGHT : 14; - unsigned int PERF_MOD : 3; - unsigned int INTERLACED : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_RSRC_WORD3 { - struct { - unsigned int DST_SEL_X : 3; - unsigned int DST_SEL_Y : 3; - unsigned int DST_SEL_Z : 3; - unsigned int DST_SEL_W : 3; - unsigned int BASE_LEVEL : 4; - unsigned int LAST_LEVEL : 4; - unsigned int TILING_INDEX : 5; - unsigned int POW2_PAD : 1; - unsigned int MTYPE__CI__VI : 1; - unsigned int ATC__CI__VI : 1; - unsigned int TYPE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_RSRC_WORD4 { - struct { - unsigned int DEPTH : 13; - unsigned int PITCH : 14; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_RSRC_WORD5 { - struct { - unsigned int BASE_ARRAY : 13; - unsigned int LAST_ARRAY : 13; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_RSRC_WORD6 { - struct { - unsigned int MIN_LOD_WARN : 12; - unsigned int COUNTER_BANK_ID__CI__VI : 8; - unsigned int LOD_HDW_CNT_EN__CI__VI : 1; - unsigned int COMPRESSION_EN__VI : 1; - unsigned int ALPHA_IS_ON_MSB__VI : 1; - unsigned int COLOR_TRANSFORM__VI : 1; - unsigned int LOST_ALPHA_BITS__VI : 4; - unsigned int LOST_COLOR_BITS__VI : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_RSRC_WORD7 { - struct { - unsigned int META_DATA_ADDRESS__VI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_SAMP_WORD0 { - struct { - unsigned int CLAMP_X : 3; - unsigned int CLAMP_Y : 3; - unsigned int CLAMP_Z : 3; - unsigned int MAX_ANISO_RATIO : 3; - unsigned int DEPTH_COMPARE_FUNC : 3; - unsigned int FORCE_UNNORMALIZED : 1; - unsigned int ANISO_THRESHOLD : 3; - unsigned int MC_COORD_TRUNC : 1; - unsigned int FORCE_DEGAMMA : 1; - unsigned int ANISO_BIAS : 6; - unsigned int TRUNC_COORD : 1; - unsigned int DISABLE_CUBE_WRAP : 1; - unsigned int FILTER_MODE : 2; - unsigned int COMPAT_MODE__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_SAMP_WORD1 { - struct { - unsigned int MIN_LOD : 12; - unsigned int MAX_LOD : 12; - unsigned int PERF_MIP : 4; - unsigned int PERF_Z : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_SAMP_WORD2 { - struct { - unsigned int LOD_BIAS : 14; - unsigned int LOD_BIAS_SEC : 6; - unsigned int XY_MAG_FILTER : 2; - unsigned int XY_MIN_FILTER : 2; - unsigned int Z_FILTER : 2; - unsigned int MIP_FILTER : 2; - unsigned int MIP_POINT_PRECLAMP : 1; - unsigned int DISABLE_LSB_CEIL : 1; - unsigned int FILTER_PREC_FIX : 1; - unsigned int ANISO_OVERRIDE__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IMG_SAMP_WORD3 { - struct { - unsigned int BORDER_COLOR_PTR : 12; - unsigned int : 18; - unsigned int BORDER_COLOR_TYPE : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IND_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_IND_INDEX { - struct { - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int THREAD_ID : 6; - unsigned int AUTO_INCR__CI__VI : 1; - unsigned int FORCE_READ__CI__VI : 1; - unsigned int READ_TIMEOUT : 1; - unsigned int UNINDEXED : 1; - unsigned int INDEX : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_INST { - struct { - unsigned int ENCODING : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_INTERRUPT_AUTO_MASK__CI__VI { - struct { - unsigned int MASK : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_INTERRUPT_MSG_CTRL__CI__VI { - struct { - unsigned int STALL : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_INTERRUPT_WORD_AUTO__CI__VI { - struct { - unsigned int THREAD_TRACE : 1; - unsigned int WLT : 1; - unsigned int THREAD_TRACE_BUF_FULL : 1; - unsigned int REG_TIMESTAMP : 1; - unsigned int CMD_TIMESTAMP : 1; - unsigned int HOST_CMD_OVERFLOW : 1; - unsigned int HOST_REG_OVERFLOW : 1; - unsigned int IMMED_OVERFLOW : 1; - unsigned int : 16; - unsigned int SE_ID : 2; - unsigned int ENCODING : 2; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_INTERRUPT_WORD_AUTO__SI { - struct { - unsigned int THREAD_TRACE : 1; - unsigned int : 24; - unsigned int SE_ID : 1; - unsigned int ENCODING : 2; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_INTERRUPT_WORD_CMN__CI__VI { - struct { - unsigned int : 24; - unsigned int SE_ID : 2; - unsigned int ENCODING : 2; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_INTERRUPT_WORD_CMN__SI { - struct { - unsigned int : 25; - unsigned int SE_ID : 1; - unsigned int ENCODING : 2; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_INTERRUPT_WORD_WAVE__CI__VI { - struct { - unsigned int DATA : 8; - unsigned int SH_ID : 1; - unsigned int PRIV : 1; - unsigned int VM_ID : 4; - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int CU_ID : 4; - unsigned int SE_ID : 2; - unsigned int ENCODING : 2; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_INTERRUPT_WORD_WAVE__SI { - struct { - unsigned int DATA : 8; - unsigned int : 2; - unsigned int VM_ID : 4; - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int CU_ID : 4; - unsigned int SH_ID : 1; - unsigned int SE_ID : 1; - unsigned int ENCODING : 2; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_LB_CTR_CTRL { - struct { - unsigned int START : 1; - unsigned int LOAD : 1; - unsigned int CLEAR : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_LB_DATA_ALU_CYCLES { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_LB_DATA_ALU_STALLS { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_LB_DATA_TEX_CYCLES { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_LB_DATA_TEX_STALLS { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_LDS_CLK_CTRL__CI__VI { - struct { - unsigned int FORCE_CU_ON_SH0 : 16; - unsigned int FORCE_CU_ON_SH1 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_MIMG_0 { - struct { - unsigned int : 8; - unsigned int DMASK : 4; - unsigned int UNORM : 1; - unsigned int GLC : 1; - unsigned int DA : 1; - unsigned int R128 : 1; - unsigned int TFE : 1; - unsigned int LWE : 1; - unsigned int OP : 7; - unsigned int SLC : 1; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_MIMG_1 { - struct { - unsigned int VADDR : 8; - unsigned int VDATA : 8; - unsigned int SRSRC : 5; - unsigned int SSAMP : 5; - unsigned int : 5; - unsigned int D16__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_MTBUF_0__SI__CI { - struct { - unsigned int OFFSET : 12; - unsigned int OFFEN : 1; - unsigned int IDXEN : 1; - unsigned int GLC : 1; - unsigned int ADDR64 : 1; - unsigned int OP : 3; - unsigned int DFMT : 4; - unsigned int NFMT : 3; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_MTBUF_0__VI { - struct { - unsigned int OFFSET : 12; - unsigned int OFFEN : 1; - unsigned int IDXEN : 1; - unsigned int GLC : 1; - unsigned int OP : 4; - unsigned int DFMT : 4; - unsigned int NFMT : 3; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_MTBUF_1 { - struct { - unsigned int VADDR : 8; - unsigned int VDATA : 8; - unsigned int SRSRC : 5; - unsigned int : 1; - unsigned int SLC : 1; - unsigned int TFE : 1; - unsigned int SOFFSET : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_MUBUF_0 { - struct { - unsigned int OFFSET : 12; - unsigned int OFFEN : 1; - unsigned int IDXEN : 1; - unsigned int GLC : 1; - unsigned int ADDR64__SI__CI : 1; - unsigned int LDS : 1; - unsigned int SLC__VI : 1; - unsigned int OP : 7; - unsigned int : 1; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_MUBUF_1__SI__CI { - struct { - unsigned int VADDR : 8; - unsigned int VDATA : 8; - unsigned int SRSRC : 5; - unsigned int : 1; - unsigned int SLC : 1; - unsigned int TFE : 1; - unsigned int SOFFSET : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_MUBUF_1__VI { - struct { - unsigned int VADDR : 8; - unsigned int VDATA : 8; - unsigned int SRSRC : 5; - unsigned int : 2; - unsigned int TFE : 1; - unsigned int SOFFSET : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER0_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER0_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER10_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER10_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER10_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER10_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER11_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER11_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER11_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER11_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER12_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER12_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER12_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER12_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER13_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER13_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER13_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER13_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER14_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER14_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER14_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER14_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER15_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER15_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER15_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER15_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER1_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER1_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER2_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER2_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER3_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER3_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER4_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER4_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER4_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER4_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER5_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER5_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER5_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER5_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER6_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER6_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER6_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER6_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER7_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER7_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER7_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER7_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER8_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER8_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER8_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER8_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER9_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER9_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER9_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 3; - unsigned int SQC_BANK_MASK : 4; - unsigned int SQC_CLIENT_MASK : 4; - unsigned int SPM_MODE : 4; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER9_SELECT__SI { - struct { - unsigned int PERF_SEL : 9; - unsigned int : 15; - unsigned int SIMD_MASK : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER_CTRL { - struct { - unsigned int PS_EN : 1; - unsigned int VS_EN : 1; - unsigned int GS_EN : 1; - unsigned int ES_EN : 1; - unsigned int HS_EN : 1; - unsigned int LS_EN : 1; - unsigned int CS_EN : 1; - unsigned int : 1; - unsigned int CNTR_RATE : 5; - unsigned int DISABLE_FLUSH : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER_CTRL2__CI__VI { - struct { - unsigned int FORCE_EN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_PERFCOUNTER_MASK__CI__VI { - struct { - unsigned int SH0_MASK : 16; - unsigned int SH1_MASK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_POWER_THROTTLE { - struct { - unsigned int MIN_POWER : 14; - unsigned int : 2; - unsigned int MAX_POWER : 14; - unsigned int PHASE_OFFSET : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_POWER_THROTTLE2 { - struct { - unsigned int MAX_POWER_DELTA : 14; - unsigned int : 2; - unsigned int SHORT_TERM_INTERVAL_SIZE : 10; - unsigned int : 1; - unsigned int LONG_TERM_INTERVAL_RATIO : 4; - unsigned int USE_REF_CLOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_RANDOM_WAVE_PRI { - struct { - unsigned int RET : 7; - unsigned int RUI : 3; - unsigned int RNG : 11; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_REG_CREDITS { - struct { - unsigned int SRBM_CREDITS : 6; - unsigned int : 2; - unsigned int CMD_CREDITS : 4; - unsigned int : 16; - unsigned int REG_BUSY__CI__VI : 1; - unsigned int SRBM_OVERFLOW__CI__VI : 1; - unsigned int IMMED_OVERFLOW__CI__VI : 1; - unsigned int CMD_OVERFLOW__CI__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_REG_TIMESTAMP__CI__VI { - struct { - unsigned int TIMESTAMP : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_SEC_CNT__SI__CI { - struct { - unsigned int LDS_SEC : 6; - unsigned int : 2; - unsigned int SGPR_SEC : 5; - unsigned int : 3; - unsigned int VGPR_SEC : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_SMRD__SI__CI { - struct { - unsigned int OFFSET : 8; - unsigned int IMM : 1; - unsigned int SBASE : 6; - unsigned int SDST : 7; - unsigned int OP : 5; - unsigned int ENCODING : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_SOP1 { - struct { - unsigned int SSRC0 : 8; - unsigned int OP : 8; - unsigned int SDST : 7; - unsigned int ENCODING : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_SOP2 { - struct { - unsigned int SSRC0 : 8; - unsigned int SSRC1 : 8; - unsigned int SDST : 7; - unsigned int OP : 7; - unsigned int ENCODING : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_SOPC { - struct { - unsigned int SSRC0 : 8; - unsigned int SSRC1 : 8; - unsigned int OP : 7; - unsigned int ENCODING : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_SOPK { - struct { - unsigned int SIMM16 : 16; - unsigned int SDST : 7; - unsigned int OP : 5; - unsigned int ENCODING : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_SOPP { - struct { - unsigned int SIMM16 : 16; - unsigned int OP : 7; - unsigned int ENCODING : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_TEX_CLK_CTRL { - struct { - unsigned int FORCE_CU_ON_SH0 : 16; - unsigned int FORCE_CU_ON_SH1 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_BASE { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_BASE2__CI__VI { - struct { - unsigned int ADDR_HI : 4; - unsigned int ATC : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_CNTR { - struct { - unsigned int CNTR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_CTRL { - struct { - unsigned int : 31; - unsigned int RESET_BUFFER : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_HIWATER { - struct { - unsigned int HIWATER : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_MASK { - struct { - unsigned int CU_SEL : 5; - unsigned int SH_SEL : 1; - unsigned int : 1; - unsigned int REG_STALL_EN__CI__VI : 1; - unsigned int SIMD_EN : 4; - unsigned int VM_ID_MASK : 2; - unsigned int SPI_STALL_EN__CI__VI : 1; - unsigned int SQ_STALL_EN__CI__VI : 1; - unsigned int RANDOM_SEED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_MODE { - struct { - unsigned int MASK_PS : 3; - unsigned int MASK_VS : 3; - unsigned int MASK_GS : 3; - unsigned int MASK_ES : 3; - unsigned int MASK_HS : 3; - unsigned int MASK_LS : 3; - unsigned int MASK_CS : 3; - unsigned int MODE : 2; - unsigned int CAPTURE_MODE : 2; - unsigned int AUTOFLUSH_EN : 1; - unsigned int PRIV : 1; - unsigned int ISSUE_MASK : 2; - unsigned int TEST_MODE : 1; - unsigned int INTERRUPT_EN : 1; - unsigned int WRAP : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_PERF_MASK { - struct { - unsigned int SH0_MASK : 16; - unsigned int SH1_MASK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_SIZE { - struct { - unsigned int SIZE : 22; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_STATUS { - struct { - unsigned int FINISH_PENDING : 10; - unsigned int : 6; - unsigned int FINISH_DONE : 10; - unsigned int : 3; - unsigned int NEW_BUF : 1; - unsigned int BUSY : 1; - unsigned int FULL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_TOKEN_MASK { - struct { - unsigned int TOKEN_MASK : 16; - unsigned int REG_MASK : 8; - unsigned int REG_DROP_ON_STALL__CI__VI : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_TOKEN_MASK2__CI { - struct { - unsigned int INST_MASK : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_TOKEN_MASK2__VI { - struct { - unsigned int INST_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_USERDATA_0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_USERDATA_1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_USERDATA_2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_USERDATA_3 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_CMN { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_EVENT { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int SH_ID : 1; - unsigned int STAGE : 3; - unsigned int : 1; - unsigned int EVENT_TYPE : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_INST__SI__CI { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int SIZE : 1; - unsigned int INST_TYPE : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_INST__VI { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int INST_TYPE : 5; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int : 5; - unsigned int PC_LO : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 { - struct { - unsigned int PC_HI : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int SH_ID : 1; - unsigned int CU_ID : 4; - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int DATA_LO : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 { - struct { - unsigned int DATA_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_ISSUE { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int SIMD_ID : 2; - unsigned int : 1; - unsigned int INST0 : 2; - unsigned int INST1 : 2; - unsigned int INST2 : 2; - unsigned int INST3 : 2; - unsigned int INST4 : 2; - unsigned int INST5 : 2; - unsigned int INST6 : 2; - unsigned int INST7 : 2; - unsigned int INST8 : 2; - unsigned int INST9 : 2; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_MISC__CI__VI { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 8; - unsigned int SH_ID : 1; - unsigned int MISC_TOKEN_TYPE : 3; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_MISC__SI { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int SH_ID : 1; - unsigned int MISC_TOKEN_TYPE : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_PERF_1_OF_2 { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int SH_ID : 1; - unsigned int CU_ID : 4; - unsigned int CNTR_BANK : 2; - unsigned int CNTR0 : 13; - unsigned int CNTR1_LO : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_PERF_2_OF_2 { - struct { - unsigned int CNTR1_HI : 6; - unsigned int CNTR2 : 13; - unsigned int CNTR3 : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_REG_1_OF_2__CI__VI { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int PIPE_ID : 2; - unsigned int ME_ID : 2; - unsigned int REG_DROPPED_PREV : 1; - unsigned int REG_TYPE : 3; - unsigned int : 1; - unsigned int REG_PRIV : 1; - unsigned int REG_OP : 1; - unsigned int REG_ADDR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_REG_1_OF_2__SI { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int : 5; - unsigned int REG_TYPE : 3; - unsigned int : 1; - unsigned int REG_PRIV : 1; - unsigned int REG_OP : 1; - unsigned int REG_ADDR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_REG_2_OF_2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__CI__VI { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int PIPE_ID : 2; - unsigned int ME_ID : 2; - unsigned int REG_ADDR : 7; - unsigned int DATA_LO : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__CI__VI { - struct { - unsigned int DATA_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int : 12; - unsigned int TIME_LO : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 { - struct { - unsigned int TIME_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_TIME__SI { - struct { - unsigned int : 4; - unsigned int : 10; - unsigned int : 1; - unsigned int : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_WAVE { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int SH_ID : 1; - unsigned int CU_ID : 4; - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WORD_WAVE_START { - struct { - unsigned int TOKEN_TYPE : 4; - unsigned int TIME_DELTA : 1; - unsigned int SH_ID : 1; - unsigned int CU_ID : 4; - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int DISPATCHER : 5; - unsigned int VS_NO_ALLOC_OR_GROUPED : 1; - unsigned int COUNT : 7; - unsigned int TG_ID : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_THREAD_TRACE_WPTR { - struct { - unsigned int WPTR : 30; - unsigned int READ_OFFSET : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_TIME_HI { - struct { - unsigned int TIME : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_TIME_LO { - struct { - unsigned int TIME : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_VINTRP { - struct { - unsigned int VSRC : 8; - unsigned int ATTRCHAN : 2; - unsigned int ATTR : 6; - unsigned int OP : 2; - unsigned int VDST : 8; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_VOP1 { - struct { - unsigned int SRC0 : 9; - unsigned int OP : 8; - unsigned int VDST : 8; - unsigned int ENCODING : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_VOP2 { - struct { - unsigned int SRC0 : 9; - unsigned int VSRC1 : 8; - unsigned int VDST : 8; - unsigned int OP : 6; - unsigned int ENCODING : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_VOP3_0__SI__CI { - struct { - unsigned int VDST : 8; - unsigned int ABS : 3; - unsigned int CLAMP : 1; - unsigned int : 5; - unsigned int OP : 9; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_VOP3_0__VI { - struct { - unsigned int VDST : 8; - unsigned int ABS : 3; - unsigned int : 4; - unsigned int CLAMP : 1; - unsigned int OP : 10; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_VOP3_0_SDST_ENC__SI__CI { - struct { - unsigned int VDST : 8; - unsigned int SDST : 7; - unsigned int : 2; - unsigned int OP : 9; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_VOP3_0_SDST_ENC__VI { - struct { - unsigned int VDST : 8; - unsigned int SDST : 7; - unsigned int CLAMP : 1; - unsigned int OP : 10; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_VOP3_1 { - struct { - unsigned int SRC0 : 9; - unsigned int SRC1 : 9; - unsigned int SRC2 : 9; - unsigned int OMOD : 2; - unsigned int NEG : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_VOPC { - struct { - unsigned int SRC0 : 9; - unsigned int VSRC1 : 8; - unsigned int OP : 8; - unsigned int ENCODING : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_EXEC_HI { - struct { - unsigned int EXEC_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_EXEC_LO { - struct { - unsigned int EXEC_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_GPR_ALLOC { - struct { - unsigned int VGPR_BASE : 6; - unsigned int : 2; - unsigned int VGPR_SIZE : 6; - unsigned int : 2; - unsigned int SGPR_BASE : 6; - unsigned int : 2; - unsigned int SGPR_SIZE : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_HW_ID__CI__VI { - struct { - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int PIPE_ID : 2; - unsigned int CU_ID : 4; - unsigned int SH_ID : 1; - unsigned int SE_ID : 2; - unsigned int : 1; - unsigned int TG_ID : 4; - unsigned int VM_ID : 4; - unsigned int QUEUE_ID : 3; - unsigned int STATE_ID : 3; - unsigned int ME_ID : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_HW_ID__SI { - struct { - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int : 2; - unsigned int CU_ID : 4; - unsigned int SH_ID : 1; - unsigned int SE_ID : 1; - unsigned int : 2; - unsigned int TG_ID : 4; - unsigned int VM_ID : 4; - unsigned int : 3; - unsigned int STATE_ID : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_IB_DBG0__SI__CI { - struct { - unsigned int IBUF_ST : 3; - unsigned int PC_INVALID : 1; - unsigned int NEED_NEXT_DW : 1; - unsigned int NO_PREFETCH_CNT : 3; - unsigned int IBUF_RPTR : 2; - unsigned int IBUF_WPTR : 2; - unsigned int : 4; - unsigned int INST_STR_ST : 3; - unsigned int MISC_CNT : 3; - unsigned int ECC_ST : 2; - unsigned int IS_HYB : 1; - unsigned int HYB_CNT : 2; - unsigned int KILL__CI : 1; - unsigned int NEED_KILL_IFETCH__CI : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_IB_DBG0__VI { - struct { - unsigned int IBUF_ST : 3; - unsigned int PC_INVALID : 1; - unsigned int NEED_NEXT_DW : 1; - unsigned int NO_PREFETCH_CNT : 3; - unsigned int IBUF_RPTR : 2; - unsigned int IBUF_WPTR : 2; - unsigned int : 4; - unsigned int INST_STR_ST : 4; - unsigned int MISC_CNT : 4; - unsigned int ECC_ST : 2; - unsigned int IS_HYB : 1; - unsigned int HYB_CNT : 2; - unsigned int KILL : 1; - unsigned int NEED_KILL_IFETCH : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_IB_STS__CI__VI { - struct { - unsigned int VM_CNT : 4; - unsigned int EXP_CNT : 3; - unsigned int : 1; - unsigned int LGKM_CNT : 4; - unsigned int VALU_CNT : 3; - unsigned int FIRST_REPLAY__VI : 1; - unsigned int RCNT__VI : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_IB_STS__SI { - struct { - unsigned int VM_CNT : 4; - unsigned int EXP_CNT : 3; - unsigned int : 1; - unsigned int LGKM_CNT : 5; - unsigned int VALU_CNT : 3; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_INST_DW0 { - struct { - unsigned int INST_DW0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_INST_DW1 { - struct { - unsigned int INST_DW1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_LDS_ALLOC { - struct { - unsigned int LDS_BASE : 8; - unsigned int : 4; - unsigned int LDS_SIZE : 9; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_M0 { - struct { - unsigned int M0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_MODE { - struct { - unsigned int FP_ROUND : 4; - unsigned int FP_DENORM : 4; - unsigned int DX10_CLAMP : 1; - unsigned int IEEE : 1; - unsigned int LOD_CLAMPED : 1; - unsigned int DEBUG_EN : 1; - unsigned int EXCP_EN : 9; - unsigned int : 6; - unsigned int GPR_IDX_EN__VI : 1; - unsigned int VSKIP : 1; - unsigned int CSP : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_PC_HI { - struct { - unsigned int PC_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_PC_LO { - struct { - unsigned int PC_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_STATUS__SI__CI { - struct { - unsigned int SCC : 1; - unsigned int SPI_PRIO : 2; - unsigned int WAVE_PRIO : 2; - unsigned int PRIV : 1; - unsigned int TRAP_EN : 1; - unsigned int TTRACE_EN : 1; - unsigned int EXPORT_RDY : 1; - unsigned int EXECZ : 1; - unsigned int VCCZ : 1; - unsigned int IN_TG : 1; - unsigned int IN_BARRIER : 1; - unsigned int HALT : 1; - unsigned int TRAP : 1; - unsigned int TTRACE_CU_EN : 1; - unsigned int VALID : 1; - unsigned int ECC_ERR : 1; - unsigned int SKIP_EXPORT : 1; - unsigned int PERF_EN : 1; - unsigned int COND_DBG_USER__CI : 1; - unsigned int COND_DBG_SYS__CI : 1; - unsigned int DATA_ATC__CI : 1; - unsigned int INST_ATC__CI : 1; - unsigned int DISPATCH_CACHE_CTRL__CI : 3; - unsigned int MUST_EXPORT__CI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_STATUS__VI { - struct { - unsigned int SCC : 1; - unsigned int SPI_PRIO : 2; - unsigned int USER_PRIO : 2; - unsigned int PRIV : 1; - unsigned int TRAP_EN : 1; - unsigned int TTRACE_EN : 1; - unsigned int EXPORT_RDY : 1; - unsigned int EXECZ : 1; - unsigned int VCCZ : 1; - unsigned int IN_TG : 1; - unsigned int IN_BARRIER : 1; - unsigned int HALT : 1; - unsigned int TRAP : 1; - unsigned int TTRACE_CU_EN : 1; - unsigned int VALID : 1; - unsigned int ECC_ERR : 1; - unsigned int SKIP_EXPORT : 1; - unsigned int PERF_EN : 1; - unsigned int COND_DBG_USER : 1; - unsigned int COND_DBG_SYS : 1; - unsigned int ALLOW_REPLAY : 1; - unsigned int INST_ATC : 1; - unsigned int : 3; - unsigned int MUST_EXPORT : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TBA_HI { - struct { - unsigned int ADDR_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TBA_LO { - struct { - unsigned int ADDR_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TMA_HI { - struct { - unsigned int ADDR_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TMA_LO { - struct { - unsigned int ADDR_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TRAPSTS { - struct { - unsigned int EXCP : 9; - unsigned int : 1; - unsigned int SAVECTX__VI : 1; - unsigned int : 5; - unsigned int EXCP_CYCLE : 6; - unsigned int : 7; - unsigned int DP_RATE : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP0 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP1 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP10 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP11 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP2 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP3 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP4 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP5 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP6 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP7 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP8 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_TTMP9 { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_CAM_DATA { - struct { - unsigned int CAM_ADDR : 16; - unsigned int CAM_REMAPADDR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_CAM_INDEX { - struct { - unsigned int CAM_INDEX : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_CHIP_REVISION { - struct { - unsigned int CHIP_REVISION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_CNTL { - struct { - unsigned int READ_TIMEOUT : 10; - unsigned int : 6; - unsigned int PWR_REQUEST_HALT : 1; - unsigned int COMBINE_SYSTEM_MC__CI__VI : 1; - unsigned int REPORT_LAST_RDERR__VI : 1; - unsigned int PWR_GFX3D_REQUEST_HALT__VI : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_DEBUG_CNTL { - struct { - unsigned int SRBM_DEBUG_INDEX : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_DEBUG_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_DEBUG_SNAPSHOT__SI__CI { - struct { - unsigned int MCB_RDY : 1; - unsigned int ROPLL_RDY__CI : 1; - unsigned int SMU_RDY__CI : 1; - unsigned int SAM_RDY__CI : 1; - unsigned int ACP_RDY__CI : 1; - unsigned int GRBM_RDY : 1; - unsigned int DC_RDY : 1; - unsigned int BIF_RDY : 1; - unsigned int XDMA_RDY : 1; - unsigned int UVD_RDY : 1; - unsigned int XSP_RDY : 1; - unsigned int REGBB_RDY : 1; - unsigned int ORB_RDY : 1; - unsigned int MCD7_RDY : 1; - unsigned int MCD6_RDY : 1; - unsigned int MCD5_RDY : 1; - unsigned int MCD4_RDY : 1; - unsigned int MCD3_RDY : 1; - unsigned int MCD2_RDY : 1; - unsigned int MCD1_RDY : 1; - unsigned int MCD0_RDY : 1; - unsigned int MCC7_RDY : 1; - unsigned int MCC6_RDY : 1; - unsigned int MCC5_RDY : 1; - unsigned int MCC4_RDY : 1; - unsigned int MCC3_RDY : 1; - unsigned int MCC2_RDY : 1; - unsigned int MCC1_RDY : 1; - unsigned int MCC0_RDY : 1; - unsigned int VCE_RDY : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_DEBUG_SNAPSHOT__VI { - struct { - unsigned int MCB_RDY : 1; - unsigned int GIONB_RDY : 1; - unsigned int SMU_RDY : 1; - unsigned int SAMMSP_RDY : 1; - unsigned int ACP_RDY : 1; - unsigned int GRBM_RDY : 1; - unsigned int DC_RDY : 1; - unsigned int BIF_RDY : 1; - unsigned int XDMA_RDY : 1; - unsigned int UVD_RDY : 1; - unsigned int VP8_RDY : 1; - unsigned int REGBB_RDY : 1; - unsigned int ODE_RDY : 1; - unsigned int MCD7_RDY : 1; - unsigned int MCD6_RDY : 1; - unsigned int MCD5_RDY : 1; - unsigned int MCD4_RDY : 1; - unsigned int MCD3_RDY : 1; - unsigned int MCD2_RDY : 1; - unsigned int MCD1_RDY : 1; - unsigned int MCD0_RDY : 1; - unsigned int MCC7_RDY : 1; - unsigned int MCC6_RDY : 1; - unsigned int MCC5_RDY : 1; - unsigned int MCC4_RDY : 1; - unsigned int MCC3_RDY : 1; - unsigned int MCC2_RDY : 1; - unsigned int MCC1_RDY : 1; - unsigned int MCC0_RDY : 1; - unsigned int VCE0_RDY : 1; - unsigned int SAMSCP_RDY : 1; - unsigned int ISP_RDY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_DEBUG__CI__VI { - struct { - unsigned int IGNORE_RDY : 1; - unsigned int DISABLE_READ_TIMEOUT : 1; - unsigned int SNAPSHOT_FREE_CNTRS : 1; - unsigned int : 1; - unsigned int SYS_CLOCK_DOMAIN_OVERRIDE : 1; - unsigned int VCE_CLOCK_DOMAIN_OVERRIDE : 1; - unsigned int UVD_CLOCK_DOMAIN_OVERRIDE : 1; - unsigned int SDMA_CLOCK_DOMAIN_OVERRIDE : 1; - unsigned int MC_CLOCK_DOMAIN_OVERRIDE : 1; - unsigned int SAM_CLOCK_DOMAIN_OVERRIDE : 1; - unsigned int ISP_CLOCK_DOMAIN_OVERRIDE__VI : 1; - unsigned int VP8_CLOCK_DOMAIN_OVERRIDE__VI : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_DEBUG__SI { - struct { - unsigned int IGNORE_RDY : 1; - unsigned int DISABLE_READ_TIMEOUT : 1; - unsigned int SNAPSHOT_FREE_CNTRS : 1; - unsigned int : 1; - unsigned int SYS_CLOCK_DOMAIN_OVERRIDE : 1; - unsigned int VCE_CLOCK_DOMAIN_OVERRIDE : 1; - unsigned int UVD_CLOCK_DOMAIN_OVERRIDE : 1; - unsigned int : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_GFX_CNTL__CI__VI { - struct { - unsigned int PIPEID : 2; - unsigned int MEID : 2; - unsigned int VMID : 4; - unsigned int QUEUEID : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_GFX_CNTL__SI { - struct { - unsigned int : 2; - unsigned int : 2; - unsigned int VMID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_INT_ACK { - struct { - unsigned int RDERR_INT_ACK : 1; - unsigned int RAERR_INT_ACK__VI : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_INT_CNTL { - struct { - unsigned int RDERR_INT_MASK : 1; - unsigned int RAERR_INT_MASK__VI : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_INT_STATUS { - struct { - unsigned int RDERR_INT_STAT : 1; - unsigned int RAERR_INT_STAT__VI : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_MC_CLKEN_CNTL__CI__VI { - struct { - unsigned int PREFIX_DELAY_CNT : 4; - unsigned int : 4; - unsigned int POST_DELAY_CNT : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_PERFCOUNTER0_HI { - struct { - unsigned int PERF_COUNT0_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_PERFCOUNTER0_LO { - struct { - unsigned int PERF_COUNT0_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_PERFCOUNTER0_SELECT { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_PERFCOUNTER1_HI { - struct { - unsigned int PERF_COUNT1_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_PERFCOUNTER1_LO { - struct { - unsigned int PERF_COUNT1_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_PERFCOUNTER1_SELECT { - struct { - unsigned int PERF_SEL : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_PERFMON_CNTL { - struct { - unsigned int PERFMON_STATE : 4; - unsigned int : 4; - unsigned int PERFMON_ENABLE_MODE : 2; - unsigned int PERFMON_SAMPLE_ENABLE : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_READ_ERROR__CI { - struct { - unsigned int : 2; - unsigned int READ_ADDRESS : 16; - unsigned int : 2; - unsigned int READ_REQUESTER_VCE : 1; - unsigned int READ_REQUESTER_SDMA1 : 1; - unsigned int READ_REQUESTER_TST : 1; - unsigned int READ_REQUESTER_SAM : 1; - unsigned int READ_REQUESTER_HI : 1; - unsigned int READ_REQUESTER_GRBM : 1; - unsigned int READ_REQUESTER_SMU : 1; - unsigned int READ_REQUESTER_ACP : 1; - unsigned int READ_REQUESTER_SDMA : 1; - unsigned int READ_REQUESTER_UVD : 1; - unsigned int : 1; - unsigned int READ_ERROR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_READ_ERROR__VI { - struct { - unsigned int : 2; - unsigned int READ_ADDRESS : 16; - unsigned int READ_REQUESTER_SDMA3 : 1; - unsigned int READ_REQUESTER_SDMA2 : 1; - unsigned int READ_REQUESTER_VCE0 : 1; - unsigned int READ_REQUESTER_SDMA1 : 1; - unsigned int READ_REQUESTER_TST : 1; - unsigned int READ_REQUESTER_SAMMSP : 1; - unsigned int READ_REQUESTER_HI : 1; - unsigned int READ_REQUESTER_GRBM : 1; - unsigned int READ_REQUESTER_SMU : 1; - unsigned int READ_REQUESTER_SAMSCP : 1; - unsigned int READ_REQUESTER_SDMA : 1; - unsigned int READ_REQUESTER_UVD : 1; - unsigned int : 1; - unsigned int READ_ERROR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_READ_ERROR__SI { - struct { - unsigned int : 2; - unsigned int READ_ADDRESS : 16; - unsigned int : 2; - unsigned int READ_REQUESTER_VCE : 1; - unsigned int : 1; - unsigned int READ_REQUESTER_TST : 1; - unsigned int : 1; - unsigned int READ_REQUESTER_HI : 1; - unsigned int READ_REQUESTER_GRBM : 1; - unsigned int READ_REQUESTER_SMU : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int READ_REQUESTER_UVD : 1; - unsigned int : 1; - unsigned int READ_ERROR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SAM_CLKEN_CNTL__CI__VI { - struct { - unsigned int PREFIX_DELAY_CNT : 4; - unsigned int : 4; - unsigned int POST_DELAY_CNT : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SDMA_CLKEN_CNTL__CI__VI { - struct { - unsigned int PREFIX_DELAY_CNT : 4; - unsigned int : 4; - unsigned int POST_DELAY_CNT : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SOFT_RESET__CI { - struct { - unsigned int : 1; - unsigned int SOFT_RESET_BIF : 1; - unsigned int : 2; - unsigned int SOFT_RESET_ROPLL : 1; - unsigned int SOFT_RESET_DC : 1; - unsigned int SOFT_RESET_SDMA1 : 1; - unsigned int : 1; - unsigned int SOFT_RESET_GRBM : 1; - unsigned int SOFT_RESET_HDP : 1; - unsigned int SOFT_RESET_IH : 1; - unsigned int SOFT_RESET_MC : 1; - unsigned int SOFT_RESET_CHUB : 1; - unsigned int : 1; - unsigned int SOFT_RESET_ROM : 1; - unsigned int SOFT_RESET_SEM : 1; - unsigned int SOFT_RESET_SMU : 1; - unsigned int SOFT_RESET_VMC : 1; - unsigned int SOFT_RESET_UVD : 1; - unsigned int SOFT_RESET_XSP : 1; - unsigned int SOFT_RESET_SDMA : 1; - unsigned int SOFT_RESET_TST : 1; - unsigned int SOFT_RESET_REGBB : 1; - unsigned int SOFT_RESET_ORB : 1; - unsigned int SOFT_RESET_VCE : 1; - unsigned int SOFT_RESET_XDMA : 1; - unsigned int SOFT_RESET_ACP : 1; - unsigned int SOFT_RESET_SAM : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SOFT_RESET__VI { - struct { - unsigned int SOFT_RESET_ATCL2 : 1; - unsigned int SOFT_RESET_BIF : 1; - unsigned int SOFT_RESET_SDMA3 : 1; - unsigned int SOFT_RESET_SDMA2 : 1; - unsigned int SOFT_RESET_GIONB : 1; - unsigned int SOFT_RESET_DC : 1; - unsigned int SOFT_RESET_SDMA1 : 1; - unsigned int : 1; - unsigned int SOFT_RESET_GRBM : 1; - unsigned int SOFT_RESET_HDP : 1; - unsigned int SOFT_RESET_IH : 1; - unsigned int SOFT_RESET_MC : 1; - unsigned int SOFT_RESET_CHUB : 1; - unsigned int SOFT_RESET_ESRAM : 1; - unsigned int SOFT_RESET_ROM : 1; - unsigned int SOFT_RESET_SEM : 1; - unsigned int SOFT_RESET_SMU : 1; - unsigned int SOFT_RESET_VMC : 1; - unsigned int SOFT_RESET_UVD : 1; - unsigned int SOFT_RESET_VP8 : 1; - unsigned int SOFT_RESET_SDMA : 1; - unsigned int SOFT_RESET_TST : 1; - unsigned int SOFT_RESET_REGBB : 1; - unsigned int SOFT_RESET_ODE : 1; - unsigned int SOFT_RESET_VCE0 : 1; - unsigned int SOFT_RESET_XDMA : 1; - unsigned int SOFT_RESET_ACP : 1; - unsigned int SOFT_RESET_SAMMSP : 1; - unsigned int SOFT_RESET_SAMSCP : 1; - unsigned int SOFT_RESET_GRN : 1; - unsigned int SOFT_RESET_ISP : 1; - unsigned int SOFT_RESET_VCE1 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SOFT_RESET__SI { - struct { - unsigned int : 1; - unsigned int SOFT_RESET_BIF : 1; - unsigned int : 3; - unsigned int SOFT_RESET_DC : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SOFT_RESET_GRBM : 1; - unsigned int SOFT_RESET_HDP : 1; - unsigned int SOFT_RESET_IH : 1; - unsigned int SOFT_RESET_MC : 1; - unsigned int : 2; - unsigned int SOFT_RESET_ROM : 1; - unsigned int SOFT_RESET_SEM : 1; - unsigned int : 1; - unsigned int SOFT_RESET_VMC : 1; - unsigned int SOFT_RESET_UVD : 1; - unsigned int SOFT_RESET_XSP : 1; - unsigned int : 1; - unsigned int SOFT_RESET_TST : 1; - unsigned int SOFT_RESET_REGBB : 1; - unsigned int SOFT_RESET_ORB : 1; - unsigned int SOFT_RESET_VCE : 1; - unsigned int SOFT_RESET_XDMA : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_STATUS__SI__CI { - struct { - unsigned int : 1; - unsigned int UVD_RQ_PENDING : 1; - unsigned int SAM_RQ_PENDING__CI : 1; - unsigned int ACP_RQ_PENDING__CI : 1; - unsigned int SMU_RQ_PENDING : 1; - unsigned int GRBM_RQ_PENDING : 1; - unsigned int HI_RQ_PENDING : 1; - unsigned int IO_EXTERN_SIGNAL : 1; - unsigned int VMC_BUSY : 1; - unsigned int MCB_BUSY : 1; - unsigned int MCB_NON_DISPLAY_BUSY : 1; - unsigned int MCC_BUSY : 1; - unsigned int MCD_BUSY : 1; - unsigned int : 1; - unsigned int SEM_BUSY : 1; - unsigned int : 1; - unsigned int ACP_BUSY__CI : 1; - unsigned int IH_BUSY : 1; - unsigned int : 1; - unsigned int UVD_BUSY : 1; - unsigned int SAM_BUSY__CI : 1; - unsigned int : 8; - unsigned int BIF_BUSY : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_STATUS__VI { - struct { - unsigned int : 1; - unsigned int UVD_RQ_PENDING : 1; - unsigned int SAMMSP_RQ_PENDING : 1; - unsigned int ACP_RQ_PENDING : 1; - unsigned int SMU_RQ_PENDING : 1; - unsigned int GRBM_RQ_PENDING : 1; - unsigned int HI_RQ_PENDING : 1; - unsigned int : 1; - unsigned int VMC_BUSY : 1; - unsigned int MCB_BUSY : 1; - unsigned int MCB_NON_DISPLAY_BUSY : 1; - unsigned int MCC_BUSY : 1; - unsigned int MCD_BUSY : 1; - unsigned int VMC1_BUSY : 1; - unsigned int SEM_BUSY : 1; - unsigned int : 1; - unsigned int ACP_BUSY : 1; - unsigned int IH_BUSY : 1; - unsigned int : 1; - unsigned int UVD_BUSY : 1; - unsigned int SAMMSP_BUSY : 1; - unsigned int GCATCL2_BUSY : 1; - unsigned int OSATCL2_BUSY : 1; - unsigned int : 6; - unsigned int BIF_BUSY : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_STATUS2__CI { - struct { - unsigned int SDMA_RQ_PENDING : 1; - unsigned int TST_RQ_PENDING : 1; - unsigned int SDMA1_RQ_PENDING : 1; - unsigned int VCE_RQ_PENDING : 1; - unsigned int XSP_BUSY : 1; - unsigned int SDMA_BUSY : 1; - unsigned int SDMA1_BUSY : 1; - unsigned int VCE_BUSY : 1; - unsigned int XDMA_BUSY : 1; - unsigned int CHUB_BUSY : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_STATUS2__VI { - struct { - unsigned int SDMA_RQ_PENDING : 1; - unsigned int TST_RQ_PENDING : 1; - unsigned int SDMA1_RQ_PENDING : 1; - unsigned int VCE0_RQ_PENDING : 1; - unsigned int VP8_BUSY : 1; - unsigned int SDMA_BUSY : 1; - unsigned int SDMA1_BUSY : 1; - unsigned int VCE0_BUSY : 1; - unsigned int XDMA_BUSY : 1; - unsigned int CHUB_BUSY : 1; - unsigned int SDMA2_BUSY : 1; - unsigned int SDMA3_BUSY : 1; - unsigned int SAMSCP_BUSY : 1; - unsigned int ISP_BUSY : 1; - unsigned int VCE1_BUSY : 1; - unsigned int ODE_BUSY : 1; - unsigned int SDMA2_RQ_PENDING : 1; - unsigned int SDMA3_RQ_PENDING : 1; - unsigned int SAMSCP_RQ_PENDING : 1; - unsigned int ISP_RQ_PENDING : 1; - unsigned int VCE1_RQ_PENDING : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_STATUS2__SI { - struct { - unsigned int : 1; - unsigned int TST_RQ_PENDING : 1; - unsigned int : 1; - unsigned int VCE_RQ_PENDING : 1; - unsigned int XSP_BUSY : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int VCE_BUSY : 1; - unsigned int XDMA_BUSY : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SYS_CLKEN_CNTL { - struct { - unsigned int PREFIX_DELAY_CNT : 4; - unsigned int : 4; - unsigned int POST_DELAY_CNT : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_UVD_CLKEN_CNTL { - struct { - unsigned int PREFIX_DELAY_CNT : 4; - unsigned int : 4; - unsigned int POST_DELAY_CNT : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_VCE_CLKEN_CNTL { - struct { - unsigned int PREFIX_DELAY_CNT : 4; - unsigned int : 4; - unsigned int POST_DELAY_CNT : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union STATE_CHANGE_STATUS__SI__VI { - struct { - unsigned int STATE_CHANGE_STATUS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union STATUS { - struct { - unsigned int : 3; - unsigned int INT_STATUS : 1; - unsigned int CAP_LIST : 1; - unsigned int PCI_66_EN : 1; - unsigned int : 1; - unsigned int FAST_BACK_CAPABLE : 1; - unsigned int MASTER_DATA_PARITY_ERROR : 1; - unsigned int DEVSEL_TIMING : 2; - unsigned int SIGNAL_TARGET_ABORT : 1; - unsigned int RECEIVED_TARGET_ABORT : 1; - unsigned int RECEIVED_MASTER_ABORT : 1; - unsigned int SIGNALED_SYSTEM_ERROR : 1; - unsigned int PARITY_ERROR_DETECTED : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union STREAM_SYNCHRONIZATION__SI { - struct { - unsigned int : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union STREAM_SYNCHRONIZATION__VI { - struct { - unsigned int STREAM_0_SYNCHRONIZATION : 1; - unsigned int STREAM_1_SYNCHRONIZATION : 1; - unsigned int STREAM_2_SYNCHRONIZATION : 1; - unsigned int STREAM_3_SYNCHRONIZATION : 1; - unsigned int STREAM_4_SYNCHRONIZATION : 1; - unsigned int STREAM_5_SYNCHRONIZATION : 1; - unsigned int STREAM_6_SYNCHRONIZATION : 1; - unsigned int STREAM_7_SYNCHRONIZATION : 1; - unsigned int STREAM_8_SYNCHRONIZATION : 1; - unsigned int STREAM_9_SYNCHRONIZATION : 1; - unsigned int STREAM_10_SYNCHRONIZATION : 1; - unsigned int STREAM_11_SYNCHRONIZATION : 1; - unsigned int STREAM_12_SYNCHRONIZATION : 1; - unsigned int STREAM_13_SYNCHRONIZATION : 1; - unsigned int STREAM_14_SYNCHRONIZATION : 1; - unsigned int STREAM_15_SYNCHRONIZATION : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SUB_CLASS { - struct { - unsigned int SUB_CLASS : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SXIFCCG_DEBUG_REG0 { - struct { - unsigned int position_address : 6; - unsigned int point_address : 3; - unsigned int sx_pending_rd_state_var_indx : 3; - unsigned int sx_pending_rd_req_mask : 4; - unsigned int sx_pending_rd_pci : 10; - unsigned int sx_pending_rd_aux_sel : 2; - unsigned int sx_pending_rd_sp_id : 2; - unsigned int sx_pending_rd_aux_inc : 1; - unsigned int sx_pending_rd_advance : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SXIFCCG_DEBUG_REG1 { - struct { - unsigned int available_positions : 7; - unsigned int sx_receive_indx : 3; - unsigned int sx_pending_fifo_contents : 5; - unsigned int statevar_bits_vs_out_misc_vec_ena : 1; - unsigned int statevar_bits_disable_sp : 4; - unsigned int aux_sel : 2; - unsigned int sx_to_pa_empty_1 : 1; - unsigned int sx_to_pa_empty_0 : 1; - unsigned int pasx_req_cnt_1 : 4; - unsigned int pasx_req_cnt_0 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SXIFCCG_DEBUG_REG2 { - struct { - unsigned int param_cache_base : 7; - unsigned int sx_aux : 2; - unsigned int sx_request_indx : 6; - unsigned int req_active_verts_loaded : 1; - unsigned int req_active_verts : 7; - unsigned int vgt_to_ccgen_state_var_indx : 3; - unsigned int vgt_to_ccgen_active_verts : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SXIFCCG_DEBUG_REG3 { - struct { - unsigned int ALWAYS_ZERO : 8; - unsigned int vertex_fifo_entriesavailable : 4; - unsigned int statevar_bits_vs_out_ccdist1_vec_ena : 1; - unsigned int statevar_bits_vs_out_ccdist0_vec_ena : 1; - unsigned int available_positions : 7; - unsigned int current_state : 2; - unsigned int vertex_fifo_empty : 1; - unsigned int vertex_fifo_full : 1; - unsigned int sx0_receive_fifo_empty : 1; - unsigned int sx0_receive_fifo_full : 1; - unsigned int vgt_to_ccgen_fifo_empty : 1; - unsigned int vgt_to_ccgen_fifo_full : 1; - unsigned int ccgen_to_clipcc_fifo_full : 1; - unsigned int sx0_receive_fifo_write : 1; - unsigned int ccgen_to_clipcc_write : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_DEBUG_1__SI__CI { - struct { - unsigned int SX_DB_QUAD_CREDIT : 7; - unsigned int DEBUG_DATA : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_DEBUG_1__VI { - struct { - unsigned int SX_DB_QUAD_CREDIT : 7; - unsigned int : 1; - unsigned int DISABLE_BLEND_OPT_DONT_RD_DST : 1; - unsigned int DISABLE_BLEND_OPT_BYPASS : 1; - unsigned int DISABLE_BLEND_OPT_DISCARD_PIXEL : 1; - unsigned int DISABLE_QUAD_PAIR_OPT : 1; - unsigned int DISABLE_PIX_EN_ZERO_OPT : 1; - unsigned int DEBUG_DATA : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_DEBUG_BUSY { - struct { - unsigned int POS_FREE_OR_VALIDS : 1; - unsigned int POS_REQUESTER_BUSY : 1; - unsigned int PA_SX_BUSY : 1; - unsigned int POS_SCBD_BUSY : 1; - unsigned int POS_BANK3VAL3_BUSY : 1; - unsigned int POS_BANK3VAL2_BUSY : 1; - unsigned int POS_BANK3VAL1_BUSY : 1; - unsigned int POS_BANK3VAL0_BUSY : 1; - unsigned int POS_BANK2VAL3_BUSY : 1; - unsigned int POS_BANK2VAL2_BUSY : 1; - unsigned int POS_BANK2VAL1_BUSY : 1; - unsigned int POS_BANK2VAL0_BUSY : 1; - unsigned int POS_BANK1VAL3_BUSY : 1; - unsigned int POS_BANK1VAL2_BUSY : 1; - unsigned int POS_BANK1VAL1_BUSY : 1; - unsigned int POS_BANK1VAL0_BUSY : 1; - unsigned int POS_BANK0VAL3_BUSY : 1; - unsigned int POS_BANK0VAL2_BUSY : 1; - unsigned int POS_BANK0VAL1_BUSY : 1; - unsigned int POS_BANK0VAL0_BUSY : 1; - unsigned int POS_INMUX_VALID : 1; - unsigned int WRCTRL1_VALIDQ3 : 1; - unsigned int WRCTRL1_VALIDQ2 : 1; - unsigned int WRCTRL1_VALIDQ1 : 1; - unsigned int WRCTRL0_VALIDQ3 : 1; - unsigned int WRCTRL0_VALIDQ2 : 1; - unsigned int WRCTRL0_VALIDQ1 : 1; - unsigned int PCCMD_VALID : 1; - unsigned int VDATA1_VALID : 1; - unsigned int VDATA0_VALID : 1; - unsigned int CMD_BUSYORVAL : 1; - unsigned int ADDR_BUSYORVAL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_DEBUG_BUSY_2__CI__VI { - struct { - unsigned int COL_SCBD_BUSY : 1; - unsigned int COL_REQ3_FREECNT_NE0 : 1; - unsigned int COL_REQ3_IDLE : 1; - unsigned int COL_REQ3_BUSY : 1; - unsigned int COL_REQ2_FREECNT_NE0 : 1; - unsigned int COL_REQ2_IDLE : 1; - unsigned int COL_REQ2_BUSY : 1; - unsigned int COL_REQ1_FREECNT_NE0 : 1; - unsigned int COL_REQ1_IDLE : 1; - unsigned int COL_REQ1_BUSY : 1; - unsigned int COL_REQ0_FREECNT_NE0 : 1; - unsigned int COL_REQ0_IDLE : 1; - unsigned int COL_REQ0_BUSY : 1; - unsigned int COL_DBIF3_SENDFREE_BUSY : 1; - unsigned int COL_DBIF3_FIFO_BUSY : 1; - unsigned int COL_DBIF3_READ_VALID : 1; - unsigned int COL_DBIF2_SENDFREE_BUSY : 1; - unsigned int COL_DBIF2_FIFO_BUSY : 1; - unsigned int COL_DBIF2_READ_VALID : 1; - unsigned int COL_DBIF1_SENDFREE_BUSY : 1; - unsigned int COL_DBIF1_FIFO_BUSY : 1; - unsigned int COL_DBIF1_READ_VALID : 1; - unsigned int COL_DBIF0_SENDFREE_BUSY : 1; - unsigned int COL_DBIF0_FIFO_BUSY : 1; - unsigned int COL_DBIF0_READ_VALID : 1; - unsigned int COL_BUFF3_BANK3_VAL3_BUSY : 1; - unsigned int COL_BUFF3_BANK3_VAL2_BUSY : 1; - unsigned int COL_BUFF3_BANK3_VAL1_BUSY : 1; - unsigned int COL_BUFF3_BANK3_VAL0_BUSY : 1; - unsigned int COL_BUFF3_BANK2_VAL3_BUSY : 1; - unsigned int COL_BUFF3_BANK2_VAL2_BUSY : 1; - unsigned int COL_BUFF3_BANK2_VAL1_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_DEBUG_BUSY_2__SI { - struct { - unsigned int COL_SCBD_BUSY : 1; - unsigned int : 6; - unsigned int COL_REQ1_FREECNT_NE0 : 1; - unsigned int COL_REQ1_IDLE : 1; - unsigned int COL_REQ1_BUSY : 1; - unsigned int COL_REQ0_FREECNT_NE0 : 1; - unsigned int COL_REQ0_IDLE : 1; - unsigned int COL_REQ0_BUSY : 1; - unsigned int : 6; - unsigned int COL_DBIF1_SENDFREE_BUSY : 1; - unsigned int COL_DBIF1_FIFO_BUSY : 1; - unsigned int COL_DBIF1_READ_VALID : 1; - unsigned int COL_DBIF0_SENDFREE_BUSY : 1; - unsigned int COL_DBIF0_FIFO_BUSY : 1; - unsigned int COL_DBIF0_READ_VALID : 1; - unsigned int COL_BUFF3_BANK3_VAL3_BUSY : 1; - unsigned int COL_BUFF3_BANK3_VAL2_BUSY : 1; - unsigned int COL_BUFF3_BANK3_VAL1_BUSY : 1; - unsigned int COL_BUFF3_BANK3_VAL0_BUSY : 1; - unsigned int COL_BUFF3_BANK2_VAL3_BUSY : 1; - unsigned int COL_BUFF3_BANK2_VAL2_BUSY : 1; - unsigned int COL_BUFF3_BANK2_VAL1_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_DEBUG_BUSY_3 { - struct { - unsigned int COL_BUFF3_BANK2_VAL0_BUSY : 1; - unsigned int COL_BUFF3_BANK1_VAL3_BUSY : 1; - unsigned int COL_BUFF3_BANK1_VAL2_BUSY : 1; - unsigned int COL_BUFF3_BANK1_VAL1_BUSY : 1; - unsigned int COL_BUFF3_BANK1_VAL0_BUSY : 1; - unsigned int COL_BUFF3_BANK0_VAL3_BUSY : 1; - unsigned int COL_BUFF3_BANK0_VAL2_BUSY : 1; - unsigned int COL_BUFF3_BANK0_VAL1_BUSY : 1; - unsigned int COL_BUFF3_BANK0_VAL0_BUSY : 1; - unsigned int COL_BUFF2_BANK3_VAL3_BUSY : 1; - unsigned int COL_BUFF2_BANK3_VAL2_BUSY : 1; - unsigned int COL_BUFF2_BANK3_VAL1_BUSY : 1; - unsigned int COL_BUFF2_BANK3_VAL0_BUSY : 1; - unsigned int COL_BUFF2_BANK2_VAL3_BUSY : 1; - unsigned int COL_BUFF2_BANK2_VAL2_BUSY : 1; - unsigned int COL_BUFF2_BANK2_VAL1_BUSY : 1; - unsigned int COL_BUFF2_BANK2_VAL0_BUSY : 1; - unsigned int COL_BUFF2_BANK1_VAL3_BUSY : 1; - unsigned int COL_BUFF2_BANK1_VAL2_BUSY : 1; - unsigned int COL_BUFF2_BANK1_VAL1_BUSY : 1; - unsigned int COL_BUFF2_BANK1_VAL0_BUSY : 1; - unsigned int COL_BUFF2_BANK0_VAL3_BUSY : 1; - unsigned int COL_BUFF2_BANK0_VAL2_BUSY : 1; - unsigned int COL_BUFF2_BANK0_VAL1_BUSY : 1; - unsigned int COL_BUFF2_BANK0_VAL0_BUSY : 1; - unsigned int COL_BUFF1_BANK3_VAL3_BUSY : 1; - unsigned int COL_BUFF1_BANK3_VAL2_BUSY : 1; - unsigned int COL_BUFF1_BANK3_VAL1_BUSY : 1; - unsigned int COL_BUFF1_BANK3_VAL0_BUSY : 1; - unsigned int COL_BUFF1_BANK2_VAL3_BUSY : 1; - unsigned int COL_BUFF1_BANK2_VAL2_BUSY : 1; - unsigned int COL_BUFF1_BANK2_VAL1_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_DEBUG_BUSY_4 { - struct { - unsigned int COL_BUFF1_BANK2_VAL0_BUSY : 1; - unsigned int COL_BUFF1_BANK1_VAL3_BUSY : 1; - unsigned int COL_BUFF1_BANK1_VAL2_BUSY : 1; - unsigned int COL_BUFF1_BANK1_VAL1_BUSY : 1; - unsigned int COL_BUFF1_BANK1_VAL0_BUSY : 1; - unsigned int COL_BUFF1_BANK0_VAL3_BUSY : 1; - unsigned int COL_BUFF1_BANK0_VAL2_BUSY : 1; - unsigned int COL_BUFF1_BANK0_VAL1_BUSY : 1; - unsigned int COL_BUFF1_BANK0_VAL0_BUSY : 1; - unsigned int COL_BUFF0_BANK3_VAL3_BUSY : 1; - unsigned int COL_BUFF0_BANK3_VAL2_BUSY : 1; - unsigned int COL_BUFF0_BANK3_VAL1_BUSY : 1; - unsigned int COL_BUFF0_BANK3_VAL0_BUSY : 1; - unsigned int COL_BUFF0_BANK2_VAL3_BUSY : 1; - unsigned int COL_BUFF0_BANK2_VAL2_BUSY : 1; - unsigned int COL_BUFF0_BANK2_VAL1_BUSY : 1; - unsigned int COL_BUFF0_BANK2_VAL0_BUSY : 1; - unsigned int COL_BUFF0_BANK1_VAL3_BUSY : 1; - unsigned int COL_BUFF0_BANK1_VAL2_BUSY : 1; - unsigned int COL_BUFF0_BANK1_VAL1_BUSY : 1; - unsigned int COL_BUFF0_BANK1_VAL0_BUSY : 1; - unsigned int COL_BUFF0_BANK0_VAL3_BUSY : 1; - unsigned int COL_BUFF0_BANK0_VAL2_BUSY : 1; - unsigned int COL_BUFF0_BANK0_VAL1_BUSY : 1; - unsigned int COL_BUFF0_BANK0_VAL0_BUSY : 1; - unsigned int RESERVED : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER0_SELECT { - struct { - unsigned int PERFCOUNTER_SELECT : 10; - unsigned int PERFCOUNTER_SELECT1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERFCOUNTER_SELECT2 : 10; - unsigned int PERFCOUNTER_SELECT3 : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER1_SELECT { - struct { - unsigned int PERFCOUNTER_SELECT : 10; - unsigned int PERFCOUNTER_SELECT1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER1_SELECT1__CI__VI { - struct { - unsigned int PERFCOUNTER_SELECT2 : 10; - unsigned int PERFCOUNTER_SELECT3 : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER2_SELECT { - struct { - unsigned int PERFCOUNTER_SELECT : 10; - unsigned int PERFCOUNTER_SELECT1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PERFCOUNTER3_SELECT { - struct { - unsigned int PERFCOUNTER_SELECT : 10; - unsigned int PERFCOUNTER_SELECT1__CI__VI : 10; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TARGET_AND_CURRENT_PROFILE_INDEX_1 { - struct { - unsigned int CURR_VDDCI_INDEX : 4; - unsigned int TARG_VDDCI_INDEX : 4; - unsigned int CURR_MVDD_INDEX : 4; - unsigned int TARG_MVDD_INDEX : 4; - unsigned int CURR_VDDC_INDEX : 4; - unsigned int TARG_VDDC_INDEX : 4; - unsigned int CURR_PCIE_INDEX : 4; - unsigned int TARG_PCIE_INDEX : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TARGET_AND_CURRENT_PROFILE_INDEX__CI__VI { - struct { - unsigned int TARGET_STATE : 4; - unsigned int CURRENT_STATE : 4; - unsigned int CURR_MCLK_INDEX : 4; - unsigned int TARG_MCLK_INDEX : 4; - unsigned int CURR_SCLK_INDEX : 5; - unsigned int TARG_SCLK_INDEX : 5; - unsigned int CURR_LCLK_INDEX : 3; - unsigned int TARG_LCLK_INDEX : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TARGET_AND_CURRENT_PROFILE_INDEX__SI { - struct { - unsigned int TARGET_STATE : 4; - unsigned int CURRENT_STATE : 4; - unsigned int CURR_MCLK_INDEX : 4; - unsigned int TARG_MCLK_INDEX : 4; - unsigned int CURR_SCLK_INDEX : 5; - unsigned int TARG_SCLK_INDEX : 5; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_BC_BASE_ADDR { - struct { - unsigned int ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_BC_BASE_ADDR_HI__CI__VI { - struct { - unsigned int ADDRESS : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_CGTT_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_CNTL { - struct { - unsigned int FX_XNACK_CREDIT__VI : 7; - unsigned int : 2; - unsigned int SQ_XNACK_CREDIT__VI : 4; - unsigned int TC_DATA_CREDIT : 3; - unsigned int ALIGNER_CREDIT : 5; - unsigned int : 1; - unsigned int TD_FIFO_CREDIT : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_CNTL_AUX { - struct { - unsigned int SCOAL_DSWIZZLE_N__VI : 1; - unsigned int RESERVED__VI : 3; - unsigned int D16_PACK_DISABLE__VI : 1; - unsigned int : 11; - unsigned int ANISO_WEIGHT_MODE : 1; - unsigned int ANISO_RATIO_LUT__VI : 1; - unsigned int ANISO_TAP__VI : 1; - unsigned int ANISO_MIP_ADJ_MODE__VI : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_CS_BC_BASE_ADDR { - struct { - unsigned int ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_CS_BC_BASE_ADDR_HI__CI__VI { - struct { - unsigned int ADDRESS : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_DEBUG_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_DEBUG_INDEX { - struct { - unsigned int INDEX : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_PERFCOUNTER0_SELECT { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 2; - unsigned int PERF_SEL1__CI__VI : 8; - unsigned int : 2; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int PERF_MODE1__CI__VI : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 8; - unsigned int : 2; - unsigned int PERF_SEL3 : 8; - unsigned int : 6; - unsigned int PERF_MODE3 : 4; - unsigned int PERF_MODE2 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_PERFCOUNTER1_SELECT { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 2; - unsigned int PERF_SEL1__CI__VI : 8; - unsigned int : 2; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int PERF_MODE1__CI__VI : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_RESERVED_010C__CI__VI { - struct { - unsigned int Unused : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_SCRATCH { - struct { - unsigned int SCRATCH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TA_STATUS { - struct { - unsigned int : 12; - unsigned int FG_PFIFO_EMPTYB : 1; - unsigned int FG_LFIFO_EMPTYB : 1; - unsigned int FG_SFIFO_EMPTYB : 1; - unsigned int : 1; - unsigned int FL_PFIFO_EMPTYB : 1; - unsigned int FL_LFIFO_EMPTYB : 1; - unsigned int FL_SFIFO_EMPTYB : 1; - unsigned int : 1; - unsigned int FA_PFIFO_EMPTYB : 1; - unsigned int FA_LFIFO_EMPTYB : 1; - unsigned int FA_SFIFO_EMPTYB : 1; - unsigned int : 1; - unsigned int IN_BUSY : 1; - unsigned int FG_BUSY : 1; - unsigned int LA_BUSY : 1; - unsigned int FL_BUSY : 1; - unsigned int TA_BUSY : 1; - unsigned int FA_BUSY : 1; - unsigned int AL_BUSY : 1; - unsigned int BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_CGTT_SCLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_CTRL { - struct { - unsigned int HOLE_TIMEOUT : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE2 : 4; - unsigned int PERF_MODE3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER0_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1 : 10; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER0_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER1_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE2 : 4; - unsigned int PERF_MODE3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER1_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1 : 10; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER1_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER2_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 10; - unsigned int CNTR_MODE : 4; - unsigned int : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER2_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER3_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 10; - unsigned int CNTR_MODE : 4; - unsigned int : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCA_PERFCOUNTER3_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_CGTT_SCLK_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_CTRL { - struct { - unsigned int CACHE_SIZE : 2; - unsigned int RATE : 2; - unsigned int WRITEBACK_MARGIN : 4; - unsigned int METADATA_LATENCY_FIFO_SIZE__VI : 4; - unsigned int SRC_FIFO_SIZE : 4; - unsigned int LATENCY_FIFO_SIZE : 4; - unsigned int WB_OR_INV_ALL_VMIDS__CI__VI : 1; - unsigned int : 3; - unsigned int MDC_SIZE__VI : 2; - unsigned int MDC_SECTOR_SIZE__VI : 2; - unsigned int MDC_SIDEBAND_FIFO_SIZE__VI : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_EDC_COUNTER__SI__CI { - struct { - unsigned int SEC_COUNT : 4; - unsigned int : 12; - unsigned int DED_COUNT : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE2 : 4; - unsigned int PERF_MODE3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER0_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1 : 10; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER0_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER1_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE2 : 4; - unsigned int PERF_MODE3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER1_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1 : 10; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER1_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER2_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 10; - unsigned int CNTR_MODE : 4; - unsigned int : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER2_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER3_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 10; - unsigned int CNTR_MODE : 4; - unsigned int : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_PERFCOUNTER3_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_REDUNDANCY__CI__VI { - struct { - unsigned int MC_SEL0 : 1; - unsigned int MC_SEL1 : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCI_CNTL_1 { - struct { - unsigned int WBINVL1_NUM_CYCLES : 16; - unsigned int REQ_FIFO_DEPTH : 8; - unsigned int WDATA_RAM_DEPTH : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCI_CNTL_2 { - struct { - unsigned int L1_INVAL_ON_WBINVL2 : 1; - unsigned int TCA_MAX_CREDIT : 8; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCI_STATUS { - struct { - unsigned int TCI_BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_ADDR_CONFIG { - struct { - unsigned int NUM_TCC_BANKS : 4; - unsigned int NUM_BANKS : 2; - unsigned int COLHI_WIDTH : 3; - unsigned int RB_SPLIT_COLHI : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_BUFFER_ADDR_HASH_CNTL { - struct { - unsigned int CHANNEL_BITS : 3; - unsigned int : 5; - unsigned int BANK_BITS : 3; - unsigned int : 5; - unsigned int CHANNEL_XOR_COUNT : 3; - unsigned int : 5; - unsigned int BANK_XOR_COUNT : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_CHAN_STEER_HI { - struct { - unsigned int CHAN8 : 4; - unsigned int CHAN9 : 4; - unsigned int CHANA : 4; - unsigned int CHANB : 4; - unsigned int CHANC : 4; - unsigned int CHAND : 4; - unsigned int CHANE : 4; - unsigned int CHANF : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_CHAN_STEER_LO { - struct { - unsigned int CHAN0 : 4; - unsigned int CHAN1 : 4; - unsigned int CHAN2 : 4; - unsigned int CHAN3 : 4; - unsigned int CHAN4 : 4; - unsigned int CHAN5 : 4; - unsigned int CHAN6 : 4; - unsigned int CHAN7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_CNTL { - struct { - unsigned int FORCE_HIT : 1; - unsigned int FORCE_MISS : 1; - unsigned int L1_SIZE : 2; - unsigned int FLAT_BUF_HASH_ENABLE__CI__VI : 1; - unsigned int FLAT_BUF_CACHE_SWIZZLE__CI__VI : 1; - unsigned int : 9; - unsigned int FORCE_EOW_TOTAL_CNT : 6; - unsigned int : 1; - unsigned int FORCE_EOW_TAGRAM_CNT : 6; - unsigned int DISABLE_Z_MAP : 1; - unsigned int INV_ALL_VMIDS__CI__VI : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_CREDIT { - struct { - unsigned int LFIFO_CREDIT : 10; - unsigned int : 6; - unsigned int REQ_FIFO_CREDIT : 7; - unsigned int : 6; - unsigned int TD_CREDIT : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_EDC_COUNTER__SI__CI { - struct { - unsigned int SEC_COUNT : 4; - unsigned int : 12; - unsigned int DED_COUNT : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_INVALIDATE { - struct { - unsigned int START : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE3 : 4; - unsigned int PERF_MODE2 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER0_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1 : 10; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER0_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER1_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE3 : 4; - unsigned int PERF_MODE2 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER1_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1 : 10; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER1_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER2_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 10; - unsigned int CNTR_MODE : 4; - unsigned int : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER2_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER3_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 10; - unsigned int CNTR_MODE : 4; - unsigned int : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_PERFCOUNTER3_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_STATUS { - struct { - unsigned int TCP_BUSY : 1; - unsigned int INPUT_BUSY__VI : 1; - unsigned int ADRS_BUSY__VI : 1; - unsigned int TAGRAMS_BUSY__VI : 1; - unsigned int CNTRL_BUSY__VI : 1; - unsigned int LFIFO_BUSY__VI : 1; - unsigned int READ_BUSY__VI : 1; - unsigned int FORMAT_BUSY__VI : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH0_ADDR_H__CI__VI { - struct { - unsigned int ADDR : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH0_ADDR_L__CI__VI { - struct { - unsigned int : 6; - unsigned int ADDR : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH0_CNTL__CI__VI { - struct { - unsigned int MASK : 24; - unsigned int VMID : 4; - unsigned int ATC__VI : 1; - unsigned int MODE : 2; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH1_ADDR_H__CI__VI { - struct { - unsigned int ADDR : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH1_ADDR_L__CI__VI { - struct { - unsigned int : 6; - unsigned int ADDR : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH1_CNTL__CI__VI { - struct { - unsigned int MASK : 24; - unsigned int VMID : 4; - unsigned int ATC__VI : 1; - unsigned int MODE : 2; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH2_ADDR_H__CI__VI { - struct { - unsigned int ADDR : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH2_ADDR_L__CI__VI { - struct { - unsigned int : 6; - unsigned int ADDR : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH2_CNTL__CI__VI { - struct { - unsigned int MASK : 24; - unsigned int VMID : 4; - unsigned int ATC__VI : 1; - unsigned int MODE : 2; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH3_ADDR_H__CI__VI { - struct { - unsigned int ADDR : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH3_ADDR_L__CI__VI { - struct { - unsigned int : 6; - unsigned int ADDR : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_WATCH3_CNTL__CI__VI { - struct { - unsigned int MASK : 24; - unsigned int VMID : 4; - unsigned int ATC__VI : 1; - unsigned int MODE : 2; - unsigned int VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_CGTT_SCLK_CTRL__CI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_CTRL__CI { - struct { - unsigned int RATE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER0_HI__CI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER0_LO__CI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER0_SELECT1__CI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE2 : 4; - unsigned int PERF_MODE3 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER0_SELECT__CI { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1 : 10; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER1_HI__CI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER1_LO__CI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER1_SELECT__CI { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 10; - unsigned int CNTR_MODE : 4; - unsigned int : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER2_HI__CI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER2_LO__CI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER2_SELECT__CI { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 10; - unsigned int CNTR_MODE : 4; - unsigned int : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER3_HI__CI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER3_LO__CI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCS_PERFCOUNTER3_SELECT__CI { - struct { - unsigned int PERF_SEL : 10; - unsigned int : 10; - unsigned int CNTR_MODE : 4; - unsigned int : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TC_CFG_L1_LOAD_POLICY0__CI__VI { - struct { - unsigned int POLICY_0 : 2; - unsigned int POLICY_1 : 2; - unsigned int POLICY_2 : 2; - unsigned int POLICY_3 : 2; - unsigned int POLICY_4 : 2; - unsigned int POLICY_5 : 2; - unsigned int POLICY_6 : 2; - unsigned int POLICY_7 : 2; - unsigned int POLICY_8 : 2; - unsigned int POLICY_9 : 2; - unsigned int POLICY_10 : 2; - unsigned int POLICY_11 : 2; - unsigned int POLICY_12 : 2; - unsigned int POLICY_13 : 2; - unsigned int POLICY_14 : 2; - unsigned int POLICY_15 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TC_CFG_L1_LOAD_POLICY1__CI__VI { - struct { - unsigned int POLICY_16 : 2; - unsigned int POLICY_17 : 2; - unsigned int POLICY_18 : 2; - unsigned int POLICY_19 : 2; - unsigned int POLICY_20 : 2; - unsigned int POLICY_21 : 2; - unsigned int POLICY_22 : 2; - unsigned int POLICY_23 : 2; - unsigned int POLICY_24 : 2; - unsigned int POLICY_25 : 2; - unsigned int POLICY_26 : 2; - unsigned int POLICY_27 : 2; - unsigned int POLICY_28 : 2; - unsigned int POLICY_29 : 2; - unsigned int POLICY_30 : 2; - unsigned int POLICY_31 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TC_CFG_L1_STORE_POLICY__CI__VI { - struct { - unsigned int POLICY_0 : 1; - unsigned int POLICY_1 : 1; - unsigned int POLICY_2 : 1; - unsigned int POLICY_3 : 1; - unsigned int POLICY_4 : 1; - unsigned int POLICY_5 : 1; - unsigned int POLICY_6 : 1; - unsigned int POLICY_7 : 1; - unsigned int POLICY_8 : 1; - unsigned int POLICY_9 : 1; - unsigned int POLICY_10 : 1; - unsigned int POLICY_11 : 1; - unsigned int POLICY_12 : 1; - unsigned int POLICY_13 : 1; - unsigned int POLICY_14 : 1; - unsigned int POLICY_15 : 1; - unsigned int POLICY_16 : 1; - unsigned int POLICY_17 : 1; - unsigned int POLICY_18 : 1; - unsigned int POLICY_19 : 1; - unsigned int POLICY_20 : 1; - unsigned int POLICY_21 : 1; - unsigned int POLICY_22 : 1; - unsigned int POLICY_23 : 1; - unsigned int POLICY_24 : 1; - unsigned int POLICY_25 : 1; - unsigned int POLICY_26 : 1; - unsigned int POLICY_27 : 1; - unsigned int POLICY_28 : 1; - unsigned int POLICY_29 : 1; - unsigned int POLICY_30 : 1; - unsigned int POLICY_31 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TC_CFG_L1_VOLATILE__CI__VI { - struct { - unsigned int VOL : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TC_CFG_L2_ATOMIC_POLICY__CI__VI { - struct { - unsigned int POLICY_0 : 2; - unsigned int POLICY_1 : 2; - unsigned int POLICY_2 : 2; - unsigned int POLICY_3 : 2; - unsigned int POLICY_4 : 2; - unsigned int POLICY_5 : 2; - unsigned int POLICY_6 : 2; - unsigned int POLICY_7 : 2; - unsigned int POLICY_8 : 2; - unsigned int POLICY_9 : 2; - unsigned int POLICY_10 : 2; - unsigned int POLICY_11 : 2; - unsigned int POLICY_12 : 2; - unsigned int POLICY_13 : 2; - unsigned int POLICY_14 : 2; - unsigned int POLICY_15 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TC_CFG_L2_LOAD_POLICY0__CI__VI { - struct { - unsigned int POLICY_0 : 2; - unsigned int POLICY_1 : 2; - unsigned int POLICY_2 : 2; - unsigned int POLICY_3 : 2; - unsigned int POLICY_4 : 2; - unsigned int POLICY_5 : 2; - unsigned int POLICY_6 : 2; - unsigned int POLICY_7 : 2; - unsigned int POLICY_8 : 2; - unsigned int POLICY_9 : 2; - unsigned int POLICY_10 : 2; - unsigned int POLICY_11 : 2; - unsigned int POLICY_12 : 2; - unsigned int POLICY_13 : 2; - unsigned int POLICY_14 : 2; - unsigned int POLICY_15 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TC_CFG_L2_LOAD_POLICY1__CI__VI { - struct { - unsigned int POLICY_16 : 2; - unsigned int POLICY_17 : 2; - unsigned int POLICY_18 : 2; - unsigned int POLICY_19 : 2; - unsigned int POLICY_20 : 2; - unsigned int POLICY_21 : 2; - unsigned int POLICY_22 : 2; - unsigned int POLICY_23 : 2; - unsigned int POLICY_24 : 2; - unsigned int POLICY_25 : 2; - unsigned int POLICY_26 : 2; - unsigned int POLICY_27 : 2; - unsigned int POLICY_28 : 2; - unsigned int POLICY_29 : 2; - unsigned int POLICY_30 : 2; - unsigned int POLICY_31 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TC_CFG_L2_STORE_POLICY0__CI__VI { - struct { - unsigned int POLICY_0 : 2; - unsigned int POLICY_1 : 2; - unsigned int POLICY_2 : 2; - unsigned int POLICY_3 : 2; - unsigned int POLICY_4 : 2; - unsigned int POLICY_5 : 2; - unsigned int POLICY_6 : 2; - unsigned int POLICY_7 : 2; - unsigned int POLICY_8 : 2; - unsigned int POLICY_9 : 2; - unsigned int POLICY_10 : 2; - unsigned int POLICY_11 : 2; - unsigned int POLICY_12 : 2; - unsigned int POLICY_13 : 2; - unsigned int POLICY_14 : 2; - unsigned int POLICY_15 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TC_CFG_L2_STORE_POLICY1__CI__VI { - struct { - unsigned int POLICY_16 : 2; - unsigned int POLICY_17 : 2; - unsigned int POLICY_18 : 2; - unsigned int POLICY_19 : 2; - unsigned int POLICY_20 : 2; - unsigned int POLICY_21 : 2; - unsigned int POLICY_22 : 2; - unsigned int POLICY_23 : 2; - unsigned int POLICY_24 : 2; - unsigned int POLICY_25 : 2; - unsigned int POLICY_26 : 2; - unsigned int POLICY_27 : 2; - unsigned int POLICY_28 : 2; - unsigned int POLICY_29 : 2; - unsigned int POLICY_30 : 2; - unsigned int POLICY_31 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TC_CFG_L2_VOLATILE__CI__VI { - struct { - unsigned int VOL : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_CGTT_CTRL { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 12; - unsigned int SOFT_OVERRIDE7 : 1; - unsigned int SOFT_OVERRIDE6 : 1; - unsigned int SOFT_OVERRIDE5 : 1; - unsigned int SOFT_OVERRIDE4 : 1; - unsigned int SOFT_OVERRIDE3 : 1; - unsigned int SOFT_OVERRIDE2 : 1; - unsigned int SOFT_OVERRIDE1 : 1; - unsigned int SOFT_OVERRIDE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_CNTL { - struct { - unsigned int SYNC_PHASE_SH : 2; - unsigned int : 2; - unsigned int SYNC_PHASE_VC_SMX : 2; - unsigned int : 2; - unsigned int PAD_STALL_EN : 1; - unsigned int EXTEND_LDS_STALL : 2; - unsigned int LDS_STALL_PHASE_ADJUST : 2; - unsigned int : 2; - unsigned int PRECISION_COMPATIBILITY__CI__VI : 1; - unsigned int GATHER4_FLOAT_MODE : 1; - unsigned int : 1; - unsigned int LD_FLOAT_MODE : 1; - unsigned int GATHER4_DX9_MODE : 1; - unsigned int DISABLE_POWER_THROTTLE__CI__VI : 1; - unsigned int ENABLE_ROUND_TO_ZERO__VI : 1; - unsigned int DISABLE_D16_PACKING__VI : 1; - unsigned int DISABLE_2BIT_SIGNED_FORMAT__VI : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_DEBUG_DATA__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_DEBUG_DATA__SI { - struct { - unsigned int DATA : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_DEBUG_INDEX { - struct { - unsigned int INDEX : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_PERFCOUNTER0_SELECT { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 2; - unsigned int PERF_SEL1__CI__VI : 8; - unsigned int : 2; - unsigned int CNTR_MODE__CI__VI : 4; - unsigned int PERF_MODE1__CI__VI : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 8; - unsigned int : 2; - unsigned int PERF_SEL3 : 8; - unsigned int : 6; - unsigned int PERF_MODE3 : 4; - unsigned int PERF_MODE2 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_PERFCOUNTER1_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_PERFCOUNTER1_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_PERFCOUNTER1_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 2; - unsigned int PERF_SEL1 : 8; - unsigned int : 2; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_SCRATCH { - struct { - unsigned int SCRATCH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_STATUS { - struct { - unsigned int : 31; - unsigned int BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_CLK_CNTL { - struct { - unsigned int CMON_CLK_SEL : 8; - unsigned int TMON_CLK_SEL : 8; - unsigned int CTF_CLK_SHUTOFF_EN__VI : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_DEBUG { - struct { - unsigned int DEBUG_RDI : 5; - unsigned int DEBUG_Z : 11; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_INT_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL0_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL10_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL11_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL12_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL13_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL14_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL15_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL1_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL2_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL3_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL4_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL5_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL6_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL7_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL8_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIL9_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR0_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR10_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR11_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR12_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR13_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR14_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR15_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR1_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR2_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR3_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR4_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR5_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR6_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR7_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR8_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_RDIR9_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_DEBUG { - struct { - unsigned int DEBUG_RDI : 5; - unsigned int DEBUG_Z : 11; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_INT_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL0_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL10_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL11_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL12_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL13_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL14_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL15_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL1_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL2_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL3_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL4_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL5_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL6_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL7_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL8_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIL9_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR0_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR10_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR11_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR12_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR13_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR14_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR15_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR1_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR2_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR3_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR4_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR5_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR6_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR7_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR8_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_RDIR9_DATA { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TMDS_CNTL__SI__VI { - struct { - unsigned int TMDS_SYNC_PHASE : 1; - unsigned int : 3; - unsigned int TMDS_PIXEL_ENCODING : 1; - unsigned int : 3; - unsigned int TMDS_COLOR_FORMAT : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TMDS_CONTROL0_FEEDBACK__SI__VI { - struct { - unsigned int TMDS_CONTROL0_FEEDBACK_SELECT : 2; - unsigned int : 6; - unsigned int TMDS_CONTROL0_FEEDBACK_DELAY : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TMDS_CONTROL_CHAR__SI__VI { - struct { - unsigned int TMDS_CONTROL_CHAR0_OUT_EN : 1; - unsigned int TMDS_CONTROL_CHAR1_OUT_EN : 1; - unsigned int TMDS_CONTROL_CHAR2_OUT_EN : 1; - unsigned int TMDS_CONTROL_CHAR3_OUT_EN : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TMDS_CTL0_1_GEN_CNTL__SI__VI { - struct { - unsigned int TMDS_CTL0_DATA_SEL : 4; - unsigned int TMDS_CTL0_DATA_DELAY : 3; - unsigned int TMDS_CTL0_DATA_INVERT : 1; - unsigned int TMDS_CTL0_DATA_MODULATION : 2; - unsigned int TMDS_CTL0_USE_FEEDBACK_PATH : 1; - unsigned int TMDS_CTL0_FB_SYNC_CONT : 1; - unsigned int TMDS_CTL0_PATTERN_OUT_EN : 1; - unsigned int : 3; - unsigned int TMDS_CTL1_DATA_SEL : 4; - unsigned int TMDS_CTL1_DATA_DELAY : 3; - unsigned int TMDS_CTL1_DATA_INVERT : 1; - unsigned int TMDS_CTL1_DATA_MODULATION : 2; - unsigned int TMDS_CTL1_USE_FEEDBACK_PATH : 1; - unsigned int TMDS_CTL1_FB_SYNC_CONT : 1; - unsigned int TMDS_CTL1_PATTERN_OUT_EN : 1; - unsigned int : 2; - unsigned int TMDS_2BIT_COUNTER_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TMDS_CTL2_3_GEN_CNTL__SI__VI { - struct { - unsigned int TMDS_CTL2_DATA_SEL : 4; - unsigned int TMDS_CTL2_DATA_DELAY : 3; - unsigned int TMDS_CTL2_DATA_INVERT : 1; - unsigned int TMDS_CTL2_DATA_MODULATION : 2; - unsigned int TMDS_CTL2_USE_FEEDBACK_PATH : 1; - unsigned int TMDS_CTL2_FB_SYNC_CONT : 1; - unsigned int TMDS_CTL2_PATTERN_OUT_EN : 1; - unsigned int : 3; - unsigned int TMDS_CTL3_DATA_SEL : 4; - unsigned int TMDS_CTL3_DATA_DELAY : 3; - unsigned int TMDS_CTL3_DATA_INVERT : 1; - unsigned int TMDS_CTL3_DATA_MODULATION : 2; - unsigned int TMDS_CTL3_USE_FEEDBACK_PATH : 1; - unsigned int TMDS_CTL3_FB_SYNC_CONT : 1; - unsigned int TMDS_CTL3_PATTERN_OUT_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TMDS_CTL_BITS__SI__VI { - struct { - unsigned int TMDS_CTL0 : 1; - unsigned int : 7; - unsigned int TMDS_CTL1 : 1; - unsigned int : 7; - unsigned int TMDS_CTL2 : 1; - unsigned int : 7; - unsigned int TMDS_CTL3 : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TMDS_DCBALANCER_CONTROL__SI__VI { - struct { - unsigned int TMDS_DCBALANCER_EN : 1; - unsigned int : 3; - unsigned int TMDS_SYNC_DCBAL_EN : 3; - unsigned int : 1; - unsigned int TMDS_DCBALANCER_TEST_EN : 1; - unsigned int : 7; - unsigned int TMDS_DCBALANCER_TEST_IN : 4; - unsigned int : 4; - unsigned int TMDS_DCBALANCER_FORCE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TMDS_DEBUG__SI__VI { - struct { - unsigned int TMDS_DEBUG_EN : 1; - unsigned int : 7; - unsigned int TMDS_DEBUG_HSYNC : 1; - unsigned int TMDS_DEBUG_HSYNC_EN : 1; - unsigned int : 6; - unsigned int TMDS_DEBUG_VSYNC : 1; - unsigned int TMDS_DEBUG_VSYNC_EN : 1; - unsigned int : 6; - unsigned int TMDS_DEBUG_DE : 1; - unsigned int TMDS_DEBUG_DE_EN : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TMDS_STEREOSYNC_CTL_SEL__SI__VI { - struct { - unsigned int TMDS_STEREOSYNC_CTL_SEL : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TMDS_SYNC_CHAR_PATTERN_0_1__SI__VI { - struct { - unsigned int TMDS_SYNC_CHAR_PATTERN0 : 10; - unsigned int : 6; - unsigned int TMDS_SYNC_CHAR_PATTERN1 : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TMDS_SYNC_CHAR_PATTERN_2_3__SI__VI { - struct { - unsigned int TMDS_SYNC_CHAR_PATTERN2 : 10; - unsigned int : 6; - unsigned int TMDS_SYNC_CHAR_PATTERN3 : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_DATA_SYNCHRONIZATION__SI { - struct { - unsigned int UNIPHY_DSYNSEL : 1; - unsigned int : 3; - unsigned int UNIPHY_DSYN_LEVEL : 2; - unsigned int UNIPHY_DSYN_ERROR : 1; - unsigned int : 1; - unsigned int UNIPHY_SOURCE_SELECT : 1; - unsigned int : 3; - unsigned int UNIPHY_LINK_ENABLE : 1; - unsigned int : 3; - unsigned int UNIPHY_DUAL_LINK_PHASE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_DATA_SYNCHRONIZATION__VI { - struct { - unsigned int UNIPHY_DSYNSEL : 1; - unsigned int : 3; - unsigned int UNIPHY_DSYN_LEVEL : 2; - unsigned int UNIPHY_DSYN_ERROR : 1; - unsigned int : 1; - unsigned int UNIPHY_SOURCE_SELECT : 1; - unsigned int : 7; - unsigned int UNIPHY_DUAL_LINK_PHASE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKA__SI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKA : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKA : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKA : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKA_AK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int UNIPHY_IMPCAL_VALUE_LINKA : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKA : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKA : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKA__VI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKA : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKA : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKA : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKA_AK : 1; - unsigned int : 5; - unsigned int UNIPHY_IMPCAL_VALUE_LINKA : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKA : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKA : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA : 1; - unsigned int : 1; - unsigned int UNIPHY_IMPCAL_SEL_LINKA : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKB__SI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKB : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKB : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKB : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKB_AK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int UNIPHY_IMPCAL_VALUE_LINKB : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKB : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKB : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKB__VI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKB : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKB : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKB : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKB_AK : 1; - unsigned int : 5; - unsigned int UNIPHY_IMPCAL_VALUE_LINKB : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKB : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKB : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB : 1; - unsigned int : 1; - unsigned int UNIPHY_IMPCAL_SEL_LINKB : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKC__SI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKC : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKC : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKC : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKC_AK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int UNIPHY_IMPCAL_VALUE_LINKC : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKC : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKC : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKC__VI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKC : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKC : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKC : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKC_AK : 1; - unsigned int : 5; - unsigned int UNIPHY_IMPCAL_VALUE_LINKC : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKC : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKC : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC : 1; - unsigned int : 1; - unsigned int UNIPHY_IMPCAL_SEL_LINKC : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKD__SI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKD : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKD : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKD : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKD_AK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int UNIPHY_IMPCAL_VALUE_LINKD : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKD : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKD : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKD__VI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKD : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKD : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKD : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKD_AK : 1; - unsigned int : 5; - unsigned int UNIPHY_IMPCAL_VALUE_LINKD : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKD : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKD : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD : 1; - unsigned int : 1; - unsigned int UNIPHY_IMPCAL_SEL_LINKD : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKE__SI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKE : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKE : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKE : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKE_AK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int UNIPHY_IMPCAL_VALUE_LINKE : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKE : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKE : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKE__VI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKE : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKE : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKE : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKE_AK : 1; - unsigned int : 5; - unsigned int UNIPHY_IMPCAL_VALUE_LINKE : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKE : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKE : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE : 1; - unsigned int : 1; - unsigned int UNIPHY_IMPCAL_SEL_LINKE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKF__SI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKF : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKF : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKF : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKF_AK : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int UNIPHY_IMPCAL_VALUE_LINKF : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKF : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKF : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_LINKF__VI { - struct { - unsigned int UNIPHY_IMPCAL_ENABLE_LINKF : 1; - unsigned int : 7; - unsigned int UNIPHY_IMPCAL_CALOUT_LINKF : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKF : 1; - unsigned int UNIPHY_CALOUT_ERROR_LINKF_AK : 1; - unsigned int : 5; - unsigned int UNIPHY_IMPCAL_VALUE_LINKF : 4; - unsigned int UNIPHY_IMPCAL_STEP_DELAY_LINKF : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_LINKF : 4; - unsigned int UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF : 1; - unsigned int : 1; - unsigned int UNIPHY_IMPCAL_SEL_LINKF : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_PERIOD__SI__VI { - struct { - unsigned int UNIPHY_IMPCAL_PERIOD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_REG_TEST_OUTPUT__SI { - struct { - unsigned int UNIPHY_TEST_CNTL : 4; - unsigned int : 6; - unsigned int : 2; - unsigned int : 1; - unsigned int UNIPHY_DIG_BIST_RESET : 1; - unsigned int : 2; - unsigned int UNIPHY_DIG_BIST_ERROR : 4; - unsigned int : 4; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_REG_TEST_OUTPUT__VI { - struct { - unsigned int UNIPHY_TEST_CNTL : 5; - unsigned int UNIPHY_PLL_TEST_VCTL : 4; - unsigned int UNIPHY_PLL_TEST_SSAMP_EN : 1; - unsigned int UNIPHY_PLL_TEST_UNLOCK_CLR : 1; - unsigned int : 4; - unsigned int UNIPHY_DIG_BIST_RESET : 1; - unsigned int UNIPHY_DIG_BIST_SEL : 1; - unsigned int UNIPHY_TEST_VCTL_EN : 1; - unsigned int : 2; - unsigned int UNIPHY_DIG_BIST_ERROR : 5; - unsigned int UNIPHY_PLL_TEST_VCTL_ADC : 3; - unsigned int UNIPHY_PLL_TEST_FREQ_LOCK : 1; - unsigned int UNIPHY_PLL_INTRESET : 1; - unsigned int UNIPHY_PLL_TEST_UNLOCK_STICKY : 1; - unsigned int UNIPHY_PLL_TEST_LOCK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union URGENCY_STAT__SI { - struct { - unsigned int : 1; - unsigned int : 7; - unsigned int : 12; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union USER_SQC_BANK_DISABLE { - struct { - unsigned int : 16; - unsigned int SQC0_BANK_DISABLE : 4; - unsigned int SQC1_BANK_DISABLE : 4; - unsigned int SQC2_BANK_DISABLE__CI__VI : 4; - unsigned int SQC3_BANK_DISABLE__CI__VI : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_CGC_CTRL__SI { - struct { - unsigned int DYN_CLOCK_MODE : 1; - unsigned int : 7; - unsigned int CLK_OFF_DELAY : 4; - unsigned int CLK_GATE_DLY_TIMER : 4; - unsigned int SYS_MODE : 1; - unsigned int UDEC_MODE : 1; - unsigned int MPEG2_MODE : 1; - unsigned int REGS_MODE : 1; - unsigned int RBC_MODE : 1; - unsigned int LMI_MC_MODE : 1; - unsigned int LMI_UMC_MODE : 1; - unsigned int IDCT_MODE : 1; - unsigned int MPRD_MODE : 1; - unsigned int MPC_MODE : 1; - unsigned int LBSI_MODE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_CGC_CTRL__VI { - struct { - unsigned int DYN_CLOCK_MODE : 1; - unsigned int JPEG2_MODE : 1; - unsigned int CLK_GATE_DLY_TIMER : 4; - unsigned int CLK_OFF_DELAY : 5; - unsigned int UDEC_RE_MODE : 1; - unsigned int UDEC_CM_MODE : 1; - unsigned int UDEC_IT_MODE : 1; - unsigned int UDEC_DB_MODE : 1; - unsigned int UDEC_MP_MODE : 1; - unsigned int SYS_MODE : 1; - unsigned int UDEC_MODE : 1; - unsigned int MPEG2_MODE : 1; - unsigned int REGS_MODE : 1; - unsigned int RBC_MODE : 1; - unsigned int LMI_MC_MODE : 1; - unsigned int LMI_UMC_MODE : 1; - unsigned int IDCT_MODE : 1; - unsigned int MPRD_MODE : 1; - unsigned int MPC_MODE : 1; - unsigned int LBSI_MODE : 1; - unsigned int LRBBM_MODE : 1; - unsigned int WCB_MODE : 1; - unsigned int VCPU_MODE : 1; - unsigned int SCPU_MODE : 1; - unsigned int JPEG_MODE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_CGC_GATE__SI__VI { - struct { - unsigned int SYS : 1; - unsigned int UDEC : 1; - unsigned int MPEG2 : 1; - unsigned int REGS : 1; - unsigned int RBC : 1; - unsigned int LMI_MC : 1; - unsigned int LMI_UMC : 1; - unsigned int IDCT : 1; - unsigned int MPRD : 1; - unsigned int MPC : 1; - unsigned int LBSI : 1; - unsigned int LRBBM__VI : 1; - unsigned int UDEC_RE__VI : 1; - unsigned int UDEC_CM__VI : 1; - unsigned int UDEC_IT__VI : 1; - unsigned int UDEC_DB__VI : 1; - unsigned int UDEC_MP__VI : 1; - unsigned int WCB__VI : 1; - unsigned int VCPU__VI : 1; - unsigned int SCPU__VI : 1; - unsigned int JPEG__VI : 1; - unsigned int JPEG2__VI : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_CGC_STATUS__SI__VI { - struct { - unsigned int SYS_SCLK : 1; - unsigned int SYS_DCLK : 1; - unsigned int SYS_VCLK : 1; - unsigned int UDEC_SCLK : 1; - unsigned int UDEC_DCLK : 1; - unsigned int UDEC_VCLK : 1; - unsigned int MPEG2_SCLK : 1; - unsigned int MPEG2_DCLK : 1; - unsigned int MPEG2_VCLK : 1; - unsigned int REGS_SCLK : 1; - unsigned int REGS_VCLK : 1; - unsigned int RBC_SCLK : 1; - unsigned int LMI_MC_SCLK : 1; - unsigned int LMI_UMC_SCLK : 1; - unsigned int IDCT_SCLK : 1; - unsigned int IDCT_VCLK : 1; - unsigned int MPRD_SCLK : 1; - unsigned int MPRD_DCLK : 1; - unsigned int MPRD_VCLK : 1; - unsigned int MPC_SCLK : 1; - unsigned int MPC_DCLK : 1; - unsigned int LBSI_SCLK : 1; - unsigned int LBSI_VCLK : 1; - unsigned int LRBBM_SCLK__VI : 1; - unsigned int WCB_SCLK__VI : 1; - unsigned int VCPU_SCLK__VI : 1; - unsigned int VCPU_VCLK__VI : 1; - unsigned int SCPU_SCLK__VI : 1; - unsigned int SCPU_VCLK__VI : 1; - unsigned int : 1; - unsigned int JPEG_ACTIVE__VI : 1; - unsigned int ALL_DEC_ACTIVE__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_CONFIG { - struct { - unsigned int : 8; - unsigned int UVD_RDREQ_URG : 4; - unsigned int : 4; - unsigned int UVD_REQ_TRAN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_CONTEXT_ID__SI__VI { - struct { - unsigned int CONTEXT_ID : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_CTX_DATA__SI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_CTX_INDEX__SI__VI { - struct { - unsigned int INDEX : 9; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_ENGINE_CNTL__SI__VI { - struct { - unsigned int ENGINE_START : 1; - unsigned int ENGINE_START_MODE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_GPCOM_VCPU_CMD__SI__VI { - struct { - unsigned int CMD_SEND : 1; - unsigned int CMD : 30; - unsigned int CMD_SOURCE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_GPCOM_VCPU_DATA0__SI__VI { - struct { - unsigned int DATA0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_GPCOM_VCPU_DATA1__SI__VI { - struct { - unsigned int DATA1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_ADDR_EXT__SI__VI { - struct { - unsigned int VCPU_ADDR_EXT : 4; - unsigned int CM_ADDR_EXT : 4; - unsigned int IT_ADDR_EXT : 4; - unsigned int VCPU_VM_ADDR_EXT : 4; - unsigned int RE_ADDR_EXT__VI : 4; - unsigned int MP_ADDR_EXT__VI : 4; - unsigned int VCPU_NC0_ADDR_EXT__VI : 4; - unsigned int VCPU_NC1_ADDR_EXT__VI : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_CACHE_CTRL__SI__VI { - struct { - unsigned int IT_EN : 1; - unsigned int IT_FLUSH : 1; - unsigned int CM_EN : 1; - unsigned int CM_FLUSH : 1; - unsigned int VCPU_EN : 1; - unsigned int VCPU_FLUSH : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_CTRL2__SI__VI { - struct { - unsigned int SPH_DIS : 1; - unsigned int STALL_ARB : 1; - unsigned int ASSERT_UMC_URGENT : 1; - unsigned int MASK_UMC_URGENT : 1; - unsigned int MCIF_WR_WATERMARK : 3; - unsigned int DRCITF_BUBBLE_FIX_DIS : 1; - unsigned int STALL_ARB_UMC : 1; - unsigned int MC_READ_ID_SEL__VI : 2; - unsigned int MC_WRITE_ID_SEL__VI : 2; - unsigned int VCPU_NC0_EXT_EN__VI : 1; - unsigned int VCPU_NC1_EXT_EN__VI : 1; - unsigned int SPU_EXTRA_CID_EN__VI : 1; - unsigned int RE_OFFLOAD_EN__VI : 1; - unsigned int RE_OFLD_MIF_WR_REQ_NUM__VI : 8; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_CTRL__SI { - struct { - unsigned int WRITE_CLEAN_TIMER : 8; - unsigned int WRITE_CLEAN_TIMER_EN : 1; - unsigned int REQ_MODE : 1; - unsigned int : 1; - unsigned int ASSERT_MC_URGENT : 1; - unsigned int MASK_MC_URGENT : 1; - unsigned int DATA_COHERENCY_EN : 1; - unsigned int CRC_RESET : 1; - unsigned int CRC_SEL : 5; - unsigned int DISABLE_ON_FWV_FAIL : 1; - unsigned int VCPU_DATA_COHERENCY_EN : 1; - unsigned int CM_DATA_COHERENCY_EN : 1; - unsigned int DB_DB_DATA_COHERENCY_EN : 1; - unsigned int DB_IT_DATA_COHERENCY_EN : 1; - unsigned int IT_IT_DATA_COHERENCY_EN : 1; - unsigned int RFU : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_CTRL__VI { - struct { - unsigned int WRITE_CLEAN_TIMER : 8; - unsigned int WRITE_CLEAN_TIMER_EN : 1; - unsigned int REQ_MODE : 1; - unsigned int : 1; - unsigned int ASSERT_MC_URGENT : 1; - unsigned int MASK_MC_URGENT : 1; - unsigned int DATA_COHERENCY_EN : 1; - unsigned int CRC_RESET : 1; - unsigned int CRC_SEL : 5; - unsigned int DISABLE_ON_FWV_FAIL : 1; - unsigned int VCPU_DATA_COHERENCY_EN : 1; - unsigned int CM_DATA_COHERENCY_EN : 1; - unsigned int DB_DB_DATA_COHERENCY_EN : 1; - unsigned int DB_IT_DATA_COHERENCY_EN : 1; - unsigned int IT_IT_DATA_COHERENCY_EN : 1; - unsigned int MIF_MIF_DATA_COHERENCY_EN : 1; - unsigned int RFU : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_EXT40_ADDR__SI__VI { - struct { - unsigned int ADDR : 8; - unsigned int : 8; - unsigned int INDEX : 5; - unsigned int : 10; - unsigned int WRITE_ADDR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_STATUS__SI__VI { - struct { - unsigned int READ_CLEAN : 1; - unsigned int WRITE_CLEAN : 1; - unsigned int WRITE_CLEAN_RAW : 1; - unsigned int VCPU_LMI_WRITE_CLEAN : 1; - unsigned int UMC_READ_CLEAN : 1; - unsigned int UMC_WRITE_CLEAN : 1; - unsigned int UMC_WRITE_CLEAN_RAW : 1; - unsigned int PENDING_UVD_MC_WRITE : 1; - unsigned int READ_CLEAN_RAW : 1; - unsigned int UMC_READ_CLEAN_RAW : 1; - unsigned int UMC_UVD_IDLE : 1; - unsigned int UMC_AVP_IDLE : 1; - unsigned int ADP_MC_READ_CLEAN : 1; - unsigned int ADP_UMC_READ_CLEAN : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_SWAP_CNTL__SI__VI { - struct { - unsigned int RB_MC_SWAP : 2; - unsigned int IB_MC_SWAP : 2; - unsigned int RB_RPTR_MC_SWAP : 2; - unsigned int VCPU_R_MC_SWAP : 2; - unsigned int VCPU_W_MC_SWAP : 2; - unsigned int CM_MC_SWAP : 2; - unsigned int IT_MC_SWAP : 2; - unsigned int DB_R_MC_SWAP : 2; - unsigned int DB_W_MC_SWAP : 2; - unsigned int CSM_MC_SWAP : 2; - unsigned int : 2; - unsigned int MP_REF16_MC_SWAP : 2; - unsigned int DBW_MC_SWAP : 2; - unsigned int RB_WR_MC_SWAP : 2; - unsigned int RE_MC_SWAP__VI : 2; - unsigned int MP_MC_SWAP__VI : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MASTINT_EN__SI__VI { - struct { - unsigned int OVERRUN_RST : 1; - unsigned int VCPU_EN : 1; - unsigned int SYS_EN : 1; - unsigned int : 1; - unsigned int INT_OVERRUN : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MPC_CNTL__SI__VI { - struct { - unsigned int : 3; - unsigned int REPLACEMENT_MODE : 3; - unsigned int PERF_RST : 1; - unsigned int : 1; - unsigned int DBG_MUX : 4; - unsigned int : 4; - unsigned int AVE_WEIGHT : 2; - unsigned int URGENT_EN : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MPC_SET_ALU__SI__VI { - struct { - unsigned int FUNCT : 3; - unsigned int : 1; - unsigned int OPERAND : 8; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MPC_SET_MUXA0__SI__VI { - struct { - unsigned int VARA_0 : 6; - unsigned int VARA_1 : 6; - unsigned int VARA_2 : 6; - unsigned int VARA_3 : 6; - unsigned int VARA_4 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MPC_SET_MUXA1__SI__VI { - struct { - unsigned int VARA_5 : 6; - unsigned int VARA_6 : 6; - unsigned int VARA_7 : 6; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MPC_SET_MUXB0__SI__VI { - struct { - unsigned int VARB_0 : 6; - unsigned int VARB_1 : 6; - unsigned int VARB_2 : 6; - unsigned int VARB_3 : 6; - unsigned int VARB_4 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MPC_SET_MUXB1__SI__VI { - struct { - unsigned int VARB_5 : 6; - unsigned int VARB_6 : 6; - unsigned int VARB_7 : 6; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MPC_SET_MUX__SI__VI { - struct { - unsigned int SET_0 : 3; - unsigned int SET_1 : 3; - unsigned int SET_2 : 3; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MP_SWAP_CNTL__SI__VI { - struct { - unsigned int MP_REF0_MC_SWAP : 2; - unsigned int MP_REF1_MC_SWAP : 2; - unsigned int MP_REF2_MC_SWAP : 2; - unsigned int MP_REF3_MC_SWAP : 2; - unsigned int MP_REF4_MC_SWAP : 2; - unsigned int MP_REF5_MC_SWAP : 2; - unsigned int MP_REF6_MC_SWAP : 2; - unsigned int MP_REF7_MC_SWAP : 2; - unsigned int MP_REF8_MC_SWAP : 2; - unsigned int MP_REF9_MC_SWAP : 2; - unsigned int MP_REF10_MC_SWAP : 2; - unsigned int MP_REF11_MC_SWAP : 2; - unsigned int MP_REF12_MC_SWAP : 2; - unsigned int MP_REF13_MC_SWAP : 2; - unsigned int MP_REF14_MC_SWAP : 2; - unsigned int MP_REF15_MC_SWAP : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_RBC_IB_BASE__SI { - struct { - unsigned int : 6; - unsigned int IB_BASE : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_RBC_IB_SIZE__SI__VI { - struct { - unsigned int : 4; - unsigned int IB_SIZE : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_RBC_RB_BASE__SI { - struct { - unsigned int : 6; - unsigned int RB_BASE : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_RBC_RB_CNTL__SI__VI { - struct { - unsigned int RB_BUFSZ : 5; - unsigned int : 3; - unsigned int RB_BLKSZ : 5; - unsigned int : 3; - unsigned int RB_NO_FETCH : 1; - unsigned int : 3; - unsigned int RB_WPTR_POLL_EN : 1; - unsigned int : 3; - unsigned int RB_NO_UPDATE : 1; - unsigned int : 3; - unsigned int RB_RPTR_WR_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_RBC_RB_RPTR_ADDR__SI__VI { - struct { - unsigned int RB_RPTR_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_RBC_RB_RPTR__SI__VI { - struct { - unsigned int : 4; - unsigned int RB_RPTR : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_RBC_RB_WPTR__SI__VI { - struct { - unsigned int : 4; - unsigned int RB_WPTR : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SEMA_ADDR_HIGH__SI__VI { - struct { - unsigned int ADDR_42_23 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SEMA_ADDR_LOW__SI__VI { - struct { - unsigned int ADDR_22_3 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SEMA_CMD__SI__VI { - struct { - unsigned int REQ_CMD : 4; - unsigned int WR_PHASE : 2; - unsigned int MODE : 1; - unsigned int VMID_EN__VI : 1; - unsigned int VMID__VI : 4; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SEMA_CNTL__SI__VI { - struct { - unsigned int SEMAPHORE_EN : 1; - unsigned int ADVANCED_MODE_DIS : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SI__VI { - struct { - unsigned int SIGNAL_INCOMPLETE_EN : 1; - unsigned int SIGNAL_INCOMPLETE_COUNT : 20; - unsigned int : 3; - unsigned int RESEND_TIMER : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SEMA_TIMEOUT_STATUS__SI__VI { - struct { - unsigned int SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT : 1; - unsigned int SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT : 1; - unsigned int SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT : 1; - unsigned int SEMAPHORE_TIMEOUT_CLEAR : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__SI__VI { - struct { - unsigned int WAIT_FAULT_EN : 1; - unsigned int WAIT_FAULT_COUNT : 20; - unsigned int : 3; - unsigned int RESEND_TIMER : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__SI__VI { - struct { - unsigned int WAIT_INCOMPLETE_EN : 1; - unsigned int WAIT_INCOMPLETE_COUNT : 20; - unsigned int : 3; - unsigned int RESEND_TIMER : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SOFT_RESET__SI { - struct { - unsigned int RBC_SOFT_RESET : 1; - unsigned int LBSI_SOFT_RESET : 1; - unsigned int LMI_SOFT_RESET : 1; - unsigned int VCPU_SOFT_RESET : 1; - unsigned int UDEC_SOFT_RESET : 1; - unsigned int CSM_SOFT_RESET : 1; - unsigned int CXW_SOFT_RESET : 1; - unsigned int TAP_SOFT_RESET : 1; - unsigned int MPC_SOFT_RESET : 1; - unsigned int FWV_SOFT_RESET : 1; - unsigned int IH_SOFT_RESET : 1; - unsigned int MPRD_SOFT_RESET : 1; - unsigned int IDCT_SOFT_RESET : 1; - unsigned int LMI_UMC_SOFT_RESET : 1; - unsigned int SPH_SOFT_RESET : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SOFT_RESET__VI { - struct { - unsigned int RBC_SOFT_RESET : 1; - unsigned int LBSI_SOFT_RESET : 1; - unsigned int LMI_SOFT_RESET : 1; - unsigned int VCPU_SOFT_RESET : 1; - unsigned int UDEC_SOFT_RESET : 1; - unsigned int CSM_SOFT_RESET : 1; - unsigned int CXW_SOFT_RESET : 1; - unsigned int TAP_SOFT_RESET : 1; - unsigned int MPC_SOFT_RESET : 1; - unsigned int JPEG_SCLK_RESET_STATUS : 1; - unsigned int IH_SOFT_RESET : 1; - unsigned int MPRD_SOFT_RESET : 1; - unsigned int IDCT_SOFT_RESET : 1; - unsigned int LMI_UMC_SOFT_RESET : 1; - unsigned int SPH_SOFT_RESET : 1; - unsigned int MIF_SOFT_RESET : 1; - unsigned int LCM_SOFT_RESET : 1; - unsigned int SUVD_SOFT_RESET : 1; - unsigned int LBSI_VCLK_RESET_STATUS : 1; - unsigned int VCPU_VCLK_RESET_STATUS : 1; - unsigned int UDEC_VCLK_RESET_STATUS : 1; - unsigned int UDEC_DCLK_RESET_STATUS : 1; - unsigned int MPC_DCLK_RESET_STATUS : 1; - unsigned int MPRD_VCLK_RESET_STATUS : 1; - unsigned int MPRD_DCLK_RESET_STATUS : 1; - unsigned int IDCT_VCLK_RESET_STATUS : 1; - unsigned int MIF_DCLK_RESET_STATUS : 1; - unsigned int LCM_DCLK_RESET_STATUS : 1; - unsigned int SUVD_VCLK_RESET_STATUS : 1; - unsigned int SUVD_DCLK_RESET_STATUS : 1; - unsigned int RE_DCLK_RESET_STATUS : 1; - unsigned int SRE_DCLK_RESET_STATUS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_STATUS__SI__VI { - struct { - unsigned int RBC_BUSY : 1; - unsigned int VCPU_REPORT : 7; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 13; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_VCPU_CACHE_OFFSET0__SI__VI { - struct { - unsigned int CACHE_OFFSET0 : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_VCPU_CACHE_OFFSET1__SI__VI { - struct { - unsigned int CACHE_OFFSET1 : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_VCPU_CACHE_OFFSET2__SI__VI { - struct { - unsigned int CACHE_OFFSET2 : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_VCPU_CACHE_SIZE0__SI__VI { - struct { - unsigned int CACHE_SIZE0 : 21; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_VCPU_CACHE_SIZE1__SI__VI { - struct { - unsigned int CACHE_SIZE1 : 21; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_VCPU_CACHE_SIZE2__SI__VI { - struct { - unsigned int CACHE_SIZE2 : 21; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_VCPU_CNTL__SI { - struct { - unsigned int IRQ_ERR : 4; - unsigned int AXI_MAX_BRST_SIZE_IS_4 : 1; - unsigned int PMB_ED_ENABLE : 1; - unsigned int PMB_SOFT_RESET : 1; - unsigned int RBBM_SOFT_RESET : 1; - unsigned int ABORT_REQ : 1; - unsigned int CLK_EN : 1; - unsigned int TRCE_EN : 1; - unsigned int TRCE_MUX : 2; - unsigned int DBG_MUX : 3; - unsigned int JTAG_EN : 1; - unsigned int CLK_ACTIVE : 1; - unsigned int TIMEOUT_DIS : 1; - unsigned int : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_VCPU_CNTL__VI { - struct { - unsigned int IRQ_ERR : 4; - unsigned int AXI_MAX_BRST_SIZE_IS_4 : 1; - unsigned int PMB_ED_ENABLE : 1; - unsigned int PMB_SOFT_RESET : 1; - unsigned int RBBM_SOFT_RESET : 1; - unsigned int ABORT_REQ : 1; - unsigned int CLK_EN : 1; - unsigned int TRCE_EN : 1; - unsigned int TRCE_MUX : 2; - unsigned int DBG_MUX : 3; - unsigned int JTAG_EN : 1; - unsigned int MIF_WR_LOW_THRESHOLD_BP : 1; - unsigned int TIMEOUT_DIS : 1; - unsigned int SUVD_EN : 1; - unsigned int PRB_TIMEOUT_VAL : 8; - unsigned int CABAC_MB_ACC : 1; - unsigned int : 1; - unsigned int WMV9_EN : 1; - unsigned int RE_OFFLOAD_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VBLANK_STATUS__SI { - struct { - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_CONFIG__CI__VI { - struct { - unsigned int : 8; - unsigned int VCE_RDREQ_URG : 4; - unsigned int : 4; - unsigned int VCE_REQ_TRAN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VENDOR_CAP_LIST__CI__VI { - struct { - unsigned int CAP_ID : 8; - unsigned int NEXT_PTR : 8; - unsigned int LENGTH : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VENDOR_ID { - struct { - unsigned int VENDOR_ID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA25_PPLL_FB_DIV__SI__VI { - struct { - unsigned int VGA25_PPLL_FB_DIV_FRACTION : 4; - unsigned int VGA25_PPLL_FB_DIV_FRACTION_CNTL : 2; - unsigned int : 10; - unsigned int VGA25_PPLL_FB_DIV : 11; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA25_PPLL_POST_DIV__SI { - struct { - unsigned int VGA25_PPLL_POST_DIV : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA25_PPLL_POST_DIV__VI { - struct { - unsigned int VGA25_PPLL_POST_DIV_PIXCLK : 7; - unsigned int : 1; - unsigned int VGA25_PPLL_POST_DIV_DVOCLK : 7; - unsigned int : 1; - unsigned int VGA25_PPLL_POST_DIV_IDCLK : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA25_PPLL_REF_DIV__SI__VI { - struct { - unsigned int VGA25_PPLL_REF_DIV : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA28_PPLL_FB_DIV__SI__VI { - struct { - unsigned int VGA28_PPLL_FB_DIV_FRACTION : 4; - unsigned int VGA28_PPLL_FB_DIV_FRACTION_CNTL : 2; - unsigned int : 10; - unsigned int VGA28_PPLL_FB_DIV : 11; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA28_PPLL_POST_DIV__SI { - struct { - unsigned int VGA28_PPLL_POST_DIV : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA28_PPLL_POST_DIV__VI { - struct { - unsigned int VGA28_PPLL_POST_DIV_PIXCLK : 7; - unsigned int : 1; - unsigned int VGA28_PPLL_POST_DIV_DVOCLK : 7; - unsigned int : 1; - unsigned int VGA28_PPLL_POST_DIV_IDCLK : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA28_PPLL_REF_DIV__SI__VI { - struct { - unsigned int VGA28_PPLL_REF_DIV : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA41_PPLL_FB_DIV__SI__VI { - struct { - unsigned int VGA41_PPLL_FB_DIV_FRACTION : 4; - unsigned int VGA41_PPLL_FB_DIV_FRACTION_CNTL : 2; - unsigned int : 10; - unsigned int VGA41_PPLL_FB_DIV : 11; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA41_PPLL_POST_DIV__SI { - struct { - unsigned int VGA41_PPLL_POST_DIV : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA41_PPLL_POST_DIV__VI { - struct { - unsigned int VGA41_PPLL_POST_DIV_PIXCLK : 7; - unsigned int : 1; - unsigned int VGA41_PPLL_POST_DIV_DVOCLK : 7; - unsigned int : 1; - unsigned int VGA41_PPLL_POST_DIV_IDCLK : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA41_PPLL_REF_DIV__SI__VI { - struct { - unsigned int VGA41_PPLL_REF_DIV : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGADCC_DBG_DCCIF_C__SI__VI { - struct { - unsigned int DBG_DCCIF_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_CACHE_CONTROL__SI__VI { - struct { - unsigned int VGA_WRITE_THROUGH_CACHE_DIS : 1; - unsigned int : 7; - unsigned int VGA_READ_CACHE_DISABLE : 1; - unsigned int : 7; - unsigned int VGA_READ_BUFFER_INVALIDATE : 1; - unsigned int : 3; - unsigned int VGA_DCCIF_W256ONLY : 1; - unsigned int : 3; - unsigned int VGA_DCCIF_WC_TIMEOUT : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_CRTC__SI__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 5; - unsigned int : 4; - unsigned int : 11; - unsigned int : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_DEBUG_READBACK_DATA__SI__VI { - struct { - unsigned int VGA_DEBUG_READBACK_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_DEBUG_READBACK_INDEX__SI__VI { - struct { - unsigned int VGA_DEBUG_READBACK_INDEX : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_DISPBUF1_SURFACE_ADDR__SI__VI { - struct { - unsigned int VGA_DISPBUF1_SURFACE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_DISPBUF2_SURFACE_ADDR__SI__VI { - struct { - unsigned int VGA_DISPBUF2_SURFACE_ADDR : 25; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_HDP_CONTROL__SI__VI { - struct { - unsigned int VGA_MEM_PAGE_SELECT_EN : 1; - unsigned int : 3; - unsigned int VGA_MEMORY_DISABLE : 1; - unsigned int : 3; - unsigned int VGA_RBBM_LOCK_DISABLE : 1; - unsigned int : 7; - unsigned int VGA_SOFT_RESET : 1; - unsigned int : 7; - unsigned int VGA_TEST_RESET_CONTROL : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_HDP__SI__VI { - struct { - unsigned int : 1; - unsigned int : 5; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 15; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_HW_DEBUG__SI__VI { - struct { - unsigned int VGA_HW_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_INTERRUPT_CONTROL__SI__VI { - struct { - unsigned int VGA_MEM_ACCESS_INT_MASK : 1; - unsigned int : 7; - unsigned int VGA_REG_ACCESS_INT_MASK : 1; - unsigned int : 7; - unsigned int VGA_DISPLAY_SWITCH_INT_MASK : 1; - unsigned int : 7; - unsigned int VGA_MODE_AUTO_TRIGGER_INT_MASK : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_INTERRUPT_STATUS__SI__VI { - struct { - unsigned int VGA_MEM_ACCESS_INT_STATUS : 1; - unsigned int VGA_REG_ACCESS_INT_STATUS : 1; - unsigned int VGA_DISPLAY_SWITCH_INT_STATUS : 1; - unsigned int VGA_MODE_AUTO_TRIGGER_INT_STATUS : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_MAIN_CONTROL__SI__VI { - struct { - unsigned int VGA_CRTC_TIMEOUT : 2; - unsigned int : 1; - unsigned int VGA_RENDER_TIMEOUT_COUNT : 2; - unsigned int VGA_VIRTUAL_VERTICAL_RETRACE_DURATION : 3; - unsigned int VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT : 2; - unsigned int : 2; - unsigned int VGA_MC_WRITE_CLEAN_WAIT_DELAY__VI : 4; - unsigned int VGA_READBACK_NO_DISPLAY_SOURCE_SELECT : 2; - unsigned int : 6; - unsigned int VGA_READBACK_CRT_INTR_SOURCE_SELECT : 2; - unsigned int VGA_READBACK_SENSE_SWITCH_SELECT : 1; - unsigned int VGA_READ_URGENT_ENABLE : 1; - unsigned int VGA_WRITES_URGENT_ENABLE : 1; - unsigned int VGA_EXTERNAL_DAC_SENSE : 1; - unsigned int : 1; - unsigned int VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_MAIN__SI__VI { - struct { - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_MEMORY_BASE_ADDRESS_HIGH__SI__VI { - struct { - unsigned int VGA_MEMORY_BASE_ADDRESS_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_MEMORY_BASE_ADDRESS__SI__VI { - struct { - unsigned int VGA_MEMORY_BASE_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_MEM_READ_PAGE_ADDR__SI__VI { - struct { - unsigned int VGA_MEM_READ_PAGE0_ADDR : 10; - unsigned int : 6; - unsigned int VGA_MEM_READ_PAGE1_ADDR : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_MEM_WRITE_PAGE_ADDR__SI__VI { - struct { - unsigned int VGA_MEM_WRITE_PAGE0_ADDR : 10; - unsigned int : 6; - unsigned int VGA_MEM_WRITE_PAGE1_ADDR : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_MODE_CONTROL__SI__VI { - struct { - unsigned int VGA_ATI_LINEAR : 1; - unsigned int : 3; - unsigned int VGA_LUT_PALETTE_UPDATE_MODE : 2; - unsigned int : 2; - unsigned int VGA_128K_APERTURE_PAGING : 1; - unsigned int : 7; - unsigned int VGA_TEXT_132_COLUMNS_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_REG__SI__VI { - struct { - unsigned int : 4; - unsigned int : 4; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 8; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_RENDER_CONTROL__SI__VI { - struct { - unsigned int VGA_BLINK_RATE : 5; - unsigned int VGA_BLINK_MODE : 2; - unsigned int VGA_CURSOR_BLINK_INVERT : 1; - unsigned int VGA_EXTD_ADDR_COUNT_ENABLE : 1; - unsigned int : 7; - unsigned int VGA_VSTATUS_CNTL : 2; - unsigned int : 6; - unsigned int VGA_LOCK_8DOT : 1; - unsigned int VGAREG_LINECMP_COMPATIBILITY_SEL : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_SEQUENCER_RESET_CONTROL__SI__VI { - struct { - unsigned int D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1; - unsigned int D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1; - unsigned int D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1; - unsigned int D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1; - unsigned int D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1; - unsigned int D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET : 1; - unsigned int : 2; - unsigned int D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1; - unsigned int D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1; - unsigned int D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1; - unsigned int D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1; - unsigned int D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1; - unsigned int D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET : 1; - unsigned int : 2; - unsigned int VGA_MODE_AUTO_TRIGGER_ENABLE : 1; - unsigned int VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT : 1; - unsigned int VGA_MODE_AUTO_TRIGGER_INDEX_SELECT : 6; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_SOURCE_SELECT__SI__VI { - struct { - unsigned int VGA_SOURCE_SEL_A : 3; - unsigned int : 5; - unsigned int VGA_SOURCE_SEL_B : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_STATUS_CLEAR__SI__VI { - struct { - unsigned int VGA_MEM_ACCESS_INT_CLEAR : 1; - unsigned int : 7; - unsigned int VGA_REG_ACCESS_INT_CLEAR : 1; - unsigned int : 7; - unsigned int VGA_DISPLAY_SWITCH_INT_CLEAR : 1; - unsigned int : 7; - unsigned int VGA_MODE_AUTO_TRIGGER_INT_CLEAR : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_STATUS__SI__VI { - struct { - unsigned int VGA_MEM_ACCESS_STATUS : 1; - unsigned int VGA_REG_ACCESS_STATUS : 1; - unsigned int VGA_DISPLAY_SWITCH_STATUS : 1; - unsigned int VGA_MODE_AUTO_TRIGGER_STATUS : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_SURFACE_PITCH_SELECT__SI__VI { - struct { - unsigned int VGA_SURFACE_PITCH_SELECT : 2; - unsigned int : 6; - unsigned int VGA_SURFACE_HEIGHT_SELECT : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_TEST_CONTROL__SI__VI { - struct { - unsigned int VGA_TEST_ENABLE : 1; - unsigned int : 7; - unsigned int VGA_TEST_RENDER_START : 1; - unsigned int : 7; - unsigned int VGA_TEST_RENDER_DONE : 1; - unsigned int : 7; - unsigned int VGA_TEST_RENDER_DISPBUF_SELECT : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_TEST_DEBUG_DATA__SI__VI { - struct { - unsigned int VGA_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_TEST_DEBUG_INDEX__SI__VI { - struct { - unsigned int VGA_TEST_DEBUG_INDEX : 8; - unsigned int VGA_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA_TEXT__SI__VI { - struct { - unsigned int : 4; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 3; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_CACHE_INVALIDATION { - struct { - unsigned int CACHE_INVALIDATION : 2; - unsigned int : 2; - unsigned int DIS_INSTANCING_OPT__VI : 1; - unsigned int VS_NO_EXTRA_BUFFER : 1; - unsigned int AUTO_INVLD_EN : 2; - unsigned int : 1; - unsigned int USE_GS_DONE : 1; - unsigned int : 1; - unsigned int DIS_RANGE_FULL_INVLD : 1; - unsigned int GS_LATE_ALLOC_EN : 1; - unsigned int STREAMOUT_FULL_FLUSH : 1; - unsigned int : 2; - unsigned int ES_LIMIT : 5; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_CNTL_STATUS { - struct { - unsigned int VGT_BUSY : 1; - unsigned int VGT_OUT_INDX_BUSY : 1; - unsigned int VGT_OUT_BUSY : 1; - unsigned int VGT_PT_BUSY : 1; - unsigned int VGT_TE_BUSY : 1; - unsigned int VGT_VR_BUSY : 1; - unsigned int VGT_PI_BUSY : 1; - unsigned int VGT_GS_BUSY : 1; - unsigned int VGT_HS_BUSY : 1; - unsigned int VGT_TE11_BUSY : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_CNTL { - struct { - unsigned int VGT_DEBUG_INDX : 6; - unsigned int VGT_DEBUG_SEL_BUS_B : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG0 { - struct { - unsigned int vgt_busy_extended : 1; - unsigned int SPARE9 : 1; - unsigned int vgt_busy : 1; - unsigned int SPARE8 : 1; - unsigned int SPARE7 : 1; - unsigned int SPARE6 : 1; - unsigned int SPARE5 : 1; - unsigned int SPARE4 : 1; - unsigned int pi_busy : 1; - unsigned int vr_pi_busy : 1; - unsigned int pt_pi_busy : 1; - unsigned int te_pi_busy : 1; - unsigned int gs_busy : 1; - unsigned int rcm_busy : 1; - unsigned int tm_busy : 1; - unsigned int cm_busy : 1; - unsigned int gog_busy : 1; - unsigned int frmt_busy : 1; - unsigned int SPARE10 : 1; - unsigned int te11_pi_busy : 1; - unsigned int SPARE3 : 1; - unsigned int combined_out_busy : 1; - unsigned int spi_vs_interfaces_busy : 1; - unsigned int pa_interfaces_busy : 1; - unsigned int reg_clk_busy : 1; - unsigned int SPARE2 : 1; - unsigned int core_clk_busy : 1; - unsigned int gs_clk_busy : 1; - unsigned int SPARE1 : 1; - unsigned int sclk_core_vld : 1; - unsigned int sclk_gs_vld : 1; - unsigned int SPARE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG1 { - struct { - unsigned int SPARE9 : 1; - unsigned int SPARE8 : 1; - unsigned int SPARE7 : 1; - unsigned int SPARE6 : 1; - unsigned int SPARE5 : 1; - unsigned int SPARE4 : 1; - unsigned int SPARE3 : 1; - unsigned int SPARE2 : 1; - unsigned int SPARE1 : 1; - unsigned int SPARE0 : 1; - unsigned int pi_vr_valid : 1; - unsigned int vr_pi_read : 1; - unsigned int pi_pt_valid : 1; - unsigned int pt_pi_read : 1; - unsigned int pi_te_valid : 1; - unsigned int te_grp_read : 1; - unsigned int vr_out_indx_valid : 1; - unsigned int SPARE12 : 1; - unsigned int vr_out_prim_valid : 1; - unsigned int SPARE11 : 1; - unsigned int pt_out_indx_valid : 1; - unsigned int SPARE10 : 1; - unsigned int pt_out_prim_valid : 1; - unsigned int SPARE23 : 1; - unsigned int te_out_data_valid : 1; - unsigned int SPARE25 : 1; - unsigned int pi_gs_valid : 1; - unsigned int gs_pi_read : 1; - unsigned int gog_out_indx_valid : 1; - unsigned int out_indx_read : 1; - unsigned int gog_out_prim_valid : 1; - unsigned int out_prim_read : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG10__CI__VI { - struct { - unsigned int index_buffer_depth_r1_q : 5; - unsigned int eopg_r2_q : 1; - unsigned int eotg_r2_q : 1; - unsigned int onchip_gs_en_r0_q : 2; - unsigned int SPARE2 : 2; - unsigned int rcm_mem_gsprim_re_qq : 1; - unsigned int rcm_mem_gsprim_re_q : 1; - unsigned int gs_rb_space_avail_r3_q_9_0 : 10; - unsigned int es_rb_space_avail_r2_q_8_0 : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG10__SI { - struct { - unsigned int index_buffer_depth_r1_q : 5; - unsigned int eopg_r2_q : 1; - unsigned int eotg_r2_q : 1; - unsigned int : 4; - unsigned int rcm_mem_gsprim_re_qq : 1; - unsigned int rcm_mem_gsprim_re_q : 1; - unsigned int gs_rb_space_avail_r3_q_9_0 : 10; - unsigned int es_rb_space_avail_r2_q_8_0 : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG11__CI__VI { - struct { - unsigned int tm_busy_q : 1; - unsigned int tm_noif_busy_q : 1; - unsigned int tm_out_busy_q : 1; - unsigned int es_rb_dealloc_fifo_busy : 1; - unsigned int vs_dealloc_tbl_busy : 1; - unsigned int SPARE1 : 1; - unsigned int spi_gsthread_fifo_busy : 1; - unsigned int spi_esthread_fifo_busy : 1; - unsigned int hold_eswave : 1; - unsigned int es_rb_roll_over_r3 : 1; - unsigned int counters_busy_r0 : 1; - unsigned int counters_avail_r0 : 1; - unsigned int counters_available_r0 : 1; - unsigned int vs_event_fifo_rtr : 1; - unsigned int VGT_SPI_gsthread_rtr_q : 1; - unsigned int VGT_SPI_esthread_rtr_q : 1; - unsigned int gs_issue_rtr : 1; - unsigned int tm_pt_event_rtr : 1; - unsigned int SPARE0 : 1; - unsigned int gs_r0_rtr : 1; - unsigned int es_r0_rtr : 1; - unsigned int gog_tm_vs_event_rtr : 1; - unsigned int tm_rcm_gs_event_rtr : 1; - unsigned int tm_rcm_gs_tbl_rtr : 1; - unsigned int tm_rcm_es_tbl_rtr : 1; - unsigned int vs_event_fifo_empty : 1; - unsigned int vs_event_fifo_full : 1; - unsigned int es_rb_dealloc_fifo_full : 1; - unsigned int vs_dealloc_tbl_full : 1; - unsigned int send_event_q : 1; - unsigned int es_tbl_empty : 1; - unsigned int no_active_states_r0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG11__SI { - struct { - unsigned int tm_busy : 1; - unsigned int tm_noif_busy : 1; - unsigned int tm_out_busy : 1; - unsigned int es_rb_dealloc_fifo_busy : 1; - unsigned int vs_dealloc_tbl_busy : 1; - unsigned int SPARE1 : 1; - unsigned int spi_gsthread_fifo_busy : 1; - unsigned int spi_esthread_fifo_busy : 1; - unsigned int hold_eswave : 1; - unsigned int es_rb_roll_over_r3 : 1; - unsigned int counters_busy_r0 : 1; - unsigned int counters_avail_r0 : 1; - unsigned int counters_available_r0 : 1; - unsigned int vs_event_fifo_rtr : 1; - unsigned int VGT_SPI_gsthread_rtr_q : 1; - unsigned int VGT_SPI_esthread_rtr_q : 1; - unsigned int gs_issue_rtr : 1; - unsigned int tm_pt_event_rtr : 1; - unsigned int SPARE0 : 1; - unsigned int gs_r0_rtr : 1; - unsigned int es_r0_rtr : 1; - unsigned int gog_tm_vs_event_rtr : 1; - unsigned int tm_rcm_gs_event_rtr : 1; - unsigned int tm_rcm_gs_tbl_rtr : 1; - unsigned int tm_rcm_es_tbl_rtr : 1; - unsigned int vs_event_fifo_empty : 1; - unsigned int vs_event_fifo_full : 1; - unsigned int es_rb_dealloc_fifo_full : 1; - unsigned int vs_dealloc_tbl_full : 1; - unsigned int send_event_q : 1; - unsigned int es_tbl_empty : 1; - unsigned int no_active_states_r0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG12 { - struct { - unsigned int gs_state0_r0_q : 3; - unsigned int gs_state1_r0_q : 3; - unsigned int gs_state2_r0_q : 3; - unsigned int gs_state3_r0_q : 3; - unsigned int gs_state4_r0_q : 3; - unsigned int gs_state5_r0_q : 3; - unsigned int gs_state6_r0_q : 3; - unsigned int gs_state7_r0_q : 3; - unsigned int gs_state8_r0_q : 3; - unsigned int gs_state9_r0_q : 3; - unsigned int hold_eswave_eop : 1; - unsigned int SPARE0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG13 { - struct { - unsigned int gs_state10_r0_q : 3; - unsigned int gs_state11_r0_q : 3; - unsigned int gs_state12_r0_q : 3; - unsigned int gs_state13_r0_q : 3; - unsigned int gs_state14_r0_q : 3; - unsigned int gs_state15_r0_q : 3; - unsigned int gs_tbl_wrptr_r0_q_3_0 : 4; - unsigned int gsfetch_done_fifo_cnt_q_not_0 : 1; - unsigned int gsfetch_done_cnt_q_not_0 : 1; - unsigned int es_tbl_full : 1; - unsigned int SPARE1 : 1; - unsigned int SPARE0 : 1; - unsigned int active_cm_sm_r0_q : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG14 { - struct { - unsigned int SPARE3 : 4; - unsigned int gsfetch_done_fifo_full : 1; - unsigned int gs_rb_space_avail_r0 : 1; - unsigned int smx_es_done_cnt_r0_q_not_0 : 1; - unsigned int SPARE8 : 2; - unsigned int vs_done_cnt_q_not_0 : 1; - unsigned int es_flush_cnt_busy_q : 1; - unsigned int gs_tbl_full_r0 : 1; - unsigned int SPARE2 : 9; - unsigned int se1spi_gsthread_fifo_busy : 1; - unsigned int SPARE : 3; - unsigned int VGT_SE1SPI_gsthread_rtr_q : 1; - unsigned int smx1_es_done_cnt_r0_q_not_0 : 1; - unsigned int se1spi_esthread_fifo_busy : 1; - unsigned int SPARE1 : 1; - unsigned int gsfetch_done_se1_cnt_q_not_0 : 1; - unsigned int SPARE0 : 1; - unsigned int VGT_SE1SPI_esthread_rtr_q : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG15__CI__VI { - struct { - unsigned int cm_busy_q : 1; - unsigned int counters_busy_q : 1; - unsigned int output_fifo_empty : 1; - unsigned int output_fifo_full : 1; - unsigned int counters_full : 1; - unsigned int active_sm_q : 5; - unsigned int entry_rdptr_q : 5; - unsigned int cntr_tbl_wrptr_q : 5; - unsigned int SPARE25 : 6; - unsigned int st_cut_mode_q : 2; - unsigned int gs_done_array_q_not_0 : 1; - unsigned int SPARE31 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG15__SI { - struct { - unsigned int cm_busy : 1; - unsigned int counters_busy : 1; - unsigned int output_fifo_empty : 1; - unsigned int output_fifo_full : 1; - unsigned int counters_full : 1; - unsigned int active_sm_q : 5; - unsigned int entry_rdptr_q : 5; - unsigned int cntr_tbl_wrptr_q : 5; - unsigned int SPARE25 : 6; - unsigned int st_cut_mode_q : 2; - unsigned int gs_done_array_q_not_0 : 1; - unsigned int SPARE31 : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG16__CI__VI { - struct { - unsigned int gog_busy : 1; - unsigned int gog_state_q : 3; - unsigned int r0_rtr : 1; - unsigned int r1_rtr : 1; - unsigned int r1_upstream_rtr : 1; - unsigned int r2_vs_tbl_rtr : 1; - unsigned int r2_prim_rtr : 1; - unsigned int r2_indx_rtr : 1; - unsigned int r2_rtr : 1; - unsigned int gog_tm_vs_event_rtr : 1; - unsigned int r3_force_vs_tbl_we_rtr : 1; - unsigned int indx_valid_r2_q : 1; - unsigned int prim_valid_r2_q : 1; - unsigned int valid_r2_q : 1; - unsigned int prim_valid_r1_q : 1; - unsigned int indx_valid_r1_q : 1; - unsigned int valid_r1_q : 1; - unsigned int indx_valid_r0_q : 1; - unsigned int prim_valid_r0_q : 1; - unsigned int valid_r0_q : 1; - unsigned int send_event_q : 1; - unsigned int SPARE24 : 1; - unsigned int vert_seen_since_sopg_r2_q : 1; - unsigned int gog_out_prim_state_sel : 3; - unsigned int multiple_streams_en_r1_q : 1; - unsigned int vs_vert_count_r2_q_not_0 : 1; - unsigned int num_gs_r2_q_not_0 : 1; - unsigned int new_vs_thread_r2 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG16__SI { - struct { - unsigned int gog_busy : 1; - unsigned int gog_state_q : 3; - unsigned int r0_rtr : 1; - unsigned int r1_rtr : 1; - unsigned int r1_upstream_rtr : 1; - unsigned int r2_vs_tbl_rtr : 1; - unsigned int r2_prim_rtr : 1; - unsigned int r2_indx_rtr : 1; - unsigned int r2_rtr : 1; - unsigned int gog_tm_vs_event_rtr : 1; - unsigned int r3_force_vs_tbl_we_rtr : 1; - unsigned int indx_valid_r2_q : 1; - unsigned int prim_valid_r2_q : 1; - unsigned int valid_r2_q : 1; - unsigned int prim_valid_r1_q : 1; - unsigned int indx_valid_r1_q : 1; - unsigned int valid_r1_q : 1; - unsigned int indx_valid_r0_q : 1; - unsigned int prim_valid_r0_q : 1; - unsigned int valid_r0_q : 1; - unsigned int send_event_q : 1; - unsigned int SPARE24 : 2; - unsigned int gog_out_prim_state_sel : 3; - unsigned int multiple_streams_en_r1_q : 1; - unsigned int : 1; - unsigned int num_gs_r2_q_not_0 : 1; - unsigned int new_vs_thread_r2 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG17 { - struct { - unsigned int gog_out_prim_rel_indx2_5_0 : 6; - unsigned int gog_out_prim_rel_indx1_5_0 : 6; - unsigned int gog_out_prim_rel_indx0_5_0 : 6; - unsigned int gog_out_indx_13_0 : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG18__CI__VI { - struct { - unsigned int grp_vr_valid : 1; - unsigned int pipe0_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int vr_grp_read : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int out_vr_indx_read : 1; - unsigned int out_vr_prim_read : 1; - unsigned int indices_to_send_q : 3; - unsigned int valid_indices : 1; - unsigned int last_indx_of_prim : 1; - unsigned int indx0_new_d : 1; - unsigned int indx1_new_d : 1; - unsigned int indx2_new_d : 1; - unsigned int indx2_hit_d : 1; - unsigned int indx1_hit_d : 1; - unsigned int indx0_hit_d : 1; - unsigned int st_vertex_reuse_off_r0_q : 1; - unsigned int last_group_of_instance_r0_q : 1; - unsigned int null_primitive_r0_q : 1; - unsigned int eop_r0_q : 1; - unsigned int eject_vtx_vect_r1_d : 1; - unsigned int sub_prim_type_r0_q : 3; - unsigned int gs_scenario_a_r0_q : 1; - unsigned int gs_scenario_b_r0_q : 1; - unsigned int components_valid_r0_q : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG18__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG19__CI__VI { - struct { - unsigned int separate_out_busy_q : 1; - unsigned int separate_out_indx_busy_q : 1; - unsigned int prim_buffer_empty : 1; - unsigned int prim_buffer_full : 1; - unsigned int pa_clips_fifo_busy_q : 1; - unsigned int pa_clipp_fifo_busy_q : 1; - unsigned int VGT_PA_clips_rtr_q : 1; - unsigned int VGT_PA_clipp_rtr_q : 1; - unsigned int spi_vsthread_fifo_busy_q : 1; - unsigned int spi_vsvert_fifo_busy_q : 1; - unsigned int pa_clipv_fifo_busy_q : 1; - unsigned int hold_prim : 1; - unsigned int VGT_SPI_vsthread_rtr_q : 1; - unsigned int VGT_SPI_vsvert_rtr_q : 1; - unsigned int VGT_PA_clipv_rtr_q : 1; - unsigned int new_packet_q : 1; - unsigned int buffered_prim_event : 1; - unsigned int buffered_prim_null_primitive : 1; - unsigned int buffered_prim_eop : 1; - unsigned int buffered_prim_eject_vtx_vect : 1; - unsigned int buffered_prim_type_event : 6; - unsigned int VGT_SE1SPI_vswave_rtr_q : 1; - unsigned int VGT_SE1SPI_vsvert_rtr_q : 1; - unsigned int num_new_unique_rel_indx : 2; - unsigned int null_terminate_vtx_vector : 1; - unsigned int filter_event : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG19__SI { - struct { - unsigned int separate_out_busy : 1; - unsigned int separate_out_indx_busy : 1; - unsigned int prim_buffer_empty : 1; - unsigned int prim_buffer_full : 1; - unsigned int pa_clips_fifo_busy : 1; - unsigned int pa_clipp_fifo_busy : 1; - unsigned int VGT_PA_clips_rtr_q : 1; - unsigned int VGT_PA_clipp_rtr_q : 1; - unsigned int spi_vsthread_fifo_busy : 1; - unsigned int spi_vsvert_fifo_busy : 1; - unsigned int pa_clipv_fifo_busy : 1; - unsigned int hold_prim : 1; - unsigned int VGT_SPI_vsthread_rtr_q : 1; - unsigned int VGT_SPI_vsvert_rtr_q : 1; - unsigned int VGT_PA_clipv_rtr_q : 1; - unsigned int new_packet_q : 1; - unsigned int buffered_prim_event : 1; - unsigned int buffered_prim_null_primitive : 1; - unsigned int buffered_prim_eop : 1; - unsigned int buffered_prim_eject_vtx_vect : 1; - unsigned int buffered_prim_type_event : 6; - unsigned int VGT_SE1SPI_vswave_rtr_q : 1; - unsigned int VGT_SE1SPI_vsvert_rtr_q : 1; - unsigned int num_new_unique_rel_indx : 2; - unsigned int null_terminate_vtx_vector : 1; - unsigned int filter_event : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG20 { - struct { - unsigned int dbg_VGT_SPI_vsthread_sovertexindex : 16; - unsigned int dbg_VGT_SPI_vsthread_sovertexcount_not_0 : 1; - unsigned int SPARE17 : 1; - unsigned int alloc_counter_q : 4; - unsigned int curr_dealloc_distance_q : 7; - unsigned int new_allocate_q : 1; - unsigned int curr_slot_in_vtx_vect_q_not_0 : 1; - unsigned int int_vtx_counter_q_not_0 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG21 { - struct { - unsigned int out_indx_fifo_empty : 1; - unsigned int indx_side_fifo_empty : 1; - unsigned int pipe0_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe2_dr : 1; - unsigned int vsthread_buff_empty : 1; - unsigned int out_indx_fifo_full : 1; - unsigned int indx_side_fifo_full : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int pipe2_rtr : 1; - unsigned int vsthread_buff_full : 1; - unsigned int interfaces_rtr : 1; - unsigned int indx_count_q_not_0 : 1; - unsigned int wait_for_external_eopg_q : 1; - unsigned int full_state_p1_q : 1; - unsigned int indx_side_indx_valid : 1; - unsigned int stateid_p0_q : 3; - unsigned int is_event_p0_q : 1; - unsigned int lshs_dealloc_p1 : 1; - unsigned int stream_id_r2_q : 1; - unsigned int vtx_vect_counter_q_not_0 : 1; - unsigned int buff_full_p1 : 1; - unsigned int strmout_valid_p1 : 1; - unsigned int eotg_r2_q : 1; - unsigned int null_r2_q : 1; - unsigned int p0_dr : 1; - unsigned int p0_rtr : 1; - unsigned int eopg_p0_q : 1; - unsigned int p0_nobp : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG22 { - struct { - unsigned int cm_state16 : 2; - unsigned int cm_state17 : 2; - unsigned int cm_state18 : 2; - unsigned int cm_state19 : 2; - unsigned int cm_state20 : 2; - unsigned int cm_state21 : 2; - unsigned int cm_state22 : 2; - unsigned int cm_state23 : 2; - unsigned int cm_state24 : 2; - unsigned int cm_state25 : 2; - unsigned int cm_state26 : 2; - unsigned int cm_state27 : 2; - unsigned int cm_state28 : 2; - unsigned int cm_state29 : 2; - unsigned int cm_state30 : 2; - unsigned int cm_state31 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG23 { - struct { - unsigned int frmt_busy : 1; - unsigned int rcm_frmt_vert_rtr : 1; - unsigned int rcm_frmt_prim_rtr : 1; - unsigned int prim_r3_rtr : 1; - unsigned int prim_r2_rtr : 1; - unsigned int vert_r3_rtr : 1; - unsigned int vert_r2_rtr : 1; - unsigned int vert_r1_rtr : 1; - unsigned int vert_r0_rtr : 1; - unsigned int prim_fifo_empty : 1; - unsigned int prim_fifo_full : 1; - unsigned int vert_dr_r2_q : 1; - unsigned int prim_dr_r2_q : 1; - unsigned int vert_dr_r1_q : 1; - unsigned int vert_dr_r0_q : 1; - unsigned int new_verts_r2_q : 2; - unsigned int verts_sent_r2_q : 4; - unsigned int prim_state_sel_r2_q : 3; - unsigned int SPARE : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG24 { - struct { - unsigned int avail_es_rb_space_r0_q_23_0 : 24; - unsigned int dependent_st_cut_mode_q : 2; - unsigned int SPARE31 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG25 { - struct { - unsigned int avail_gs_rb_space_r0_q_25_0 : 26; - unsigned int active_sm_r0_q : 4; - unsigned int add_gs_rb_space_r1_q : 1; - unsigned int add_gs_rb_space_r0_q : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG26__CI__VI { - struct { - unsigned int cm_state0 : 2; - unsigned int cm_state1 : 2; - unsigned int cm_state2 : 2; - unsigned int cm_state3 : 2; - unsigned int cm_state4 : 2; - unsigned int cm_state5 : 2; - unsigned int cm_state6 : 2; - unsigned int cm_state7 : 2; - unsigned int cm_state8 : 2; - unsigned int cm_state9 : 2; - unsigned int cm_state10 : 2; - unsigned int cm_state11 : 2; - unsigned int cm_state12 : 2; - unsigned int cm_state13 : 2; - unsigned int cm_state14 : 2; - unsigned int cm_state15 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG26__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG27 { - struct { - unsigned int pipe0_dr : 1; - unsigned int gsc0_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int tm_pt_event_rtr : 1; - unsigned int pipe0_rtr : 1; - unsigned int gsc0_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int last_indx_of_prim_p1_q : 1; - unsigned int indices_to_send_p0_q : 2; - unsigned int event_flag_p1_q : 1; - unsigned int eop_p1_q : 1; - unsigned int gs_out_prim_type_p0_q : 2; - unsigned int gsc_null_primitive_p0_q : 1; - unsigned int gsc_eop_p0_q : 1; - unsigned int gsc_2cycle_output : 1; - unsigned int gsc_2nd_cycle_p0_q : 1; - unsigned int last_indx_of_vsprim : 1; - unsigned int first_vsprim_of_gsprim_p0_q : 1; - unsigned int gsc_indx_count_p0_q : 11; - unsigned int last_vsprim_of_gsprim : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG28 { - struct { - unsigned int con_state_q : 4; - unsigned int second_cycle_q : 1; - unsigned int process_tri_middle_p0_q : 1; - unsigned int process_tri_1st_2nd_half_p0_q : 1; - unsigned int process_tri_center_poly_p0_q : 1; - unsigned int pipe0_patch_dr : 1; - unsigned int pipe0_edge_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe0_patch_rtr : 1; - unsigned int pipe0_edge_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int outer_parity_p0_q : 1; - unsigned int parallel_parity_p0_q : 1; - unsigned int first_ring_of_patch_p0_q : 1; - unsigned int last_ring_of_patch_p0_q : 1; - unsigned int last_edge_of_outer_ring_p0_q : 1; - unsigned int last_point_of_outer_ring_p1 : 1; - unsigned int last_point_of_inner_ring_p1 : 1; - unsigned int outer_edge_tf_eq_one_p0_q : 1; - unsigned int advance_outer_point_p1 : 1; - unsigned int advance_inner_point_p1 : 1; - unsigned int next_ring_is_rect_p0_q : 1; - unsigned int pipe1_outer1_rtr : 1; - unsigned int pipe1_outer2_rtr : 1; - unsigned int pipe1_inner1_rtr : 1; - unsigned int pipe1_inner2_rtr : 1; - unsigned int pipe1_patch_rtr : 1; - unsigned int pipe1_edge_rtr : 1; - unsigned int use_stored_inner_q_ring2 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG29 { - struct { - unsigned int con_state_q : 4; - unsigned int second_cycle_q : 1; - unsigned int process_tri_middle_p0_q : 1; - unsigned int process_tri_1st_2nd_half_p0_q : 1; - unsigned int process_tri_center_poly_p0_q : 1; - unsigned int pipe0_patch_dr : 1; - unsigned int pipe0_edge_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe0_patch_rtr : 1; - unsigned int pipe0_edge_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int outer_parity_p0_q : 1; - unsigned int parallel_parity_p0_q : 1; - unsigned int first_ring_of_patch_p0_q : 1; - unsigned int last_ring_of_patch_p0_q : 1; - unsigned int last_edge_of_outer_ring_p0_q : 1; - unsigned int last_point_of_outer_ring_p1 : 1; - unsigned int last_point_of_inner_ring_p1 : 1; - unsigned int outer_edge_tf_eq_one_p0_q : 1; - unsigned int advance_outer_point_p1 : 1; - unsigned int advance_inner_point_p1 : 1; - unsigned int next_ring_is_rect_p0_q : 1; - unsigned int pipe1_outer1_rtr : 1; - unsigned int pipe1_outer2_rtr : 1; - unsigned int pipe1_inner1_rtr : 1; - unsigned int pipe1_inner2_rtr : 1; - unsigned int pipe1_patch_rtr : 1; - unsigned int pipe1_edge_rtr : 1; - unsigned int use_stored_inner_q_ring3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG2__CI__VI { - struct { - unsigned int hs_grp_busy : 1; - unsigned int hs_noif_busy : 1; - unsigned int tfmmIsBusy : 1; - unsigned int lsVertIfBusy_0 : 1; - unsigned int te11_hs_tess_input_rtr : 1; - unsigned int lsWaveIfBusy_0 : 1; - unsigned int hs_te11_tess_input_rts : 1; - unsigned int grpModBusy : 1; - unsigned int lsVertFifoEmpty : 1; - unsigned int lsWaveFifoEmpty : 1; - unsigned int hsVertFifoEmpty : 1; - unsigned int hsWaveFifoEmpty : 1; - unsigned int hsInputFifoEmpty : 1; - unsigned int hsTifFifoEmpty : 1; - unsigned int lsVertFifoFull : 1; - unsigned int lsWaveFifoFull : 1; - unsigned int hsVertFifoFull : 1; - unsigned int hsWaveFifoFull : 1; - unsigned int hsInputFifoFull : 1; - unsigned int hsTifFifoFull : 1; - unsigned int p0_rtr : 1; - unsigned int p1_rtr : 1; - unsigned int p0_dr : 1; - unsigned int p1_dr : 1; - unsigned int p0_rts : 1; - unsigned int p1_rts : 1; - unsigned int ls_sh_id : 1; - unsigned int lsFwaveFlag : 1; - unsigned int lsWaveSendFlush : 1; - unsigned int SPARE : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG2__SI { - struct { - unsigned int SPARE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG30__CI { - struct { - unsigned int pipe0_dr : 1; - unsigned int pipe0_tf_dr : 1; - unsigned int pipe2_dr : 1; - unsigned int event_or_null_p0_q : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int pipe1_tf_rtr : 1; - unsigned int pipe2_rtr : 1; - unsigned int ttp_patch_fifo_full : 1; - unsigned int ttp_patch_fifo_empty : 1; - unsigned int ttp_tf0_fifo_empty : 1; - unsigned int ttp_tf1_fifo_empty : 1; - unsigned int ttp_tf2_fifo_empty : 1; - unsigned int ttp_tf3_fifo_empty : 1; - unsigned int ttp_tf4_fifo_empty : 1; - unsigned int ttp_tf5_fifo_empty : 1; - unsigned int tf_fetch_state_q : 3; - unsigned int last_tf_of_tg : 1; - unsigned int tf_pointer_p0_q : 4; - unsigned int dynamic_hs_p0_q : 1; - unsigned int first_fetch_of_tg_p0_q : 1; - unsigned int first_data_ret_of_req_p0_q : 1; - unsigned int first_data_chunk_invalid_p0_q : 1; - unsigned int tf_xfer_count_p2_q : 2; - unsigned int pipe4_dr : 1; - unsigned int pipe4_rtr : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG30__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG31__CI__VI { - struct { - unsigned int pipe0_dr : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_outer_dr : 1; - unsigned int pipe1_inner_dr : 1; - unsigned int pipe2_outer_dr : 1; - unsigned int pipe2_inner_dr : 1; - unsigned int pipe3_outer_dr : 1; - unsigned int pipe3_inner_dr : 1; - unsigned int pipe4_outer_dr : 1; - unsigned int pipe4_inner_dr : 1; - unsigned int pipe5_outer_dr : 1; - unsigned int pipe5_inner_dr : 1; - unsigned int pipe2_outer_rtr : 1; - unsigned int pipe2_inner_rtr : 1; - unsigned int pipe3_outer_rtr : 1; - unsigned int pipe3_inner_rtr : 1; - unsigned int pipe4_outer_rtr : 1; - unsigned int pipe4_inner_rtr : 1; - unsigned int pipe5_outer_rtr : 1; - unsigned int pipe5_inner_rtr : 1; - unsigned int pg_con_outer_point1_rts : 1; - unsigned int pg_con_outer_point2_rts : 1; - unsigned int pg_con_inner_point1_rts : 1; - unsigned int pg_con_inner_point2_rts : 1; - unsigned int pg_patch_fifo_empty : 1; - unsigned int pg_edge_fifo_empty : 1; - unsigned int pg_inner3_perp_fifo_empty : 1; - unsigned int pg_patch_fifo_full : 1; - unsigned int pg_edge_fifo_full : 1; - unsigned int pg_inner_perp_fifo_full : 1; - unsigned int outer_ring_done_q : 1; - unsigned int inner_ring_done_q : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG31__SI { - struct { - unsigned int : 12; - unsigned int : 6; - unsigned int : 8; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG32__CI__VI { - struct { - unsigned int first_ring_of_patch : 1; - unsigned int last_ring_of_patch : 1; - unsigned int last_edge_of_outer_ring : 1; - unsigned int last_point_of_outer_edge : 1; - unsigned int last_edge_of_inner_ring : 1; - unsigned int last_point_of_inner_edge : 1; - unsigned int last_patch_of_tg_p0_q : 1; - unsigned int event_null_special_p0_q : 1; - unsigned int event_flag_p5_q : 1; - unsigned int first_point_of_patch_p5_q : 1; - unsigned int first_point_of_edge_p5_q : 1; - unsigned int last_patch_of_tg_p5_q : 1; - unsigned int tess_topology_p5_q : 2; - unsigned int pipe5_inner3_rtr : 1; - unsigned int pipe5_inner2_rtr : 1; - unsigned int pg_edge_fifo3_full : 1; - unsigned int pg_edge_fifo2_full : 1; - unsigned int pg_inner3_point_fifo_full : 1; - unsigned int pg_outer3_point_fifo_full : 1; - unsigned int pg_inner2_point_fifo_full : 1; - unsigned int pg_outer2_point_fifo_full : 1; - unsigned int pg_inner_point_fifo_full : 1; - unsigned int pg_outer_point_fifo_full : 1; - unsigned int inner2_fifos_rtr : 1; - unsigned int inner_fifos_rtr : 1; - unsigned int outer_fifos_rtr : 1; - unsigned int fifos_rtr : 1; - unsigned int SPARE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG32__SI { - struct { - unsigned int : 8; - unsigned int : 16; - unsigned int : 5; - unsigned int : 1; - unsigned int : 1; - unsigned int SPARE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG33__CI__VI { - struct { - unsigned int pipe0_patch_dr : 1; - unsigned int ring3_pipe1_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe2_dr : 1; - unsigned int pipe0_patch_rtr : 1; - unsigned int ring2_pipe1_dr : 1; - unsigned int ring1_pipe1_dr : 1; - unsigned int pipe2_rtr : 1; - unsigned int pipe3_dr : 1; - unsigned int pipe3_rtr : 1; - unsigned int ring2_in_sync_q : 1; - unsigned int ring1_in_sync_q : 1; - unsigned int pipe1_patch_rtr : 1; - unsigned int ring3_in_sync_q : 1; - unsigned int tm_te11_event_rtr : 1; - unsigned int first_prim_of_patch_q : 1; - unsigned int con_prim_fifo_full : 1; - unsigned int con_vert_fifo_full : 1; - unsigned int con_prim_fifo_empty : 1; - unsigned int con_vert_fifo_empty : 1; - unsigned int last_patch_of_tg_p0_q : 1; - unsigned int ring3_valid_p2 : 1; - unsigned int ring2_valid_p2 : 1; - unsigned int ring1_valid_p2 : 1; - unsigned int tess_type_p0_q : 2; - unsigned int tess_topology_p0_q : 2; - unsigned int te11_out_vert_gs_en : 1; - unsigned int con_ring3_busy : 1; - unsigned int con_ring2_busy : 1; - unsigned int con_ring1_busy : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG33__SI { - struct { - unsigned int : 3; - unsigned int : 5; - unsigned int : 3; - unsigned int : 5; - unsigned int : 3; - unsigned int : 5; - unsigned int : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG34__CI__VI { - struct { - unsigned int con_state_q : 4; - unsigned int second_cycle_q : 1; - unsigned int process_tri_middle_p0_q : 1; - unsigned int process_tri_1st_2nd_half_p0_q : 1; - unsigned int process_tri_center_poly_p0_q : 1; - unsigned int pipe0_patch_dr : 1; - unsigned int pipe0_edge_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe0_patch_rtr : 1; - unsigned int pipe0_edge_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int outer_parity_p0_q : 1; - unsigned int parallel_parity_p0_q : 1; - unsigned int first_ring_of_patch_p0_q : 1; - unsigned int last_ring_of_patch_p0_q : 1; - unsigned int last_edge_of_outer_ring_p0_q : 1; - unsigned int last_point_of_outer_ring_p1 : 1; - unsigned int last_point_of_inner_ring_p1 : 1; - unsigned int outer_edge_tf_eq_one_p0_q : 1; - unsigned int advance_outer_point_p1 : 1; - unsigned int advance_inner_point_p1 : 1; - unsigned int next_ring_is_rect_p0_q : 1; - unsigned int pipe1_outer1_rtr : 1; - unsigned int pipe1_outer2_rtr : 1; - unsigned int pipe1_inner1_rtr : 1; - unsigned int pipe1_inner2_rtr : 1; - unsigned int pipe1_patch_rtr : 1; - unsigned int pipe1_edge_rtr : 1; - unsigned int use_stored_inner_q_ring1 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG34__SI { - struct { - unsigned int : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG35__CI { - struct { - unsigned int pipe0_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int tfreq_tg_fifo_empty : 1; - unsigned int tfreq_tg_fifo_full : 1; - unsigned int tf_data_fifo_busy_q : 1; - unsigned int tf_data_fifo_rtr_q : 1; - unsigned int tf_skid_fifo_empty : 1; - unsigned int tf_skid_fifo_full : 1; - unsigned int vgt_tc_rdreq_rtr_q : 1; - unsigned int last_req_of_tg_p2 : 1; - unsigned int spi_vgt_hs_done_cnt_q : 6; - unsigned int event_flag_p1_q : 1; - unsigned int null_flag_p1_q : 1; - unsigned int tf_data_fifo_cnt_q : 7; - unsigned int second_tf_ret_data_q : 1; - unsigned int first_req_of_tg_p1_q : 1; - unsigned int VGT_TC_rdreq_send_out : 1; - unsigned int VGT_TC_rdnfo_stall_out : 1; - unsigned int TC_VGT_rdret_data_in : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG35__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 11; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG36__SI { - struct { - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG36__VI { - struct { - unsigned int VGT_PA_clipp_eop : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG3__CI__VI { - struct { - unsigned int lsTgRelInd : 12; - unsigned int lsWaveRelInd : 6; - unsigned int lsPatchCnt : 8; - unsigned int hsWaveRelInd : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG3__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG4__CI__VI { - struct { - unsigned int hsPatchCnt : 8; - unsigned int hsPrimId_15_0 : 16; - unsigned int hsCpCnt : 5; - unsigned int hsWaveSendFlush : 1; - unsigned int hsFwaveFlag : 1; - unsigned int SPARE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG4__SI { - struct { - unsigned int SPARE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG5__CI__VI { - struct { - unsigned int SPARE4 : 3; - unsigned int hsWaveCreditCnt_0 : 5; - unsigned int SPARE3 : 3; - unsigned int hsVertCreditCnt_0 : 5; - unsigned int SPARE2 : 3; - unsigned int lsWaveCreditCnt_0 : 5; - unsigned int SPARE1 : 3; - unsigned int lsVertCreditCnt_0 : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG5__SI { - struct { - unsigned int SPARE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG6__CI__VI { - struct { - unsigned int debug_BASE : 16; - unsigned int debug_SIZE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG6__SI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG7__CI__VI { - struct { - unsigned int debug_tfmmFifoEmpty : 1; - unsigned int debug_tfmmFifoFull : 1; - unsigned int hs_pipe0_dr : 1; - unsigned int hs_pipe0_rtr : 1; - unsigned int hs_pipe1_rtr : 1; - unsigned int SPARE : 11; - unsigned int TF_addr : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG7__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG8__CI__VI { - struct { - unsigned int rcm_busy_q : 1; - unsigned int rcm_noif_busy_q : 1; - unsigned int r1_inst_rtr : 1; - unsigned int spi_gsprim_fifo_busy_q : 1; - unsigned int spi_esvert_fifo_busy_q : 1; - unsigned int gs_tbl_valid_r3_q : 1; - unsigned int valid_r0_q : 1; - unsigned int valid_r1_q : 1; - unsigned int valid_r2 : 1; - unsigned int valid_r2_q : 1; - unsigned int r0_rtr : 1; - unsigned int r1_rtr : 1; - unsigned int r2_indx_rtr : 1; - unsigned int r2_rtr : 1; - unsigned int es_gs_rtr : 1; - unsigned int gs_event_fifo_rtr : 1; - unsigned int tm_rcm_gs_event_rtr : 1; - unsigned int gs_tbl_r3_rtr : 1; - unsigned int prim_skid_fifo_empty : 1; - unsigned int VGT_SPI_gsprim_rtr_q : 1; - unsigned int tm_rcm_gs_tbl_rtr : 1; - unsigned int tm_rcm_es_tbl_rtr : 1; - unsigned int VGT_SPI_esvert_rtr_q : 1; - unsigned int r2_no_bp_rtr : 1; - unsigned int hold_for_es_flush : 1; - unsigned int gs_event_fifo_empty : 1; - unsigned int gsprim_buff_empty_q : 1; - unsigned int gsprim_buff_full_q : 1; - unsigned int te_prim_fifo_empty : 1; - unsigned int te_prim_fifo_full : 1; - unsigned int te_vert_fifo_empty : 1; - unsigned int te_vert_fifo_full : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG8__SI { - struct { - unsigned int rcm_busy : 1; - unsigned int rcm_noif_busy : 1; - unsigned int r1_inst_rtr : 1; - unsigned int spi_gsprim_fifo_busy_q : 1; - unsigned int spi_esvert_fifo_busy_q : 1; - unsigned int gs_tbl_valid_r3_q : 1; - unsigned int valid_r0_q : 1; - unsigned int valid_r1_q : 1; - unsigned int valid_r2 : 1; - unsigned int valid_r2_q : 1; - unsigned int r0_rtr : 1; - unsigned int r1_rtr : 1; - unsigned int r2_indx_rtr : 1; - unsigned int r2_rtr : 1; - unsigned int es_gs_rtr : 1; - unsigned int gs_event_fifo_rtr : 1; - unsigned int tm_rcm_gs_event_rtr : 1; - unsigned int gs_tbl_r3_rtr : 1; - unsigned int prim_skid_fifo_empty : 1; - unsigned int VGT_SPI_gsprim_rtr_q : 1; - unsigned int tm_rcm_gs_tbl_rtr : 1; - unsigned int tm_rcm_es_tbl_rtr : 1; - unsigned int VGT_SPI_esvert_rtr_q : 1; - unsigned int r2_no_bp_rtr : 1; - unsigned int hold_for_es_flush : 1; - unsigned int gs_event_fifo_empty : 1; - unsigned int gsprim_buff_empty_q : 1; - unsigned int gsprim_buff_full_q : 1; - unsigned int te_prim_fifo_empty : 1; - unsigned int te_prim_fifo_full : 1; - unsigned int te_vert_fifo_empty : 1; - unsigned int te_vert_fifo_full : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DEBUG_REG9 { - struct { - unsigned int indices_to_send_r2_q : 2; - unsigned int valid_indices_r3 : 1; - unsigned int gs_eov_r3 : 1; - unsigned int eop_indx_r3 : 1; - unsigned int eop_prim_r3 : 1; - unsigned int es_eov_r3 : 1; - unsigned int es_tbl_state_r3_q_0 : 1; - unsigned int pending_es_send_r3_q : 1; - unsigned int pending_es_flush_r3 : 1; - unsigned int gs_tbl_num_es_per_gs_r3_q_not_0 : 1; - unsigned int gs_tbl_prim_cnt_r3_q : 7; - unsigned int gs_tbl_eop_r3_q : 1; - unsigned int gs_tbl_state_r3_q : 3; - unsigned int gs_pending_state_r3_q : 1; - unsigned int invalidate_rb_roll_over_q : 1; - unsigned int gs_instancing_state_q : 1; - unsigned int es_per_gs_vert_cnt_r3_q_not_0 : 1; - unsigned int gs_prim_per_es_ctr_r3_q_not_0 : 1; - unsigned int pre_r0_rtr : 1; - unsigned int valid_r3_q : 1; - unsigned int valid_pre_r0_q : 1; - unsigned int SPARE0 : 1; - unsigned int off_chip_hs_r2_q : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_BASE { - struct { - unsigned int BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_BASE_HI { - struct { - unsigned int BASE_ADDR : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_CONTROL__CI__VI { - struct { - unsigned int PRIMGROUP_SIZE : 16; - unsigned int : 1; - unsigned int IA_SWITCH_ON_EOP : 1; - unsigned int : 2; - unsigned int WD_SWITCH_ON_EOP : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_DATA_FIFO_DEPTH { - struct { - unsigned int DMA_DATA_FIFO_DEPTH : 9; - unsigned int DMA2DRAW_FIFO_DEPTH__VI : 10; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_INDEX_TYPE__SI__CI { - struct { - unsigned int INDEX_TYPE : 2; - unsigned int SWAP_MODE : 2; - unsigned int BUF_TYPE__CI : 2; - unsigned int RDREQ_POLICY__CI : 2; - unsigned int ATC__CI : 1; - unsigned int NOT_EOP__CI : 1; - unsigned int REQ_PATH__CI : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_INDEX_TYPE__VI { - struct { - unsigned int INDEX_TYPE : 2; - unsigned int SWAP_MODE : 2; - unsigned int BUF_TYPE : 2; - unsigned int RDREQ_POLICY : 1; - unsigned int : 2; - unsigned int NOT_EOP : 1; - unsigned int REQ_PATH : 1; - unsigned int MTYPE : 2; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_LS_HS_CONFIG__CI__VI { - struct { - unsigned int : 8; - unsigned int HS_NUM_INPUT_CP : 6; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_MAX_SIZE { - struct { - unsigned int MAX_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_NUM_INSTANCES { - struct { - unsigned int NUM_INSTANCES : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_PRIMITIVE_TYPE__CI__VI { - struct { - unsigned int PRIM_TYPE : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_REQ_FIFO_DEPTH { - struct { - unsigned int DMA_REQ_FIFO_DEPTH : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DMA_SIZE { - struct { - unsigned int NUM_INDICES : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DRAW_INITIATOR { - struct { - unsigned int SOURCE_SELECT : 2; - unsigned int MAJOR_MODE : 2; - unsigned int SPRITE_EN_R6XX : 1; - unsigned int NOT_EOP : 1; - unsigned int USE_OPAQUE : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DRAW_INIT_FIFO_DEPTH { - struct { - unsigned int DRAW_INIT_FIFO_DEPTH : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_ENHANCE { - struct { - unsigned int MISC : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_ESGS_RING_ITEMSIZE { - struct { - unsigned int ITEMSIZE : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_ESGS_RING_SIZE { - struct { - unsigned int MEM_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_ES_PER_GS { - struct { - unsigned int ES_PER_GS : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_EVENT_ADDRESS_REG { - struct { - unsigned int ADDRESS_LOW : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_EVENT_INITIATOR { - struct { - unsigned int EVENT_TYPE : 6; - unsigned int : 12; - unsigned int ADDRESS_HI : 9; - unsigned int EXTENDED_EVENT : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_FIFO_DEPTHS { - struct { - unsigned int VS_DEALLOC_TBL_DEPTH : 7; - unsigned int : 1; - unsigned int CLIPP_FIFO_DEPTH : 14; - unsigned int HSINPUT_FIFO_DEPTH__VI : 6; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GROUP_DECR { - struct { - unsigned int DECR : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GROUP_FIRST_DECR { - struct { - unsigned int FIRST_DECR : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GROUP_PRIM_TYPE { - struct { - unsigned int PRIM_TYPE : 5; - unsigned int : 9; - unsigned int RETAIN_ORDER : 1; - unsigned int RETAIN_QUADS : 1; - unsigned int PRIM_ORDER : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GROUP_VECT_0_CNTL { - struct { - unsigned int COMP_X_EN : 1; - unsigned int COMP_Y_EN : 1; - unsigned int COMP_Z_EN : 1; - unsigned int COMP_W_EN : 1; - unsigned int : 4; - unsigned int STRIDE : 8; - unsigned int SHIFT : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GROUP_VECT_0_FMT_CNTL { - struct { - unsigned int X_CONV : 4; - unsigned int X_OFFSET : 4; - unsigned int Y_CONV : 4; - unsigned int Y_OFFSET : 4; - unsigned int Z_CONV : 4; - unsigned int Z_OFFSET : 4; - unsigned int W_CONV : 4; - unsigned int W_OFFSET : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GROUP_VECT_1_CNTL { - struct { - unsigned int COMP_X_EN : 1; - unsigned int COMP_Y_EN : 1; - unsigned int COMP_Z_EN : 1; - unsigned int COMP_W_EN : 1; - unsigned int : 4; - unsigned int STRIDE : 8; - unsigned int SHIFT : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GROUP_VECT_1_FMT_CNTL { - struct { - unsigned int X_CONV : 4; - unsigned int X_OFFSET : 4; - unsigned int Y_CONV : 4; - unsigned int Y_OFFSET : 4; - unsigned int Z_CONV : 4; - unsigned int Z_OFFSET : 4; - unsigned int W_CONV : 4; - unsigned int W_OFFSET : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GSVS_RING_ITEMSIZE { - struct { - unsigned int ITEMSIZE : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GSVS_RING_OFFSET_1 { - struct { - unsigned int OFFSET : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GSVS_RING_OFFSET_2 { - struct { - unsigned int OFFSET : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GSVS_RING_OFFSET_3 { - struct { - unsigned int OFFSET : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GSVS_RING_SIZE { - struct { - unsigned int MEM_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_INSTANCE_CNT { - struct { - unsigned int ENABLE : 1; - unsigned int : 1; - unsigned int CNT : 7; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_MAX_VERT_OUT { - struct { - unsigned int MAX_VERT_OUT : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_MODE { - struct { - unsigned int MODE : 3; - unsigned int RESERVED_0__VI : 1; - unsigned int CUT_MODE : 2; - unsigned int RESERVED_1__VI : 5; - unsigned int GS_C_PACK_EN : 1; - unsigned int RESERVED_2__VI : 1; - unsigned int ES_PASSTHRU : 1; - unsigned int COMPUTE_MODE : 1; - unsigned int FAST_COMPUTE_MODE : 1; - unsigned int ELEMENT_INFO_EN : 1; - unsigned int PARTIAL_THD_AT_EOI : 1; - unsigned int SUPPRESS_CUTS : 1; - unsigned int ES_WRITE_OPTIMIZE : 1; - unsigned int GS_WRITE_OPTIMIZE : 1; - unsigned int ONCHIP__CI__VI : 2; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_ONCHIP_CNTL__CI__VI { - struct { - unsigned int ES_VERTS_PER_SUBGRP : 11; - unsigned int GS_PRIMS_PER_SUBGRP : 11; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_OUT_PRIM_TYPE { - struct { - unsigned int OUTPRIM_TYPE : 6; - unsigned int : 2; - unsigned int OUTPRIM_TYPE_1 : 6; - unsigned int : 2; - unsigned int OUTPRIM_TYPE_2 : 6; - unsigned int OUTPRIM_TYPE_3 : 6; - unsigned int : 3; - unsigned int UNIQUE_TYPE_PER_STREAM : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_PER_ES { - struct { - unsigned int GS_PER_ES : 11; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_PER_VS { - struct { - unsigned int GS_PER_VS : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_VERTEX_REUSE { - struct { - unsigned int VERT_REUSE : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_VERT_ITEMSIZE { - struct { - unsigned int ITEMSIZE : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_VERT_ITEMSIZE_1 { - struct { - unsigned int ITEMSIZE : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_VERT_ITEMSIZE_2 { - struct { - unsigned int ITEMSIZE : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_GS_VERT_ITEMSIZE_3 { - struct { - unsigned int ITEMSIZE : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_HOS_CNTL { - struct { - unsigned int TESS_MODE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_HOS_MAX_TESS_LEVEL { - struct { - unsigned int MAX_TESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_HOS_MIN_TESS_LEVEL { - struct { - unsigned int MIN_TESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_HOS_REUSE_DEPTH { - struct { - unsigned int REUSE_DEPTH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_HS_OFFCHIP_PARAM { - struct { - unsigned int OFFCHIP_BUFFERING : 9; - unsigned int OFFCHIP_GRANULARITY__CI__VI : 2; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_IMMED_DATA { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_INDEX_TYPE { - struct { - unsigned int INDEX_TYPE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_INDX_OFFSET { - struct { - unsigned int INDX_OFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_INSTANCE_STEP_RATE_0 { - struct { - unsigned int STEP_RATE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_INSTANCE_STEP_RATE_1 { - struct { - unsigned int STEP_RATE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_LAST_COPY_STATE { - struct { - unsigned int SRC_STATE_ID : 3; - unsigned int : 13; - unsigned int DST_STATE_ID : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_LS_HS_CONFIG { - struct { - unsigned int NUM_PATCHES : 8; - unsigned int HS_NUM_INPUT_CP : 6; - unsigned int HS_NUM_OUTPUT_CP : 6; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_MAX_VTX_INDX { - struct { - unsigned int MAX_INDX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_MC_LAT_CNTL { - struct { - unsigned int MC_TIME_STAMP_RES : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_MIN_VTX_INDX { - struct { - unsigned int MIN_INDX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_MULTI_PRIM_IB_RESET_EN { - struct { - unsigned int RESET_EN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_MULTI_PRIM_IB_RESET_INDX { - struct { - unsigned int RESET_INDX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_NUM_INDICES { - struct { - unsigned int NUM_INDICES : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_NUM_INSTANCES { - struct { - unsigned int NUM_INSTANCES : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_OUTPUT_PATH_CNTL { - struct { - unsigned int PATH_SELECT : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_OUT_DEALLOC_CNTL { - struct { - unsigned int DEALLOC_DIST : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER0_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER0_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER0_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE3 : 4; - unsigned int PERF_MODE2 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER0_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1 : 10; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER0_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER1_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER1_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER1_SELECT1__CI__VI { - struct { - unsigned int PERF_SEL2 : 10; - unsigned int PERF_SEL3 : 10; - unsigned int : 4; - unsigned int PERF_MODE3 : 4; - unsigned int PERF_MODE2 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER1_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 10; - unsigned int PERF_SEL1 : 10; - unsigned int CNTR_MODE : 4; - unsigned int PERF_MODE1 : 4; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER1_SELECT__SI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER2_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER2_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER2_SELECT { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER3_HI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER3_LO { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER3_SELECT { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PERFCOUNTER_SEID_MASK { - struct { - unsigned int PERF_SEID_IGNORE_MASK : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PRIMITIVEID_EN { - struct { - unsigned int PRIMITIVEID_EN : 1; - unsigned int DISABLE_RESET_ON_EOI : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PRIMITIVEID_RESET { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_PRIMITIVE_TYPE { - struct { - unsigned int PRIM_TYPE : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_RESET_DEBUG__CI__VI { - struct { - unsigned int GS_DISABLE : 1; - unsigned int TESS_DISABLE : 1; - unsigned int WD_DISABLE : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_REUSE_OFF { - struct { - unsigned int REUSE_OFF : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_SHADER_STAGES_EN { - struct { - unsigned int LS_EN : 2; - unsigned int HS_EN : 1; - unsigned int ES_EN : 2; - unsigned int GS_EN : 1; - unsigned int VS_EN : 2; - unsigned int DYNAMIC_HS : 1; - unsigned int DISPATCH_DRAW_EN__VI : 1; - unsigned int DIS_DEALLOC_ACCUM_0__VI : 1; - unsigned int DIS_DEALLOC_ACCUM_1__VI : 1; - unsigned int VS_WAVE_ID_EN__VI : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_CONFIG { - struct { - unsigned int STREAM_0_BUFFER_EN : 4; - unsigned int STREAM_1_BUFFER_EN : 4; - unsigned int STREAM_2_BUFFER_EN : 4; - unsigned int STREAM_3_BUFFER_EN : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_FILLED_SIZE_0 { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_FILLED_SIZE_1 { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_FILLED_SIZE_2 { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_FILLED_SIZE_3 { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_OFFSET_0 { - struct { - unsigned int OFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_OFFSET_1 { - struct { - unsigned int OFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_OFFSET_2 { - struct { - unsigned int OFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_OFFSET_3 { - struct { - unsigned int OFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_SIZE_0 { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_SIZE_1 { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_SIZE_2 { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_BUFFER_SIZE_3 { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_CONFIG { - struct { - unsigned int STREAMOUT_0_EN : 1; - unsigned int STREAMOUT_1_EN : 1; - unsigned int STREAMOUT_2_EN : 1; - unsigned int STREAMOUT_3_EN : 1; - unsigned int RAST_STREAM : 3; - unsigned int : 1; - unsigned int RAST_STREAM_MASK : 4; - unsigned int : 19; - unsigned int USE_RAST_STREAM_MASK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_DELAY__CI__VI { - struct { - unsigned int SKIP_DELAY : 8; - unsigned int SE0_WD_DELAY : 3; - unsigned int SE1_WD_DELAY : 3; - unsigned int SE2_WD_DELAY : 3; - unsigned int SE3_WD_DELAY : 3; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE { - struct { - unsigned int SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_DRAW_OPAQUE_OFFSET { - struct { - unsigned int OFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE { - struct { - unsigned int VERTEX_STRIDE : 9; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_VTX_STRIDE_0 { - struct { - unsigned int STRIDE : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_VTX_STRIDE_1 { - struct { - unsigned int STRIDE : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_VTX_STRIDE_2 { - struct { - unsigned int STRIDE : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_STRMOUT_VTX_STRIDE_3 { - struct { - unsigned int STRIDE : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_SYS_CONFIG { - struct { - unsigned int DUAL_CORE_EN : 1; - unsigned int MAX_LS_HS_THDGRP : 6; - unsigned int ADC_EVENT_FILTER_DISABLE : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_TF_MEMORY_BASE { - struct { - unsigned int BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_TF_PARAM { - struct { - unsigned int TYPE : 2; - unsigned int PARTITIONING : 3; - unsigned int TOPOLOGY : 3; - unsigned int : 1; - unsigned int DEPRECATED : 1; - unsigned int NUM_DS_WAVES_PER_SIMD : 4; - unsigned int DISABLE_DONUTS : 1; - unsigned int RDREQ_POLICY__CI__VI : 2; - unsigned int DISTRIBUTION_MODE__VI : 2; - unsigned int MTYPE__VI : 2; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_TF_RING_SIZE { - struct { - unsigned int SIZE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_VERTEX_REUSE_BLOCK_CNTL { - struct { - unsigned int VTX_REUSE_DEPTH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_VS_MAX_WAVE_ID__CI__VI { - struct { - unsigned int MAX_WAVE_ID : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_VTX_CNT_EN { - struct { - unsigned int VTX_CNT_EN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_VTX_VECT_EJECT_REG { - struct { - unsigned int PRIM_COUNT : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VIEWPORT_SIZE__SI__VI { - struct { - unsigned int VIEWPORT_HEIGHT : 14; - unsigned int : 2; - unsigned int VIEWPORT_WIDTH : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VIEWPORT_START__SI__VI { - struct { - unsigned int VIEWPORT_Y_START : 14; - unsigned int : 2; - unsigned int VIEWPORT_X_START : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VLINE_START_END__SI { - struct { - unsigned int : 14; - unsigned int : 2; - unsigned int : 14; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VLINE_STATUS__SI { - struct { - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT0_CNTL__SI__CI { - struct { - unsigned int ENABLE_CONTEXT : 1; - unsigned int PAGE_TABLE_DEPTH : 2; - unsigned int RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int RANGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int : 1; - unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int PAGE_TABLE_BLOCK_SIZE : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT0_CNTL__VI { - struct { - unsigned int ENABLE_CONTEXT : 1; - unsigned int PAGE_TABLE_DEPTH : 2; - unsigned int RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int RANGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int : 1; - unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int PAGE_TABLE_BLOCK_SIZE : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT0_CNTL2 { - struct { - unsigned int CLEAR_PROTECTION_FAULT_STATUS_ADDR : 1; - unsigned int ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT : 1; - unsigned int ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT : 1; - unsigned int ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES : 1; - unsigned int WAIT_FOR_IDLE_WHEN_INVALIDATE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT0_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT0_PAGE_TABLE_END_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT0_PAGE_TABLE_START_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT0_PROTECTION_FAULT_ADDR { - struct { - unsigned int LOGICAL_PAGE_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR { - struct { - unsigned int PHYSICAL_PAGE_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__CI__VI { - struct { - unsigned int NAME : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT0_PROTECTION_FAULT_STATUS { - struct { - unsigned int PROTECTIONS : 8; - unsigned int : 4; - unsigned int MEMORY_CLIENT_ID : 9; - unsigned int : 3; - unsigned int MEMORY_CLIENT_RW : 1; - unsigned int VMID : 4; - unsigned int ATOMIC__VI : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT10_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT11_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT12_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT13_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT14_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT15_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT1_CNTL__SI__CI { - struct { - unsigned int ENABLE_CONTEXT : 1; - unsigned int PAGE_TABLE_DEPTH : 2; - unsigned int RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int RANGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int : 1; - unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int PAGE_TABLE_BLOCK_SIZE : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT1_CNTL__VI { - struct { - unsigned int ENABLE_CONTEXT : 1; - unsigned int PAGE_TABLE_DEPTH : 2; - unsigned int RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int RANGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int : 1; - unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int PDE0_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int VALID_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int READ_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int WRITE_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT : 1; - unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT : 1; - unsigned int EXECUTE_PROTECTION_FAULT_ENABLE_SAVE : 1; - unsigned int PAGE_TABLE_BLOCK_SIZE : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT1_CNTL2 { - struct { - unsigned int CLEAR_PROTECTION_FAULT_STATUS_ADDR : 1; - unsigned int ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT : 1; - unsigned int ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT : 1; - unsigned int ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES : 1; - unsigned int WAIT_FOR_IDLE_WHEN_INVALIDATE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT1_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT1_PAGE_TABLE_END_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT1_PAGE_TABLE_START_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT1_PROTECTION_FAULT_ADDR { - struct { - unsigned int LOGICAL_PAGE_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR { - struct { - unsigned int PHYSICAL_PAGE_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__CI__VI { - struct { - unsigned int NAME : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT1_PROTECTION_FAULT_STATUS { - struct { - unsigned int PROTECTIONS : 8; - unsigned int : 4; - unsigned int MEMORY_CLIENT_ID : 9; - unsigned int : 3; - unsigned int MEMORY_CLIENT_RW : 1; - unsigned int VMID : 4; - unsigned int ATOMIC__VI : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT2_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT3_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT4_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT5_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT6_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT7_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT8_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXT9_PAGE_TABLE_BASE_ADDR { - struct { - unsigned int PHYSICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_CONTEXTS_DISABLE { - struct { - unsigned int DISABLE_CONTEXT_0 : 1; - unsigned int DISABLE_CONTEXT_1 : 1; - unsigned int DISABLE_CONTEXT_2 : 1; - unsigned int DISABLE_CONTEXT_3 : 1; - unsigned int DISABLE_CONTEXT_4 : 1; - unsigned int DISABLE_CONTEXT_5 : 1; - unsigned int DISABLE_CONTEXT_6 : 1; - unsigned int DISABLE_CONTEXT_7 : 1; - unsigned int DISABLE_CONTEXT_8 : 1; - unsigned int DISABLE_CONTEXT_9 : 1; - unsigned int DISABLE_CONTEXT_10 : 1; - unsigned int DISABLE_CONTEXT_11 : 1; - unsigned int DISABLE_CONTEXT_12 : 1; - unsigned int DISABLE_CONTEXT_13 : 1; - unsigned int DISABLE_CONTEXT_14 : 1; - unsigned int DISABLE_CONTEXT_15 : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_DEBUG { - struct { - unsigned int FLAGS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_DUMMY_PAGE_FAULT_ADDR { - struct { - unsigned int DUMMY_PAGE_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_DUMMY_PAGE_FAULT_CNTL { - struct { - unsigned int DUMMY_PAGE_FAULT_ENABLE : 1; - unsigned int DUMMY_PAGE_ADDRESS_LOGICAL : 1; - unsigned int DUMMY_PAGE_COMPARE_MASK : 2; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_FAULT_CLIENT_ID { - struct { - unsigned int MEMORY_CLIENT : 9; - unsigned int MEMORY_CLIENT_MASK : 9; - unsigned int MEMORY_CLIENT_ID_MSB__VI : 1; - unsigned int MEMORY_CLIENT_ID_MASK_MSB__VI : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_INVALIDATE_REQUEST { - struct { - unsigned int INVALIDATE_DOMAIN_0 : 1; - unsigned int INVALIDATE_DOMAIN_1 : 1; - unsigned int INVALIDATE_DOMAIN_2 : 1; - unsigned int INVALIDATE_DOMAIN_3 : 1; - unsigned int INVALIDATE_DOMAIN_4 : 1; - unsigned int INVALIDATE_DOMAIN_5 : 1; - unsigned int INVALIDATE_DOMAIN_6 : 1; - unsigned int INVALIDATE_DOMAIN_7 : 1; - unsigned int INVALIDATE_DOMAIN_8 : 1; - unsigned int INVALIDATE_DOMAIN_9 : 1; - unsigned int INVALIDATE_DOMAIN_10 : 1; - unsigned int INVALIDATE_DOMAIN_11 : 1; - unsigned int INVALIDATE_DOMAIN_12 : 1; - unsigned int INVALIDATE_DOMAIN_13 : 1; - unsigned int INVALIDATE_DOMAIN_14 : 1; - unsigned int INVALIDATE_DOMAIN_15 : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_INVALIDATE_RESPONSE { - struct { - unsigned int DOMAIN_INVALIDATED_0 : 1; - unsigned int DOMAIN_INVALIDATED_1 : 1; - unsigned int DOMAIN_INVALIDATED_2 : 1; - unsigned int DOMAIN_INVALIDATED_3 : 1; - unsigned int DOMAIN_INVALIDATED_4 : 1; - unsigned int DOMAIN_INVALIDATED_5 : 1; - unsigned int DOMAIN_INVALIDATED_6 : 1; - unsigned int DOMAIN_INVALIDATED_7 : 1; - unsigned int DOMAIN_INVALIDATED_8 : 1; - unsigned int DOMAIN_INVALIDATED_9 : 1; - unsigned int DOMAIN_INVALIDATED_10 : 1; - unsigned int DOMAIN_INVALIDATED_11 : 1; - unsigned int DOMAIN_INVALIDATED_12 : 1; - unsigned int DOMAIN_INVALIDATED_13 : 1; - unsigned int DOMAIN_INVALIDATED_14 : 1; - unsigned int DOMAIN_INVALIDATED_15 : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_BANK_SELECT_MASKA { - struct { - unsigned int BANK_SELECT_MASK : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_BANK_SELECT_MASKB { - struct { - unsigned int BANK_SELECT_MASK : 9; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_CG { - struct { - unsigned int : 6; - unsigned int OFFDLY : 6; - unsigned int : 6; - unsigned int ENABLE : 1; - unsigned int MEM_LS_ENABLE : 1; - unsigned int OVERRIDE__VI : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_CNTL2 { - struct { - unsigned int INVALIDATE_ALL_L1_TLBS : 1; - unsigned int INVALIDATE_L2_CACHE : 1; - unsigned int : 19; - unsigned int DISABLE_INVALIDATE_PER_DOMAIN : 1; - unsigned int DISABLE_BIGK_CACHE_OPTIMIZATION : 1; - unsigned int L2_CACHE_BIGK_VMID_MODE : 3; - unsigned int INVALIDATE_CACHE_MODE : 2; - unsigned int PDE_CACHE_EFFECTIVE_SIZE__CI__VI : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_CNTL3 { - struct { - unsigned int BANK_SELECT : 6; - unsigned int L2_CACHE_UPDATE_MODE : 2; - unsigned int L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE : 5; - unsigned int : 2; - unsigned int L2_CACHE_BIGK_FRAGMENT_SIZE : 5; - unsigned int L2_CACHE_BIGK_ASSOCIATIVITY : 1; - unsigned int L2_CACHE_4K_EFFECTIVE_SIZE : 3; - unsigned int L2_CACHE_BIGK_EFFECTIVE_SIZE : 4; - unsigned int L2_CACHE_4K_FORCE_MISS : 1; - unsigned int L2_CACHE_BIGK_FORCE_MISS : 1; - unsigned int PDE_CACHE_FORCE_MISS__CI__VI : 1; - unsigned int L2_CACHE_4K_ASSOCIATIVITY__VI : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_CNTL__CI__VI { - struct { - unsigned int ENABLE_L2_CACHE : 1; - unsigned int ENABLE_L2_FRAGMENT_PROCESSING : 1; - unsigned int L2_CACHE_PTE_ENDIAN_SWAP_MODE : 2; - unsigned int L2_CACHE_PDE_ENDIAN_SWAP_MODE : 2; - unsigned int : 2; - unsigned int L2_PDE0_CACHE_TAG_GENERATION_MODE : 1; - unsigned int ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE : 1; - unsigned int ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE : 1; - unsigned int ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY : 1; - unsigned int L2_PDE0_CACHE_SPLIT_MODE : 3; - unsigned int EFFECTIVE_L2_QUEUE_SIZE : 3; - unsigned int PDE_FAULT_CLASSIFICATION : 1; - unsigned int CONTEXT1_IDENTITY_ACCESS_MODE : 2; - unsigned int IDENTITY_MODE_FRAGMENT_SIZE : 5; - unsigned int L2_CACHE_4K_SWAP_TAG_INDEX_LSBS : 2; - unsigned int L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_CNTL__SI { - struct { - unsigned int ENABLE_L2_CACHE : 1; - unsigned int ENABLE_L2_FRAGMENT_PROCESSING : 1; - unsigned int L2_CACHE_PTE_ENDIAN_SWAP_MODE : 2; - unsigned int L2_CACHE_PDE_ENDIAN_SWAP_MODE : 2; - unsigned int : 2; - unsigned int L2_PDE0_CACHE_TAG_GENERATION_MODE : 1; - unsigned int ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE : 1; - unsigned int ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE : 1; - unsigned int : 1; - unsigned int L2_PDE0_CACHE_SPLIT_MODE : 3; - unsigned int EFFECTIVE_L2_QUEUE_SIZE : 3; - unsigned int PDE_FAULT_CLASSIFICATION : 1; - unsigned int CONTEXT1_IDENTITY_ACCESS_MODE : 2; - unsigned int IDENTITY_MODE_FRAGMENT_SIZE : 5; - unsigned int L2_CACHE_4K_SWAP_TAG_INDEX_LSBS : 2; - unsigned int L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET { - struct { - unsigned int PHYSICAL_PAGE_OFFSET : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_STATUS { - struct { - unsigned int L2_BUSY : 1; - unsigned int CONTEXT_DOMAIN_BUSY : 16; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_PRT_APERTURE0_HIGH_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_PRT_APERTURE0_LOW_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_PRT_APERTURE1_HIGH_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_PRT_APERTURE1_LOW_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_PRT_APERTURE2_HIGH_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_PRT_APERTURE2_LOW_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_PRT_APERTURE3_HIGH_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_PRT_APERTURE3_LOW_ADDR { - struct { - unsigned int LOGICAL_PAGE_NUMBER : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_PRT_CNTL__CI__VI { - struct { - unsigned int CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS : 1; - unsigned int TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS : 1; - unsigned int L2_CACHE_STORE_INVALID_ENTRIES : 1; - unsigned int L1_TLB_STORE_INVALID_ENTRIES : 1; - unsigned int CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS : 1; - unsigned int TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS : 1; - unsigned int MASK_PDE0_FAULT : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_PRT_CNTL__SI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int L2_CACHE_STORE_INVALID_ENTRIES : 1; - unsigned int L1_TLB_STORE_INVALID_ENTRIES : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union V_COUNTER__SI { - struct { - unsigned int : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WAKE_ENABLE__SI__VI { - struct { - unsigned int SDIN_WAKE_ENABLE_FLAG : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WALL_CLOCK_COUNTER_ALIAS__SI__VI { - struct { - unsigned int WALL_CLOCK_COUNTER_ALIAS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WALL_CLOCK_COUNTER__SI__VI { - struct { - unsigned int WALL_CLOCK_COUNTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_CNTL_STATUS__CI__VI { - struct { - unsigned int WD_BUSY : 1; - unsigned int WD_SPL_DMA_BUSY : 1; - unsigned int WD_SPL_DI_BUSY : 1; - unsigned int WD_ADC_BUSY : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_CNTL__CI__VI { - struct { - unsigned int WD_DEBUG_INDX : 6; - unsigned int WD_DEBUG_SEL_BUS_B : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_DATA__CI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_REG0__CI__VI { - struct { - unsigned int wd_busy_extended : 1; - unsigned int wd_nodma_busy_extended : 1; - unsigned int wd_busy : 1; - unsigned int wd_nodma_busy : 1; - unsigned int rbiu_busy : 1; - unsigned int spl_dma_busy : 1; - unsigned int spl_di_busy : 1; - unsigned int vgt0_active_q : 1; - unsigned int vgt1_active_q : 1; - unsigned int spl_dma_p1_busy : 1; - unsigned int rbiu_dr_p1_fifo_busy : 1; - unsigned int rbiu_di_p1_fifo_busy : 1; - unsigned int SPARE2 : 1; - unsigned int rbiu_dr_fifo_busy : 1; - unsigned int rbiu_spl_dr_valid : 1; - unsigned int spl_rbiu_dr_read : 1; - unsigned int SPARE3 : 1; - unsigned int rbiu_di_fifo_busy : 1; - unsigned int rbiu_spl_di_valid : 1; - unsigned int spl_rbiu_di_read : 1; - unsigned int se0_synced_q : 1; - unsigned int se1_synced_q : 1; - unsigned int se2_synced_q : 1; - unsigned int se3_synced_q : 1; - unsigned int reg_clk_busy : 1; - unsigned int input_clk_busy : 1; - unsigned int core_clk_busy : 1; - unsigned int vgt2_active_q : 1; - unsigned int sclk_reg_vld : 1; - unsigned int sclk_input_vld : 1; - unsigned int sclk_core_vld : 1; - unsigned int vgt3_active_q : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_REG1__CI__VI { - struct { - unsigned int grbm_fifo_empty : 1; - unsigned int grbm_fifo_full : 1; - unsigned int grbm_fifo_we : 1; - unsigned int grbm_fifo_re : 1; - unsigned int draw_initiator_valid_q : 1; - unsigned int event_initiator_valid_q : 1; - unsigned int event_addr_valid_q : 1; - unsigned int dma_request_valid_q : 1; - unsigned int SPARE0 : 1; - unsigned int min_indx_valid_q : 1; - unsigned int max_indx_valid_q : 1; - unsigned int indx_offset_valid_q : 1; - unsigned int grbm_fifo_rdata_reg_id : 5; - unsigned int grbm_fifo_rdata_state : 3; - unsigned int free_cnt_q : 6; - unsigned int rbiu_di_fifo_we : 1; - unsigned int rbiu_dr_fifo_we : 1; - unsigned int rbiu_di_fifo_empty : 1; - unsigned int rbiu_di_fifo_full : 1; - unsigned int rbiu_dr_fifo_empty : 1; - unsigned int rbiu_dr_fifo_full : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_REG2__CI__VI { - struct { - unsigned int p1_grbm_fifo_empty : 1; - unsigned int p1_grbm_fifo_full : 1; - unsigned int p1_grbm_fifo_we : 1; - unsigned int p1_grbm_fifo_re : 1; - unsigned int p1_draw_initiator_valid_q : 1; - unsigned int p1_event_initiator_valid_q : 1; - unsigned int p1_event_addr_valid_q : 1; - unsigned int p1_dma_request_valid_q : 1; - unsigned int SPARE0 : 1; - unsigned int p1_min_indx_valid_q : 1; - unsigned int p1_max_indx_valid_q : 1; - unsigned int p1_indx_offset_valid_q : 1; - unsigned int p1_grbm_fifo_rdata_reg_id : 5; - unsigned int p1_grbm_fifo_rdata_state : 3; - unsigned int p1_free_cnt_q : 6; - unsigned int p1_rbiu_di_fifo_we : 1; - unsigned int p1_rbiu_dr_fifo_we : 1; - unsigned int p1_rbiu_di_fifo_empty : 1; - unsigned int p1_rbiu_di_fifo_full : 1; - unsigned int p1_rbiu_dr_fifo_empty : 1; - unsigned int p1_rbiu_dr_fifo_full : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_REG3__CI__VI { - struct { - unsigned int rbiu_spl_dr_valid : 1; - unsigned int SPARE0 : 1; - unsigned int pipe0_dr : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe1_rtr : 1; - unsigned int wd_subdma_fifo_empty : 1; - unsigned int wd_subdma_fifo_full : 1; - unsigned int dma_buf_type_p0_q : 2; - unsigned int dma_zero_indices_p0_q : 1; - unsigned int dma_req_path_p3_q : 1; - unsigned int dma_not_eop_p1_q : 1; - unsigned int out_of_range_p4 : 1; - unsigned int last_sub_dma_p3_q : 1; - unsigned int last_rdreq_of_sub_dma_p4 : 1; - unsigned int WD_IA_dma_send_d : 1; - unsigned int WD_IA_dma_rtr : 1; - unsigned int WD_IA1_dma_send_d : 1; - unsigned int WD_IA1_dma_rtr : 1; - unsigned int last_inst_of_dma_p2 : 1; - unsigned int last_sd_of_inst_p2 : 1; - unsigned int last_sd_of_dma_p2 : 1; - unsigned int SPARE1 : 1; - unsigned int WD_IA_dma_busy : 1; - unsigned int WD_IA1_dma_busy : 1; - unsigned int send_to_ia1_p3_q : 1; - unsigned int dma_wd_switch_on_eop_p3_q : 1; - unsigned int pipe3_dr : 1; - unsigned int pipe3_rtr : 1; - unsigned int wd_dma2draw_fifo_empty : 1; - unsigned int wd_dma2draw_fifo_full : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_REG4__CI__VI { - struct { - unsigned int rbiu_spl_di_valid : 1; - unsigned int spl_rbiu_di_read : 1; - unsigned int rbiu_spl_p1_di_valid : 1; - unsigned int spl_rbiu_p1_di_read : 1; - unsigned int pipe0_dr : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe1_rtr : 1; - unsigned int pipe2_dr : 1; - unsigned int pipe2_rtr : 1; - unsigned int pipe3_ld : 1; - unsigned int pipe3_rtr : 1; - unsigned int WD_IA_draw_send_d : 1; - unsigned int WD_IA_draw_rtr : 1; - unsigned int di_type_p0 : 2; - unsigned int di_state_sel_p1_q : 3; - unsigned int di_wd_switch_on_eop_p1_q : 1; - unsigned int rbiu_spl_pipe0_lockout : 1; - unsigned int last_inst_of_di_p2 : 1; - unsigned int last_sd_of_inst_p2 : 1; - unsigned int last_sd_of_di_p2 : 1; - unsigned int not_eop_wait_p1_q : 1; - unsigned int not_eop_wait_q : 1; - unsigned int ext_event_wait_p1_q : 1; - unsigned int ext_event_wait_q : 1; - unsigned int WD_IA1_draw_send_d : 1; - unsigned int WD_IA1_draw_rtr : 1; - unsigned int send_to_ia1_q : 1; - unsigned int dual_ia_mode : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_REG5__CI__VI { - struct { - unsigned int p1_rbiu_spl_dr_valid : 1; - unsigned int SPARE0 : 1; - unsigned int p1_pipe0_dr : 1; - unsigned int p1_pipe0_rtr : 1; - unsigned int p1_pipe1_dr : 1; - unsigned int p1_pipe1_rtr : 1; - unsigned int p1_wd_subdma_fifo_empty : 1; - unsigned int p1_wd_subdma_fifo_full : 1; - unsigned int p1_dma_buf_type_p0_q : 2; - unsigned int p1_dma_zero_indices_p0_q : 1; - unsigned int p1_dma_req_path_p3_q : 1; - unsigned int p1_dma_not_eop_p1_q : 1; - unsigned int p1_out_of_range_p4 : 1; - unsigned int p1_last_sub_dma_p3_q : 1; - unsigned int p1_last_rdreq_of_sub_dma_p4 : 1; - unsigned int p1_WD_IA_dma_send_d : 1; - unsigned int p1_WD_IA_dma_rtr : 1; - unsigned int p1_WD_IA1_dma_send_d : 1; - unsigned int p1_WD_IA1_dma_rtr : 1; - unsigned int p1_last_inst_of_dma_p2 : 1; - unsigned int p1_last_sd_of_inst_p2 : 1; - unsigned int p1_last_sd_of_dma_p2 : 1; - unsigned int SPARE1 : 1; - unsigned int p1_WD_IA_dma_busy : 1; - unsigned int p1_WD_IA1_dma_busy : 1; - unsigned int p1_send_to_ia1_p3_q : 1; - unsigned int p1_dma_wd_switch_on_eop_p3_q : 1; - unsigned int p1_pipe3_dr : 1; - unsigned int p1_pipe3_rtr : 1; - unsigned int p1_wd_dma2draw_fifo_empty : 1; - unsigned int p1_wd_dma2draw_fifo_full : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_ENHANCE__CI__VI { - struct { - unsigned int MISC : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER0_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER0_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER0_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER1_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER1_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER1_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER2_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER2_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER2_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER3_HI__CI__VI { - struct { - unsigned int PERFCOUNTER_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER3_LO__CI__VI { - struct { - unsigned int PERFCOUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_PERFCOUNTER3_SELECT__CI__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int : 20; - unsigned int PERF_MODE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - -//Merged Registers - - union AFMT_AUDIO_DBG_DTO_CNTL__VI { - struct { - unsigned int AFMT_AUDIO_DTO_FS_DIV_SEL : 3; - unsigned int : 5; - unsigned int AFMT_AUDIO_DTO_DBG_BASE : 1; - unsigned int : 3; - unsigned int AFMT_AUDIO_DTO_DBG_MULTI : 3; - unsigned int : 1; - unsigned int AFMT_AUDIO_DTO_DBG_DIV : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_AUDIO_SRC_CONTROL__VI { - struct { - unsigned int AFMT_AUDIO_SRC_SELECT : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_GENERIC_0__VI { - struct { - unsigned int AFMT_GENERIC_BYTE0 : 8; - unsigned int AFMT_GENERIC_BYTE1 : 8; - unsigned int AFMT_GENERIC_BYTE2 : 8; - unsigned int AFMT_GENERIC_BYTE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_GENERIC_1__VI { - struct { - unsigned int AFMT_GENERIC_BYTE4 : 8; - unsigned int AFMT_GENERIC_BYTE5 : 8; - unsigned int AFMT_GENERIC_BYTE6 : 8; - unsigned int AFMT_GENERIC_BYTE7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_GENERIC_2__VI { - struct { - unsigned int AFMT_GENERIC_BYTE8 : 8; - unsigned int AFMT_GENERIC_BYTE9 : 8; - unsigned int AFMT_GENERIC_BYTE10 : 8; - unsigned int AFMT_GENERIC_BYTE11 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_GENERIC_3__VI { - struct { - unsigned int AFMT_GENERIC_BYTE12 : 8; - unsigned int AFMT_GENERIC_BYTE13 : 8; - unsigned int AFMT_GENERIC_BYTE14 : 8; - unsigned int AFMT_GENERIC_BYTE15 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_GENERIC_4__VI { - struct { - unsigned int AFMT_GENERIC_BYTE16 : 8; - unsigned int AFMT_GENERIC_BYTE17 : 8; - unsigned int AFMT_GENERIC_BYTE18 : 8; - unsigned int AFMT_GENERIC_BYTE19 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_GENERIC_5__VI { - struct { - unsigned int AFMT_GENERIC_BYTE20 : 8; - unsigned int AFMT_GENERIC_BYTE21 : 8; - unsigned int AFMT_GENERIC_BYTE22 : 8; - unsigned int AFMT_GENERIC_BYTE23 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_GENERIC_6__VI { - struct { - unsigned int AFMT_GENERIC_BYTE24 : 8; - unsigned int AFMT_GENERIC_BYTE25 : 8; - unsigned int AFMT_GENERIC_BYTE26 : 8; - unsigned int AFMT_GENERIC_BYTE27 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_GENERIC_7__VI { - struct { - unsigned int AFMT_GENERIC_BYTE28 : 8; - unsigned int AFMT_GENERIC_BYTE29 : 8; - unsigned int AFMT_GENERIC_BYTE30 : 8; - unsigned int AFMT_GENERIC_BYTE31 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AFMT_GENERIC_HDR__VI { - struct { - unsigned int AFMT_GENERIC_HB0 : 8; - unsigned int AFMT_GENERIC_HB1 : 8; - unsigned int AFMT_GENERIC_HB2 : 8; - unsigned int AFMT_GENERIC_HB3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ALPHA_CONTROL__VI { - struct { - unsigned int ALPHA_ROUND_TRUNC_MODE : 1; - unsigned int CURSOR_ALPHA_BLND_ENA : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_FAULT_STATUS_INFO2__VI { - struct { - unsigned int VF : 1; - unsigned int VFID : 5; - unsigned int : 3; - unsigned int L1_ID : 8; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_SMU_STATUS__VI { - struct { - unsigned int VDDGFX_POWERED_DOWN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_ATS_VMID_STATUS__VI { - struct { - unsigned int VMID0_OUTSTANDING : 1; - unsigned int VMID1_OUTSTANDING : 1; - unsigned int VMID2_OUTSTANDING : 1; - unsigned int VMID3_OUTSTANDING : 1; - unsigned int VMID4_OUTSTANDING : 1; - unsigned int VMID5_OUTSTANDING : 1; - unsigned int VMID6_OUTSTANDING : 1; - unsigned int VMID7_OUTSTANDING : 1; - unsigned int VMID8_OUTSTANDING : 1; - unsigned int VMID9_OUTSTANDING : 1; - unsigned int VMID10_OUTSTANDING : 1; - unsigned int VMID11_OUTSTANDING : 1; - unsigned int VMID12_OUTSTANDING : 1; - unsigned int VMID13_OUTSTANDING : 1; - unsigned int VMID14_OUTSTANDING : 1; - unsigned int VMID15_OUTSTANDING : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L1RD_DEBUG2_TLB__VI { - struct { - unsigned int : 10; - unsigned int : 2; - unsigned int INJECT_SOFT_PARITY_ERROR : 1; - unsigned int INJECT_HARD_PARITY_ERROR : 1; - unsigned int CLEAR_CAM_PARITY_ERROR : 1; - unsigned int CAM_INDEX : 5; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L1WR_DEBUG2_TLB__VI { - struct { - unsigned int : 10; - unsigned int : 2; - unsigned int INJECT_SOFT_PARITY_ERROR : 1; - unsigned int INJECT_HARD_PARITY_ERROR : 1; - unsigned int CLEAR_CAM_PARITY_ERROR : 1; - unsigned int CAM_INDEX : 5; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L2_CACHE_DATA0__VI { - struct { - unsigned int DATA_REGISTER_VALID : 1; - unsigned int CACHE_ENTRY_VALID : 1; - unsigned int CACHED_ATTRIBUTES : 18; - unsigned int VIRTUAL_PAGE_ADDRESS_HIGH : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L2_CACHE_DATA1__VI { - struct { - unsigned int VIRTUAL_PAGE_ADDRESS_LOW : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L2_CACHE_DATA2__VI { - struct { - unsigned int PHYSICAL_PAGE_ADDRESS_LOW : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L2_CNTL3__VI { - struct { - unsigned int ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING : 7; - unsigned int ENABLE_FREE_COUNTER : 1; - unsigned int L2_CACHE_EVICTION_THRESHOLD : 5; - unsigned int DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION : 1; - unsigned int L2_DELAY_SEND_INVALIDATION_REQUEST : 3; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L2_STATUS__VI { - struct { - unsigned int BUSY : 1; - unsigned int PARITY_ERROR_INFO : 29; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ATC_L2_STATUS2__VI { - struct { - unsigned int CACHE_ADDRESS_MODE : 3; - unsigned int PARITY_ERROR_INFO : 8; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_GTC_SYNC_CONTROL__VI { - struct { - unsigned int AUX_GTC_SYNC_EN : 1; - unsigned int : 3; - unsigned int AUX_GTC_SYNC_IMPCAL_EN : 1; - unsigned int : 3; - unsigned int AUX_GTC_SYNC_IMPCAL_INTERVAL : 4; - unsigned int AUX_GTC_SYNC_LOCK_ACQ_PERIOD : 4; - unsigned int AUX_GTC_SYNC_LOCK_MAINT_PERIOD : 3; - unsigned int : 1; - unsigned int AUX_GTC_SYNC_BLOCK_REQ : 1; - unsigned int : 1; - unsigned int AUX_GTC_SYNC_INTERVAL_RESET_WINDOW : 2; - unsigned int AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT : 2; - unsigned int : 2; - unsigned int AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_GTC_SYNC_CONTROLLER_STATUS__VI { - struct { - unsigned int AUX_GTC_SYNC_LOCK_ACQ_COMPLETE : 1; - unsigned int : 3; - unsigned int AUX_GTC_SYNC_LOCK_LOST : 1; - unsigned int : 3; - unsigned int AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED : 1; - unsigned int AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE : 4; - unsigned int : 3; - unsigned int AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL : 1; - unsigned int : 3; - unsigned int AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED : 1; - unsigned int AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK : 1; - unsigned int AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED : 1; - unsigned int AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK : 1; - unsigned int AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED : 1; - unsigned int AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK : 1; - unsigned int : 2; - unsigned int AUX_GTC_SYNC_CTRL_STATE : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_GTC_SYNC_DATA__VI { - struct { - unsigned int AUX_GTC_DATA_RW : 1; - unsigned int : 7; - unsigned int AUX_GTC_DATA : 8; - unsigned int AUX_GTC_INDEX : 6; - unsigned int : 9; - unsigned int AUX_GTC_INDEX_AUTOINCREMENT_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_GTC_SYNC_ERROR_CONTROL__VI { - struct { - unsigned int AUX_GTC_POTENTIAL_ERROR_THRESHOLD : 5; - unsigned int : 3; - unsigned int AUX_GTC_DEFINITE_ERROR_THRESHOLD : 5; - unsigned int : 3; - unsigned int AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN : 2; - unsigned int : 2; - unsigned int AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT : 2; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI { - struct { - unsigned int AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN : 1; - unsigned int : 3; - unsigned int AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE : 16; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_GTC_SYNC_STATUS__VI { - struct { - unsigned int AUX_GTC_SYNC_DONE : 1; - unsigned int AUX_GTC_SYNC_REQ : 1; - unsigned int : 2; - unsigned int AUX_GTC_SYNC_RX_TIMEOUT_STATE : 3; - unsigned int AUX_GTC_SYNC_TIMEOUT : 1; - unsigned int AUX_GTC_SYNC_RX_OVERFLOW : 1; - unsigned int AUX_GTC_SYNC_HPD_DISCON : 1; - unsigned int AUX_GTC_SYNC_RX_PARTIAL_BYTE : 1; - unsigned int AUX_GTC_SYNC_NON_AUX_MODE : 1; - unsigned int AUX_GTC_SYNC_RX_MIN_COUNT_VIOL : 1; - unsigned int : 1; - unsigned int AUX_GTC_SYNC_RX_INVALID_STOP : 1; - unsigned int : 2; - unsigned int AUX_GTC_SYNC_RX_SYNC_INVALID_L : 1; - unsigned int AUX_GTC_SYNC_RX_SYNC_INVALID_H : 1; - unsigned int AUX_GTC_SYNC_RX_INVALID_START : 1; - unsigned int AUX_GTC_SYNC_RX_RECV_NO_DET : 1; - unsigned int : 1; - unsigned int AUX_GTC_SYNC_RX_RECV_INVALID_H : 1; - unsigned int AUX_GTC_SYNC_RX_RECV_INVALID_L : 1; - unsigned int AUX_GTC_SYNC_REPLY_BYTE_COUNT : 5; - unsigned int AUX_GTC_SYNC_NACKED : 1; - unsigned int AUX_GTC_MASTER_REQ_BY_RX : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_TEST_DEBUG_DATA__VI { - struct { - unsigned int AUX_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AUX_TEST_DEBUG_INDEX__VI { - struct { - unsigned int AUX_TEST_DEBUG_INDEX : 8; - unsigned int AUX_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AVSYNC_COUNTER_CONTROL__VI { - struct { - unsigned int AVSYNC_COUNTER_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AVSYNC_COUNTER_READ__VI { - struct { - unsigned int AVSYNC_COUNTER_RDVALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AVSYNC_COUNTER_WRITE__VI { - struct { - unsigned int AVSYNC_COUNTER_WRVALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CONTROLLER_CLOCK_GATING__VI { - struct { - unsigned int ENABLE_CLOCK_GATING : 1; - unsigned int : 3; - unsigned int CLOCK_ON_STATE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CONTROLLER_DEBUG__VI { - struct { - unsigned int CONTROLLER_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CHANNEL0__VI { - struct { - unsigned int CRC_CHANNEL0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CHANNEL1__VI { - struct { - unsigned int CRC_CHANNEL1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CHANNEL2__VI { - struct { - unsigned int CRC_CHANNEL2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CHANNEL3__VI { - struct { - unsigned int CRC_CHANNEL3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CHANNEL4__VI { - struct { - unsigned int CRC_CHANNEL4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CHANNEL5__VI { - struct { - unsigned int CRC_CHANNEL5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CHANNEL6__VI { - struct { - unsigned int CRC_CHANNEL6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CHANNEL7__VI { - struct { - unsigned int CRC_CHANNEL7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CONTROL0__VI { - struct { - unsigned int CRC_EN : 1; - unsigned int : 3; - unsigned int CRC_BLOCK_MODE : 1; - unsigned int : 3; - unsigned int CRC_INSTANCE_SEL : 3; - unsigned int : 1; - unsigned int CRC_SOURCE_SEL : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CONTROL1__VI { - struct { - unsigned int CRC_BLOCK_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CONTROL2__VI { - struct { - unsigned int CRC_BLOCK_ITERATION : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_CONTROL3__VI { - struct { - unsigned int CRC_COMPLETE : 1; - unsigned int : 3; - unsigned int CRC_BLOCK_COMPLETE_PHASE : 1; - unsigned int : 3; - unsigned int CRC_CHANNEL_RESULT_SEL : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC0_RESULT__VI { - struct { - unsigned int CRC_RESULT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CHANNEL0__VI { - struct { - unsigned int CRC_CHANNEL0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CHANNEL1__VI { - struct { - unsigned int CRC_CHANNEL1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CHANNEL2__VI { - struct { - unsigned int CRC_CHANNEL2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CHANNEL3__VI { - struct { - unsigned int CRC_CHANNEL3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CHANNEL4__VI { - struct { - unsigned int CRC_CHANNEL4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CHANNEL5__VI { - struct { - unsigned int CRC_CHANNEL5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CHANNEL6__VI { - struct { - unsigned int CRC_CHANNEL6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CHANNEL7__VI { - struct { - unsigned int CRC_CHANNEL7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CONTROL0__VI { - struct { - unsigned int CRC_EN : 1; - unsigned int : 3; - unsigned int CRC_BLOCK_MODE : 1; - unsigned int : 3; - unsigned int CRC_INSTANCE_SEL : 3; - unsigned int : 1; - unsigned int CRC_SOURCE_SEL : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CONTROL1__VI { - struct { - unsigned int CRC_BLOCK_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CONTROL2__VI { - struct { - unsigned int CRC_BLOCK_ITERATION : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_CONTROL3__VI { - struct { - unsigned int CRC_COMPLETE : 1; - unsigned int : 3; - unsigned int CRC_BLOCK_COMPLETE_PHASE : 1; - unsigned int : 3; - unsigned int CRC_CHANNEL_RESULT_SEL : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_CRC1_RESULT__VI { - struct { - unsigned int CRC_RESULT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_AUDIO_DISABLED_INT_STATUS__VI { - struct { - unsigned int AUDIO_DISABLED_FLAG : 1; - unsigned int : 3; - unsigned int AUDIO_DISABLED_MASK : 1; - unsigned int : 3; - unsigned int AUDIO_DISABLED_TYPE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_AUDIO_ENABLED_INT_STATUS__VI { - struct { - unsigned int AUDIO_ENABLED_FLAG : 1; - unsigned int : 3; - unsigned int AUDIO_ENABLED_MASK : 1; - unsigned int : 3; - unsigned int AUDIO_ENABLED_TYPE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_AUDIO_ENABLE_STATUS__VI { - struct { - unsigned int AUDIO_ENABLE_STATUS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__VI { - struct { - unsigned int AUDIO_FORMAT_CHANGED_FLAG : 1; - unsigned int : 3; - unsigned int AUDIO_FORMAT_CHANGED_MASK : 1; - unsigned int : 3; - unsigned int AUDIO_FORMAT_CHANGED_TYPE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__VI { - struct { - unsigned int HBR_CHANNEL_COUNT : 3; - unsigned int : 1; - unsigned int COMPRESSED_CHANNEL_COUNT : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__VI { - struct { - unsigned int NUMBER_OF_CHANNELS : 4; - unsigned int BITS_PER_SAMPLE : 3; - unsigned int : 1; - unsigned int SAMPLE_BASE_DIVISOR : 3; - unsigned int SAMPLE_BASE_MULTIPLE : 3; - unsigned int SAMPLE_BASE_RATE : 1; - unsigned int STREAM_TYPE : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI { - struct { - unsigned int DIGEN : 1; - unsigned int V : 1; - unsigned int VCFG : 1; - unsigned int PRE : 1; - unsigned int COPY : 1; - unsigned int NON_AUDIO : 1; - unsigned int PRO : 1; - unsigned int L : 1; - unsigned int CC : 7; - unsigned int : 8; - unsigned int KEEPALIVE : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__VI { - struct { - unsigned int PRESENTATION_TIME_EMBEDDING_ENABLE : 1; - unsigned int PRESENTATION_TIME_OFFSET_CHANGED : 1; - unsigned int CLEAR_GTC_COUNTER_MIN_MAX_DELTA : 1; - unsigned int : 1; - unsigned int PRESENTATION_TIME_EMBEDDING_GROUP : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__VI { - struct { - unsigned int PRESENTATION_TIME_OFFSET_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__VI { - struct { - unsigned int RAMP_RATE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__VI { - struct { - unsigned int GTC_COUNTER_DELTA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__VI { - struct { - unsigned int GTC_COUNTER_DELTA_MAX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__VI { - struct { - unsigned int GTC_COUNTER_DELTA_MIN : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI { - struct { - unsigned int AUDIO_CHANNEL_CAPABILITIES : 1; - unsigned int INPUT_AMPLIFIER_PRESENT : 1; - unsigned int OUTPUT_AMPLIFIER_PRESENT : 1; - unsigned int AMPLIFIER_PARAMETER_OVERRIDE : 1; - unsigned int FORMAT_OVERRIDE : 1; - unsigned int STRIPE : 1; - unsigned int PROCESSING_WIDGET : 1; - unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1; - unsigned int CONNECTION_LIST : 1; - unsigned int DIGITAL : 1; - unsigned int POWER_CONTROL : 1; - unsigned int LR_SWAP : 1; - unsigned int : 4; - unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4; - unsigned int TYPE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__VI { - struct { - unsigned int STREAM_FORMATS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI { - struct { - unsigned int AUDIO_RATE_CAPABILITIES : 12; - unsigned int : 4; - unsigned int AUDIO_BIT_CAPABILITIES : 5; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__VI { - struct { - unsigned int AZALIA_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__VI { - struct { - unsigned int STRIPE_CONTROL : 2; - unsigned int : 18; - unsigned int STRIPE_CAPABILITY : 3; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_DEBUG__VI { - struct { - unsigned int DISABLE_FORMAT_COMPARISON : 6; - unsigned int CODEC_DEBUG : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_ENDPOINT_DATA__VI { - struct { - unsigned int AZALIA_ENDPOINT_REG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_ENDPOINT_INDEX__VI { - struct { - unsigned int AZALIA_ENDPOINT_REG_INDEX : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__VI { - struct { - unsigned int CONVERTER_SYNCHRONIZATION : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI { - struct { - unsigned int CHANNEL_ID : 4; - unsigned int STREAM_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__VI { - struct { - unsigned int NUMBER_OF_CHANNELS : 4; - unsigned int BITS_PER_SAMPLE : 3; - unsigned int : 1; - unsigned int SAMPLE_BASE_DIVISOR : 3; - unsigned int SAMPLE_BASE_MULTIPLE : 3; - unsigned int SAMPLE_BASE_RATE : 1; - unsigned int STREAM_TYPE : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI { - struct { - unsigned int DIGEN : 1; - unsigned int V : 1; - unsigned int VCFG : 1; - unsigned int PRE : 1; - unsigned int COPY : 1; - unsigned int NON_AUDIO : 1; - unsigned int PRO : 1; - unsigned int L : 1; - unsigned int CC : 7; - unsigned int : 8; - unsigned int KEEPALIVE : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI { - struct { - unsigned int AUDIO_CHANNEL_CAPABILITIES : 1; - unsigned int INPUT_AMPLIFIER_PRESENT : 1; - unsigned int OUTPUT_AMPLIFIER_PRESENT : 1; - unsigned int AMPLIFIER_PARAMETER_OVERRIDE : 1; - unsigned int FORMAT_OVERRIDE : 1; - unsigned int STRIPE : 1; - unsigned int PROCESSING_WIDGET : 1; - unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1; - unsigned int CONNECTION_LIST : 1; - unsigned int DIGITAL : 1; - unsigned int POWER_CONTROL : 1; - unsigned int LR_SWAP : 1; - unsigned int : 4; - unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4; - unsigned int TYPE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__VI { - struct { - unsigned int STREAM_FORMATS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI { - struct { - unsigned int AUDIO_RATE_CAPABILITIES : 12; - unsigned int : 4; - unsigned int AUDIO_BIT_CAPABILITIES : 5; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__VI { - struct { - unsigned int AZALIA_INPUT_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI { - struct { - unsigned int AZALIA_INPUT_ENDPOINT_REG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI { - struct { - unsigned int AZALIA_INPUT_ENDPOINT_REG_INDEX : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__VI { - struct { - unsigned int CHANNEL_ALLOCATION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__VI { - struct { - unsigned int CLOCK_GATING_DISABLE : 1; - unsigned int : 3; - unsigned int CLOCK_ON_STATE : 1; - unsigned int : 26; - unsigned int AUDIO_ENABLED : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__VI { - struct { - unsigned int CHANNEL_COUNT : 3; - unsigned int : 5; - unsigned int CHANNEL_ALLOCATION : 8; - unsigned int INFOFRAME_BYTE_5 : 8; - unsigned int : 7; - unsigned int INFOFRAME_VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__VI { - struct { - unsigned int INPUT_ACTIVITY : 1; - unsigned int CHANNEL_LAYOUT : 2; - unsigned int : 1; - unsigned int INPUT_ACTIVITY_UR_ENABLE : 1; - unsigned int INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__VI { - struct { - unsigned int LPIB : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI { - struct { - unsigned int LPIB_SNAPSHOT_LOCK : 1; - unsigned int : 7; - unsigned int CYCLIC_BUFFER_WRAP_COUNT : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI { - struct { - unsigned int LPIB_TIMER_SNAPSHOT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__VI { - struct { - unsigned int MULTICHANNEL0_ENABLE : 1; - unsigned int MULTICHANNEL0_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL0_CHANNEL_ID : 4; - unsigned int MULTICHANNEL1_ENABLE : 1; - unsigned int MULTICHANNEL1_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL1_CHANNEL_ID : 4; - unsigned int MULTICHANNEL2_ENABLE : 1; - unsigned int MULTICHANNEL2_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL2_CHANNEL_ID : 4; - unsigned int MULTICHANNEL3_ENABLE : 1; - unsigned int MULTICHANNEL3_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL3_CHANNEL_ID : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__VI { - struct { - unsigned int MULTICHANNEL4_ENABLE : 1; - unsigned int MULTICHANNEL4_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL4_CHANNEL_ID : 4; - unsigned int MULTICHANNEL5_ENABLE : 1; - unsigned int MULTICHANNEL5_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL5_CHANNEL_ID : 4; - unsigned int MULTICHANNEL6_ENABLE : 1; - unsigned int MULTICHANNEL6_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL6_CHANNEL_ID : 4; - unsigned int MULTICHANNEL7_ENABLE : 1; - unsigned int MULTICHANNEL7_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL7_CHANNEL_ID : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI { - struct { - unsigned int SEQUENCE : 4; - unsigned int DEFAULT_ASSOCIATION : 4; - unsigned int MISC : 4; - unsigned int COLOR : 4; - unsigned int CONNECTION_TYPE : 4; - unsigned int DEFAULT_DEVICE : 4; - unsigned int LOCATION : 6; - unsigned int PORT_CONNECTIVITY : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__VI { - struct { - unsigned int HBR_CAPABLE : 1; - unsigned int : 3; - unsigned int HBR_ENABLE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__VI { - struct { - unsigned int IMPEDANCE_SENSE : 31; - unsigned int PRESENCE_DETECT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__VI { - struct { - unsigned int TAG : 6; - unsigned int : 1; - unsigned int ENABLE : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__VI { - struct { - unsigned int UNSOLICITED_RESPONSE_PAYLOAD : 26; - unsigned int : 2; - unsigned int UNSOLICITED_RESPONSE_FORCE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__VI { - struct { - unsigned int : 5; - unsigned int IN_ENABLE : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI { - struct { - unsigned int AUDIO_CHANNEL_CAPABILITIES : 1; - unsigned int INPUT_AMPLIFIER_PRESENT : 1; - unsigned int OUTPUT_AMPLIFIER_PRESENT : 1; - unsigned int AMPLIFIER_PARAMETER_OVERRIDE : 1; - unsigned int : 1; - unsigned int STRIPE : 1; - unsigned int PROCESSING_WIDGET : 1; - unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1; - unsigned int CONNECTION_LIST : 1; - unsigned int DIGITAL : 1; - unsigned int POWER_CONTROL : 1; - unsigned int LR_SWAP : 1; - unsigned int : 4; - unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4; - unsigned int TYPE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VI { - struct { - unsigned int IMPEDANCE_SENSE_CAPABLE : 1; - unsigned int TRIGGER_REQUIRED : 1; - unsigned int JACK_DETECTION_CAPABILITY : 1; - unsigned int HEADPHONE_DRIVE_CAPABLE : 1; - unsigned int OUTPUT_CAPABLE : 1; - unsigned int INPUT_CAPABLE : 1; - unsigned int BALANCED_I_O_PINS : 1; - unsigned int HDMI : 1; - unsigned int VREF_CONTROL : 8; - unsigned int EAPD_CAPABLE : 1; - unsigned int : 7; - unsigned int DP : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__VI { - struct { - unsigned int ASSOCIATION_INFO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int : 5; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__VI { - struct { - unsigned int SPEAKER_ALLOCATION : 7; - unsigned int : 1; - unsigned int CHANNEL_ALLOCATION : 8; - unsigned int HDMI_CONNECTION : 1; - unsigned int DP_CONNECTION : 1; - unsigned int EXTRA_CONNECTION_INFO : 6; - unsigned int LFE_PLAYBACK_LEVEL : 2; - unsigned int : 1; - unsigned int LEVEL_SHIFT : 4; - unsigned int DOWN_MIX_INHIBIT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__VI { - struct { - unsigned int CODING_TYPE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__VI { - struct { - unsigned int OUTPUT_ACTIVE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__VI { - struct { - unsigned int FORMAT_CHANGED : 1; - unsigned int FORMAT_CHANGED_ACK_UR_ENABLE : 1; - unsigned int : 6; - unsigned int FORMAT_CHANGE_REASON : 8; - unsigned int FORMAT_CHANGE_RESPONSE : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__VI { - struct { - unsigned int CLOCK_GATING_DISABLE : 1; - unsigned int : 3; - unsigned int CLOCK_ON_STATE : 1; - unsigned int : 26; - unsigned int AUDIO_ENABLED : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_LPIB__VI { - struct { - unsigned int LPIB : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI { - struct { - unsigned int LPIB_SNAPSHOT_LOCK : 1; - unsigned int : 7; - unsigned int CYCLIC_BUFFER_WRAP_COUNT : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI { - struct { - unsigned int LPIB_TIMER_SNAPSHOT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__VI { - struct { - unsigned int MULTICHANNEL01_ENABLE : 1; - unsigned int MULTICHANNEL01_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL01_CHANNEL_ID : 4; - unsigned int MULTICHANNEL23_ENABLE : 1; - unsigned int MULTICHANNEL23_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL23_CHANNEL_ID : 4; - unsigned int MULTICHANNEL45_ENABLE : 1; - unsigned int MULTICHANNEL45_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL45_CHANNEL_ID : 4; - unsigned int MULTICHANNEL67_ENABLE : 1; - unsigned int MULTICHANNEL67_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL67_CHANNEL_ID : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__VI { - struct { - unsigned int MULTICHANNEL1_ENABLE : 1; - unsigned int MULTICHANNEL1_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL1_CHANNEL_ID : 4; - unsigned int MULTICHANNEL3_ENABLE : 1; - unsigned int MULTICHANNEL3_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL3_CHANNEL_ID : 4; - unsigned int MULTICHANNEL5_ENABLE : 1; - unsigned int MULTICHANNEL5_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL5_CHANNEL_ID : 4; - unsigned int MULTICHANNEL7_ENABLE : 1; - unsigned int MULTICHANNEL7_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL7_CHANNEL_ID : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__VI { - struct { - unsigned int MULTICHANNEL_MODE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__VI { - struct { - unsigned int REMOTE_KEEP_ALIVE_ENABLE : 1; - unsigned int : 3; - unsigned int REMOTE_KEEP_ALIVE_CAPABILITY : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI { - struct { - unsigned int SEQUENCE : 4; - unsigned int DEFAULT_ASSOCIATION : 4; - unsigned int MISC : 4; - unsigned int COLOR : 4; - unsigned int CONNECTION_TYPE : 4; - unsigned int DEFAULT_DEVICE : 4; - unsigned int LOCATION : 6; - unsigned int PORT_CONNECTIVITY : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__VI { - struct { - unsigned int HBR_CAPABLE : 1; - unsigned int : 3; - unsigned int HBR_ENABLE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VI { - struct { - unsigned int VIDEO_LIPSYNC : 8; - unsigned int AUDIO_LIPSYNC : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__VI { - struct { - unsigned int IMPEDANCE_SENSE : 31; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__VI { - struct { - unsigned int MANUFACTURER_ID : 16; - unsigned int PRODUCT_ID : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__VI { - struct { - unsigned int SINK_DESCRIPTION_LEN : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__VI { - struct { - unsigned int PORT_ID0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__VI { - struct { - unsigned int PORT_ID1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__VI { - struct { - unsigned int DESCRIPTION0 : 8; - unsigned int DESCRIPTION1 : 8; - unsigned int DESCRIPTION2 : 8; - unsigned int DESCRIPTION3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__VI { - struct { - unsigned int DESCRIPTION4 : 8; - unsigned int DESCRIPTION5 : 8; - unsigned int DESCRIPTION6 : 8; - unsigned int DESCRIPTION7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__VI { - struct { - unsigned int DESCRIPTION8 : 8; - unsigned int DESCRIPTION9 : 8; - unsigned int DESCRIPTION10 : 8; - unsigned int DESCRIPTION11 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__VI { - struct { - unsigned int DESCRIPTION12 : 8; - unsigned int DESCRIPTION13 : 8; - unsigned int DESCRIPTION14 : 8; - unsigned int DESCRIPTION15 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__VI { - struct { - unsigned int DESCRIPTION16 : 8; - unsigned int DESCRIPTION17 : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__VI { - struct { - unsigned int UNSOLICITED_RESPONSE_PAYLOAD : 26; - unsigned int : 2; - unsigned int UNSOLICITED_RESPONSE_FORCE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__VI { - struct { - unsigned int WIRELESS_DISPLAY_IDENTIFICATION : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI { - struct { - unsigned int AUDIO_CHANNEL_CAPABILITIES : 1; - unsigned int INPUT_AMPLIFIER_PRESENT : 1; - unsigned int OUTPUT_AMPLIFIER_PRESENT : 1; - unsigned int AMPLIFIER_PARAMETER_OVERRIDE : 1; - unsigned int : 1; - unsigned int STRIPE : 1; - unsigned int PROCESSING_WIDGET : 1; - unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1; - unsigned int CONNECTION_LIST : 1; - unsigned int DIGITAL : 1; - unsigned int POWER_CONTROL : 1; - unsigned int LR_SWAP : 1; - unsigned int : 4; - unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4; - unsigned int TYPE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VI { - struct { - unsigned int IMPEDANCE_SENSE_CAPABLE : 1; - unsigned int TRIGGER_REQUIRED : 1; - unsigned int JACK_DETECTION_CAPABILITY : 1; - unsigned int HEADPHONE_DRIVE_CAPABLE : 1; - unsigned int OUTPUT_CAPABLE : 1; - unsigned int INPUT_CAPABLE : 1; - unsigned int BALANCED_I_O_PINS : 1; - unsigned int HDMI : 1; - unsigned int VREF_CONTROL : 8; - unsigned int EAPD_CAPABLE : 1; - unsigned int : 7; - unsigned int DP : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__VI { - struct { - unsigned int RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW : 6; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_GTC_GROUP_OFFSET0__VI { - struct { - unsigned int GTC_GROUP_OFFSET0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_GTC_GROUP_OFFSET1__VI { - struct { - unsigned int GTC_GROUP_OFFSET1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_GTC_GROUP_OFFSET2__VI { - struct { - unsigned int GTC_GROUP_OFFSET2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_GTC_GROUP_OFFSET3__VI { - struct { - unsigned int GTC_GROUP_OFFSET3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_GTC_GROUP_OFFSET4__VI { - struct { - unsigned int GTC_GROUP_OFFSET4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_GTC_GROUP_OFFSET5__VI { - struct { - unsigned int GTC_GROUP_OFFSET5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_GTC_GROUP_OFFSET6__VI { - struct { - unsigned int GTC_GROUP_OFFSET6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__VI { - struct { - unsigned int IEC_60958_CS_MODE : 2; - unsigned int IEC_60958_CS_SOURCE_NUMBER : 4; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__VI { - struct { - unsigned int IEC_60958_CS_CLOCK_ACCURACY : 2; - unsigned int IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN : 1; - unsigned int IEC_60958_CS_WORD_LENGTH : 4; - unsigned int IEC_60958_CS_WORD_LENGTH_OVRRD_EN : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__VI { - struct { - unsigned int IEC_60958_CS_SAMPLING_FREQUENCY : 6; - unsigned int IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__VI { - struct { - unsigned int IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY : 4; - unsigned int IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__VI { - struct { - unsigned int IEC_60958_CS_SAMPLING_FREQUENCY_COEFF : 4; - unsigned int IEC_60958_CS_MPEG_SURROUND_INFO : 1; - unsigned int IEC_60958_CS_CGMS_A : 2; - unsigned int IEC_60958_CS_CGMS_A_VALID : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__VI { - struct { - unsigned int IEC_60958_CS_CHANNEL_NUMBER_L : 4; - unsigned int IEC_60958_CS_CHANNEL_NUMBER_R : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__VI { - struct { - unsigned int IEC_60958_CS_CHANNEL_NUMBER_2 : 4; - unsigned int IEC_60958_CS_CHANNEL_NUMBER_3 : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__VI { - struct { - unsigned int IEC_60958_CS_CHANNEL_NUMBER_4 : 4; - unsigned int IEC_60958_CS_CHANNEL_NUMBER_5 : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__VI { - struct { - unsigned int IEC_60958_CS_CHANNEL_NUMBER_6 : 4; - unsigned int IEC_60958_CS_CHANNEL_NUMBER_7 : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI { - struct { - unsigned int CHANNEL_ID : 4; - unsigned int STREAM_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__VI { - struct { - unsigned int NUMBER_OF_CHANNELS : 4; - unsigned int BITS_PER_SAMPLE : 3; - unsigned int : 1; - unsigned int SAMPLE_BASE_DIVISOR : 3; - unsigned int SAMPLE_BASE_MULTIPLE : 3; - unsigned int SAMPLE_BASE_RATE : 1; - unsigned int STREAM_TYPE : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI { - struct { - unsigned int DIGEN : 1; - unsigned int V : 1; - unsigned int VCFG : 1; - unsigned int PRE : 1; - unsigned int COPY : 1; - unsigned int NON_AUDIO : 1; - unsigned int PRO : 1; - unsigned int L : 1; - unsigned int CC : 7; - unsigned int : 8; - unsigned int KEEPALIVE : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__VI { - struct { - unsigned int CC : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__VI { - struct { - unsigned int : 7; - unsigned int KEEPALIVE : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__VI { - struct { - unsigned int PRESENTATION_TIME_EMBEDDING_ENABLE : 1; - unsigned int PRESENTATION_TIME_OFFSET_CHANGED : 1; - unsigned int : 2; - unsigned int PRESENTATION_TIME_EMBEDDING_GROUP : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__VI { - struct { - unsigned int RAMP_RATE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI { - struct { - unsigned int AUDIO_CHANNEL_CAPABILITIES : 1; - unsigned int INPUT_AMPLIFIER_PRESENT : 1; - unsigned int OUTPUT_AMPLIFIER_PRESENT : 1; - unsigned int AMPLIFIER_PARAMETER_OVERRIDE : 1; - unsigned int FORMAT_OVERRIDE : 1; - unsigned int STRIPE : 1; - unsigned int PROCESSING_WIDGET : 1; - unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1; - unsigned int CONNECTION_LIST : 1; - unsigned int DIGITAL : 1; - unsigned int POWER_CONTROL : 1; - unsigned int LR_SWAP : 1; - unsigned int : 4; - unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4; - unsigned int TYPE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__VI { - struct { - unsigned int STREAM_FORMATS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI { - struct { - unsigned int AUDIO_RATE_CAPABILITIES : 12; - unsigned int : 4; - unsigned int AUDIO_BIT_CAPABILITIES : 5; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__VI { - struct { - unsigned int STRIPE_CONTROL : 2; - unsigned int : 18; - unsigned int STRIPE_CAPABILITY : 3; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__VI { - struct { - unsigned int CONVERTER_SYNCHRONIZATION : 7; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI { - struct { - unsigned int CHANNEL_ID : 4; - unsigned int STREAM_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__VI { - struct { - unsigned int NUMBER_OF_CHANNELS : 4; - unsigned int BITS_PER_SAMPLE : 3; - unsigned int : 1; - unsigned int SAMPLE_BASE_DIVISOR : 3; - unsigned int SAMPLE_BASE_MULTIPLE : 3; - unsigned int SAMPLE_BASE_RATE : 1; - unsigned int STREAM_TYPE : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI { - struct { - unsigned int DIGEN : 1; - unsigned int V : 1; - unsigned int VCFG : 1; - unsigned int PRE : 1; - unsigned int COPY : 1; - unsigned int NON_AUDIO : 1; - unsigned int PRO : 1; - unsigned int L : 1; - unsigned int CC : 7; - unsigned int : 8; - unsigned int KEEPALIVE : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI { - struct { - unsigned int AUDIO_CHANNEL_CAPABILITIES : 1; - unsigned int INPUT_AMPLIFIER_PRESENT : 1; - unsigned int OUTPUT_AMPLIFIER_PRESENT : 1; - unsigned int AMPLIFIER_PARAMETER_OVERRIDE : 1; - unsigned int FORMAT_OVERRIDE : 1; - unsigned int STRIPE : 1; - unsigned int PROCESSING_WIDGET : 1; - unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1; - unsigned int CONNECTION_LIST : 1; - unsigned int DIGITAL : 1; - unsigned int POWER_CONTROL : 1; - unsigned int LR_SWAP : 1; - unsigned int : 4; - unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4; - unsigned int TYPE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__VI { - struct { - unsigned int STREAM_FORMATS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI { - struct { - unsigned int AUDIO_RATE_CAPABILITIES : 12; - unsigned int : 4; - unsigned int AUDIO_BIT_CAPABILITIES : 5; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__VI { - struct { - unsigned int CHANNEL_ALLOCATION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__VI { - struct { - unsigned int CHANNEL_STATUS_H : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__VI { - struct { - unsigned int CHANNEL_STATUS_L : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__VI { - struct { - unsigned int HBR_CAPABLE : 1; - unsigned int : 3; - unsigned int HBR_ENABLE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__VI { - struct { - unsigned int CHANNEL_COUNT : 3; - unsigned int : 5; - unsigned int CHANNEL_ALLOCATION : 8; - unsigned int INFOFRAME_BYTE_5 : 8; - unsigned int : 7; - unsigned int INFOFRAME_VALID : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__VI { - struct { - unsigned int INPUT_ACTIVITY : 1; - unsigned int CHANNEL_LAYOUT : 2; - unsigned int : 1; - unsigned int INPUT_ACTIVITY_UR_ENABLE : 1; - unsigned int INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__VI { - struct { - unsigned int LPIB : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI { - struct { - unsigned int LPIB_SNAPSHOT_LOCK : 1; - unsigned int : 7; - unsigned int CYCLIC_BUFFER_WRAP_COUNT : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI { - struct { - unsigned int LPIB_TIMER_SNAPSHOT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__VI { - struct { - unsigned int MULTICHANNEL0_ENABLE : 1; - unsigned int MULTICHANNEL0_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL0_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__VI { - struct { - unsigned int MULTICHANNEL1_ENABLE : 1; - unsigned int MULTICHANNEL1_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL1_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__VI { - struct { - unsigned int MULTICHANNEL2_ENABLE : 1; - unsigned int MULTICHANNEL2_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL2_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__VI { - struct { - unsigned int MULTICHANNEL3_ENABLE : 1; - unsigned int MULTICHANNEL3_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL3_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__VI { - struct { - unsigned int MULTICHANNEL4_ENABLE : 1; - unsigned int MULTICHANNEL4_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL4_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__VI { - struct { - unsigned int MULTICHANNEL5_ENABLE : 1; - unsigned int MULTICHANNEL5_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL5_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__VI { - struct { - unsigned int MULTICHANNEL6_ENABLE : 1; - unsigned int MULTICHANNEL6_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL6_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__VI { - struct { - unsigned int MULTICHANNEL7_ENABLE : 1; - unsigned int MULTICHANNEL7_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL7_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI { - struct { - unsigned int SEQUENCE : 4; - unsigned int DEFAULT_ASSOCIATION : 4; - unsigned int MISC : 4; - unsigned int COLOR : 4; - unsigned int CONNECTION_TYPE : 4; - unsigned int DEFAULT_DEVICE : 4; - unsigned int LOCATION : 6; - unsigned int PORT_CONNECTIVITY : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__VI { - struct { - unsigned int MISC : 4; - unsigned int COLOR : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__VI { - struct { - unsigned int CONNECTION_TYPE : 4; - unsigned int DEFAULT_DEVICE : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__VI { - struct { - unsigned int LOCATION : 6; - unsigned int PORT_CONNECTIVITY : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__VI { - struct { - unsigned int IMPEDANCE_SENSE : 31; - unsigned int PRESENCE_DETECT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__VI { - struct { - unsigned int TAG : 6; - unsigned int : 1; - unsigned int ENABLE : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__VI { - struct { - unsigned int : 5; - unsigned int IN_ENABLE : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI { - struct { - unsigned int AUDIO_CHANNEL_CAPABILITIES : 1; - unsigned int INPUT_AMPLIFIER_PRESENT : 1; - unsigned int OUTPUT_AMPLIFIER_PRESENT : 1; - unsigned int AMPLIFIER_PARAMETER_OVERRIDE : 1; - unsigned int : 1; - unsigned int STRIPE : 1; - unsigned int PROCESSING_WIDGET : 1; - unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1; - unsigned int CONNECTION_LIST : 1; - unsigned int DIGITAL : 1; - unsigned int POWER_CONTROL : 1; - unsigned int LR_SWAP : 1; - unsigned int : 4; - unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4; - unsigned int TYPE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VI { - struct { - unsigned int IMPEDANCE_SENSE_CAPABLE : 1; - unsigned int TRIGGER_REQUIRED : 1; - unsigned int JACK_DETECTION_CAPABILITY : 1; - unsigned int HEADPHONE_DRIVE_CAPABLE : 1; - unsigned int OUTPUT_CAPABLE : 1; - unsigned int INPUT_CAPABLE : 1; - unsigned int BALANCED_I_O_PINS : 1; - unsigned int HDMI : 1; - unsigned int VREF_CONTROL : 8; - unsigned int EAPD_CAPABLE : 1; - unsigned int : 7; - unsigned int DP : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__VI { - struct { - unsigned int ASSOCIATION_INFO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__VI { - struct { - unsigned int MAX_CHANNELS : 3; - unsigned int FORMAT_CODE : 4; - unsigned int : 1; - unsigned int SUPPORTED_FREQUENCIES : 8; - unsigned int DESCRIPTOR_BYTE_2 : 8; - unsigned int SUPPORTED_FREQUENCIES_STEREO : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__VI { - struct { - unsigned int DESCRIPTOR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__VI { - struct { - unsigned int SINK_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__VI { - struct { - unsigned int SINK_INFO_INDEX : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__VI { - struct { - unsigned int CHANNEL_ALLOCATION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__VI { - struct { - unsigned int CODING_TYPE : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__VI { - struct { - unsigned int OUTPUT_ACTIVE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__VI { - struct { - unsigned int LFE_PLAYBACK_LEVEL : 2; - unsigned int : 1; - unsigned int LEVEL_SHIFT : 4; - unsigned int DOWN_MIX_INHIBIT : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__VI { - struct { - unsigned int FORMAT_CHANGED : 1; - unsigned int FORMAT_CHANGED_ACK_UR_ENABLE : 1; - unsigned int : 6; - unsigned int FORMAT_CHANGE_REASON : 8; - unsigned int FORMAT_CHANGE_RESPONSE : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_HBR__VI { - struct { - unsigned int HBR_CAPABLE : 1; - unsigned int : 3; - unsigned int HBR_ENABLE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VI { - struct { - unsigned int VIDEO_LIPSYNC : 8; - unsigned int AUDIO_LIPSYNC : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_LPIB__VI { - struct { - unsigned int LPIB : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI { - struct { - unsigned int LPIB_SNAPSHOT_LOCK : 1; - unsigned int : 7; - unsigned int CYCLIC_BUFFER_WRAP_COUNT : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI { - struct { - unsigned int LPIB_TIMER_SNAPSHOT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__VI { - struct { - unsigned int MANUFACTURER_ID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__VI { - struct { - unsigned int MULTICHANNEL01_ENABLE : 1; - unsigned int MULTICHANNEL01_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL01_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__VI { - struct { - unsigned int MULTICHANNEL1_ENABLE : 1; - unsigned int MULTICHANNEL1_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL1_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__VI { - struct { - unsigned int MULTICHANNEL23_ENABLE : 1; - unsigned int MULTICHANNEL23_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL23_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__VI { - struct { - unsigned int MULTICHANNEL3_ENABLE : 1; - unsigned int MULTICHANNEL3_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL3_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__VI { - struct { - unsigned int MULTICHANNEL45_ENABLE : 1; - unsigned int MULTICHANNEL45_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL45_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__VI { - struct { - unsigned int MULTICHANNEL5_ENABLE : 1; - unsigned int MULTICHANNEL5_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL5_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__VI { - struct { - unsigned int MULTICHANNEL67_ENABLE : 1; - unsigned int MULTICHANNEL67_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL67_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__VI { - struct { - unsigned int MULTICHANNEL7_ENABLE : 1; - unsigned int MULTICHANNEL7_MUTE : 1; - unsigned int : 2; - unsigned int MULTICHANNEL7_CHANNEL_ID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__VI { - struct { - unsigned int MULTICHANNEL_MODE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__VI { - struct { - unsigned int PORTID : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__VI { - struct { - unsigned int PORTID : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__VI { - struct { - unsigned int PRODUCT_ID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__VI { - struct { - unsigned int REMOTE_KEEP_ALIVE_ENABLE : 1; - unsigned int : 3; - unsigned int REMOTE_KEEP_ALIVE_CAPABILITY : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI { - struct { - unsigned int SEQUENCE : 4; - unsigned int DEFAULT_ASSOCIATION : 4; - unsigned int MISC : 4; - unsigned int COLOR : 4; - unsigned int CONNECTION_TYPE : 4; - unsigned int DEFAULT_DEVICE : 4; - unsigned int LOCATION : 6; - unsigned int PORT_CONNECTIVITY : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__VI { - struct { - unsigned int MISC : 4; - unsigned int COLOR : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__VI { - struct { - unsigned int CONNECTION_TYPE : 4; - unsigned int DEFAULT_DEVICE : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__VI { - struct { - unsigned int LOCATION : 6; - unsigned int PORT_CONNECTIVITY : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__VI { - struct { - unsigned int CONNECTION_LIST_ENTRY : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__VI { - struct { - unsigned int IMPEDANCE_SENSE : 31; - unsigned int PRESENCE_DETECT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__VI { - struct { - unsigned int SPEAKER_ALLOCATION : 7; - unsigned int : 1; - unsigned int HDMI_CONNECTION : 1; - unsigned int DP_CONNECTION : 1; - unsigned int EXTRA_CONNECTION_INFO : 6; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__VI { - struct { - unsigned int SINK_DESCRIPTION_LEN : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__VI { - struct { - unsigned int TAG : 6; - unsigned int : 1; - unsigned int ENABLE : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__VI { - struct { - unsigned int : 6; - unsigned int OUT_ENABLE : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__VI { - struct { - unsigned int WIRELESS_DISPLAY_IDENTIFICATION : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI { - struct { - unsigned int AUDIO_CHANNEL_CAPABILITIES : 1; - unsigned int INPUT_AMPLIFIER_PRESENT : 1; - unsigned int OUTPUT_AMPLIFIER_PRESENT : 1; - unsigned int AMPLIFIER_PARAMETER_OVERRIDE : 1; - unsigned int : 1; - unsigned int STRIPE : 1; - unsigned int PROCESSING_WIDGET : 1; - unsigned int UNSOLICITED_RESPONSE_CAPABILITY : 1; - unsigned int CONNECTION_LIST : 1; - unsigned int DIGITAL : 1; - unsigned int POWER_CONTROL : 1; - unsigned int LR_SWAP : 1; - unsigned int : 4; - unsigned int AUDIO_WIDGET_CAPABILITIES_DELAY : 4; - unsigned int TYPE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VI { - struct { - unsigned int IMPEDANCE_SENSE_CAPABLE : 1; - unsigned int TRIGGER_REQUIRED : 1; - unsigned int JACK_DETECTION_CAPABILITY : 1; - unsigned int HEADPHONE_DRIVE_CAPABLE : 1; - unsigned int OUTPUT_CAPABLE : 1; - unsigned int INPUT_CAPABLE : 1; - unsigned int BALANCED_I_O_PINS : 1; - unsigned int HDMI : 1; - unsigned int VREF_CONTROL : 8; - unsigned int EAPD_CAPABLE : 1; - unsigned int : 7; - unsigned int DP : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__VI { - struct { - unsigned int CONNECTION_LIST_LENGTH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__VI { - struct { - unsigned int IEC_60958_CS_MODE : 2; - unsigned int IEC_60958_CS_SOURCE_NUMBER : 4; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__VI { - struct { - unsigned int IEC_60958_CS_CLOCK_ACCURACY : 2; - unsigned int IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN : 1; - unsigned int IEC_60958_CS_WORD_LENGTH : 4; - unsigned int IEC_60958_CS_WORD_LENGTH_OVRRD_EN : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__VI { - struct { - unsigned int IEC_60958_CS_SAMPLING_FREQUENCY : 6; - unsigned int IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__VI { - struct { - unsigned int IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY : 4; - unsigned int IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__VI { - struct { - unsigned int IEC_60958_CS_SAMPLING_FREQUENCY_COEFF : 4; - unsigned int IEC_60958_CS_MPEG_SURROUND_INFO : 1; - unsigned int IEC_60958_CS_CGMS_A : 2; - unsigned int IEC_60958_CS_CGMS_A_VALID : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__VI { - struct { - unsigned int IEC_60958_CS_CHANNEL_NUMBER_L : 4; - unsigned int IEC_60958_CS_CHANNEL_NUMBER_R : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__VI { - struct { - unsigned int IEC_60958_CS_CHANNEL_NUMBER_2 : 4; - unsigned int IEC_60958_CS_CHANNEL_NUMBER_3 : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__VI { - struct { - unsigned int IEC_60958_CS_CHANNEL_NUMBER_4 : 4; - unsigned int IEC_60958_CS_CHANNEL_NUMBER_5 : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__VI { - struct { - unsigned int IEC_60958_CS_CHANNEL_NUMBER_6 : 4; - unsigned int IEC_60958_CS_CHANNEL_NUMBER_7 : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_FIFO_SIZE_CONTROL__VI { - struct { - unsigned int MIN_FIFO_SIZE : 7; - unsigned int : 1; - unsigned int MAX_FIFO_SIZE : 7; - unsigned int : 1; - unsigned int MAX_LATENCY_SUPPORT : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_GLOBAL_CAPABILITIES__VI { - struct { - unsigned int : 1; - unsigned int NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS : 2; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CHANNEL0__VI { - struct { - unsigned int INPUT_CRC_CHANNEL0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CHANNEL1__VI { - struct { - unsigned int INPUT_CRC_CHANNEL1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CHANNEL2__VI { - struct { - unsigned int INPUT_CRC_CHANNEL2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CHANNEL3__VI { - struct { - unsigned int INPUT_CRC_CHANNEL3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CHANNEL4__VI { - struct { - unsigned int INPUT_CRC_CHANNEL4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CHANNEL5__VI { - struct { - unsigned int INPUT_CRC_CHANNEL5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CHANNEL6__VI { - struct { - unsigned int INPUT_CRC_CHANNEL6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CHANNEL7__VI { - struct { - unsigned int INPUT_CRC_CHANNEL7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CONTROL0__VI { - struct { - unsigned int INPUT_CRC_EN : 1; - unsigned int : 3; - unsigned int INPUT_CRC_BLOCK_MODE : 1; - unsigned int : 3; - unsigned int INPUT_CRC_INSTANCE_SEL : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CONTROL1__VI { - struct { - unsigned int INPUT_CRC_BLOCK_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CONTROL2__VI { - struct { - unsigned int INPUT_CRC_BLOCK_ITERATION : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_CONTROL3__VI { - struct { - unsigned int INPUT_CRC_COMPLETE : 1; - unsigned int : 3; - unsigned int INPUT_CRC_BLOCK_COMPLETE_PHASE : 1; - unsigned int : 3; - unsigned int INPUT_CRC_CHANNEL_RESULT_SEL : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC0_RESULT__VI { - struct { - unsigned int INPUT_CRC_RESULT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CHANNEL0__VI { - struct { - unsigned int INPUT_CRC_CHANNEL0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CHANNEL1__VI { - struct { - unsigned int INPUT_CRC_CHANNEL1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CHANNEL2__VI { - struct { - unsigned int INPUT_CRC_CHANNEL2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CHANNEL3__VI { - struct { - unsigned int INPUT_CRC_CHANNEL3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CHANNEL4__VI { - struct { - unsigned int INPUT_CRC_CHANNEL4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CHANNEL5__VI { - struct { - unsigned int INPUT_CRC_CHANNEL5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CHANNEL6__VI { - struct { - unsigned int INPUT_CRC_CHANNEL6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CHANNEL7__VI { - struct { - unsigned int INPUT_CRC_CHANNEL7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CONTROL0__VI { - struct { - unsigned int INPUT_CRC_EN : 1; - unsigned int : 3; - unsigned int INPUT_CRC_BLOCK_MODE : 1; - unsigned int : 3; - unsigned int INPUT_CRC_INSTANCE_SEL : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CONTROL1__VI { - struct { - unsigned int INPUT_CRC_BLOCK_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CONTROL2__VI { - struct { - unsigned int INPUT_CRC_BLOCK_ITERATION : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_CONTROL3__VI { - struct { - unsigned int INPUT_CRC_COMPLETE : 1; - unsigned int : 3; - unsigned int INPUT_CRC_BLOCK_COMPLETE_PHASE : 1; - unsigned int : 3; - unsigned int INPUT_CRC_CHANNEL_RESULT_SEL : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_CRC1_RESULT__VI { - struct { - unsigned int INPUT_CRC_RESULT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_INPUT_PAYLOAD_CAPABILITY__VI { - struct { - unsigned int INPUT_PAYLOAD_CAPABILITY : 16; - unsigned int INSTRMPAY : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_MEM_PWR_CTRL__VI { - struct { - unsigned int AZ_MEM_PWR_FORCE : 2; - unsigned int AZ_MEM_PWR_DIS : 1; - unsigned int AZ_INPUT_STREAM0_MEM_PWR_FORCE : 2; - unsigned int AZ_INPUT_STREAM0_MEM_PWR_DIS : 1; - unsigned int AZ_INPUT_STREAM1_MEM_PWR_FORCE : 2; - unsigned int AZ_INPUT_STREAM1_MEM_PWR_DIS : 1; - unsigned int AZ_INPUT_STREAM2_MEM_PWR_FORCE : 2; - unsigned int AZ_INPUT_STREAM2_MEM_PWR_DIS : 1; - unsigned int AZ_INPUT_STREAM3_MEM_PWR_FORCE : 2; - unsigned int AZ_INPUT_STREAM3_MEM_PWR_DIS : 1; - unsigned int AZ_INPUT_STREAM4_MEM_PWR_FORCE : 2; - unsigned int AZ_INPUT_STREAM4_MEM_PWR_DIS : 1; - unsigned int AZ_INPUT_STREAM5_MEM_PWR_FORCE : 2; - unsigned int AZ_INPUT_STREAM5_MEM_PWR_DIS : 1; - unsigned int : 7; - unsigned int AZ_MEM_PWR_MODE_SEL : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_MEM_PWR_STATUS__VI { - struct { - unsigned int AZ_MEM_PWR_STATE : 2; - unsigned int AZ_INPUT_STREAM0_MEM_PWR_STATE : 2; - unsigned int AZ_INPUT_STREAM1_MEM_PWR_STATE : 2; - unsigned int AZ_INPUT_STREAM2_MEM_PWR_STATE : 2; - unsigned int AZ_INPUT_STREAM3_MEM_PWR_STATE : 2; - unsigned int AZ_INPUT_STREAM4_MEM_PWR_STATE : 2; - unsigned int AZ_INPUT_STREAM5_MEM_PWR_STATE : 2; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_OUTPUT_PAYLOAD_CAPABILITY__VI { - struct { - unsigned int OUTPUT_PAYLOAD_CAPABILITY : 16; - unsigned int OUTSTRMPAY : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__VI { - struct { - unsigned int LATENCY_HIDING_LEVEL : 8; - unsigned int SYS_MEM_ACTIVE_ENABLE : 1; - unsigned int : 7; - unsigned int INPUT_LATENCY_HIDING_LEVEL : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_SCLK_CONTROL__VI { - struct { - unsigned int : 2; - unsigned int : 2; - unsigned int AUDIO_SCLK_CONTROL : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_STREAM_DATA__VI { - struct { - unsigned int AZALIA_STREAM_REG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_STREAM_DEBUG__VI { - struct { - unsigned int STREAM_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZALIA_STREAM_INDEX__VI { - struct { - unsigned int AZALIA_STREAM_REG_INDEX : 8; - unsigned int AZALIA_STREAM_REG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__VI { - struct { - unsigned int IMMEDIATE_COMMAND_WRITE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__VI { - struct { - unsigned int IMMEDIATE_COMMAND_WRITE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__VI { - struct { - unsigned int IMMEDIATE_COMMAND_WRITE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__VI { - struct { - unsigned int IMMEDIATE_COMMAND_WRITE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__VI { - struct { - unsigned int IMMEDIATE_COMMAND_WRITE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__VI { - struct { - unsigned int IMMEDIATE_COMMAND_WRITE : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BF_ANA_ISO_CNTL__VI { - struct { - unsigned int BF_ANA_ISO_DIS_MASK : 1; - unsigned int BF_VDDC_ISO_DIS_MASK : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_ATOMIC_ERR_LOG__VI { - struct { - unsigned int UR_ATOMIC_OPCODE : 1; - unsigned int UR_ATOMIC_REQEN_LOW : 1; - unsigned int : 14; - unsigned int CLEAR_UR_ATOMIC_OPCODE : 1; - unsigned int CLEAR_UR_ATOMIC_REQEN_LOW : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_BME_STATUS__VI { - struct { - unsigned int DMA_ON_BME_LOW : 1; - unsigned int : 15; - unsigned int CLEAR_DMA_ON_BME_LOW : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_CLK_CTRL__VI { - struct { - unsigned int BIF_XSTCLK_READY : 1; - unsigned int BACO_XSTCLK_SWITCH_BYPASS : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_DOORBELL_APER_EN__VI { - struct { - unsigned int BIF_DOORBELL_APER_EN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_DOORBELL_GBLAPER1_LOWER__VI { - struct { - unsigned int : 2; - unsigned int DOORBELL_GBLAPER1_LOWER : 10; - unsigned int : 19; - unsigned int DOORBELL_GBLAPER1_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_DOORBELL_GBLAPER1_UPPER__VI { - struct { - unsigned int : 2; - unsigned int DOORBELL_GBLAPER1_UPPER : 10; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_DOORBELL_GBLAPER2_LOWER__VI { - struct { - unsigned int : 2; - unsigned int DOORBELL_GBLAPER2_LOWER : 10; - unsigned int : 19; - unsigned int DOORBELL_GBLAPER2_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_DOORBELL_GBLAPER2_UPPER__VI { - struct { - unsigned int : 2; - unsigned int DOORBELL_GBLAPER2_UPPER : 10; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_GPUIOV_FB_TOTAL_FB_INFO__VI { - struct { - unsigned int TOTAL_FB_AVAILABLE : 16; - unsigned int TOTAL_FB_CONSUMED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_GPUIOV_RESET_NOTIFICATION__VI { - struct { - unsigned int RESET_NOTIFICATION : 17; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_GPUIOV_VM_INIT_STATUS__VI { - struct { - unsigned int VM_INIT_STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_IOV_FUNC_IDENTIFIER__VI { - struct { - unsigned int FUNC_IDENTIFIER : 1; - unsigned int : 30; - unsigned int IOV_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_MM_INDACCESS_CNTL__VI { - struct { - unsigned int : 1; - unsigned int MM_INDACCESS_DIS : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_MST_TRANS_PENDING__VI { - struct { - unsigned int BIF_MST_TRANS_PENDING : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RB_BASE__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RB_CNTL__VI { - struct { - unsigned int RB_ENABLE : 1; - unsigned int RB_SIZE : 5; - unsigned int : 2; - unsigned int WPTR_WRITEBACK_ENABLE : 1; - unsigned int WPTR_WRITEBACK_TIMER : 5; - unsigned int : 3; - unsigned int BIF_RB_TRAN : 1; - unsigned int : 13; - unsigned int WPTR_OVERFLOW_CLEAR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RB_RPTR__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RB_WPTR__VI { - struct { - unsigned int BIF_RB_OVERFLOW : 1; - unsigned int : 1; - unsigned int OFFSET : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RB_WPTR_ADDR_HI__VI { - struct { - unsigned int ADDR : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RB_WPTR_ADDR_LO__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_MST_SMBUS_CMDSTATUS__VI { - struct { - unsigned int REG_SMBUS_clkGate_timer : 8; - unsigned int REG_SMBUS_clkSetup_timer : 4; - unsigned int : 4; - unsigned int REG_SMBUS_timeout_timer : 8; - unsigned int SMBUS_RFE_mstTimeout : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RFE_WARMRST_CNTL__VI { - struct { - unsigned int REG_RST_warmRstRfeEn : 1; - unsigned int REG_RST_warmRstImpEn : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_RLC_INTR_CNTL__VI { - struct { - unsigned int RLC_HVCMD_INTERRUPT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SLV_TRANS_PENDING__VI { - struct { - unsigned int BIF_SLV_TRANS_PENDING : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SMU_DATA__VI { - struct { - unsigned int : 2; - unsigned int BIF_SMU_DATA : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_SMU_INDEX__VI { - struct { - unsigned int : 2; - unsigned int BIF_SMU_INDEX : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_FB_CMP__VI { - struct { - unsigned int VDDGFX_FB_HDP_CMP_EN : 1; - unsigned int VDDGFX_FB_HDP_STALL_EN : 1; - unsigned int VDDGFX_FB_XDMA_CMP_EN : 1; - unsigned int VDDGFX_FB_XDMA_STALL_EN : 1; - unsigned int VDDGFX_FB_VGA_CMP_EN : 1; - unsigned int VDDGFX_FB_VGA_STALL_EN : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX0_LOWER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX0_REG_LOWER : 16; - unsigned int : 12; - unsigned int VDDGFX_GFX0_REG_CMP_EN : 1; - unsigned int VDDGFX_GFX0_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX0_UPPER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX0_REG_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX1_LOWER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX1_REG_LOWER : 16; - unsigned int : 12; - unsigned int VDDGFX_GFX1_REG_CMP_EN : 1; - unsigned int VDDGFX_GFX1_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX1_UPPER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX1_REG_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX2_LOWER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX2_REG_LOWER : 16; - unsigned int : 12; - unsigned int VDDGFX_GFX2_REG_CMP_EN : 1; - unsigned int VDDGFX_GFX2_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX2_UPPER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX2_REG_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX3_LOWER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX3_REG_LOWER : 16; - unsigned int : 12; - unsigned int VDDGFX_GFX3_REG_CMP_EN : 1; - unsigned int VDDGFX_GFX3_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX3_UPPER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX3_REG_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX4_LOWER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX4_REG_LOWER : 16; - unsigned int : 12; - unsigned int VDDGFX_GFX4_REG_CMP_EN : 1; - unsigned int VDDGFX_GFX4_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX4_UPPER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX4_REG_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX5_LOWER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX5_REG_LOWER : 16; - unsigned int : 12; - unsigned int VDDGFX_GFX5_REG_CMP_EN : 1; - unsigned int VDDGFX_GFX5_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_GFX5_UPPER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_GFX5_REG_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_RSV1_LOWER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_RSV1_REG_LOWER : 16; - unsigned int : 12; - unsigned int VDDGFX_RSV1_REG_CMP_EN : 1; - unsigned int VDDGFX_RSV1_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_RSV1_UPPER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_RSV1_REG_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_RSV2_LOWER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_RSV2_REG_LOWER : 16; - unsigned int : 12; - unsigned int VDDGFX_RSV2_REG_CMP_EN : 1; - unsigned int VDDGFX_RSV2_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_RSV2_UPPER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_RSV2_REG_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_RSV3_LOWER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_RSV3_REG_LOWER : 16; - unsigned int : 12; - unsigned int VDDGFX_RSV3_REG_CMP_EN : 1; - unsigned int VDDGFX_RSV3_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_RSV3_UPPER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_RSV3_REG_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_RSV4_LOWER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_RSV4_REG_LOWER : 16; - unsigned int : 12; - unsigned int VDDGFX_RSV4_REG_CMP_EN : 1; - unsigned int VDDGFX_RSV4_REG_STALL_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VDDGFX_RSV4_UPPER__VI { - struct { - unsigned int : 2; - unsigned int VDDGFX_RSV4_REG_UPPER : 16; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BIF_VIRT_RESET_REQ__VI { - struct { - unsigned int VIRT_RESET_REQ_VF : 16; - unsigned int : 15; - unsigned int VIRT_RESET_REQ_SOFTPF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BLND_CONTROL__VI { - struct { - unsigned int BLND_GLOBAL_GAIN : 8; - unsigned int BLND_MODE : 2; - unsigned int BLND_STEREO_TYPE : 2; - unsigned int BLND_STEREO_POLARITY : 1; - unsigned int BLND_FEEDTHROUGH_EN : 1; - unsigned int : 2; - unsigned int BLND_ALPHA_MODE : 2; - unsigned int : 2; - unsigned int BLND_MULTIPLIED_MODE : 1; - unsigned int : 3; - unsigned int BLND_GLOBAL_ALPHA : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BLND_CONTROL2__VI { - struct { - unsigned int PTI_ENABLE : 1; - unsigned int : 3; - unsigned int PTI_NEW_PIXEL_GAP : 2; - unsigned int BLND_NEW_PIXEL_MODE : 1; - unsigned int BLND_SUPERAA_DEGAMMA_EN : 1; - unsigned int BLND_SUPERAA_REGAMMA_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BLND_DEBUG__VI { - struct { - unsigned int BLND_CNV_MUX_SELECT : 1; - unsigned int BLND_DEBUG : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BLND_REG_UPDATE_STATUS__VI { - struct { - unsigned int DCP_BLNDC_GRPH_UPDATE_PENDING : 1; - unsigned int DCP_BLNDO_GRPH_UPDATE_PENDING : 1; - unsigned int DCP_BLNDC_GRPH_SURF_UPDATE_PENDING : 1; - unsigned int DCP_BLNDO_GRPH_SURF_UPDATE_PENDING : 1; - unsigned int DCP_BLNDC_OVL_UPDATE_PENDING : 1; - unsigned int DCP_BLNDO_OVL_UPDATE_PENDING : 1; - unsigned int DCP_BLNDC_CUR_UPDATE_PENDING : 1; - unsigned int DCP_BLNDO_CUR_UPDATE_PENDING : 1; - unsigned int SCL_BLNDC_UPDATE_PENDING : 1; - unsigned int SCL_BLNDO_UPDATE_PENDING : 1; - unsigned int BLND_BLNDC_UPDATE_PENDING : 1; - unsigned int BLND_BLNDO_UPDATE_PENDING : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BLND_TEST_DEBUG_DATA__VI { - struct { - unsigned int BLND_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BLND_TEST_DEBUG_INDEX__VI { - struct { - unsigned int BLND_TEST_DEBUG_INDEX : 8; - unsigned int BLND_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BLND_UNDERFLOW_INTERRUPT__VI { - struct { - unsigned int BLND_UNDERFLOW_INT_OCCURED : 1; - unsigned int : 7; - unsigned int BLND_UNDERFLOW_INT_ACK : 1; - unsigned int : 3; - unsigned int BLND_UNDERFLOW_INT_MASK : 1; - unsigned int : 3; - unsigned int BLND_UNDERFLOW_INT_PIPE_INDEX : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BLND_UPDATE__VI { - struct { - unsigned int BLND_UPDATE_PENDING : 1; - unsigned int : 7; - unsigned int BLND_UPDATE_TAKEN : 1; - unsigned int : 7; - unsigned int BLND_UPDATE_LOCK : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BLND_V_UPDATE_LOCK__VI { - struct { - unsigned int BLND_DCP_GRPH_V_UPDATE_LOCK : 1; - unsigned int BLND_DCP_GRPH_SURF_V_UPDATE_LOCK : 1; - unsigned int : 6; - unsigned int BLND_DCP_OVL_V_UPDATE_LOCK : 1; - unsigned int : 7; - unsigned int BLND_DCP_CUR_V_UPDATE_LOCK : 1; - unsigned int : 7; - unsigned int BLND_DCP_CUR2_V_UPDATE_LOCK : 1; - unsigned int : 3; - unsigned int BLND_SCL_V_UPDATE_LOCK : 1; - unsigned int BLND_BLND_V_UPDATE_LOCK : 1; - unsigned int : 1; - unsigned int BLND_V_UPDATE_LOCK_MODE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BPHYC_DAC_AUTO_CALIB_CONTROL__VI { - struct { - unsigned int BPHYC_DAC_CAL_INITB : 1; - unsigned int BPHYC_DAC_CAL_EN : 1; - unsigned int BPHYC_DAC_CAL_DACADJ_EN : 1; - unsigned int : 1; - unsigned int BPHYC_DAC_CAL_WAIT_ADJUST : 10; - unsigned int : 6; - unsigned int BPHYC_DAC_CAL_MASK : 3; - unsigned int : 5; - unsigned int BPHYC_DAC_CAL_COMPLETE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BPHYC_DAC_MACRO_CNTL__VI { - struct { - unsigned int BPHYC_DAC_WHITE_LEVEL : 2; - unsigned int : 6; - unsigned int BPHYC_DAC_WHITE_FINE_CONTROL : 6; - unsigned int : 2; - unsigned int BPHYC_DAC_BANDGAP_ADJUSTMENT : 6; - unsigned int : 2; - unsigned int BPHYC_DAC_ANALOG_MONITOR : 4; - unsigned int BPHYC_DAC_COREMON : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union BX_RESET_CNTL__VI { - struct { - unsigned int LINK_TRAIN_EN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_DCC_BASE__VI { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR0_DCC_CONTROL__VI { - struct { - unsigned int OVERWRITE_COMBINER_DISABLE : 1; - unsigned int KEY_CLEAR_ENABLE : 1; - unsigned int MAX_UNCOMPRESSED_BLOCK_SIZE : 2; - unsigned int MIN_COMPRESSED_BLOCK_SIZE : 1; - unsigned int MAX_COMPRESSED_BLOCK_SIZE : 2; - unsigned int COLOR_TRANSFORM : 2; - unsigned int INDEPENDENT_64B_BLOCKS : 1; - unsigned int LOSSY_RGB_PRECISION : 4; - unsigned int LOSSY_ALPHA_PRECISION : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_DCC_BASE__VI { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR1_DCC_CONTROL__VI { - struct { - unsigned int OVERWRITE_COMBINER_DISABLE : 1; - unsigned int KEY_CLEAR_ENABLE : 1; - unsigned int MAX_UNCOMPRESSED_BLOCK_SIZE : 2; - unsigned int MIN_COMPRESSED_BLOCK_SIZE : 1; - unsigned int MAX_COMPRESSED_BLOCK_SIZE : 2; - unsigned int COLOR_TRANSFORM : 2; - unsigned int INDEPENDENT_64B_BLOCKS : 1; - unsigned int LOSSY_RGB_PRECISION : 4; - unsigned int LOSSY_ALPHA_PRECISION : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_DCC_BASE__VI { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR2_DCC_CONTROL__VI { - struct { - unsigned int OVERWRITE_COMBINER_DISABLE : 1; - unsigned int KEY_CLEAR_ENABLE : 1; - unsigned int MAX_UNCOMPRESSED_BLOCK_SIZE : 2; - unsigned int MIN_COMPRESSED_BLOCK_SIZE : 1; - unsigned int MAX_COMPRESSED_BLOCK_SIZE : 2; - unsigned int COLOR_TRANSFORM : 2; - unsigned int INDEPENDENT_64B_BLOCKS : 1; - unsigned int LOSSY_RGB_PRECISION : 4; - unsigned int LOSSY_ALPHA_PRECISION : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_DCC_BASE__VI { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR3_DCC_CONTROL__VI { - struct { - unsigned int OVERWRITE_COMBINER_DISABLE : 1; - unsigned int KEY_CLEAR_ENABLE : 1; - unsigned int MAX_UNCOMPRESSED_BLOCK_SIZE : 2; - unsigned int MIN_COMPRESSED_BLOCK_SIZE : 1; - unsigned int MAX_COMPRESSED_BLOCK_SIZE : 2; - unsigned int COLOR_TRANSFORM : 2; - unsigned int INDEPENDENT_64B_BLOCKS : 1; - unsigned int LOSSY_RGB_PRECISION : 4; - unsigned int LOSSY_ALPHA_PRECISION : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_DCC_BASE__VI { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR4_DCC_CONTROL__VI { - struct { - unsigned int OVERWRITE_COMBINER_DISABLE : 1; - unsigned int KEY_CLEAR_ENABLE : 1; - unsigned int MAX_UNCOMPRESSED_BLOCK_SIZE : 2; - unsigned int MIN_COMPRESSED_BLOCK_SIZE : 1; - unsigned int MAX_COMPRESSED_BLOCK_SIZE : 2; - unsigned int COLOR_TRANSFORM : 2; - unsigned int INDEPENDENT_64B_BLOCKS : 1; - unsigned int LOSSY_RGB_PRECISION : 4; - unsigned int LOSSY_ALPHA_PRECISION : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_DCC_BASE__VI { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR5_DCC_CONTROL__VI { - struct { - unsigned int OVERWRITE_COMBINER_DISABLE : 1; - unsigned int KEY_CLEAR_ENABLE : 1; - unsigned int MAX_UNCOMPRESSED_BLOCK_SIZE : 2; - unsigned int MIN_COMPRESSED_BLOCK_SIZE : 1; - unsigned int MAX_COMPRESSED_BLOCK_SIZE : 2; - unsigned int COLOR_TRANSFORM : 2; - unsigned int INDEPENDENT_64B_BLOCKS : 1; - unsigned int LOSSY_RGB_PRECISION : 4; - unsigned int LOSSY_ALPHA_PRECISION : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_DCC_BASE__VI { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR6_DCC_CONTROL__VI { - struct { - unsigned int OVERWRITE_COMBINER_DISABLE : 1; - unsigned int KEY_CLEAR_ENABLE : 1; - unsigned int MAX_UNCOMPRESSED_BLOCK_SIZE : 2; - unsigned int MIN_COMPRESSED_BLOCK_SIZE : 1; - unsigned int MAX_COMPRESSED_BLOCK_SIZE : 2; - unsigned int COLOR_TRANSFORM : 2; - unsigned int INDEPENDENT_64B_BLOCKS : 1; - unsigned int LOSSY_RGB_PRECISION : 4; - unsigned int LOSSY_ALPHA_PRECISION : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_DCC_BASE__VI { - struct { - unsigned int BASE_256B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_COLOR7_DCC_CONTROL__VI { - struct { - unsigned int OVERWRITE_COMBINER_DISABLE : 1; - unsigned int KEY_CLEAR_ENABLE : 1; - unsigned int MAX_UNCOMPRESSED_BLOCK_SIZE : 2; - unsigned int MIN_COMPRESSED_BLOCK_SIZE : 1; - unsigned int MAX_COMPRESSED_BLOCK_SIZE : 2; - unsigned int COLOR_TRANSFORM : 2; - unsigned int INDEPENDENT_64B_BLOCKS : 1; - unsigned int LOSSY_RGB_PRECISION : 4; - unsigned int LOSSY_ALPHA_PRECISION : 4; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DCC_CONFIG__VI { - struct { - unsigned int OVERWRITE_COMBINER_DEPTH : 5; - unsigned int OVERWRITE_COMBINER_DISABLE : 1; - unsigned int OVERWRITE_COMBINER_CC_POP_DISABLE : 1; - unsigned int : 1; - unsigned int FC_RDLAT_KEYID_FIFO_DEPTH : 8; - unsigned int READ_RETURN_SKID_FIFO_DEPTH : 7; - unsigned int : 1; - unsigned int DCC_CACHE_EVICT_POINT : 4; - unsigned int DCC_CACHE_NUM_TAGS : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DCC_CONTROL__VI { - struct { - unsigned int OVERWRITE_COMBINER_DISABLE : 1; - unsigned int OVERWRITE_COMBINER_MRT_SHARING_DISABLE : 1; - unsigned int OVERWRITE_COMBINER_WATERMARK : 5; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_19__VI { - struct { - unsigned int SURF_SYNC_STATE : 2; - unsigned int SURF_SYNC_START : 1; - unsigned int SF_BUSY : 1; - unsigned int CS_BUSY : 1; - unsigned int RB_BUSY : 1; - unsigned int DS_BUSY : 1; - unsigned int TB_BUSY : 1; - unsigned int IB_BUSY : 1; - unsigned int DRR_BUSY : 1; - unsigned int DF_BUSY : 1; - unsigned int DD_BUSY : 1; - unsigned int DC_BUSY : 1; - unsigned int DK_BUSY : 1; - unsigned int DF_SKID_FIFO_EMPTY : 1; - unsigned int DF_CLEAR_FIFO_EMPTY : 1; - unsigned int DD_READY : 1; - unsigned int DC_FIFO_FULL : 1; - unsigned int DC_READY : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_20__VI { - struct { - unsigned int MC_RDREQ_CREDITS : 6; - unsigned int MC_WRREQ_CREDITS : 6; - unsigned int CC_RDREQ_HAD_ITS_TURN : 1; - unsigned int FC_RDREQ_HAD_ITS_TURN : 1; - unsigned int CM_RDREQ_HAD_ITS_TURN : 1; - unsigned int : 1; - unsigned int CC_WRREQ_HAD_ITS_TURN : 1; - unsigned int FC_WRREQ_HAD_ITS_TURN : 1; - unsigned int CM_WRREQ_HAD_ITS_TURN : 1; - unsigned int : 1; - unsigned int CC_WRREQ_FIFO_EMPTY : 1; - unsigned int FC_WRREQ_FIFO_EMPTY : 1; - unsigned int CM_WRREQ_FIFO_EMPTY : 1; - unsigned int DCC_WRREQ_FIFO_EMPTY : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_21__VI { - struct { - unsigned int CM_BUSY : 1; - unsigned int FC_BUSY : 1; - unsigned int CC_BUSY : 1; - unsigned int BB_BUSY : 1; - unsigned int MA_BUSY : 1; - unsigned int CORE_SCLK_VLD : 1; - unsigned int REG_SCLK1_VLD : 1; - unsigned int REG_SCLK0_VLD : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CB_DEBUG_BUS_22__VI { - struct { - unsigned int OUTSTANDING_MC_READS : 12; - unsigned int OUTSTANDING_MC_WRITES : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_DC_PIPE_DIS__VI { - struct { - unsigned int : 1; - unsigned int DC_PIPE_DIS : 6; - unsigned int : 1; - unsigned int MCIF_WB_URG_OVRD : 1; - unsigned int MCIF_WB_URG_LVL : 4; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_FCTRL_FUSES__VI { - struct { - unsigned int : 1; - unsigned int EXT_EFUSE_MACRO_PRESENT : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_GC_SHADER_RATE_CONFIG__VI { - struct { - unsigned int : 1; - unsigned int DPFP_RATE : 2; - unsigned int SQC_BALANCE_DISABLE : 1; - unsigned int HALF_LDS : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_HARVEST_FUSES__VI { - struct { - unsigned int : 1; - unsigned int VCE_DISABLE : 2; - unsigned int : 1; - unsigned int UVD_DISABLE : 1; - unsigned int : 1; - unsigned int ACP_EXISTS : 1; - unsigned int : 1; - unsigned int DC_DISABLE : 6; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__VI { - struct { - unsigned int INPUT_PORT_CONNECTIVITY : 3; - unsigned int : 1; - unsigned int INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__VI { - struct { - unsigned int PORT_CONNECTIVITY : 3; - unsigned int : 1; - unsigned int PORT_CONNECTIVITY_OVERRIDE_ENABLE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CFG_LNC_WINDOW__VI { - struct { - unsigned int CFG_LNC_WINDOW0 : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_CLKPIN_CNTL_DC__VI { - struct { - unsigned int OSC_EN : 1; - unsigned int XTL_LOW_GAIN : 2; - unsigned int : 6; - unsigned int XTL_XOCLK_DRV_R_EN : 1; - unsigned int XTALIN_SEL : 3; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_MCLK_CNTL__VI { - struct { - unsigned int MCLK_DIVIDER : 7; - unsigned int : 1; - unsigned int MCLK_DIR_CNTL_EN : 1; - unsigned int MCLK_DIR_CNTL_TOG : 1; - unsigned int MCLK_DIR_CNTL_DIVIDER : 7; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_MCLK_STATUS__VI { - struct { - unsigned int MCLK_STATUS : 1; - unsigned int MCLK_DIR_CNTL_DONETOG : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CG_SPLL_FUNC_CNTL_7__VI { - struct { - unsigned int SPLL_BW_CNTRL : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT0_OFFSET_HI__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT1_OFFSET_HI__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT2_OFFSET_HI__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_BM__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_CD0__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_CD1__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_CD2__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_CD3__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_CK0__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_CK1__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_CK2__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_CK3__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_K0__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_K1__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_K2__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_K3__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_OFFSET__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_OFFSET_HI__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT3_STATUS__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_BM__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_CD0__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_CD1__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_CD2__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_CD3__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_CK0__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_CK1__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_CK2__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_CK3__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_K0__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_K1__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_K2__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_K3__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_OFFSET__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_OFFSET_HI__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLIENT4_STATUS__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CLKREQB_PERF_COUNTER__VI { - struct { - unsigned int CLKREQB_PERF_COUNTER_LOWER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_C11_C12__VI { - struct { - unsigned int CNV_CSC_C11 : 13; - unsigned int : 3; - unsigned int CNV_CSC_C12 : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_C13_C14__VI { - struct { - unsigned int CNV_CSC_C13 : 13; - unsigned int : 3; - unsigned int CNV_CSC_C14 : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_C21_C22__VI { - struct { - unsigned int CNV_CSC_C21 : 13; - unsigned int : 3; - unsigned int CNV_CSC_C22 : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_C23_C24__VI { - struct { - unsigned int CNV_CSC_C23 : 13; - unsigned int : 3; - unsigned int CNV_CSC_C24 : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_C31_C32__VI { - struct { - unsigned int CNV_CSC_C31 : 13; - unsigned int : 3; - unsigned int CNV_CSC_C32 : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_C33_C34__VI { - struct { - unsigned int CNV_CSC_C33 : 13; - unsigned int : 3; - unsigned int CNV_CSC_C34 : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_CLAMP_B__VI { - struct { - unsigned int CNV_CSC_CLAMP_UPPER_B : 16; - unsigned int CNV_CSC_CLAMP_LOWER_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_CLAMP_G__VI { - struct { - unsigned int CNV_CSC_CLAMP_UPPER_G : 16; - unsigned int CNV_CSC_CLAMP_LOWER_G : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_CLAMP_R__VI { - struct { - unsigned int CNV_CSC_CLAMP_UPPER_R : 16; - unsigned int CNV_CSC_CLAMP_LOWER_R : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_CONTROL__VI { - struct { - unsigned int CNV_CSC_BYPASS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_ROUND_OFFSET_B__VI { - struct { - unsigned int CNV_CSC_ROUND_OFFSET_B : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_ROUND_OFFSET_G__VI { - struct { - unsigned int CNV_CSC_ROUND_OFFSET_G : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_CSC_ROUND_OFFSET_R__VI { - struct { - unsigned int CNV_CSC_ROUND_OFFSET_R : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_INPUT_SELECT__VI { - struct { - unsigned int CNV_INPUT_SRC_SELECT : 2; - unsigned int CNV_INPUT_PIPE_SELECT : 3; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_MODE__VI { - struct { - unsigned int : 8; - unsigned int CNV_FRAME_CAPTURE_RATE : 2; - unsigned int : 2; - unsigned int CNV_WINDOW_CROP_EN : 1; - unsigned int CNV_STEREO_TYPE : 2; - unsigned int CNV_INTERLACED_MODE : 1; - unsigned int CNV_EYE_SELECTION : 2; - unsigned int CNV_STEREO_POLARITY : 1; - unsigned int CNV_INTERLACED_FIELD_ORDER : 1; - unsigned int CNV_STEREO_SPLIT : 1; - unsigned int : 3; - unsigned int CNV_NEW_CONTENT : 1; - unsigned int : 6; - unsigned int CNV_FRAME_CAPTURE_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_SOURCE_SIZE__VI { - struct { - unsigned int CNV_SOURCE_WIDTH : 15; - unsigned int : 1; - unsigned int CNV_SOURCE_HEIGHT : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_TEST_CNTL__VI { - struct { - unsigned int : 4; - unsigned int CNV_TEST_CRC_EN : 1; - unsigned int : 3; - unsigned int CNV_TEST_CRC_CONT_EN : 1; - unsigned int : 7; - unsigned int CNV_TEST_CRC_DE_ONLY : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_TEST_CRC_BLUE__VI { - struct { - unsigned int : 4; - unsigned int CNV_TEST_CRC_BLUE_MASK : 12; - unsigned int CNV_TEST_CRC_SIG_BLUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_TEST_CRC_GREEN__VI { - struct { - unsigned int : 4; - unsigned int CNV_TEST_CRC_GREEN_MASK : 12; - unsigned int CNV_TEST_CRC_SIG_GREEN : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_TEST_CRC_RED__VI { - struct { - unsigned int : 4; - unsigned int CNV_TEST_CRC_RED_MASK : 12; - unsigned int CNV_TEST_CRC_SIG_RED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_TEST_DEBUG_DATA__VI { - struct { - unsigned int CNV_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_TEST_DEBUG_INDEX__VI { - struct { - unsigned int CNV_TEST_DEBUG_INDEX : 8; - unsigned int CNV_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_UPDATE__VI { - struct { - unsigned int CNV_UPDATE_PENDING : 1; - unsigned int : 7; - unsigned int CNV_UPDATE_TAKEN : 1; - unsigned int : 7; - unsigned int CNV_UPDATE_LOCK : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_WINDOW_SIZE__VI { - struct { - unsigned int CNV_WINDOW_WIDTH : 12; - unsigned int : 4; - unsigned int CNV_WINDOW_HEIGHT : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CNV_WINDOW_START__VI { - struct { - unsigned int CNV_WINDOW_START_X : 12; - unsigned int : 4; - unsigned int CNV_WINDOW_START_Y : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COL_MAN_DEBUG_CONTROL__VI { - struct { - unsigned int COL_MAN_GLOBAL_PASSTHROUGH_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COL_MAN_FP_CONVERTED_FIELD__VI { - struct { - unsigned int COL_MAN_FP_CONVERTED_FIELD_DATA : 18; - unsigned int : 2; - unsigned int COL_MAN_FP_CONVERTED_FIELD_INDEX : 6; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COL_MAN_INPUT_CSC_CONTROL__VI { - struct { - unsigned int INPUT_CSC_MODE : 2; - unsigned int INPUT_CSC_INPUT_TYPE : 2; - unsigned int INPUT_CSC_CONVERSION_MODE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COL_MAN_OUTPUT_CSC_CONTROL__VI { - struct { - unsigned int OUTPUT_CSC_MODE : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COL_MAN_TEST_DEBUG_DATA__VI { - struct { - unsigned int COL_MAN_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COL_MAN_TEST_DEBUG_INDEX__VI { - struct { - unsigned int COL_MAN_TEST_DEBUG_INDEX : 8; - unsigned int COL_MAN_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COL_MAN_UPDATE__VI { - struct { - unsigned int COL_MAN_UPDATE_PENDING : 1; - unsigned int COL_MAN_UPDATE_TAKEN : 1; - unsigned int : 14; - unsigned int COL_MAN_UPDATE_LOCK : 1; - unsigned int : 7; - unsigned int COL_MAN_DISABLE_MULTIPLE_UPDATE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXA_TRANS_C11_C12__VI { - struct { - unsigned int COMM_MATRIXA_TRANS_C11 : 16; - unsigned int COMM_MATRIXA_TRANS_C12 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXA_TRANS_C13_C14__VI { - struct { - unsigned int COMM_MATRIXA_TRANS_C13 : 16; - unsigned int COMM_MATRIXA_TRANS_C14 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXA_TRANS_C21_C22__VI { - struct { - unsigned int COMM_MATRIXA_TRANS_C21 : 16; - unsigned int COMM_MATRIXA_TRANS_C22 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXA_TRANS_C23_C24__VI { - struct { - unsigned int COMM_MATRIXA_TRANS_C23 : 16; - unsigned int COMM_MATRIXA_TRANS_C24 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXA_TRANS_C31_C32__VI { - struct { - unsigned int COMM_MATRIXA_TRANS_C31 : 16; - unsigned int COMM_MATRIXA_TRANS_C32 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXA_TRANS_C33_C34__VI { - struct { - unsigned int COMM_MATRIXA_TRANS_C33 : 16; - unsigned int COMM_MATRIXA_TRANS_C34 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXB_TRANS_C11_C12__VI { - struct { - unsigned int COMM_MATRIXB_TRANS_C11 : 16; - unsigned int COMM_MATRIXB_TRANS_C12 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXB_TRANS_C13_C14__VI { - struct { - unsigned int COMM_MATRIXB_TRANS_C13 : 16; - unsigned int COMM_MATRIXB_TRANS_C14 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXB_TRANS_C21_C22__VI { - struct { - unsigned int COMM_MATRIXB_TRANS_C21 : 16; - unsigned int COMM_MATRIXB_TRANS_C22 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXB_TRANS_C23_C24__VI { - struct { - unsigned int COMM_MATRIXB_TRANS_C23 : 16; - unsigned int COMM_MATRIXB_TRANS_C24 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXB_TRANS_C31_C32__VI { - struct { - unsigned int COMM_MATRIXB_TRANS_C31 : 16; - unsigned int COMM_MATRIXB_TRANS_C32 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMM_MATRIXB_TRANS_C33_C34__VI { - struct { - unsigned int COMM_MATRIXB_TRANS_C33 : 16; - unsigned int COMM_MATRIXB_TRANS_C34 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_DISPATCH_ID__VI { - struct { - unsigned int DISPATCH_ID : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_NOWHERE__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_RELAUNCH__VI { - struct { - unsigned int PAYLOAD : 30; - unsigned int IS_EVENT : 1; - unsigned int IS_STATE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_THREADGROUP_ID__VI { - struct { - unsigned int THREADGROUP_ID : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_WAVE_RESTORE_ADDR_HI__VI { - struct { - unsigned int ADDR : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_WAVE_RESTORE_ADDR_LO__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union COMPUTE_WAVE_RESTORE_CONTROL__VI { - struct { - unsigned int ATC : 1; - unsigned int MTYPE : 2; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CONFIG_RESERVED__VI { - struct { - unsigned int CONFIG_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED0__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED1__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED10__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED11__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED2__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED3__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED4__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED5__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED6__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED7__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED8__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPLL_MACRO_CNTL_RESERVED9__VI { - struct { - unsigned int CPLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CPM_CONTROL__VI { - struct { - unsigned int LCLK_DYN_GATE_ENABLE : 1; - unsigned int TXCLK_DYN_GATE_ENABLE : 1; - unsigned int TXCLK_PERM_GATE_ENABLE : 1; - unsigned int TXCLK_PIF_GATE_ENABLE : 1; - unsigned int TXCLK_GSKT_GATE_ENABLE : 1; - unsigned int TXCLK_LCNT_GATE_ENABLE : 1; - unsigned int TXCLK_REGS_GATE_ENABLE : 1; - unsigned int TXCLK_PRBS_GATE_ENABLE : 1; - unsigned int REFCLK_REGS_GATE_ENABLE : 1; - unsigned int LCLK_DYN_GATE_LATENCY : 1; - unsigned int TXCLK_DYN_GATE_LATENCY : 1; - unsigned int TXCLK_PERM_GATE_LATENCY : 1; - unsigned int TXCLK_REGS_GATE_LATENCY : 1; - unsigned int REFCLK_REGS_GATE_LATENCY : 1; - unsigned int LCLK_GATE_TXCLK_FREE : 1; - unsigned int RCVR_DET_CLK_ENABLE : 1; - unsigned int TXCLK_PERM_GATE_PLL_PDN : 1; - unsigned int FAST_TXCLK_LATENCY : 3; - unsigned int MASTER_PCIE_PLL_SELECT : 1; - unsigned int MASTER_PCIE_PLL_AUTO : 1; - unsigned int REFCLK_XSTCLK_ENABLE : 1; - unsigned int REFCLK_XSTCLK_LATENCY : 1; - unsigned int SPARE_REGS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_COMPLETION_STATUS__VI { - struct { - unsigned int STATUS : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_METADATA_BASE_ADDR__VI { - struct { - unsigned int ADDR_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_METADATA_BASE_ADDR_HI__VI { - struct { - unsigned int ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CE_RB_OFFSET__VI { - struct { - unsigned int RB_OFFSET : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_IC_BASE_CNTL__VI { - struct { - unsigned int VMID : 4; - unsigned int : 19; - unsigned int ATC : 1; - unsigned int CACHE_POLICY : 1; - unsigned int : 2; - unsigned int MTYPE : 2; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_IC_BASE_HI__VI { - struct { - unsigned int IC_BASE_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_IC_BASE_LO__VI { - struct { - unsigned int : 12; - unsigned int IC_BASE_LO : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_IC_OP_CNTL__VI { - struct { - unsigned int INVALIDATE_CACHE : 1; - unsigned int : 3; - unsigned int PRIME_ICACHE : 1; - unsigned int ICACHE_PRIMED : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_CPC_MGCG_SYNC_CNTL__VI { - struct { - unsigned int COOLDOWN_PERIOD : 8; - unsigned int WARMUP_PERIOD : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DFY_CMD__VI { - struct { - unsigned int OFFSET : 9; - unsigned int : 7; - unsigned int SIZE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DISPATCH_INDR_ADDR__VI { - struct { - unsigned int ADDR_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DISPATCH_INDR_ADDR_HI__VI { - struct { - unsigned int ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DRAW_INDX_INDR_ADDR__VI { - struct { - unsigned int ADDR_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DRAW_INDX_INDR_ADDR_HI__VI { - struct { - unsigned int ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DRAW_OBJECT__VI { - struct { - unsigned int OBJECT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DRAW_OBJECT_COUNTER__VI { - struct { - unsigned int COUNT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DRAW_WINDOW_CNTL__VI { - struct { - unsigned int DISABLE_DRAW_WINDOW_LO_MAX : 1; - unsigned int DISABLE_DRAW_WINDOW_LO_MIN : 1; - unsigned int DISABLE_DRAW_WINDOW_HI : 1; - unsigned int : 5; - unsigned int MODE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DRAW_WINDOW_HI__VI { - struct { - unsigned int WINDOW_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DRAW_WINDOW_LO__VI { - struct { - unsigned int MIN : 16; - unsigned int MAX : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_DRAW_WINDOW_MASK_HI__VI { - struct { - unsigned int WINDOW_MASK_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_EOP_DONE_CNTX_ID__VI { - struct { - unsigned int CNTX_ID : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_GDS_BKUP_ADDR__VI { - struct { - unsigned int ADDR_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_GDS_BKUP_ADDR_HI__VI { - struct { - unsigned int ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HPD_STATUS0__VI { - struct { - unsigned int QUEUE_STATE : 5; - unsigned int MAPPED_QUEUE : 3; - unsigned int QUEUE_AVAILABLE : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_CNTL_STACK_OFFSET__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 13; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_CNTL_STACK_SIZE__VI { - struct { - unsigned int : 12; - unsigned int SIZE : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_CTX_SAVE_BASE_ADDR_HI__VI { - struct { - unsigned int ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_CTX_SAVE_BASE_ADDR_LO__VI { - struct { - unsigned int : 12; - unsigned int ADDR : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_CTX_SAVE_CONTROL__VI { - struct { - unsigned int ATC : 1; - unsigned int MTYPE : 2; - unsigned int POLICY : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_CTX_SAVE_SIZE__VI { - struct { - unsigned int : 12; - unsigned int SIZE : 13; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_EOP_BASE_ADDR__VI { - struct { - unsigned int BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_EOP_BASE_ADDR_HI__VI { - struct { - unsigned int BASE_ADDR_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_EOP_CONTROL__VI { - struct { - unsigned int EOP_SIZE : 6; - unsigned int : 2; - unsigned int PROCESSING_EOP : 1; - unsigned int : 3; - unsigned int PROCESS_EOP_EN : 1; - unsigned int PROCESSING_EOPIB : 1; - unsigned int PROCESS_EOPIB_EN : 1; - unsigned int MTYPE : 2; - unsigned int : 6; - unsigned int EOP_ATC : 1; - unsigned int CACHE_POLICY : 1; - unsigned int : 4; - unsigned int SIG_SEM_RESULT : 2; - unsigned int PEND_SIG_SEM : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_EOP_DONES__VI { - struct { - unsigned int DONE_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_EOP_EVENTS__VI { - struct { - unsigned int EVENT_COUNT : 12; - unsigned int : 4; - unsigned int CS_PARTIAL_FLUSH_PEND : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_EOP_RPTR__VI { - struct { - unsigned int RPTR : 13; - unsigned int : 17; - unsigned int RPTR_EQ_CSMD_WPTR : 1; - unsigned int INIT_FETCHER : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_EOP_WPTR__VI { - struct { - unsigned int WPTR : 13; - unsigned int : 3; - unsigned int EOP_AVAIL : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_EOP_WPTR_MEM__VI { - struct { - unsigned int WPTR : 13; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_ERROR__VI { - struct { - unsigned int EDC_ERROR_ID : 4; - unsigned int SUA_ERROR : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_GDS_RESOURCE_STATE__VI { - struct { - unsigned int OA_REQUIRED : 1; - unsigned int OA_ACQUIRED : 1; - unsigned int : 2; - unsigned int GWS_SIZE : 6; - unsigned int : 2; - unsigned int GWS_PNTR : 6; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_HQ_CONTROL0__VI { - struct { - unsigned int CONTROL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_HQ_CONTROL1__VI { - struct { - unsigned int CONTROL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_HQ_STATUS0__VI { - struct { - unsigned int DEQUEUE_STATUS : 2; - unsigned int DEQUEUE_RETRY_CNT : 2; - unsigned int RSV_6_4 : 3; - unsigned int SCRATCH_RAM_INIT : 1; - unsigned int TCL2_DIRTY : 1; - unsigned int PG_ACTIVATED : 1; - unsigned int RSVR_31_10 : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_HQ_STATUS1__VI { - struct { - unsigned int STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_OFFLOAD__VI { - struct { - unsigned int DMA_OFFLOAD : 1; - unsigned int DMA_OFFLOAD_EN : 1; - unsigned int : 2; - unsigned int EOP_OFFLOAD : 1; - unsigned int EOP_OFFLOAD_EN : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_HQD_WG_STATE_OFFSET__VI { - struct { - unsigned int : 2; - unsigned int OFFSET : 23; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INDEX_BASE_ADDR__VI { - struct { - unsigned int ADDR_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INDEX_BASE_ADDR_HI__VI { - struct { - unsigned int ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_INDEX_TYPE__VI { - struct { - unsigned int INDEX_TYPE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC1_F32_INT_DIS__VI { - struct { - unsigned int EDC_ROQ_FED_INT : 1; - unsigned int PRIV_REG_INT : 1; - unsigned int RESERVED_BIT_ERR_INT : 1; - unsigned int EDC_TC_FED_INT : 1; - unsigned int EDC_GDS_FED_INT : 1; - unsigned int EDC_SCRATCH_FED_INT : 1; - unsigned int WAVE_RESTORE_INT : 1; - unsigned int SUA_VIOLATION_INT : 1; - unsigned int EDC_DMA_FED_INT : 1; - unsigned int IQ_TIMER_INT : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC2_F32_INT_DIS__VI { - struct { - unsigned int EDC_ROQ_FED_INT : 1; - unsigned int PRIV_REG_INT : 1; - unsigned int RESERVED_BIT_ERR_INT : 1; - unsigned int EDC_TC_FED_INT : 1; - unsigned int EDC_GDS_FED_INT : 1; - unsigned int EDC_SCRATCH_FED_INT : 1; - unsigned int WAVE_RESTORE_INT : 1; - unsigned int SUA_VIOLATION_INT : 1; - unsigned int EDC_DMA_FED_INT : 1; - unsigned int IQ_TIMER_INT : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC_DOORBELL_RANGE_LOWER__VI { - struct { - unsigned int : 2; - unsigned int DOORBELL_RANGE_LOWER : 21; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_MEC_DOORBELL_RANGE_UPPER__VI { - struct { - unsigned int : 2; - unsigned int DOORBELL_RANGE_UPPER : 21; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_COMPLETION_STATUS__VI { - struct { - unsigned int STATUS : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_METADATA_BASE_ADDR__VI { - struct { - unsigned int ADDR_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PFP_METADATA_BASE_ADDR_HI__VI { - struct { - unsigned int ADDR_HI : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PIPE_STATS_CONTROL__VI { - struct { - unsigned int : 25; - unsigned int CACHE_CONTROL : 1; - unsigned int : 1; - unsigned int MTYPE : 2; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PQ_STATUS__VI { - struct { - unsigned int DOORBELL_UPDATED : 1; - unsigned int DOORBELL_ENABLE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_PRED_NOT_VISIBLE__VI { - struct { - unsigned int NOT_VISIBLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_DOORBELL_CONTROL__VI { - struct { - unsigned int : 2; - unsigned int DOORBELL_OFFSET : 21; - unsigned int : 7; - unsigned int DOORBELL_EN : 1; - unsigned int DOORBELL_HIT : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_DOORBELL_RANGE_LOWER__VI { - struct { - unsigned int : 2; - unsigned int DOORBELL_RANGE_LOWER : 21; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_RB_DOORBELL_RANGE_UPPER__VI { - struct { - unsigned int : 2; - unsigned int DOORBELL_RANGE_UPPER : 21; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_SAMPLE_STATUS__VI { - struct { - unsigned int Z_PASS_ACITVE : 1; - unsigned int STREAMOUT_ACTIVE : 1; - unsigned int PIPELINE_ACTIVE : 1; - unsigned int STIPPLE_ACTIVE : 1; - unsigned int VGT_BUFFERS_ACTIVE : 1; - unsigned int SCREEN_EXT_ACTIVE : 1; - unsigned int DRAW_INDIRECT_ACTIVE : 1; - unsigned int DISP_INDIRECT_ACTIVE : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_STREAM_OUT_CONTROL__VI { - struct { - unsigned int : 25; - unsigned int CACHE_CONTROL : 1; - unsigned int : 1; - unsigned int MTYPE : 2; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VIRT_STATUS__VI { - struct { - unsigned int VIRT_STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CP_VMID_STATUS__VI { - struct { - unsigned int PREEMPT_DE_STATUS : 16; - unsigned int PREEMPT_CE_STATUS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_3D_STRUCTURE_CONTROL__VI { - struct { - unsigned int CRTC_3D_STRUCTURE_EN : 1; - unsigned int : 3; - unsigned int CRTC_3D_STRUCTURE_EN_DB : 1; - unsigned int : 3; - unsigned int CRTC_3D_STRUCTURE_V_UPDATE_MODE : 2; - unsigned int : 2; - unsigned int CRTC_3D_STRUCTURE_STEREO_SEL_OVR : 1; - unsigned int : 3; - unsigned int CRTC_3D_STRUCTURE_F_COUNT_RESET : 1; - unsigned int CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING : 1; - unsigned int CRTC_3D_STRUCTURE_F_COUNT : 2; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_AVSYNC_COUNTER__VI { - struct { - unsigned int CRTC_AVSYNC_COUNTER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_BLACK_COLOR_EXT__VI { - struct { - unsigned int CRTC_BLACK_COLOR_B_CB_EXT : 2; - unsigned int : 6; - unsigned int CRTC_BLACK_COLOR_G_Y_EXT : 2; - unsigned int : 6; - unsigned int CRTC_BLACK_COLOR_R_CR_EXT : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_BLANK_DATA_COLOR_EXT__VI { - struct { - unsigned int CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT : 2; - unsigned int : 6; - unsigned int CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT : 2; - unsigned int : 6; - unsigned int CRTC_BLANK_DATA_COLOR_RED_CR_EXT : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC0_DATA_B__VI { - struct { - unsigned int CRC0_B_CB : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC0_DATA_RG__VI { - struct { - unsigned int CRC0_R_CR : 16; - unsigned int CRC0_G_Y : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC0_WINDOWA_X_CONTROL__VI { - struct { - unsigned int CRTC_CRC0_WINDOWA_X_START : 14; - unsigned int : 2; - unsigned int CRTC_CRC0_WINDOWA_X_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC0_WINDOWA_Y_CONTROL__VI { - struct { - unsigned int CRTC_CRC0_WINDOWA_Y_START : 14; - unsigned int : 2; - unsigned int CRTC_CRC0_WINDOWA_Y_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC0_WINDOWB_X_CONTROL__VI { - struct { - unsigned int CRTC_CRC0_WINDOWB_X_START : 14; - unsigned int : 2; - unsigned int CRTC_CRC0_WINDOWB_X_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC0_WINDOWB_Y_CONTROL__VI { - struct { - unsigned int CRTC_CRC0_WINDOWB_Y_START : 14; - unsigned int : 2; - unsigned int CRTC_CRC0_WINDOWB_Y_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC1_DATA_B__VI { - struct { - unsigned int CRC1_B_CB : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC1_DATA_RG__VI { - struct { - unsigned int CRC1_R_CR : 16; - unsigned int CRC1_G_Y : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC1_WINDOWA_X_CONTROL__VI { - struct { - unsigned int CRTC_CRC1_WINDOWA_X_START : 14; - unsigned int : 2; - unsigned int CRTC_CRC1_WINDOWA_X_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC1_WINDOWA_Y_CONTROL__VI { - struct { - unsigned int CRTC_CRC1_WINDOWA_Y_START : 14; - unsigned int : 2; - unsigned int CRTC_CRC1_WINDOWA_Y_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC1_WINDOWB_X_CONTROL__VI { - struct { - unsigned int CRTC_CRC1_WINDOWB_X_START : 14; - unsigned int : 2; - unsigned int CRTC_CRC1_WINDOWB_X_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC1_WINDOWB_Y_CONTROL__VI { - struct { - unsigned int CRTC_CRC1_WINDOWB_Y_START : 14; - unsigned int : 2; - unsigned int CRTC_CRC1_WINDOWB_Y_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_CRC_CNTL__VI { - struct { - unsigned int CRTC_CRC_EN : 1; - unsigned int : 3; - unsigned int CRTC_CRC_CONT_EN : 1; - unsigned int : 3; - unsigned int CRTC_CRC_STEREO_MODE : 2; - unsigned int : 2; - unsigned int CRTC_CRC_INTERLACE_MODE : 2; - unsigned int : 2; - unsigned int CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS : 1; - unsigned int : 3; - unsigned int CRTC_CRC0_SELECT : 3; - unsigned int : 1; - unsigned int CRTC_CRC1_SELECT : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_DCFE_CLOCK_CONTROL__VI { - struct { - unsigned int : 4; - unsigned int CRTC_DISPCLK_R_DCFE_GATE_DISABLE : 1; - unsigned int : 3; - unsigned int CRTC_DISPCLK_G_DCP_GATE_DISABLE : 1; - unsigned int : 3; - unsigned int CRTC_DISPCLK_G_SCL_GATE_DISABLE : 1; - unsigned int : 11; - unsigned int CRTC_DCFE_TEST_CLK_SEL : 5; - unsigned int : 2; - unsigned int CRTC_DCFE_CLOCK_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_EXT_TIMING_SYNC_CONTROL__VI { - struct { - unsigned int CRTC_EXT_TIMING_SYNC_ENABLE : 2; - unsigned int : 1; - unsigned int CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE : 1; - unsigned int CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE : 1; - unsigned int CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW : 2; - unsigned int : 1; - unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE : 1; - unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE : 1; - unsigned int : 2; - unsigned int CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY : 1; - unsigned int CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY : 1; - unsigned int CRTC_EXT_TIMING_SYNC_INTERLACE_MODE : 1; - unsigned int : 9; - unsigned int CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE : 3; - unsigned int : 1; - unsigned int CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI { - struct { - unsigned int CRTC_EXT_TIMING_SYNC_INT_ENABLE : 1; - unsigned int : 3; - unsigned int CRTC_EXT_TIMING_SYNC_STATUS : 1; - unsigned int : 3; - unsigned int CRTC_EXT_TIMING_SYNC_INT_STATUS : 1; - unsigned int : 7; - unsigned int CRTC_EXT_TIMING_SYNC_CLEAR : 1; - unsigned int : 3; - unsigned int CRTC_EXT_TIMING_SYNC_INT_TYPE : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI { - struct { - unsigned int CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE : 1; - unsigned int : 3; - unsigned int CRTC_EXT_TIMING_SYNC_LOSS_STATUS : 1; - unsigned int : 3; - unsigned int CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS : 1; - unsigned int : 7; - unsigned int CRTC_EXT_TIMING_SYNC_LOSS_CLEAR : 1; - unsigned int : 3; - unsigned int CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE : 1; - unsigned int : 8; - unsigned int CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI { - struct { - unsigned int CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE : 1; - unsigned int : 3; - unsigned int CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS : 1; - unsigned int : 3; - unsigned int CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS : 1; - unsigned int : 7; - unsigned int CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR : 1; - unsigned int : 3; - unsigned int CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_EXT_TIMING_SYNC_WINDOW_END__VI { - struct { - unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_END_X : 14; - unsigned int : 2; - unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_END_Y : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_EXT_TIMING_SYNC_WINDOW_START__VI { - struct { - unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_START_X : 14; - unsigned int : 2; - unsigned int CRTC_EXT_TIMING_SYNC_WINDOW_START_Y : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_FIELD_INDICATION_CONTROL__VI { - struct { - unsigned int CRTC_FIELD_INDICATION_OUTPUT_POLARITY : 1; - unsigned int CRTC_FIELD_ALIGNMENT : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_GSL_CONTROL__VI { - struct { - unsigned int CRTC_GSL_CHECK_LINE_NUM : 14; - unsigned int : 2; - unsigned int CRTC_GSL_FORCE_DELAY : 5; - unsigned int : 7; - unsigned int CRTC_GSL_CHECK_ALL_FIELDS : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_GSL_VSYNC_GAP__VI { - struct { - unsigned int CRTC_GSL_VSYNC_GAP_LIMIT : 8; - unsigned int CRTC_GSL_VSYNC_GAP_DELAY : 8; - unsigned int CRTC_GSL_VSYNC_GAP_SOURCE_SEL : 1; - unsigned int CRTC_GSL_VSYNC_GAP_MODE : 2; - unsigned int CRTC_GSL_VSYNC_GAP_CLEAR : 1; - unsigned int CRTC_GSL_VSYNC_GAP_OCCURRED : 1; - unsigned int : 2; - unsigned int CRTC_GSL_VSYNC_GAP_MASTER_FASTER : 1; - unsigned int CRTC_GSL_VSYNC_GAP : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_GSL_WINDOW__VI { - struct { - unsigned int CRTC_GSL_WINDOW_START : 14; - unsigned int : 2; - unsigned int CRTC_GSL_WINDOW_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_H_BLANK_EARLY_NUM__VI { - struct { - unsigned int CRTC_H_BLANK_EARLY_NUM : 10; - unsigned int : 6; - unsigned int CRTC_H_BLANK_EARLY_NUM_DIS : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_OVERSCAN_COLOR_EXT__VI { - struct { - unsigned int CRTC_OVERSCAN_COLOR_BLUE_EXT : 2; - unsigned int : 6; - unsigned int CRTC_OVERSCAN_COLOR_GREEN_EXT : 2; - unsigned int : 6; - unsigned int CRTC_OVERSCAN_COLOR_RED_EXT : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_PIXEL_DATA_READBACK0__VI { - struct { - unsigned int CRTC_PIXEL_DATA_BLUE_CB : 12; - unsigned int : 4; - unsigned int CRTC_PIXEL_DATA_GREEN_Y : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_PIXEL_DATA_READBACK1__VI { - struct { - unsigned int CRTC_PIXEL_DATA_RED_CR : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_STATIC_SCREEN_CONTROL__VI { - struct { - unsigned int CRTC_STATIC_SCREEN_EVENT_MASK : 16; - unsigned int CRTC_STATIC_SCREEN_FRAME_COUNT : 8; - unsigned int CRTC_CPU_SS_INT_ENABLE : 1; - unsigned int CRTC_SS_STATUS : 1; - unsigned int CRTC_CPU_SS_INT_STATUS : 1; - unsigned int CRTC_CPU_SS_INT_CLEAR : 1; - unsigned int CRTC_CPU_SS_INT_TYPE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_VERTICAL_INTERRUPT0_CONTROL__VI { - struct { - unsigned int : 4; - unsigned int CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT0_INT_ENABLE : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT0_STATUS : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT0_INT_STATUS : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT0_CLEAR : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT0_INT_TYPE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_VERTICAL_INTERRUPT0_POSITION__VI { - struct { - unsigned int CRTC_VERTICAL_INTERRUPT0_LINE_START : 14; - unsigned int : 2; - unsigned int CRTC_VERTICAL_INTERRUPT0_LINE_END : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_VERTICAL_INTERRUPT1_CONTROL__VI { - struct { - unsigned int : 8; - unsigned int CRTC_VERTICAL_INTERRUPT1_INT_ENABLE : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT1_STATUS : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT1_INT_STATUS : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT1_CLEAR : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT1_INT_TYPE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_VERTICAL_INTERRUPT1_POSITION__VI { - struct { - unsigned int CRTC_VERTICAL_INTERRUPT1_LINE_START : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_VERTICAL_INTERRUPT2_CONTROL__VI { - struct { - unsigned int : 8; - unsigned int CRTC_VERTICAL_INTERRUPT2_INT_ENABLE : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT2_STATUS : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT2_INT_STATUS : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT2_CLEAR : 1; - unsigned int : 3; - unsigned int CRTC_VERTICAL_INTERRUPT2_INT_TYPE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CRTC_VERTICAL_INTERRUPT2_POSITION__VI { - struct { - unsigned int CRTC_VERTICAL_INTERRUPT2_LINE_START : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR2_COLOR1__VI { - struct { - unsigned int CUR2_COLOR1_BLUE : 8; - unsigned int CUR2_COLOR1_GREEN : 8; - unsigned int CUR2_COLOR1_RED : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR2_COLOR2__VI { - struct { - unsigned int CUR2_COLOR2_BLUE : 8; - unsigned int CUR2_COLOR2_GREEN : 8; - unsigned int CUR2_COLOR2_RED : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR2_CONTROL__VI { - struct { - unsigned int CURSOR2_EN : 1; - unsigned int : 3; - unsigned int CUR2_INV_TRANS_CLAMP : 1; - unsigned int : 3; - unsigned int CURSOR2_MODE : 2; - unsigned int : 6; - unsigned int CURSOR2_2X_MAGNIFY : 1; - unsigned int : 3; - unsigned int CURSOR2_FORCE_MC_ON : 1; - unsigned int : 3; - unsigned int CURSOR2_URGENT_CONTROL : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR2_HOT_SPOT__VI { - struct { - unsigned int CURSOR2_HOT_SPOT_Y : 7; - unsigned int : 9; - unsigned int CURSOR2_HOT_SPOT_X : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR2_POSITION__VI { - struct { - unsigned int CURSOR2_Y_POSITION : 14; - unsigned int : 2; - unsigned int CURSOR2_X_POSITION : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR2_SIZE__VI { - struct { - unsigned int CURSOR2_HEIGHT : 7; - unsigned int : 9; - unsigned int CURSOR2_WIDTH : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR2_STEREO_CONTROL__VI { - struct { - unsigned int CURSOR2_STEREO_EN : 1; - unsigned int CURSOR2_STEREO_OFFSET_YNX : 1; - unsigned int : 2; - unsigned int CURSOR2_PRIMARY_OFFSET : 10; - unsigned int : 2; - unsigned int CURSOR2_SECONDARY_OFFSET : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR2_SURFACE_ADDRESS__VI { - struct { - unsigned int CURSOR2_SURFACE_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR2_SURFACE_ADDRESS_HIGH__VI { - struct { - unsigned int CURSOR2_SURFACE_ADDRESS_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR2_UPDATE__VI { - struct { - unsigned int CURSOR2_UPDATE_PENDING : 1; - unsigned int CURSOR2_UPDATE_TAKEN : 1; - unsigned int : 14; - unsigned int CURSOR2_UPDATE_LOCK : 1; - unsigned int : 7; - unsigned int CURSOR2_DISABLE_MULTIPLE_UPDATE : 1; - unsigned int CURSOR2_UPDATE_STEREO_MODE : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR_REQUEST_FILTER_CNTL__VI { - struct { - unsigned int CUR_REQUEST_FILTER_DIS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union CUR_STEREO_CONTROL__VI { - struct { - unsigned int CURSOR_STEREO_EN : 1; - unsigned int CURSOR_STEREO_OFFSET_YNX : 1; - unsigned int : 2; - unsigned int CURSOR_PRIMARY_OFFSET : 10; - unsigned int : 2; - unsigned int CURSOR_SECONDARY_OFFSET : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_CLK_ENABLE__VI { - struct { - unsigned int DACA_CLK_ENABLE : 1; - unsigned int : 3; - unsigned int DACB_CLK_ENABLE : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_FIFO_STATUS__VI { - struct { - unsigned int : 1; - unsigned int DAC_FIFO_USE_OVERWRITE_LEVEL : 1; - unsigned int DAC_FIFO_OVERWRITE_LEVEL : 6; - unsigned int : 2; - unsigned int DAC_FIFO_CAL_AVERAGE_LEVEL : 6; - unsigned int DAC_FIFO_MAXIMUM_LEVEL : 4; - unsigned int : 2; - unsigned int DAC_FIFO_MINIMUM_LEVEL : 4; - unsigned int : 3; - unsigned int DAC_FIFO_CALIBRATED : 1; - unsigned int DAC_FIFO_FORCE_RECAL_AVERAGE : 1; - unsigned int DAC_FIFO_FORCE_RECOMP_MINMAX : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_MACRO_CNTL_RESERVED0__VI { - struct { - unsigned int DAC_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_MACRO_CNTL_RESERVED1__VI { - struct { - unsigned int DAC_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_MACRO_CNTL_RESERVED2__VI { - struct { - unsigned int DAC_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_MACRO_CNTL_RESERVED3__VI { - struct { - unsigned int DAC_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_TEST_DEBUG_DATA__VI { - struct { - unsigned int DAC_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DAC_TEST_DEBUG_INDEX__VI { - struct { - unsigned int DAC_TEST_DEBUG_INDEX : 8; - unsigned int DAC_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DBG_OUT_CNTL__VI { - struct { - unsigned int DBG_OUT_PIN_EN : 1; - unsigned int : 3; - unsigned int DBG_OUT_PIN_SEL : 1; - unsigned int : 3; - unsigned int DBG_OUT_12BIT_SEL : 2; - unsigned int : 2; - unsigned int DBG_OUT_TEST_DATA : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DBG_SMB_BYPASS_SRBM_ACCESS__VI { - struct { - unsigned int DBG_SMB_BYPASS_SRBM_EN : 1; - unsigned int : 4; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_AUDIO_DTO1_MODULE__VI { - struct { - unsigned int DCCG_AUDIO_DTO1_MODULE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_AUDIO_DTO1_PHASE__VI { - struct { - unsigned int DCCG_AUDIO_DTO1_PHASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_AUDIO_DTO_SOURCE__VI { - struct { - unsigned int DCCG_AUDIO_DTO0_SOURCE_SEL : 3; - unsigned int : 1; - unsigned int DCCG_AUDIO_DTO_SEL : 2; - unsigned int : 6; - unsigned int DCCG_AUDIO_DTO2_SOURCE_SEL : 2; - unsigned int : 2; - unsigned int DCCG_AUDIO_DTO2_CLOCK_EN : 1; - unsigned int : 3; - unsigned int DCCG_AUDIO_DTO2_USE_512FBR_DTO : 1; - unsigned int : 3; - unsigned int DCCG_AUDIO_DTO0_USE_512FBR_DTO : 1; - unsigned int : 3; - unsigned int DCCG_AUDIO_DTO1_USE_512FBR_DTO : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_CAC_STATUS__VI { - struct { - unsigned int CAC_STATUS_RDDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_CBUS_WRCMD_DELAY__VI { - struct { - unsigned int CBUS_PLL_WRCMD_DELAY : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_DISP_CNTL_REG__VI { - struct { - unsigned int : 8; - unsigned int ALLOW_SR_ON_TRANS_REQ : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_DS_CNTL__VI { - struct { - unsigned int DCCG_DS_ENABLE : 1; - unsigned int : 7; - unsigned int DCCG_DS_HW_CAL_ENABLE : 1; - unsigned int DCCG_DS_ENABLED_STATUS : 1; - unsigned int : 6; - unsigned int DCCG_DS_XTALIN_RATE_DIV : 2; - unsigned int : 6; - unsigned int DCCG_DS_JITTER_REMOVE_DIS : 1; - unsigned int DCCG_DS_DELAY_XTAL_SEL : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_DS_DEBUG_CNTL__VI { - struct { - unsigned int DCCG_DS_DEBUG_COUNT_ENABLE : 1; - unsigned int : 3; - unsigned int DCCG_DS_DEBUG_COUNT_TRIG_VALUE : 9; - unsigned int : 3; - unsigned int DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED : 1; - unsigned int DCCG_DS_DEBUG_COUNT_TRIG_CLEAR : 1; - unsigned int : 2; - unsigned int DCCG_DS_JITTER_COUNT_ENABLE : 1; - unsigned int DCCG_DS_JITTER_COUNT_SRC_SEL : 1; - unsigned int : 2; - unsigned int DCCG_DS_JITTER_COUNT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_DS_DTO_INCR__VI { - struct { - unsigned int DCCG_DS_DTO_INCR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_DS_DTO_MODULO__VI { - struct { - unsigned int DCCG_DS_DTO_MODULO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_DS_HW_CAL_INTERVAL__VI { - struct { - unsigned int DCCG_DS_HW_CAL_INTERVAL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_GTC_CNTL__VI { - struct { - unsigned int DCCG_GTC_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_GTC_CURRENT__VI { - struct { - unsigned int DCCG_GTC_CURRENT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_GTC_DTO_INCR__VI { - struct { - unsigned int DCCG_GTC_DTO_INCR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_GTC_DTO_MODULO__VI { - struct { - unsigned int DCCG_GTC_DTO_MODULO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_PERFMON_CNTL__VI { - struct { - unsigned int DCCG_PERF_DISPCLK_ENABLE : 1; - unsigned int DCCG_PERF_DPREFCLK_ENABLE : 1; - unsigned int DCCG_PERF_PIXCLK1_ENABLE : 1; - unsigned int DCCG_PERF_PIXCLK2_ENABLE : 1; - unsigned int DCCG_PERF_PIXCLK0_ENABLE : 1; - unsigned int DCCG_PERF_RUN : 1; - unsigned int DCCG_PERF_MODE_VSYNC : 1; - unsigned int DCCG_PERF_MODE_HSYNC : 1; - unsigned int DCCG_PERF_CRTC_SEL : 3; - unsigned int DCCG_PERF_XTALIN_PULSE_DIV : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_PERFMON_CNTL2__VI { - struct { - unsigned int DCCG_PERF_DSICLK_ENABLE : 1; - unsigned int DCCG_PERF_REFCLK_ENABLE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCCG_SOFT_RESET__VI { - struct { - unsigned int REFCLK_SOFT_RESET : 1; - unsigned int PCIE_REFCLK_SOFT_RESET : 1; - unsigned int SOFT_RESET_DVO : 1; - unsigned int DVO_ENABLE_RST : 1; - unsigned int AUDIO_DTO2_CLK_SOFT_RESET : 1; - unsigned int : 3; - unsigned int DPREFCLK_SOFT_RESET : 1; - unsigned int : 3; - unsigned int AMCLK0_SOFT_RESET : 1; - unsigned int AMCLK1_SOFT_RESET : 1; - unsigned int P0PLL_CFG_IF_SOFT_RESET : 1; - unsigned int P1PLL_CFG_IF_SOFT_RESET : 1; - unsigned int P2PLL_CFG_IF_SOFT_RESET : 1; - unsigned int A0PLL_CFG_IF_SOFT_RESET : 1; - unsigned int A1PLL_CFG_IF_SOFT_RESET : 1; - unsigned int C0PLL_CFG_IF_SOFT_RESET : 1; - unsigned int C1PLL_CFG_IF_SOFT_RESET : 1; - unsigned int C2PLL_CFG_IF_SOFT_RESET : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCDEBUG_BUS_CLK5_SEL__VI { - struct { - unsigned int DCDEBUG_BUS_CLK5_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCDEBUG_OUT_DATA__VI { - struct { - unsigned int DCDEBUG_OUT_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCE_VCE_CONTROL__VI { - struct { - unsigned int DC_VCE_VIDEO_PIPE_SELECT : 3; - unsigned int : 1; - unsigned int DC_VCE_AUDIO_STREAM_SELECT : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFEV0_CRTC_PIXEL_RATE_CNTL__VI { - struct { - unsigned int DCFEV0_CRTC_PIXEL_RATE_SOURCE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFEV0_PG_CONFIG__VI { - struct { - unsigned int DCFEV0_POWER_FORCEON : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFEV0_PG_ENABLE__VI { - struct { - unsigned int DCFEV0_POWER_GATE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFEV0_PG_STATUS__VI { - struct { - unsigned int DCFEV0_PGFSM_READ_DATA : 24; - unsigned int DCFEV0_DEBUG_PWR_STATUS : 2; - unsigned int : 2; - unsigned int DCFEV0_DESIRED_PWR_STATE : 1; - unsigned int DCFEV0_REQUESTED_PWR_STATE : 1; - unsigned int DCFEV0_PGFSM_PWR_STATUS : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFEV_CLOCK_CONTROL__VI { - struct { - unsigned int : 3; - unsigned int DISPCLK_R_DCFEV_GATE_DISABLE : 1; - unsigned int : 3; - unsigned int DISPCLK_G_UNP_GATE_DISABLE : 1; - unsigned int : 1; - unsigned int DISPCLK_G_SCLV_GATE_DISABLE : 1; - unsigned int : 1; - unsigned int DISPCLK_G_COL_MAN_GATE_DISABLE : 1; - unsigned int : 1; - unsigned int DISPCLK_G_PSCLV_GATE_DISABLE : 1; - unsigned int : 1; - unsigned int DISPCLK_G_CRTC_GATE_DISABLE : 1; - unsigned int : 8; - unsigned int DCFEV_TEST_CLK_SEL : 5; - unsigned int : 2; - unsigned int DCFEV_CLOCK_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFEV_DBG_CONFIG__VI { - struct { - unsigned int DCFEV_DBG_EN : 1; - unsigned int : 3; - unsigned int DCFEV_DBG_SEL : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFEV_DMIFV_CLOCK_CONTROL__VI { - struct { - unsigned int : 3; - unsigned int DMIFV_SCLK_G_DMIFTRK_GATE_DIS : 1; - unsigned int DMIFV_DISPCLK_G_DMIFVL_GATE_DIS : 1; - unsigned int DMIFV_DISPCLK_G_DMIFVC_GATE_DIS : 1; - unsigned int DMIFV_SOFT_RESET : 1; - unsigned int : 17; - unsigned int DMIFV_TEST_CLK_SEL : 5; - unsigned int : 2; - unsigned int DMIFV_BUFFER_MODE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFEV_DMIFV_MEM_PWR_CTRL__VI { - struct { - unsigned int DMIFV_MEM_PWR_SEL : 2; - unsigned int DMIFV_MEM_PWR_LUMA_0_FORCE : 1; - unsigned int DMIFV_MEM_PWR_LUMA_1_FORCE : 1; - unsigned int DMIFV_MEM_PWR_LUMA_2_FORCE : 1; - unsigned int DMIFV_MEM_PWR_LUMA_3_FORCE : 1; - unsigned int DMIFV_MEM_PWR_LUMA_4_FORCE : 1; - unsigned int DMIFV_MEM_PWR_CHROMA_0_FORCE : 1; - unsigned int DMIFV_MEM_PWR_CHROMA_1_FORCE : 1; - unsigned int DMIFV_MEM_PWR_CHROMA_2_FORCE : 1; - unsigned int DMIFV_MEM_PWR_CHROMA_3_FORCE : 1; - unsigned int DMIFV_MEM_PWR_CHROMA_4_FORCE : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFEV_DMIFV_MEM_PWR_STATUS__VI { - struct { - unsigned int DMIFV_MEM_PWR_LUMA_0_STATE : 2; - unsigned int DMIFV_MEM_PWR_LUMA_1_STATE : 2; - unsigned int DMIFV_MEM_PWR_LUMA_2_STATE : 2; - unsigned int DMIFV_MEM_PWR_LUMA_3_STATE : 2; - unsigned int DMIFV_MEM_PWR_LUMA_4_STATE : 2; - unsigned int DMIFV_MEM_PWR_CHROMA_0_STATE : 2; - unsigned int DMIFV_MEM_PWR_CHROMA_1_STATE : 2; - unsigned int DMIFV_MEM_PWR_CHROMA_2_STATE : 2; - unsigned int DMIFV_MEM_PWR_CHROMA_3_STATE : 2; - unsigned int DMIFV_MEM_PWR_CHROMA_4_STATE : 2; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFEV_SOFT_RESET__VI { - struct { - unsigned int UNP_PIXPIPE_SOFT_RESET : 1; - unsigned int UNP_REQ_SOFT_RESET : 1; - unsigned int SCLV_ALU_SOFT_RESET : 1; - unsigned int SCLV_SOFT_RESET : 1; - unsigned int CRTC_SOFT_RESET : 1; - unsigned int PSCLV_SOFT_RESET : 1; - unsigned int COL_MAN_SOFT_RESET : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFE_CLOCK_CONTROL__VI { - struct { - unsigned int : 4; - unsigned int DISPCLK_R_DCFE_GATE_DISABLE : 1; - unsigned int : 3; - unsigned int DISPCLK_G_DCP_GATE_DISABLE : 1; - unsigned int : 3; - unsigned int DISPCLK_G_SCL_GATE_DISABLE : 1; - unsigned int : 11; - unsigned int DCFE_TEST_CLK_SEL : 5; - unsigned int : 2; - unsigned int DCFE_CLOCK_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFE_DBG_CONFIG__VI { - struct { - unsigned int DCFE_DBG_EN : 1; - unsigned int : 3; - unsigned int DCFE_DBG_SEL : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFE_DBG_SEL__VI { - struct { - unsigned int DCFE_DBG_SEL : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFE_MEM_PWR_CTRL__VI { - struct { - unsigned int DCP_LUT_MEM_PWR_FORCE : 2; - unsigned int DCP_LUT_MEM_PWR_DIS : 1; - unsigned int DCP_REGAMMA_MEM_PWR_FORCE : 2; - unsigned int DCP_REGAMMA_MEM_PWR_DIS : 1; - unsigned int SCL_COEFF_MEM_PWR_FORCE : 2; - unsigned int SCL_COEFF_MEM_PWR_DIS : 1; - unsigned int DCP_CURSOR_MEM_PWR_FORCE : 2; - unsigned int DCP_CURSOR_MEM_PWR_DIS : 1; - unsigned int LB0_ALPHA_MEM_PWR_FORCE : 2; - unsigned int LB0_ALPHA_MEM_PWR_DIS : 1; - unsigned int LB1_ALPHA_MEM_PWR_FORCE : 2; - unsigned int LB1_ALPHA_MEM_PWR_DIS : 1; - unsigned int LB2_ALPHA_MEM_PWR_FORCE : 2; - unsigned int LB2_ALPHA_MEM_PWR_DIS : 1; - unsigned int LB0_MEM_PWR_FORCE : 2; - unsigned int LB0_MEM_PWR_DIS : 1; - unsigned int LB1_MEM_PWR_FORCE : 2; - unsigned int LB1_MEM_PWR_DIS : 1; - unsigned int LB2_MEM_PWR_FORCE : 2; - unsigned int LB2_MEM_PWR_DIS : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFE_MEM_PWR_CTRL2__VI { - struct { - unsigned int DCP_LUT_MEM_PWR_MODE_SEL : 2; - unsigned int DCP_REGAMMA_MEM_PWR_MODE_SEL : 2; - unsigned int SCL_COEFF_MEM_PWR_MODE_SEL : 2; - unsigned int DCP_CURSOR_MEM_PWR_MODE_SEL : 2; - unsigned int LB_ALPHA_MEM_PWR_MODE_SEL : 2; - unsigned int LB_MEM_PWR_MODE_SEL : 2; - unsigned int DCP_CURSOR2_MEM_PWR_MODE_SEL : 2; - unsigned int BLND_MEM_PWR_MODE_SEL : 2; - unsigned int BLND_MEM_PWR_FORCE : 2; - unsigned int BLND_MEM_PWR_DIS : 1; - unsigned int OVLSCL_MEM_PWR_FORCE : 1; - unsigned int OVLSCL_MEM_PWR_DIS : 1; - unsigned int DCP_CURSOR2_MEM_PWR_FORCE : 2; - unsigned int DCP_CURSOR2_MEM_PWR_DIS : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFE_MEM_PWR_STATUS__VI { - struct { - unsigned int DCP_LUT_MEM_PWR_STATE : 2; - unsigned int DCP_REGAMMA_MEM_PWR_STATE : 2; - unsigned int SCL_COEFF_MEM_PWR_STATE : 2; - unsigned int DCP_CURSOR_MEM_PWR_STATE : 2; - unsigned int DCP_CURSOR2_MEM_PWR_STATE : 2; - unsigned int LB0_ALPHA_MEM_PWR_STATE : 2; - unsigned int LB1_ALPHA_MEM_PWR_STATE : 2; - unsigned int LB2_ALPHA_MEM_PWR_STATE : 2; - unsigned int LB0_MEM_PWR_STATE : 2; - unsigned int LB1_MEM_PWR_STATE : 2; - unsigned int LB2_MEM_PWR_STATE : 2; - unsigned int BLND_MEM_PWR_STATE : 2; - unsigned int OVLSCL_MEM_PWR_STATE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCFE_SOFT_RESET__VI { - struct { - unsigned int DCP_PIXPIPE_SOFT_RESET : 1; - unsigned int DCP_REQ_SOFT_RESET : 1; - unsigned int SCL_ALU_SOFT_RESET : 1; - unsigned int SCL_SOFT_RESET : 1; - unsigned int CRTC_SOFT_RESET : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_CLOCK_CNTL__VI { - struct { - unsigned int DCIO_TEST_CLK_SEL : 5; - unsigned int DISPCLK_R_DCIO_GATE_DIS : 1; - unsigned int : 2; - unsigned int DISPCLK_R_DCIO_RAMP_DIS : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG10__VI { - struct { - unsigned int DCIO_DIGC_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG11__VI { - struct { - unsigned int DCIO_DIGD_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG12__VI { - struct { - unsigned int DCIO_DIGE_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG13__VI { - struct { - unsigned int DCIO_DIGF_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG14__VI { - struct { - unsigned int DCIO_DIGG_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG15__VI { - struct { - unsigned int DCIO_DEBUG15 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG16__VI { - struct { - unsigned int DCIO_DEBUG16 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG8__VI { - struct { - unsigned int DCIO_DEBUG8 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG9__VI { - struct { - unsigned int DCIO_DEBUG9 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUGA__VI { - struct { - unsigned int DCIO_DEBUGA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUGB__VI { - struct { - unsigned int DCIO_DEBUGB : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUGC__VI { - struct { - unsigned int DCIO_DEBUGC : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUGD__VI { - struct { - unsigned int DCIO_DEBUGD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUGE__VI { - struct { - unsigned int DCIO_DIGA_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUGF__VI { - struct { - unsigned int DCIO_DIGB_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG_CONFIG__VI { - struct { - unsigned int DCIO_DBG_EN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DEBUG_ID__VI { - struct { - unsigned int DCIO_DEBUG_ID : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_DPHY_SEL__VI { - struct { - unsigned int DPHY_LANE0_SEL : 2; - unsigned int DPHY_LANE1_SEL : 2; - unsigned int DPHY_LANE2_SEL : 2; - unsigned int DPHY_LANE3_SEL : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_GSL0_CNTL__VI { - struct { - unsigned int DCIO_GSL0_VSYNC_SEL : 3; - unsigned int : 5; - unsigned int DCIO_GSL0_TIMING_SYNC_SEL : 3; - unsigned int : 5; - unsigned int DCIO_GSL0_GLOBAL_UNLOCK_SEL : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_GSL1_CNTL__VI { - struct { - unsigned int DCIO_GSL1_VSYNC_SEL : 3; - unsigned int : 5; - unsigned int DCIO_GSL1_TIMING_SYNC_SEL : 3; - unsigned int : 5; - unsigned int DCIO_GSL1_GLOBAL_UNLOCK_SEL : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_GSL2_CNTL__VI { - struct { - unsigned int DCIO_GSL2_VSYNC_SEL : 3; - unsigned int : 5; - unsigned int DCIO_GSL2_TIMING_SYNC_SEL : 3; - unsigned int : 5; - unsigned int DCIO_GSL2_GLOBAL_UNLOCK_SEL : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_GSL_GENLK_PAD_CNTL__VI { - struct { - unsigned int DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL : 2; - unsigned int : 2; - unsigned int DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL : 2; - unsigned int : 2; - unsigned int DCIO_GENLK_CLK_GSL_MASK : 2; - unsigned int : 6; - unsigned int DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL : 2; - unsigned int : 2; - unsigned int DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL : 2; - unsigned int : 2; - unsigned int DCIO_GENLK_VSYNC_GSL_MASK : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_GSL_SWAPLOCK_PAD_CNTL__VI { - struct { - unsigned int DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL : 2; - unsigned int : 2; - unsigned int DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL : 2; - unsigned int : 2; - unsigned int DCIO_SWAPLOCK_A_GSL_MASK : 2; - unsigned int : 6; - unsigned int DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL : 2; - unsigned int : 2; - unsigned int DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL : 2; - unsigned int : 2; - unsigned int DCIO_SWAPLOCK_B_GSL_MASK : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_IMPCAL_CNTL__VI { - struct { - unsigned int CALR_CNTL_OVERRIDE : 4; - unsigned int : 1; - unsigned int IMPCAL_SOFT_RESET : 1; - unsigned int : 2; - unsigned int IMPCAL_STATUS : 2; - unsigned int : 2; - unsigned int IMPCAL_ARB_STATE : 3; - unsigned int AUX_IMPCAL_INTERVAL : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_SOFT_RESET__VI { - struct { - unsigned int UNIPHYA_SOFT_RESET : 1; - unsigned int DSYNCA_SOFT_RESET : 1; - unsigned int UNIPHYB_SOFT_RESET : 1; - unsigned int DSYNCB_SOFT_RESET : 1; - unsigned int UNIPHYC_SOFT_RESET : 1; - unsigned int DSYNCC_SOFT_RESET : 1; - unsigned int UNIPHYD_SOFT_RESET : 1; - unsigned int DSYNCD_SOFT_RESET : 1; - unsigned int UNIPHYE_SOFT_RESET : 1; - unsigned int DSYNCE_SOFT_RESET : 1; - unsigned int UNIPHYF_SOFT_RESET : 1; - unsigned int DSYNCF_SOFT_RESET : 1; - unsigned int UNIPHYG_SOFT_RESET : 1; - unsigned int DSYNCG_SOFT_RESET : 1; - unsigned int : 2; - unsigned int DACA_SOFT_RESET : 1; - unsigned int : 3; - unsigned int DCRXPHY_SOFT_RESET : 1; - unsigned int : 3; - unsigned int DPHY_SOFT_RESET : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_TEST_DEBUG_DATA__VI { - struct { - unsigned int DCIO_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_TEST_DEBUG_INDEX__VI { - struct { - unsigned int DCIO_TEST_DEBUG_INDEX : 8; - unsigned int DCIO_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCIO_WRCMD_DELAY__VI { - struct { - unsigned int UNIPHY_DELAY : 4; - unsigned int DAC_DELAY : 4; - unsigned int DPHY_DELAY : 4; - unsigned int DCRXPHY_DELAY : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_CLK_CNTL__VI { - struct { - unsigned int DCI_TEST_CLK_SEL : 5; - unsigned int DISPCLK_R_DCI_GATE_DIS : 1; - unsigned int DISPCLK_M_GATE_DIS : 1; - unsigned int SCLK_G_STREAM_AZ_GATE_DIS : 1; - unsigned int SCLK_R_AZ_GATE_DIS : 1; - unsigned int DISPCLK_G_FBC_GATE_DIS : 1; - unsigned int : 1; - unsigned int DISPCLK_G_VGA_GATE_DIS : 1; - unsigned int : 1; - unsigned int DISPCLK_G_VIP_GATE_DIS : 1; - unsigned int VPCLK_POL : 1; - unsigned int DISPCLK_G_DMCU_GATE_DIS : 1; - unsigned int DISPCLK_G_DMIF0_GATE_DIS : 1; - unsigned int DISPCLK_G_DMIF1_GATE_DIS : 1; - unsigned int DISPCLK_G_DMIF2_GATE_DIS : 1; - unsigned int DISPCLK_G_DMIF3_GATE_DIS : 1; - unsigned int DISPCLK_G_DMIF4_GATE_DIS : 1; - unsigned int DISPCLK_G_DMIF5_GATE_DIS : 1; - unsigned int SCLK_G_DMIF_GATE_DIS : 1; - unsigned int SCLK_G_DMIFTRK_GATE_DIS : 1; - unsigned int SCLK_G_CNTL_AZ_GATE_DIS : 1; - unsigned int DISPCLK_G_DMIFV_L_GATE_DIS : 1; - unsigned int DISPCLK_G_DMIFV_C_GATE_DIS : 1; - unsigned int DCI_PG_TEST_CLK_SEL : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_CLK_RAMP_CNTL__VI { - struct { - unsigned int DISPCLK_G_MCIF_DWB_GATE_DIS : 1; - unsigned int SCLK_G_MCIF_DWB_GATE_DIS : 1; - unsigned int DISPCLK_G_MCIF_CWB0_GATE_DIS : 1; - unsigned int SCLK_G_MCIF_CWB0_GATE_DIS : 1; - unsigned int DISPCLK_G_MCIF_CWB1_GATE_DIS : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SCLK_G_MCIF_CWB1_GATE_DIS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_DEBUG_CONFIG__VI { - struct { - unsigned int DCI_DBG_EN : 1; - unsigned int : 3; - unsigned int DCI_DBG_BLOCK_SEL : 4; - unsigned int DCI_DBG_CLOCK_SEL : 4; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_MEM_PWR_CNTL__VI { - struct { - unsigned int DMIF_RDREQ_MEM_PWR_FORCE : 2; - unsigned int DMIF_RDREQ_MEM_PWR_DIS : 1; - unsigned int MCIF_RDREQ_MEM_PWR_FORCE : 1; - unsigned int MCIF_RDREQ_MEM_PWR_DIS : 1; - unsigned int MCIF_WRREQ_MEM_PWR_FORCE : 1; - unsigned int MCIF_WRREQ_MEM_PWR_DIS : 1; - unsigned int VGA_MEM_PWR_FORCE : 1; - unsigned int VGA_MEM_PWR_DIS : 1; - unsigned int DMCU_ERAM_MEM_PWR_FORCE : 2; - unsigned int DMCU_ERAM_MEM_PWR_DIS : 1; - unsigned int DMCU_IRAM_MEM_PWR_FORCE : 1; - unsigned int DMCU_IRAM_MEM_PWR_DIS : 1; - unsigned int FBC_MEM_PWR_FORCE : 2; - unsigned int FBC_MEM_PWR_DIS : 1; - unsigned int MCIF_MEM_PWR_FORCE : 2; - unsigned int MCIF_MEM_PWR_DIS : 1; - unsigned int MCIF_DWB_MEM_PWR_FORCE : 2; - unsigned int MCIF_DWB_MEM_PWR_DIS : 1; - unsigned int MCIF_CWB0_MEM_PWR_FORCE : 2; - unsigned int MCIF_CWB0_MEM_PWR_DIS : 1; - unsigned int MCIF_CWB1_MEM_PWR_FORCE : 2; - unsigned int MCIF_CWB1_MEM_PWR_DIS : 1; - unsigned int VIP_MEM_PWR_FORCE : 1; - unsigned int VIP_MEM_PWR_DIS : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_MEM_PWR_CNTL2__VI { - struct { - unsigned int DMIF0_ASYNC_MEM_PWR_FORCE : 2; - unsigned int DMIF0_ASYNC_MEM_PWR_DIS : 1; - unsigned int DMIF0_DATA_MEM_PWR_FORCE : 2; - unsigned int DMIF0_DATA_MEM_PWR_DIS : 1; - unsigned int DMIF0_CHUNK_MEM_PWR_FORCE : 1; - unsigned int DMIF0_CHUNK_MEM_PWR_DIS : 1; - unsigned int DMIF1_ASYNC_MEM_PWR_FORCE : 2; - unsigned int DMIF1_ASYNC_MEM_PWR_DIS : 1; - unsigned int DMIF1_DATA_MEM_PWR_FORCE : 2; - unsigned int DMIF1_DATA_MEM_PWR_DIS : 1; - unsigned int DMIF1_CHUNK_MEM_PWR_FORCE : 1; - unsigned int DMIF1_CHUNK_MEM_PWR_DIS : 1; - unsigned int DMIF2_ASYNC_MEM_PWR_FORCE : 2; - unsigned int DMIF2_ASYNC_MEM_PWR_DIS : 1; - unsigned int DMIF2_DATA_MEM_PWR_FORCE : 2; - unsigned int DMIF2_DATA_MEM_PWR_DIS : 1; - unsigned int DMIF2_CHUNK_MEM_PWR_FORCE : 1; - unsigned int DMIF2_CHUNK_MEM_PWR_DIS : 1; - unsigned int DMIF3_ASYNC_MEM_PWR_FORCE : 2; - unsigned int DMIF3_ASYNC_MEM_PWR_DIS : 1; - unsigned int DMIF3_DATA_MEM_PWR_FORCE : 2; - unsigned int DMIF3_DATA_MEM_PWR_DIS : 1; - unsigned int DMIF3_CHUNK_MEM_PWR_FORCE : 1; - unsigned int DMIF3_CHUNK_MEM_PWR_DIS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_MEM_PWR_CNTL3__VI { - struct { - unsigned int DMIF4_ASYNC_MEM_PWR_FORCE : 2; - unsigned int DMIF4_ASYNC_MEM_PWR_DIS : 1; - unsigned int DMIF4_DATA_MEM_PWR_FORCE : 2; - unsigned int DMIF4_DATA_MEM_PWR_DIS : 1; - unsigned int DMIF4_CHUNK_MEM_PWR_FORCE : 1; - unsigned int DMIF4_CHUNK_MEM_PWR_DIS : 1; - unsigned int DMIF5_ASYNC_MEM_PWR_FORCE : 2; - unsigned int DMIF5_ASYNC_MEM_PWR_DIS : 1; - unsigned int DMIF5_DATA_MEM_PWR_FORCE : 2; - unsigned int DMIF5_DATA_MEM_PWR_DIS : 1; - unsigned int DMIF5_CHUNK_MEM_PWR_FORCE : 1; - unsigned int DMIF5_CHUNK_MEM_PWR_DIS : 1; - unsigned int DMIF_RDREQ_MEM_PWR_MODE_SEL : 2; - unsigned int DMIF_ASYNC_MEM_PWR_MODE_SEL : 2; - unsigned int DMIF_DATA_MEM_PWR_MODE_SEL : 2; - unsigned int DMCU_ERAM_MEM_PWR_MODE_SEL : 1; - unsigned int FBC_MEM_PWR_MODE_SEL : 2; - unsigned int MCIF_CWB0_MEM_PWR_MODE_SEL : 2; - unsigned int MCIF_CWB1_MEM_PWR_MODE_SEL : 2; - unsigned int MCIF_DWB_MEM_PWR_MODE_SEL : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_MEM_PWR_STATUS__VI { - struct { - unsigned int DMIF_RDREQ_MEM1_PWR_STATE : 2; - unsigned int DMIF_RDREQ_MEM2_PWR_STATE : 2; - unsigned int MCIF_RDREQ_MEM_PWR_STATE : 1; - unsigned int : 1; - unsigned int MCIF_WRREQ_MEM_PWR_STATE : 1; - unsigned int : 1; - unsigned int VGA_MEM_PWR_STATE : 1; - unsigned int DMCU_ERAM_MEM_PWR_STATE : 2; - unsigned int DMCU_IRAM_MEM_PWR_STATE : 1; - unsigned int FBC_MEM_PWR_STATE : 2; - unsigned int MCIF_MEM_PWR_STATE : 2; - unsigned int MCIF_DWB_MEM_PWR_STATE : 2; - unsigned int MCIF_CWB0_MEM_PWR_STATE : 2; - unsigned int MCIF_CWB1_MEM_PWR_STATE : 2; - unsigned int VIP_MEM_PWR_STATE : 1; - unsigned int : 1; - unsigned int DMIF0_ASYNC_MEM_PWR_STATE : 2; - unsigned int DMIF0_DATA_MEM_PWR_STATE : 2; - unsigned int DMIF0_CHUNK_MEM_PWR_STATE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_MEM_PWR_STATUS2__VI { - struct { - unsigned int DMIF1_ASYNC_MEM_PWR_STATE : 2; - unsigned int DMIF1_DATA_MEM_PWR_STATE : 2; - unsigned int DMIF1_CHUNK_MEM_PWR_STATE : 1; - unsigned int DMIF2_ASYNC_MEM_PWR_STATE : 2; - unsigned int DMIF2_DATA_MEM_PWR_STATE : 2; - unsigned int DMIF2_CHUNK_MEM_PWR_STATE : 1; - unsigned int DMIF3_ASYNC_MEM_PWR_STATE : 2; - unsigned int DMIF3_DATA_MEM_PWR_STATE : 2; - unsigned int DMIF3_CHUNK_MEM_PWR_STATE : 1; - unsigned int DMIF4_ASYNC_MEM_PWR_STATE : 2; - unsigned int DMIF4_DATA_MEM_PWR_STATE : 2; - unsigned int DMIF4_CHUNK_MEM_PWR_STATE : 1; - unsigned int DMIF5_ASYNC_MEM_PWR_STATE : 2; - unsigned int DMIF5_DATA_MEM_PWR_STATE : 2; - unsigned int DMIF5_CHUNK_MEM_PWR_STATE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_PG_DEBUG_CONFIG__VI { - struct { - unsigned int DCI_PG_DBG_EN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCI_SOFT_RESET__VI { - struct { - unsigned int VGA_SOFT_RESET : 1; - unsigned int VIP_SOFT_RESET : 1; - unsigned int MCIF_SOFT_RESET : 1; - unsigned int FBC_SOFT_RESET : 1; - unsigned int DMIF0_SOFT_RESET : 1; - unsigned int DMIF1_SOFT_RESET : 1; - unsigned int DMIF2_SOFT_RESET : 1; - unsigned int DMIF3_SOFT_RESET : 1; - unsigned int DMIF4_SOFT_RESET : 1; - unsigned int DMIF5_SOFT_RESET : 1; - unsigned int DCFEV0_L_SOFT_RESET : 1; - unsigned int DCFEV0_C_SOFT_RESET : 1; - unsigned int DMIFARB_SOFT_RESET : 1; - unsigned int : 3; - unsigned int MCIF_DWB_SOFT_RESET : 1; - unsigned int MCIF_CWB0_SOFT_RESET : 1; - unsigned int MCIF_CWB1_SOFT_RESET : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_CLK_CNTL__VI { - struct { - unsigned int DCO_TEST_CLK_SEL : 5; - unsigned int DISPCLK_R_DCO_GATE_DIS : 1; - unsigned int DISPCLK_G_ABM_GATE_DIS : 1; - unsigned int DISPCLK_G_DVO_GATE_DIS : 1; - unsigned int DISPCLK_G_DACA_GATE_DIS : 1; - unsigned int DISPCLK_G_DACB_GATE_DIS : 1; - unsigned int REFCLK_R_DCO_GATE_DIS : 1; - unsigned int : 5; - unsigned int DISPCLK_G_FMT0_GATE_DIS : 1; - unsigned int DISPCLK_G_FMT1_GATE_DIS : 1; - unsigned int DISPCLK_G_FMT2_GATE_DIS : 1; - unsigned int DISPCLK_G_FMT3_GATE_DIS : 1; - unsigned int DISPCLK_G_FMT4_GATE_DIS : 1; - unsigned int DISPCLK_G_FMT5_GATE_DIS : 1; - unsigned int : 2; - unsigned int DISPCLK_G_DIGA_GATE_DIS : 1; - unsigned int DISPCLK_G_DIGB_GATE_DIS : 1; - unsigned int DISPCLK_G_DIGC_GATE_DIS : 1; - unsigned int DISPCLK_G_DIGD_GATE_DIS : 1; - unsigned int DISPCLK_G_DIGE_GATE_DIS : 1; - unsigned int DISPCLK_G_DIGF_GATE_DIS : 1; - unsigned int DISPCLK_G_DIGG_GATE_DIS : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_CLK_RAMP_CNTL__VI { - struct { - unsigned int : 4; - unsigned int REFCLK_R_DCO_RAMP_DIS : 1; - unsigned int DISPCLK_R_DCO_RAMP_DIS : 1; - unsigned int DISPCLK_G_ABM_RAMP_DIS : 1; - unsigned int DISPCLK_G_DVO_RAMP_DIS : 1; - unsigned int DISPCLK_G_DACA_RAMP_DIS : 1; - unsigned int DISPCLK_G_DACB_RAMP_DIS : 1; - unsigned int : 6; - unsigned int DISPCLK_G_FMT0_RAMP_DIS : 1; - unsigned int DISPCLK_G_FMT1_RAMP_DIS : 1; - unsigned int DISPCLK_G_FMT2_RAMP_DIS : 1; - unsigned int DISPCLK_G_FMT3_RAMP_DIS : 1; - unsigned int DISPCLK_G_FMT4_RAMP_DIS : 1; - unsigned int DISPCLK_G_FMT5_RAMP_DIS : 1; - unsigned int : 2; - unsigned int DISPCLK_G_DIGA_RAMP_DIS : 1; - unsigned int DISPCLK_G_DIGB_RAMP_DIS : 1; - unsigned int DISPCLK_G_DIGC_RAMP_DIS : 1; - unsigned int DISPCLK_G_DIGD_RAMP_DIS : 1; - unsigned int DISPCLK_G_DIGE_RAMP_DIS : 1; - unsigned int DISPCLK_G_DIGF_RAMP_DIS : 1; - unsigned int DISPCLK_G_DIGG_RAMP_DIS : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_DCFE_EXT_VSYNC_CNTL__VI { - struct { - unsigned int DCO_DCFE0_EXT_VSYNC_MUX : 3; - unsigned int : 1; - unsigned int DCO_DCFE1_EXT_VSYNC_MUX : 3; - unsigned int : 1; - unsigned int DCO_DCFE2_EXT_VSYNC_MUX : 3; - unsigned int : 1; - unsigned int DCO_DCFE3_EXT_VSYNC_MUX : 3; - unsigned int : 1; - unsigned int DCO_DCFE4_EXT_VSYNC_MUX : 3; - unsigned int : 1; - unsigned int DCO_DCFE5_EXT_VSYNC_MUX : 3; - unsigned int : 1; - unsigned int DCO_SWAPLOCKB_EXT_VSYNC_MASK : 3; - unsigned int : 1; - unsigned int DCO_GENERICB_EXT_VSYNC_MASK : 3; - unsigned int DCO_CRTC_MANUAL_FLOW_CONTROL : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_MEM_PWR_CTRL__VI { - struct { - unsigned int I2C_LIGHT_SLEEP_FORCE : 1; - unsigned int I2C_LIGHT_SLEEP_DIS : 1; - unsigned int TVOUT_LIGHT_SLEEP_DIS : 1; - unsigned int MVP_LIGHT_SLEEP_DIS : 1; - unsigned int DPA_LIGHT_SLEEP_DIS : 1; - unsigned int DPB_LIGHT_SLEEP_DIS : 1; - unsigned int DPC_LIGHT_SLEEP_DIS : 1; - unsigned int DPD_LIGHT_SLEEP_DIS : 1; - unsigned int DPE_LIGHT_SLEEP_DIS : 1; - unsigned int DPF_LIGHT_SLEEP_DIS : 1; - unsigned int DPG_LIGHT_SLEEP_DIS : 1; - unsigned int HDMI0_MEM_PWR_FORCE : 2; - unsigned int HDMI0_MEM_PWR_DIS : 1; - unsigned int HDMI1_MEM_PWR_FORCE : 2; - unsigned int HDMI1_MEM_PWR_DIS : 1; - unsigned int HDMI2_MEM_PWR_FORCE : 2; - unsigned int HDMI2_MEM_PWR_DIS : 1; - unsigned int HDMI3_MEM_PWR_FORCE : 2; - unsigned int HDMI3_MEM_PWR_DIS : 1; - unsigned int HDMI4_MEM_PWR_FORCE : 2; - unsigned int HDMI4_MEM_PWR_DIS : 1; - unsigned int HDMI5_MEM_PWR_FORCE : 2; - unsigned int HDMI5_MEM_PWR_DIS : 1; - unsigned int HDMI6_MEM_PWR_FORCE : 2; - unsigned int HDMI6_MEM_PWR_DIS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_MEM_PWR_CTRL2__VI { - struct { - unsigned int HDMI_MEM_PWR_MODE_SEL : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_MEM_PWR_STATUS__VI { - struct { - unsigned int I2C_MEM_PWR_STATE : 1; - unsigned int TVOUT_MEM_PWR_STATE : 1; - unsigned int MVP_MEM_PWR_STATE : 1; - unsigned int DPA_MEM_PWR_STATE : 1; - unsigned int DPB_MEM_PWR_STATE : 1; - unsigned int DPC_MEM_PWR_STATE : 1; - unsigned int DPD_MEM_PWR_STATE : 1; - unsigned int DPE_MEM_PWR_STATE : 1; - unsigned int DPF_MEM_PWR_STATE : 1; - unsigned int DPG_MEM_PWR_STATE : 1; - unsigned int HDMI0_MEM_PWR_STATE : 2; - unsigned int HDMI1_MEM_PWR_STATE : 2; - unsigned int HDMI2_MEM_PWR_STATE : 2; - unsigned int HDMI3_MEM_PWR_STATE : 2; - unsigned int HDMI4_MEM_PWR_STATE : 2; - unsigned int HDMI5_MEM_PWR_STATE : 2; - unsigned int HDMI6_MEM_PWR_STATE : 2; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_POWER_MANAGEMENT_CNTL__VI { - struct { - unsigned int PM_ASSERT_RESET : 1; - unsigned int : 7; - unsigned int PM_ALL_BUSY_OFF : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_SCRATCH0__VI { - struct { - unsigned int DCO_SCRATCH0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_SCRATCH1__VI { - struct { - unsigned int DCO_SCRATCH1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_SCRATCH2__VI { - struct { - unsigned int DCO_SCRATCH2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_SCRATCH3__VI { - struct { - unsigned int DCO_SCRATCH3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_SCRATCH4__VI { - struct { - unsigned int DCO_SCRATCH4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_SCRATCH5__VI { - struct { - unsigned int DCO_SCRATCH5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_SCRATCH6__VI { - struct { - unsigned int DCO_SCRATCH6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_SCRATCH7__VI { - struct { - unsigned int DCO_SCRATCH7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_SOFT_RESET__VI { - struct { - unsigned int DACA_SOFT_RESET : 1; - unsigned int : 3; - unsigned int I2S0_SPDIF0_SOFT_RESET : 1; - unsigned int I2S1_SOFT_RESET : 1; - unsigned int SPDIF1_SOFT_RESET : 1; - unsigned int : 5; - unsigned int DB_CLK_SOFT_RESET : 1; - unsigned int : 3; - unsigned int FMT0_SOFT_RESET : 1; - unsigned int FMT1_SOFT_RESET : 1; - unsigned int FMT2_SOFT_RESET : 1; - unsigned int FMT3_SOFT_RESET : 1; - unsigned int FMT4_SOFT_RESET : 1; - unsigned int FMT5_SOFT_RESET : 1; - unsigned int : 2; - unsigned int MVP_SOFT_RESET : 1; - unsigned int ABM_SOFT_RESET : 1; - unsigned int : 1; - unsigned int DVO_SOFT_RESET : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_STEREOSYNC_SEL__VI { - struct { - unsigned int GENERICA_STEREOSYNC_SEL : 3; - unsigned int : 13; - unsigned int GENERICB_STEREOSYNC_SEL : 3; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_TEST_DEBUG_DATA__VI { - struct { - unsigned int DCO_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCO_TEST_DEBUG_INDEX__VI { - struct { - unsigned int DCO_TEST_DEBUG_INDEX : 8; - unsigned int DCO_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCPG_TEST_DEBUG_DATA__VI { - struct { - unsigned int DCPG_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCPG_TEST_DEBUG_INDEX__VI { - struct { - unsigned int DCPG_TEST_DEBUG_INDEX : 8; - unsigned int DCPG_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_DEBUG2__VI { - struct { - unsigned int DCP_DEBUG2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_FP_CONVERTED_FIELD__VI { - struct { - unsigned int DCP_FP_CONVERTED_FIELD_DATA : 18; - unsigned int : 2; - unsigned int DCP_FP_CONVERTED_FIELD_INDEX : 7; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_GSL_CONTROL__VI { - struct { - unsigned int DCP_GSL0_EN : 1; - unsigned int DCP_GSL1_EN : 1; - unsigned int DCP_GSL2_EN : 1; - unsigned int : 5; - unsigned int DCP_GSL_MODE : 2; - unsigned int : 2; - unsigned int DCP_GSL_HSYNC_FLIP_FORCE_DELAY : 4; - unsigned int DCP_GSL_MASTER_EN : 1; - unsigned int DCP_GSL_XDMA_GROUP : 2; - unsigned int DCP_GSL_XDMA_GROUP_UNDERFLOW_EN : 1; - unsigned int : 4; - unsigned int DCP_GSL_SYNC_SOURCE : 2; - unsigned int : 1; - unsigned int DCP_GSL_DELAY_SURFACE_UPDATE_PENDING : 1; - unsigned int DCP_GSL_HSYNC_FLIP_CHECK_DELAY : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_RANDOM_SEEDS__VI { - struct { - unsigned int DCP_RAND_R_SEED : 8; - unsigned int DCP_RAND_G_SEED : 8; - unsigned int DCP_RAND_B_SEED : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCP_SPATIAL_DITHER_CNTL__VI { - struct { - unsigned int DCP_SPATIAL_DITHER_EN : 1; - unsigned int : 3; - unsigned int DCP_SPATIAL_DITHER_MODE : 2; - unsigned int DCP_SPATIAL_DITHER_DEPTH : 2; - unsigned int DCP_FRAME_RANDOM_ENABLE : 1; - unsigned int DCP_RGB_RANDOM_ENABLE : 1; - unsigned int DCP_HIGHPASS_RANDOM_ENABLE : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED0__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED1__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED10__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED100__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED101__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED102__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED103__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED104__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED105__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED106__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED107__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED108__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED109__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED11__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED110__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED111__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED112__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED113__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED114__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED115__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED116__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED117__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED118__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED119__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED12__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED120__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED121__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED122__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED123__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED124__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED125__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED126__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED127__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED128__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED129__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED13__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED130__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED131__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED132__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED133__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED134__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED135__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED136__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED137__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED138__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED139__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED14__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED140__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED141__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED142__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED143__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED144__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED145__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED146__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED147__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED148__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED149__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED15__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED150__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED151__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED152__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED153__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED154__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED155__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED156__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED157__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED158__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED159__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED16__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED160__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED161__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED162__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED163__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED164__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED165__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED166__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED167__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED168__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED169__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED17__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED170__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED171__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED172__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED173__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED174__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED175__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED176__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED177__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED178__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED179__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED18__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED180__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED181__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED182__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED183__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED184__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED185__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED186__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED187__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED188__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED189__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED19__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED190__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED191__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED192__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED193__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED194__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED195__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED196__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED197__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED198__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED199__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED2__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED20__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED200__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED201__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED202__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED203__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED204__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED205__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED206__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED207__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED208__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED209__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED21__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED210__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED211__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED212__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED213__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED214__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED215__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED216__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED217__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED218__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED219__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED22__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED220__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED221__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED222__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED223__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED224__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED225__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED226__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED227__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED228__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED229__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED23__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED230__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED231__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED232__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED233__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED234__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED235__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED236__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED237__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED238__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED239__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED24__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED240__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED241__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED242__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED243__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED244__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED245__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED246__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED247__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED248__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED249__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED25__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED250__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED251__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED252__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED253__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED254__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED255__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED256__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED257__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED258__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED259__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED26__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED260__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED261__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED262__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED263__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED264__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED265__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED266__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED267__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED268__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED269__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED27__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED270__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED271__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED272__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED273__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED274__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED275__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED276__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED277__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED278__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED279__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED28__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED280__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED281__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED282__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED283__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED284__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED285__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED286__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED287__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED288__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED289__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED29__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED290__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED291__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED292__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED293__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED294__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED295__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED296__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED297__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED298__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED299__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED3__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED30__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED300__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED301__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED302__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED303__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED304__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED305__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED306__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED307__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED308__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED309__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED31__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED310__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED311__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED312__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED313__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED314__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED315__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED316__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED317__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED318__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED319__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED32__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED320__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED321__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED322__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED323__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED324__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED325__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED326__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED327__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED328__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED329__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED33__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED330__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED331__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED332__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED333__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED334__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED335__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED336__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED337__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED338__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED339__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED34__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED340__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED341__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED342__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED343__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED344__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED345__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED346__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED347__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED348__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED349__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED35__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED350__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED351__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED352__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED353__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED354__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED355__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED356__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED357__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED358__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED359__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED36__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED360__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED361__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED362__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED363__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED364__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED365__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED366__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED367__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED368__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED369__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED37__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED370__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED371__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED372__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED373__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED374__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED375__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED376__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED377__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED378__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED379__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED38__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED39__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED4__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED40__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED41__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED42__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED43__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED44__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED45__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED46__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED47__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED48__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED49__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED5__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED50__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED51__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED52__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED53__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED54__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED55__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED56__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED57__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED58__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED59__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED6__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED60__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED61__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED62__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED63__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED64__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED65__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED66__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED67__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED68__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED69__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED7__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED70__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED71__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED72__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED73__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED74__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED75__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED76__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED77__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED78__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED79__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED8__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED80__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED81__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED82__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED83__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED84__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED85__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED86__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED87__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED88__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED89__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED9__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED90__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED91__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED92__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED93__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED94__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED95__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED96__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED97__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED98__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DCRX_PHY_MACRO_CNTL_RESERVED99__VI { - struct { - unsigned int DCRX_PHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_ABM1_OVERSCAN_PIXEL_VALUE__VI { - struct { - unsigned int ABM1_OVERSCAN_R_PIXEL_VALUE : 10; - unsigned int ABM1_OVERSCAN_G_PIXEL_VALUE : 10; - unsigned int ABM1_OVERSCAN_B_PIXEL_VALUE : 10; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_DVODATA_CONFIG__VI { - struct { - unsigned int : 19; - unsigned int VIP_MUX_EN : 1; - unsigned int VIP_ALTER_MAPPING_EN : 1; - unsigned int DVO_ALTER_MAPPING_EN : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDCVGA_A__VI { - struct { - unsigned int DC_GPIO_DDCVGACLK_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDCVGADATA_A : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDCVGA_EN__VI { - struct { - unsigned int DC_GPIO_DDCVGACLK_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDCVGADATA_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDCVGA_MASK__VI { - struct { - unsigned int DC_GPIO_DDCVGACLK_MASK : 1; - unsigned int : 5; - unsigned int DC_GPIO_DDCVGACLK_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDCVGADATA_MASK : 1; - unsigned int : 3; - unsigned int DC_GPIO_DDCVGADATA_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDCVGADATA_RECV : 1; - unsigned int : 1; - unsigned int AUX_PADVGA_MODE : 1; - unsigned int : 3; - unsigned int AUXVGA_POL : 1; - unsigned int : 1; - unsigned int ALLOW_HW_DDCVGA_PD_EN : 1; - unsigned int : 1; - unsigned int DC_GPIO_DDCVGACLK_STR : 4; - unsigned int DC_GPIO_DDCVGADATA_STR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_DDCVGA_Y__VI { - struct { - unsigned int DC_GPIO_DDCVGACLK_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_DDCVGADATA_Y : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_GENLK_A__VI { - struct { - unsigned int DC_GPIO_GENLK_CLK_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_GENLK_VSYNC_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_SWAPLOCK_A_A : 1; - unsigned int : 7; - unsigned int DC_GPIO_SWAPLOCK_B_A : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_GENLK_EN__VI { - struct { - unsigned int DC_GPIO_GENLK_CLK_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_GENLK_VSYNC_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_SWAPLOCK_A_EN : 1; - unsigned int : 7; - unsigned int DC_GPIO_SWAPLOCK_B_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_GENLK_MASK__VI { - struct { - unsigned int DC_GPIO_GENLK_CLK_MASK : 1; - unsigned int DC_GPIO_GENLK_CLK_PD_DIS : 1; - unsigned int DC_GPIO_GENLK_CLK_RECV : 1; - unsigned int DC_GPIO_GENLK_CLK_PU_EN : 1; - unsigned int : 4; - unsigned int DC_GPIO_GENLK_VSYNC_MASK : 1; - unsigned int DC_GPIO_GENLK_VSYNC_PD_DIS : 1; - unsigned int DC_GPIO_GENLK_VSYNC_RECV : 1; - unsigned int DC_GPIO_GENLK_VSYNC_PU_EN : 1; - unsigned int : 4; - unsigned int DC_GPIO_SWAPLOCK_A_MASK : 1; - unsigned int DC_GPIO_SWAPLOCK_A_PD_DIS : 1; - unsigned int DC_GPIO_SWAPLOCK_A_RECV : 1; - unsigned int DC_GPIO_SWAPLOCK_A_PU_EN : 1; - unsigned int : 4; - unsigned int DC_GPIO_SWAPLOCK_B_MASK : 1; - unsigned int DC_GPIO_SWAPLOCK_B_PD_DIS : 1; - unsigned int DC_GPIO_SWAPLOCK_B_RECV : 1; - unsigned int DC_GPIO_SWAPLOCK_B_PU_EN : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_GENLK_Y__VI { - struct { - unsigned int DC_GPIO_GENLK_CLK_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_GENLK_VSYNC_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_SWAPLOCK_A_Y : 1; - unsigned int : 7; - unsigned int DC_GPIO_SWAPLOCK_B_Y : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_I2CPAD_A__VI { - struct { - unsigned int DC_GPIO_SCL_A : 1; - unsigned int DC_GPIO_SDA_A : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_I2CPAD_EN__VI { - struct { - unsigned int DC_GPIO_SCL_EN : 1; - unsigned int DC_GPIO_SDA_EN : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_I2CPAD_MASK__VI { - struct { - unsigned int DC_GPIO_SCL_MASK : 1; - unsigned int DC_GPIO_SCL_PD_DIS : 1; - unsigned int DC_GPIO_SCL_RECV : 1; - unsigned int : 1; - unsigned int DC_GPIO_SDA_MASK : 1; - unsigned int DC_GPIO_SDA_PD_DIS : 1; - unsigned int DC_GPIO_SDA_RECV : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_I2CPAD_STRENGTH__VI { - struct { - unsigned int I2C_STRENGTH_SN : 4; - unsigned int I2C_STRENGTH_SP : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPIO_I2CPAD_Y__VI { - struct { - unsigned int DC_GPIO_SCL_Y : 1; - unsigned int DC_GPIO_SDA_Y : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPU_TIMER_START_POSITION_P_FLIP__VI { - struct { - unsigned int DC_GPU_TIMER_START_POSITION_D1_P_FLIP : 3; - unsigned int : 1; - unsigned int DC_GPU_TIMER_START_POSITION_D2_P_FLIP : 3; - unsigned int : 1; - unsigned int DC_GPU_TIMER_START_POSITION_D3_P_FLIP : 3; - unsigned int : 1; - unsigned int DC_GPU_TIMER_START_POSITION_D4_P_FLIP : 3; - unsigned int : 1; - unsigned int DC_GPU_TIMER_START_POSITION_D5_P_FLIP : 3; - unsigned int : 1; - unsigned int DC_GPU_TIMER_START_POSITION_D6_P_FLIP : 3; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_GPU_TIMER_START_POSITION_V_UPDATE__VI { - struct { - unsigned int DC_GPU_TIMER_START_POSITION_D1_V_UPDATE : 3; - unsigned int : 1; - unsigned int DC_GPU_TIMER_START_POSITION_D2_V_UPDATE : 3; - unsigned int : 1; - unsigned int DC_GPU_TIMER_START_POSITION_D3_V_UPDATE : 3; - unsigned int : 1; - unsigned int DC_GPU_TIMER_START_POSITION_D4_V_UPDATE : 3; - unsigned int : 1; - unsigned int DC_GPU_TIMER_START_POSITION_D5_V_UPDATE : 3; - unsigned int : 1; - unsigned int DC_GPU_TIMER_START_POSITION_D6_V_UPDATE : 3; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD_CONTROL__VI { - struct { - unsigned int DC_HPD_CONNECTION_TIMER : 13; - unsigned int : 3; - unsigned int DC_HPD_RX_INT_TIMER : 10; - unsigned int : 2; - unsigned int DC_HPD_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD_FAST_TRAIN_CNTL__VI { - struct { - unsigned int DC_HPD_CONNECT_AUX_TX_DELAY : 8; - unsigned int : 4; - unsigned int DC_HPD_CONNECT_FAST_TRAIN_DELAY : 8; - unsigned int : 4; - unsigned int DC_HPD_CONNECT_AUX_TX_EN : 1; - unsigned int : 3; - unsigned int DC_HPD_CONNECT_FAST_TRAIN_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD_INT_CONTROL__VI { - struct { - unsigned int DC_HPD_INT_ACK : 1; - unsigned int : 7; - unsigned int DC_HPD_INT_POLARITY : 1; - unsigned int : 7; - unsigned int DC_HPD_INT_EN : 1; - unsigned int : 3; - unsigned int DC_HPD_RX_INT_ACK : 1; - unsigned int : 3; - unsigned int DC_HPD_RX_INT_EN : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD_INT_STATUS__VI { - struct { - unsigned int DC_HPD_INT_STATUS : 1; - unsigned int DC_HPD_SENSE : 1; - unsigned int : 2; - unsigned int DC_HPD_SENSE_DELAYED : 1; - unsigned int : 3; - unsigned int DC_HPD_RX_INT_STATUS : 1; - unsigned int : 3; - unsigned int DC_HPD_TOGGLE_FILT_CON_TIMER_VAL : 8; - unsigned int : 4; - unsigned int DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_HPD_TOGGLE_FILT_CNTL__VI { - struct { - unsigned int DC_HPD_CONNECT_INT_DELAY : 8; - unsigned int : 12; - unsigned int DC_HPD_DISCONNECT_INT_DELAY : 8; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDCVGA_HW_STATUS__VI { - struct { - unsigned int DC_I2C_DDCVGA_HW_STATUS : 2; - unsigned int : 1; - unsigned int DC_I2C_DDCVGA_HW_DONE : 1; - unsigned int : 12; - unsigned int DC_I2C_DDCVGA_HW_REQ : 1; - unsigned int DC_I2C_DDCVGA_HW_URG : 1; - unsigned int : 2; - unsigned int DC_I2C_DDCVGA_EDID_DETECT_STATUS : 1; - unsigned int : 3; - unsigned int DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES : 4; - unsigned int DC_I2C_DDCVGA_EDID_DETECT_STATE : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDCVGA_SETUP__VI { - struct { - unsigned int DC_I2C_DDCVGA_DATA_DRIVE_EN : 1; - unsigned int DC_I2C_DDCVGA_DATA_DRIVE_SEL : 1; - unsigned int : 2; - unsigned int DC_I2C_DDCVGA_EDID_DETECT_ENABLE : 1; - unsigned int DC_I2C_DDCVGA_EDID_DETECT_MODE : 1; - unsigned int DC_I2C_DDCVGA_ENABLE : 1; - unsigned int DC_I2C_DDCVGA_CLK_DRIVE_EN : 1; - unsigned int DC_I2C_DDCVGA_INTRA_BYTE_DELAY : 8; - unsigned int DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY : 8; - unsigned int DC_I2C_DDCVGA_TIME_LIMIT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_DDCVGA_SPEED__VI { - struct { - unsigned int DC_I2C_DDCVGA_THRESHOLD : 2; - unsigned int : 2; - unsigned int DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL : 1; - unsigned int : 11; - unsigned int DC_I2C_DDCVGA_PRESCALE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_I2C_EDID_DETECT_CTRL__VI { - struct { - unsigned int DC_I2C_EDID_DETECT_WAIT_TIME : 16; - unsigned int : 4; - unsigned int DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID : 4; - unsigned int : 4; - unsigned int DC_I2C_EDID_DETECT_SEND_RESET : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_IP_REQUEST_CNTL__VI { - struct { - unsigned int IP_REQUEST_EN : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_LUT_VGA_ACCESS_ENABLE__VI { - struct { - unsigned int DC_LUT_VGA_ACCESS_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_MEM_GLOBAL_PWR_REQ_CNTL__VI { - struct { - unsigned int DC_MEM_GLOBAL_PWR_REQ_DIS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_PGCNTL_STATUS_REG__VI { - struct { - unsigned int SWREQ_RWOP_BUSY : 1; - unsigned int SWREQ_RWOP_FORCE : 1; - unsigned int IPREQ_IGNORE_STATUS : 1; - unsigned int : 13; - unsigned int DCPG_ECO_DEBUG : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_PGFSM_CONFIG_REG__VI { - struct { - unsigned int PGFSM_CONFIG_REG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DC_PGFSM_WRITE_REG__VI { - struct { - unsigned int PGFSM_WRITE_REG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DEGAMMA_CONTROL__VI { - struct { - unsigned int GRPH_DEGAMMA_MODE : 2; - unsigned int : 2; - unsigned int OVL_DEGAMMA_MODE : 2; - unsigned int : 2; - unsigned int CURSOR2_DEGAMMA_MODE : 2; - unsigned int : 2; - unsigned int CURSOR_DEGAMMA_MODE : 2; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DENORM_CLAMP_CONTROL__VI { - struct { - unsigned int DENORM_FACTOR : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DENORM_CLAMP_RANGE_B_CB__VI { - struct { - unsigned int RANGE_CLAMP_MAX_B_CB : 12; - unsigned int RANGE_CLAMP_MIN_B_CB : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DENORM_CLAMP_RANGE_G_Y__VI { - struct { - unsigned int RANGE_CLAMP_MAX_G_Y : 12; - unsigned int RANGE_CLAMP_MIN_G_Y : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DENORM_CLAMP_RANGE_R_CR__VI { - struct { - unsigned int RANGE_CLAMP_MAX_R_CR : 12; - unsigned int RANGE_CLAMP_MIN_R_CR : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DENORM_CONTROL__VI { - struct { - unsigned int DENORM_MODE : 3; - unsigned int : 1; - unsigned int DENORM_14BIT_OUT : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DBR_CTRL0__VI { - struct { - unsigned int DIDT_CTRL_EN : 1; - unsigned int USE_REF_CLOCK : 1; - unsigned int PHASE_OFFSET : 2; - unsigned int DIDT_CTRL_RST : 1; - unsigned int DIDT_CLK_EN_OVERRIDE : 1; - unsigned int : 6; - unsigned int : 6; - unsigned int UNUSED_0 : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DBR_CTRL1__VI { - struct { - unsigned int MIN_POWER : 16; - unsigned int MAX_POWER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DBR_CTRL2__VI { - struct { - unsigned int MAX_POWER_DELTA : 14; - unsigned int UNUSED_0 : 2; - unsigned int SHORT_TERM_INTERVAL_SIZE : 10; - unsigned int UNUSED_1 : 1; - unsigned int LONG_TERM_INTERVAL_RATIO : 4; - unsigned int UNUSED_2 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DBR_CTRL_OCP__VI { - struct { - unsigned int UNUSED_0 : 16; - unsigned int OCP_MAX_POWER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DBR_WEIGHT0_3__VI { - struct { - unsigned int WEIGHT0 : 8; - unsigned int WEIGHT1 : 8; - unsigned int WEIGHT2 : 8; - unsigned int WEIGHT3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DBR_WEIGHT4_7__VI { - struct { - unsigned int WEIGHT4 : 8; - unsigned int WEIGHT5 : 8; - unsigned int WEIGHT6 : 8; - unsigned int WEIGHT7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DBR_WEIGHT8_11__VI { - struct { - unsigned int WEIGHT8 : 8; - unsigned int WEIGHT9 : 8; - unsigned int WEIGHT10 : 8; - unsigned int WEIGHT11 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_DB_CTRL_OCP__VI { - struct { - unsigned int UNUSED_0 : 16; - unsigned int OCP_MAX_POWER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_SQ_CTRL_OCP__VI { - struct { - unsigned int UNUSED_0 : 16; - unsigned int OCP_MAX_POWER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TCP_CTRL_OCP__VI { - struct { - unsigned int UNUSED_0 : 16; - unsigned int OCP_MAX_POWER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIDT_TD_CTRL_OCP__VI { - struct { - unsigned int UNUSED_0 : 16; - unsigned int OCP_MAX_POWER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_BE_CNTL__VI { - struct { - unsigned int : 8; - unsigned int DIG_FE_SOURCE_SELECT : 7; - unsigned int : 1; - unsigned int DIG_MODE : 3; - unsigned int : 9; - unsigned int DIG_HPD_SELECT : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_BE_EN_CNTL__VI { - struct { - unsigned int DIG_ENABLE : 1; - unsigned int : 7; - unsigned int DIG_SYMCLK_BE_ON : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_DISPCLK_SWITCH_CNTL__VI { - struct { - unsigned int DIG_DISPCLK_SWITCH_POINT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_DISPCLK_SWITCH_STATUS__VI { - struct { - unsigned int DIG_DISPCLK_SWITCH_ALLOWED : 1; - unsigned int : 3; - unsigned int DIG_DISPCLK_SWITCH_ALLOWED_INT : 1; - unsigned int : 3; - unsigned int DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK : 1; - unsigned int : 3; - unsigned int DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_FE_CNTL__VI { - struct { - unsigned int DIG_SOURCE_SELECT : 3; - unsigned int : 1; - unsigned int DIG_STEREOSYNC_SELECT : 3; - unsigned int : 1; - unsigned int DIG_STEREOSYNC_GATE_EN : 1; - unsigned int : 1; - unsigned int DIG_START : 1; - unsigned int : 5; - unsigned int DIG_DUAL_LINK_ENABLE : 1; - unsigned int : 1; - unsigned int DIG_SWAP : 1; - unsigned int : 1; - unsigned int DIG_RB_SWITCH_EN : 1; - unsigned int : 3; - unsigned int DIG_SYMCLK_FE_ON : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_FE_TEST_DEBUG_DATA__VI { - struct { - unsigned int DIG_FE_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_FE_TEST_DEBUG_INDEX__VI { - struct { - unsigned int DIG_FE_TEST_DEBUG_INDEX : 8; - unsigned int DIG_FE_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_FIFO_STATUS__VI { - struct { - unsigned int DIG_FIFO_LEVEL_ERROR : 1; - unsigned int DIG_FIFO_USE_OVERWRITE_LEVEL : 1; - unsigned int DIG_FIFO_OVERWRITE_LEVEL : 6; - unsigned int DIG_FIFO_ERROR_ACK : 1; - unsigned int : 1; - unsigned int DIG_FIFO_CAL_AVERAGE_LEVEL : 6; - unsigned int DIG_FIFO_MAXIMUM_LEVEL : 5; - unsigned int : 1; - unsigned int DIG_FIFO_MINIMUM_LEVEL : 4; - unsigned int : 3; - unsigned int DIG_FIFO_CALIBRATED : 1; - unsigned int DIG_FIFO_FORCE_RECAL_AVERAGE : 1; - unsigned int DIG_FIFO_FORCE_RECOMP_MINMAX : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_LANE_ENABLE__VI { - struct { - unsigned int DIG_LANE0EN : 1; - unsigned int DIG_LANE1EN : 1; - unsigned int DIG_LANE2EN : 1; - unsigned int DIG_LANE3EN : 1; - unsigned int : 4; - unsigned int DIG_CLK_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_SOFT_RESET__VI { - struct { - unsigned int DIGA_FE_SOFT_RESET : 1; - unsigned int DIGA_BE_SOFT_RESET : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGB_FE_SOFT_RESET : 1; - unsigned int DIGB_BE_SOFT_RESET : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGC_FE_SOFT_RESET : 1; - unsigned int DIGC_BE_SOFT_RESET : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGD_FE_SOFT_RESET : 1; - unsigned int DIGD_BE_SOFT_RESET : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGE_FE_SOFT_RESET : 1; - unsigned int DIGE_BE_SOFT_RESET : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGF_FE_SOFT_RESET : 1; - unsigned int DIGF_BE_SOFT_RESET : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGG_FE_SOFT_RESET : 1; - unsigned int DIGG_BE_SOFT_RESET : 1; - unsigned int : 1; - unsigned int : 4; - unsigned int DPDBG_SOFT_RESET : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_TEST_DEBUG_DATA__VI { - struct { - unsigned int DIG_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DIG_TEST_DEBUG_INDEX__VI { - struct { - unsigned int DIG_TEST_DEBUG_INDEX : 8; - unsigned int DIG_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISPCLK_FREQ_CHANGE_CNTL__VI { - struct { - unsigned int DISPCLK_STEP_DELAY : 14; - unsigned int : 2; - unsigned int DISPCLK_STEP_SIZE : 4; - unsigned int DISPCLK_FREQ_RAMP_DONE : 1; - unsigned int : 4; - unsigned int DISPCLK_MAX_ERRDET_CYCLES : 3; - unsigned int DCCG_FIFO_ERRDET_RESET : 1; - unsigned int DCCG_FIFO_ERRDET_STATE : 1; - unsigned int DCCG_FIFO_ERRDET_OVR_EN : 1; - unsigned int DISPCLK_CHG_FWD_CORR_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISPPLL_BG_CNTL__VI { - struct { - unsigned int DISPPLL_BG_PDN : 1; - unsigned int : 3; - unsigned int DISPPLL_BG_ADJ : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS_CONTINUE3__VI { - struct { - unsigned int SCL_DISP4_MODE_CHANGE_INTERRUPT : 1; - unsigned int D4BLND_DATA_UNDERFLOW_INTERRUPT : 1; - unsigned int LB_D4_VLINE_INTERRUPT : 1; - unsigned int LB_D4_VBLANK_INTERRUPT : 1; - unsigned int CRTC4_SNAPSHOT_INTERRUPT : 1; - unsigned int CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1; - unsigned int CRTC4_FORCE_COUNT_NOW_INTERRUPT : 1; - unsigned int CRTC4_TRIGA_INTERRUPT : 1; - unsigned int CRTC4_TRIGB_INTERRUPT : 1; - unsigned int CRTC4_VSYNC_NOM_INTERRUPT : 1; - unsigned int CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1; - unsigned int DIGD_DP_VID_STREAM_DISABLE_INTERRUPT : 1; - unsigned int DC_HPD4_INTERRUPT : 1; - unsigned int DC_HPD4_RX_INTERRUPT : 1; - unsigned int AUX4_SW_DONE_INTERRUPT : 1; - unsigned int AUX4_LS_DONE_INTERRUPT : 1; - unsigned int BUFMGR_IHIF_INTERRUPT : 1; - unsigned int WBSCL_HOST_CONFLICT_INTERRUPT : 1; - unsigned int WBSCL_DATA_OVERFLOW_INTERRUPT : 1; - unsigned int : 1; - unsigned int CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1; - unsigned int CRTC3_EXT_TIMING_SYNC_INTERRUPT : 1; - unsigned int CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1; - unsigned int CRTC3_VERTICAL_INTERRUPT0 : 1; - unsigned int CRTC3_VERTICAL_INTERRUPT1 : 1; - unsigned int CRTC3_VERTICAL_INTERRUPT2 : 1; - unsigned int DISP_INTERRUPT_STATUS_CONTINUE4 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS_CONTINUE4__VI { - struct { - unsigned int SCL_DISP5_MODE_CHANGE_INTERRUPT : 1; - unsigned int D5BLND_DATA_UNDERFLOW_INTERRUPT : 1; - unsigned int LB_D5_VLINE_INTERRUPT : 1; - unsigned int LB_D5_VBLANK_INTERRUPT : 1; - unsigned int CRTC5_SNAPSHOT_INTERRUPT : 1; - unsigned int CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1; - unsigned int CRTC5_FORCE_COUNT_NOW_INTERRUPT : 1; - unsigned int CRTC5_TRIGA_INTERRUPT : 1; - unsigned int CRTC5_TRIGB_INTERRUPT : 1; - unsigned int CRTC5_VSYNC_NOM_INTERRUPT : 1; - unsigned int CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1; - unsigned int DIGE_DP_VID_STREAM_DISABLE_INTERRUPT : 1; - unsigned int DC_HPD5_INTERRUPT : 1; - unsigned int DC_HPD5_RX_INTERRUPT : 1; - unsigned int AUX5_SW_DONE_INTERRUPT : 1; - unsigned int AUX5_LS_DONE_INTERRUPT : 1; - unsigned int : 1; - unsigned int CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1; - unsigned int CRTC4_EXT_TIMING_SYNC_INTERRUPT : 1; - unsigned int CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1; - unsigned int CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1; - unsigned int CRTC5_EXT_TIMING_SYNC_INTERRUPT : 1; - unsigned int CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1; - unsigned int CRTC4_VERTICAL_INTERRUPT0 : 1; - unsigned int CRTC4_VERTICAL_INTERRUPT1 : 1; - unsigned int CRTC4_VERTICAL_INTERRUPT2 : 1; - unsigned int DISP_INTERRUPT_STATUS_CONTINUE5 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS_CONTINUE5__VI { - struct { - unsigned int SCL_DISP6_MODE_CHANGE_INTERRUPT : 1; - unsigned int D6BLND_DATA_UNDERFLOW_INTERRUPT : 1; - unsigned int LB_D6_VLINE_INTERRUPT : 1; - unsigned int LB_D6_VBLANK_INTERRUPT : 1; - unsigned int CRTC6_SNAPSHOT_INTERRUPT : 1; - unsigned int CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT : 1; - unsigned int CRTC6_FORCE_COUNT_NOW_INTERRUPT : 1; - unsigned int CRTC6_TRIGA_INTERRUPT : 1; - unsigned int CRTC6_TRIGB_INTERRUPT : 1; - unsigned int CRTC6_VSYNC_NOM_INTERRUPT : 1; - unsigned int CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1; - unsigned int DIGF_DP_VID_STREAM_DISABLE_INTERRUPT : 1; - unsigned int DC_HPD6_INTERRUPT : 1; - unsigned int DC_HPD6_RX_INTERRUPT : 1; - unsigned int AUX6_SW_DONE_INTERRUPT : 1; - unsigned int AUX6_LS_DONE_INTERRUPT : 1; - unsigned int : 1; - unsigned int CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT : 1; - unsigned int CRTC6_EXT_TIMING_SYNC_INTERRUPT : 1; - unsigned int CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT : 1; - unsigned int CRTC5_VERTICAL_INTERRUPT0 : 1; - unsigned int CRTC5_VERTICAL_INTERRUPT1 : 1; - unsigned int CRTC5_VERTICAL_INTERRUPT2 : 1; - unsigned int CRTC6_VERTICAL_INTERRUPT0 : 1; - unsigned int CRTC6_VERTICAL_INTERRUPT1 : 1; - unsigned int CRTC6_VERTICAL_INTERRUPT2 : 1; - unsigned int DISP_INTERRUPT_STATUS_CONTINUE6 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS_CONTINUE6__VI { - struct { - unsigned int DCRX_PERFMON_COUNTER0_INTERRUPT : 1; - unsigned int DCRX_PERFMON_COUNTER1_INTERRUPT : 1; - unsigned int DCRX_PERFMON_COUNTER2_INTERRUPT : 1; - unsigned int DCRX_PERFMON_COUNTER3_INTERRUPT : 1; - unsigned int DCRX_PERFMON_COUNTER4_INTERRUPT : 1; - unsigned int DCRX_PERFMON_COUNTER5_INTERRUPT : 1; - unsigned int DCRX_PERFMON_COUNTER6_INTERRUPT : 1; - unsigned int DCRX_PERFMON_COUNTER7_INTERRUPT : 1; - unsigned int DCRX_PERFMON_COUNTER_OFF_INTERRUPT : 1; - unsigned int BUFMGR_CWB0_IHIF_INTERRUPT : 1; - unsigned int BUFMGR_CWB1_IHIF_INTERRUPT : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT : 1; - unsigned int DIGG_DP_VID_STREAM_DISABLE_INTERRUPT : 1; - unsigned int AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT : 1; - unsigned int AUX1_GTC_SYNC_ERROR_INTERRUPT : 1; - unsigned int AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT : 1; - unsigned int AUX2_GTC_SYNC_ERROR_INTERRUPT : 1; - unsigned int AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT : 1; - unsigned int AUX3_GTC_SYNC_ERROR_INTERRUPT : 1; - unsigned int AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT : 1; - unsigned int AUX4_GTC_SYNC_ERROR_INTERRUPT : 1; - unsigned int AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT : 1; - unsigned int AUX5_GTC_SYNC_ERROR_INTERRUPT : 1; - unsigned int AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT : 1; - unsigned int AUX6_GTC_SYNC_ERROR_INTERRUPT : 1; - unsigned int : 2; - unsigned int DISP_INTERRUPT_STATUS_CONTINUE7 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS_CONTINUE7__VI { - struct { - unsigned int DCCG_PERFMON_COUNTER0_INTERRUPT : 1; - unsigned int DCCG_PERFMON_COUNTER1_INTERRUPT : 1; - unsigned int DCCG_PERFMON_COUNTER2_INTERRUPT : 1; - unsigned int DCCG_PERFMON_COUNTER3_INTERRUPT : 1; - unsigned int DCCG_PERFMON_COUNTER4_INTERRUPT : 1; - unsigned int DCCG_PERFMON_COUNTER5_INTERRUPT : 1; - unsigned int DCCG_PERFMON_COUNTER6_INTERRUPT : 1; - unsigned int DCCG_PERFMON_COUNTER7_INTERRUPT : 1; - unsigned int DCCG_PERFMON_COUNTER_OFF_INTERRUPT : 1; - unsigned int DCI_PERFMON_COUNTER0_INTERRUPT : 1; - unsigned int DCI_PERFMON_COUNTER1_INTERRUPT : 1; - unsigned int DCI_PERFMON_COUNTER2_INTERRUPT : 1; - unsigned int DCI_PERFMON_COUNTER3_INTERRUPT : 1; - unsigned int DCI_PERFMON_COUNTER4_INTERRUPT : 1; - unsigned int DCI_PERFMON_COUNTER5_INTERRUPT : 1; - unsigned int DCI_PERFMON_COUNTER6_INTERRUPT : 1; - unsigned int DCI_PERFMON_COUNTER7_INTERRUPT : 1; - unsigned int DCI_PERFMON_COUNTER_OFF_INTERRUPT : 1; - unsigned int DCO_PERFMON_COUNTER0_INTERRUPT : 1; - unsigned int DCO_PERFMON_COUNTER1_INTERRUPT : 1; - unsigned int DCO_PERFMON_COUNTER2_INTERRUPT : 1; - unsigned int DCO_PERFMON_COUNTER3_INTERRUPT : 1; - unsigned int DCO_PERFMON_COUNTER4_INTERRUPT : 1; - unsigned int DCO_PERFMON_COUNTER5_INTERRUPT : 1; - unsigned int DCO_PERFMON_COUNTER6_INTERRUPT : 1; - unsigned int DCO_PERFMON_COUNTER7_INTERRUPT : 1; - unsigned int DCO_PERFMON_COUNTER_OFF_INTERRUPT : 1; - unsigned int WB_PERFMON_COUNTER0_INTERRUPT : 1; - unsigned int WB_PERFMON_COUNTER1_INTERRUPT : 1; - unsigned int WB_PERFMON_COUNTER2_INTERRUPT : 1; - unsigned int WB_PERFMON_COUNTER3_INTERRUPT : 1; - unsigned int DISP_INTERRUPT_STATUS_CONTINUE8 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS_CONTINUE8__VI { - struct { - unsigned int DCFE0_PERFMON_COUNTER0_INTERRUPT : 1; - unsigned int DCFE0_PERFMON_COUNTER1_INTERRUPT : 1; - unsigned int DCFE0_PERFMON_COUNTER2_INTERRUPT : 1; - unsigned int DCFE0_PERFMON_COUNTER3_INTERRUPT : 1; - unsigned int DCFE0_PERFMON_COUNTER4_INTERRUPT : 1; - unsigned int DCFE0_PERFMON_COUNTER5_INTERRUPT : 1; - unsigned int DCFE0_PERFMON_COUNTER6_INTERRUPT : 1; - unsigned int DCFE0_PERFMON_COUNTER7_INTERRUPT : 1; - unsigned int DCFE0_PERFMON_COUNTER_OFF_INTERRUPT : 1; - unsigned int DCFE1_PERFMON_COUNTER0_INTERRUPT : 1; - unsigned int DCFE1_PERFMON_COUNTER1_INTERRUPT : 1; - unsigned int DCFE1_PERFMON_COUNTER2_INTERRUPT : 1; - unsigned int DCFE1_PERFMON_COUNTER3_INTERRUPT : 1; - unsigned int DCFE1_PERFMON_COUNTER4_INTERRUPT : 1; - unsigned int DCFE1_PERFMON_COUNTER5_INTERRUPT : 1; - unsigned int DCFE1_PERFMON_COUNTER6_INTERRUPT : 1; - unsigned int DCFE1_PERFMON_COUNTER7_INTERRUPT : 1; - unsigned int DCFE1_PERFMON_COUNTER_OFF_INTERRUPT : 1; - unsigned int DCFE2_PERFMON_COUNTER0_INTERRUPT : 1; - unsigned int DCFE2_PERFMON_COUNTER1_INTERRUPT : 1; - unsigned int DCFE2_PERFMON_COUNTER2_INTERRUPT : 1; - unsigned int DCFE2_PERFMON_COUNTER3_INTERRUPT : 1; - unsigned int DCFE2_PERFMON_COUNTER4_INTERRUPT : 1; - unsigned int DCFE2_PERFMON_COUNTER5_INTERRUPT : 1; - unsigned int DCFE2_PERFMON_COUNTER6_INTERRUPT : 1; - unsigned int DCFE2_PERFMON_COUNTER7_INTERRUPT : 1; - unsigned int DCFE2_PERFMON_COUNTER_OFF_INTERRUPT : 1; - unsigned int WB_PERFMON_COUNTER4_INTERRUPT : 1; - unsigned int WB_PERFMON_COUNTER5_INTERRUPT : 1; - unsigned int WB_PERFMON_COUNTER6_INTERRUPT : 1; - unsigned int WB_PERFMON_COUNTER7_INTERRUPT : 1; - unsigned int DISP_INTERRUPT_STATUS_CONTINUE9 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DISP_INTERRUPT_STATUS_CONTINUE9__VI { - struct { - unsigned int DCFE3_PERFMON_COUNTER0_INTERRUPT : 1; - unsigned int DCFE3_PERFMON_COUNTER1_INTERRUPT : 1; - unsigned int DCFE3_PERFMON_COUNTER2_INTERRUPT : 1; - unsigned int DCFE3_PERFMON_COUNTER3_INTERRUPT : 1; - unsigned int DCFE3_PERFMON_COUNTER4_INTERRUPT : 1; - unsigned int DCFE3_PERFMON_COUNTER5_INTERRUPT : 1; - unsigned int DCFE3_PERFMON_COUNTER6_INTERRUPT : 1; - unsigned int DCFE3_PERFMON_COUNTER7_INTERRUPT : 1; - unsigned int DCFE3_PERFMON_COUNTER_OFF_INTERRUPT : 1; - unsigned int DCFE4_PERFMON_COUNTER0_INTERRUPT : 1; - unsigned int DCFE4_PERFMON_COUNTER1_INTERRUPT : 1; - unsigned int DCFE4_PERFMON_COUNTER2_INTERRUPT : 1; - unsigned int DCFE4_PERFMON_COUNTER3_INTERRUPT : 1; - unsigned int DCFE4_PERFMON_COUNTER4_INTERRUPT : 1; - unsigned int DCFE4_PERFMON_COUNTER5_INTERRUPT : 1; - unsigned int DCFE4_PERFMON_COUNTER6_INTERRUPT : 1; - unsigned int DCFE4_PERFMON_COUNTER7_INTERRUPT : 1; - unsigned int DCFE4_PERFMON_COUNTER_OFF_INTERRUPT : 1; - unsigned int DCFE5_PERFMON_COUNTER0_INTERRUPT : 1; - unsigned int DCFE5_PERFMON_COUNTER1_INTERRUPT : 1; - unsigned int DCFE5_PERFMON_COUNTER2_INTERRUPT : 1; - unsigned int DCFE5_PERFMON_COUNTER3_INTERRUPT : 1; - unsigned int DCFE5_PERFMON_COUNTER4_INTERRUPT : 1; - unsigned int DCFE5_PERFMON_COUNTER5_INTERRUPT : 1; - unsigned int DCFE5_PERFMON_COUNTER6_INTERRUPT : 1; - unsigned int DCFE5_PERFMON_COUNTER7_INTERRUPT : 1; - unsigned int DCFE5_PERFMON_COUNTER_OFF_INTERRUPT : 1; - unsigned int WB_PERFMON_COUNTER_OFF_INTERRUPT : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_DPRX_INTERRUPT_STATUS1__VI { - struct { - unsigned int DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED : 1; - unsigned int DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED : 1; - unsigned int DPRX_SD0P0_VERTICAL_INT0_OCCURRED : 1; - unsigned int DPRX_SD0P0_VERTICAL_INT1_OCCURRED : 1; - unsigned int DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED : 1; - unsigned int DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED : 1; - unsigned int DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED : 1; - unsigned int DPRX_SD1P0_VERTICAL_INT0_OCCURRED : 1; - unsigned int DPRX_SD1P0_VERTICAL_INT1_OCCURRED : 1; - unsigned int DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED : 1; - unsigned int DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED : 1; - unsigned int DPRX_AUX_P0_AUX_INT_OCCURRED : 1; - unsigned int DPRX_AUX_P0_I2C_INT_OCCURRED : 1; - unsigned int DPRX_AUX_P0_CPU_INT_OCCURRED : 1; - unsigned int DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED : 1; - unsigned int DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED : 1; - unsigned int DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED : 1; - unsigned int DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__VI { - struct { - unsigned int DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN : 1; - unsigned int DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN : 1; - unsigned int DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN : 1; - unsigned int DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN : 1; - unsigned int DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN : 1; - unsigned int DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN : 1; - unsigned int DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN : 1; - unsigned int DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN : 1; - unsigned int DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN : 1; - unsigned int DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN : 1; - unsigned int DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN : 1; - unsigned int DPRX_AUX_P0_AUX_INT_TO_UC_EN : 1; - unsigned int DPRX_AUX_P0_I2C_INT_TO_UC_EN : 1; - unsigned int DPRX_AUX_P0_CPU_INT_TO_UC_EN : 1; - unsigned int DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN : 1; - unsigned int DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN : 1; - unsigned int DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN : 1; - unsigned int DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI { - struct { - unsigned int DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL : 1; - unsigned int DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_STATUS1__VI { - struct { - unsigned int DCI_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int DCI_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int DCI_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int DCI_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int DCI_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int DCI_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int DCI_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int DCI_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int DCO_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int DCO_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int DCO_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int DCO_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int DCO_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int DCO_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int DCO_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int DCO_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int DCCG_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int DCCG_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int DCCG_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int DCCG_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int DCCG_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int DCCG_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int DCCG_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int DCCG_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int DCI_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int DCO_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_STATUS2__VI { - struct { - unsigned int DCFE0_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int DCFE0_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int DCFE0_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int DCFE0_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int DCFE0_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int DCFE0_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int DCFE0_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int DCFE0_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int DCFE1_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int DCFE1_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int DCFE1_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int DCFE1_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int DCFE1_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int DCFE1_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int DCFE1_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int DCFE1_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int DCFE2_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int DCFE2_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int DCFE2_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int DCFE2_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int DCFE2_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int DCFE2_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int DCFE2_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int DCFE2_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_STATUS3__VI { - struct { - unsigned int DCFE3_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int DCFE3_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int DCFE3_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int DCFE3_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int DCFE3_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int DCFE3_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int DCFE3_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int DCFE3_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int DCFE4_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int DCFE4_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int DCFE4_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int DCFE4_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int DCFE4_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int DCFE4_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int DCFE4_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int DCFE4_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int DCFE5_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int DCFE5_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int DCFE5_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int DCFE5_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int DCFE5_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int DCFE5_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int DCFE5_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int DCFE5_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_STATUS4__VI { - struct { - unsigned int WB_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int WB_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int WB_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int WB_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int WB_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int WB_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int WB_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int WB_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int DCRX_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int DCRX_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int DCRX_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int DCRX_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int DCRX_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int DCRX_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int DCRX_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int DCRX_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int : 8; - unsigned int WB_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_STATUS5__VI { - struct { - unsigned int DCFEV_PERFMON_COUNTER0_INT_OCCURRED : 1; - unsigned int DCFEV_PERFMON_COUNTER1_INT_OCCURRED : 1; - unsigned int DCFEV_PERFMON_COUNTER2_INT_OCCURRED : 1; - unsigned int DCFEV_PERFMON_COUNTER3_INT_OCCURRED : 1; - unsigned int DCFEV_PERFMON_COUNTER4_INT_OCCURRED : 1; - unsigned int DCFEV_PERFMON_COUNTER5_INT_OCCURRED : 1; - unsigned int DCFEV_PERFMON_COUNTER6_INT_OCCURRED : 1; - unsigned int DCFEV_PERFMON_COUNTER7_INT_OCCURRED : 1; - unsigned int DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__VI { - struct { - unsigned int DCI_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int DCI_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int DCI_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int DCI_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int DCI_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int DCI_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int DCI_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int DCI_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int DCO_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int DCO_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int DCO_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int DCO_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int DCO_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int DCO_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int DCO_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int DCO_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int DCCG_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int DCCG_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int DCCG_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int DCCG_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int DCCG_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int DCCG_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int DCCG_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int DCCG_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int DCI_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int DCO_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int DCCG_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__VI { - struct { - unsigned int DCFE0_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int DCFE0_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int DCFE0_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int DCFE0_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int DCFE0_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int DCFE0_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int DCFE0_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int DCFE0_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int DCFE1_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int DCFE1_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int DCFE1_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int DCFE1_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int DCFE1_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int DCFE1_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int DCFE1_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int DCFE1_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int DCFE2_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int DCFE2_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int DCFE2_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int DCFE2_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int DCFE2_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int DCFE2_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int DCFE2_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int DCFE2_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int DCFE0_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int DCFE1_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int DCFE2_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__VI { - struct { - unsigned int DCFE3_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int DCFE3_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int DCFE3_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int DCFE3_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int DCFE3_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int DCFE3_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int DCFE3_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int DCFE3_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int DCFE4_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int DCFE4_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int DCFE4_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int DCFE4_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int DCFE4_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int DCFE4_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int DCFE4_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int DCFE4_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int DCFE5_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int DCFE5_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int DCFE5_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int DCFE5_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int DCFE5_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int DCFE5_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int DCFE5_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int DCFE5_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int DCFE3_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int DCFE4_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int DCFE5_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__VI { - struct { - unsigned int WB_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int WB_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int WB_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int WB_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int WB_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int WB_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int WB_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int WB_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int DCRX_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int DCRX_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int DCRX_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int DCRX_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int DCRX_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int DCRX_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int DCRX_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int DCRX_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int : 8; - unsigned int WB_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int DCRX_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__VI { - struct { - unsigned int DCFEV_PERFMON_COUNTER0_INT_MASK : 1; - unsigned int DCFEV_PERFMON_COUNTER1_INT_MASK : 1; - unsigned int DCFEV_PERFMON_COUNTER2_INT_MASK : 1; - unsigned int DCFEV_PERFMON_COUNTER3_INT_MASK : 1; - unsigned int DCFEV_PERFMON_COUNTER4_INT_MASK : 1; - unsigned int DCFEV_PERFMON_COUNTER5_INT_MASK : 1; - unsigned int DCFEV_PERFMON_COUNTER6_INT_MASK : 1; - unsigned int DCFEV_PERFMON_COUNTER7_INT_MASK : 1; - unsigned int DCFEV_PERFMON_COUNTER_OFF_INT_MASK : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__VI { - struct { - unsigned int DCI_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int DCI_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int DCI_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int DCI_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int DCI_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int DCI_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int DCI_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int DCI_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int DCO_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int DCO_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int DCO_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int DCO_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int DCO_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int DCO_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int DCO_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int DCO_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int DCCG_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int DCCG_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int DCCG_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int DCCG_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int DCCG_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int DCCG_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int DCCG_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int DCCG_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__VI { - struct { - unsigned int DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__VI { - struct { - unsigned int DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__VI { - struct { - unsigned int WB_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int WB_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int WB_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int WB_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int WB_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int WB_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int WB_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int WB_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int DCRX_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int DCRX_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int DCRX_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int DCRX_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int DCRX_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int DCRX_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int DCRX_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int DCRX_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int : 8; - unsigned int WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__VI { - struct { - unsigned int DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN : 1; - unsigned int DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN : 1; - unsigned int DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN : 1; - unsigned int DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN : 1; - unsigned int DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN : 1; - unsigned int DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN : 1; - unsigned int DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN : 1; - unsigned int DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN : 1; - unsigned int DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI { - struct { - unsigned int DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__VI { - struct { - unsigned int DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__VI { - struct { - unsigned int DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__VI { - struct { - unsigned int WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int : 8; - unsigned int WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__VI { - struct { - unsigned int DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL : 1; - unsigned int DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_SMU_INTERRUPT_CNTL__VI { - struct { - unsigned int DMCU_SMU_STATIC_SCREEN_INT : 1; - unsigned int : 15; - unsigned int DMCU_SMU_STATIC_SCREEN_STATUS : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_SS_INTERRUPT_CNTL_STATUS__VI { - struct { - unsigned int : 13; - unsigned int STATIC_SCREEN1_INT_STATUS : 1; - unsigned int STATIC_SCREEN1_INT_OCCURRED : 1; - unsigned int STATIC_SCREEN2_INT_STATUS : 1; - unsigned int STATIC_SCREEN2_INT_OCCURRED : 1; - unsigned int STATIC_SCREEN3_INT_STATUS : 1; - unsigned int STATIC_SCREEN3_INT_OCCURRED : 1; - unsigned int STATIC_SCREEN4_INT_STATUS : 1; - unsigned int STATIC_SCREEN4_INT_OCCURRED : 1; - unsigned int STATIC_SCREEN5_INT_STATUS : 1; - unsigned int STATIC_SCREEN5_INT_OCCURRED : 1; - unsigned int STATIC_SCREEN6_INT_STATUS : 1; - unsigned int STATIC_SCREEN6_INT_OCCURRED : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMCU_UC_CLK_GATING_CNTL__VI { - struct { - unsigned int UC_IRAM_RD_DELAY : 3; - unsigned int : 5; - unsigned int UC_ERAM_RD_DELAY : 3; - unsigned int : 5; - unsigned int UC_RBBM_RD_CLK_GATING_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_ADDR_CALC__VI { - struct { - unsigned int : 4; - unsigned int ADDR_CONFIG_PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 21; - unsigned int ADDR_CONFIG_ROW_SIZE : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_ADDR_CONFIG__VI { - struct { - unsigned int NUM_PIPES : 3; - unsigned int : 1; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int BANK_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_SHADER_ENGINES : 2; - unsigned int : 2; - unsigned int SHADER_ENGINE_TILE_SIZE : 3; - unsigned int : 9; - unsigned int ROW_SIZE : 2; - unsigned int NUM_LOWER_PIPES : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_DEBUG02_CORE0__VI { - struct { - unsigned int DB_DATA : 16; - unsigned int MC_RDRET_COUNT_EN : 1; - unsigned int MC_RDRET_COUNTER : 11; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_DEBUG02_CORE1__VI { - struct { - unsigned int DB_DATA : 16; - unsigned int MC_RDRET_COUNT_EN : 1; - unsigned int MC_RDRET_COUNTER : 11; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_P_VMID__VI { - struct { - unsigned int P_VMID_PIPE0 : 4; - unsigned int P_VMID_PIPE1 : 4; - unsigned int P_VMID_PIPE2 : 4; - unsigned int P_VMID_PIPE3 : 4; - unsigned int P_VMID_PIPE4 : 4; - unsigned int P_VMID_PIPE5 : 4; - unsigned int P_VMID_PIPE6 : 4; - unsigned int P_VMID_PIPE7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_STATUS2__VI { - struct { - unsigned int DMIF_PIPE0_DISPCLK_STATUS : 1; - unsigned int DMIF_PIPE1_DISPCLK_STATUS : 1; - unsigned int DMIF_PIPE2_DISPCLK_STATUS : 1; - unsigned int DMIF_PIPE3_DISPCLK_STATUS : 1; - unsigned int DMIF_PIPE4_DISPCLK_STATUS : 1; - unsigned int DMIF_PIPE5_DISPCLK_STATUS : 1; - unsigned int : 2; - unsigned int DMIF_CHUNK_TRACKER_SCLK_STATUS : 1; - unsigned int DMIF_FBC_TRACKER_SCLK_STATUS : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DMIF_URG_OVERRIDE__VI { - struct { - unsigned int DMIF_URG_OVERRIDE_EN : 1; - unsigned int : 3; - unsigned int DMIF_URG_OVERRIDE_LEVEL : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPDBG_CLK_FORCE_CONTROL__VI { - struct { - unsigned int : 4; - unsigned int DPDBG_CLK_FORCE_EN : 1; - unsigned int : 3; - unsigned int DPDBG_CLK_FORCE_SRC : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPDBG_CNTL__VI { - struct { - unsigned int DPDBG_ENABLE : 1; - unsigned int DPDBG_INPUT_ENABLE : 1; - unsigned int : 2; - unsigned int DPDBG_SYMCLK_ON : 1; - unsigned int : 3; - unsigned int DPDBG_ERROR_DETECTION_MODE : 1; - unsigned int : 7; - unsigned int DPDBG_LINE_LENGTH : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPDBG_INTERRUPT__VI { - struct { - unsigned int DPDBG_FIFO_OVERFLOW_INT_MASK : 1; - unsigned int DPDBG_FIFO_OVERFLOW_INT_TYPE : 1; - unsigned int : 6; - unsigned int DPDBG_FIFO_OVERFLOW_INT_ACK : 1; - unsigned int : 7; - unsigned int DPDBG_FIFO_OVERFLOW_OCCURRED : 1; - unsigned int : 7; - unsigned int DPDBG_FIFO_OVERFLOW_INT_STATUS : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_HW_DEBUG_11__VI { - struct { - unsigned int DPG_HW_DEBUG_11 : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_HW_DEBUG_A__VI { - struct { - unsigned int DPG_HW_DEBUG_A : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_HW_DEBUG_B__VI { - struct { - unsigned int DPG_HW_DEBUG_B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_PIPE_ARBITRATION_CONTROL1__VI { - struct { - unsigned int PIXEL_DURATION : 16; - unsigned int BASE_WEIGHT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_PIPE_ARBITRATION_CONTROL2__VI { - struct { - unsigned int TIME_WEIGHT : 16; - unsigned int URGENCY_WEIGHT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_PIPE_DPM_CONTROL__VI { - struct { - unsigned int DPM_ENABLE : 1; - unsigned int : 3; - unsigned int MCLK_CHANGE_ENABLE : 1; - unsigned int : 3; - unsigned int MCLK_CHANGE_FORCE_ON : 1; - unsigned int : 3; - unsigned int MCLK_CHANGE_WATERMARK_MASK : 2; - unsigned int : 2; - unsigned int MCLK_CHANGE_WATERMARK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI { - struct { - unsigned int NB_PSTATE_CHANGE_ENABLE : 1; - unsigned int : 3; - unsigned int NB_PSTATE_CHANGE_URGENT_DURING_REQUEST : 1; - unsigned int : 3; - unsigned int NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST : 1; - unsigned int NB_PSTATE_CHANGE_FORCE_ON : 1; - unsigned int NB_PSTATE_ALLOW_FOR_URGENT : 1; - unsigned int : 5; - unsigned int NB_PSTATE_CHANGE_WATERMARK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_PIPE_STUTTER_CONTROL__VI { - struct { - unsigned int STUTTER_ENABLE : 1; - unsigned int : 3; - unsigned int STUTTER_IGNORE_CURSOR : 1; - unsigned int STUTTER_IGNORE_ICON : 1; - unsigned int STUTTER_IGNORE_VGA : 1; - unsigned int STUTTER_IGNORE_FBC : 1; - unsigned int STUTTER_WM_HIGH_FORCE_ON : 1; - unsigned int STUTTER_WM_HIGH_EXCLUDES_VBLANK : 1; - unsigned int STUTTER_URGENT_IN_NOT_SELF_REFRESH : 1; - unsigned int STUTTER_SELF_REFRESH_FORCE_ON : 1; - unsigned int : 4; - unsigned int STUTTER_EXIT_SELF_REFRESH_WATERMARK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI { - struct { - unsigned int STUTTER_ENABLE_NONLPTCH : 1; - unsigned int : 3; - unsigned int STUTTER_IGNORE_CURSOR_NONLPTCH : 1; - unsigned int STUTTER_IGNORE_ICON_NONLPTCH : 1; - unsigned int STUTTER_IGNORE_VGA_NONLPTCH : 1; - unsigned int STUTTER_IGNORE_FBC_NONLPTCH : 1; - unsigned int STUTTER_WM_HIGH_FORCE_ON_NONLPTCH : 1; - unsigned int STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH : 1; - unsigned int STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH : 1; - unsigned int STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_PIPE_URGENCY_CONTROL__VI { - struct { - unsigned int URGENCY_LOW_WATERMARK : 16; - unsigned int URGENCY_HIGH_WATERMARK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_REPEATER_PROGRAM__VI { - struct { - unsigned int REG_DPG_DMIFRC_REPEATER : 3; - unsigned int : 1; - unsigned int REG_DMIFRC_DPG_REPEATER : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_TEST_DEBUG_DATA__VI { - struct { - unsigned int DPG_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_TEST_DEBUG_INDEX__VI { - struct { - unsigned int DPG_TEST_DEBUG_INDEX : 8; - unsigned int DPG_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPG_WATERMARK_MASK_CONTROL__VI { - struct { - unsigned int STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK : 2; - unsigned int : 6; - unsigned int URGENCY_WATERMARK_MASK : 2; - unsigned int : 6; - unsigned int NB_PSTATE_CHANGE_WATERMARK_MASK : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED0__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED1__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED10__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED11__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED12__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED13__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED14__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED15__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED16__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED17__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED18__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED19__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED2__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED20__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED21__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED22__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED23__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED24__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED25__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED26__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED27__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED28__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED29__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED3__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED30__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED31__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED32__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED33__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED34__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED35__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED36__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED37__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED38__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED39__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED4__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED40__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED41__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED42__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED43__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED44__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED45__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED46__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED47__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED48__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED49__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED5__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED50__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED51__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED52__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED53__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED54__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED55__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED56__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED57__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED58__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED59__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED6__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED60__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED61__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED62__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED63__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED7__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED8__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPHY_MACRO_CNTL_RESERVED9__VI { - struct { - unsigned int DPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_1__VI { - struct { - unsigned int GraphicsPIDController_Ki : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_10__VI { - struct { - unsigned int MemoryPIDController_Ki : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_100__VI { - struct { - unsigned int GraphicsLevel_0_SpllSpreadSpectrum : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_101__VI { - struct { - unsigned int GraphicsLevel_0_SpllSpreadSpectrum2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_102__VI { - struct { - unsigned int GraphicsLevel_0_CcPwrDynRm : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_103__VI { - struct { - unsigned int GraphicsLevel_0_CcPwrDynRm1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_104__VI { - struct { - unsigned int GraphicsLevel_0_EnabledForThrottle : 8; - unsigned int GraphicsLevel_0_EnabledForActivity : 8; - unsigned int GraphicsLevel_0_DisplayWatermark : 8; - unsigned int GraphicsLevel_0_SclkDid : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_105__VI { - struct { - unsigned int GraphicsLevel_0_PowerThrottle : 8; - unsigned int GraphicsLevel_0_VoltageDownHyst : 8; - unsigned int GraphicsLevel_0_DownHyst : 8; - unsigned int GraphicsLevel_0_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_106__VI { - struct { - unsigned int GraphicsLevel_1_MinVoltage_Phases : 8; - unsigned int GraphicsLevel_1_MinVoltage_VddGfx : 8; - unsigned int GraphicsLevel_1_MinVoltage_Vddci : 8; - unsigned int GraphicsLevel_1_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_107__VI { - struct { - unsigned int GraphicsLevel_1_SclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_108__VI { - struct { - unsigned int GraphicsLevel_1_ActivityLevel : 16; - unsigned int GraphicsLevel_1_DeepSleepDivId : 8; - unsigned int GraphicsLevel_1_pcieDpmLevel : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_109__VI { - struct { - unsigned int GraphicsLevel_1_CgSpllFuncCntl3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_11__VI { - struct { - unsigned int MemoryPIDController_LFWindupUpperLim : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_110__VI { - struct { - unsigned int GraphicsLevel_1_CgSpllFuncCntl4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_111__VI { - struct { - unsigned int GraphicsLevel_1_SpllSpreadSpectrum : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_112__VI { - struct { - unsigned int GraphicsLevel_1_SpllSpreadSpectrum2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_113__VI { - struct { - unsigned int GraphicsLevel_1_CcPwrDynRm : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_114__VI { - struct { - unsigned int GraphicsLevel_1_CcPwrDynRm1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_115__VI { - struct { - unsigned int GraphicsLevel_1_EnabledForThrottle : 8; - unsigned int GraphicsLevel_1_EnabledForActivity : 8; - unsigned int GraphicsLevel_1_DisplayWatermark : 8; - unsigned int GraphicsLevel_1_SclkDid : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_116__VI { - struct { - unsigned int GraphicsLevel_1_PowerThrottle : 8; - unsigned int GraphicsLevel_1_VoltageDownHyst : 8; - unsigned int GraphicsLevel_1_DownHyst : 8; - unsigned int GraphicsLevel_1_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_117__VI { - struct { - unsigned int GraphicsLevel_2_MinVoltage_Phases : 8; - unsigned int GraphicsLevel_2_MinVoltage_VddGfx : 8; - unsigned int GraphicsLevel_2_MinVoltage_Vddci : 8; - unsigned int GraphicsLevel_2_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_118__VI { - struct { - unsigned int GraphicsLevel_2_SclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_119__VI { - struct { - unsigned int GraphicsLevel_2_ActivityLevel : 16; - unsigned int GraphicsLevel_2_DeepSleepDivId : 8; - unsigned int GraphicsLevel_2_pcieDpmLevel : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_12__VI { - struct { - unsigned int MemoryPIDController_LFWindupLowerLim : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_120__VI { - struct { - unsigned int GraphicsLevel_2_CgSpllFuncCntl3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_121__VI { - struct { - unsigned int GraphicsLevel_2_CgSpllFuncCntl4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_122__VI { - struct { - unsigned int GraphicsLevel_2_SpllSpreadSpectrum : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_123__VI { - struct { - unsigned int GraphicsLevel_2_SpllSpreadSpectrum2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_124__VI { - struct { - unsigned int GraphicsLevel_2_CcPwrDynRm : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_125__VI { - struct { - unsigned int GraphicsLevel_2_CcPwrDynRm1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_126__VI { - struct { - unsigned int GraphicsLevel_2_EnabledForThrottle : 8; - unsigned int GraphicsLevel_2_EnabledForActivity : 8; - unsigned int GraphicsLevel_2_DisplayWatermark : 8; - unsigned int GraphicsLevel_2_SclkDid : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_127__VI { - struct { - unsigned int GraphicsLevel_2_PowerThrottle : 8; - unsigned int GraphicsLevel_2_VoltageDownHyst : 8; - unsigned int GraphicsLevel_2_DownHyst : 8; - unsigned int GraphicsLevel_2_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_128__VI { - struct { - unsigned int GraphicsLevel_3_MinVoltage_Phases : 8; - unsigned int GraphicsLevel_3_MinVoltage_VddGfx : 8; - unsigned int GraphicsLevel_3_MinVoltage_Vddci : 8; - unsigned int GraphicsLevel_3_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_129__VI { - struct { - unsigned int GraphicsLevel_3_SclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_13__VI { - struct { - unsigned int MemoryPIDController_StatePrecision : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_130__VI { - struct { - unsigned int GraphicsLevel_3_ActivityLevel : 16; - unsigned int GraphicsLevel_3_DeepSleepDivId : 8; - unsigned int GraphicsLevel_3_pcieDpmLevel : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_131__VI { - struct { - unsigned int GraphicsLevel_3_CgSpllFuncCntl3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_132__VI { - struct { - unsigned int GraphicsLevel_3_CgSpllFuncCntl4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_133__VI { - struct { - unsigned int GraphicsLevel_3_SpllSpreadSpectrum : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_134__VI { - struct { - unsigned int GraphicsLevel_3_SpllSpreadSpectrum2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_135__VI { - struct { - unsigned int GraphicsLevel_3_CcPwrDynRm : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_136__VI { - struct { - unsigned int GraphicsLevel_3_CcPwrDynRm1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_137__VI { - struct { - unsigned int GraphicsLevel_3_EnabledForThrottle : 8; - unsigned int GraphicsLevel_3_EnabledForActivity : 8; - unsigned int GraphicsLevel_3_DisplayWatermark : 8; - unsigned int GraphicsLevel_3_SclkDid : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_138__VI { - struct { - unsigned int GraphicsLevel_3_PowerThrottle : 8; - unsigned int GraphicsLevel_3_VoltageDownHyst : 8; - unsigned int GraphicsLevel_3_DownHyst : 8; - unsigned int GraphicsLevel_3_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_139__VI { - struct { - unsigned int GraphicsLevel_4_MinVoltage_Phases : 8; - unsigned int GraphicsLevel_4_MinVoltage_VddGfx : 8; - unsigned int GraphicsLevel_4_MinVoltage_Vddci : 8; - unsigned int GraphicsLevel_4_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_14__VI { - struct { - unsigned int MemoryPIDController_LfPrecision : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_140__VI { - struct { - unsigned int GraphicsLevel_4_SclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_141__VI { - struct { - unsigned int GraphicsLevel_4_ActivityLevel : 16; - unsigned int GraphicsLevel_4_DeepSleepDivId : 8; - unsigned int GraphicsLevel_4_pcieDpmLevel : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_142__VI { - struct { - unsigned int GraphicsLevel_4_CgSpllFuncCntl3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_143__VI { - struct { - unsigned int GraphicsLevel_4_CgSpllFuncCntl4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_144__VI { - struct { - unsigned int GraphicsLevel_4_SpllSpreadSpectrum : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_145__VI { - struct { - unsigned int GraphicsLevel_4_SpllSpreadSpectrum2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_146__VI { - struct { - unsigned int GraphicsLevel_4_CcPwrDynRm : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_147__VI { - struct { - unsigned int GraphicsLevel_4_CcPwrDynRm1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_148__VI { - struct { - unsigned int GraphicsLevel_4_EnabledForThrottle : 8; - unsigned int GraphicsLevel_4_EnabledForActivity : 8; - unsigned int GraphicsLevel_4_DisplayWatermark : 8; - unsigned int GraphicsLevel_4_SclkDid : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_149__VI { - struct { - unsigned int GraphicsLevel_4_PowerThrottle : 8; - unsigned int GraphicsLevel_4_VoltageDownHyst : 8; - unsigned int GraphicsLevel_4_DownHyst : 8; - unsigned int GraphicsLevel_4_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_15__VI { - struct { - unsigned int MemoryPIDController_LfOffset : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_150__VI { - struct { - unsigned int GraphicsLevel_5_MinVoltage_Phases : 8; - unsigned int GraphicsLevel_5_MinVoltage_VddGfx : 8; - unsigned int GraphicsLevel_5_MinVoltage_Vddci : 8; - unsigned int GraphicsLevel_5_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_151__VI { - struct { - unsigned int GraphicsLevel_5_SclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_152__VI { - struct { - unsigned int GraphicsLevel_5_ActivityLevel : 16; - unsigned int GraphicsLevel_5_DeepSleepDivId : 8; - unsigned int GraphicsLevel_5_pcieDpmLevel : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_153__VI { - struct { - unsigned int GraphicsLevel_5_CgSpllFuncCntl3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_154__VI { - struct { - unsigned int GraphicsLevel_5_CgSpllFuncCntl4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_155__VI { - struct { - unsigned int GraphicsLevel_5_SpllSpreadSpectrum : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_156__VI { - struct { - unsigned int GraphicsLevel_5_SpllSpreadSpectrum2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_157__VI { - struct { - unsigned int GraphicsLevel_5_CcPwrDynRm : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_158__VI { - struct { - unsigned int GraphicsLevel_5_CcPwrDynRm1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_159__VI { - struct { - unsigned int GraphicsLevel_5_EnabledForThrottle : 8; - unsigned int GraphicsLevel_5_EnabledForActivity : 8; - unsigned int GraphicsLevel_5_DisplayWatermark : 8; - unsigned int GraphicsLevel_5_SclkDid : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_16__VI { - struct { - unsigned int MemoryPIDController_MaxState : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_160__VI { - struct { - unsigned int GraphicsLevel_5_PowerThrottle : 8; - unsigned int GraphicsLevel_5_VoltageDownHyst : 8; - unsigned int GraphicsLevel_5_DownHyst : 8; - unsigned int GraphicsLevel_5_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_161__VI { - struct { - unsigned int GraphicsLevel_6_MinVoltage_Phases : 8; - unsigned int GraphicsLevel_6_MinVoltage_VddGfx : 8; - unsigned int GraphicsLevel_6_MinVoltage_Vddci : 8; - unsigned int GraphicsLevel_6_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_162__VI { - struct { - unsigned int GraphicsLevel_6_SclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_163__VI { - struct { - unsigned int GraphicsLevel_6_ActivityLevel : 16; - unsigned int GraphicsLevel_6_DeepSleepDivId : 8; - unsigned int GraphicsLevel_6_pcieDpmLevel : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_164__VI { - struct { - unsigned int GraphicsLevel_6_CgSpllFuncCntl3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_165__VI { - struct { - unsigned int GraphicsLevel_6_CgSpllFuncCntl4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_166__VI { - struct { - unsigned int GraphicsLevel_6_SpllSpreadSpectrum : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_167__VI { - struct { - unsigned int GraphicsLevel_6_SpllSpreadSpectrum2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_168__VI { - struct { - unsigned int GraphicsLevel_6_CcPwrDynRm : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_169__VI { - struct { - unsigned int GraphicsLevel_6_CcPwrDynRm1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_17__VI { - struct { - unsigned int MemoryPIDController_MaxLfFraction : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_170__VI { - struct { - unsigned int GraphicsLevel_6_EnabledForThrottle : 8; - unsigned int GraphicsLevel_6_EnabledForActivity : 8; - unsigned int GraphicsLevel_6_DisplayWatermark : 8; - unsigned int GraphicsLevel_6_SclkDid : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_171__VI { - struct { - unsigned int GraphicsLevel_6_PowerThrottle : 8; - unsigned int GraphicsLevel_6_VoltageDownHyst : 8; - unsigned int GraphicsLevel_6_DownHyst : 8; - unsigned int GraphicsLevel_6_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_172__VI { - struct { - unsigned int GraphicsLevel_7_MinVoltage_Phases : 8; - unsigned int GraphicsLevel_7_MinVoltage_VddGfx : 8; - unsigned int GraphicsLevel_7_MinVoltage_Vddci : 8; - unsigned int GraphicsLevel_7_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_173__VI { - struct { - unsigned int GraphicsLevel_7_SclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_174__VI { - struct { - unsigned int GraphicsLevel_7_ActivityLevel : 16; - unsigned int GraphicsLevel_7_DeepSleepDivId : 8; - unsigned int GraphicsLevel_7_pcieDpmLevel : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_175__VI { - struct { - unsigned int GraphicsLevel_7_CgSpllFuncCntl3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_176__VI { - struct { - unsigned int GraphicsLevel_7_CgSpllFuncCntl4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_177__VI { - struct { - unsigned int GraphicsLevel_7_SpllSpreadSpectrum : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_178__VI { - struct { - unsigned int GraphicsLevel_7_SpllSpreadSpectrum2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_179__VI { - struct { - unsigned int GraphicsLevel_7_CcPwrDynRm : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_18__VI { - struct { - unsigned int MemoryPIDController_StateShift : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_180__VI { - struct { - unsigned int GraphicsLevel_7_CcPwrDynRm1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_181__VI { - struct { - unsigned int GraphicsLevel_7_EnabledForThrottle : 8; - unsigned int GraphicsLevel_7_EnabledForActivity : 8; - unsigned int GraphicsLevel_7_DisplayWatermark : 8; - unsigned int GraphicsLevel_7_SclkDid : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_182__VI { - struct { - unsigned int GraphicsLevel_7_PowerThrottle : 8; - unsigned int GraphicsLevel_7_VoltageDownHyst : 8; - unsigned int GraphicsLevel_7_DownHyst : 8; - unsigned int GraphicsLevel_7_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_183__VI { - struct { - unsigned int MemoryACPILevel_MinVoltage_Phases : 8; - unsigned int MemoryACPILevel_MinVoltage_VddGfx : 8; - unsigned int MemoryACPILevel_MinVoltage_Vddci : 8; - unsigned int MemoryACPILevel_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_184__VI { - struct { - unsigned int MemoryACPILevel_MinMvdd : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_185__VI { - struct { - unsigned int MemoryACPILevel_MclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_186__VI { - struct { - unsigned int MemoryACPILevel_EnabledForActivity : 8; - unsigned int MemoryACPILevel_EnabledForThrottle : 8; - unsigned int MemoryACPILevel_FreqRange : 8; - unsigned int MemoryACPILevel_StutterEnable : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_187__VI { - struct { - unsigned int MemoryACPILevel_padding : 8; - unsigned int MemoryACPILevel_VoltageDownHyst : 8; - unsigned int MemoryACPILevel_DownHyst : 8; - unsigned int MemoryACPILevel_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_188__VI { - struct { - unsigned int MemoryACPILevel_MclkDivider : 8; - unsigned int MemoryACPILevel_DisplayWatermark : 8; - unsigned int MemoryACPILevel_ActivityLevel : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_189__VI { - struct { - unsigned int MemoryLevel_0_MinVoltage_Phases : 8; - unsigned int MemoryLevel_0_MinVoltage_VddGfx : 8; - unsigned int MemoryLevel_0_MinVoltage_Vddci : 8; - unsigned int MemoryLevel_0_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_19__VI { - struct { - unsigned int LinkPIDController_Ki : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_190__VI { - struct { - unsigned int MemoryLevel_0_MinMvdd : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_191__VI { - struct { - unsigned int MemoryLevel_0_MclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_192__VI { - struct { - unsigned int MemoryLevel_0_EnabledForActivity : 8; - unsigned int MemoryLevel_0_EnabledForThrottle : 8; - unsigned int MemoryLevel_0_FreqRange : 8; - unsigned int MemoryLevel_0_StutterEnable : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_193__VI { - struct { - unsigned int MemoryLevel_0_padding : 8; - unsigned int MemoryLevel_0_VoltageDownHyst : 8; - unsigned int MemoryLevel_0_DownHyst : 8; - unsigned int MemoryLevel_0_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_194__VI { - struct { - unsigned int MemoryLevel_0_MclkDivider : 8; - unsigned int MemoryLevel_0_DisplayWatermark : 8; - unsigned int MemoryLevel_0_ActivityLevel : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_195__VI { - struct { - unsigned int MemoryLevel_1_MinVoltage_Phases : 8; - unsigned int MemoryLevel_1_MinVoltage_VddGfx : 8; - unsigned int MemoryLevel_1_MinVoltage_Vddci : 8; - unsigned int MemoryLevel_1_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_196__VI { - struct { - unsigned int MemoryLevel_1_MinMvdd : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_197__VI { - struct { - unsigned int MemoryLevel_1_MclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_198__VI { - struct { - unsigned int MemoryLevel_1_EnabledForActivity : 8; - unsigned int MemoryLevel_1_EnabledForThrottle : 8; - unsigned int MemoryLevel_1_FreqRange : 8; - unsigned int MemoryLevel_1_StutterEnable : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_199__VI { - struct { - unsigned int MemoryLevel_1_padding : 8; - unsigned int MemoryLevel_1_VoltageDownHyst : 8; - unsigned int MemoryLevel_1_DownHyst : 8; - unsigned int MemoryLevel_1_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_2__VI { - struct { - unsigned int GraphicsPIDController_LFWindupUpperLim : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_20__VI { - struct { - unsigned int LinkPIDController_LFWindupUpperLim : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_200__VI { - struct { - unsigned int MemoryLevel_1_MclkDivider : 8; - unsigned int MemoryLevel_1_DisplayWatermark : 8; - unsigned int MemoryLevel_1_ActivityLevel : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_201__VI { - struct { - unsigned int MemoryLevel_2_MinVoltage_Phases : 8; - unsigned int MemoryLevel_2_MinVoltage_VddGfx : 8; - unsigned int MemoryLevel_2_MinVoltage_Vddci : 8; - unsigned int MemoryLevel_2_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_202__VI { - struct { - unsigned int MemoryLevel_2_MinMvdd : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_203__VI { - struct { - unsigned int MemoryLevel_2_MclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_204__VI { - struct { - unsigned int MemoryLevel_2_EnabledForActivity : 8; - unsigned int MemoryLevel_2_EnabledForThrottle : 8; - unsigned int MemoryLevel_2_FreqRange : 8; - unsigned int MemoryLevel_2_StutterEnable : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_205__VI { - struct { - unsigned int MemoryLevel_2_padding : 8; - unsigned int MemoryLevel_2_VoltageDownHyst : 8; - unsigned int MemoryLevel_2_DownHyst : 8; - unsigned int MemoryLevel_2_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_206__VI { - struct { - unsigned int MemoryLevel_2_MclkDivider : 8; - unsigned int MemoryLevel_2_DisplayWatermark : 8; - unsigned int MemoryLevel_2_ActivityLevel : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_207__VI { - struct { - unsigned int MemoryLevel_3_MinVoltage_Phases : 8; - unsigned int MemoryLevel_3_MinVoltage_VddGfx : 8; - unsigned int MemoryLevel_3_MinVoltage_Vddci : 8; - unsigned int MemoryLevel_3_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_208__VI { - struct { - unsigned int MemoryLevel_3_MinMvdd : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_209__VI { - struct { - unsigned int MemoryLevel_3_MclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_21__VI { - struct { - unsigned int LinkPIDController_LFWindupLowerLim : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_210__VI { - struct { - unsigned int MemoryLevel_3_EnabledForActivity : 8; - unsigned int MemoryLevel_3_EnabledForThrottle : 8; - unsigned int MemoryLevel_3_FreqRange : 8; - unsigned int MemoryLevel_3_StutterEnable : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_211__VI { - struct { - unsigned int MemoryLevel_3_padding : 8; - unsigned int MemoryLevel_3_VoltageDownHyst : 8; - unsigned int MemoryLevel_3_DownHyst : 8; - unsigned int MemoryLevel_3_UpHyst : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_212__VI { - struct { - unsigned int MemoryLevel_3_MclkDivider : 8; - unsigned int MemoryLevel_3_DisplayWatermark : 8; - unsigned int MemoryLevel_3_ActivityLevel : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_213__VI { - struct { - unsigned int LinkLevel_0_SPC : 8; - unsigned int LinkLevel_0_EnabledForActivity : 8; - unsigned int LinkLevel_0_PcieLaneCount : 8; - unsigned int LinkLevel_0_PcieGenSpeed : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_214__VI { - struct { - unsigned int LinkLevel_0_DownThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_215__VI { - struct { - unsigned int LinkLevel_0_UpThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_216__VI { - struct { - unsigned int LinkLevel_0_Reserved : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_217__VI { - struct { - unsigned int LinkLevel_1_SPC : 8; - unsigned int LinkLevel_1_EnabledForActivity : 8; - unsigned int LinkLevel_1_PcieLaneCount : 8; - unsigned int LinkLevel_1_PcieGenSpeed : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_218__VI { - struct { - unsigned int LinkLevel_1_DownThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_219__VI { - struct { - unsigned int LinkLevel_1_UpThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_22__VI { - struct { - unsigned int LinkPIDController_StatePrecision : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_220__VI { - struct { - unsigned int LinkLevel_1_Reserved : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_221__VI { - struct { - unsigned int LinkLevel_2_SPC : 8; - unsigned int LinkLevel_2_EnabledForActivity : 8; - unsigned int LinkLevel_2_PcieLaneCount : 8; - unsigned int LinkLevel_2_PcieGenSpeed : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_222__VI { - struct { - unsigned int LinkLevel_2_DownThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_223__VI { - struct { - unsigned int LinkLevel_2_UpThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_224__VI { - struct { - unsigned int LinkLevel_2_Reserved : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_225__VI { - struct { - unsigned int LinkLevel_3_SPC : 8; - unsigned int LinkLevel_3_EnabledForActivity : 8; - unsigned int LinkLevel_3_PcieLaneCount : 8; - unsigned int LinkLevel_3_PcieGenSpeed : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_226__VI { - struct { - unsigned int LinkLevel_3_DownThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_227__VI { - struct { - unsigned int LinkLevel_3_UpThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_228__VI { - struct { - unsigned int LinkLevel_3_Reserved : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_229__VI { - struct { - unsigned int LinkLevel_4_SPC : 8; - unsigned int LinkLevel_4_EnabledForActivity : 8; - unsigned int LinkLevel_4_PcieLaneCount : 8; - unsigned int LinkLevel_4_PcieGenSpeed : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_23__VI { - struct { - unsigned int LinkPIDController_LfPrecision : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_230__VI { - struct { - unsigned int LinkLevel_4_DownThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_231__VI { - struct { - unsigned int LinkLevel_4_UpThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_232__VI { - struct { - unsigned int LinkLevel_4_Reserved : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_233__VI { - struct { - unsigned int LinkLevel_5_SPC : 8; - unsigned int LinkLevel_5_EnabledForActivity : 8; - unsigned int LinkLevel_5_PcieLaneCount : 8; - unsigned int LinkLevel_5_PcieGenSpeed : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_234__VI { - struct { - unsigned int LinkLevel_5_DownThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_235__VI { - struct { - unsigned int LinkLevel_5_UpThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_236__VI { - struct { - unsigned int LinkLevel_5_Reserved : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_237__VI { - struct { - unsigned int LinkLevel_6_SPC : 8; - unsigned int LinkLevel_6_EnabledForActivity : 8; - unsigned int LinkLevel_6_PcieLaneCount : 8; - unsigned int LinkLevel_6_PcieGenSpeed : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_238__VI { - struct { - unsigned int LinkLevel_6_DownThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_239__VI { - struct { - unsigned int LinkLevel_6_UpThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_24__VI { - struct { - unsigned int LinkPIDController_LfOffset : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_240__VI { - struct { - unsigned int LinkLevel_6_Reserved : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_241__VI { - struct { - unsigned int LinkLevel_7_SPC : 8; - unsigned int LinkLevel_7_EnabledForActivity : 8; - unsigned int LinkLevel_7_PcieLaneCount : 8; - unsigned int LinkLevel_7_PcieGenSpeed : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_242__VI { - struct { - unsigned int LinkLevel_7_DownThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_243__VI { - struct { - unsigned int LinkLevel_7_UpThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_244__VI { - struct { - unsigned int LinkLevel_7_Reserved : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_245__VI { - struct { - unsigned int ACPILevel_Flags : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_246__VI { - struct { - unsigned int ACPILevel_MinVoltage_Phases : 8; - unsigned int ACPILevel_MinVoltage_VddGfx : 8; - unsigned int ACPILevel_MinVoltage_Vddci : 8; - unsigned int ACPILevel_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_247__VI { - struct { - unsigned int ACPILevel_SclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_248__VI { - struct { - unsigned int ACPILevel_padding : 8; - unsigned int ACPILevel_DeepSleepDivId : 8; - unsigned int ACPILevel_DisplayWatermark : 8; - unsigned int ACPILevel_SclkDid : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_249__VI { - struct { - unsigned int ACPILevel_CgSpllFuncCntl : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_25__VI { - struct { - unsigned int LinkPIDController_MaxState : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_250__VI { - struct { - unsigned int ACPILevel_CgSpllFuncCntl2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_251__VI { - struct { - unsigned int ACPILevel_CgSpllFuncCntl3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_252__VI { - struct { - unsigned int ACPILevel_CgSpllFuncCntl4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_253__VI { - struct { - unsigned int ACPILevel_SpllSpreadSpectrum : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_254__VI { - struct { - unsigned int ACPILevel_SpllSpreadSpectrum2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_255__VI { - struct { - unsigned int ACPILevel_CcPwrDynRm : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_256__VI { - struct { - unsigned int ACPILevel_CcPwrDynRm1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_257__VI { - struct { - unsigned int UvdLevel_0_VclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_258__VI { - struct { - unsigned int UvdLevel_0_DclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_259__VI { - struct { - unsigned int UvdLevel_0_MinVoltage_Phases : 8; - unsigned int UvdLevel_0_MinVoltage_VddGfx : 8; - unsigned int UvdLevel_0_MinVoltage_Vddci : 8; - unsigned int UvdLevel_0_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_26__VI { - struct { - unsigned int LinkPIDController_MaxLfFraction : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_260__VI { - struct { - unsigned int UvdLevel_0_padding_1 : 8; - unsigned int UvdLevel_0_padding_0 : 8; - unsigned int UvdLevel_0_DclkDivider : 8; - unsigned int UvdLevel_0_VclkDivider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_261__VI { - struct { - unsigned int UvdLevel_1_VclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_262__VI { - struct { - unsigned int UvdLevel_1_DclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_263__VI { - struct { - unsigned int UvdLevel_1_MinVoltage_Phases : 8; - unsigned int UvdLevel_1_MinVoltage_VddGfx : 8; - unsigned int UvdLevel_1_MinVoltage_Vddci : 8; - unsigned int UvdLevel_1_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_264__VI { - struct { - unsigned int UvdLevel_1_padding_1 : 8; - unsigned int UvdLevel_1_padding_0 : 8; - unsigned int UvdLevel_1_DclkDivider : 8; - unsigned int UvdLevel_1_VclkDivider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_265__VI { - struct { - unsigned int UvdLevel_2_VclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_266__VI { - struct { - unsigned int UvdLevel_2_DclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_267__VI { - struct { - unsigned int UvdLevel_2_MinVoltage_Phases : 8; - unsigned int UvdLevel_2_MinVoltage_VddGfx : 8; - unsigned int UvdLevel_2_MinVoltage_Vddci : 8; - unsigned int UvdLevel_2_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_268__VI { - struct { - unsigned int UvdLevel_2_padding_1 : 8; - unsigned int UvdLevel_2_padding_0 : 8; - unsigned int UvdLevel_2_DclkDivider : 8; - unsigned int UvdLevel_2_VclkDivider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_269__VI { - struct { - unsigned int UvdLevel_3_VclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_27__VI { - struct { - unsigned int LinkPIDController_StateShift : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_270__VI { - struct { - unsigned int UvdLevel_3_DclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_271__VI { - struct { - unsigned int UvdLevel_3_MinVoltage_Phases : 8; - unsigned int UvdLevel_3_MinVoltage_VddGfx : 8; - unsigned int UvdLevel_3_MinVoltage_Vddci : 8; - unsigned int UvdLevel_3_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_272__VI { - struct { - unsigned int UvdLevel_3_padding_1 : 8; - unsigned int UvdLevel_3_padding_0 : 8; - unsigned int UvdLevel_3_DclkDivider : 8; - unsigned int UvdLevel_3_VclkDivider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_273__VI { - struct { - unsigned int UvdLevel_4_VclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_274__VI { - struct { - unsigned int UvdLevel_4_DclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_275__VI { - struct { - unsigned int UvdLevel_4_MinVoltage_Phases : 8; - unsigned int UvdLevel_4_MinVoltage_VddGfx : 8; - unsigned int UvdLevel_4_MinVoltage_Vddci : 8; - unsigned int UvdLevel_4_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_276__VI { - struct { - unsigned int UvdLevel_4_padding_1 : 8; - unsigned int UvdLevel_4_padding_0 : 8; - unsigned int UvdLevel_4_DclkDivider : 8; - unsigned int UvdLevel_4_VclkDivider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_277__VI { - struct { - unsigned int UvdLevel_5_VclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_278__VI { - struct { - unsigned int UvdLevel_5_DclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_279__VI { - struct { - unsigned int UvdLevel_5_MinVoltage_Phases : 8; - unsigned int UvdLevel_5_MinVoltage_VddGfx : 8; - unsigned int UvdLevel_5_MinVoltage_Vddci : 8; - unsigned int UvdLevel_5_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_28__VI { - struct { - unsigned int SystemFlags : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_280__VI { - struct { - unsigned int UvdLevel_5_padding_1 : 8; - unsigned int UvdLevel_5_padding_0 : 8; - unsigned int UvdLevel_5_DclkDivider : 8; - unsigned int UvdLevel_5_VclkDivider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_281__VI { - struct { - unsigned int UvdLevel_6_VclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_282__VI { - struct { - unsigned int UvdLevel_6_DclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_283__VI { - struct { - unsigned int UvdLevel_6_MinVoltage_Phases : 8; - unsigned int UvdLevel_6_MinVoltage_VddGfx : 8; - unsigned int UvdLevel_6_MinVoltage_Vddci : 8; - unsigned int UvdLevel_6_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_284__VI { - struct { - unsigned int UvdLevel_6_padding_1 : 8; - unsigned int UvdLevel_6_padding_0 : 8; - unsigned int UvdLevel_6_DclkDivider : 8; - unsigned int UvdLevel_6_VclkDivider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_285__VI { - struct { - unsigned int UvdLevel_7_VclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_286__VI { - struct { - unsigned int UvdLevel_7_DclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_287__VI { - struct { - unsigned int UvdLevel_7_MinVoltage_Phases : 8; - unsigned int UvdLevel_7_MinVoltage_VddGfx : 8; - unsigned int UvdLevel_7_MinVoltage_Vddci : 8; - unsigned int UvdLevel_7_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_288__VI { - struct { - unsigned int UvdLevel_7_padding_1 : 8; - unsigned int UvdLevel_7_padding_0 : 8; - unsigned int UvdLevel_7_DclkDivider : 8; - unsigned int UvdLevel_7_VclkDivider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_289__VI { - struct { - unsigned int VceLevel_0_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_29__VI { - struct { - unsigned int VRConfig : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_290__VI { - struct { - unsigned int VceLevel_0_MinVoltage_Phases : 8; - unsigned int VceLevel_0_MinVoltage_VddGfx : 8; - unsigned int VceLevel_0_MinVoltage_Vddci : 8; - unsigned int VceLevel_0_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_291__VI { - struct { - unsigned int VceLevel_0_padding_2 : 8; - unsigned int VceLevel_0_padding_1 : 8; - unsigned int VceLevel_0_padding_0 : 8; - unsigned int VceLevel_0_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_292__VI { - struct { - unsigned int VceLevel_1_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_293__VI { - struct { - unsigned int VceLevel_1_MinVoltage_Phases : 8; - unsigned int VceLevel_1_MinVoltage_VddGfx : 8; - unsigned int VceLevel_1_MinVoltage_Vddci : 8; - unsigned int VceLevel_1_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_294__VI { - struct { - unsigned int VceLevel_1_padding_2 : 8; - unsigned int VceLevel_1_padding_1 : 8; - unsigned int VceLevel_1_padding_0 : 8; - unsigned int VceLevel_1_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_295__VI { - struct { - unsigned int VceLevel_2_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_296__VI { - struct { - unsigned int VceLevel_2_MinVoltage_Phases : 8; - unsigned int VceLevel_2_MinVoltage_VddGfx : 8; - unsigned int VceLevel_2_MinVoltage_Vddci : 8; - unsigned int VceLevel_2_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_297__VI { - struct { - unsigned int VceLevel_2_padding_2 : 8; - unsigned int VceLevel_2_padding_1 : 8; - unsigned int VceLevel_2_padding_0 : 8; - unsigned int VceLevel_2_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_298__VI { - struct { - unsigned int VceLevel_3_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_299__VI { - struct { - unsigned int VceLevel_3_MinVoltage_Phases : 8; - unsigned int VceLevel_3_MinVoltage_VddGfx : 8; - unsigned int VceLevel_3_MinVoltage_Vddci : 8; - unsigned int VceLevel_3_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_3__VI { - struct { - unsigned int GraphicsPIDController_LFWindupLowerLim : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_30__VI { - struct { - unsigned int SmioMask1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_300__VI { - struct { - unsigned int VceLevel_3_padding_2 : 8; - unsigned int VceLevel_3_padding_1 : 8; - unsigned int VceLevel_3_padding_0 : 8; - unsigned int VceLevel_3_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_301__VI { - struct { - unsigned int VceLevel_4_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_302__VI { - struct { - unsigned int VceLevel_4_MinVoltage_Phases : 8; - unsigned int VceLevel_4_MinVoltage_VddGfx : 8; - unsigned int VceLevel_4_MinVoltage_Vddci : 8; - unsigned int VceLevel_4_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_303__VI { - struct { - unsigned int VceLevel_4_padding_2 : 8; - unsigned int VceLevel_4_padding_1 : 8; - unsigned int VceLevel_4_padding_0 : 8; - unsigned int VceLevel_4_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_304__VI { - struct { - unsigned int VceLevel_5_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_305__VI { - struct { - unsigned int VceLevel_5_MinVoltage_Phases : 8; - unsigned int VceLevel_5_MinVoltage_VddGfx : 8; - unsigned int VceLevel_5_MinVoltage_Vddci : 8; - unsigned int VceLevel_5_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_306__VI { - struct { - unsigned int VceLevel_5_padding_2 : 8; - unsigned int VceLevel_5_padding_1 : 8; - unsigned int VceLevel_5_padding_0 : 8; - unsigned int VceLevel_5_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_307__VI { - struct { - unsigned int VceLevel_6_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_308__VI { - struct { - unsigned int VceLevel_6_MinVoltage_Phases : 8; - unsigned int VceLevel_6_MinVoltage_VddGfx : 8; - unsigned int VceLevel_6_MinVoltage_Vddci : 8; - unsigned int VceLevel_6_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_309__VI { - struct { - unsigned int VceLevel_6_padding_2 : 8; - unsigned int VceLevel_6_padding_1 : 8; - unsigned int VceLevel_6_padding_0 : 8; - unsigned int VceLevel_6_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_31__VI { - struct { - unsigned int SmioMask2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_310__VI { - struct { - unsigned int VceLevel_7_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_311__VI { - struct { - unsigned int VceLevel_7_MinVoltage_Phases : 8; - unsigned int VceLevel_7_MinVoltage_VddGfx : 8; - unsigned int VceLevel_7_MinVoltage_Vddci : 8; - unsigned int VceLevel_7_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_312__VI { - struct { - unsigned int VceLevel_7_padding_2 : 8; - unsigned int VceLevel_7_padding_1 : 8; - unsigned int VceLevel_7_padding_0 : 8; - unsigned int VceLevel_7_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_313__VI { - struct { - unsigned int AcpLevel_0_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_314__VI { - struct { - unsigned int AcpLevel_0_MinVoltage_Phases : 8; - unsigned int AcpLevel_0_MinVoltage_VddGfx : 8; - unsigned int AcpLevel_0_MinVoltage_Vddci : 8; - unsigned int AcpLevel_0_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_315__VI { - struct { - unsigned int AcpLevel_0_padding_2 : 8; - unsigned int AcpLevel_0_padding_1 : 8; - unsigned int AcpLevel_0_padding_0 : 8; - unsigned int AcpLevel_0_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_316__VI { - struct { - unsigned int AcpLevel_1_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_317__VI { - struct { - unsigned int AcpLevel_1_MinVoltage_Phases : 8; - unsigned int AcpLevel_1_MinVoltage_VddGfx : 8; - unsigned int AcpLevel_1_MinVoltage_Vddci : 8; - unsigned int AcpLevel_1_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_318__VI { - struct { - unsigned int AcpLevel_1_padding_2 : 8; - unsigned int AcpLevel_1_padding_1 : 8; - unsigned int AcpLevel_1_padding_0 : 8; - unsigned int AcpLevel_1_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_319__VI { - struct { - unsigned int AcpLevel_2_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_32__VI { - struct { - unsigned int SmioTable1_Pattern_0_padding : 8; - unsigned int SmioTable1_Pattern_0_Smio : 8; - unsigned int SmioTable1_Pattern_0_Voltage : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_320__VI { - struct { - unsigned int AcpLevel_2_MinVoltage_Phases : 8; - unsigned int AcpLevel_2_MinVoltage_VddGfx : 8; - unsigned int AcpLevel_2_MinVoltage_Vddci : 8; - unsigned int AcpLevel_2_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_321__VI { - struct { - unsigned int AcpLevel_2_padding_2 : 8; - unsigned int AcpLevel_2_padding_1 : 8; - unsigned int AcpLevel_2_padding_0 : 8; - unsigned int AcpLevel_2_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_322__VI { - struct { - unsigned int AcpLevel_3_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_323__VI { - struct { - unsigned int AcpLevel_3_MinVoltage_Phases : 8; - unsigned int AcpLevel_3_MinVoltage_VddGfx : 8; - unsigned int AcpLevel_3_MinVoltage_Vddci : 8; - unsigned int AcpLevel_3_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_324__VI { - struct { - unsigned int AcpLevel_3_padding_2 : 8; - unsigned int AcpLevel_3_padding_1 : 8; - unsigned int AcpLevel_3_padding_0 : 8; - unsigned int AcpLevel_3_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_325__VI { - struct { - unsigned int AcpLevel_4_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_326__VI { - struct { - unsigned int AcpLevel_4_MinVoltage_Phases : 8; - unsigned int AcpLevel_4_MinVoltage_VddGfx : 8; - unsigned int AcpLevel_4_MinVoltage_Vddci : 8; - unsigned int AcpLevel_4_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_327__VI { - struct { - unsigned int AcpLevel_4_padding_2 : 8; - unsigned int AcpLevel_4_padding_1 : 8; - unsigned int AcpLevel_4_padding_0 : 8; - unsigned int AcpLevel_4_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_328__VI { - struct { - unsigned int AcpLevel_5_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_329__VI { - struct { - unsigned int AcpLevel_5_MinVoltage_Phases : 8; - unsigned int AcpLevel_5_MinVoltage_VddGfx : 8; - unsigned int AcpLevel_5_MinVoltage_Vddci : 8; - unsigned int AcpLevel_5_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_33__VI { - struct { - unsigned int SmioTable1_Pattern_1_padding : 8; - unsigned int SmioTable1_Pattern_1_Smio : 8; - unsigned int SmioTable1_Pattern_1_Voltage : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_330__VI { - struct { - unsigned int AcpLevel_5_padding_2 : 8; - unsigned int AcpLevel_5_padding_1 : 8; - unsigned int AcpLevel_5_padding_0 : 8; - unsigned int AcpLevel_5_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_331__VI { - struct { - unsigned int AcpLevel_6_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_332__VI { - struct { - unsigned int AcpLevel_6_MinVoltage_Phases : 8; - unsigned int AcpLevel_6_MinVoltage_VddGfx : 8; - unsigned int AcpLevel_6_MinVoltage_Vddci : 8; - unsigned int AcpLevel_6_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_333__VI { - struct { - unsigned int AcpLevel_6_padding_2 : 8; - unsigned int AcpLevel_6_padding_1 : 8; - unsigned int AcpLevel_6_padding_0 : 8; - unsigned int AcpLevel_6_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_334__VI { - struct { - unsigned int AcpLevel_7_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_335__VI { - struct { - unsigned int AcpLevel_7_MinVoltage_Phases : 8; - unsigned int AcpLevel_7_MinVoltage_VddGfx : 8; - unsigned int AcpLevel_7_MinVoltage_Vddci : 8; - unsigned int AcpLevel_7_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_336__VI { - struct { - unsigned int AcpLevel_7_padding_2 : 8; - unsigned int AcpLevel_7_padding_1 : 8; - unsigned int AcpLevel_7_padding_0 : 8; - unsigned int AcpLevel_7_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_337__VI { - struct { - unsigned int SamuLevel_0_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_338__VI { - struct { - unsigned int SamuLevel_0_MinVoltage_Phases : 8; - unsigned int SamuLevel_0_MinVoltage_VddGfx : 8; - unsigned int SamuLevel_0_MinVoltage_Vddci : 8; - unsigned int SamuLevel_0_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_339__VI { - struct { - unsigned int SamuLevel_0_padding_2 : 8; - unsigned int SamuLevel_0_padding_1 : 8; - unsigned int SamuLevel_0_padding_0 : 8; - unsigned int SamuLevel_0_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_34__VI { - struct { - unsigned int SmioTable1_Pattern_2_padding : 8; - unsigned int SmioTable1_Pattern_2_Smio : 8; - unsigned int SmioTable1_Pattern_2_Voltage : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_340__VI { - struct { - unsigned int SamuLevel_1_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_341__VI { - struct { - unsigned int SamuLevel_1_MinVoltage_Phases : 8; - unsigned int SamuLevel_1_MinVoltage_VddGfx : 8; - unsigned int SamuLevel_1_MinVoltage_Vddci : 8; - unsigned int SamuLevel_1_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_342__VI { - struct { - unsigned int SamuLevel_1_padding_2 : 8; - unsigned int SamuLevel_1_padding_1 : 8; - unsigned int SamuLevel_1_padding_0 : 8; - unsigned int SamuLevel_1_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_343__VI { - struct { - unsigned int SamuLevel_2_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_344__VI { - struct { - unsigned int SamuLevel_2_MinVoltage_Phases : 8; - unsigned int SamuLevel_2_MinVoltage_VddGfx : 8; - unsigned int SamuLevel_2_MinVoltage_Vddci : 8; - unsigned int SamuLevel_2_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_345__VI { - struct { - unsigned int SamuLevel_2_padding_2 : 8; - unsigned int SamuLevel_2_padding_1 : 8; - unsigned int SamuLevel_2_padding_0 : 8; - unsigned int SamuLevel_2_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_346__VI { - struct { - unsigned int SamuLevel_3_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_347__VI { - struct { - unsigned int SamuLevel_3_MinVoltage_Phases : 8; - unsigned int SamuLevel_3_MinVoltage_VddGfx : 8; - unsigned int SamuLevel_3_MinVoltage_Vddci : 8; - unsigned int SamuLevel_3_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_348__VI { - struct { - unsigned int SamuLevel_3_padding_2 : 8; - unsigned int SamuLevel_3_padding_1 : 8; - unsigned int SamuLevel_3_padding_0 : 8; - unsigned int SamuLevel_3_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_349__VI { - struct { - unsigned int SamuLevel_4_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_35__VI { - struct { - unsigned int SmioTable1_Pattern_3_padding : 8; - unsigned int SmioTable1_Pattern_3_Smio : 8; - unsigned int SmioTable1_Pattern_3_Voltage : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_350__VI { - struct { - unsigned int SamuLevel_4_MinVoltage_Phases : 8; - unsigned int SamuLevel_4_MinVoltage_VddGfx : 8; - unsigned int SamuLevel_4_MinVoltage_Vddci : 8; - unsigned int SamuLevel_4_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_351__VI { - struct { - unsigned int SamuLevel_4_padding_2 : 8; - unsigned int SamuLevel_4_padding_1 : 8; - unsigned int SamuLevel_4_padding_0 : 8; - unsigned int SamuLevel_4_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_352__VI { - struct { - unsigned int SamuLevel_5_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_353__VI { - struct { - unsigned int SamuLevel_5_MinVoltage_Phases : 8; - unsigned int SamuLevel_5_MinVoltage_VddGfx : 8; - unsigned int SamuLevel_5_MinVoltage_Vddci : 8; - unsigned int SamuLevel_5_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_354__VI { - struct { - unsigned int SamuLevel_5_padding_2 : 8; - unsigned int SamuLevel_5_padding_1 : 8; - unsigned int SamuLevel_5_padding_0 : 8; - unsigned int SamuLevel_5_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_355__VI { - struct { - unsigned int SamuLevel_6_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_356__VI { - struct { - unsigned int SamuLevel_6_MinVoltage_Phases : 8; - unsigned int SamuLevel_6_MinVoltage_VddGfx : 8; - unsigned int SamuLevel_6_MinVoltage_Vddci : 8; - unsigned int SamuLevel_6_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_357__VI { - struct { - unsigned int SamuLevel_6_padding_2 : 8; - unsigned int SamuLevel_6_padding_1 : 8; - unsigned int SamuLevel_6_padding_0 : 8; - unsigned int SamuLevel_6_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_358__VI { - struct { - unsigned int SamuLevel_7_Frequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_359__VI { - struct { - unsigned int SamuLevel_7_MinVoltage_Phases : 8; - unsigned int SamuLevel_7_MinVoltage_VddGfx : 8; - unsigned int SamuLevel_7_MinVoltage_Vddci : 8; - unsigned int SamuLevel_7_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_36__VI { - struct { - unsigned int SmioTable2_Pattern_0_padding : 8; - unsigned int SmioTable2_Pattern_0_Smio : 8; - unsigned int SmioTable2_Pattern_0_Voltage : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_360__VI { - struct { - unsigned int SamuLevel_7_padding_2 : 8; - unsigned int SamuLevel_7_padding_1 : 8; - unsigned int SamuLevel_7_padding_0 : 8; - unsigned int SamuLevel_7_Divider : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_361__VI { - struct { - unsigned int Ulv_CcPwrDynRm : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_362__VI { - struct { - unsigned int Ulv_CcPwrDynRm1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_363__VI { - struct { - unsigned int Ulv_VddcPhase : 8; - unsigned int Ulv_VddcOffsetVid : 8; - unsigned int Ulv_VddcOffset : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_364__VI { - struct { - unsigned int Ulv_Reserved : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_365__VI { - struct { - unsigned int SclkStepSize : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_366__VI { - struct { - unsigned int Smio_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_367__VI { - struct { - unsigned int Smio_1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_368__VI { - struct { - unsigned int Smio_2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_369__VI { - struct { - unsigned int Smio_3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_37__VI { - struct { - unsigned int SmioTable2_Pattern_1_padding : 8; - unsigned int SmioTable2_Pattern_1_Smio : 8; - unsigned int SmioTable2_Pattern_1_Voltage : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_370__VI { - struct { - unsigned int Smio_4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_371__VI { - struct { - unsigned int Smio_5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_372__VI { - struct { - unsigned int Smio_6 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_373__VI { - struct { - unsigned int Smio_7 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_374__VI { - struct { - unsigned int Smio_8 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_375__VI { - struct { - unsigned int Smio_9 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_376__VI { - struct { - unsigned int Smio_10 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_377__VI { - struct { - unsigned int Smio_11 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_378__VI { - struct { - unsigned int Smio_12 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_379__VI { - struct { - unsigned int Smio_13 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_38__VI { - struct { - unsigned int SmioTable2_Pattern_2_padding : 8; - unsigned int SmioTable2_Pattern_2_Smio : 8; - unsigned int SmioTable2_Pattern_2_Voltage : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_380__VI { - struct { - unsigned int Smio_14 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_381__VI { - struct { - unsigned int Smio_15 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_382__VI { - struct { - unsigned int Smio_16 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_383__VI { - struct { - unsigned int Smio_17 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_384__VI { - struct { - unsigned int Smio_18 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_385__VI { - struct { - unsigned int Smio_19 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_386__VI { - struct { - unsigned int Smio_20 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_387__VI { - struct { - unsigned int Smio_21 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_388__VI { - struct { - unsigned int Smio_22 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_389__VI { - struct { - unsigned int Smio_23 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_39__VI { - struct { - unsigned int SmioTable2_Pattern_3_padding : 8; - unsigned int SmioTable2_Pattern_3_Smio : 8; - unsigned int SmioTable2_Pattern_3_Voltage : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_390__VI { - struct { - unsigned int Smio_24 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_391__VI { - struct { - unsigned int Smio_25 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_392__VI { - struct { - unsigned int Smio_26 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_393__VI { - struct { - unsigned int Smio_27 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_394__VI { - struct { - unsigned int Smio_28 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_395__VI { - struct { - unsigned int Smio_29 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_396__VI { - struct { - unsigned int Smio_30 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_397__VI { - struct { - unsigned int Smio_31 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_398__VI { - struct { - unsigned int SamuBootLevel : 8; - unsigned int AcpBootLevel : 8; - unsigned int VceBootLevel : 8; - unsigned int UvdBootLevel : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_399__VI { - struct { - unsigned int GraphicsInterval : 8; - unsigned int GraphicsThermThrottleEnable : 8; - unsigned int GraphicsVoltageChangeEnable : 8; - unsigned int GraphicsBootLevel : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_4__VI { - struct { - unsigned int GraphicsPIDController_StatePrecision : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_40__VI { - struct { - unsigned int VddcLevelCount : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_400__VI { - struct { - unsigned int TemperatureLimitHigh : 16; - unsigned int ThermalInterval : 8; - unsigned int VoltageInterval : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_401__VI { - struct { - unsigned int MemoryVoltageChangeEnable : 8; - unsigned int MemoryBootLevel : 8; - unsigned int TemperatureLimitLow : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_402__VI { - struct { - unsigned int MemoryThermThrottleEnable : 8; - unsigned int MemoryInterval : 8; - unsigned int BootMVdd : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_403__VI { - struct { - unsigned int PhaseResponseTime : 16; - unsigned int VoltageResponseTime : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_404__VI { - struct { - unsigned int DTEMode : 8; - unsigned int DTEInterval : 8; - unsigned int PCIeGenInterval : 8; - unsigned int PCIeBootLinkLevel : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_405__VI { - struct { - unsigned int ThermGpio : 8; - unsigned int AcDcGpio : 8; - unsigned int VRHotGpio : 8; - unsigned int SVI2Enable : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_406__VI { - struct { - unsigned int PPM_TemperatureLimit : 16; - unsigned int PPM_PkgPwrLimit : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_407__VI { - struct { - unsigned int TargetTdp : 16; - unsigned int DefaultTdp : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_408__VI { - struct { - unsigned int FpsLowThreshold : 16; - unsigned int FpsHighThreshold : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_409__VI { - struct { - unsigned int BAPMTI_R_0_1_0 : 16; - unsigned int BAPMTI_R_0_0_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_41__VI { - struct { - unsigned int VddciLevelCount : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_410__VI { - struct { - unsigned int BAPMTI_R_1_0_0 : 16; - unsigned int BAPMTI_R_0_2_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_411__VI { - struct { - unsigned int BAPMTI_R_1_2_0 : 16; - unsigned int BAPMTI_R_1_1_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_412__VI { - struct { - unsigned int BAPMTI_R_2_1_0 : 16; - unsigned int BAPMTI_R_2_0_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_413__VI { - struct { - unsigned int BAPMTI_R_3_0_0 : 16; - unsigned int BAPMTI_R_2_2_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_414__VI { - struct { - unsigned int BAPMTI_R_3_2_0 : 16; - unsigned int BAPMTI_R_3_1_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_415__VI { - struct { - unsigned int BAPMTI_R_4_1_0 : 16; - unsigned int BAPMTI_R_4_0_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_416__VI { - struct { - unsigned int BAPMTI_RC_0_0_0 : 16; - unsigned int BAPMTI_R_4_2_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_417__VI { - struct { - unsigned int BAPMTI_RC_0_2_0 : 16; - unsigned int BAPMTI_RC_0_1_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_418__VI { - struct { - unsigned int BAPMTI_RC_1_1_0 : 16; - unsigned int BAPMTI_RC_1_0_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_419__VI { - struct { - unsigned int BAPMTI_RC_2_0_0 : 16; - unsigned int BAPMTI_RC_1_2_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_42__VI { - struct { - unsigned int VddGfxLevelCount : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_420__VI { - struct { - unsigned int BAPMTI_RC_2_2_0 : 16; - unsigned int BAPMTI_RC_2_1_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_421__VI { - struct { - unsigned int BAPMTI_RC_3_1_0 : 16; - unsigned int BAPMTI_RC_3_0_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_422__VI { - struct { - unsigned int BAPMTI_RC_4_0_0 : 16; - unsigned int BAPMTI_RC_3_2_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_423__VI { - struct { - unsigned int BAPMTI_RC_4_2_0 : 16; - unsigned int BAPMTI_RC_4_1_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_424__VI { - struct { - unsigned int GpuTjHyst : 8; - unsigned int GpuTjMax : 8; - unsigned int DTETjOffset : 8; - unsigned int DTEAmbientTempBase : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_425__VI { - struct { - unsigned int BootVoltage_Phases : 8; - unsigned int BootVoltage_VddGfx : 8; - unsigned int BootVoltage_Vddci : 8; - unsigned int BootVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_426__VI { - struct { - unsigned int BAPM_TEMP_GRADIENT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_427__VI { - struct { - unsigned int LowSclkInterruptThreshold : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_428__VI { - struct { - unsigned int VddGfxReChkWait : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_429__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_43__VI { - struct { - unsigned int MvddLevelCount : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_430__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_431__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_432__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_433__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_434__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_435__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_436__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_437__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_438__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_439__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_44__VI { - struct { - unsigned int VddcTable_1 : 16; - unsigned int VddcTable_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_440__VI { - struct { - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5 : 8; - unsigned int ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_45__VI { - struct { - unsigned int VddcTable_3 : 16; - unsigned int VddcTable_2 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_46__VI { - struct { - unsigned int VddcTable_5 : 16; - unsigned int VddcTable_4 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_47__VI { - struct { - unsigned int VddcTable_7 : 16; - unsigned int VddcTable_6 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_48__VI { - struct { - unsigned int VddcTable_9 : 16; - unsigned int VddcTable_8 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_49__VI { - struct { - unsigned int VddcTable_11 : 16; - unsigned int VddcTable_10 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_5__VI { - struct { - unsigned int GraphicsPIDController_LfPrecision : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_50__VI { - struct { - unsigned int VddcTable_13 : 16; - unsigned int VddcTable_12 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_51__VI { - struct { - unsigned int VddcTable_15 : 16; - unsigned int VddcTable_14 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_52__VI { - struct { - unsigned int VddGfxTable_1 : 16; - unsigned int VddGfxTable_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_53__VI { - struct { - unsigned int VddGfxTable_3 : 16; - unsigned int VddGfxTable_2 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_54__VI { - struct { - unsigned int VddGfxTable_5 : 16; - unsigned int VddGfxTable_4 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_55__VI { - struct { - unsigned int VddGfxTable_7 : 16; - unsigned int VddGfxTable_6 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_56__VI { - struct { - unsigned int VddGfxTable_9 : 16; - unsigned int VddGfxTable_8 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_57__VI { - struct { - unsigned int VddGfxTable_11 : 16; - unsigned int VddGfxTable_10 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_58__VI { - struct { - unsigned int VddGfxTable_13 : 16; - unsigned int VddGfxTable_12 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_59__VI { - struct { - unsigned int VddGfxTable_15 : 16; - unsigned int VddGfxTable_14 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_6__VI { - struct { - unsigned int GraphicsPIDController_LfOffset : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_60__VI { - struct { - unsigned int VddciTable_1 : 16; - unsigned int VddciTable_0 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_61__VI { - struct { - unsigned int VddciTable_3 : 16; - unsigned int VddciTable_2 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_62__VI { - struct { - unsigned int VddciTable_5 : 16; - unsigned int VddciTable_4 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_63__VI { - struct { - unsigned int VddciTable_7 : 16; - unsigned int VddciTable_6 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_64__VI { - struct { - unsigned int BapmVddGfxVidHiSidd_3 : 8; - unsigned int BapmVddGfxVidHiSidd_2 : 8; - unsigned int BapmVddGfxVidHiSidd_1 : 8; - unsigned int BapmVddGfxVidHiSidd_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_65__VI { - struct { - unsigned int BapmVddGfxVidHiSidd_7 : 8; - unsigned int BapmVddGfxVidHiSidd_6 : 8; - unsigned int BapmVddGfxVidHiSidd_5 : 8; - unsigned int BapmVddGfxVidHiSidd_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_66__VI { - struct { - unsigned int BapmVddGfxVidHiSidd_11 : 8; - unsigned int BapmVddGfxVidHiSidd_10 : 8; - unsigned int BapmVddGfxVidHiSidd_9 : 8; - unsigned int BapmVddGfxVidHiSidd_8 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_67__VI { - struct { - unsigned int BapmVddGfxVidHiSidd_15 : 8; - unsigned int BapmVddGfxVidHiSidd_14 : 8; - unsigned int BapmVddGfxVidHiSidd_13 : 8; - unsigned int BapmVddGfxVidHiSidd_12 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_68__VI { - struct { - unsigned int BapmVddGfxVidLoSidd_3 : 8; - unsigned int BapmVddGfxVidLoSidd_2 : 8; - unsigned int BapmVddGfxVidLoSidd_1 : 8; - unsigned int BapmVddGfxVidLoSidd_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_69__VI { - struct { - unsigned int BapmVddGfxVidLoSidd_7 : 8; - unsigned int BapmVddGfxVidLoSidd_6 : 8; - unsigned int BapmVddGfxVidLoSidd_5 : 8; - unsigned int BapmVddGfxVidLoSidd_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_7__VI { - struct { - unsigned int GraphicsPIDController_MaxState : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_70__VI { - struct { - unsigned int BapmVddGfxVidLoSidd_11 : 8; - unsigned int BapmVddGfxVidLoSidd_10 : 8; - unsigned int BapmVddGfxVidLoSidd_9 : 8; - unsigned int BapmVddGfxVidLoSidd_8 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_71__VI { - struct { - unsigned int BapmVddGfxVidLoSidd_15 : 8; - unsigned int BapmVddGfxVidLoSidd_14 : 8; - unsigned int BapmVddGfxVidLoSidd_13 : 8; - unsigned int BapmVddGfxVidLoSidd_12 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_72__VI { - struct { - unsigned int BapmVddGfxVidHiSidd2_3 : 8; - unsigned int BapmVddGfxVidHiSidd2_2 : 8; - unsigned int BapmVddGfxVidHiSidd2_1 : 8; - unsigned int BapmVddGfxVidHiSidd2_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_73__VI { - struct { - unsigned int BapmVddGfxVidHiSidd2_7 : 8; - unsigned int BapmVddGfxVidHiSidd2_6 : 8; - unsigned int BapmVddGfxVidHiSidd2_5 : 8; - unsigned int BapmVddGfxVidHiSidd2_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_74__VI { - struct { - unsigned int BapmVddGfxVidHiSidd2_11 : 8; - unsigned int BapmVddGfxVidHiSidd2_10 : 8; - unsigned int BapmVddGfxVidHiSidd2_9 : 8; - unsigned int BapmVddGfxVidHiSidd2_8 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_75__VI { - struct { - unsigned int BapmVddGfxVidHiSidd2_15 : 8; - unsigned int BapmVddGfxVidHiSidd2_14 : 8; - unsigned int BapmVddGfxVidHiSidd2_13 : 8; - unsigned int BapmVddGfxVidHiSidd2_12 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_76__VI { - struct { - unsigned int BapmVddcVidHiSidd_3 : 8; - unsigned int BapmVddcVidHiSidd_2 : 8; - unsigned int BapmVddcVidHiSidd_1 : 8; - unsigned int BapmVddcVidHiSidd_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_77__VI { - struct { - unsigned int BapmVddcVidHiSidd_7 : 8; - unsigned int BapmVddcVidHiSidd_6 : 8; - unsigned int BapmVddcVidHiSidd_5 : 8; - unsigned int BapmVddcVidHiSidd_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_78__VI { - struct { - unsigned int BapmVddcVidHiSidd_11 : 8; - unsigned int BapmVddcVidHiSidd_10 : 8; - unsigned int BapmVddcVidHiSidd_9 : 8; - unsigned int BapmVddcVidHiSidd_8 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_79__VI { - struct { - unsigned int BapmVddcVidHiSidd_15 : 8; - unsigned int BapmVddcVidHiSidd_14 : 8; - unsigned int BapmVddcVidHiSidd_13 : 8; - unsigned int BapmVddcVidHiSidd_12 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_8__VI { - struct { - unsigned int GraphicsPIDController_MaxLfFraction : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_80__VI { - struct { - unsigned int BapmVddcVidLoSidd_3 : 8; - unsigned int BapmVddcVidLoSidd_2 : 8; - unsigned int BapmVddcVidLoSidd_1 : 8; - unsigned int BapmVddcVidLoSidd_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_81__VI { - struct { - unsigned int BapmVddcVidLoSidd_7 : 8; - unsigned int BapmVddcVidLoSidd_6 : 8; - unsigned int BapmVddcVidLoSidd_5 : 8; - unsigned int BapmVddcVidLoSidd_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_82__VI { - struct { - unsigned int BapmVddcVidLoSidd_11 : 8; - unsigned int BapmVddcVidLoSidd_10 : 8; - unsigned int BapmVddcVidLoSidd_9 : 8; - unsigned int BapmVddcVidLoSidd_8 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_83__VI { - struct { - unsigned int BapmVddcVidLoSidd_15 : 8; - unsigned int BapmVddcVidLoSidd_14 : 8; - unsigned int BapmVddcVidLoSidd_13 : 8; - unsigned int BapmVddcVidLoSidd_12 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_84__VI { - struct { - unsigned int BapmVddcVidHiSidd2_3 : 8; - unsigned int BapmVddcVidHiSidd2_2 : 8; - unsigned int BapmVddcVidHiSidd2_1 : 8; - unsigned int BapmVddcVidHiSidd2_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_85__VI { - struct { - unsigned int BapmVddcVidHiSidd2_7 : 8; - unsigned int BapmVddcVidHiSidd2_6 : 8; - unsigned int BapmVddcVidHiSidd2_5 : 8; - unsigned int BapmVddcVidHiSidd2_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_86__VI { - struct { - unsigned int BapmVddcVidHiSidd2_11 : 8; - unsigned int BapmVddcVidHiSidd2_10 : 8; - unsigned int BapmVddcVidHiSidd2_9 : 8; - unsigned int BapmVddcVidHiSidd2_8 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_87__VI { - struct { - unsigned int BapmVddcVidHiSidd2_15 : 8; - unsigned int BapmVddcVidHiSidd2_14 : 8; - unsigned int BapmVddcVidHiSidd2_13 : 8; - unsigned int BapmVddcVidHiSidd2_12 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_88__VI { - struct { - unsigned int MasterDeepSleepControl : 8; - unsigned int LinkLevelCount : 8; - unsigned int MemoryDpmLevelCount : 8; - unsigned int GraphicsDpmLevelCount : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_89__VI { - struct { - unsigned int SamuLevelCount : 8; - unsigned int AcpLevelCount : 8; - unsigned int VceLevelCount : 8; - unsigned int UvdLevelCount : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_9__VI { - struct { - unsigned int GraphicsPIDController_StateShift : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_90__VI { - struct { - unsigned int Reserved_0 : 8; - unsigned int ThermOutMode : 8; - unsigned int ThermOutPolarity : 8; - unsigned int ThermOutGpio : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_91__VI { - struct { - unsigned int Reserved_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_92__VI { - struct { - unsigned int Reserved_1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_93__VI { - struct { - unsigned int Reserved_2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_94__VI { - struct { - unsigned int Reserved_3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_95__VI { - struct { - unsigned int GraphicsLevel_0_MinVoltage_Phases : 8; - unsigned int GraphicsLevel_0_MinVoltage_VddGfx : 8; - unsigned int GraphicsLevel_0_MinVoltage_Vddci : 8; - unsigned int GraphicsLevel_0_MinVoltage_Vddc : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_96__VI { - struct { - unsigned int GraphicsLevel_0_SclkFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_97__VI { - struct { - unsigned int GraphicsLevel_0_ActivityLevel : 16; - unsigned int GraphicsLevel_0_DeepSleepDivId : 8; - unsigned int GraphicsLevel_0_pcieDpmLevel : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_98__VI { - struct { - unsigned int GraphicsLevel_0_CgSpllFuncCntl3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPM_TABLE_99__VI { - struct { - unsigned int GraphicsLevel_0_CgSpllFuncCntl4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPREFCLK_CGTT_BLK_CTRL_REG__VI { - struct { - unsigned int DPREFCLK_TURN_ON_DELAY : 4; - unsigned int DPREFCLK_TURN_OFF_DELAY : 8; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DPREFCLK_CNTL__VI { - struct { - unsigned int DPREFCLK_SRC_SEL : 3; - unsigned int : 5; - unsigned int UNB_DB_CLK_ENABLE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_A__VI { - struct { - unsigned int DP_AUX_DEBUG_A : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_B__VI { - struct { - unsigned int DP_AUX_DEBUG_B : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_C__VI { - struct { - unsigned int DP_AUX_DEBUG_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_D__VI { - struct { - unsigned int DP_AUX_DEBUG_D : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_E__VI { - struct { - unsigned int DP_AUX_DEBUG_E : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_F__VI { - struct { - unsigned int DP_AUX_DEBUG_F : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_G__VI { - struct { - unsigned int DP_AUX_DEBUG_G : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_H__VI { - struct { - unsigned int DP_AUX_DEBUG_H : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_I__VI { - struct { - unsigned int DP_AUX_DEBUG_I : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_J__VI { - struct { - unsigned int DP_AUX_DEBUG_J : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_K__VI { - struct { - unsigned int DP_AUX_DEBUG_K : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_L__VI { - struct { - unsigned int DP_AUX_DEBUG_L : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_M__VI { - struct { - unsigned int DP_AUX_DEBUG_M : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_N__VI { - struct { - unsigned int DP_AUX_DEBUG_N : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_O__VI { - struct { - unsigned int DP_AUX_DEBUG_O : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_P__VI { - struct { - unsigned int DP_AUX_DEBUG_P : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_AUX_DEBUG_Q__VI { - struct { - unsigned int DP_AUX_DEBUG_Q : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_CRC_MST_CNTL__VI { - struct { - unsigned int DPHY_CRC_MST_FIRST_SLOT : 6; - unsigned int : 2; - unsigned int DPHY_CRC_MST_LAST_SLOT : 6; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_CRC_MST_STATUS__VI { - struct { - unsigned int DPHY_CRC_MST_PHASE_LOCK : 1; - unsigned int : 7; - unsigned int DPHY_CRC_MST_PHASE_ERROR : 1; - unsigned int : 7; - unsigned int DPHY_CRC_MST_PHASE_ERROR_ACK : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_FAST_TRAINING_STATUS__VI { - struct { - unsigned int DPHY_FAST_TRAINING_STATE : 3; - unsigned int : 1; - unsigned int DPHY_FAST_TRAINING_COMPLETE_OCCURRED : 1; - unsigned int : 3; - unsigned int DPHY_FAST_TRAINING_COMPLETE_MASK : 1; - unsigned int : 3; - unsigned int DPHY_FAST_TRAINING_COMPLETE_ACK : 1; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_SYM0__VI { - struct { - unsigned int DPHY_SYM1 : 10; - unsigned int DPHY_SYM2 : 10; - unsigned int DPHY_SYM3 : 10; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_SYM1__VI { - struct { - unsigned int DPHY_SYM4 : 10; - unsigned int DPHY_SYM5 : 10; - unsigned int DPHY_SYM6 : 10; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_DPHY_SYM2__VI { - struct { - unsigned int DPHY_SYM7 : 10; - unsigned int DPHY_SYM8 : 10; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_FE_TEST_DEBUG_DATA__VI { - struct { - unsigned int DP_FE_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_FE_TEST_DEBUG_INDEX__VI { - struct { - unsigned int DP_FE_TEST_DEBUG_INDEX : 8; - unsigned int DP_FE_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_HBR2_EYE_PATTERN__VI { - struct { - unsigned int DP_HBR2_EYE_PATTERN_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_LINK_FRAMING_CNTL__VI { - struct { - unsigned int DP_IDLE_BS_INTERVAL : 18; - unsigned int : 6; - unsigned int DP_VBID_DISABLE : 1; - unsigned int : 3; - unsigned int DP_VID_ENHANCED_FRAME_MODE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSA_COLORIMETRY__VI { - struct { - unsigned int DP_MSA_MISC0_OVERRIDE : 8; - unsigned int DP_MSA_MISC0_OVERRIDE_ENABLE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSA_MISC__VI { - struct { - unsigned int : 3; - unsigned int DP_MSA_MISC1 : 4; - unsigned int : 1; - unsigned int DP_MSA_MISC2 : 8; - unsigned int DP_MSA_MISC3 : 8; - unsigned int DP_MSA_MISC4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSA_V_TIMING_OVERRIDE1__VI { - struct { - unsigned int DP_MSA_V_TIMING_OVERRIDE_EN : 1; - unsigned int : 3; - unsigned int DP_MSA_V_TOTAL_OVERRIDE : 14; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSA_V_TIMING_OVERRIDE2__VI { - struct { - unsigned int DP_MSA_V_BLANK_START_OVERRIDE : 14; - unsigned int : 2; - unsigned int DP_MSA_V_BLANK_END_OVERRIDE : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSE_LINK_TIMING__VI { - struct { - unsigned int DP_MSE_LINK_FRAME : 10; - unsigned int : 6; - unsigned int DP_MSE_LINK_LINE : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSE_MISC_CNTL__VI { - struct { - unsigned int DP_MSE_BLANK_CODE : 1; - unsigned int : 3; - unsigned int DP_MSE_TIMESTAMP_MODE : 1; - unsigned int : 3; - unsigned int DP_MSE_ZERO_ENCODER : 1; - unsigned int : 7; - unsigned int DP_MSE_OUTPUT_DPDBG_DATA : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSE_RATE_CNTL__VI { - struct { - unsigned int DP_MSE_RATE_Y : 26; - unsigned int DP_MSE_RATE_X : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSE_RATE_UPDATE__VI { - struct { - unsigned int DP_MSE_RATE_UPDATE_PENDING : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSE_SAT0__VI { - struct { - unsigned int DP_MSE_SAT_SRC0 : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int DP_MSE_SAT_SLOT_COUNT0 : 6; - unsigned int : 2; - unsigned int DP_MSE_SAT_SRC1 : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int DP_MSE_SAT_SLOT_COUNT1 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSE_SAT1__VI { - struct { - unsigned int DP_MSE_SAT_SRC2 : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int DP_MSE_SAT_SLOT_COUNT2 : 6; - unsigned int : 2; - unsigned int DP_MSE_SAT_SRC3 : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int DP_MSE_SAT_SLOT_COUNT3 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSE_SAT2__VI { - struct { - unsigned int DP_MSE_SAT_SRC4 : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int DP_MSE_SAT_SLOT_COUNT4 : 6; - unsigned int : 2; - unsigned int DP_MSE_SAT_SRC5 : 3; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int DP_MSE_SAT_SLOT_COUNT5 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_MSE_SAT_UPDATE__VI { - struct { - unsigned int DP_MSE_SAT_UPDATE : 2; - unsigned int : 6; - unsigned int DP_MSE_16_MTP_KEEPOUT : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DP_SEC_CNTL1__VI { - struct { - unsigned int DP_SEC_ISRC_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_CLK_ENABLE__VI { - struct { - unsigned int DVO_CLK_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_FIFO_ERROR_STATUS__VI { - struct { - unsigned int DVO_FIFO_LEVEL_ERROR : 1; - unsigned int DVO_FIFO_USE_OVERWRITE_LEVEL : 1; - unsigned int DVO_FIFO_OVERWRITE_LEVEL : 6; - unsigned int DVO_FIFO_ERROR_ACK : 1; - unsigned int : 1; - unsigned int DVO_FIFO_CAL_AVERAGE_LEVEL : 6; - unsigned int DVO_FIFO_MAXIMUM_LEVEL : 4; - unsigned int : 2; - unsigned int DVO_FIFO_MINIMUM_LEVEL : 4; - unsigned int : 3; - unsigned int DVO_FIFO_CALIBRATED : 1; - unsigned int DVO_FIFO_FORCE_RECAL_AVERAGE : 1; - unsigned int DVO_FIFO_FORCE_RECOMP_MINMAX : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_SKEW_ADJUST__VI { - struct { - unsigned int DVO_SKEW_ADJUST : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_TEST_DEBUG_DATA__VI { - struct { - unsigned int DVO_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_TEST_DEBUG_INDEX__VI { - struct { - unsigned int DVO_TEST_DEBUG_INDEX : 8; - unsigned int DVO_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union DVO_VREF_CONTROL__VI { - struct { - unsigned int DVO_VREFPON : 1; - unsigned int DVO_VREFSEL : 1; - unsigned int : 2; - unsigned int DVO_VREFCAL : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union ENTITY_TEMPERATURES_1__VI { - struct { - unsigned int GPU : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_DEBUG_CSR_RDATA_HI__VI { - struct { - unsigned int FBC_DEBUG_CSR_RDATA_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_DEBUG_CSR_WDATA_HI__VI { - struct { - unsigned int FBC_DEBUG_CSR_WDATA_HI : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FBC_STATUS__VI { - struct { - unsigned int FBC_ENABLE_STATUS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FEATURE_STATUS__VI { - struct { - unsigned int SCLK_DPM_ON : 1; - unsigned int MCLK_DPM_ON : 1; - unsigned int LCLK_DPM_ON : 1; - unsigned int UVD_DPM_ON : 1; - unsigned int VCE_DPM_ON : 1; - unsigned int SAMU_DPM_ON : 1; - unsigned int ACP_DPM_ON : 1; - unsigned int PCIE_DPM_ON : 1; - unsigned int BAPM_ON : 1; - unsigned int LPMX_ON : 1; - unsigned int NBDPM_ON : 1; - unsigned int LHTC_ON : 1; - unsigned int VPC_ON : 1; - unsigned int VOLTAGE_CONTROLLER_ON : 1; - unsigned int TDC_LIMIT_ON : 1; - unsigned int GPU_CAC_ON : 1; - unsigned int AVS_ON : 1; - unsigned int SPMI_ON : 1; - unsigned int SCLK_DPM_FORCED : 1; - unsigned int MCLK_DPM_FORCED : 1; - unsigned int LCLK_DPM_FORCED : 1; - unsigned int PCIE_DPM_FORCED : 1; - unsigned int RESERVED : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_CLAMP_COMPONENT_B__VI { - struct { - unsigned int FMT_CLAMP_LOWER_B : 16; - unsigned int FMT_CLAMP_UPPER_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_CLAMP_COMPONENT_G__VI { - struct { - unsigned int FMT_CLAMP_LOWER_G : 16; - unsigned int FMT_CLAMP_UPPER_G : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_CLAMP_COMPONENT_R__VI { - struct { - unsigned int FMT_CLAMP_LOWER_R : 16; - unsigned int FMT_CLAMP_UPPER_R : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_DEBUG0__VI { - struct { - unsigned int FMT_DEBUG0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_DEBUG1__VI { - struct { - unsigned int FMT_DEBUG1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_DEBUG2__VI { - struct { - unsigned int FMT_DEBUG2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_DEBUG_ID__VI { - struct { - unsigned int FMT_DEBUG_ID : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_TEST_DEBUG_DATA__VI { - struct { - unsigned int FMT_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union FMT_TEST_DEBUG_INDEX__VI { - struct { - unsigned int FMT_TEST_DEBUG_INDEX : 8; - unsigned int FMT_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_END_CNTL1__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION_END : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_END_CNTL2__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE : 16; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION_END_BASE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_REGION_0_1__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_REGION_10_11__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_REGION_12_13__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_REGION_14_15__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_REGION_2_3__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_REGION_4_5__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_REGION_6_7__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_REGION_8_9__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_SLOPE_CNTL__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLA_START_CNTL__VI { - struct { - unsigned int GAMMA_CORR_CNTLA_EXP_REGION_START : 18; - unsigned int : 2; - unsigned int GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT : 7; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_END_CNTL1__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION_END : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_END_CNTL2__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE : 16; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION_END_BASE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_REGION_0_1__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_REGION_10_11__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_REGION_12_13__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_REGION_14_15__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_REGION_2_3__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_REGION_4_5__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_REGION_6_7__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_REGION_8_9__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET : 8; - unsigned int : 3; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET : 8; - unsigned int : 4; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_SLOPE_CNTL__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CNTLB_START_CNTL__VI { - struct { - unsigned int GAMMA_CORR_CNTLB_EXP_REGION_START : 18; - unsigned int : 2; - unsigned int GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT : 7; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_CONTROL__VI { - struct { - unsigned int GAMMA_CORR_MODE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_LUT_DATA__VI { - struct { - unsigned int GAMMA_CORR_LUT_DATA : 19; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_LUT_INDEX__VI { - struct { - unsigned int GAMMA_CORR_LUT_INDEX : 9; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMMA_CORR_LUT_WRITE_EN_MASK__VI { - struct { - unsigned int GAMMA_CORR_LUT_WRITE_EN_MASK : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMUT_REMAP_C11_C12__VI { - struct { - unsigned int GAMUT_REMAP_C11 : 16; - unsigned int GAMUT_REMAP_C12 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMUT_REMAP_C13_C14__VI { - struct { - unsigned int GAMUT_REMAP_C13 : 16; - unsigned int GAMUT_REMAP_C14 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMUT_REMAP_C21_C22__VI { - struct { - unsigned int GAMUT_REMAP_C21 : 16; - unsigned int GAMUT_REMAP_C22 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMUT_REMAP_C23_C24__VI { - struct { - unsigned int GAMUT_REMAP_C23 : 16; - unsigned int GAMUT_REMAP_C24 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMUT_REMAP_C31_C32__VI { - struct { - unsigned int GAMUT_REMAP_C31 : 16; - unsigned int GAMUT_REMAP_C32 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMUT_REMAP_C33_C34__VI { - struct { - unsigned int GAMUT_REMAP_C33 : 16; - unsigned int GAMUT_REMAP_C34 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GAMUT_REMAP_CONTROL__VI { - struct { - unsigned int GRPH_GAMUT_REMAP_MODE : 2; - unsigned int : 2; - unsigned int OVL_GAMUT_REMAP_MODE : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_CP_DMA_ME_COMMAND__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_CP_DMA_PFP_COMMAND__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_CP_DMA_PIO_COMMAND__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_CP_RB0_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_CP_RB1_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_CP_RB2_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_GARLIC_FLUSH_REQ__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_SAM_SAB_RBI_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_SAM_SAB_RBO_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_SDMA0_GFX_RB_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_SDMA1_GFX_RB_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_SDMA2_GFX_RB_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_SDMA3_GFX_RB_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_UVD_RBC_RB_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_VCE_OUT_RB_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_VCE_RB_WPTR__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GARLIC_COHE_VCE_RB_WPTR2__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GCK_ADFS_CLK_BYPASS_CNTL1__VI { - struct { - unsigned int ECLK_BYPASS_CNTL : 3; - unsigned int SCLK_BYPASS_CNTL : 3; - unsigned int LCLK_BYPASS_CNTL : 3; - unsigned int DCLK_BYPASS_CNTL : 3; - unsigned int VCLK_BYPASS_CNTL : 3; - unsigned int DISPCLK_BYPASS_CNTL : 3; - unsigned int DRREFCLK_BYPASS_CNTL : 3; - unsigned int ACLK_BYPASS_CNTL : 3; - unsigned int SAMCLK_BYPASS_CNTL : 3; - unsigned int ACLK_DIV_BYPASS_CNTL : 3; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GCK_DFS_BYPASS_CNTL__VI { - struct { - unsigned int BYPASSECLK : 1; - unsigned int BYPASSLCLK : 1; - unsigned int BYPASSEVCLK : 1; - unsigned int BYPASSDCLK : 1; - unsigned int BYPASSVCLK : 1; - unsigned int BYPASSDISPCLK : 1; - unsigned int BYPASSDPREFCLK : 1; - unsigned int BYPASSACLK : 1; - unsigned int BYPASSADIVCLK : 1; - unsigned int BYPASSPSPCLK : 1; - unsigned int BYPASSSAMCLK : 1; - unsigned int BYPASSSCLK : 1; - unsigned int USE_SPLL_BYPASS_EN : 1; - unsigned int BYPASSMCLK : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GCK_MCLK_FUSES__VI { - struct { - unsigned int StartupMClkDid : 7; - unsigned int MClkADCA : 4; - unsigned int MClkDDCA : 2; - unsigned int MClkDiDtWait : 3; - unsigned int MClkDiDtFloor : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GCK_PLL_TEST_CNTL_2__VI { - struct { - unsigned int : 17; - unsigned int TEST_COUNT : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU0__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU1__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU10__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU11__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU12__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU13__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU14__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU15__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU2__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU3__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU4__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU5__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU6__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU7__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU8__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_ACC_CU9__VI { - struct { - unsigned int ACCUMULATOR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_CGTT_CLK_CTRL__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 18; - unsigned int SOFT_OVERRIDE_DYN : 1; - unsigned int SOFT_OVERRIDE_REG : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_LKG_AGGR_LOWER__VI { - struct { - unsigned int LKG_AGGR_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_LKG_AGGR_UPPER__VI { - struct { - unsigned int LKG_AGGR_63_32 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_OVRD_CU__VI { - struct { - unsigned int OVRRD_SELECT : 16; - unsigned int OVRRD_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_WEIGHT_CU_0__VI { - struct { - unsigned int WEIGHT_CU_SIG0 : 16; - unsigned int WEIGHT_CU_SIG1 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_WEIGHT_CU_1__VI { - struct { - unsigned int WEIGHT_CU_SIG2 : 16; - unsigned int WEIGHT_CU_SIG3 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_WEIGHT_CU_2__VI { - struct { - unsigned int WEIGHT_CU_SIG4 : 16; - unsigned int WEIGHT_CU_SIG5 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_WEIGHT_CU_3__VI { - struct { - unsigned int WEIGHT_CU_SIG6 : 16; - unsigned int WEIGHT_CU_SIG7 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_WEIGHT_CU_4__VI { - struct { - unsigned int WEIGHT_CU_SIG8 : 16; - unsigned int WEIGHT_CU_SIG9 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_WEIGHT_CU_5__VI { - struct { - unsigned int WEIGHT_CU_SIG10 : 16; - unsigned int WEIGHT_CU_SIG11 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_WEIGHT_CU_6__VI { - struct { - unsigned int WEIGHT_CU_SIG12 : 16; - unsigned int WEIGHT_CU_SIG13 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_CAC_WEIGHT_CU_7__VI { - struct { - unsigned int WEIGHT_CU_SIG14 : 16; - unsigned int WEIGHT_CU_SIG15 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GC_USER_SHADER_RATE_CONFIG__VI { - struct { - unsigned int : 1; - unsigned int DPFP_RATE : 2; - unsigned int SQC_BALANCE_DISABLE : 1; - unsigned int HALF_LDS : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_CS_CTXSW_CNT0__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_CS_CTXSW_CNT1__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_CS_CTXSW_CNT2__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_CS_CTXSW_CNT3__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_CS_CTXSW_STATUS__VI { - struct { - unsigned int R : 1; - unsigned int W : 1; - unsigned int UNUSED : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_DSM_CNTL__VI { - struct { - unsigned int SEL_DSM_GDS_IRRITATOR_DATA_A_0 : 1; - unsigned int SEL_DSM_GDS_IRRITATOR_DATA_A_1 : 1; - unsigned int GDS_ENABLE_SINGLE_WRITE_A : 1; - unsigned int SEL_DSM_GDS_IRRITATOR_DATA_B_0 : 1; - unsigned int SEL_DSM_GDS_IRRITATOR_DATA_B_1 : 1; - unsigned int GDS_ENABLE_SINGLE_WRITE_B : 1; - unsigned int UNUSED : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_EDC_CNT__VI { - struct { - unsigned int DED : 8; - unsigned int SED : 8; - unsigned int SEC : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_EDC_GRBM_CNT__VI { - struct { - unsigned int DED : 8; - unsigned int : 8; - unsigned int SEC : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_EDC_OA_DED__VI { - struct { - unsigned int ME0_GFXHP3D_PIX_DED : 1; - unsigned int ME0_GFXHP3D_VTX_DED : 1; - unsigned int ME0_CS_DED : 1; - unsigned int UNUSED0 : 1; - unsigned int ME1_PIPE0_DED : 1; - unsigned int ME1_PIPE1_DED : 1; - unsigned int ME1_PIPE2_DED : 1; - unsigned int ME1_PIPE3_DED : 1; - unsigned int ME2_PIPE0_DED : 1; - unsigned int ME2_PIPE1_DED : 1; - unsigned int ME2_PIPE2_DED : 1; - unsigned int ME2_PIPE3_DED : 1; - unsigned int UNUSED1 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_GFX_CTXSW_STATUS__VI { - struct { - unsigned int R : 1; - unsigned int W : 1; - unsigned int UNUSED : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS0_CTXSW_CNT0__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS0_CTXSW_CNT1__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS0_CTXSW_CNT2__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS0_CTXSW_CNT3__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS1_CTXSW_CNT0__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS1_CTXSW_CNT1__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS1_CTXSW_CNT2__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS1_CTXSW_CNT3__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS2_CTXSW_CNT0__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS2_CTXSW_CNT1__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS2_CTXSW_CNT2__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS2_CTXSW_CNT3__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS3_CTXSW_CNT0__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS3_CTXSW_CNT1__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS3_CTXSW_CNT2__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS3_CTXSW_CNT3__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS4_CTXSW_CNT0__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS4_CTXSW_CNT1__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS4_CTXSW_CNT2__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS4_CTXSW_CNT3__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS5_CTXSW_CNT0__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS5_CTXSW_CNT1__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS5_CTXSW_CNT2__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS5_CTXSW_CNT3__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS6_CTXSW_CNT0__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS6_CTXSW_CNT1__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS6_CTXSW_CNT2__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS6_CTXSW_CNT3__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS7_CTXSW_CNT0__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS7_CTXSW_CNT1__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS7_CTXSW_CNT2__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_PS7_CTXSW_CNT3__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VS_CTXSW_CNT0__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VS_CTXSW_CNT1__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VS_CTXSW_CNT2__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GDS_VS_CTXSW_CNT3__VI { - struct { - unsigned int UPDN : 16; - unsigned int PTR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GMCON_LPT_TARGET__VI { - struct { - unsigned int STCTRL_LPT_TARGET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GPU_BIST_CONTROL__VI { - struct { - unsigned int STOP_ON_FAIL_HW : 1; - unsigned int STOP_ON_FAIL_CU_HARV : 1; - unsigned int CU_HARV_LOOP_COUNT : 4; - unsigned int : 1; - unsigned int RESERVED : 17; - unsigned int GLOBAL_LOOP_COUNT : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_DSM_BYPASS__VI { - struct { - unsigned int BYPASS_BITS : 2; - unsigned int BYPASS_EN : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_HYP_CAM_DATA__VI { - struct { - unsigned int CAM_ADDR : 16; - unsigned int CAM_REMAPADDR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_HYP_CAM_INDEX__VI { - struct { - unsigned int CAM_INDEX : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_TRAP_ADDR__VI { - struct { - unsigned int DATA : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_TRAP_ADDR_MSK__VI { - struct { - unsigned int DATA : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_TRAP_OP__VI { - struct { - unsigned int RW : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_TRAP_WD__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_TRAP_WD_MSK__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRBM_WRITE_ERROR__VI { - struct { - unsigned int WRITE_REQUESTER_RLC : 1; - unsigned int WRITE_REQUESTER_SRBM : 1; - unsigned int WRITE_SSRCID : 3; - unsigned int WRITE_VFID : 4; - unsigned int : 3; - unsigned int WRITE_VF : 1; - unsigned int WRITE_VMID : 4; - unsigned int : 3; - unsigned int WRITE_PIPEID : 2; - unsigned int WRITE_MEID : 2; - unsigned int : 7; - unsigned int WRITE_ERROR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_FLIP_RATE_CNTL__VI { - struct { - unsigned int GRPH_FLIP_RATE : 3; - unsigned int GRPH_FLIP_RATE_ENABLE : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_STEREOSYNC_FLIP__VI { - struct { - unsigned int GRPH_STEREOSYNC_FLIP_EN : 1; - unsigned int : 7; - unsigned int GRPH_STEREOSYNC_FLIP_MODE : 2; - unsigned int : 6; - unsigned int GRPH_PRIMARY_SURFACE_PENDING : 1; - unsigned int GRPH_SECONDARY_SURFACE_PENDING : 1; - unsigned int : 10; - unsigned int GRPH_STEREOSYNC_SELECT_DISABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI { - struct { - unsigned int GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN : 1; - unsigned int GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE : 1; - unsigned int : 2; - unsigned int GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT : 13; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI { - struct { - unsigned int GRPH_XDMA_CACHE_UNDERFLOW_CNT : 20; - unsigned int : 4; - unsigned int GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS : 1; - unsigned int GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK : 1; - unsigned int GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK : 1; - unsigned int : 1; - unsigned int GRPH_XDMA_CACHE_UNDERFLOW_INT : 1; - unsigned int GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK : 1; - unsigned int GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI { - struct { - unsigned int : 8; - unsigned int GRPH_XDMA_RECOVERY_SURFACE_ADDRESS : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI { - struct { - unsigned int GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union GSKT_CONTROL__VI { - struct { - unsigned int GSKT_TxFifoBypass : 1; - unsigned int GSKT_TxFifoDelay : 1; - unsigned int GSKT_TxFifoDelay2 : 1; - unsigned int GSKT_SpareRegs : 5; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_GENERIC_PACKET_CONTROL0__VI { - struct { - unsigned int HDMI_GENERIC0_SEND : 1; - unsigned int HDMI_GENERIC0_CONT : 1; - unsigned int : 2; - unsigned int HDMI_GENERIC1_SEND : 1; - unsigned int HDMI_GENERIC1_CONT : 1; - unsigned int : 10; - unsigned int HDMI_GENERIC0_LINE : 6; - unsigned int : 2; - unsigned int HDMI_GENERIC1_LINE : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDMI_GENERIC_PACKET_CONTROL1__VI { - struct { - unsigned int HDMI_GENERIC2_SEND : 1; - unsigned int HDMI_GENERIC2_CONT : 1; - unsigned int : 2; - unsigned int HDMI_GENERIC3_SEND : 1; - unsigned int HDMI_GENERIC3_CONT : 1; - unsigned int : 10; - unsigned int HDMI_GENERIC2_LINE : 6; - unsigned int : 2; - unsigned int HDMI_GENERIC3_LINE : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_ADDR_CONFIG__VI { - struct { - unsigned int NUM_PIPES : 3; - unsigned int : 1; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int BANK_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_SHADER_ENGINES : 2; - unsigned int : 2; - unsigned int SHADER_ENGINE_TILE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_GPUS : 3; - unsigned int : 1; - unsigned int MULTI_GPU_TILE_SIZE : 2; - unsigned int : 2; - unsigned int ROW_SIZE : 2; - unsigned int NUM_LOWER_PIPES : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_MEMIO_ADDR__VI { - struct { - unsigned int MEMIO_ADDR_LOWER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_MEMIO_CNTL__VI { - struct { - unsigned int MEMIO_SEND : 1; - unsigned int MEMIO_OP : 1; - unsigned int MEMIO_BE : 4; - unsigned int MEMIO_WR_STROBE : 1; - unsigned int MEMIO_RD_STROBE : 1; - unsigned int MEMIO_ADDR_UPPER : 6; - unsigned int MEMIO_CLR_WR_ERROR : 1; - unsigned int MEMIO_CLR_RD_ERROR : 1; - unsigned int MEMIO_VF : 1; - unsigned int MEMIO_VFID : 4; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_MEMIO_RD_DATA__VI { - struct { - unsigned int MEMIO_RD_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_MEMIO_STATUS__VI { - struct { - unsigned int MEMIO_WR_STATUS : 1; - unsigned int MEMIO_RD_STATUS : 1; - unsigned int MEMIO_WR_ERROR : 1; - unsigned int MEMIO_RD_ERROR : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_MEMIO_WR_DATA__VI { - struct { - unsigned int MEMIO_WR_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_MEM_POWER_LS__VI { - struct { - unsigned int LS_ENABLE : 1; - unsigned int LS_SETUP : 6; - unsigned int LS_HOLD : 6; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_MISC_CNTL__VI { - struct { - unsigned int FLUSH_INVALIDATE_CACHE : 1; - unsigned int VM_ID : 4; - unsigned int OUTSTANDING_WRITE_COUNT_1024 : 1; - unsigned int MULTIPLE_READS : 1; - unsigned int HDP_BIF_RDRET_CREDIT : 4; - unsigned int SIMULTANEOUS_READS_WRITES : 1; - unsigned int NO_SPLIT_ARRAY_LINEAR : 1; - unsigned int MC_RDREQ_CREDIT : 6; - unsigned int READ_CACHE_INVALIDATE : 1; - unsigned int ADDRLIB_LINEAR_BYPASS : 1; - unsigned int FED_ENABLE : 1; - unsigned int LEGACY_TILING_ENABLE : 1; - unsigned int LEGACY_SURFACES_ENABLE : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_NONSURFACE_PREFETCH__VI { - struct { - unsigned int NONSURF_PREFETCH_PRI : 3; - unsigned int NONSURF_PREFETCH_DIR : 3; - unsigned int NONSURF_PREFETCH_NUM : 3; - unsigned int NONSURF_PREFETCH_MAX_Z : 11; - unsigned int : 7; - unsigned int NONSURF_PIPE_CONFIG : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_VF_ENABLE__VI { - struct { - unsigned int VF_EN : 1; - unsigned int : 15; - unsigned int VF_NUM : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HDP_XDP_BARS_ADDR_39_36__VI { - struct { - unsigned int BAR0_ADDR_39_36 : 4; - unsigned int BAR1_ADDR_39_36 : 4; - unsigned int BAR2_ADDR_39_36 : 4; - unsigned int BAR3_ADDR_39_36 : 4; - unsigned int BAR4_ADDR_39_36 : 4; - unsigned int BAR5_ADDR_39_36 : 4; - unsigned int BAR6_ADDR_39_36 : 4; - unsigned int BAR7_ADDR_39_36 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union HW_ROTATION__VI { - struct { - unsigned int GRPH_ROTATION_ANGLE : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_ACTIVE_FCN_ID__VI { - struct { - unsigned int VF_ID : 4; - unsigned int RESERVED : 27; - unsigned int PF_VF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VI { - struct { - unsigned int CG : 1; - unsigned int DC : 1; - unsigned int : 1; - unsigned int SAMMSP : 1; - unsigned int RLC : 1; - unsigned int ROM : 1; - unsigned int SRBM : 1; - unsigned int VMC : 1; - unsigned int UVD : 1; - unsigned int BIF : 1; - unsigned int SDMA0 : 1; - unsigned int SDMA1 : 1; - unsigned int ISP : 1; - unsigned int VCE0 : 1; - unsigned int VCE1 : 1; - unsigned int ATC : 1; - unsigned int XDMA : 1; - unsigned int ACP : 1; - unsigned int SH : 1; - unsigned int SH1 : 1; - unsigned int SH2 : 1; - unsigned int SH3 : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_DEBUG__VI { - struct { - unsigned int RB_FULL_DRAIN_ENABLE : 1; - unsigned int WPTR_OVERFLOW_ENABLE : 1; - unsigned int MC_WR_FIFO_BLOCK_ENABLE : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_DOORBELL_RPTR__VI { - struct { - unsigned int OFFSET : 21; - unsigned int : 7; - unsigned int ENABLE : 1; - unsigned int : 1; - unsigned int CAPTURED : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_DSM_MATCH_DATA_CONTROL__VI { - struct { - unsigned int VALUE : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_DSM_MATCH_FIELD_CONTROL__VI { - struct { - unsigned int SRC_EN : 1; - unsigned int FCNID_EN : 1; - unsigned int TIMESTAMP_EN : 1; - unsigned int RINGID_EN : 1; - unsigned int VMID_EN : 1; - unsigned int PASID_EN : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_DSM_MATCH_VALUE_BIT_31_0__VI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_DSM_MATCH_VALUE_BIT_63_32__VI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_DSM_MATCH_VALUE_BIT_95_64__VI { - struct { - unsigned int VALUE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_LEVEL_INTR_MASK__VI { - struct { - unsigned int MASK : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_RESET_INCOMPLETE_INT_CNTL__VI { - struct { - unsigned int CG : 1; - unsigned int DC : 1; - unsigned int : 1; - unsigned int SAMMSP : 1; - unsigned int RLC : 1; - unsigned int ROM : 1; - unsigned int SRBM : 1; - unsigned int VMC : 1; - unsigned int UVD : 1; - unsigned int BIF : 1; - unsigned int SDMA0 : 1; - unsigned int SDMA1 : 1; - unsigned int ISP : 1; - unsigned int VCE0 : 1; - unsigned int VCE1 : 1; - unsigned int ATC : 1; - unsigned int XDMA : 1; - unsigned int ACP : 1; - unsigned int SH : 1; - unsigned int SH1 : 1; - unsigned int SH2 : 1; - unsigned int SH3 : 1; - unsigned int RESET_ENABLE : 1; - unsigned int : 1; - unsigned int INCOMPLETE_CNT : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VERSION__VI { - struct { - unsigned int VALUE : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VF_ENABLE__VI { - struct { - unsigned int VALUE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VF_RB_BIF_STATUS__VI { - struct { - unsigned int RB_FULL_VF : 16; - unsigned int BIF_INTERRUPT_LINE_VF : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VF_RB_STATUS__VI { - struct { - unsigned int RB_FULL_DRAIN_VF : 16; - unsigned int RB_OVERFLOW_VF : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union IH_VIRT_RESET_REQ__VI { - struct { - unsigned int VF : 16; - unsigned int : 15; - unsigned int PF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C11_C12__VI { - struct { - unsigned int INPUT_CSC_C11 : 16; - unsigned int INPUT_CSC_C12 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C11_C12_A__VI { - struct { - unsigned int INPUT_CSC_C11_A : 16; - unsigned int INPUT_CSC_C12_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C11_C12_B__VI { - struct { - unsigned int INPUT_CSC_C11_B : 16; - unsigned int INPUT_CSC_C12_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C13_C14__VI { - struct { - unsigned int INPUT_CSC_C13 : 16; - unsigned int INPUT_CSC_C14 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C13_C14_A__VI { - struct { - unsigned int INPUT_CSC_C13_A : 16; - unsigned int INPUT_CSC_C14_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C13_C14_B__VI { - struct { - unsigned int INPUT_CSC_C13_B : 16; - unsigned int INPUT_CSC_C14_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C21_C22__VI { - struct { - unsigned int INPUT_CSC_C21 : 16; - unsigned int INPUT_CSC_C22 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C21_C22_A__VI { - struct { - unsigned int INPUT_CSC_C21_A : 16; - unsigned int INPUT_CSC_C22_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C21_C22_B__VI { - struct { - unsigned int INPUT_CSC_C21_B : 16; - unsigned int INPUT_CSC_C22_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C23_C24__VI { - struct { - unsigned int INPUT_CSC_C23 : 16; - unsigned int INPUT_CSC_C24 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C23_C24_A__VI { - struct { - unsigned int INPUT_CSC_C23_A : 16; - unsigned int INPUT_CSC_C24_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C23_C24_B__VI { - struct { - unsigned int INPUT_CSC_C23_B : 16; - unsigned int INPUT_CSC_C24_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C31_C32__VI { - struct { - unsigned int INPUT_CSC_C31 : 16; - unsigned int INPUT_CSC_C32 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C31_C32_A__VI { - struct { - unsigned int INPUT_CSC_C31_A : 16; - unsigned int INPUT_CSC_C32_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C31_C32_B__VI { - struct { - unsigned int INPUT_CSC_C31_B : 16; - unsigned int INPUT_CSC_C32_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C33_C34__VI { - struct { - unsigned int INPUT_CSC_C33 : 16; - unsigned int INPUT_CSC_C34 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C33_C34_A__VI { - struct { - unsigned int INPUT_CSC_C33_A : 16; - unsigned int INPUT_CSC_C34_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_C33_C34_B__VI { - struct { - unsigned int INPUT_CSC_C33_B : 16; - unsigned int INPUT_CSC_C34_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_CSC_CONTROL__VI { - struct { - unsigned int INPUT_CSC_GRPH_MODE : 2; - unsigned int : 2; - unsigned int INPUT_CSC_OVL_MODE : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_GAMMA_CONTROL__VI { - struct { - unsigned int GRPH_INPUT_GAMMA_MODE : 2; - unsigned int : 2; - unsigned int OVL_INPUT_GAMMA_MODE : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union INPUT_STREAM_PAYLOAD_CAPABILITY__VI { - struct { - unsigned int INSTRMPAY : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KEY_CONTROL__VI { - struct { - unsigned int KEY_SELECT : 1; - unsigned int KEY_MODE : 2; - unsigned int : 25; - unsigned int GRPH_OVL_HALF_BLEND : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KEY_RANGE_ALPHA__VI { - struct { - unsigned int KEY_ALPHA_LOW : 16; - unsigned int KEY_ALPHA_HIGH : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KEY_RANGE_BLUE__VI { - struct { - unsigned int KEY_BLUE_LOW : 16; - unsigned int KEY_BLUE_HIGH : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KEY_RANGE_GREEN__VI { - struct { - unsigned int KEY_GREEN_LOW : 16; - unsigned int KEY_GREEN_HIGH : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union KEY_RANGE_RED__VI { - struct { - unsigned int KEY_RED_LOW : 16; - unsigned int KEY_RED_HIGH : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_BLACK_KEYER_B_CB__VI { - struct { - unsigned int : 4; - unsigned int LB_BLACK_KEYER_B_CB : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_BLACK_KEYER_G_Y__VI { - struct { - unsigned int : 4; - unsigned int LB_BLACK_KEYER_G_Y : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_BLACK_KEYER_R_CR__VI { - struct { - unsigned int : 4; - unsigned int LB_BLACK_KEYER_R_CR : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_BUFFER_LEVEL_STATUS__VI { - struct { - unsigned int REQ_FIFO_LEVEL : 6; - unsigned int : 4; - unsigned int REQ_FIFO_FULL_CNTL : 6; - unsigned int DATA_BUFFER_LEVEL : 12; - unsigned int DATA_FIFO_FULL_CNTL : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_BUFFER_STATUS__VI { - struct { - unsigned int LB_BUFFER_EMPTY_MARGIN : 4; - unsigned int LB_BUFFER_EMPTY_STAT : 1; - unsigned int : 3; - unsigned int LB_BUFFER_EMPTY_OCCURRED : 1; - unsigned int : 3; - unsigned int LB_BUFFER_EMPTY_ACK : 1; - unsigned int : 3; - unsigned int LB_BUFFER_FULL_STAT : 1; - unsigned int : 3; - unsigned int LB_BUFFER_FULL_OCCURRED : 1; - unsigned int : 3; - unsigned int LB_BUFFER_FULL_ACK : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_BUFFER_URGENCY_CTRL__VI { - struct { - unsigned int LB_BUFFER_URGENCY_MARK_ON : 12; - unsigned int : 4; - unsigned int LB_BUFFER_URGENCY_MARK_OFF : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_BUFFER_URGENCY_STATUS__VI { - struct { - unsigned int LB_BUFFER_URGENCY_LEVEL : 12; - unsigned int : 4; - unsigned int LB_BUFFER_URGENCY_STAT : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_DATA_FORMAT__VI { - struct { - unsigned int PIXEL_DEPTH : 2; - unsigned int PIXEL_EXPAN_MODE : 1; - unsigned int INTERLEAVE_EN : 1; - unsigned int PIXEL_REDUCE_MODE : 1; - unsigned int DYNAMIC_PIXEL_DEPTH : 1; - unsigned int DITHER_EN : 1; - unsigned int DOWNSCALE_PREFETCH_EN : 1; - unsigned int : 4; - unsigned int PREFETCH : 1; - unsigned int : 11; - unsigned int REQUEST_MODE : 1; - unsigned int : 6; - unsigned int ALPHA_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_DEBUG__VI { - struct { - unsigned int LB_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_DEBUG2__VI { - struct { - unsigned int LB_DEBUG2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_DEBUG3__VI { - struct { - unsigned int LB_DEBUG3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_DESKTOP_HEIGHT__VI { - struct { - unsigned int DESKTOP_HEIGHT : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_INTERRUPT_MASK__VI { - struct { - unsigned int VBLANK_INTERRUPT_MASK : 1; - unsigned int : 3; - unsigned int VLINE_INTERRUPT_MASK : 1; - unsigned int : 3; - unsigned int VLINE2_INTERRUPT_MASK : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_KEYER_COLOR_B_CB__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_B_CB : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_KEYER_COLOR_CTRL__VI { - struct { - unsigned int LB_KEYER_COLOR_EN : 1; - unsigned int : 7; - unsigned int LB_KEYER_COLOR_REP_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_KEYER_COLOR_G_Y__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_G_Y : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_KEYER_COLOR_REP_B_CB__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_REP_B_CB : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_KEYER_COLOR_REP_G_Y__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_REP_G_Y : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_KEYER_COLOR_REP_R_CR__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_REP_R_CR : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_KEYER_COLOR_R_CR__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_R_CR : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_MEMORY_CTRL__VI { - struct { - unsigned int LB_MEMORY_SIZE : 12; - unsigned int : 4; - unsigned int LB_NUM_PARTITIONS : 4; - unsigned int LB_MEMORY_CONFIG : 2; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_MEMORY_SIZE_STATUS__VI { - struct { - unsigned int LB_MEMORY_SIZE_STATUS : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_NO_OUTSTANDING_REQ_STATUS__VI { - struct { - unsigned int LB_NO_OUTSTANDING_REQ_STAT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_SNAPSHOT_V_COUNTER__VI { - struct { - unsigned int SNAPSHOT_V_COUNTER : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_SNAPSHOT_V_COUNTER_CHROMA__VI { - struct { - unsigned int SNAPSHOT_V_COUNTER_CHROMA : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_SYNC_RESET_SEL__VI { - struct { - unsigned int LB_SYNC_RESET_SEL : 2; - unsigned int : 2; - unsigned int LB_SYNC_RESET_SEL2 : 1; - unsigned int : 3; - unsigned int LB_SYNC_RESET_DELAY : 8; - unsigned int : 6; - unsigned int LB_SYNC_DURATION : 2; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_TEST_DEBUG_DATA__VI { - struct { - unsigned int LB_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_TEST_DEBUG_INDEX__VI { - struct { - unsigned int LB_TEST_DEBUG_INDEX : 8; - unsigned int LB_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_VBLANK_STATUS__VI { - struct { - unsigned int VBLANK_OCCURRED : 1; - unsigned int : 3; - unsigned int VBLANK_ACK : 1; - unsigned int : 7; - unsigned int VBLANK_STAT : 1; - unsigned int : 3; - unsigned int VBLANK_INTERRUPT : 1; - unsigned int VBLANK_INTERRUPT_TYPE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_VLINE2_START_END__VI { - struct { - unsigned int VLINE2_START : 14; - unsigned int : 2; - unsigned int VLINE2_END : 15; - unsigned int VLINE2_INV : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_VLINE2_STATUS__VI { - struct { - unsigned int VLINE2_OCCURRED : 1; - unsigned int : 3; - unsigned int VLINE2_ACK : 1; - unsigned int : 7; - unsigned int VLINE2_STAT : 1; - unsigned int : 3; - unsigned int VLINE2_INTERRUPT : 1; - unsigned int VLINE2_INTERRUPT_TYPE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_VLINE_START_END__VI { - struct { - unsigned int VLINE_START : 14; - unsigned int : 2; - unsigned int VLINE_END : 15; - unsigned int VLINE_INV : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_VLINE_STATUS__VI { - struct { - unsigned int VLINE_OCCURRED : 1; - unsigned int : 3; - unsigned int VLINE_ACK : 1; - unsigned int : 7; - unsigned int VLINE_STAT : 1; - unsigned int : 3; - unsigned int VLINE_INTERRUPT : 1; - unsigned int VLINE_INTERRUPT_TYPE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_V_COUNTER__VI { - struct { - unsigned int V_COUNTER : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LBV_V_COUNTER_CHROMA__VI { - struct { - unsigned int V_COUNTER_CHROMA : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_BLACK_KEYER_B_CB__VI { - struct { - unsigned int : 4; - unsigned int LB_BLACK_KEYER_B_CB : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_BLACK_KEYER_G_Y__VI { - struct { - unsigned int : 4; - unsigned int LB_BLACK_KEYER_G_Y : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_BLACK_KEYER_R_CR__VI { - struct { - unsigned int : 4; - unsigned int LB_BLACK_KEYER_R_CR : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_BUFFER_LEVEL_STATUS__VI { - struct { - unsigned int REQ_FIFO_LEVEL : 6; - unsigned int : 4; - unsigned int REQ_FIFO_FULL_CNTL : 6; - unsigned int DATA_BUFFER_LEVEL : 12; - unsigned int DATA_FIFO_FULL_CNTL : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_BUFFER_STATUS__VI { - struct { - unsigned int LB_BUFFER_EMPTY_MARGIN : 4; - unsigned int LB_BUFFER_EMPTY_STAT : 1; - unsigned int : 3; - unsigned int LB_BUFFER_EMPTY_OCCURRED : 1; - unsigned int : 3; - unsigned int LB_BUFFER_EMPTY_ACK : 1; - unsigned int : 3; - unsigned int LB_BUFFER_FULL_STAT : 1; - unsigned int : 3; - unsigned int LB_BUFFER_FULL_OCCURRED : 1; - unsigned int : 3; - unsigned int LB_BUFFER_FULL_ACK : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_BUFFER_URGENCY_CTRL__VI { - struct { - unsigned int LB_BUFFER_URGENCY_MARK_ON : 12; - unsigned int : 4; - unsigned int LB_BUFFER_URGENCY_MARK_OFF : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_BUFFER_URGENCY_STATUS__VI { - struct { - unsigned int LB_BUFFER_URGENCY_LEVEL : 12; - unsigned int : 4; - unsigned int LB_BUFFER_URGENCY_STAT : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_DATA_FORMAT__VI { - struct { - unsigned int PIXEL_DEPTH : 2; - unsigned int PIXEL_EXPAN_MODE : 1; - unsigned int INTERLEAVE_EN : 1; - unsigned int PIXEL_REDUCE_MODE : 1; - unsigned int DYNAMIC_PIXEL_DEPTH : 1; - unsigned int : 6; - unsigned int PREFETCH : 1; - unsigned int : 11; - unsigned int REQUEST_MODE : 1; - unsigned int : 6; - unsigned int ALPHA_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_DEBUG2__VI { - struct { - unsigned int LB_DEBUG2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_DEBUG3__VI { - struct { - unsigned int LB_DEBUG3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_DESKTOP_HEIGHT__VI { - struct { - unsigned int DESKTOP_HEIGHT : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_INTERRUPT_MASK__VI { - struct { - unsigned int VBLANK_INTERRUPT_MASK : 1; - unsigned int : 3; - unsigned int VLINE_INTERRUPT_MASK : 1; - unsigned int : 3; - unsigned int VLINE2_INTERRUPT_MASK : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_KEYER_COLOR_B_CB__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_B_CB : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_KEYER_COLOR_CTRL__VI { - struct { - unsigned int LB_KEYER_COLOR_EN : 1; - unsigned int : 7; - unsigned int LB_KEYER_COLOR_REP_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_KEYER_COLOR_G_Y__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_G_Y : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_KEYER_COLOR_REP_B_CB__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_REP_B_CB : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_KEYER_COLOR_REP_G_Y__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_REP_G_Y : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_KEYER_COLOR_REP_R_CR__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_REP_R_CR : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_KEYER_COLOR_R_CR__VI { - struct { - unsigned int : 4; - unsigned int LB_KEYER_COLOR_R_CR : 12; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_MEMORY_CTRL__VI { - struct { - unsigned int LB_MEMORY_SIZE : 12; - unsigned int : 4; - unsigned int LB_NUM_PARTITIONS : 4; - unsigned int LB_MEMORY_CONFIG : 2; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_MEMORY_SIZE_STATUS__VI { - struct { - unsigned int LB_MEMORY_SIZE_STATUS : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_NO_OUTSTANDING_REQ_STATUS__VI { - struct { - unsigned int LB_NO_OUTSTANDING_REQ_STAT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_SNAPSHOT_V_COUNTER__VI { - struct { - unsigned int SNAPSHOT_V_COUNTER : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_VBLANK_STATUS__VI { - struct { - unsigned int VBLANK_OCCURRED : 1; - unsigned int : 3; - unsigned int VBLANK_ACK : 1; - unsigned int : 7; - unsigned int VBLANK_STAT : 1; - unsigned int : 3; - unsigned int VBLANK_INTERRUPT : 1; - unsigned int VBLANK_INTERRUPT_TYPE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_VLINE2_START_END__VI { - struct { - unsigned int VLINE2_START : 14; - unsigned int : 2; - unsigned int VLINE2_END : 15; - unsigned int VLINE2_INV : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_VLINE2_STATUS__VI { - struct { - unsigned int VLINE2_OCCURRED : 1; - unsigned int : 3; - unsigned int VLINE2_ACK : 1; - unsigned int : 7; - unsigned int VLINE2_STAT : 1; - unsigned int : 3; - unsigned int VLINE2_INTERRUPT : 1; - unsigned int VLINE2_INTERRUPT_TYPE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_VLINE_START_END__VI { - struct { - unsigned int VLINE_START : 14; - unsigned int : 2; - unsigned int VLINE_END : 15; - unsigned int VLINE_INV : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_VLINE_STATUS__VI { - struct { - unsigned int VLINE_OCCURRED : 1; - unsigned int : 3; - unsigned int VLINE_ACK : 1; - unsigned int : 7; - unsigned int VLINE_STAT : 1; - unsigned int : 3; - unsigned int VLINE_INTERRUPT : 1; - unsigned int VLINE_INTERRUPT_TYPE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LB_V_COUNTER__VI { - struct { - unsigned int V_COUNTER : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC6_CNTL__VI { - struct { - unsigned int MC6_ENABLE : 1; - unsigned int MC6_THRESHOLD : 16; - unsigned int MC6_BLOCK_ID : 5; - unsigned int MC6_SIGNAL_ID : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC6_OVR_SEL__VI { - struct { - unsigned int MC6_OVR_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC6_OVR_VAL__VI { - struct { - unsigned int MC6_OVR_VAL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC7_CNTL__VI { - struct { - unsigned int MC7_ENABLE : 1; - unsigned int MC7_THRESHOLD : 16; - unsigned int MC7_BLOCK_ID : 5; - unsigned int MC7_SIGNAL_ID : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC7_OVR_SEL__VI { - struct { - unsigned int MC7_OVR_SEL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LCAC_MC7_OVR_VAL__VI { - struct { - unsigned int MC7_OVR_VAL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_CONTROL__VI { - struct { - unsigned int : 1; - unsigned int LoopbackSelect : 4; - unsigned int PRBSPCIeLbSelect : 1; - unsigned int LoopbackHalfRate : 2; - unsigned int LoopbackFifoPtr : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_LANEENABLE__VI { - struct { - unsigned int LANE_enable : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_PCIERXMUX0__VI { - struct { - unsigned int RXLANE0 : 8; - unsigned int RXLANE1 : 8; - unsigned int RXLANE2 : 8; - unsigned int RXLANE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_PCIERXMUX1__VI { - struct { - unsigned int RXLANE4 : 8; - unsigned int RXLANE5 : 8; - unsigned int RXLANE6 : 8; - unsigned int RXLANE7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_PCIERXMUX2__VI { - struct { - unsigned int RXLANE8 : 8; - unsigned int RXLANE9 : 8; - unsigned int RXLANE10 : 8; - unsigned int RXLANE11 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_PCIERXMUX3__VI { - struct { - unsigned int RXLANE12 : 8; - unsigned int RXLANE13 : 8; - unsigned int RXLANE14 : 8; - unsigned int RXLANE15 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_PCIETXMUX0__VI { - struct { - unsigned int TXLANE0 : 8; - unsigned int TXLANE1 : 8; - unsigned int TXLANE2 : 8; - unsigned int TXLANE3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_PCIETXMUX1__VI { - struct { - unsigned int TXLANE4 : 8; - unsigned int TXLANE5 : 8; - unsigned int TXLANE6 : 8; - unsigned int TXLANE7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_PCIETXMUX2__VI { - struct { - unsigned int TXLANE8 : 8; - unsigned int TXLANE9 : 8; - unsigned int TXLANE10 : 8; - unsigned int TXLANE11 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_PCIETXMUX3__VI { - struct { - unsigned int TXLANE12 : 8; - unsigned int TXLANE13 : 8; - unsigned int TXLANE14 : 8; - unsigned int TXLANE15 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_POWERCONTROL__VI { - struct { - unsigned int LMTxPhyCmd0 : 3; - unsigned int LMRxPhyCmd0 : 3; - unsigned int LMLinkSpeed0 : 2; - unsigned int LMTxPhyCmd1 : 3; - unsigned int LMRxPhyCmd1 : 3; - unsigned int LMLinkSpeed1 : 2; - unsigned int LMTxPhyCmd2 : 3; - unsigned int LMRxPhyCmd2 : 3; - unsigned int LMLinkSpeed2 : 2; - unsigned int LMTxPhyCmd3 : 3; - unsigned int LMRxPhyCmd3 : 3; - unsigned int LMLinkSpeed3 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_POWERCONTROL1__VI { - struct { - unsigned int LMTxEn0 : 1; - unsigned int LMTxClkEn0 : 1; - unsigned int LMTxMargin0 : 3; - unsigned int LMSkipBit0 : 1; - unsigned int LMLaneUnused0 : 1; - unsigned int LMTxMarginEn0 : 1; - unsigned int LMDeemph0 : 1; - unsigned int LMTxEn1 : 1; - unsigned int LMTxClkEn1 : 1; - unsigned int LMTxMargin1 : 3; - unsigned int LMSkipBit1 : 1; - unsigned int LMLaneUnused1 : 1; - unsigned int LMTxMarginEn1 : 1; - unsigned int LMDeemph1 : 1; - unsigned int LMTxEn2 : 1; - unsigned int LMTxClkEn2 : 1; - unsigned int LMTxMargin2 : 3; - unsigned int LMSkipBit2 : 1; - unsigned int LMLaneUnused2 : 1; - unsigned int LMTxMarginEn2 : 1; - unsigned int LMDeemph2 : 1; - unsigned int TxCoeffID0 : 2; - unsigned int TxCoeffID1 : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_POWERCONTROL2__VI { - struct { - unsigned int LMTxEn3 : 1; - unsigned int LMTxClkEn3 : 1; - unsigned int LMTxMargin3 : 3; - unsigned int LMSkipBit3 : 1; - unsigned int LMLaneUnused3 : 1; - unsigned int LMTxMarginEn3 : 1; - unsigned int LMDeemph3 : 1; - unsigned int TxCoeffID2 : 2; - unsigned int TxCoeffID3 : 2; - unsigned int TxCoeff0 : 6; - unsigned int TxCoeff1 : 6; - unsigned int TxCoeff2 : 6; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_POWERCONTROL3__VI { - struct { - unsigned int TxCoeff3 : 6; - unsigned int RxEqCtl0 : 6; - unsigned int RxEqCtl1 : 6; - unsigned int RxEqCtl2 : 6; - unsigned int RxEqCtl3 : 6; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_POWERCONTROL4__VI { - struct { - unsigned int LinkNum0 : 3; - unsigned int LinkNum1 : 3; - unsigned int LinkNum2 : 3; - unsigned int LinkNum3 : 3; - unsigned int LaneNum0 : 4; - unsigned int LaneNum1 : 4; - unsigned int LaneNum2 : 4; - unsigned int LaneNum3 : 4; - unsigned int SpcMode0 : 1; - unsigned int SpcMode1 : 1; - unsigned int SpcMode2 : 1; - unsigned int SpcMode3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LM_PRBSCONTROL__VI { - struct { - unsigned int PRBSPCIeSelect : 16; - unsigned int : 12; - unsigned int LMLaneDegrade0 : 1; - unsigned int LMLaneDegrade1 : 1; - unsigned int LMLaneDegrade2 : 1; - unsigned int LMLaneDegrade3 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LNCNT_QUAN_THRD__VI { - struct { - unsigned int CFG_LNC_BW_QUAN_THRD0 : 3; - unsigned int : 1; - unsigned int CFG_LNC_CMN_QUAN_THRD4 : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LNCNT_WEIGHT__VI { - struct { - unsigned int CFG_LNC_BW_WEIGHT0 : 16; - unsigned int CFG_LNC_CMN_WEIGHT16 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LNC_BW_WACC__VI { - struct { - unsigned int LNC_BW_WACC : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LNC_CMN_WACC__VI { - struct { - unsigned int LNC_CMN_WACC : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LNC_TOTAL_WACC__VI { - struct { - unsigned int LNC_TOTAL_WACC : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union LOW_POWER_TILING_CONTROL__VI { - struct { - unsigned int LOW_POWER_TILING_ENABLE : 1; - unsigned int : 2; - unsigned int LOW_POWER_TILING_MODE : 2; - unsigned int LOW_POWER_TILING_NUM_PIPES : 3; - unsigned int LOW_POWER_TILING_NUM_BANKS : 3; - unsigned int LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE : 1; - unsigned int LOW_POWER_TILING_ROW_SIZE : 3; - unsigned int : 1; - unsigned int LOW_POWER_TILING_ROWS_PER_CHAN : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAILBOX_CONTROL__VI { - struct { - unsigned int TRN_MSG_VALID : 1; - unsigned int TRN_MSG_ACK : 1; - unsigned int RCV_MSG_VALID : 1; - unsigned int RCV_MSG_ACK : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAILBOX_INDEX__VI { - struct { - unsigned int MAILBOX_INDEX : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAILBOX_INT_CNTL__VI { - struct { - unsigned int VALID_INT_EN : 1; - unsigned int ACK_INT_EN : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAILBOX_MSGBUF_RCV_DW0__VI { - struct { - unsigned int MSGBUF_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAILBOX_MSGBUF_RCV_DW1__VI { - struct { - unsigned int MSGBUF_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAILBOX_MSGBUF_RCV_DW2__VI { - struct { - unsigned int MSGBUF_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAILBOX_MSGBUF_RCV_DW3__VI { - struct { - unsigned int MSGBUF_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAILBOX_MSGBUF_TRN_DW0__VI { - struct { - unsigned int MSGBUF_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAILBOX_MSGBUF_TRN_DW1__VI { - struct { - unsigned int MSGBUF_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAILBOX_MSGBUF_TRN_DW2__VI { - struct { - unsigned int MSGBUF_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MAILBOX_MSGBUF_TRN_DW3__VI { - struct { - unsigned int MSGBUF_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_1__VI { - struct { - unsigned int entries_0_0_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_10__VI { - struct { - unsigned int entries_0_3_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_11__VI { - struct { - unsigned int entries_0_3_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_12__VI { - struct { - unsigned int entries_0_3_padding_2 : 8; - unsigned int entries_0_3_padding_1 : 8; - unsigned int entries_0_3_padding_0 : 8; - unsigned int entries_0_3_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_13__VI { - struct { - unsigned int entries_1_0_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_14__VI { - struct { - unsigned int entries_1_0_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_15__VI { - struct { - unsigned int entries_1_0_padding_2 : 8; - unsigned int entries_1_0_padding_1 : 8; - unsigned int entries_1_0_padding_0 : 8; - unsigned int entries_1_0_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_16__VI { - struct { - unsigned int entries_1_1_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_17__VI { - struct { - unsigned int entries_1_1_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_18__VI { - struct { - unsigned int entries_1_1_padding_2 : 8; - unsigned int entries_1_1_padding_1 : 8; - unsigned int entries_1_1_padding_0 : 8; - unsigned int entries_1_1_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_19__VI { - struct { - unsigned int entries_1_2_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_2__VI { - struct { - unsigned int entries_0_0_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_20__VI { - struct { - unsigned int entries_1_2_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_21__VI { - struct { - unsigned int entries_1_2_padding_2 : 8; - unsigned int entries_1_2_padding_1 : 8; - unsigned int entries_1_2_padding_0 : 8; - unsigned int entries_1_2_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_22__VI { - struct { - unsigned int entries_1_3_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_23__VI { - struct { - unsigned int entries_1_3_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_24__VI { - struct { - unsigned int entries_1_3_padding_2 : 8; - unsigned int entries_1_3_padding_1 : 8; - unsigned int entries_1_3_padding_0 : 8; - unsigned int entries_1_3_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_25__VI { - struct { - unsigned int entries_2_0_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_26__VI { - struct { - unsigned int entries_2_0_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_27__VI { - struct { - unsigned int entries_2_0_padding_2 : 8; - unsigned int entries_2_0_padding_1 : 8; - unsigned int entries_2_0_padding_0 : 8; - unsigned int entries_2_0_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_28__VI { - struct { - unsigned int entries_2_1_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_29__VI { - struct { - unsigned int entries_2_1_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_3__VI { - struct { - unsigned int entries_0_0_padding_2 : 8; - unsigned int entries_0_0_padding_1 : 8; - unsigned int entries_0_0_padding_0 : 8; - unsigned int entries_0_0_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_30__VI { - struct { - unsigned int entries_2_1_padding_2 : 8; - unsigned int entries_2_1_padding_1 : 8; - unsigned int entries_2_1_padding_0 : 8; - unsigned int entries_2_1_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_31__VI { - struct { - unsigned int entries_2_2_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_32__VI { - struct { - unsigned int entries_2_2_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_33__VI { - struct { - unsigned int entries_2_2_padding_2 : 8; - unsigned int entries_2_2_padding_1 : 8; - unsigned int entries_2_2_padding_0 : 8; - unsigned int entries_2_2_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_34__VI { - struct { - unsigned int entries_2_3_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_35__VI { - struct { - unsigned int entries_2_3_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_36__VI { - struct { - unsigned int entries_2_3_padding_2 : 8; - unsigned int entries_2_3_padding_1 : 8; - unsigned int entries_2_3_padding_0 : 8; - unsigned int entries_2_3_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_37__VI { - struct { - unsigned int entries_3_0_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_38__VI { - struct { - unsigned int entries_3_0_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_39__VI { - struct { - unsigned int entries_3_0_padding_2 : 8; - unsigned int entries_3_0_padding_1 : 8; - unsigned int entries_3_0_padding_0 : 8; - unsigned int entries_3_0_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_4__VI { - struct { - unsigned int entries_0_1_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_40__VI { - struct { - unsigned int entries_3_1_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_41__VI { - struct { - unsigned int entries_3_1_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_42__VI { - struct { - unsigned int entries_3_1_padding_2 : 8; - unsigned int entries_3_1_padding_1 : 8; - unsigned int entries_3_1_padding_0 : 8; - unsigned int entries_3_1_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_43__VI { - struct { - unsigned int entries_3_2_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_44__VI { - struct { - unsigned int entries_3_2_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_45__VI { - struct { - unsigned int entries_3_2_padding_2 : 8; - unsigned int entries_3_2_padding_1 : 8; - unsigned int entries_3_2_padding_0 : 8; - unsigned int entries_3_2_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_46__VI { - struct { - unsigned int entries_3_3_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_47__VI { - struct { - unsigned int entries_3_3_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_48__VI { - struct { - unsigned int entries_3_3_padding_2 : 8; - unsigned int entries_3_3_padding_1 : 8; - unsigned int entries_3_3_padding_0 : 8; - unsigned int entries_3_3_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_49__VI { - struct { - unsigned int entries_4_0_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_5__VI { - struct { - unsigned int entries_0_1_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_50__VI { - struct { - unsigned int entries_4_0_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_51__VI { - struct { - unsigned int entries_4_0_padding_2 : 8; - unsigned int entries_4_0_padding_1 : 8; - unsigned int entries_4_0_padding_0 : 8; - unsigned int entries_4_0_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_52__VI { - struct { - unsigned int entries_4_1_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_53__VI { - struct { - unsigned int entries_4_1_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_54__VI { - struct { - unsigned int entries_4_1_padding_2 : 8; - unsigned int entries_4_1_padding_1 : 8; - unsigned int entries_4_1_padding_0 : 8; - unsigned int entries_4_1_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_55__VI { - struct { - unsigned int entries_4_2_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_56__VI { - struct { - unsigned int entries_4_2_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_57__VI { - struct { - unsigned int entries_4_2_padding_2 : 8; - unsigned int entries_4_2_padding_1 : 8; - unsigned int entries_4_2_padding_0 : 8; - unsigned int entries_4_2_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_58__VI { - struct { - unsigned int entries_4_3_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_59__VI { - struct { - unsigned int entries_4_3_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_6__VI { - struct { - unsigned int entries_0_1_padding_2 : 8; - unsigned int entries_0_1_padding_1 : 8; - unsigned int entries_0_1_padding_0 : 8; - unsigned int entries_0_1_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_60__VI { - struct { - unsigned int entries_4_3_padding_2 : 8; - unsigned int entries_4_3_padding_1 : 8; - unsigned int entries_4_3_padding_0 : 8; - unsigned int entries_4_3_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_61__VI { - struct { - unsigned int entries_5_0_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_62__VI { - struct { - unsigned int entries_5_0_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_63__VI { - struct { - unsigned int entries_5_0_padding_2 : 8; - unsigned int entries_5_0_padding_1 : 8; - unsigned int entries_5_0_padding_0 : 8; - unsigned int entries_5_0_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_64__VI { - struct { - unsigned int entries_5_1_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_65__VI { - struct { - unsigned int entries_5_1_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_66__VI { - struct { - unsigned int entries_5_1_padding_2 : 8; - unsigned int entries_5_1_padding_1 : 8; - unsigned int entries_5_1_padding_0 : 8; - unsigned int entries_5_1_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_67__VI { - struct { - unsigned int entries_5_2_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_68__VI { - struct { - unsigned int entries_5_2_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_69__VI { - struct { - unsigned int entries_5_2_padding_2 : 8; - unsigned int entries_5_2_padding_1 : 8; - unsigned int entries_5_2_padding_0 : 8; - unsigned int entries_5_2_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_7__VI { - struct { - unsigned int entries_0_2_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_70__VI { - struct { - unsigned int entries_5_3_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_71__VI { - struct { - unsigned int entries_5_3_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_72__VI { - struct { - unsigned int entries_5_3_padding_2 : 8; - unsigned int entries_5_3_padding_1 : 8; - unsigned int entries_5_3_padding_0 : 8; - unsigned int entries_5_3_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_73__VI { - struct { - unsigned int entries_6_0_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_74__VI { - struct { - unsigned int entries_6_0_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_75__VI { - struct { - unsigned int entries_6_0_padding_2 : 8; - unsigned int entries_6_0_padding_1 : 8; - unsigned int entries_6_0_padding_0 : 8; - unsigned int entries_6_0_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_76__VI { - struct { - unsigned int entries_6_1_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_77__VI { - struct { - unsigned int entries_6_1_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_78__VI { - struct { - unsigned int entries_6_1_padding_2 : 8; - unsigned int entries_6_1_padding_1 : 8; - unsigned int entries_6_1_padding_0 : 8; - unsigned int entries_6_1_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_79__VI { - struct { - unsigned int entries_6_2_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_8__VI { - struct { - unsigned int entries_0_2_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_80__VI { - struct { - unsigned int entries_6_2_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_81__VI { - struct { - unsigned int entries_6_2_padding_2 : 8; - unsigned int entries_6_2_padding_1 : 8; - unsigned int entries_6_2_padding_0 : 8; - unsigned int entries_6_2_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_82__VI { - struct { - unsigned int entries_6_3_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_83__VI { - struct { - unsigned int entries_6_3_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_84__VI { - struct { - unsigned int entries_6_3_padding_2 : 8; - unsigned int entries_6_3_padding_1 : 8; - unsigned int entries_6_3_padding_0 : 8; - unsigned int entries_6_3_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_85__VI { - struct { - unsigned int entries_7_0_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_86__VI { - struct { - unsigned int entries_7_0_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_87__VI { - struct { - unsigned int entries_7_0_padding_2 : 8; - unsigned int entries_7_0_padding_1 : 8; - unsigned int entries_7_0_padding_0 : 8; - unsigned int entries_7_0_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_88__VI { - struct { - unsigned int entries_7_1_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_89__VI { - struct { - unsigned int entries_7_1_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_9__VI { - struct { - unsigned int entries_0_2_padding_2 : 8; - unsigned int entries_0_2_padding_1 : 8; - unsigned int entries_0_2_padding_0 : 8; - unsigned int entries_0_2_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_90__VI { - struct { - unsigned int entries_7_1_padding_2 : 8; - unsigned int entries_7_1_padding_1 : 8; - unsigned int entries_7_1_padding_0 : 8; - unsigned int entries_7_1_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_91__VI { - struct { - unsigned int entries_7_2_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_92__VI { - struct { - unsigned int entries_7_2_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_93__VI { - struct { - unsigned int entries_7_2_padding_2 : 8; - unsigned int entries_7_2_padding_1 : 8; - unsigned int entries_7_2_padding_0 : 8; - unsigned int entries_7_2_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_94__VI { - struct { - unsigned int entries_7_3_McArbDramTiming : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_95__VI { - struct { - unsigned int entries_7_3_McArbDramTiming2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCARB_DRAM_TIMING_TABLE_96__VI { - struct { - unsigned int entries_7_3_padding_2 : 8; - unsigned int entries_7_3_padding_1 : 8; - unsigned int entries_7_3_padding_0 : 8; - unsigned int entries_7_3_McArbBurstTime : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_MEM_CONTROL__VI { - struct { - unsigned int MCIFMEM_CACHE_MODE_DIS : 1; - unsigned int : 3; - unsigned int MCIFMEM_CACHE_MODE : 2; - unsigned int : 2; - unsigned int MCIFMEM_CACHE_SIZE : 8; - unsigned int MCIFMEM_CACHE_PIPE : 3; - unsigned int MCIFMEM_CACHE_TYPE : 2; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_VMID__VI { - struct { - unsigned int MCIF_WR_VMID : 4; - unsigned int VIP_WR_VMID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_ARBITRATION_CONTROL__VI { - struct { - unsigned int MCIF_WB_CLIENT_ARBITRATION_SLICE : 2; - unsigned int : 24; - unsigned int MCIF_WB_TIME_PER_PIXEL : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUFMGR_CUR_LINE_R__VI { - struct { - unsigned int MCIF_WB_BUFMGR_CUR_LINE_R : 13; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUFMGR_STATUS__VI { - struct { - unsigned int MCIF_WB_BUFMGR_VCE_INT_STATUS : 1; - unsigned int MCIF_WB_BUFMGR_SW_INT_STATUS : 1; - unsigned int : 2; - unsigned int MCIF_WB_BUFMGR_CUR_BUF : 3; - unsigned int MCIF_WB_BUF_DUALSIZE_STATUS : 1; - unsigned int MCIF_WB_BUFMGR_BUFTAG : 4; - unsigned int MCIF_WB_BUFMGR_CUR_LINE_L : 13; - unsigned int : 3; - unsigned int MCIF_WB_BUFMGR_NEXT_BUF : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUFMGR_SW_CONTROL__VI { - struct { - unsigned int MCIF_WB_BUFMGR_ENABLE : 1; - unsigned int MCIF_WB_BUF_DUALSIZE_REQ : 1; - unsigned int : 2; - unsigned int MCIF_WB_BUFMGR_SW_INT_EN : 1; - unsigned int MCIF_WB_BUFMGR_SW_INT_ACK : 1; - unsigned int MCIF_WB_BUFMGR_SW_SLICE_INT_EN : 1; - unsigned int : 1; - unsigned int MCIF_WB_BUFMGR_SW_LOCK : 4; - unsigned int : 4; - unsigned int MCIF_WB_P_VMID : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUFMGR_VCE_CONTROL__VI { - struct { - unsigned int MCIF_WB_BUFMGR_VCE_LOCK_IGNORE : 1; - unsigned int : 3; - unsigned int MCIF_WB_BUFMGR_VCE_INT_EN : 1; - unsigned int MCIF_WB_BUFMGR_VCE_INT_ACK : 1; - unsigned int MCIF_WB_BUFMGR_VCE_SLICE_INT_EN : 1; - unsigned int : 1; - unsigned int MCIF_WB_BUFMGR_VCE_LOCK : 4; - unsigned int : 4; - unsigned int MCIF_WB_BUFMGR_SLICE_SIZE : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_1_ADDR_C__VI { - struct { - unsigned int MCIF_WB_BUF_1_ADDR_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_1_ADDR_C_OFFSET__VI { - struct { - unsigned int MCIF_WB_BUF_1_ADDR_C_OFFSET : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_1_ADDR_Y__VI { - struct { - unsigned int MCIF_WB_BUF_1_ADDR_Y : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_1_ADDR_Y_OFFSET__VI { - struct { - unsigned int MCIF_WB_BUF_1_ADDR_Y_OFFSET : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_1_STATUS__VI { - struct { - unsigned int MCIF_WB_BUF_1_ACTIVE : 1; - unsigned int MCIF_WB_BUF_1_SW_LOCKED : 1; - unsigned int MCIF_WB_BUF_1_VCE_LOCKED : 1; - unsigned int MCIF_WB_BUF_1_OVERFLOW : 1; - unsigned int MCIF_WB_BUF_1_DISABLE : 1; - unsigned int MCIF_WB_BUF_1_MODE : 3; - unsigned int MCIF_WB_BUF_1_BUFTAG : 4; - unsigned int MCIF_WB_BUF_1_NXT_BUF : 3; - unsigned int MCIF_WB_BUF_1_FIELD : 1; - unsigned int MCIF_WB_BUF_1_CUR_LINE_L : 13; - unsigned int MCIF_WB_BUF_1_LONG_LINE_ERROR : 1; - unsigned int MCIF_WB_BUF_1_SHORT_LINE_ERROR : 1; - unsigned int MCIF_WB_BUF_1_FRAME_LENGTH_ERROR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_1_STATUS2__VI { - struct { - unsigned int MCIF_WB_BUF_1_CUR_LINE_R : 13; - unsigned int MCIF_WB_BUF_1_NEW_CONTENT : 1; - unsigned int MCIF_WB_BUF_1_COLOR_DEPTH : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_2_ADDR_C__VI { - struct { - unsigned int MCIF_WB_BUF_2_ADDR_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_2_ADDR_C_OFFSET__VI { - struct { - unsigned int MCIF_WB_BUF_2_ADDR_C_OFFSET : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_2_ADDR_Y__VI { - struct { - unsigned int MCIF_WB_BUF_2_ADDR_Y : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_2_ADDR_Y_OFFSET__VI { - struct { - unsigned int MCIF_WB_BUF_2_ADDR_Y_OFFSET : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_2_STATUS__VI { - struct { - unsigned int MCIF_WB_BUF_2_ACTIVE : 1; - unsigned int MCIF_WB_BUF_2_SW_LOCKED : 1; - unsigned int MCIF_WB_BUF_2_VCE_LOCKED : 1; - unsigned int MCIF_WB_BUF_2_OVERFLOW : 1; - unsigned int MCIF_WB_BUF_2_DISABLE : 1; - unsigned int MCIF_WB_BUF_2_MODE : 3; - unsigned int MCIF_WB_BUF_2_BUFTAG : 4; - unsigned int MCIF_WB_BUF_2_NXT_BUF : 3; - unsigned int MCIF_WB_BUF_2_FIELD : 1; - unsigned int MCIF_WB_BUF_2_CUR_LINE_L : 13; - unsigned int MCIF_WB_BUF_2_LONG_LINE_ERROR : 1; - unsigned int MCIF_WB_BUF_2_SHORT_LINE_ERROR : 1; - unsigned int MCIF_WB_BUF_2_FRAME_LENGTH_ERROR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_2_STATUS2__VI { - struct { - unsigned int MCIF_WB_BUF_2_CUR_LINE_R : 13; - unsigned int MCIF_WB_BUF_2_NEW_CONTENT : 1; - unsigned int MCIF_WB_BUF_2_COLOR_DEPTH : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_3_ADDR_C__VI { - struct { - unsigned int MCIF_WB_BUF_3_ADDR_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_3_ADDR_C_OFFSET__VI { - struct { - unsigned int MCIF_WB_BUF_3_ADDR_C_OFFSET : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_3_ADDR_Y__VI { - struct { - unsigned int MCIF_WB_BUF_3_ADDR_Y : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_3_ADDR_Y_OFFSET__VI { - struct { - unsigned int MCIF_WB_BUF_3_ADDR_Y_OFFSET : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_3_STATUS__VI { - struct { - unsigned int MCIF_WB_BUF_3_ACTIVE : 1; - unsigned int MCIF_WB_BUF_3_SW_LOCKED : 1; - unsigned int MCIF_WB_BUF_3_VCE_LOCKED : 1; - unsigned int MCIF_WB_BUF_3_OVERFLOW : 1; - unsigned int MCIF_WB_BUF_3_DISABLE : 1; - unsigned int MCIF_WB_BUF_3_MODE : 3; - unsigned int MCIF_WB_BUF_3_BUFTAG : 4; - unsigned int MCIF_WB_BUF_3_NXT_BUF : 3; - unsigned int MCIF_WB_BUF_3_FIELD : 1; - unsigned int MCIF_WB_BUF_3_CUR_LINE_L : 13; - unsigned int MCIF_WB_BUF_3_LONG_LINE_ERROR : 1; - unsigned int MCIF_WB_BUF_3_SHORT_LINE_ERROR : 1; - unsigned int MCIF_WB_BUF_3_FRAME_LENGTH_ERROR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_3_STATUS2__VI { - struct { - unsigned int MCIF_WB_BUF_3_CUR_LINE_R : 13; - unsigned int MCIF_WB_BUF_3_NEW_CONTENT : 1; - unsigned int MCIF_WB_BUF_3_COLOR_DEPTH : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_4_ADDR_C__VI { - struct { - unsigned int MCIF_WB_BUF_4_ADDR_C : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_4_ADDR_C_OFFSET__VI { - struct { - unsigned int MCIF_WB_BUF_4_ADDR_C_OFFSET : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_4_ADDR_Y__VI { - struct { - unsigned int MCIF_WB_BUF_4_ADDR_Y : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_4_ADDR_Y_OFFSET__VI { - struct { - unsigned int MCIF_WB_BUF_4_ADDR_Y_OFFSET : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_4_STATUS__VI { - struct { - unsigned int MCIF_WB_BUF_4_ACTIVE : 1; - unsigned int MCIF_WB_BUF_4_SW_LOCKED : 1; - unsigned int MCIF_WB_BUF_4_VCE_LOCKED : 1; - unsigned int MCIF_WB_BUF_4_OVERFLOW : 1; - unsigned int MCIF_WB_BUF_4_DISABLE : 1; - unsigned int MCIF_WB_BUF_4_MODE : 3; - unsigned int MCIF_WB_BUF_4_BUFTAG : 4; - unsigned int MCIF_WB_BUF_4_NXT_BUF : 3; - unsigned int MCIF_WB_BUF_4_FIELD : 1; - unsigned int MCIF_WB_BUF_4_CUR_LINE_L : 13; - unsigned int MCIF_WB_BUF_4_LONG_LINE_ERROR : 1; - unsigned int MCIF_WB_BUF_4_SHORT_LINE_ERROR : 1; - unsigned int MCIF_WB_BUF_4_FRAME_LENGTH_ERROR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_4_STATUS2__VI { - struct { - unsigned int MCIF_WB_BUF_4_CUR_LINE_R : 13; - unsigned int MCIF_WB_BUF_4_NEW_CONTENT : 1; - unsigned int MCIF_WB_BUF_4_COLOR_DEPTH : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_BUF_PITCH__VI { - struct { - unsigned int : 8; - unsigned int MCIF_WB_BUF_LUMA_PITCH : 8; - unsigned int : 8; - unsigned int MCIF_WB_BUF_CHROMA_PITCH : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_HVVMID_CONTROL__VI { - struct { - unsigned int : 8; - unsigned int MCIF_WB_DEFAULT_VMID : 4; - unsigned int : 4; - unsigned int MCIF_WB_ALLOWED_VMID_MASK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_TEST_DEBUG_DATA__VI { - struct { - unsigned int MCIF_WB_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_TEST_DEBUG_INDEX__VI { - struct { - unsigned int MCIF_WB_TEST_DEBUG_INDEX : 8; - unsigned int MCIF_WB_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MCIF_WB_URGENCY_WATERMARK__VI { - struct { - unsigned int MCIF_WB_CLIENT0_URGENCY_WATERMARK : 16; - unsigned int MCIF_WB_CLIENT1_URGENCY_WATERMARK : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_ATOMIC__VI { - struct { - unsigned int TC_GRP : 3; - unsigned int TC_GRP_EN : 1; - unsigned int SDMA_GRP : 3; - unsigned int SDMA_GRP_EN : 1; - unsigned int OUTSTANDING : 8; - unsigned int ATOMIC_RTN_GRP : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GRUB__VI { - struct { - unsigned int GRUB_WATERMARK : 8; - unsigned int GRUB_WATERMARK_PRI : 8; - unsigned int GRUB_WATERMARK_MED : 8; - unsigned int REG_WR_EN : 2; - unsigned int REG_RD_SEL : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GRUB2__VI { - struct { - unsigned int REALTIME_GRP_RD : 8; - unsigned int REALTIME_GRP_WR : 8; - unsigned int DISP_RD_STALL_EN : 1; - unsigned int ACP_RD_STALL_EN : 1; - unsigned int UVD_RD_STALL_EN : 1; - unsigned int VCE0_RD_STALL_EN : 1; - unsigned int VCE1_RD_STALL_EN : 1; - unsigned int REALTIME_RD_WTS : 1; - unsigned int REALTIME_WR_WTS : 1; - unsigned int URGENT_BY_DISP_STALL : 1; - unsigned int PROMOTE_BY_DMIF_URG : 1; - unsigned int PRIORITY_URGENT_OUTSTANDING_ONLY_RD : 1; - unsigned int PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD : 1; - unsigned int PRIORITY_URGENT_OUTSTANDING_ONLY_WR : 1; - unsigned int PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GRUB_PRIORITY1_RD__VI { - struct { - unsigned int CB0 : 2; - unsigned int CBCMASK0 : 2; - unsigned int CBFMASK0 : 2; - unsigned int DB0 : 2; - unsigned int DBHTILE0 : 2; - unsigned int DBSTEN0 : 2; - unsigned int TC0 : 2; - unsigned int ACPG : 2; - unsigned int ACPO : 2; - unsigned int DMIF : 2; - unsigned int DMIF_EXT0 : 2; - unsigned int DMIF_EXT1 : 2; - unsigned int DMIF_TW : 2; - unsigned int MCIF : 2; - unsigned int RLC : 2; - unsigned int VMC : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GRUB_PRIORITY1_WR__VI { - struct { - unsigned int CB0 : 2; - unsigned int CBCMASK0 : 2; - unsigned int CBFMASK0 : 2; - unsigned int CBIMMED0 : 2; - unsigned int DB0 : 2; - unsigned int DBHTILE0 : 2; - unsigned int DBSTEN0 : 2; - unsigned int TC0 : 2; - unsigned int SH : 2; - unsigned int ACPG : 2; - unsigned int ACPO : 2; - unsigned int MCIF : 2; - unsigned int RLC : 2; - unsigned int SDMA1 : 2; - unsigned int SMU : 2; - unsigned int VCE : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GRUB_PRIORITY2_RD__VI { - struct { - unsigned int SDMA1 : 2; - unsigned int SMU : 2; - unsigned int VCE : 2; - unsigned int : 2; - unsigned int XDMAM : 2; - unsigned int SDMA0 : 2; - unsigned int HDP : 2; - unsigned int UMC : 2; - unsigned int UVD : 2; - unsigned int UVD_EXT0 : 2; - unsigned int UVD_EXT1 : 2; - unsigned int SEM : 2; - unsigned int SAMMSP : 2; - unsigned int VP8 : 2; - unsigned int ISP : 2; - unsigned int RSV2 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GRUB_PRIORITY2_WR__VI { - struct { - unsigned int : 2; - unsigned int SAMMSP : 2; - unsigned int XDMA : 2; - unsigned int XDMAM : 2; - unsigned int SDMA0 : 2; - unsigned int HDP : 2; - unsigned int UMC : 2; - unsigned int UVD : 2; - unsigned int UVD_EXT0 : 2; - unsigned int UVD_EXT1 : 2; - unsigned int XDP : 2; - unsigned int SEM : 2; - unsigned int IH : 2; - unsigned int VP8 : 2; - unsigned int ISP : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GRUB_PROMOTE__VI { - struct { - unsigned int URGENT_RD : 8; - unsigned int URGENT_WR : 8; - unsigned int PROMOTE_RD : 8; - unsigned int PROMOTE_WR : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GRUB_REALTIME_RD__VI { - struct { - unsigned int CB0 : 1; - unsigned int CBCMASK0 : 1; - unsigned int CBFMASK0 : 1; - unsigned int DB0 : 1; - unsigned int DBHTILE0 : 1; - unsigned int DBSTEN0 : 1; - unsigned int TC0 : 1; - unsigned int IA : 1; - unsigned int ACPG : 1; - unsigned int ACPO : 1; - unsigned int DMIF : 1; - unsigned int DMIF_EXT0 : 1; - unsigned int DMIF_EXT1 : 1; - unsigned int DMIF_TW : 1; - unsigned int MCIF : 1; - unsigned int RLC : 1; - unsigned int VMC : 1; - unsigned int SDMA1 : 1; - unsigned int SMU : 1; - unsigned int VCE : 1; - unsigned int : 1; - unsigned int XDMAM : 1; - unsigned int SDMA0 : 1; - unsigned int HDP : 1; - unsigned int UMC : 1; - unsigned int UVD : 1; - unsigned int UVD_EXT0 : 1; - unsigned int UVD_EXT1 : 1; - unsigned int SEM : 1; - unsigned int SAMMSP : 1; - unsigned int VP8 : 1; - unsigned int ISP : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_GRUB_REALTIME_WR__VI { - struct { - unsigned int CB0 : 1; - unsigned int CBCMASK0 : 1; - unsigned int CBFMASK0 : 1; - unsigned int CBIMMED0 : 1; - unsigned int DB0 : 1; - unsigned int DBHTILE0 : 1; - unsigned int DBSTEN0 : 1; - unsigned int TC0 : 1; - unsigned int SH : 1; - unsigned int ACPG : 1; - unsigned int ACPO : 1; - unsigned int MCIF : 1; - unsigned int RLC : 1; - unsigned int SDMA1 : 1; - unsigned int SMU : 1; - unsigned int VCE : 1; - unsigned int : 1; - unsigned int SAMMSP : 1; - unsigned int XDMA : 1; - unsigned int XDMAM : 1; - unsigned int SDMA0 : 1; - unsigned int HDP : 1; - unsigned int UMC : 1; - unsigned int UVD : 1; - unsigned int UVD_EXT0 : 1; - unsigned int UVD_EXT1 : 1; - unsigned int XDP : 1; - unsigned int SEM : 1; - unsigned int IH : 1; - unsigned int VP8 : 1; - unsigned int ISP : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_PERF_CID__VI { - struct { - unsigned int CH0 : 8; - unsigned int CH1 : 8; - unsigned int CH0_EN : 1; - unsigned int CH1_EN : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_ARB_SNOOP__VI { - struct { - unsigned int TC_GRP_RD : 3; - unsigned int TC_GRP_RD_EN : 1; - unsigned int TC_GRP_WR : 3; - unsigned int TC_GRP_WR_EN : 1; - unsigned int SDMA_GRP_RD : 3; - unsigned int SDMA_GRP_RD_EN : 1; - unsigned int SDMA_GRP_WR : 3; - unsigned int SDMA_GRP_WR_EN : 1; - unsigned int OUTSTANDING_RD : 8; - unsigned int OUTSTANDING_WR : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_CMD__VI { - struct { - unsigned int : 3; - unsigned int : 1; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 2; - unsigned int : 2; - unsigned int : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_BIST_DAT__VI { - struct { - unsigned int : 4; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int : 12; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_CITF_CREDITS_ARB_RD2__VI { - struct { - unsigned int READ_MED : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_ARB_GARLIC_CNTL__VI { - struct { - unsigned int RX_RDRESP_FIFO_PTR_INIT_VALUE : 8; - unsigned int RX_WRRESP_FIFO_PTR_INIT_VALUE : 7; - unsigned int EN_64_BYTE_WRITE : 1; - unsigned int EDC_RESPONSE_ENABLE : 1; - unsigned int OUTSTANDING_RDRESP_LIMIT : 9; - unsigned int OUTSTANDING_WRRESP_LIMIT : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_ARB_GARLIC_ISOC_PRI__VI { - struct { - unsigned int DMIF_RD_TOKURG_EN : 1; - unsigned int UVD_RD_TOKURG_EN : 1; - unsigned int VCE_RD_TOKURG_EN : 1; - unsigned int ACP_RD_TOKURG_EN : 1; - unsigned int DMIF_RD_PRIURG_EN : 1; - unsigned int UVD_RD_PRIURG_EN : 1; - unsigned int VCE_RD_PRIURG_EN : 1; - unsigned int ACP_RD_PRIURG_EN : 1; - unsigned int DMIF_RD_ISOC_EN : 1; - unsigned int UVD_RD_ISOC_EN : 1; - unsigned int VCE_RD_ISOC_EN : 1; - unsigned int MCIF_RD_ISOC_EN : 1; - unsigned int UMC_RD_ISOC_EN : 1; - unsigned int VCEU_RD_ISOC_EN : 1; - unsigned int ACP_RD_ISOC_EN : 1; - unsigned int REQPRI_OVERRIDE_EN : 1; - unsigned int REQPRI_OVERRIDE_VAL : 2; - unsigned int PRIPRMTE_OVERRIDE_EN : 1; - unsigned int TOKURG_OVERRIDE_EN : 1; - unsigned int PRIURG_OVERRIDE_EN : 1; - unsigned int PRIPRMTE_OVERRIDE_VAL : 1; - unsigned int TOKURG_OVERRIDE_VAL : 1; - unsigned int PRIURG_OVERRIDE_VAL : 1; - unsigned int GARLIC_REQ_CREDITS : 5; - unsigned int MM_REL_LATE : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_ARB_GARLIC_WR_PRI__VI { - struct { - unsigned int CB_WR_PRI : 2; - unsigned int DB_WR_PRI : 2; - unsigned int TC_WR_PRI : 2; - unsigned int CP_WR_PRI : 2; - unsigned int HDP_WR_PRI : 2; - unsigned int XDP_WR_PRI : 2; - unsigned int UMC_WR_PRI : 2; - unsigned int UVD_WR_PRI : 2; - unsigned int RLC_WR_PRI : 2; - unsigned int IH_WR_PRI : 2; - unsigned int SDMA_WR_PRI : 2; - unsigned int SEM_WR_PRI : 2; - unsigned int SH_WR_PRI : 2; - unsigned int MCIF_WR_PRI : 2; - unsigned int VCE_WR_PRI : 2; - unsigned int VCEU_WR_PRI : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_ARB_GARLIC_WR_PRI2__VI { - struct { - unsigned int SMU_WR_PRI : 2; - unsigned int SAM_WR_PRI : 2; - unsigned int ACP_WR_PRI : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM0_BANK_ADDR_MAPPING__VI { - struct { - unsigned int DIMM0ADDRMAP : 4; - unsigned int DIMM1ADDRMAP : 4; - unsigned int BANKSWIZZLEMODE : 1; - unsigned int BANKSWAP : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM0_CS0_BASE__VI { - struct { - unsigned int CSENABLE : 1; - unsigned int : 4; - unsigned int BASEADDR21_11 : 11; - unsigned int : 3; - unsigned int BASEADDR38_27 : 12; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM0_CS1_BASE__VI { - struct { - unsigned int CSENABLE : 1; - unsigned int : 4; - unsigned int BASEADDR21_11 : 11; - unsigned int : 3; - unsigned int BASEADDR38_27 : 12; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM0_CS2_BASE__VI { - struct { - unsigned int CSENABLE : 1; - unsigned int : 4; - unsigned int BASEADDR21_11 : 11; - unsigned int : 3; - unsigned int BASEADDR38_27 : 12; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM0_CS3_BASE__VI { - struct { - unsigned int CSENABLE : 1; - unsigned int : 4; - unsigned int BASEADDR21_11 : 11; - unsigned int : 3; - unsigned int BASEADDR38_27 : 12; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM0_CTL_BASE__VI { - struct { - unsigned int DCTSEL : 3; - unsigned int DCTINTLVEN : 4; - unsigned int DCTBASEADDR : 21; - unsigned int DCTOFFSETEN : 1; - unsigned int : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM0_CTL_LIMIT__VI { - struct { - unsigned int DCTLIMITADDR : 21; - unsigned int DRAMHOLEVALID : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM1_BANK_ADDR_MAPPING__VI { - struct { - unsigned int DIMM0ADDRMAP : 4; - unsigned int DIMM1ADDRMAP : 4; - unsigned int BANKSWIZZLEMODE : 1; - unsigned int BANKSWAP : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM1_CS0_BASE__VI { - struct { - unsigned int CSENABLE : 1; - unsigned int : 4; - unsigned int BASEADDR21_11 : 11; - unsigned int : 3; - unsigned int BASEADDR38_27 : 12; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM1_CS1_BASE__VI { - struct { - unsigned int CSENABLE : 1; - unsigned int : 4; - unsigned int BASEADDR21_11 : 11; - unsigned int : 3; - unsigned int BASEADDR38_27 : 12; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM1_CS2_BASE__VI { - struct { - unsigned int CSENABLE : 1; - unsigned int : 4; - unsigned int BASEADDR21_11 : 11; - unsigned int : 3; - unsigned int BASEADDR38_27 : 12; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM1_CS3_BASE__VI { - struct { - unsigned int CSENABLE : 1; - unsigned int : 4; - unsigned int BASEADDR21_11 : 11; - unsigned int : 3; - unsigned int BASEADDR38_27 : 12; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM1_CTL_BASE__VI { - struct { - unsigned int DCTSEL : 3; - unsigned int DCTINTLVEN : 4; - unsigned int DCTBASEADDR : 21; - unsigned int DCTOFFSETEN : 1; - unsigned int : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM1_CTL_LIMIT__VI { - struct { - unsigned int DCTLIMITADDR : 21; - unsigned int DRAMHOLEVALID : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM_APER_BASE__VI { - struct { - unsigned int BASE : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM_APER_DEF__VI { - struct { - unsigned int DEF : 28; - unsigned int LOCK_MC_FUS_DRAM_REGS : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM_APER_TOP__VI { - struct { - unsigned int TOP : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM_CTL_HIGH_01__VI { - struct { - unsigned int DCTHIGHADDROFF0 : 12; - unsigned int DCTHIGHADDROFF1 : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM_CTL_HIGH_23__VI { - struct { - unsigned int DCTHIGHADDROFF2 : 12; - unsigned int DCTHIGHADDROFF3 : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_FUS_DRAM_MODE__VI { - struct { - unsigned int DCTSELINTLVADDR : 3; - unsigned int DRAMTYPE : 3; - unsigned int DRAMHOLEOFFSET : 9; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_FEATURES__VI { - struct { - unsigned int WR_COMBINE_OFF : 1; - unsigned int SCLK_CG_DISABLE : 1; - unsigned int PRB_FILTER_DISABLE : 1; - unsigned int ARB_NRT_STACK_DISABLE : 1; - unsigned int ARB_FIXED_PRIORITY : 1; - unsigned int PRIORITY_UPDATE_DISABLE : 1; - unsigned int RT_BYPASS_OFF : 1; - unsigned int SYNC_ON_ERROR_DISABLE : 1; - unsigned int SYNC_REFLECT_DISABLE : 1; - unsigned int : 1; - unsigned int ARB_STALL_EN : 1; - unsigned int CREDIT_STALL_EN : 1; - unsigned int ARB_STALL_SET_SEL : 2; - unsigned int ARB_STALL_CLR_SEL : 2; - unsigned int CREDIT_STALL_SET_SEL : 2; - unsigned int CREDIT_STALL_CLR_SEL : 2; - unsigned int WR_REORDER_OFF : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_PERFCOUNTER0_CFG__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_PERFCOUNTER1_CFG__VI { - struct { - unsigned int PERF_SEL : 8; - unsigned int PERF_SEL_END : 8; - unsigned int : 8; - unsigned int PERF_MODE : 4; - unsigned int ENABLE : 1; - unsigned int CLEAR : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_PERFCOUNTER_HI__VI { - struct { - unsigned int COUNTER_HI : 16; - unsigned int COMPARE_VALUE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_PERFCOUNTER_LO__VI { - struct { - unsigned int COUNTER_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_PERFCOUNTER_RSLT_CNTL__VI { - struct { - unsigned int PERF_COUNTER_SELECT : 4; - unsigned int : 4; - unsigned int START_TRIGGER : 8; - unsigned int STOP_TRIGGER : 8; - unsigned int ENABLE_ANY : 1; - unsigned int CLEAR_ALL : 1; - unsigned int STOP_ALL_ON_SATURATE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_POST_PROBE_DELAY__VI { - struct { - unsigned int REQ_TO_RSP_DELAY : 5; - unsigned int : 3; - unsigned int REQLCL_TO_RET_DELAY : 5; - unsigned int : 3; - unsigned int REQREM_TO_RET_DELAY : 5; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_PROBE_CREDITS__VI { - struct { - unsigned int CREDITS_LIMIT_LO : 6; - unsigned int : 2; - unsigned int CREDITS_LIMIT_HI : 6; - unsigned int : 1; - unsigned int INTPRB_FIFO_LEVEL : 1; - unsigned int INTPRB_TIMEOUT_THRESH : 3; - unsigned int : 1; - unsigned int MEM_TIMEOUT_THRESH : 3; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_PROBE_MAP__VI { - struct { - unsigned int ADDR0_TO_TC_MAP : 2; - unsigned int ADDR1_TO_TC_MAP : 2; - unsigned int ADDR2_TO_TC_MAP : 2; - unsigned int ADDR3_TO_TC_MAP : 2; - unsigned int ADDR0_TO_GRUB_MAP : 1; - unsigned int ADDR1_TO_GRUB_MAP : 1; - unsigned int ADDR2_TO_GRUB_MAP : 1; - unsigned int ADDR3_TO_GRUB_MAP : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_TCB_DATA_HI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_TCB_DATA_LO__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_TCB_INDEX__VI { - struct { - unsigned int INDEX : 7; - unsigned int : 1; - unsigned int TCB0_WR_EN : 1; - unsigned int TCB1_WR_EN : 1; - unsigned int RD_EN : 1; - unsigned int TCB_SEL : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_GRUB_TX_CREDITS__VI { - struct { - unsigned int SRCTAG_LIMIT : 6; - unsigned int : 2; - unsigned int SRCTAG_RT_RESERVE : 4; - unsigned int NPC_RT_RESERVE : 4; - unsigned int NPD_RT_RESERVE : 4; - unsigned int TX_FIFO_DEPTH : 5; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_MISC_ATOMIC_IDLE_STATUS__VI { - struct { - unsigned int OUTSTANDING_GFX_ATOMIC : 1; - unsigned int OUTSTANDING_RLC_ATOMIC : 1; - unsigned int OUTSTANDING_SDMA0_ATOMIC : 1; - unsigned int OUTSTANDING_SDMA1_ATOMIC : 1; - unsigned int OUTSTANDING_DISP_ATOMIC : 1; - unsigned int OUTSTANDING_UVD_ATOMIC : 1; - unsigned int OUTSTANDING_SMU_ATOMIC : 1; - unsigned int OUTSTANDING_HDP_ATOMIC : 1; - unsigned int OUTSTANDING_OTH_ATOMIC : 1; - unsigned int OUTSTANDING_VMC_ATOMIC : 1; - unsigned int OUTSTANDING_VCE_ATOMIC : 1; - unsigned int OUTSTANDING_ACP_ATOMIC : 1; - unsigned int OUTSTANDING_SAMMSP_ATOMIC : 1; - unsigned int OUTSTANDING_XDMA_ATOMIC : 1; - unsigned int OUTSTANDING_ISP_ATOMIC : 1; - unsigned int OUTSTANDING_VP8_ATOMIC : 1; - unsigned int OUTSTANDING_VIN0_READ : 1; - unsigned int OUTSTANDING_VIN0_WRITE : 1; - unsigned int OUTSTANDING_VIN0_ATOMIC : 1; - unsigned int OUTSTANDING_TLS_READ : 1; - unsigned int OUTSTANDING_TLS_WRITE : 1; - unsigned int OUTSTANDING_TLS_ATOMIC : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_BYPASS_GBL0__VI { - struct { - unsigned int ENABLE : 1; - unsigned int CID1 : 8; - unsigned int CID2 : 8; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_ISP_CCPU__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int PRIORITY_DISABLE : 1; - unsigned int STALL_FILTER_ENABLE : 1; - unsigned int STALL_THRESHOLD : 6; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_ISP_MPM__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int PRIORITY_DISABLE : 1; - unsigned int STALL_FILTER_ENABLE : 1; - unsigned int STALL_THRESHOLD : 6; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_ISP_SPM__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int PRIORITY_DISABLE : 1; - unsigned int STALL_FILTER_ENABLE : 1; - unsigned int STALL_THRESHOLD : 6; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDS__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int STALL_THRESHOLD : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDT__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int STALL_THRESHOLD : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDU__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int STALL_THRESHOLD : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_MCDV__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int BUS : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int ASK_CREDITS : 7; - unsigned int DISPLAY_CREDITS : 7; - unsigned int STALL_THRESHOLD : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_SAMMSP__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_TLS__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_VCE0__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int VM_BYPASS : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_VCE1__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int VM_BYPASS : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_VCEU0__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_VCEU1__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_VP8__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_RDREQ_VP8U__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_BP2__VI { - struct { - unsigned int RDRET : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_BYPASS_GBL0__VI { - struct { - unsigned int ENABLE : 1; - unsigned int CID1 : 8; - unsigned int CID2 : 8; - unsigned int HDP_PRIORITY_TIME : 7; - unsigned int OTH_PRIORITY_TIME : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_BYPASS_GBL1__VI { - struct { - unsigned int ENABLE : 1; - unsigned int CID1 : 8; - unsigned int CID2 : 8; - unsigned int HDP_PRIORITY_TIME : 7; - unsigned int OTH_PRIORITY_TIME : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CREDITS2__VI { - struct { - unsigned int STOR0_PRI : 8; - unsigned int STOR1_PRI : 8; - unsigned int VM2 : 8; - unsigned int VM3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CREDITS3__VI { - struct { - unsigned int STOR0_URG : 8; - unsigned int STOR1_URG : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CREDITS_MCDS__VI { - struct { - unsigned int WR_PRI : 7; - unsigned int WR_PRI_STALL_THRESHOLD : 7; - unsigned int WR_URG : 7; - unsigned int WR_URG_STALL_THRESHOLD : 7; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CREDITS_MCDT__VI { - struct { - unsigned int WR_PRI : 7; - unsigned int WR_PRI_STALL_THRESHOLD : 7; - unsigned int WR_URG : 7; - unsigned int WR_URG_STALL_THRESHOLD : 7; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CREDITS_MCDU__VI { - struct { - unsigned int WR_PRI : 7; - unsigned int WR_PRI_STALL_THRESHOLD : 7; - unsigned int WR_URG : 7; - unsigned int WR_URG_STALL_THRESHOLD : 7; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CREDITS_MCDV__VI { - struct { - unsigned int WR_PRI : 7; - unsigned int WR_PRI_STALL_THRESHOLD : 7; - unsigned int WR_URG : 7; - unsigned int WR_URG_STALL_THRESHOLD : 7; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CREDITS_MCDW__VI { - struct { - unsigned int WR_PRI : 7; - unsigned int WR_PRI_STALL_THRESHOLD : 7; - unsigned int WR_URG : 7; - unsigned int WR_URG_STALL_THRESHOLD : 7; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CREDITS_MCDX__VI { - struct { - unsigned int WR_PRI : 7; - unsigned int WR_PRI_STALL_THRESHOLD : 7; - unsigned int WR_URG : 7; - unsigned int WR_URG_STALL_THRESHOLD : 7; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CREDITS_MCDY__VI { - struct { - unsigned int WR_PRI : 7; - unsigned int WR_PRI_STALL_THRESHOLD : 7; - unsigned int WR_URG : 7; - unsigned int WR_URG_STALL_THRESHOLD : 7; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_CREDITS_MCDZ__VI { - struct { - unsigned int WR_PRI : 7; - unsigned int WR_PRI_STALL_THRESHOLD : 7; - unsigned int WR_URG : 7; - unsigned int WR_URG_STALL_THRESHOLD : 7; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_ISP_CCPU__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int PRIORITY_DISABLE : 1; - unsigned int STALL_FILTER_ENABLE : 1; - unsigned int STALL_THRESHOLD : 6; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_ISP_MPM__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int PRIORITY_DISABLE : 1; - unsigned int STALL_FILTER_ENABLE : 1; - unsigned int STALL_THRESHOLD : 6; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_ISP_MPS__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int PRIORITY_DISABLE : 1; - unsigned int STALL_FILTER_ENABLE : 1; - unsigned int STALL_THRESHOLD : 6; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_ISP_SPM__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int PRIORITY_DISABLE : 1; - unsigned int STALL_FILTER_ENABLE : 1; - unsigned int STALL_THRESHOLD : 6; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_MCDS__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 1; - unsigned int MAXBURST : 4; - unsigned int ASK_CREDITS : 6; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_THRESHOLD : 7; - unsigned int ASK_CREDITS_W : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_MCDT__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 1; - unsigned int MAXBURST : 4; - unsigned int ASK_CREDITS : 6; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_THRESHOLD : 7; - unsigned int ASK_CREDITS_W : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_MCDU__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 1; - unsigned int MAXBURST : 4; - unsigned int ASK_CREDITS : 6; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_THRESHOLD : 7; - unsigned int ASK_CREDITS_W : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_MCDV__VI { - struct { - unsigned int ENABLE : 1; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 1; - unsigned int MAXBURST : 4; - unsigned int ASK_CREDITS : 6; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_THRESHOLD : 7; - unsigned int ASK_CREDITS_W : 7; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_SAMMSP__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_VCE0__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int VM_BYPASS : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_VCE1__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int VM_BYPASS : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_VCEU0__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_VCEU1__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_VIN0__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_VP8__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WDP_VP8U__VI { - struct { - unsigned int ENABLE : 1; - unsigned int PRESCALE : 2; - unsigned int BLACKOUT_EXEMPT : 1; - unsigned int STALL_MODE : 2; - unsigned int STALL_OVERRIDE : 1; - unsigned int MAXBURST : 4; - unsigned int LAZY_TIMER : 4; - unsigned int STALL_OVERRIDE_WTM : 1; - unsigned int BYPASS_AVAIL_OVERRIDE : 1; - unsigned int URG_BYPASS_AVAIL_OVERRIDE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WRRET_MCDS__VI { - struct { - unsigned int STALL_MODE : 1; - unsigned int CREDIT_COUNT : 7; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WRRET_MCDT__VI { - struct { - unsigned int STALL_MODE : 1; - unsigned int CREDIT_COUNT : 7; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WRRET_MCDU__VI { - struct { - unsigned int STALL_MODE : 1; - unsigned int CREDIT_COUNT : 7; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_HUB_WRRET_MCDV__VI { - struct { - unsigned int STALL_MODE : 1; - unsigned int CREDIT_COUNT : 7; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_TCI_CNTL__VI { - struct { - unsigned int TCI_ENABLE : 1; - unsigned int TCI_POLICY : 2; - unsigned int TCI_VOL : 1; - unsigned int TCI_VMID : 4; - unsigned int TCI_REQ_CREDITS : 8; - unsigned int TCI_MAX_WRITES : 8; - unsigned int TCI_MAX_READS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_RPB_TCI_CNTL2__VI { - struct { - unsigned int TCI_POLICY : 1; - unsigned int TCI_MTYPE : 2; - unsigned int TCI_SNOOP : 1; - unsigned int TCI_PHYSICAL : 1; - unsigned int TCI_PERF_CNTR_EN : 1; - unsigned int TCI_EXE : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SEQ_IO_RESERVE__VI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SHARED_ACTIVE_FCN_ID__VI { - struct { - unsigned int VFID : 4; - unsigned int : 27; - unsigned int VF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SHARED_CHREMAP2__VI { - struct { - unsigned int CHAN8 : 4; - unsigned int CHAN9 : 4; - unsigned int CHAN10 : 4; - unsigned int CHAN11 : 4; - unsigned int CHAN12 : 4; - unsigned int CHAN13 : 4; - unsigned int CHAN14 : 4; - unsigned int CHAN15 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SHARED_VF_ENABLE__VI { - struct { - unsigned int VF_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_SHARED_VIRT_RESET_REQ__VI { - struct { - unsigned int VF : 16; - unsigned int : 15; - unsigned int PF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF0__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF1__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF10__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF11__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF12__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF13__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF14__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF15__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF2__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF3__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF4__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF5__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF6__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF7__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF8__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_FB_SIZE_OFFSET_VF9__VI { - struct { - unsigned int VF_FB_SIZE : 16; - unsigned int VF_FB_OFFSET : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_BASE_HI_0__VI { - struct { - unsigned int MARC_BASE_HI_0 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_BASE_HI_1__VI { - struct { - unsigned int MARC_BASE_HI_1 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_BASE_HI_2__VI { - struct { - unsigned int MARC_BASE_HI_2 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_BASE_HI_3__VI { - struct { - unsigned int MARC_BASE_HI_3 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_BASE_LO_0__VI { - struct { - unsigned int : 12; - unsigned int MARC_BASE_LO_0 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_BASE_LO_1__VI { - struct { - unsigned int : 12; - unsigned int MARC_BASE_LO_1 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_BASE_LO_2__VI { - struct { - unsigned int : 12; - unsigned int MARC_BASE_LO_2 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_BASE_LO_3__VI { - struct { - unsigned int : 12; - unsigned int MARC_BASE_LO_3 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_CNTL__VI { - struct { - unsigned int ENABLE_ALL_CLIENTS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_LEN_HI_0__VI { - struct { - unsigned int MARC_LEN_HI_0 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_LEN_HI_1__VI { - struct { - unsigned int MARC_LEN_HI_1 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_LEN_HI_2__VI { - struct { - unsigned int MARC_LEN_HI_2 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_LEN_HI_3__VI { - struct { - unsigned int MARC_LEN_HI_3 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_LEN_LO_0__VI { - struct { - unsigned int : 12; - unsigned int MARC_LEN_LO_0 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_LEN_LO_1__VI { - struct { - unsigned int : 12; - unsigned int MARC_LEN_LO_1 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_LEN_LO_2__VI { - struct { - unsigned int : 12; - unsigned int MARC_LEN_LO_2 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_LEN_LO_3__VI { - struct { - unsigned int : 12; - unsigned int MARC_LEN_LO_3 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_RELOC_HI_0__VI { - struct { - unsigned int MARC_RELOC_HI_0 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_RELOC_HI_1__VI { - struct { - unsigned int MARC_RELOC_HI_1 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_RELOC_HI_2__VI { - struct { - unsigned int MARC_RELOC_HI_2 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_RELOC_HI_3__VI { - struct { - unsigned int MARC_RELOC_HI_3 : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_RELOC_LO_0__VI { - struct { - unsigned int MARC_ENABLE_0 : 1; - unsigned int MARC_READONLY_0 : 1; - unsigned int : 10; - unsigned int MARC_RELOC_LO_0 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_RELOC_LO_1__VI { - struct { - unsigned int MARC_ENABLE_1 : 1; - unsigned int MARC_READONLY_1 : 1; - unsigned int : 10; - unsigned int MARC_RELOC_LO_1 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_RELOC_LO_2__VI { - struct { - unsigned int MARC_ENABLE_2 : 1; - unsigned int MARC_READONLY_2 : 1; - unsigned int : 10; - unsigned int MARC_RELOC_LO_2 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MARC_RELOC_LO_3__VI { - struct { - unsigned int MARC_ENABLE_3 : 1; - unsigned int MARC_READONLY_3 : 1; - unsigned int : 10; - unsigned int MARC_RELOC_LO_3 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLB1_DEBUG__VI { - struct { - unsigned int INVALIDATE_L1_TLB : 1; - unsigned int : 7; - unsigned int SEND_FREE_AT_RTN : 1; - unsigned int EFFECTIVE_L1_TLB_SIZE : 3; - unsigned int EFFECTIVE_L1_QUEUE_SIZE : 3; - unsigned int L1_TLB_DEBUG : 4; - unsigned int L1_TLB_FORCE_MISS : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_CNTL0__VI { - struct { - unsigned int REQ_STREAM_ID : 9; - unsigned int : 3; - unsigned int EN : 1; - unsigned int PREFETCH_DONE : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_CNTL1__VI { - struct { - unsigned int REQ_STREAM_ID : 9; - unsigned int : 3; - unsigned int EN : 1; - unsigned int PREFETCH_DONE : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_CNTL2__VI { - struct { - unsigned int REQ_STREAM_ID : 9; - unsigned int : 3; - unsigned int EN : 1; - unsigned int PREFETCH_DONE : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_CNTL3__VI { - struct { - unsigned int REQ_STREAM_ID : 9; - unsigned int : 3; - unsigned int EN : 1; - unsigned int PREFETCH_DONE : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_CNTL4__VI { - struct { - unsigned int REQ_STREAM_ID : 9; - unsigned int : 3; - unsigned int EN : 1; - unsigned int PREFETCH_DONE : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_CNTL5__VI { - struct { - unsigned int REQ_STREAM_ID : 9; - unsigned int : 3; - unsigned int EN : 1; - unsigned int PREFETCH_DONE : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_CNTL6__VI { - struct { - unsigned int REQ_STREAM_ID : 9; - unsigned int : 3; - unsigned int EN : 1; - unsigned int PREFETCH_DONE : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_CNTL7__VI { - struct { - unsigned int REQ_STREAM_ID : 9; - unsigned int : 3; - unsigned int EN : 1; - unsigned int PREFETCH_DONE : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_CNTL8__VI { - struct { - unsigned int REQ_STREAM_ID : 9; - unsigned int : 3; - unsigned int EN : 1; - unsigned int PREFETCH_DONE : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_END_ADDR0__VI { - struct { - unsigned int END_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_END_ADDR1__VI { - struct { - unsigned int END_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_END_ADDR2__VI { - struct { - unsigned int END_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_END_ADDR3__VI { - struct { - unsigned int END_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_END_ADDR4__VI { - struct { - unsigned int END_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_END_ADDR5__VI { - struct { - unsigned int END_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_END_ADDR6__VI { - struct { - unsigned int END_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_END_ADDR7__VI { - struct { - unsigned int END_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_END_ADDR8__VI { - struct { - unsigned int END_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__VI { - struct { - unsigned int LOGICAL_PAGE_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VI { - struct { - unsigned int PROTECTIONS : 8; - unsigned int : 4; - unsigned int MEMORY_CLIENT_ID : 9; - unsigned int : 3; - unsigned int MEMORY_CLIENT_RW : 1; - unsigned int VMID : 4; - unsigned int ATOMIC : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_START_ADDR0__VI { - struct { - unsigned int START_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_START_ADDR1__VI { - struct { - unsigned int START_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_START_ADDR2__VI { - struct { - unsigned int START_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_START_ADDR3__VI { - struct { - unsigned int START_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_START_ADDR4__VI { - struct { - unsigned int START_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_START_ADDR5__VI { - struct { - unsigned int START_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_START_ADDR6__VI { - struct { - unsigned int START_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_START_ADDR7__VI { - struct { - unsigned int START_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_MB_L1_TLS0_START_ADDR8__VI { - struct { - unsigned int START_ADDR : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_NB_LOWER_TOP_OF_DRAM2__VI { - struct { - unsigned int ENABLE : 1; - unsigned int : 22; - unsigned int LOWER_TOM2 : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_NB_MMIOBASE__VI { - struct { - unsigned int MMIOBASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_NB_MMIOLIMIT__VI { - struct { - unsigned int MMIOLIMIT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_NB_PCI_ARB__VI { - struct { - unsigned int : 3; - unsigned int VGA_HOLE : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_NB_PCI_CTRL__VI { - struct { - unsigned int : 23; - unsigned int MMIOENABLE : 1; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_NB_TOP_OF_DRAM3__VI { - struct { - unsigned int TOM3_LIMIT : 30; - unsigned int : 1; - unsigned int TOM3_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_NB_TOP_OF_DRAM_SLOT1__VI { - struct { - unsigned int : 23; - unsigned int TOP_OF_DRAM : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_VM_NB_UPPER_TOP_OF_DRAM2__VI { - struct { - unsigned int UPPER_TOM2 : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_FIFO_MON_CNTL0__VI { - struct { - unsigned int START_THRESH : 12; - unsigned int STOP_THRESH : 12; - unsigned int START_MODE : 2; - unsigned int STOP_MODE : 2; - unsigned int ALLOW_WRAP : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_FIFO_MON_CNTL1__VI { - struct { - unsigned int THRESH_CNTR_ID : 8; - unsigned int START_TRIG_ID : 8; - unsigned int STOP_TRIG_ID : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_FIFO_MON_CNTL2__VI { - struct { - unsigned int MON0_ID : 8; - unsigned int MON1_ID : 8; - unsigned int MON2_ID : 8; - unsigned int MON3_ID : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_FIFO_MON_MAX_THSH__VI { - struct { - unsigned int MON0 : 8; - unsigned int MON1 : 8; - unsigned int MON2 : 8; - unsigned int MON3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_FIFO_MON_RSLT0__VI { - struct { - unsigned int COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_FIFO_MON_RSLT1__VI { - struct { - unsigned int COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_FIFO_MON_RSLT2__VI { - struct { - unsigned int COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MC_XBAR_FIFO_MON_RSLT3__VI { - struct { - unsigned int COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MILLISECOND_TIME_BASE_DIV__VI { - struct { - unsigned int MILLISECOND_TIME_BASE_DIV : 17; - unsigned int : 3; - unsigned int MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MP_FPS_CNT__VI { - struct { - unsigned int FPS_CNT : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MSI_MASK__VI { - struct { - unsigned int MSI_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MSI_MASK_64__VI { - struct { - unsigned int MSI_MASK_64 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MSI_PENDING__VI { - struct { - unsigned int MSI_PENDING : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MSI_PENDING_64__VI { - struct { - unsigned int MSI_PENDING_64 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union MVP_DEBUG__VI { - struct { - unsigned int MVP_SWAP_LOCK_IN_EN : 1; - unsigned int MVP_FLOW_CONTROL_IN_EN : 1; - unsigned int MVP_SWAP_LOCK_IN_SEL : 1; - unsigned int MVP_FLOW_CONTROL_IN_SEL : 1; - unsigned int MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP : 1; - unsigned int MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP : 1; - unsigned int MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR : 1; - unsigned int MVP_DIS_READ_POINTER_RESET_DELAY : 1; - unsigned int MVP_DEBUG_BITS : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C11_C12__VI { - struct { - unsigned int OUTPUT_CSC_C11 : 16; - unsigned int OUTPUT_CSC_C12 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C11_C12_A__VI { - struct { - unsigned int OUTPUT_CSC_C11_A : 16; - unsigned int OUTPUT_CSC_C12_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C11_C12_B__VI { - struct { - unsigned int OUTPUT_CSC_C11_B : 16; - unsigned int OUTPUT_CSC_C12_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C13_C14__VI { - struct { - unsigned int OUTPUT_CSC_C13 : 16; - unsigned int OUTPUT_CSC_C14 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C13_C14_A__VI { - struct { - unsigned int OUTPUT_CSC_C13_A : 16; - unsigned int OUTPUT_CSC_C14_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C13_C14_B__VI { - struct { - unsigned int OUTPUT_CSC_C13_B : 16; - unsigned int OUTPUT_CSC_C14_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C21_C22__VI { - struct { - unsigned int OUTPUT_CSC_C21 : 16; - unsigned int OUTPUT_CSC_C22 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C21_C22_A__VI { - struct { - unsigned int OUTPUT_CSC_C21_A : 16; - unsigned int OUTPUT_CSC_C22_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C21_C22_B__VI { - struct { - unsigned int OUTPUT_CSC_C21_B : 16; - unsigned int OUTPUT_CSC_C22_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C23_C24__VI { - struct { - unsigned int OUTPUT_CSC_C23 : 16; - unsigned int OUTPUT_CSC_C24 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C23_C24_A__VI { - struct { - unsigned int OUTPUT_CSC_C23_A : 16; - unsigned int OUTPUT_CSC_C24_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C23_C24_B__VI { - struct { - unsigned int OUTPUT_CSC_C23_B : 16; - unsigned int OUTPUT_CSC_C24_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C31_C32__VI { - struct { - unsigned int OUTPUT_CSC_C31 : 16; - unsigned int OUTPUT_CSC_C32 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C31_C32_A__VI { - struct { - unsigned int OUTPUT_CSC_C31_A : 16; - unsigned int OUTPUT_CSC_C32_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C31_C32_B__VI { - struct { - unsigned int OUTPUT_CSC_C31_B : 16; - unsigned int OUTPUT_CSC_C32_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C33_C34__VI { - struct { - unsigned int OUTPUT_CSC_C33 : 16; - unsigned int OUTPUT_CSC_C34 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C33_C34_A__VI { - struct { - unsigned int OUTPUT_CSC_C33_A : 16; - unsigned int OUTPUT_CSC_C34_A : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_C33_C34_B__VI { - struct { - unsigned int OUTPUT_CSC_C33_B : 16; - unsigned int OUTPUT_CSC_C34_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_CSC_CONTROL__VI { - struct { - unsigned int OUTPUT_CSC_GRPH_MODE : 3; - unsigned int : 1; - unsigned int OUTPUT_CSC_OVL_MODE : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__VI { - struct { - unsigned int BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS : 7; - unsigned int BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__VI { - struct { - unsigned int BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__VI { - struct { - unsigned int STREAM_RESET : 1; - unsigned int STREAM_RUN : 1; - unsigned int INTERRUPT_ON_COMPLETION_ENABLE : 1; - unsigned int FIFO_ERROR_INTERRUPT_ENABLE : 1; - unsigned int DESCRIPTOR_ERROR_INTERRUPT_ENABLE : 1; - unsigned int : 11; - unsigned int STRIPE_CONTROL : 2; - unsigned int TRAFFIC_PRIORITY : 1; - unsigned int : 1; - unsigned int STREAM_NUMBER : 4; - unsigned int : 2; - unsigned int BUFFER_COMPLETION_INTERRUPT_STATUS : 1; - unsigned int FIFO_ERROR : 1; - unsigned int DESCRIPTOR_ERROR : 1; - unsigned int FIFO_READY : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__VI { - struct { - unsigned int CYCLIC_BUFFER_LENGTH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__VI { - struct { - unsigned int FIFO_SIZE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_STREAM_DESCRIPTOR_FORMAT__VI { - struct { - unsigned int NUMBER_OF_CHANNELS : 4; - unsigned int BITS_PER_SAMPLE : 3; - unsigned int : 1; - unsigned int SAMPLE_BASE_DIVISOR : 3; - unsigned int SAMPLE_BASE_MULTIPLE : 3; - unsigned int SAMPLE_BASE_RATE : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__VI { - struct { - unsigned int LAST_VALID_INDEX : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__VI { - struct { - unsigned int LINK_POSITION_IN_BUFFER : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__VI { - struct { - unsigned int LINK_POSITION_IN_BUFFER_ALIAS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUTPUT_STREAM_PAYLOAD_CAPABILITY__VI { - struct { - unsigned int OUTSTRMPAY : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUT_CLAMP_CONTROL_B_CB__VI { - struct { - unsigned int OUT_CLAMP_MAX_B_CB : 14; - unsigned int : 2; - unsigned int OUT_CLAMP_MIN_B_CB : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUT_CLAMP_CONTROL_G_Y__VI { - struct { - unsigned int OUT_CLAMP_MAX_G_Y : 14; - unsigned int : 2; - unsigned int OUT_CLAMP_MIN_G_Y : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUT_CLAMP_CONTROL_R_CR__VI { - struct { - unsigned int OUT_CLAMP_MAX_R_CR : 14; - unsigned int : 2; - unsigned int OUT_CLAMP_MIN_R_CR : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OUT_ROUND_CONTROL__VI { - struct { - unsigned int OUT_ROUND_TRUNC_MODE : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_SECONDARY_SURFACE_ADDRESS__VI { - struct { - unsigned int OVL_SECONDARY_DFQ_ENABLE : 1; - unsigned int : 7; - unsigned int OVL_SECONDARY_SURFACE_ADDRESS : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI { - struct { - unsigned int OVL_SECONDARY_SURFACE_ADDRESS_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union OVL_STEREOSYNC_FLIP__VI { - struct { - unsigned int OVL_STEREOSYNC_FLIP_EN : 1; - unsigned int : 7; - unsigned int OVL_STEREOSYNC_FLIP_MODE : 2; - unsigned int : 6; - unsigned int OVL_PRIMARY_SURFACE_PENDING : 1; - unsigned int OVL_SECONDARY_SURFACE_PENDING : 1; - unsigned int : 10; - unsigned int OVL_STEREOSYNC_SELECT_DISABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_BIF_CMD_STATUS__VI { - struct { - unsigned int TXPHYSTATUS_0 : 1; - unsigned int TXPHYSTATUS_1 : 1; - unsigned int TXPHYSTATUS_2 : 1; - unsigned int TXPHYSTATUS_3 : 1; - unsigned int TXPHYSTATUS_4 : 1; - unsigned int TXPHYSTATUS_5 : 1; - unsigned int TXPHYSTATUS_6 : 1; - unsigned int TXPHYSTATUS_7 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int RXPHYSTATUS_0 : 1; - unsigned int RXPHYSTATUS_1 : 1; - unsigned int RXPHYSTATUS_2 : 1; - unsigned int RXPHYSTATUS_3 : 1; - unsigned int RXPHYSTATUS_4 : 1; - unsigned int RXPHYSTATUS_5 : 1; - unsigned int RXPHYSTATUS_6 : 1; - unsigned int RXPHYSTATUS_7 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_CMD_BUS_CTRL__VI { - struct { - unsigned int CMD_BUS_SCHL_MODE : 2; - unsigned int CMD_BUS_STAG_MODE : 2; - unsigned int CMD_BUS_STAG_DIS : 1; - unsigned int CMD_BUS_SCH_REQ_MODE : 2; - unsigned int CMD_BUS_IGNR_PEND_PWR : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_CMD_BUS_GLB_OVRD__VI { - struct { - unsigned int TXMARG_OVRD_EN : 1; - unsigned int DEEMPH_OVRD_EN : 1; - unsigned int PLLFREQ_OVRD_EN : 1; - unsigned int TXMARG : 3; - unsigned int DEEMPH : 1; - unsigned int PLLFREQ : 2; - unsigned int RESPONSEMODE_PIF_OVRD : 1; - unsigned int : 6; - unsigned int CMD_BUS_LANE_DIS_0 : 1; - unsigned int CMD_BUS_LANE_DIS_1 : 1; - unsigned int CMD_BUS_LANE_DIS_2 : 1; - unsigned int CMD_BUS_LANE_DIS_3 : 1; - unsigned int CMD_BUS_LANE_DIS_4 : 1; - unsigned int CMD_BUS_LANE_DIS_5 : 1; - unsigned int CMD_BUS_LANE_DIS_6 : 1; - unsigned int CMD_BUS_LANE_DIS_7 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_CTRL__VI { - struct { - unsigned int PIF_PLL_PWRDN_EN : 1; - unsigned int DTM_FORCE_FREQDIV_X1 : 1; - unsigned int PIF_PLL_HNDSHK_EARLY_ABORT : 1; - unsigned int PIF_PLL_PWRDN_EARLY_EXIT : 1; - unsigned int PHY_RST_PWROK_VDD : 1; - unsigned int : 1; - unsigned int PIF_PLL_STATUS : 2; - unsigned int PIF_PLL_DEGRADE_OFF_VOTE : 1; - unsigned int PIF_PLL_UNUSED_OFF_VOTE : 1; - unsigned int PIF_PLL_DEGRADE_S2_VOTE : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_GLB_OVRD__VI { - struct { - unsigned int RXDETECT_OVERRIDE_VAL_0 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_1 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_2 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_3 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_4 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_5 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_6 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_7 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int RXDETECT_OVERRIDE_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_GLB_OVRD2__VI { - struct { - unsigned int X2_LANE_1_0_OVRD : 1; - unsigned int X2_LANE_3_2_OVRD : 1; - unsigned int X2_LANE_5_4_OVRD : 1; - unsigned int X2_LANE_7_6_OVRD : 1; - unsigned int X2_LANE_9_8_OVRD : 1; - unsigned int X2_LANE_11_10_OVRD : 1; - unsigned int X2_LANE_13_12_OVRD : 1; - unsigned int X2_LANE_15_14_OVRD : 1; - unsigned int X4_LANE_3_0_OVRD : 1; - unsigned int X4_LANE_7_4_OVRD : 1; - unsigned int X4_LANE_11_8_OVRD : 1; - unsigned int X4_LANE_15_12_OVRD : 1; - unsigned int : 4; - unsigned int X8_LANE_7_0_OVRD : 1; - unsigned int X8_LANE_15_8_OVRD : 1; - unsigned int : 2; - unsigned int X16_LANE_15_0_OVRD : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE0_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_0 : 1; - unsigned int FREQDIV_OVRD_EN_0 : 1; - unsigned int LINKSPEED_OVRD_EN_0 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_0 : 1; - unsigned int TXPWR_OVRD_EN_0 : 1; - unsigned int TXPGENABLE_OVRD_EN_0 : 1; - unsigned int RXPWR_OVRD_EN_0 : 1; - unsigned int RXPGENABLE_OVRD_EN_0 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_0 : 1; - unsigned int ENABLEFOM_OVRD_EN_0 : 1; - unsigned int REQUESTFOM_OVRD_EN_0 : 1; - unsigned int RESPONSEMODE_OVRD_EN_0 : 1; - unsigned int REQUESTTRK_OVRD_EN_0 : 1; - unsigned int REQUESTTRN_OVRD_EN_0 : 1; - unsigned int COEFFICIENTID_OVRD_EN_0 : 1; - unsigned int COEFFICIENT_OVRD_EN_0 : 1; - unsigned int CDREN_OVRD_EN_0 : 1; - unsigned int CDREN_OVRD_VAL_0 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE0_OVRD2__VI { - struct { - unsigned int GANGMODE_0 : 3; - unsigned int FREQDIV_0 : 2; - unsigned int LINKSPEED_0 : 2; - unsigned int TWOSYMENABLE_0 : 1; - unsigned int TXPWR_0 : 3; - unsigned int TXPGENABLE_0 : 2; - unsigned int RXPWR_0 : 3; - unsigned int RXPGENABLE_0 : 2; - unsigned int ELECIDLEDETEN_0 : 1; - unsigned int ENABLEFOM_0 : 1; - unsigned int REQUESTFOM_0 : 1; - unsigned int RESPONSEMODE_0 : 1; - unsigned int REQUESTTRK_0 : 1; - unsigned int REQUESTTRN_0 : 1; - unsigned int COEFFICIENTID_0 : 2; - unsigned int COEFFICIENT_0 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE1_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_1 : 1; - unsigned int FREQDIV_OVRD_EN_1 : 1; - unsigned int LINKSPEED_OVRD_EN_1 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_1 : 1; - unsigned int TXPWR_OVRD_EN_1 : 1; - unsigned int TXPGENABLE_OVRD_EN_1 : 1; - unsigned int RXPWR_OVRD_EN_1 : 1; - unsigned int RXPGENABLE_OVRD_EN_1 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_1 : 1; - unsigned int ENABLEFOM_OVRD_EN_1 : 1; - unsigned int REQUESTFOM_OVRD_EN_1 : 1; - unsigned int RESPONSEMODE_OVRD_EN_1 : 1; - unsigned int REQUESTTRK_OVRD_EN_1 : 1; - unsigned int REQUESTTRN_OVRD_EN_1 : 1; - unsigned int COEFFICIENTID_OVRD_EN_1 : 1; - unsigned int COEFFICIENT_OVRD_EN_1 : 1; - unsigned int CDREN_OVRD_EN_1 : 1; - unsigned int CDREN_OVRD_VAL_1 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE1_OVRD2__VI { - struct { - unsigned int GANGMODE_1 : 3; - unsigned int FREQDIV_1 : 2; - unsigned int LINKSPEED_1 : 2; - unsigned int TWOSYMENABLE_1 : 1; - unsigned int TXPWR_1 : 3; - unsigned int TXPGENABLE_1 : 2; - unsigned int RXPWR_1 : 3; - unsigned int RXPGENABLE_1 : 2; - unsigned int ELECIDLEDETEN_1 : 1; - unsigned int ENABLEFOM_1 : 1; - unsigned int REQUESTFOM_1 : 1; - unsigned int RESPONSEMODE_1 : 1; - unsigned int REQUESTTRK_1 : 1; - unsigned int REQUESTTRN_1 : 1; - unsigned int COEFFICIENTID_1 : 2; - unsigned int COEFFICIENT_1 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE2_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_2 : 1; - unsigned int FREQDIV_OVRD_EN_2 : 1; - unsigned int LINKSPEED_OVRD_EN_2 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_2 : 1; - unsigned int TXPWR_OVRD_EN_2 : 1; - unsigned int TXPGENABLE_OVRD_EN_2 : 1; - unsigned int RXPWR_OVRD_EN_2 : 1; - unsigned int RXPGENABLE_OVRD_EN_2 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_2 : 1; - unsigned int ENABLEFOM_OVRD_EN_2 : 1; - unsigned int REQUESTFOM_OVRD_EN_2 : 1; - unsigned int RESPONSEMODE_OVRD_EN_2 : 1; - unsigned int REQUESTTRK_OVRD_EN_2 : 1; - unsigned int REQUESTTRN_OVRD_EN_2 : 1; - unsigned int COEFFICIENTID_OVRD_EN_2 : 1; - unsigned int COEFFICIENT_OVRD_EN_2 : 1; - unsigned int CDREN_OVRD_EN_2 : 1; - unsigned int CDREN_OVRD_VAL_2 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE2_OVRD2__VI { - struct { - unsigned int GANGMODE_2 : 3; - unsigned int FREQDIV_2 : 2; - unsigned int LINKSPEED_2 : 2; - unsigned int TWOSYMENABLE_2 : 1; - unsigned int TXPWR_2 : 3; - unsigned int TXPGENABLE_2 : 2; - unsigned int RXPWR_2 : 3; - unsigned int RXPGENABLE_2 : 2; - unsigned int ELECIDLEDETEN_2 : 1; - unsigned int ENABLEFOM_2 : 1; - unsigned int REQUESTFOM_2 : 1; - unsigned int RESPONSEMODE_2 : 1; - unsigned int REQUESTTRK_2 : 1; - unsigned int REQUESTTRN_2 : 1; - unsigned int COEFFICIENTID_2 : 2; - unsigned int COEFFICIENT_2 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE3_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_3 : 1; - unsigned int FREQDIV_OVRD_EN_3 : 1; - unsigned int LINKSPEED_OVRD_EN_3 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_3 : 1; - unsigned int TXPWR_OVRD_EN_3 : 1; - unsigned int TXPGENABLE_OVRD_EN_3 : 1; - unsigned int RXPWR_OVRD_EN_3 : 1; - unsigned int RXPGENABLE_OVRD_EN_3 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_3 : 1; - unsigned int ENABLEFOM_OVRD_EN_3 : 1; - unsigned int REQUESTFOM_OVRD_EN_3 : 1; - unsigned int RESPONSEMODE_OVRD_EN_3 : 1; - unsigned int REQUESTTRK_OVRD_EN_3 : 1; - unsigned int REQUESTTRN_OVRD_EN_3 : 1; - unsigned int COEFFICIENTID_OVRD_EN_3 : 1; - unsigned int COEFFICIENT_OVRD_EN_3 : 1; - unsigned int CDREN_OVRD_EN_3 : 1; - unsigned int CDREN_OVRD_VAL_3 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE3_OVRD2__VI { - struct { - unsigned int GANGMODE_3 : 3; - unsigned int FREQDIV_3 : 2; - unsigned int LINKSPEED_3 : 2; - unsigned int TWOSYMENABLE_3 : 1; - unsigned int TXPWR_3 : 3; - unsigned int TXPGENABLE_3 : 2; - unsigned int RXPWR_3 : 3; - unsigned int RXPGENABLE_3 : 2; - unsigned int ELECIDLEDETEN_3 : 1; - unsigned int ENABLEFOM_3 : 1; - unsigned int REQUESTFOM_3 : 1; - unsigned int RESPONSEMODE_3 : 1; - unsigned int REQUESTTRK_3 : 1; - unsigned int REQUESTTRN_3 : 1; - unsigned int COEFFICIENTID_3 : 2; - unsigned int COEFFICIENT_3 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE4_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_4 : 1; - unsigned int FREQDIV_OVRD_EN_4 : 1; - unsigned int LINKSPEED_OVRD_EN_4 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_4 : 1; - unsigned int TXPWR_OVRD_EN_4 : 1; - unsigned int TXPGENABLE_OVRD_EN_4 : 1; - unsigned int RXPWR_OVRD_EN_4 : 1; - unsigned int RXPGENABLE_OVRD_EN_4 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_4 : 1; - unsigned int ENABLEFOM_OVRD_EN_4 : 1; - unsigned int REQUESTFOM_OVRD_EN_4 : 1; - unsigned int RESPONSEMODE_OVRD_EN_4 : 1; - unsigned int REQUESTTRK_OVRD_EN_4 : 1; - unsigned int REQUESTTRN_OVRD_EN_4 : 1; - unsigned int COEFFICIENTID_OVRD_EN_4 : 1; - unsigned int COEFFICIENT_OVRD_EN_4 : 1; - unsigned int CDREN_OVRD_EN_4 : 1; - unsigned int CDREN_OVRD_VAL_4 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE4_OVRD2__VI { - struct { - unsigned int GANGMODE_4 : 3; - unsigned int FREQDIV_4 : 2; - unsigned int LINKSPEED_4 : 2; - unsigned int TWOSYMENABLE_4 : 1; - unsigned int TXPWR_4 : 3; - unsigned int TXPGENABLE_4 : 2; - unsigned int RXPWR_4 : 3; - unsigned int RXPGENABLE_4 : 2; - unsigned int ELECIDLEDETEN_4 : 1; - unsigned int ENABLEFOM_4 : 1; - unsigned int REQUESTFOM_4 : 1; - unsigned int RESPONSEMODE_4 : 1; - unsigned int REQUESTTRK_4 : 1; - unsigned int REQUESTTRN_4 : 1; - unsigned int COEFFICIENTID_4 : 2; - unsigned int COEFFICIENT_4 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE5_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_5 : 1; - unsigned int FREQDIV_OVRD_EN_5 : 1; - unsigned int LINKSPEED_OVRD_EN_5 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_5 : 1; - unsigned int TXPWR_OVRD_EN_5 : 1; - unsigned int TXPGENABLE_OVRD_EN_5 : 1; - unsigned int RXPWR_OVRD_EN_5 : 1; - unsigned int RXPGENABLE_OVRD_EN_5 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_5 : 1; - unsigned int ENABLEFOM_OVRD_EN_5 : 1; - unsigned int REQUESTFOM_OVRD_EN_5 : 1; - unsigned int RESPONSEMODE_OVRD_EN_5 : 1; - unsigned int REQUESTTRK_OVRD_EN_5 : 1; - unsigned int REQUESTTRN_OVRD_EN_5 : 1; - unsigned int COEFFICIENTID_OVRD_EN_5 : 1; - unsigned int COEFFICIENT_OVRD_EN_5 : 1; - unsigned int CDREN_OVRD_EN_5 : 1; - unsigned int CDREN_OVRD_VAL_5 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE5_OVRD2__VI { - struct { - unsigned int GANGMODE_5 : 3; - unsigned int FREQDIV_5 : 2; - unsigned int LINKSPEED_5 : 2; - unsigned int TWOSYMENABLE_5 : 1; - unsigned int TXPWR_5 : 3; - unsigned int TXPGENABLE_5 : 2; - unsigned int RXPWR_5 : 3; - unsigned int RXPGENABLE_5 : 2; - unsigned int ELECIDLEDETEN_5 : 1; - unsigned int ENABLEFOM_5 : 1; - unsigned int REQUESTFOM_5 : 1; - unsigned int RESPONSEMODE_5 : 1; - unsigned int REQUESTTRK_5 : 1; - unsigned int REQUESTTRN_5 : 1; - unsigned int COEFFICIENTID_5 : 2; - unsigned int COEFFICIENT_5 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE6_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_6 : 1; - unsigned int FREQDIV_OVRD_EN_6 : 1; - unsigned int LINKSPEED_OVRD_EN_6 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_6 : 1; - unsigned int TXPWR_OVRD_EN_6 : 1; - unsigned int TXPGENABLE_OVRD_EN_6 : 1; - unsigned int RXPWR_OVRD_EN_6 : 1; - unsigned int RXPGENABLE_OVRD_EN_6 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_6 : 1; - unsigned int ENABLEFOM_OVRD_EN_6 : 1; - unsigned int REQUESTFOM_OVRD_EN_6 : 1; - unsigned int RESPONSEMODE_OVRD_EN_6 : 1; - unsigned int REQUESTTRK_OVRD_EN_6 : 1; - unsigned int REQUESTTRN_OVRD_EN_6 : 1; - unsigned int COEFFICIENTID_OVRD_EN_6 : 1; - unsigned int COEFFICIENT_OVRD_EN_6 : 1; - unsigned int CDREN_OVRD_EN_6 : 1; - unsigned int CDREN_OVRD_VAL_6 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE6_OVRD2__VI { - struct { - unsigned int GANGMODE_6 : 3; - unsigned int FREQDIV_6 : 2; - unsigned int LINKSPEED_6 : 2; - unsigned int TWOSYMENABLE_6 : 1; - unsigned int TXPWR_6 : 3; - unsigned int TXPGENABLE_6 : 2; - unsigned int RXPWR_6 : 3; - unsigned int RXPGENABLE_6 : 2; - unsigned int ELECIDLEDETEN_6 : 1; - unsigned int ENABLEFOM_6 : 1; - unsigned int REQUESTFOM_6 : 1; - unsigned int RESPONSEMODE_6 : 1; - unsigned int REQUESTTRK_6 : 1; - unsigned int REQUESTTRN_6 : 1; - unsigned int COEFFICIENTID_6 : 2; - unsigned int COEFFICIENT_6 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE7_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_7 : 1; - unsigned int FREQDIV_OVRD_EN_7 : 1; - unsigned int LINKSPEED_OVRD_EN_7 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_7 : 1; - unsigned int TXPWR_OVRD_EN_7 : 1; - unsigned int TXPGENABLE_OVRD_EN_7 : 1; - unsigned int RXPWR_OVRD_EN_7 : 1; - unsigned int RXPGENABLE_OVRD_EN_7 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_7 : 1; - unsigned int ENABLEFOM_OVRD_EN_7 : 1; - unsigned int REQUESTFOM_OVRD_EN_7 : 1; - unsigned int RESPONSEMODE_OVRD_EN_7 : 1; - unsigned int REQUESTTRK_OVRD_EN_7 : 1; - unsigned int REQUESTTRN_OVRD_EN_7 : 1; - unsigned int COEFFICIENTID_OVRD_EN_7 : 1; - unsigned int COEFFICIENT_OVRD_EN_7 : 1; - unsigned int CDREN_OVRD_EN_7 : 1; - unsigned int CDREN_OVRD_VAL_7 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_LANE7_OVRD2__VI { - struct { - unsigned int GANGMODE_7 : 3; - unsigned int FREQDIV_7 : 2; - unsigned int LINKSPEED_7 : 2; - unsigned int TWOSYMENABLE_7 : 1; - unsigned int TXPWR_7 : 3; - unsigned int TXPGENABLE_7 : 2; - unsigned int RXPWR_7 : 3; - unsigned int RXPGENABLE_7 : 2; - unsigned int ELECIDLEDETEN_7 : 1; - unsigned int ENABLEFOM_7 : 1; - unsigned int REQUESTFOM_7 : 1; - unsigned int RESPONSEMODE_7 : 1; - unsigned int REQUESTTRK_7 : 1; - unsigned int REQUESTTRN_7 : 1; - unsigned int COEFFICIENTID_7 : 2; - unsigned int COEFFICIENT_7 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_RX_CTRL__VI { - struct { - unsigned int RXPWR_IN_S2 : 3; - unsigned int RXPWR_IN_SPDCHNG : 3; - unsigned int RXPWR_IN_OFF : 3; - unsigned int RXPWR_IN_DEGRADE : 3; - unsigned int RXPWR_IN_UNUSED : 3; - unsigned int RXPWR_IN_INIT : 3; - unsigned int RXPWR_IN_PLL_OFF : 3; - unsigned int RXPWR_IN_DEGRADE_MODE : 1; - unsigned int RXPWR_IN_UNUSED_MODE : 1; - unsigned int RXPWR_GATING_IN_L1 : 1; - unsigned int RXPWR_GATING_IN_UNUSED : 1; - unsigned int RX_HLD_EIE_COUNT : 1; - unsigned int RX_EI_DET_IN_PS2_DEGRADE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_RX_CTRL2__VI { - struct { - unsigned int RX_RDY_DASRT_COUNT : 3; - unsigned int RX_STATUS_DASRT_COUNT : 3; - unsigned int RXPHYSTATUS_DELAY : 3; - unsigned int : 7; - unsigned int FORCE_CDREN_IN_L0S : 1; - unsigned int EI_DET_CYCLE_MODE : 2; - unsigned int EI_DET_ON_TIME : 2; - unsigned int EI_DET_OFF_TIME : 3; - unsigned int EI_DET_CYCLE_DIS_IN_PS1 : 1; - unsigned int RX_CDR_XTND_MODE : 2; - unsigned int RX_L0S_TO_L0_DETECT_EI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_STRAP_0__VI { - struct { - unsigned int : 1; - unsigned int STRAP_TX_RDY_XTND_DIS : 1; - unsigned int STRAP_RX_RDY_XTND_DIS : 1; - unsigned int STRAP_TX_STATUS_XTND_DIS : 1; - unsigned int STRAP_RX_STATUS_XTND_DIS : 1; - unsigned int STRAP_FORCE_OWN_MSTR : 1; - unsigned int STRAP_PIF_CDR_EN_MODE : 2; - unsigned int STRAP_RX_EI_FILTER : 2; - unsigned int STRAP_RX_DIS_HLD_EIE_IN_PS1 : 1; - unsigned int STRAP_RX_DIS_HLD_EIE_IN_PS2 : 1; - unsigned int STRAP_PIF_BIT_12 : 1; - unsigned int STRAP_PIF_BIT_13 : 1; - unsigned int STRAP_PIF_BIT_14 : 1; - unsigned int STRAP_PIF_BIT_15 : 1; - unsigned int STRAP_PIF_BIT_16 : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_TX_CTRL__VI { - struct { - unsigned int TXPWR_IN_S2 : 3; - unsigned int TXPWR_IN_SPDCHNG : 3; - unsigned int TXPWR_IN_OFF : 3; - unsigned int TXPWR_IN_DEGRADE : 3; - unsigned int TXPWR_IN_UNUSED : 3; - unsigned int TXPWR_IN_INIT : 3; - unsigned int TXPWR_IN_PLL_OFF : 3; - unsigned int TXPWR_IN_DEGRADE_MODE : 1; - unsigned int TXPWR_IN_UNUSED_MODE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_PIF_TX_CTRL2__VI { - struct { - unsigned int TX_RDY_DASRT_COUNT : 3; - unsigned int TX_STATUS_DASRT_COUNT : 3; - unsigned int TXPHYSTATUS_DELAY : 3; - unsigned int : 7; - unsigned int TX_HIGH_IMP_STAG_MP : 1; - unsigned int TX_HIGH_IMP_STAG_MODE : 2; - unsigned int : 2; - unsigned int TX_FORCE_DATA_VALID : 1; - unsigned int TX_L0_TO_HIZ_DLY : 3; - unsigned int TX_FIFO_INIT_UPCONFIG : 1; - unsigned int TX_HIZ_TO_L0_DLY : 3; - unsigned int TX_LINKSPEED_ACK_IN_S2 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_STRAP_GLB_REG1__VI { - struct { - unsigned int : 1; - unsigned int STRAP_RX_ADAPT_RST_MODE : 2; - unsigned int STRAP_RX_L0_ENTRY_MODE : 2; - unsigned int STRAP_RX_EI_FILTER : 2; - unsigned int STRAP_RX_ADAPT_RST_SUB_ENTRY : 1; - unsigned int STRAP_RX_PS0_RDY_GEN_MODE : 2; - unsigned int STRAP_RX_DLL_RESET_IN_SPDCHG : 1; - unsigned int STRAP_RX_ADAPT_TIME_OUT : 2; - unsigned int : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB0_STRAP_GLB_REG2__VI { - struct { - unsigned int : 2; - unsigned int STRAP_BPHYC_PLL_RAMP_UP_TIME : 3; - unsigned int STRAP_IMPCAL_SETTLE_TIME : 2; - unsigned int STRAP_BG_SETTLE_TIME : 2; - unsigned int STRAP_TX_CMDET_TIME : 2; - unsigned int STRAP_TX_STARTUP_TIME : 2; - unsigned int : 15; - unsigned int STRAP_B_PCB_DIS0 : 1; - unsigned int STRAP_B_PCB_DIS1 : 1; - unsigned int STRAP_B_PCB_DRV_STR : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_BIF_CMD_STATUS__VI { - struct { - unsigned int TXPHYSTATUS_0 : 1; - unsigned int TXPHYSTATUS_1 : 1; - unsigned int TXPHYSTATUS_2 : 1; - unsigned int TXPHYSTATUS_3 : 1; - unsigned int TXPHYSTATUS_4 : 1; - unsigned int TXPHYSTATUS_5 : 1; - unsigned int TXPHYSTATUS_6 : 1; - unsigned int TXPHYSTATUS_7 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int RXPHYSTATUS_0 : 1; - unsigned int RXPHYSTATUS_1 : 1; - unsigned int RXPHYSTATUS_2 : 1; - unsigned int RXPHYSTATUS_3 : 1; - unsigned int RXPHYSTATUS_4 : 1; - unsigned int RXPHYSTATUS_5 : 1; - unsigned int RXPHYSTATUS_6 : 1; - unsigned int RXPHYSTATUS_7 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_CMD_BUS_CTRL__VI { - struct { - unsigned int CMD_BUS_SCHL_MODE : 2; - unsigned int CMD_BUS_STAG_MODE : 2; - unsigned int CMD_BUS_STAG_DIS : 1; - unsigned int CMD_BUS_SCH_REQ_MODE : 2; - unsigned int CMD_BUS_IGNR_PEND_PWR : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_CMD_BUS_GLB_OVRD__VI { - struct { - unsigned int TXMARG_OVRD_EN : 1; - unsigned int DEEMPH_OVRD_EN : 1; - unsigned int PLLFREQ_OVRD_EN : 1; - unsigned int TXMARG : 3; - unsigned int DEEMPH : 1; - unsigned int PLLFREQ : 2; - unsigned int RESPONSEMODE_PIF_OVRD : 1; - unsigned int : 6; - unsigned int CMD_BUS_LANE_DIS_0 : 1; - unsigned int CMD_BUS_LANE_DIS_1 : 1; - unsigned int CMD_BUS_LANE_DIS_2 : 1; - unsigned int CMD_BUS_LANE_DIS_3 : 1; - unsigned int CMD_BUS_LANE_DIS_4 : 1; - unsigned int CMD_BUS_LANE_DIS_5 : 1; - unsigned int CMD_BUS_LANE_DIS_6 : 1; - unsigned int CMD_BUS_LANE_DIS_7 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_CTRL__VI { - struct { - unsigned int PIF_PLL_PWRDN_EN : 1; - unsigned int DTM_FORCE_FREQDIV_X1 : 1; - unsigned int PIF_PLL_HNDSHK_EARLY_ABORT : 1; - unsigned int PIF_PLL_PWRDN_EARLY_EXIT : 1; - unsigned int PHY_RST_PWROK_VDD : 1; - unsigned int : 1; - unsigned int PIF_PLL_STATUS : 2; - unsigned int PIF_PLL_DEGRADE_OFF_VOTE : 1; - unsigned int PIF_PLL_UNUSED_OFF_VOTE : 1; - unsigned int PIF_PLL_DEGRADE_S2_VOTE : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_GLB_OVRD__VI { - struct { - unsigned int RXDETECT_OVERRIDE_VAL_0 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_1 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_2 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_3 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_4 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_5 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_6 : 1; - unsigned int RXDETECT_OVERRIDE_VAL_7 : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int RXDETECT_OVERRIDE_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_GLB_OVRD2__VI { - struct { - unsigned int X2_LANE_1_0_OVRD : 1; - unsigned int X2_LANE_3_2_OVRD : 1; - unsigned int X2_LANE_5_4_OVRD : 1; - unsigned int X2_LANE_7_6_OVRD : 1; - unsigned int X2_LANE_9_8_OVRD : 1; - unsigned int X2_LANE_11_10_OVRD : 1; - unsigned int X2_LANE_13_12_OVRD : 1; - unsigned int X2_LANE_15_14_OVRD : 1; - unsigned int X4_LANE_3_0_OVRD : 1; - unsigned int X4_LANE_7_4_OVRD : 1; - unsigned int X4_LANE_11_8_OVRD : 1; - unsigned int X4_LANE_15_12_OVRD : 1; - unsigned int : 4; - unsigned int X8_LANE_7_0_OVRD : 1; - unsigned int X8_LANE_15_8_OVRD : 1; - unsigned int : 2; - unsigned int X16_LANE_15_0_OVRD : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE0_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_0 : 1; - unsigned int FREQDIV_OVRD_EN_0 : 1; - unsigned int LINKSPEED_OVRD_EN_0 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_0 : 1; - unsigned int TXPWR_OVRD_EN_0 : 1; - unsigned int TXPGENABLE_OVRD_EN_0 : 1; - unsigned int RXPWR_OVRD_EN_0 : 1; - unsigned int RXPGENABLE_OVRD_EN_0 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_0 : 1; - unsigned int ENABLEFOM_OVRD_EN_0 : 1; - unsigned int REQUESTFOM_OVRD_EN_0 : 1; - unsigned int RESPONSEMODE_OVRD_EN_0 : 1; - unsigned int REQUESTTRK_OVRD_EN_0 : 1; - unsigned int REQUESTTRN_OVRD_EN_0 : 1; - unsigned int COEFFICIENTID_OVRD_EN_0 : 1; - unsigned int COEFFICIENT_OVRD_EN_0 : 1; - unsigned int CDREN_OVRD_EN_0 : 1; - unsigned int CDREN_OVRD_VAL_0 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE0_OVRD2__VI { - struct { - unsigned int GANGMODE_0 : 3; - unsigned int FREQDIV_0 : 2; - unsigned int LINKSPEED_0 : 2; - unsigned int TWOSYMENABLE_0 : 1; - unsigned int TXPWR_0 : 3; - unsigned int TXPGENABLE_0 : 2; - unsigned int RXPWR_0 : 3; - unsigned int RXPGENABLE_0 : 2; - unsigned int ELECIDLEDETEN_0 : 1; - unsigned int ENABLEFOM_0 : 1; - unsigned int REQUESTFOM_0 : 1; - unsigned int RESPONSEMODE_0 : 1; - unsigned int REQUESTTRK_0 : 1; - unsigned int REQUESTTRN_0 : 1; - unsigned int COEFFICIENTID_0 : 2; - unsigned int COEFFICIENT_0 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE1_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_1 : 1; - unsigned int FREQDIV_OVRD_EN_1 : 1; - unsigned int LINKSPEED_OVRD_EN_1 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_1 : 1; - unsigned int TXPWR_OVRD_EN_1 : 1; - unsigned int TXPGENABLE_OVRD_EN_1 : 1; - unsigned int RXPWR_OVRD_EN_1 : 1; - unsigned int RXPGENABLE_OVRD_EN_1 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_1 : 1; - unsigned int ENABLEFOM_OVRD_EN_1 : 1; - unsigned int REQUESTFOM_OVRD_EN_1 : 1; - unsigned int RESPONSEMODE_OVRD_EN_1 : 1; - unsigned int REQUESTTRK_OVRD_EN_1 : 1; - unsigned int REQUESTTRN_OVRD_EN_1 : 1; - unsigned int COEFFICIENTID_OVRD_EN_1 : 1; - unsigned int COEFFICIENT_OVRD_EN_1 : 1; - unsigned int CDREN_OVRD_EN_1 : 1; - unsigned int CDREN_OVRD_VAL_1 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE1_OVRD2__VI { - struct { - unsigned int GANGMODE_1 : 3; - unsigned int FREQDIV_1 : 2; - unsigned int LINKSPEED_1 : 2; - unsigned int TWOSYMENABLE_1 : 1; - unsigned int TXPWR_1 : 3; - unsigned int TXPGENABLE_1 : 2; - unsigned int RXPWR_1 : 3; - unsigned int RXPGENABLE_1 : 2; - unsigned int ELECIDLEDETEN_1 : 1; - unsigned int ENABLEFOM_1 : 1; - unsigned int REQUESTFOM_1 : 1; - unsigned int RESPONSEMODE_1 : 1; - unsigned int REQUESTTRK_1 : 1; - unsigned int REQUESTTRN_1 : 1; - unsigned int COEFFICIENTID_1 : 2; - unsigned int COEFFICIENT_1 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE2_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_2 : 1; - unsigned int FREQDIV_OVRD_EN_2 : 1; - unsigned int LINKSPEED_OVRD_EN_2 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_2 : 1; - unsigned int TXPWR_OVRD_EN_2 : 1; - unsigned int TXPGENABLE_OVRD_EN_2 : 1; - unsigned int RXPWR_OVRD_EN_2 : 1; - unsigned int RXPGENABLE_OVRD_EN_2 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_2 : 1; - unsigned int ENABLEFOM_OVRD_EN_2 : 1; - unsigned int REQUESTFOM_OVRD_EN_2 : 1; - unsigned int RESPONSEMODE_OVRD_EN_2 : 1; - unsigned int REQUESTTRK_OVRD_EN_2 : 1; - unsigned int REQUESTTRN_OVRD_EN_2 : 1; - unsigned int COEFFICIENTID_OVRD_EN_2 : 1; - unsigned int COEFFICIENT_OVRD_EN_2 : 1; - unsigned int CDREN_OVRD_EN_2 : 1; - unsigned int CDREN_OVRD_VAL_2 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE2_OVRD2__VI { - struct { - unsigned int GANGMODE_2 : 3; - unsigned int FREQDIV_2 : 2; - unsigned int LINKSPEED_2 : 2; - unsigned int TWOSYMENABLE_2 : 1; - unsigned int TXPWR_2 : 3; - unsigned int TXPGENABLE_2 : 2; - unsigned int RXPWR_2 : 3; - unsigned int RXPGENABLE_2 : 2; - unsigned int ELECIDLEDETEN_2 : 1; - unsigned int ENABLEFOM_2 : 1; - unsigned int REQUESTFOM_2 : 1; - unsigned int RESPONSEMODE_2 : 1; - unsigned int REQUESTTRK_2 : 1; - unsigned int REQUESTTRN_2 : 1; - unsigned int COEFFICIENTID_2 : 2; - unsigned int COEFFICIENT_2 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE3_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_3 : 1; - unsigned int FREQDIV_OVRD_EN_3 : 1; - unsigned int LINKSPEED_OVRD_EN_3 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_3 : 1; - unsigned int TXPWR_OVRD_EN_3 : 1; - unsigned int TXPGENABLE_OVRD_EN_3 : 1; - unsigned int RXPWR_OVRD_EN_3 : 1; - unsigned int RXPGENABLE_OVRD_EN_3 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_3 : 1; - unsigned int ENABLEFOM_OVRD_EN_3 : 1; - unsigned int REQUESTFOM_OVRD_EN_3 : 1; - unsigned int RESPONSEMODE_OVRD_EN_3 : 1; - unsigned int REQUESTTRK_OVRD_EN_3 : 1; - unsigned int REQUESTTRN_OVRD_EN_3 : 1; - unsigned int COEFFICIENTID_OVRD_EN_3 : 1; - unsigned int COEFFICIENT_OVRD_EN_3 : 1; - unsigned int CDREN_OVRD_EN_3 : 1; - unsigned int CDREN_OVRD_VAL_3 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE3_OVRD2__VI { - struct { - unsigned int GANGMODE_3 : 3; - unsigned int FREQDIV_3 : 2; - unsigned int LINKSPEED_3 : 2; - unsigned int TWOSYMENABLE_3 : 1; - unsigned int TXPWR_3 : 3; - unsigned int TXPGENABLE_3 : 2; - unsigned int RXPWR_3 : 3; - unsigned int RXPGENABLE_3 : 2; - unsigned int ELECIDLEDETEN_3 : 1; - unsigned int ENABLEFOM_3 : 1; - unsigned int REQUESTFOM_3 : 1; - unsigned int RESPONSEMODE_3 : 1; - unsigned int REQUESTTRK_3 : 1; - unsigned int REQUESTTRN_3 : 1; - unsigned int COEFFICIENTID_3 : 2; - unsigned int COEFFICIENT_3 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE4_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_4 : 1; - unsigned int FREQDIV_OVRD_EN_4 : 1; - unsigned int LINKSPEED_OVRD_EN_4 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_4 : 1; - unsigned int TXPWR_OVRD_EN_4 : 1; - unsigned int TXPGENABLE_OVRD_EN_4 : 1; - unsigned int RXPWR_OVRD_EN_4 : 1; - unsigned int RXPGENABLE_OVRD_EN_4 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_4 : 1; - unsigned int ENABLEFOM_OVRD_EN_4 : 1; - unsigned int REQUESTFOM_OVRD_EN_4 : 1; - unsigned int RESPONSEMODE_OVRD_EN_4 : 1; - unsigned int REQUESTTRK_OVRD_EN_4 : 1; - unsigned int REQUESTTRN_OVRD_EN_4 : 1; - unsigned int COEFFICIENTID_OVRD_EN_4 : 1; - unsigned int COEFFICIENT_OVRD_EN_4 : 1; - unsigned int CDREN_OVRD_EN_4 : 1; - unsigned int CDREN_OVRD_VAL_4 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE4_OVRD2__VI { - struct { - unsigned int GANGMODE_4 : 3; - unsigned int FREQDIV_4 : 2; - unsigned int LINKSPEED_4 : 2; - unsigned int TWOSYMENABLE_4 : 1; - unsigned int TXPWR_4 : 3; - unsigned int TXPGENABLE_4 : 2; - unsigned int RXPWR_4 : 3; - unsigned int RXPGENABLE_4 : 2; - unsigned int ELECIDLEDETEN_4 : 1; - unsigned int ENABLEFOM_4 : 1; - unsigned int REQUESTFOM_4 : 1; - unsigned int RESPONSEMODE_4 : 1; - unsigned int REQUESTTRK_4 : 1; - unsigned int REQUESTTRN_4 : 1; - unsigned int COEFFICIENTID_4 : 2; - unsigned int COEFFICIENT_4 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE5_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_5 : 1; - unsigned int FREQDIV_OVRD_EN_5 : 1; - unsigned int LINKSPEED_OVRD_EN_5 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_5 : 1; - unsigned int TXPWR_OVRD_EN_5 : 1; - unsigned int TXPGENABLE_OVRD_EN_5 : 1; - unsigned int RXPWR_OVRD_EN_5 : 1; - unsigned int RXPGENABLE_OVRD_EN_5 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_5 : 1; - unsigned int ENABLEFOM_OVRD_EN_5 : 1; - unsigned int REQUESTFOM_OVRD_EN_5 : 1; - unsigned int RESPONSEMODE_OVRD_EN_5 : 1; - unsigned int REQUESTTRK_OVRD_EN_5 : 1; - unsigned int REQUESTTRN_OVRD_EN_5 : 1; - unsigned int COEFFICIENTID_OVRD_EN_5 : 1; - unsigned int COEFFICIENT_OVRD_EN_5 : 1; - unsigned int CDREN_OVRD_EN_5 : 1; - unsigned int CDREN_OVRD_VAL_5 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE5_OVRD2__VI { - struct { - unsigned int GANGMODE_5 : 3; - unsigned int FREQDIV_5 : 2; - unsigned int LINKSPEED_5 : 2; - unsigned int TWOSYMENABLE_5 : 1; - unsigned int TXPWR_5 : 3; - unsigned int TXPGENABLE_5 : 2; - unsigned int RXPWR_5 : 3; - unsigned int RXPGENABLE_5 : 2; - unsigned int ELECIDLEDETEN_5 : 1; - unsigned int ENABLEFOM_5 : 1; - unsigned int REQUESTFOM_5 : 1; - unsigned int RESPONSEMODE_5 : 1; - unsigned int REQUESTTRK_5 : 1; - unsigned int REQUESTTRN_5 : 1; - unsigned int COEFFICIENTID_5 : 2; - unsigned int COEFFICIENT_5 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE6_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_6 : 1; - unsigned int FREQDIV_OVRD_EN_6 : 1; - unsigned int LINKSPEED_OVRD_EN_6 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_6 : 1; - unsigned int TXPWR_OVRD_EN_6 : 1; - unsigned int TXPGENABLE_OVRD_EN_6 : 1; - unsigned int RXPWR_OVRD_EN_6 : 1; - unsigned int RXPGENABLE_OVRD_EN_6 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_6 : 1; - unsigned int ENABLEFOM_OVRD_EN_6 : 1; - unsigned int REQUESTFOM_OVRD_EN_6 : 1; - unsigned int RESPONSEMODE_OVRD_EN_6 : 1; - unsigned int REQUESTTRK_OVRD_EN_6 : 1; - unsigned int REQUESTTRN_OVRD_EN_6 : 1; - unsigned int COEFFICIENTID_OVRD_EN_6 : 1; - unsigned int COEFFICIENT_OVRD_EN_6 : 1; - unsigned int CDREN_OVRD_EN_6 : 1; - unsigned int CDREN_OVRD_VAL_6 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE6_OVRD2__VI { - struct { - unsigned int GANGMODE_6 : 3; - unsigned int FREQDIV_6 : 2; - unsigned int LINKSPEED_6 : 2; - unsigned int TWOSYMENABLE_6 : 1; - unsigned int TXPWR_6 : 3; - unsigned int TXPGENABLE_6 : 2; - unsigned int RXPWR_6 : 3; - unsigned int RXPGENABLE_6 : 2; - unsigned int ELECIDLEDETEN_6 : 1; - unsigned int ENABLEFOM_6 : 1; - unsigned int REQUESTFOM_6 : 1; - unsigned int RESPONSEMODE_6 : 1; - unsigned int REQUESTTRK_6 : 1; - unsigned int REQUESTTRN_6 : 1; - unsigned int COEFFICIENTID_6 : 2; - unsigned int COEFFICIENT_6 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE7_OVRD__VI { - struct { - unsigned int GANGMODE_OVRD_EN_7 : 1; - unsigned int FREQDIV_OVRD_EN_7 : 1; - unsigned int LINKSPEED_OVRD_EN_7 : 1; - unsigned int TWOSYMENABLE_OVRD_EN_7 : 1; - unsigned int TXPWR_OVRD_EN_7 : 1; - unsigned int TXPGENABLE_OVRD_EN_7 : 1; - unsigned int RXPWR_OVRD_EN_7 : 1; - unsigned int RXPGENABLE_OVRD_EN_7 : 1; - unsigned int ELECIDLEDETEN_OVRD_EN_7 : 1; - unsigned int ENABLEFOM_OVRD_EN_7 : 1; - unsigned int REQUESTFOM_OVRD_EN_7 : 1; - unsigned int RESPONSEMODE_OVRD_EN_7 : 1; - unsigned int REQUESTTRK_OVRD_EN_7 : 1; - unsigned int REQUESTTRN_OVRD_EN_7 : 1; - unsigned int COEFFICIENTID_OVRD_EN_7 : 1; - unsigned int COEFFICIENT_OVRD_EN_7 : 1; - unsigned int CDREN_OVRD_EN_7 : 1; - unsigned int CDREN_OVRD_VAL_7 : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_LANE7_OVRD2__VI { - struct { - unsigned int GANGMODE_7 : 3; - unsigned int FREQDIV_7 : 2; - unsigned int LINKSPEED_7 : 2; - unsigned int TWOSYMENABLE_7 : 1; - unsigned int TXPWR_7 : 3; - unsigned int TXPGENABLE_7 : 2; - unsigned int RXPWR_7 : 3; - unsigned int RXPGENABLE_7 : 2; - unsigned int ELECIDLEDETEN_7 : 1; - unsigned int ENABLEFOM_7 : 1; - unsigned int REQUESTFOM_7 : 1; - unsigned int RESPONSEMODE_7 : 1; - unsigned int REQUESTTRK_7 : 1; - unsigned int REQUESTTRN_7 : 1; - unsigned int COEFFICIENTID_7 : 2; - unsigned int COEFFICIENT_7 : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_RX_CTRL__VI { - struct { - unsigned int RXPWR_IN_S2 : 3; - unsigned int RXPWR_IN_SPDCHNG : 3; - unsigned int RXPWR_IN_OFF : 3; - unsigned int RXPWR_IN_DEGRADE : 3; - unsigned int RXPWR_IN_UNUSED : 3; - unsigned int RXPWR_IN_INIT : 3; - unsigned int RXPWR_IN_PLL_OFF : 3; - unsigned int RXPWR_IN_DEGRADE_MODE : 1; - unsigned int RXPWR_IN_UNUSED_MODE : 1; - unsigned int RXPWR_GATING_IN_L1 : 1; - unsigned int RXPWR_GATING_IN_UNUSED : 1; - unsigned int RX_HLD_EIE_COUNT : 1; - unsigned int RX_EI_DET_IN_PS2_DEGRADE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_RX_CTRL2__VI { - struct { - unsigned int RX_RDY_DASRT_COUNT : 3; - unsigned int RX_STATUS_DASRT_COUNT : 3; - unsigned int RXPHYSTATUS_DELAY : 3; - unsigned int : 7; - unsigned int FORCE_CDREN_IN_L0S : 1; - unsigned int EI_DET_CYCLE_MODE : 2; - unsigned int EI_DET_ON_TIME : 2; - unsigned int EI_DET_OFF_TIME : 3; - unsigned int EI_DET_CYCLE_DIS_IN_PS1 : 1; - unsigned int RX_CDR_XTND_MODE : 2; - unsigned int RX_L0S_TO_L0_DETECT_EI : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_STRAP_0__VI { - struct { - unsigned int : 1; - unsigned int STRAP_TX_RDY_XTND_DIS : 1; - unsigned int STRAP_RX_RDY_XTND_DIS : 1; - unsigned int STRAP_TX_STATUS_XTND_DIS : 1; - unsigned int STRAP_RX_STATUS_XTND_DIS : 1; - unsigned int STRAP_FORCE_OWN_MSTR : 1; - unsigned int STRAP_PIF_CDR_EN_MODE : 2; - unsigned int STRAP_RX_EI_FILTER : 2; - unsigned int STRAP_RX_DIS_HLD_EIE_IN_PS1 : 1; - unsigned int STRAP_RX_DIS_HLD_EIE_IN_PS2 : 1; - unsigned int STRAP_PIF_BIT_12 : 1; - unsigned int STRAP_PIF_BIT_13 : 1; - unsigned int STRAP_PIF_BIT_14 : 1; - unsigned int STRAP_PIF_BIT_15 : 1; - unsigned int STRAP_PIF_BIT_16 : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_TX_CTRL__VI { - struct { - unsigned int TXPWR_IN_S2 : 3; - unsigned int TXPWR_IN_SPDCHNG : 3; - unsigned int TXPWR_IN_OFF : 3; - unsigned int TXPWR_IN_DEGRADE : 3; - unsigned int TXPWR_IN_UNUSED : 3; - unsigned int TXPWR_IN_INIT : 3; - unsigned int TXPWR_IN_PLL_OFF : 3; - unsigned int TXPWR_IN_DEGRADE_MODE : 1; - unsigned int TXPWR_IN_UNUSED_MODE : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_PIF_TX_CTRL2__VI { - struct { - unsigned int TX_RDY_DASRT_COUNT : 3; - unsigned int TX_STATUS_DASRT_COUNT : 3; - unsigned int TXPHYSTATUS_DELAY : 3; - unsigned int : 7; - unsigned int TX_HIGH_IMP_STAG_MP : 1; - unsigned int TX_HIGH_IMP_STAG_MODE : 2; - unsigned int : 2; - unsigned int TX_FORCE_DATA_VALID : 1; - unsigned int TX_L0_TO_HIZ_DLY : 3; - unsigned int TX_FIFO_INIT_UPCONFIG : 1; - unsigned int TX_HIZ_TO_L0_DLY : 3; - unsigned int TX_LINKSPEED_ACK_IN_S2 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_STRAP_GLB_REG1__VI { - struct { - unsigned int : 1; - unsigned int STRAP_RX_ADAPT_RST_MODE : 2; - unsigned int STRAP_RX_L0_ENTRY_MODE : 2; - unsigned int STRAP_RX_EI_FILTER : 2; - unsigned int STRAP_RX_ADAPT_RST_SUB_ENTRY : 1; - unsigned int STRAP_RX_PS0_RDY_GEN_MODE : 2; - unsigned int STRAP_RX_DLL_RESET_IN_SPDCHG : 1; - unsigned int STRAP_RX_ADAPT_TIME_OUT : 2; - unsigned int : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PB1_STRAP_GLB_REG2__VI { - struct { - unsigned int : 2; - unsigned int STRAP_BPHYC_PLL_RAMP_UP_TIME : 3; - unsigned int STRAP_IMPCAL_SETTLE_TIME : 2; - unsigned int STRAP_BG_SETTLE_TIME : 2; - unsigned int STRAP_TX_CMDET_TIME : 2; - unsigned int STRAP_TX_STARTUP_TIME : 2; - unsigned int : 15; - unsigned int STRAP_B_PCB_DIS0 : 1; - unsigned int STRAP_B_PCB_DIS1 : 1; - unsigned int STRAP_B_PCB_DRV_STR : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_ERROR_INJECT_PHYSICAL__VI { - struct { - unsigned int ERROR_INJECT_PL_LANE_ERR : 2; - unsigned int ERROR_INJECT_PL_FRAMING_ERR : 2; - unsigned int ERROR_INJECT_PL_BAD_PARITY_IN_SKP : 2; - unsigned int ERROR_INJECT_PL_BAD_LFSR_IN_SKP : 2; - unsigned int ERROR_INJECT_PL_LOOPBACK_UFLOW : 2; - unsigned int ERROR_INJECT_PL_LOOPBACK_OFLOW : 2; - unsigned int ERROR_INJECT_PL_DESKEW_ERR : 2; - unsigned int ERROR_INJECT_PL_8B10B_DISPARITY_ERR : 2; - unsigned int ERROR_INJECT_PL_8B10B_DECODE_ERR : 2; - unsigned int ERROR_INJECT_PL_SKP_OS_ERROR : 2; - unsigned int ERROR_INJECT_PL_INV_OS_IDENTIFIER : 2; - unsigned int ERROR_INJECT_PL_BAD_SYNC_HEADER : 2; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_ERROR_INJECT_TRANSACTION__VI { - struct { - unsigned int ERROR_INJECT_TL_FLOW_CTL_ERR : 2; - unsigned int ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER : 2; - unsigned int ERROR_INJECT_TL_BAD_DLLP : 2; - unsigned int ERROR_INJECT_TL_BAD_TLP : 2; - unsigned int ERROR_INJECT_TL_UNSUPPORTED_REQ : 2; - unsigned int ERROR_INJECT_TL_ECRC_ERROR : 2; - unsigned int ERROR_INJECT_TL_MALFORMED_TLP : 2; - unsigned int ERROR_INJECT_TL_UNEXPECTED_CMPLT : 2; - unsigned int ERROR_INJECT_TL_COMPLETER_ABORT : 2; - unsigned int ERROR_INJECT_TL_COMPLETION_TIMEOUT : 2; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIEP_SRIOV_PRIV_CTRL__VI { - struct { - unsigned int RX_SRIOV_VF_MAPPING_MODE : 2; - unsigned int SRIOV_SAVE_VFS_ON_VFENABLE_CLR : 2; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ARI_CAP__VI { - struct { - unsigned int ARI_MFVC_FUNC_GROUPS_CAP : 1; - unsigned int ARI_ACS_FUNC_GROUPS_CAP : 1; - unsigned int : 6; - unsigned int ARI_NEXT_FUNC_NUM : 8; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ARI_CNTL__VI { - struct { - unsigned int ARI_MFVC_FUNC_GROUPS_EN : 1; - unsigned int ARI_ACS_FUNC_GROUPS_EN : 1; - unsigned int : 2; - unsigned int ARI_FUNCTION_GROUP : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_ARI_ENH_CAP_LIST__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_EFUSE__VI { - struct { - unsigned int PCIE_EFUSE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_EFUSE2__VI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_EFUSE3__VI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_EFUSE4__VI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_EFUSE5__VI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_EFUSE6__VI { - struct { - unsigned int : 1; - unsigned int STRAP_BIF_F0_SUPPORTED_PAGE_SIZES : 16; - unsigned int SPARE_15_PCIEFUSE6 : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_EFUSE7__VI { - struct { - unsigned int : 1; - unsigned int STRAP_BIF_F0_SRIOV_VF_DEVICE_ID : 16; - unsigned int SPARE_15_PCIEFUSE7 : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_HOLD_TRAINING_A__VI { - struct { - unsigned int HOLD_TRAINING_A : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_BEST_EQ_SETTINGS__VI { - struct { - unsigned int LC_BEST_PRESET : 4; - unsigned int LC_BEST_PRECURSOR : 6; - unsigned int LC_BEST_CURSOR : 6; - unsigned int LC_BEST_POSTCURSOR : 6; - unsigned int LC_BEST_FOM : 8; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_CNTL6__VI { - struct { - unsigned int LC_SPC_MODE_2P5GT : 1; - unsigned int : 1; - unsigned int LC_SPC_MODE_5GT : 1; - unsigned int : 1; - unsigned int LC_SPC_MODE_8GT : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LC_FORCE_EQ_REQ_COEFF__VI { - struct { - unsigned int LC_FORCE_COEFF_IN_EQ_REQ_PHASE : 1; - unsigned int LC_FORCE_PRE_CURSOR_REQ : 6; - unsigned int LC_FORCE_CURSOR_REQ : 6; - unsigned int LC_FORCE_POST_CURSOR_REQ : 6; - unsigned int LC_FS_OTHER_END : 6; - unsigned int LC_LF_OTHER_END : 6; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LTR_CAP__VI { - struct { - unsigned int LTR_MAX_S_LATENCY_VALUE : 10; - unsigned int LTR_MAX_S_LATENCY_SCALE : 3; - unsigned int : 3; - unsigned int LTR_MAX_NS_LATENCY_VALUE : 10; - unsigned int LTR_MAX_NS_LATENCY_SCALE : 3; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_LTR_ENH_CAP_LIST__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_MC_ADDR0__VI { - struct { - unsigned int MC_INDEX_POS : 6; - unsigned int : 6; - unsigned int MC_BASE_ADDR_0 : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_MC_ADDR1__VI { - struct { - unsigned int MC_BASE_ADDR_1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_MC_BLOCK_ALL0__VI { - struct { - unsigned int MC_BLOCK_ALL_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_MC_BLOCK_ALL1__VI { - struct { - unsigned int MC_BLOCK_ALL_1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_MC_BLOCK_UNTRANSLATED_0__VI { - struct { - unsigned int MC_BLOCK_UNTRANSLATED_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_MC_BLOCK_UNTRANSLATED_1__VI { - struct { - unsigned int MC_BLOCK_UNTRANSLATED_1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_MC_CAP__VI { - struct { - unsigned int MC_MAX_GROUP : 6; - unsigned int : 2; - unsigned int MC_WIN_SIZE_REQ : 6; - unsigned int : 1; - unsigned int MC_ECRC_REGEN_SUPP : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_MC_CNTL__VI { - struct { - unsigned int MC_NUM_GROUP : 6; - unsigned int : 9; - unsigned int MC_ENABLE : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_MC_ENH_CAP_LIST__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_MC_RCV0__VI { - struct { - unsigned int MC_RECEIVE_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_MC_RCV1__VI { - struct { - unsigned int MC_RECEIVE_1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_OBFF_CNTL__VI { - struct { - unsigned int TX_OBFF_PRIV_DISABLE : 1; - unsigned int TX_OBFF_WAKE_SIMPLE_MODE_EN : 1; - unsigned int TX_OBFF_HOSTMEM_TO_ACTIVE : 1; - unsigned int TX_OBFF_SLVCPL_TO_ACTIVE : 1; - unsigned int TX_OBFF_WAKE_MAX_PULSE_WIDTH : 4; - unsigned int TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH : 4; - unsigned int TX_OBFF_WAKE_SAMPLING_PERIOD : 4; - unsigned int TX_OBFF_INTR_TO_ACTIVE : 1; - unsigned int TX_OBFF_ERR_TO_ACTIVE : 1; - unsigned int TX_OBFF_ANY_MSG_TO_ACTIVE : 1; - unsigned int TX_OBFF_ACCEPT_IN_NOND0 : 1; - unsigned int TX_OBFF_PENDING_REQ_TO_ACTIVE : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_RXDET_OVERRIDE__VI { - struct { - unsigned int RxDetOvrVal : 16; - unsigned int RxDetOvrEn : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_CAP__VI { - struct { - unsigned int SRIOV_VF_MIGRATION_CAP : 1; - unsigned int SRIOV_ARI_CAP_HIERARCHY_PRESERVED : 1; - unsigned int : 19; - unsigned int SRIOV_VF_MIGRATION_INTR_MSG_NUM : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_CONTROL__VI { - struct { - unsigned int SRIOV_VF_ENABLE : 1; - unsigned int SRIOV_VF_MIGRATION_ENABLE : 1; - unsigned int SRIOV_VF_MIGRATION_INTR_ENABLE : 1; - unsigned int SRIOV_VF_MSE : 1; - unsigned int SRIOV_ARI_CAP_HIERARCHY : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_ENH_CAP_LIST__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_FIRST_VF_OFFSET__VI { - struct { - unsigned int SRIOV_FIRST_VF_OFFSET : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_FUNC_DEP_LINK__VI { - struct { - unsigned int SRIOV_FUNC_DEP_LINK : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_INITIAL_VFS__VI { - struct { - unsigned int SRIOV_INITIAL_VFS : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_NUM_VFS__VI { - struct { - unsigned int SRIOV_NUM_VFS : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_STATUS__VI { - struct { - unsigned int SRIOV_VF_MIGRATION_STATUS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI { - struct { - unsigned int SRIOV_SUPPORTED_PAGE_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_SYSTEM_PAGE_SIZE__VI { - struct { - unsigned int SRIOV_SYSTEM_PAGE_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_TOTAL_VFS__VI { - struct { - unsigned int SRIOV_TOTAL_VFS : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_VF_BASE_ADDR_0__VI { - struct { - unsigned int VF_BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_VF_BASE_ADDR_1__VI { - struct { - unsigned int VF_BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_VF_BASE_ADDR_2__VI { - struct { - unsigned int VF_BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_VF_BASE_ADDR_3__VI { - struct { - unsigned int VF_BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_VF_BASE_ADDR_4__VI { - struct { - unsigned int VF_BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_VF_BASE_ADDR_5__VI { - struct { - unsigned int VF_BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_VF_DEVICE_ID__VI { - struct { - unsigned int SRIOV_VF_DEVICE_ID : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI { - struct { - unsigned int SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_SRIOV_VF_STRIDE__VI { - struct { - unsigned int SRIOV_VF_STRIDE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TPH_REQR_CAP__VI { - struct { - unsigned int TPH_REQR_NO_ST_MODE_SUPPORTED : 1; - unsigned int TPH_REQR_INT_VEC_MODE_SUPPORTED : 1; - unsigned int TPH_REQR_DEV_SPC_MODE_SUPPORTED : 1; - unsigned int : 5; - unsigned int TPH_REQR_EXTND_TPH_REQR_SUPPORED : 1; - unsigned int TPH_REQR_ST_TABLE_LOCATION : 2; - unsigned int : 5; - unsigned int TPH_REQR_ST_TABLE_SIZE : 11; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TPH_REQR_CNTL__VI { - struct { - unsigned int TPH_REQR_ST_MODE_SEL : 3; - unsigned int : 5; - unsigned int TPH_REQR_EN : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TPH_REQR_ENH_CAP_LIST__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_TX_LTR_CNTL__VI { - struct { - unsigned int LTR_PRIV_S_SHORT_VALUE : 3; - unsigned int LTR_PRIV_S_LONG_VALUE : 3; - unsigned int LTR_PRIV_S_REQUIREMENT : 1; - unsigned int LTR_PRIV_NS_SHORT_VALUE : 3; - unsigned int LTR_PRIV_NS_LONG_VALUE : 3; - unsigned int LTR_PRIV_NS_REQUIREMENT : 1; - unsigned int LTR_PRIV_MSG_DIS_IN_PM_NON_D0 : 1; - unsigned int LTR_PRIV_RST_LTR_IN_DL_DOWN : 1; - unsigned int TX_CHK_FC_FOR_L1 : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI { - struct { - unsigned int CAP_ID : 16; - unsigned int CAP_VER : 4; - unsigned int NEXT_PTR : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI { - struct { - unsigned int VSEC_ID : 16; - unsigned int VSEC_REV : 4; - unsigned int VSEC_LENGTH : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI { - struct { - unsigned int SOFT_PF_FLR : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_WRAP_DTM_MISC__VI { - struct { - unsigned int DTM_BULKPHY_FREQDIV_OVERRIDE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_WRAP_MISC__VI { - struct { - unsigned int : 1; - unsigned int STRAP_BIF_HOLD_TRAINING_STICKY : 1; - unsigned int STRAP_BIF_QUICKSIM_START : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_WRAP_PIF_MISC__VI { - struct { - unsigned int DTM_PIF_DELAY_FI : 3; - unsigned int : 1; - unsigned int DTM_PIF_DELAY_DI : 3; - unsigned int DTM_PIF_ATSEL_FI : 1; - unsigned int DTM_PIF_ATSEL_DI : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_WRAP_REG_TARG_MISC__VI { - struct { - unsigned int CLKEN_MASK : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_WRAP_SCRATCH1__VI { - struct { - unsigned int PCIE_WRAP_SCRATCH1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_WRAP_SCRATCH2__VI { - struct { - unsigned int PCIE_WRAP_SCRATCH2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PCIE_WRAP_TURNAROUND_DAISYCHAIN__VI { - struct { - unsigned int END_BIFCORE_REGISTER_DAISYCHAIN : 1; - unsigned int END_WRAPPER_REGISTER_DAISYCHAIN : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PERFCOUNTER_CNTL__VI { - struct { - unsigned int PERFCOUNTER_EVENT_SEL : 9; - unsigned int PERFCOUNTER_CVALUE_SEL : 3; - unsigned int PERFCOUNTER_INC_MODE : 2; - unsigned int PERFCOUNTER_HW_CNTL_SEL : 1; - unsigned int PERFCOUNTER_RUNEN_MODE : 1; - unsigned int PERFCOUNTER_CNTOFF_SEL : 5; - unsigned int PERFCOUNTER_CNTOFF_START_DIS : 1; - unsigned int PERFCOUNTER_RESTART_EN : 1; - unsigned int PERFCOUNTER_INT_EN : 1; - unsigned int PERFCOUNTER_OFF_MASK : 1; - unsigned int PERFCOUNTER_ACTIVE : 1; - unsigned int PERFCOUNTER_INT_TYPE : 1; - unsigned int PERFCOUNTER_COUNTED_VALUE_TYPE : 1; - unsigned int : 1; - unsigned int PERFCOUNTER_CNTL_SEL : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PERFCOUNTER_STATE__VI { - struct { - unsigned int PERFCOUNTER_CNT0_STATE : 2; - unsigned int PERFCOUNTER_STATE_SEL0 : 1; - unsigned int : 1; - unsigned int PERFCOUNTER_CNT1_STATE : 2; - unsigned int PERFCOUNTER_STATE_SEL1 : 1; - unsigned int : 1; - unsigned int PERFCOUNTER_CNT2_STATE : 2; - unsigned int PERFCOUNTER_STATE_SEL2 : 1; - unsigned int : 1; - unsigned int PERFCOUNTER_CNT3_STATE : 2; - unsigned int PERFCOUNTER_STATE_SEL3 : 1; - unsigned int : 1; - unsigned int PERFCOUNTER_CNT4_STATE : 2; - unsigned int PERFCOUNTER_STATE_SEL4 : 1; - unsigned int : 1; - unsigned int PERFCOUNTER_CNT5_STATE : 2; - unsigned int PERFCOUNTER_STATE_SEL5 : 1; - unsigned int : 1; - unsigned int PERFCOUNTER_CNT6_STATE : 2; - unsigned int PERFCOUNTER_STATE_SEL6 : 1; - unsigned int : 1; - unsigned int PERFCOUNTER_CNT7_STATE : 2; - unsigned int PERFCOUNTER_STATE_SEL7 : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PERFMON_CNTL__VI { - struct { - unsigned int PERFMON_STATE : 2; - unsigned int PERFMON_RUN_ENABLE_SEL : 6; - unsigned int PERFMON_RPT_COUNT : 20; - unsigned int PERFMON_CNTOFF_AND_OR : 1; - unsigned int PERFMON_CNTOFF_INT_EN : 1; - unsigned int PERFMON_CNTOFF_INT_STATUS : 1; - unsigned int PERFMON_CNTOFF_INT_ACK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PERFMON_CNTL2__VI { - struct { - unsigned int PERFMON_CNTOFF_INT_TYPE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PERFMON_CVALUE_INT_MISC__VI { - struct { - unsigned int PERFCOUNTER_INT0_STATUS : 1; - unsigned int PERFCOUNTER_INT1_STATUS : 1; - unsigned int PERFCOUNTER_INT2_STATUS : 1; - unsigned int PERFCOUNTER_INT3_STATUS : 1; - unsigned int PERFCOUNTER_INT4_STATUS : 1; - unsigned int PERFCOUNTER_INT5_STATUS : 1; - unsigned int PERFCOUNTER_INT6_STATUS : 1; - unsigned int PERFCOUNTER_INT7_STATUS : 1; - unsigned int PERFCOUNTER_INT0_ACK : 1; - unsigned int PERFCOUNTER_INT1_ACK : 1; - unsigned int PERFCOUNTER_INT2_ACK : 1; - unsigned int PERFCOUNTER_INT3_ACK : 1; - unsigned int PERFCOUNTER_INT4_ACK : 1; - unsigned int PERFCOUNTER_INT5_ACK : 1; - unsigned int PERFCOUNTER_INT6_ACK : 1; - unsigned int PERFCOUNTER_INT7_ACK : 1; - unsigned int PERFMON_CVALUE_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PERFMON_CVALUE_LOW__VI { - struct { - unsigned int PERFMON_CVALUE_LOW : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PERFMON_HI__VI { - struct { - unsigned int PERFMON_HI : 16; - unsigned int : 13; - unsigned int PERFMON_READ_SEL : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PERFMON_LOW__VI { - struct { - unsigned int PERFMON_LOW : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PERFMON_TEST_DEBUG_DATA__VI { - struct { - unsigned int PERFMON_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PERFMON_TEST_DEBUG_INDEX__VI { - struct { - unsigned int PERFMON_TEST_DEBUG_INDEX : 8; - unsigned int PERFMON_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE0_DMIF_BUFFER_CONTROL__VI { - struct { - unsigned int DMIF_BUFFERS_ALLOCATED : 3; - unsigned int : 1; - unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE0_MAX_REQUESTS__VI { - struct { - unsigned int MAX_REQUESTS : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE0_PG_CONFIG__VI { - struct { - unsigned int PIPE0_POWER_FORCEON : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE0_PG_ENABLE__VI { - struct { - unsigned int PIPE0_POWER_GATE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE0_PG_STATUS__VI { - struct { - unsigned int PIPE0_PGFSM_READ_DATA : 24; - unsigned int PIPE0_DEBUG_PWR_STATUS : 2; - unsigned int : 2; - unsigned int PIPE0_DESIRED_PWR_STATE : 1; - unsigned int PIPE0_REQUESTED_PWR_STATE : 1; - unsigned int PIPE0_PGFSM_PWR_STATUS : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE1_DMIF_BUFFER_CONTROL__VI { - struct { - unsigned int DMIF_BUFFERS_ALLOCATED : 3; - unsigned int : 1; - unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE1_MAX_REQUESTS__VI { - struct { - unsigned int MAX_REQUESTS : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE1_PG_CONFIG__VI { - struct { - unsigned int PIPE1_POWER_FORCEON : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE1_PG_ENABLE__VI { - struct { - unsigned int PIPE1_POWER_GATE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE1_PG_STATUS__VI { - struct { - unsigned int PIPE1_PGFSM_READ_DATA : 24; - unsigned int PIPE1_DEBUG_PWR_STATUS : 2; - unsigned int : 2; - unsigned int PIPE1_DESIRED_PWR_STATE : 1; - unsigned int PIPE1_REQUESTED_PWR_STATE : 1; - unsigned int PIPE1_PGFSM_PWR_STATUS : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE2_DMIF_BUFFER_CONTROL__VI { - struct { - unsigned int DMIF_BUFFERS_ALLOCATED : 3; - unsigned int : 1; - unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE2_MAX_REQUESTS__VI { - struct { - unsigned int MAX_REQUESTS : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE2_PG_CONFIG__VI { - struct { - unsigned int PIPE2_POWER_FORCEON : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE2_PG_ENABLE__VI { - struct { - unsigned int PIPE2_POWER_GATE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE2_PG_STATUS__VI { - struct { - unsigned int PIPE2_PGFSM_READ_DATA : 24; - unsigned int PIPE2_DEBUG_PWR_STATUS : 2; - unsigned int : 2; - unsigned int PIPE2_DESIRED_PWR_STATE : 1; - unsigned int PIPE2_REQUESTED_PWR_STATE : 1; - unsigned int PIPE2_PGFSM_PWR_STATUS : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE3_DMIF_BUFFER_CONTROL__VI { - struct { - unsigned int DMIF_BUFFERS_ALLOCATED : 3; - unsigned int : 1; - unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE3_MAX_REQUESTS__VI { - struct { - unsigned int MAX_REQUESTS : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE3_PG_CONFIG__VI { - struct { - unsigned int PIPE3_POWER_FORCEON : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE3_PG_ENABLE__VI { - struct { - unsigned int PIPE3_POWER_GATE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE3_PG_STATUS__VI { - struct { - unsigned int PIPE3_PGFSM_READ_DATA : 24; - unsigned int PIPE3_DEBUG_PWR_STATUS : 2; - unsigned int : 2; - unsigned int PIPE3_DESIRED_PWR_STATE : 1; - unsigned int PIPE3_REQUESTED_PWR_STATE : 1; - unsigned int PIPE3_PGFSM_PWR_STATUS : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE4_DMIF_BUFFER_CONTROL__VI { - struct { - unsigned int DMIF_BUFFERS_ALLOCATED : 3; - unsigned int : 1; - unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE4_MAX_REQUESTS__VI { - struct { - unsigned int MAX_REQUESTS : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE4_PG_CONFIG__VI { - struct { - unsigned int PIPE4_POWER_FORCEON : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE4_PG_ENABLE__VI { - struct { - unsigned int PIPE4_POWER_GATE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE4_PG_STATUS__VI { - struct { - unsigned int PIPE4_PGFSM_READ_DATA : 24; - unsigned int PIPE4_DEBUG_PWR_STATUS : 2; - unsigned int : 2; - unsigned int PIPE4_DESIRED_PWR_STATE : 1; - unsigned int PIPE4_REQUESTED_PWR_STATE : 1; - unsigned int PIPE4_PGFSM_PWR_STATUS : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE5_DMIF_BUFFER_CONTROL__VI { - struct { - unsigned int DMIF_BUFFERS_ALLOCATED : 3; - unsigned int : 1; - unsigned int DMIF_BUFFERS_ALLOCATION_COMPLETED : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE5_MAX_REQUESTS__VI { - struct { - unsigned int MAX_REQUESTS : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE5_PG_CONFIG__VI { - struct { - unsigned int PIPE5_POWER_FORCEON : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE5_PG_ENABLE__VI { - struct { - unsigned int PIPE5_POWER_GATE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE5_PG_STATUS__VI { - struct { - unsigned int PIPE5_PGFSM_READ_DATA : 24; - unsigned int PIPE5_DEBUG_PWR_STATUS : 2; - unsigned int : 2; - unsigned int PIPE5_DESIRED_PWR_STATE : 1; - unsigned int PIPE5_REQUESTED_PWR_STATE : 1; - unsigned int PIPE5_PGFSM_PWR_STATUS : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE6_ARBITRATION_CONTROL3__VI { - struct { - unsigned int EFFICIENCY_WEIGHT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE6_MAX_REQUESTS__VI { - struct { - unsigned int MAX_REQUESTS : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE7_ARBITRATION_CONTROL3__VI { - struct { - unsigned int EFFICIENCY_WEIGHT : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIPE7_MAX_REQUESTS__VI { - struct { - unsigned int MAX_REQUESTS : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PIXCLK0_RESYNC_CNTL__VI { - struct { - unsigned int PIXCLK0_RESYNC_ENABLE : 1; - unsigned int : 3; - unsigned int DCCG_DEEP_COLOR_CNTL0 : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_ANALOG__VI { - struct { - unsigned int PLL_CAL_MODE : 5; - unsigned int PLL_PFD_PULSE_SEL : 2; - unsigned int : 1; - unsigned int PLL_CP : 4; - unsigned int PLL_LF_MODE : 9; - unsigned int PLL_VREG_FB_TRIM : 3; - unsigned int PLL_IBIAS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_ANALOG_CNTL__VI { - struct { - unsigned int PLL_ANALOG_TEST_EN : 1; - unsigned int PLL_ANALOG_MUX_CNTL : 4; - unsigned int PLL_ANALOGOUT_MUX_CNTL : 4; - unsigned int PLL_REGREF_TRIM : 5; - unsigned int PLL_CALIB_FBDIV : 3; - unsigned int PLL_CALIB_FASTCAL : 1; - unsigned int PLL_TEST_SSAMP_EN : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_CNTL__VI { - struct { - unsigned int PLL_RESET : 1; - unsigned int PLL_POWER_DOWN : 1; - unsigned int PLL_BYPASS_CAL : 1; - unsigned int PLL_POST_DIV_SRC : 1; - unsigned int PLL_VCOREF : 2; - unsigned int PLL_PCIE_REFCLK_SEL : 1; - unsigned int PLL_ANTIGLITCH_RESETB : 1; - unsigned int PLL_CALREF : 2; - unsigned int PLL_CAL_BYPASS_REFDIV : 1; - unsigned int PLL_REFCLK_SEL : 2; - unsigned int PLL_ANTI_GLITCH_RESET : 1; - unsigned int PLL_XOCLK_DRV_R_EN : 1; - unsigned int : 1; - unsigned int PLL_REF_DIV_SRC : 3; - unsigned int PLL_LOCK_FREQ_SEL : 1; - unsigned int PLL_CALIB_DONE : 1; - unsigned int PLL_LOCKED : 1; - unsigned int PLL_REFCLK_RECV_EN : 1; - unsigned int PLL_REFCLK_RECV_SEL : 1; - unsigned int PLL_TIMING_MODE_STATUS : 2; - unsigned int PLL_DIG_SPARE : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_DEBUG_CNTL__VI { - struct { - unsigned int PLL_DEBUG_SIGNALS_ENABLE : 1; - unsigned int : 3; - unsigned int PLL_DEBUG_MUXOUT_SEL : 4; - unsigned int PLL_DEBUG_CLK_SEL : 5; - unsigned int : 3; - unsigned int PLL_DEBUG_ADC_CNTL : 8; - unsigned int PLL_DEBUG_ADC_READBACK : 3; - unsigned int PLL_DEBUG_ADC_EN : 1; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_DS_CNTL__VI { - struct { - unsigned int PLL_DS_FRAC : 16; - unsigned int PLL_DS_ORDER : 2; - unsigned int PLL_DS_MODE : 1; - unsigned int PLL_DS_PRBS_EN : 1; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_FB_DIV__VI { - struct { - unsigned int PLL_FB_DIV_FRACTION : 4; - unsigned int PLL_FB_DIV_FRACTION_CNTL : 2; - unsigned int : 10; - unsigned int PLL_FB_DIV : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_IDCLK_CNTL__VI { - struct { - unsigned int PLL_LTDP_IDCLK_EN : 1; - unsigned int PLL_LTDP_IDCLK_DIFF_EN : 1; - unsigned int PLL_TMDP_IDCLK_EN : 1; - unsigned int PLL_TMDP_IDCLK_DIFF_EN : 1; - unsigned int PLL_IDCLK_EN : 1; - unsigned int : 3; - unsigned int PLL_DIFF_POST_DIV_RESET : 1; - unsigned int : 3; - unsigned int PLL_DIFF_POST_DIV_SELECT : 1; - unsigned int : 3; - unsigned int PLL_DIFF_POST_DIV : 4; - unsigned int PLL_CUR_LTDP : 2; - unsigned int PLL_CUR_PREDRV : 2; - unsigned int PLL_CUR_TMDP : 2; - unsigned int PLL_CML_A_DRVSTR : 2; - unsigned int PLL_CML_B_DRVSTR : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED0__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED1__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED10__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED11__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED12__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED13__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED14__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED15__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED16__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED17__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED18__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED19__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED2__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED20__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED21__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED22__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED23__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED24__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED25__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED26__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED27__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED28__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED29__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED3__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED30__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED31__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED32__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED33__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED34__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED35__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED36__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED37__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED38__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED39__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED4__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED40__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED41__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED5__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED6__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED7__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED8__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_MACRO_CNTL_RESERVED9__VI { - struct { - unsigned int PLL_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_POST_DIV__VI { - struct { - unsigned int PLL_POST_DIV_PIXCLK : 7; - unsigned int PLL_POST_DIV1P5_DISPCLK : 1; - unsigned int PLL_POST_DIV_DVOCLK : 7; - unsigned int PLL_POST_DIV1P5_DPREFCLK : 1; - unsigned int PLL_POST_DIV_IDCLK : 7; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_REF_DIV__VI { - struct { - unsigned int PLL_REF_DIV : 10; - unsigned int : 2; - unsigned int PLL_CALIBRATION_REF_DIV : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_SS_AMOUNT_DSFRAC__VI { - struct { - unsigned int PLL_SS_AMOUNT_DSFRAC : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_SS_CNTL__VI { - struct { - unsigned int PLL_SS_AMOUNT_FBDIV : 8; - unsigned int PLL_SS_AMOUNT_NFRAC_SLIP : 4; - unsigned int PLL_SS_EN : 1; - unsigned int PLL_SS_MODE : 1; - unsigned int : 2; - unsigned int PLL_SS_STEP_SIZE_DSFRAC : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_UNLOCK_DETECT_CNTL__VI { - struct { - unsigned int PLL_UNLOCK_DETECT_ENABLE : 1; - unsigned int PLL_UNLOCK_DET_RES100_SELECT : 1; - unsigned int PLL_UNLOCK_STICKY_STATUS : 1; - unsigned int : 1; - unsigned int PLL_UNLOCK_DET_COUNT : 3; - unsigned int PLL_UNLOCKED_STICKY_RST_TEST : 1; - unsigned int PLL_UNLOCKED_STICKY_TEST_READBACK : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_UPDATE_CNTL__VI { - struct { - unsigned int PLL_UPDATE_PENDING : 1; - unsigned int : 7; - unsigned int PLL_UPDATE_POINT : 1; - unsigned int : 7; - unsigned int PLL_AUTO_RESET_DISABLE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_UPDATE_LOCK__VI { - struct { - unsigned int PLL_UPDATE_LOCK : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_VREG_CNTL__VI { - struct { - unsigned int PLL_VREG_CNTL : 20; - unsigned int PLL_BG_VREG_BIAS : 2; - unsigned int : 4; - unsigned int PLL_VREF_SEL : 1; - unsigned int : 1; - unsigned int PLL_VREG_BIAS : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PLL_XOR_LOCK__VI { - struct { - unsigned int PLL_XOR_LOCK : 1; - unsigned int PLL_XOR_LOCK_READBACK : 1; - unsigned int : 6; - unsigned int PLL_SPARE : 6; - unsigned int : 2; - unsigned int PLL_LOCK_COUNT_SEL : 4; - unsigned int PLL_LOCK_DETECTOR_RESOLUTION_FREF : 3; - unsigned int PLL_LOCK_DETECTOR_RESOLUTION_FFB : 3; - unsigned int PLL_LOCK_DETECTOR_OPAMP_BIAS : 2; - unsigned int PLL_FAST_LOCK_MODE_EN : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_1__VI { - struct { - unsigned int SviLoadLineOffsetVddC : 8; - unsigned int SviLoadLineTrimVddC : 8; - unsigned int SviLoadLineVddC : 8; - unsigned int SviLoadLineEn : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_10__VI { - struct { - unsigned int GnbLPML_3 : 8; - unsigned int GnbLPML_2 : 8; - unsigned int GnbLPML_1 : 8; - unsigned int GnbLPML_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_11__VI { - struct { - unsigned int GnbLPML_7 : 8; - unsigned int GnbLPML_6 : 8; - unsigned int GnbLPML_5 : 8; - unsigned int GnbLPML_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_12__VI { - struct { - unsigned int GnbLPML_11 : 8; - unsigned int GnbLPML_10 : 8; - unsigned int GnbLPML_9 : 8; - unsigned int GnbLPML_8 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_13__VI { - struct { - unsigned int GnbLPML_15 : 8; - unsigned int GnbLPML_14 : 8; - unsigned int GnbLPML_13 : 8; - unsigned int GnbLPML_12 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_14__VI { - struct { - unsigned int Reserved1_1 : 8; - unsigned int Reserved1_0 : 8; - unsigned int GnbLPMLMinVid : 8; - unsigned int GnbLPMLMaxVid : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_15__VI { - struct { - unsigned int BapmVddCBaseLeakageLoSidd : 16; - unsigned int BapmVddCBaseLeakageHiSidd : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_2__VI { - struct { - unsigned int TDC_MAWt : 8; - unsigned int TDC_VDDC_ThrottleReleaseLimitPerc : 8; - unsigned int TDC_VDDC_PkgLimit : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_3__VI { - struct { - unsigned int Reserved : 8; - unsigned int LPMLTemperatureMax : 8; - unsigned int LPMLTemperatureMin : 8; - unsigned int TdcWaterfallCtl : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_4__VI { - struct { - unsigned int LPMLTemperatureScaler_3 : 8; - unsigned int LPMLTemperatureScaler_2 : 8; - unsigned int LPMLTemperatureScaler_1 : 8; - unsigned int LPMLTemperatureScaler_0 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_5__VI { - struct { - unsigned int LPMLTemperatureScaler_7 : 8; - unsigned int LPMLTemperatureScaler_6 : 8; - unsigned int LPMLTemperatureScaler_5 : 8; - unsigned int LPMLTemperatureScaler_4 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_6__VI { - struct { - unsigned int LPMLTemperatureScaler_11 : 8; - unsigned int LPMLTemperatureScaler_10 : 8; - unsigned int LPMLTemperatureScaler_9 : 8; - unsigned int LPMLTemperatureScaler_8 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_7__VI { - struct { - unsigned int LPMLTemperatureScaler_15 : 8; - unsigned int LPMLTemperatureScaler_14 : 8; - unsigned int LPMLTemperatureScaler_13 : 8; - unsigned int LPMLTemperatureScaler_12 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_8__VI { - struct { - unsigned int FuzzyFan_ErrorRateSetDelta : 16; - unsigned int FuzzyFan_ErrorSetDelta : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PM_FUSES_9__VI { - struct { - unsigned int Reserved6 : 16; - unsigned int FuzzyFan_PwmSetDelta : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PPLL_DEBUG_MUX_CNTL__VI { - struct { - unsigned int DEBUG_BUS_MUX_SEL : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PPLL_DIV_UPDATE_DEBUG__VI { - struct { - unsigned int PLL_REF_DIV_CHANGED : 1; - unsigned int PLL_FB_DIV_CHANGED : 1; - unsigned int PLL_UPDATE_PENDING : 1; - unsigned int PLL_UPDATE_CURRENT_STATE : 2; - unsigned int PLL_UPDATE_ENABLE : 1; - unsigned int PLL_UPDATE_REQ : 1; - unsigned int PLL_UPDATE_ACK : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PPLL_SPARE0__VI { - struct { - unsigned int PLL_SPARE0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PPLL_SPARE1__VI { - struct { - unsigned int PLL_SPARE1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PPLL_STATUS_DEBUG__VI { - struct { - unsigned int PLL_DEBUG_BUS : 16; - unsigned int PLL_UNLOCK : 1; - unsigned int PLL_CAL_RESULT : 4; - unsigned int : 3; - unsigned int PLL_POWERGOOD_ISO_ENB : 1; - unsigned int PLL_POWERGOOD_S : 1; - unsigned int PLL_POWERGOOD_V : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_CONTROL__VI { - struct { - unsigned int PRESCALE_MODE : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_GRPH_CONTROL__VI { - struct { - unsigned int GRPH_PRESCALE_SELECT : 1; - unsigned int GRPH_PRESCALE_R_SIGN : 1; - unsigned int GRPH_PRESCALE_G_SIGN : 1; - unsigned int GRPH_PRESCALE_B_SIGN : 1; - unsigned int GRPH_PRESCALE_BYPASS : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_OVL_CONTROL__VI { - struct { - unsigned int OVL_PRESCALE_SELECT : 1; - unsigned int OVL_PRESCALE_CB_SIGN : 1; - unsigned int OVL_PRESCALE_Y_SIGN : 1; - unsigned int OVL_PRESCALE_CR_SIGN : 1; - unsigned int OVL_PRESCALE_BYPASS : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_VALUES_B__VI { - struct { - unsigned int PRESCALE_BIAS_B : 16; - unsigned int PRESCALE_SCALE_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_VALUES_G__VI { - struct { - unsigned int PRESCALE_BIAS_G : 16; - unsigned int PRESCALE_SCALE_G : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_VALUES_GRPH_B__VI { - struct { - unsigned int GRPH_PRESCALE_BIAS_B : 16; - unsigned int GRPH_PRESCALE_SCALE_B : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_VALUES_GRPH_G__VI { - struct { - unsigned int GRPH_PRESCALE_BIAS_G : 16; - unsigned int GRPH_PRESCALE_SCALE_G : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_VALUES_GRPH_R__VI { - struct { - unsigned int GRPH_PRESCALE_BIAS_R : 16; - unsigned int GRPH_PRESCALE_SCALE_R : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_VALUES_OVL_CB__VI { - struct { - unsigned int OVL_PRESCALE_BIAS_CB : 16; - unsigned int OVL_PRESCALE_SCALE_CB : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_VALUES_OVL_CR__VI { - struct { - unsigned int OVL_PRESCALE_BIAS_CR : 16; - unsigned int OVL_PRESCALE_SCALE_CR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_VALUES_OVL_Y__VI { - struct { - unsigned int OVL_PRESCALE_BIAS_Y : 16; - unsigned int OVL_PRESCALE_SCALE_Y : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PRESCALE_VALUES_R__VI { - struct { - unsigned int PRESCALE_BIAS_R : 16; - unsigned int PRESCALE_SCALE_R : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS0_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS10_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS11_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS12_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS13_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS14_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS15_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS16_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS17_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS18_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS19_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS1_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS20_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS21_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS22_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS23_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS24_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS25_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS26_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS27_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS2_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS3_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS4_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS5_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS6_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS7_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS8_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS9_CNTL_STATUS__VI { - struct { - unsigned int MmDatOut : 8; - unsigned int PsmTdo : 1; - unsigned int AlarmFlag : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS_CNTL__VI { - struct { - unsigned int MmBusIn : 8; - unsigned int MmLclRdEn : 1; - unsigned int MmLclWrEn : 1; - unsigned int MmLclSz : 2; - unsigned int MmState : 6; - unsigned int PsmScanMode : 1; - unsigned int PsmGater : 1; - unsigned int PsmTrst : 1; - unsigned int PsmEn : 1; - unsigned int SkipPhaseEn : 1; - unsigned int Isolate : 1; - unsigned int AvfsRst : 1; - unsigned int PccIsolateEn : 1; - unsigned int DeepSleepIsolateEn : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_AVFS_SEL__VI { - struct { - unsigned int AvfsSel : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_CKS_CNTL__VI { - struct { - unsigned int CKS_BYPASS : 1; - unsigned int CKS_PCCEnable : 1; - unsigned int CKS_TEMP_COMP : 1; - unsigned int CKS_STRETCH_AMOUNT : 4; - unsigned int CKS_SKIP_PHASE_BYPASS : 1; - unsigned int CKS_SAMPLE_SIZE : 4; - unsigned int CKS_FSM_WAIT_CYCLES : 4; - unsigned int CKS_USE_FOR_LOW_FREQ : 1; - unsigned int CKS_NO_EXTRA_COARSE_STEP : 1; - unsigned int CKS_LDO_REFSEL : 4; - unsigned int DDT_DEBUS_SEL : 1; - unsigned int CKS_LDO_READY_COUNT_VAL : 8; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_CKS_ENABLE__VI { - struct { - unsigned int STRETCH_ENABLE : 1; - unsigned int masterReset : 1; - unsigned int staticEnable : 1; - unsigned int IGNORE_DROOP_DETECT : 1; - unsigned int PCC_HAND_SHAKE_EN : 1; - unsigned int MET_CTRL_SEL : 2; - unsigned int DS_HAND_SHAKE_EN : 1; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_DISP_TIMER2_CONTROL__VI { - struct { - unsigned int DISP_TIMER_INT_COUNT : 25; - unsigned int DISP_TIMER_INT_ENABLE : 1; - unsigned int DISP_TIMER_INT_DISABLE : 1; - unsigned int DISP_TIMER_INT_MASK : 1; - unsigned int DISP_TIMER_INT_STAT_AK : 1; - unsigned int DISP_TIMER_INT_TYPE : 1; - unsigned int DISP_TIMER_INT_MODE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_DISP_TIMER2_DEBUG__VI { - struct { - unsigned int DISP_TIMER_INT_RUNNING : 1; - unsigned int DISP_TIMER_INT_STAT : 1; - unsigned int DISP_TIMER_INT : 1; - unsigned int : 4; - unsigned int DISP_TIMER_RUN_VAL : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_DISP_TIMER_CONTROL__VI { - struct { - unsigned int DISP_TIMER_INT_COUNT : 25; - unsigned int DISP_TIMER_INT_ENABLE : 1; - unsigned int DISP_TIMER_INT_DISABLE : 1; - unsigned int DISP_TIMER_INT_MASK : 1; - unsigned int DISP_TIMER_INT_STAT_AK : 1; - unsigned int DISP_TIMER_INT_TYPE : 1; - unsigned int DISP_TIMER_INT_MODE : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_DISP_TIMER_CONTROL2__VI { - struct { - unsigned int DISP_TIMER_PULSE_WIDTH : 10; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_DISP_TIMER_DEBUG__VI { - struct { - unsigned int DISP_TIMER_INT_RUNNING : 1; - unsigned int DISP_TIMER_INT_STAT : 1; - unsigned int DISP_TIMER_INT : 1; - unsigned int : 4; - unsigned int DISP_TIMER_RUN_VAL : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_PCC_CONTROL__VI { - struct { - unsigned int PCC_POLARITY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union PWR_PCC_GPIO_SELECT__VI { - struct { - unsigned int GPIO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RAS_TA_SIGNATURE1__VI { - struct { - unsigned int SIGNATURE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RBBMIF_STATUS__VI { - struct { - unsigned int RBBMIF_TIMEOUT_CLIENTS_DEC : 15; - unsigned int : 13; - unsigned int RBBMIF_TIMEOUT_OP : 1; - unsigned int RBBMIF_TIMEOUT_RDWR_STATUS : 1; - unsigned int RBBMIF_TIMEOUT_ACK : 1; - unsigned int RBBMIF_TIMEOUT_MASK : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RBBMIF_STATUS_FLAG__VI { - struct { - unsigned int RBBMIF_STATE : 3; - unsigned int RBBMIF_ACK_TIMEOUT : 1; - unsigned int RBBMIF_READ_TIMEOUT : 1; - unsigned int RBBMIF_FIFO_EMPTY : 1; - unsigned int RBBMIF_FIFO_FULL : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RBBMIF_TIMEOUT__VI { - struct { - unsigned int RBBMIF_TIMEOUT_DELAY : 20; - unsigned int RBBMIF_ACK_HOLD : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RBBMIF_TIMEOUT_DIS__VI { - struct { - unsigned int CLIENT0_TIMEOUT_DIS : 1; - unsigned int CLIENT1_TIMEOUT_DIS : 1; - unsigned int CLIENT2_TIMEOUT_DIS : 1; - unsigned int CLIENT3_TIMEOUT_DIS : 1; - unsigned int CLIENT4_TIMEOUT_DIS : 1; - unsigned int CLIENT5_TIMEOUT_DIS : 1; - unsigned int CLIENT6_TIMEOUT_DIS : 1; - unsigned int CLIENT7_TIMEOUT_DIS : 1; - unsigned int CLIENT8_TIMEOUT_DIS : 1; - unsigned int CLIENT9_TIMEOUT_DIS : 1; - unsigned int CLIENT10_TIMEOUT_DIS : 1; - unsigned int CLIENT11_TIMEOUT_DIS : 1; - unsigned int CLIENT12_TIMEOUT_DIS : 1; - unsigned int CLIENT13_TIMEOUT_DIS : 1; - unsigned int CLIENT14_TIMEOUT_DIS : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RCU_VIRT_RESET_REQ__VI { - struct { - unsigned int VF : 16; - unsigned int : 15; - unsigned int PF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REFCLK_CGTT_BLK_CTRL_REG__VI { - struct { - unsigned int REFCLK_TURN_ON_DELAY : 4; - unsigned int REFCLK_TURN_OFF_DELAY : 8; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REFCLK_CNTL__VI { - struct { - unsigned int REFCLK_CLOCK_EN : 1; - unsigned int REFCLK_SRC_SEL : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_END_CNTL1__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION_END : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_END_CNTL2__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION_END_SLOPE : 16; - unsigned int REGAMMA_CNTLA_EXP_REGION_END_BASE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_REGION_0_1__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_REGION_10_11__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_REGION_12_13__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_REGION_14_15__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_REGION_2_3__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_REGION_4_5__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_REGION_6_7__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_REGION_8_9__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_SLOPE_CNTL__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLA_START_CNTL__VI { - struct { - unsigned int REGAMMA_CNTLA_EXP_REGION_START : 18; - unsigned int : 2; - unsigned int REGAMMA_CNTLA_EXP_REGION_START_SEGMENT : 7; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_END_CNTL1__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION_END : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_END_CNTL2__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION_END_SLOPE : 16; - unsigned int REGAMMA_CNTLB_EXP_REGION_END_BASE : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_REGION_0_1__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_REGION_10_11__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_REGION_12_13__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_REGION_14_15__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_REGION_2_3__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_REGION_4_5__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_REGION_6_7__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_REGION_8_9__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS : 3; - unsigned int : 1; - unsigned int REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET : 9; - unsigned int : 3; - unsigned int REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_SLOPE_CNTL__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE : 18; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CNTLB_START_CNTL__VI { - struct { - unsigned int REGAMMA_CNTLB_EXP_REGION_START : 18; - unsigned int : 2; - unsigned int REGAMMA_CNTLB_EXP_REGION_START_SEGMENT : 7; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_CONTROL__VI { - struct { - unsigned int GRPH_REGAMMA_MODE : 3; - unsigned int : 1; - unsigned int OVL_REGAMMA_MODE : 3; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_LUT_DATA__VI { - struct { - unsigned int REGAMMA_LUT_DATA : 19; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_LUT_INDEX__VI { - struct { - unsigned int REGAMMA_LUT_INDEX : 9; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REGAMMA_LUT_WRITE_EN_MASK__VI { - struct { - unsigned int REGAMMA_LUT_WRITE_EN_MASK : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REG_ADAPT_pciecore0_CONTROL__VI { - struct { - unsigned int ACCESS_MODE_pciecore0 : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REG_ADAPT_pif0_CONTROL__VI { - struct { - unsigned int ACCESS_MODE_pif0 : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REG_ADAPT_pwregr_CONTROL__VI { - struct { - unsigned int ACCESS_MODE_pwregr : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REG_ADAPT_pwregt_CONTROL__VI { - struct { - unsigned int ACCESS_MODE_pwregt : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REMAP_HDP_MEM_FLUSH_CNTL__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union REMAP_HDP_REG_FLUSH_CNTL__VI { - struct { - unsigned int : 2; - unsigned int ADDRESS : 17; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CP_RESPONSE0__VI { - struct { - unsigned int RESPONSE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CP_RESPONSE1__VI { - struct { - unsigned int RESPONSE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CP_RESPONSE2__VI { - struct { - unsigned int RESPONSE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CP_RESPONSE3__VI { - struct { - unsigned int RESPONSE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CP_SCHEDULERS__VI { - struct { - unsigned int scheduler0 : 8; - unsigned int scheduler1 : 8; - unsigned int scheduler2 : 8; - unsigned int scheduler3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CSIB_ADDR_HI__VI { - struct { - unsigned int ADDRESS : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CSIB_ADDR_LO__VI { - struct { - unsigned int ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_CSIB_LENGTH__VI { - struct { - unsigned int LENGTH : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_INT_DISABLE_TH0__VI { - struct { - unsigned int DISABLE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_INT_DISABLE_TH1__VI { - struct { - unsigned int DISABLE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_INT_FORCE_TH0__VI { - struct { - unsigned int FORCE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_INT_FORCE_TH1__VI { - struct { - unsigned int FORCE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_THREAD_RESET__VI { - struct { - unsigned int THREAD0_RESET : 1; - unsigned int THREAD1_RESET : 1; - unsigned int THREAD2_RESET : 1; - unsigned int THREAD3_RESET : 1; - unsigned int RESERVED : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPM_VMID_THREAD2__VI { - struct { - unsigned int RLC_VMID : 4; - unsigned int RESERVED0 : 4; - unsigned int RLC_QUEUEID : 3; - unsigned int RESERVED1 : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_ACTIVE_FCN_ID__VI { - struct { - unsigned int VF_ID : 4; - unsigned int RESERVED : 27; - unsigned int PF_VF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_CFG_REG1__VI { - struct { - unsigned int CMD_TYPE : 4; - unsigned int CMD_EXECUTE : 1; - unsigned int CMD_EXECUTE_INTR_EN : 1; - unsigned int RESERVED : 2; - unsigned int FCN_ID : 8; - unsigned int NEXT_FCN_ID : 8; - unsigned int RESERVED1 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_CFG_REG10__VI { - struct { - unsigned int TIME_QUANTA_PF : 16; - unsigned int RESERVED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_CFG_REG11__VI { - struct { - unsigned int YIELD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_CFG_REG12__VI { - struct { - unsigned int TIME_QUANTA_VF0 : 8; - unsigned int TIME_QUANTA_VF1 : 8; - unsigned int TIME_QUANTA_VF2 : 8; - unsigned int TIME_QUANTA_VF3 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_CFG_REG13__VI { - struct { - unsigned int TIME_QUANTA_VF4 : 8; - unsigned int TIME_QUANTA_VF5 : 8; - unsigned int TIME_QUANTA_VF6 : 8; - unsigned int TIME_QUANTA_VF7 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_CFG_REG14__VI { - struct { - unsigned int TIME_QUANTA_VF8 : 8; - unsigned int TIME_QUANTA_VF9 : 8; - unsigned int TIME_QUANTA_VF10 : 8; - unsigned int TIME_QUANTA_VF11 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_CFG_REG15__VI { - struct { - unsigned int TIME_QUANTA_VF12 : 8; - unsigned int TIME_QUANTA_VF13 : 8; - unsigned int TIME_QUANTA_VF14 : 8; - unsigned int TIME_QUANTA_VF15 : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_CFG_REG2__VI { - struct { - unsigned int CMD_STATUS : 4; - unsigned int RESERVED : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_CFG_REG6__VI { - struct { - unsigned int CNTXT_SIZE : 7; - unsigned int CNTXT_LOCATION : 1; - unsigned int RESERVED : 2; - unsigned int CNTXT_OFFSET : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_CFG_REG8__VI { - struct { - unsigned int VM_BUSY_STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_CFG_REG9__VI { - struct { - unsigned int ACTIVE_FCN_ID : 8; - unsigned int ACTIVE_FCN_ID_STATUS : 4; - unsigned int RESERVED : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_F32_CNTL__VI { - struct { - unsigned int ENABLE : 1; - unsigned int RESERVED : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_F32_RESET__VI { - struct { - unsigned int RESET : 1; - unsigned int RESERVED : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_INT_DISABLE__VI { - struct { - unsigned int DISABLE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_INT_FORCE__VI { - struct { - unsigned int FORCE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_RLC_RESPONSE__VI { - struct { - unsigned int RESP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SCH_0__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SCH_1__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SCH_2__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SCH_3__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SCH_INT__VI { - struct { - unsigned int interrupt : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SCRATCH_ADDR__VI { - struct { - unsigned int ADDR : 9; - unsigned int RESERVED : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SCRATCH_DATA__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SDMA0_BUSY_STATUS__VI { - struct { - unsigned int VM_BUSY_STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SDMA0_STATUS__VI { - struct { - unsigned int PREEMPTED : 1; - unsigned int RESERVED : 7; - unsigned int SAVED : 1; - unsigned int RESERVED1 : 3; - unsigned int RESTORED : 1; - unsigned int RESERVED2 : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SDMA1_BUSY_STATUS__VI { - struct { - unsigned int VM_BUSY_STATUS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SDMA1_STATUS__VI { - struct { - unsigned int PREEMPTED : 1; - unsigned int RESERVED : 7; - unsigned int SAVED : 1; - unsigned int RESERVED1 : 3; - unsigned int RESTORED : 1; - unsigned int RESERVED2 : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_SMU_RESPONSE__VI { - struct { - unsigned int RESP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_UCODE_ADDR__VI { - struct { - unsigned int UCODE_ADDR : 12; - unsigned int RESERVED : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_UCODE_DATA__VI { - struct { - unsigned int UCODE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_VF_ENABLE__VI { - struct { - unsigned int VF_ENABLE : 1; - unsigned int RESERVED : 15; - unsigned int VF_NUM : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_GPU_IOV_VIRT_RESET_REQ__VI { - struct { - unsigned int VF_FLR : 16; - unsigned int RESERVED : 15; - unsigned int SOFT_PF_FLR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_HYP_GPM_UCODE_ADDR__VI { - struct { - unsigned int UCODE_ADDR : 12; - unsigned int RESERVED : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_HYP_GPM_UCODE_DATA__VI { - struct { - unsigned int UCODE_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_MGCG_CTRL__VI { - struct { - unsigned int MGCG_EN : 1; - unsigned int SILICON_EN : 1; - unsigned int SIMULATION_EN : 1; - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int GC_CAC_MGCG_CLK_CNTL : 1; - unsigned int SE_CAC_MGCG_CLK_CNTL : 1; - unsigned int SPARE : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PERFMON_CLK_CNTL__VI { - struct { - unsigned int PERFMON_CLOCK_STATE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_PG_DELAY_3__VI { - struct { - unsigned int CGCG_ACTIVE_BEFORE_CGPG : 8; - unsigned int RESERVED : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_RLCV_COMMAND__VI { - struct { - unsigned int CMD : 4; - unsigned int RESERVED : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_RLCV_SAFE_MODE__VI { - struct { - unsigned int CMD : 1; - unsigned int MESSAGE : 4; - unsigned int RESERVED1 : 3; - unsigned int RESPONSE : 4; - unsigned int RESERVED : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_ROM_CNTL__VI { - struct { - unsigned int USE_ROM : 1; - unsigned int SLP_MODE_EN : 1; - unsigned int EFUSE_DISTRIB_EN : 1; - unsigned int HELLOWORLD_EN : 1; - unsigned int CU_HARVEST_EN : 1; - unsigned int RESERVED : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SMU_COMMAND__VI { - struct { - unsigned int CMD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SMU_MESSAGE__VI { - struct { - unsigned int CMD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SMU_SAFE_MODE__VI { - struct { - unsigned int CMD : 1; - unsigned int MESSAGE : 4; - unsigned int RESERVED1 : 3; - unsigned int RESPONSE : 4; - unsigned int RESERVED : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int RESERVED : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int RESERVED : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int RESERVED : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__VI { - struct { - unsigned int PERFMON_SAMPLE_DELAY : 8; - unsigned int RESERVED : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_ARAM_ADDR__VI { - struct { - unsigned int ADDR : 10; - unsigned int RESERVED : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_ARAM_DATA__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_CNTL__VI { - struct { - unsigned int SRM_ENABLE : 1; - unsigned int AUTO_INCR_ADDR : 1; - unsigned int RESERVED : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_DEBUG__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_DEBUG_SELECT__VI { - struct { - unsigned int SELECT : 8; - unsigned int RESERVED : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_DRAM_ADDR__VI { - struct { - unsigned int ADDR : 10; - unsigned int RESERVED : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_DRAM_DATA__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_GPM_ABORT__VI { - struct { - unsigned int ABORT : 1; - unsigned int RESERVED : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_GPM_COMMAND__VI { - struct { - unsigned int OP : 1; - unsigned int INDEX_CNTL : 1; - unsigned int INDEX_CNTL_NUM : 3; - unsigned int SIZE : 12; - unsigned int START_OFFSET : 12; - unsigned int RESERVED1 : 2; - unsigned int DEST_MEMORY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_GPM_COMMAND_STATUS__VI { - struct { - unsigned int FIFO_EMPTY : 1; - unsigned int FIFO_FULL : 1; - unsigned int RESERVED : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_ADDR_0__VI { - struct { - unsigned int ADDRESS : 16; - unsigned int RESERVED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_ADDR_1__VI { - struct { - unsigned int ADDRESS : 16; - unsigned int RESERVED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_ADDR_2__VI { - struct { - unsigned int ADDRESS : 16; - unsigned int RESERVED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_ADDR_3__VI { - struct { - unsigned int ADDRESS : 16; - unsigned int RESERVED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_ADDR_4__VI { - struct { - unsigned int ADDRESS : 16; - unsigned int RESERVED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_ADDR_5__VI { - struct { - unsigned int ADDRESS : 16; - unsigned int RESERVED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_ADDR_6__VI { - struct { - unsigned int ADDRESS : 16; - unsigned int RESERVED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_ADDR_7__VI { - struct { - unsigned int ADDRESS : 16; - unsigned int RESERVED : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_DATA_0__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_DATA_1__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_DATA_2__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_DATA_3__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_DATA_4__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_DATA_5__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_DATA_6__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_INDEX_CNTL_DATA_7__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_RLCV_COMMAND__VI { - struct { - unsigned int OP : 1; - unsigned int RESERVED : 3; - unsigned int SIZE : 12; - unsigned int START_OFFSET : 12; - unsigned int RESERVED1 : 3; - unsigned int DEST_MEMORY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_RLCV_COMMAND_STATUS__VI { - struct { - unsigned int FIFO_EMPTY : 1; - unsigned int FIFO_FULL : 1; - unsigned int RESERVED : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union RLC_SRM_STAT__VI { - struct { - unsigned int SRM_STATUS : 1; - unsigned int RESERVED : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SAM_IH_EXT_ERR_INTR__VI { - struct { - unsigned int UVD : 1; - unsigned int VCE : 1; - unsigned int ISP : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SAM_IH_EXT_ERR_INTR_STATUS__VI { - struct { - unsigned int UVD : 1; - unsigned int VCE : 1; - unsigned int ISP : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SAM_SAB_RBI_WPTR__VI { - struct { - unsigned int : 26; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SAM_SAB_RBO_WPTR__VI { - struct { - unsigned int : 30; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_ALU_CONTROL__VI { - struct { - unsigned int SCL_ALU_DISABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_AUTOMATIC_MODE_CONTROL__VI { - struct { - unsigned int SCL_V_CALC_AUTO_RATIO_EN : 1; - unsigned int : 15; - unsigned int SCL_H_CALC_AUTO_RATIO_EN : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_COEF_RAM_SELECT__VI { - struct { - unsigned int SCL_C_RAM_TAP_PAIR_IDX : 2; - unsigned int : 6; - unsigned int SCL_C_RAM_PHASE : 7; - unsigned int : 1; - unsigned int SCL_C_RAM_FILTER_TYPE : 2; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_COEF_RAM_TAP_DATA__VI { - struct { - unsigned int SCL_C_RAM_EVEN_TAP_COEF : 14; - unsigned int : 1; - unsigned int SCL_C_RAM_EVEN_TAP_COEF_EN : 1; - unsigned int SCL_C_RAM_ODD_TAP_COEF : 14; - unsigned int : 1; - unsigned int SCL_C_RAM_ODD_TAP_COEF_EN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_CONTROL__VI { - struct { - unsigned int SCL_BOUNDARY_MODE : 1; - unsigned int : 3; - unsigned int SCL_EARLY_EOL_MODE : 1; - unsigned int : 3; - unsigned int SCL_TOTAL_PHASE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_DEBUG__VI { - struct { - unsigned int SCL_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_DEBUG2__VI { - struct { - unsigned int SCL_DEBUG_REQ_MODE : 1; - unsigned int SCL_DEBUG_EOF_MODE : 2; - unsigned int SCL_DEBUG2 : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_EXT_OVERSCAN_LEFT_RIGHT__VI { - struct { - unsigned int EXT_OVERSCAN_RIGHT : 13; - unsigned int : 3; - unsigned int EXT_OVERSCAN_LEFT : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_EXT_OVERSCAN_TOP_BOTTOM__VI { - struct { - unsigned int EXT_OVERSCAN_BOTTOM : 13; - unsigned int : 3; - unsigned int EXT_OVERSCAN_TOP : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_HORZ_FILTER_CONTROL__VI { - struct { - unsigned int : 8; - unsigned int SCL_H_2TAP_HARDCODE_COEF_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_HORZ_FILTER_INIT__VI { - struct { - unsigned int SCL_H_INIT_FRAC : 24; - unsigned int SCL_H_INIT_INT : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_HORZ_FILTER_INIT_C__VI { - struct { - unsigned int SCL_H_INIT_FRAC_C : 24; - unsigned int SCL_H_INIT_INT_C : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_HORZ_FILTER_SCALE_RATIO__VI { - struct { - unsigned int SCL_H_SCALE_RATIO : 26; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_HORZ_FILTER_SCALE_RATIO_C__VI { - struct { - unsigned int SCL_H_SCALE_RATIO_C : 26; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_MANUAL_REPLICATE_CONTROL__VI { - struct { - unsigned int SCL_V_MANUAL_REPLICATE_FACTOR : 4; - unsigned int : 4; - unsigned int SCL_H_MANUAL_REPLICATE_FACTOR : 4; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_MODE__VI { - struct { - unsigned int SCL_MODE : 1; - unsigned int : 3; - unsigned int SCL_PSCL_EN : 1; - unsigned int : 3; - unsigned int SCL_INTERLACE_SOURCE : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_MODE_CHANGE_DET1__VI { - struct { - unsigned int SCL_MODE_CHANGE : 1; - unsigned int : 3; - unsigned int SCL_MODE_CHANGE_ACK : 1; - unsigned int : 2; - unsigned int SCL_ALU_H_SCALE_RATIO : 21; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_MODE_CHANGE_DET2__VI { - struct { - unsigned int SCL_ALU_V_SCALE_RATIO : 21; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_MODE_CHANGE_DET3__VI { - struct { - unsigned int SCL_ALU_SOURCE_HEIGHT : 14; - unsigned int : 2; - unsigned int SCL_ALU_SOURCE_WIDTH : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_MODE_CHANGE_MASK__VI { - struct { - unsigned int SCL_MODE_CHANGE_MASK : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_ROUND_OFFSET__VI { - struct { - unsigned int SCL_ROUND_OFFSET_RGB_Y : 16; - unsigned int SCL_ROUND_OFFSET_CBCR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_TAP_CONTROL__VI { - struct { - unsigned int SCL_V_NUM_OF_TAPS : 3; - unsigned int : 1; - unsigned int SCL_H_NUM_OF_TAPS : 3; - unsigned int : 1; - unsigned int SCL_V_NUM_OF_TAPS_C : 3; - unsigned int : 1; - unsigned int SCL_H_NUM_OF_TAPS_C : 3; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_TEST_DEBUG_DATA__VI { - struct { - unsigned int SCL_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_TEST_DEBUG_INDEX__VI { - struct { - unsigned int SCL_TEST_DEBUG_INDEX : 8; - unsigned int SCL_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_UPDATE__VI { - struct { - unsigned int SCL_UPDATE_PENDING : 1; - unsigned int : 7; - unsigned int SCL_UPDATE_TAKEN : 1; - unsigned int : 7; - unsigned int SCL_UPDATE_LOCK : 1; - unsigned int : 7; - unsigned int SCL_COEF_UPDATE_COMPLETE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VERT_FILTER_CONTROL__VI { - struct { - unsigned int : 8; - unsigned int SCL_V_2TAP_HARDCODE_COEF_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VERT_FILTER_INIT__VI { - struct { - unsigned int SCL_V_INIT_FRAC : 24; - unsigned int SCL_V_INIT_INT : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VERT_FILTER_INIT_BOT__VI { - struct { - unsigned int SCL_V_INIT_FRAC_BOT : 24; - unsigned int SCL_V_INIT_INT_BOT : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VERT_FILTER_INIT_BOT_C__VI { - struct { - unsigned int SCL_V_INIT_FRAC_BOT_C : 24; - unsigned int SCL_V_INIT_INT_BOT_C : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VERT_FILTER_INIT_C__VI { - struct { - unsigned int SCL_V_INIT_FRAC_C : 24; - unsigned int SCL_V_INIT_INT_C : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VERT_FILTER_SCALE_RATIO__VI { - struct { - unsigned int SCL_V_SCALE_RATIO : 26; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VERT_FILTER_SCALE_RATIO_C__VI { - struct { - unsigned int SCL_V_SCALE_RATIO_C : 26; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VIEWPORT_SIZE__VI { - struct { - unsigned int VIEWPORT_HEIGHT : 13; - unsigned int : 3; - unsigned int VIEWPORT_WIDTH : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VIEWPORT_SIZE_C__VI { - struct { - unsigned int VIEWPORT_HEIGHT_C : 13; - unsigned int : 3; - unsigned int VIEWPORT_WIDTH_C : 13; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VIEWPORT_START__VI { - struct { - unsigned int VIEWPORT_Y_START : 14; - unsigned int : 2; - unsigned int VIEWPORT_X_START : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VIEWPORT_START_C__VI { - struct { - unsigned int VIEWPORT_Y_START_C : 14; - unsigned int : 2; - unsigned int VIEWPORT_X_START_C : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VIEWPORT_START_SECONDARY__VI { - struct { - unsigned int VIEWPORT_Y_START_SECONDARY : 14; - unsigned int : 2; - unsigned int VIEWPORT_X_START_SECONDARY : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCLV_VIEWPORT_START_SECONDARY_C__VI { - struct { - unsigned int VIEWPORT_Y_START_SECONDARY_C : 14; - unsigned int : 2; - unsigned int VIEWPORT_X_START_SECONDARY_C : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_DEBUG2__VI { - struct { - unsigned int SCL_DEBUG_REQ_MODE : 1; - unsigned int SCL_DEBUG_EOF_MODE : 2; - unsigned int SCL_DEBUG2 : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_HORZ_FILTER_INIT__VI { - struct { - unsigned int SCL_H_INIT_FRAC : 24; - unsigned int SCL_H_INIT_INT : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_MODE__VI { - struct { - unsigned int SCL_MODE : 2; - unsigned int : 2; - unsigned int SCL_PSCL_EN : 1; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SCL_ROUND_OFFSET__VI { - struct { - unsigned int SCL_ROUND_OFFSET_RGB_Y : 16; - unsigned int SCL_ROUND_OFFSET_CBCR : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_ACTIVE_FCN_ID__VI { - struct { - unsigned int VFID : 4; - unsigned int : 27; - unsigned int VF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_ATOMIC_CNTL__VI { - struct { - unsigned int LOOP_TIMER : 31; - unsigned int ATOMIC_RTN_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_ATOMIC_PREOP_HI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_ATOMIC_PREOP_LO__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_BA_THRESHOLD__VI { - struct { - unsigned int READ_THRES : 10; - unsigned int : 6; - unsigned int WRITE_THRES : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_CONTEXT_REG_TYPE0__VI { - struct { - unsigned int SDMA0_GFX_RB_CNTL : 1; - unsigned int SDMA0_GFX_RB_BASE : 1; - unsigned int SDMA0_GFX_RB_BASE_HI : 1; - unsigned int SDMA0_GFX_RB_RPTR : 1; - unsigned int SDMA0_GFX_RB_WPTR : 1; - unsigned int SDMA0_GFX_RB_WPTR_POLL_CNTL : 1; - unsigned int SDMA0_GFX_RB_WPTR_POLL_ADDR_HI : 1; - unsigned int SDMA0_GFX_RB_WPTR_POLL_ADDR_LO : 1; - unsigned int SDMA0_GFX_RB_RPTR_ADDR_HI : 1; - unsigned int SDMA0_GFX_RB_RPTR_ADDR_LO : 1; - unsigned int SDMA0_GFX_IB_CNTL : 1; - unsigned int SDMA0_GFX_IB_RPTR : 1; - unsigned int SDMA0_GFX_IB_OFFSET : 1; - unsigned int SDMA0_GFX_IB_BASE_LO : 1; - unsigned int SDMA0_GFX_IB_BASE_HI : 1; - unsigned int SDMA0_GFX_IB_SIZE : 1; - unsigned int SDMA0_GFX_SKIP_CNTL : 1; - unsigned int SDMA0_GFX_CONTEXT_STATUS : 1; - unsigned int SDMA0_GFX_DOORBELL : 1; - unsigned int SDMA0_GFX_CONTEXT_CNTL : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_CONTEXT_REG_TYPE1__VI { - struct { - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int SDMA0_GFX_VIRTUAL_ADDR : 1; - unsigned int SDMA0_GFX_APE1_CNTL : 1; - unsigned int SDMA0_GFX_DOORBELL_LOG : 1; - unsigned int SDMA0_GFX_WATERMARK : 1; - unsigned int VOID_REG1 : 1; - unsigned int SDMA0_GFX_CSA_ADDR_LO : 1; - unsigned int SDMA0_GFX_CSA_ADDR_HI : 1; - unsigned int VOID_REG2 : 1; - unsigned int SDMA0_GFX_IB_SUB_REMAIN : 1; - unsigned int SDMA0_GFX_PREEMPT : 1; - unsigned int SDMA0_GFX_DUMMY_REG : 1; - unsigned int RESERVED : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_CONTEXT_REG_TYPE2__VI { - struct { - unsigned int SDMA0_GFX_MIDCMD_DATA0 : 1; - unsigned int SDMA0_GFX_MIDCMD_DATA1 : 1; - unsigned int SDMA0_GFX_MIDCMD_DATA2 : 1; - unsigned int SDMA0_GFX_MIDCMD_DATA3 : 1; - unsigned int SDMA0_GFX_MIDCMD_DATA4 : 1; - unsigned int SDMA0_GFX_MIDCMD_DATA5 : 1; - unsigned int SDMA0_GFX_MIDCMD_CNTL : 1; - unsigned int RESERVED : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_EDC_CONFIG__VI { - struct { - unsigned int : 1; - unsigned int DIS_EDC : 1; - unsigned int ECC_INT_ENABLE : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_CSA_ADDR_HI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_CSA_ADDR_LO__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_DOORBELL__VI { - struct { - unsigned int OFFSET : 21; - unsigned int : 7; - unsigned int ENABLE : 1; - unsigned int : 1; - unsigned int CAPTURED : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_DOORBELL_LOG__VI { - struct { - unsigned int BE_ERROR : 1; - unsigned int : 1; - unsigned int DATA : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_DUMMY_REG__VI { - struct { - unsigned int DUMMY : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_IB_SUB_REMAIN__VI { - struct { - unsigned int SIZE : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_MIDCMD_CNTL__VI { - struct { - unsigned int DATA_VALID : 1; - unsigned int COPY_MODE : 1; - unsigned int : 2; - unsigned int SPLIT_STATE : 4; - unsigned int ALLOW_PREEMPT : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_MIDCMD_DATA0__VI { - struct { - unsigned int DATA0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_MIDCMD_DATA1__VI { - struct { - unsigned int DATA1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_MIDCMD_DATA2__VI { - struct { - unsigned int DATA2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_MIDCMD_DATA3__VI { - struct { - unsigned int DATA3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_MIDCMD_DATA4__VI { - struct { - unsigned int DATA4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_MIDCMD_DATA5__VI { - struct { - unsigned int DATA5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_PREEMPT__VI { - struct { - unsigned int IB_PREEMPT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_GFX_WATERMARK__VI { - struct { - unsigned int RD_OUTSTANDING : 12; - unsigned int : 4; - unsigned int WR_OUTSTANDING : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_ID__VI { - struct { - unsigned int DEVICE_ID : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_PERF_REG_TYPE0__VI { - struct { - unsigned int SDMA0_PERFMON_CNTL : 1; - unsigned int SDMA0_PERFCOUNTER0_RESULT : 1; - unsigned int SDMA0_PERFCOUNTER1_RESULT : 1; - unsigned int RESERVED_31_3 : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_POWER_CNTL_IDLE__VI { - struct { - unsigned int DELAY1 : 16; - unsigned int DELAY2 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_PUB_REG_TYPE0__VI { - struct { - unsigned int SDMA0_UCODE_ADDR : 1; - unsigned int SDMA0_UCODE_DATA : 1; - unsigned int SDMA0_POWER_CNTL : 1; - unsigned int SDMA0_CLK_CTRL : 1; - unsigned int SDMA0_CNTL : 1; - unsigned int SDMA0_CHICKEN_BITS : 1; - unsigned int SDMA0_TILING_CONFIG : 1; - unsigned int SDMA0_HASH : 1; - unsigned int : 1; - unsigned int SDMA0_SEM_WAIT_FAIL_TIMER_CNTL : 1; - unsigned int SDMA0_RB_RPTR_FETCH : 1; - unsigned int SDMA0_IB_OFFSET_FETCH : 1; - unsigned int SDMA0_PROGRAM : 1; - unsigned int SDMA0_STATUS_REG : 1; - unsigned int SDMA0_STATUS1_REG : 1; - unsigned int SDMA0_RD_BURST_CNTL : 1; - unsigned int RESERVED_16 : 1; - unsigned int RESERVED_17 : 1; - unsigned int SDMA0_F32_CNTL : 1; - unsigned int SDMA0_FREEZE : 1; - unsigned int SDMA0_PHASE0_QUANTUM : 1; - unsigned int SDMA0_PHASE1_QUANTUM : 1; - unsigned int SDMA_POWER_GATING : 1; - unsigned int SDMA_PGFSM_CONFIG : 1; - unsigned int SDMA_PGFSM_WRITE : 1; - unsigned int SDMA_PGFSM_READ : 1; - unsigned int SDMA0_EDC_CONFIG : 1; - unsigned int SDMA0_BA_THRESHOLD : 1; - unsigned int SDMA0_DEVICE_ID : 1; - unsigned int : 1; - unsigned int RESERVED : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_PUB_REG_TYPE1__VI { - struct { - unsigned int SDMA0_VM_CNTL : 1; - unsigned int SDMA0_VM_CTX_LO : 1; - unsigned int SDMA0_VM_CTX_HI : 1; - unsigned int SDMA0_STATUS2_REG : 1; - unsigned int SDMA0_VM_CTX_CNTL : 1; - unsigned int RESERVED : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RD_BURST_CNTL__VI { - struct { - unsigned int RD_BURST : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_CSA_ADDR_HI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_CSA_ADDR_LO__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_DUMMY_REG__VI { - struct { - unsigned int DUMMY : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_IB_SUB_REMAIN__VI { - struct { - unsigned int SIZE : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_MIDCMD_CNTL__VI { - struct { - unsigned int DATA_VALID : 1; - unsigned int COPY_MODE : 1; - unsigned int : 2; - unsigned int SPLIT_STATE : 4; - unsigned int ALLOW_PREEMPT : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_MIDCMD_DATA0__VI { - struct { - unsigned int DATA0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_MIDCMD_DATA1__VI { - struct { - unsigned int DATA1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_MIDCMD_DATA2__VI { - struct { - unsigned int DATA2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_MIDCMD_DATA3__VI { - struct { - unsigned int DATA3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_MIDCMD_DATA4__VI { - struct { - unsigned int DATA4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_MIDCMD_DATA5__VI { - struct { - unsigned int DATA5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_PREEMPT__VI { - struct { - unsigned int IB_PREEMPT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC0_WATERMARK__VI { - struct { - unsigned int RD_OUTSTANDING : 12; - unsigned int : 4; - unsigned int WR_OUTSTANDING : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_CSA_ADDR_HI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_CSA_ADDR_LO__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_DUMMY_REG__VI { - struct { - unsigned int DUMMY : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_IB_SUB_REMAIN__VI { - struct { - unsigned int SIZE : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_MIDCMD_CNTL__VI { - struct { - unsigned int DATA_VALID : 1; - unsigned int COPY_MODE : 1; - unsigned int : 2; - unsigned int SPLIT_STATE : 4; - unsigned int ALLOW_PREEMPT : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_MIDCMD_DATA0__VI { - struct { - unsigned int DATA0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_MIDCMD_DATA1__VI { - struct { - unsigned int DATA1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_MIDCMD_DATA2__VI { - struct { - unsigned int DATA2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_MIDCMD_DATA3__VI { - struct { - unsigned int DATA3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_MIDCMD_DATA4__VI { - struct { - unsigned int DATA4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_MIDCMD_DATA5__VI { - struct { - unsigned int DATA5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_PREEMPT__VI { - struct { - unsigned int IB_PREEMPT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_RLC1_WATERMARK__VI { - struct { - unsigned int RD_OUTSTANDING : 12; - unsigned int : 4; - unsigned int WR_OUTSTANDING : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_STATUS2_REG__VI { - struct { - unsigned int ID : 2; - unsigned int F32_INSTR_PTR : 14; - unsigned int CMD_OP : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_VERSION__VI { - struct { - unsigned int VALUE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_VF_ENABLE__VI { - struct { - unsigned int VF_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_VIRT_RESET_REQ__VI { - struct { - unsigned int VF : 16; - unsigned int : 15; - unsigned int PF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_VM_CNTL__VI { - struct { - unsigned int CMD : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_VM_CTX_CNTL__VI { - struct { - unsigned int PRIV : 1; - unsigned int : 3; - unsigned int VMID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_VM_CTX_HI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA0_VM_CTX_LO__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_ACTIVE_FCN_ID__VI { - struct { - unsigned int VFID : 4; - unsigned int : 27; - unsigned int VF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_ATOMIC_CNTL__VI { - struct { - unsigned int LOOP_TIMER : 31; - unsigned int ATOMIC_RTN_INT_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_ATOMIC_PREOP_HI__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_ATOMIC_PREOP_LO__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_BA_THRESHOLD__VI { - struct { - unsigned int READ_THRES : 10; - unsigned int : 6; - unsigned int WRITE_THRES : 10; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_CONTEXT_REG_TYPE0__VI { - struct { - unsigned int SDMA1_GFX_RB_CNTL : 1; - unsigned int SDMA1_GFX_RB_BASE : 1; - unsigned int SDMA1_GFX_RB_BASE_HI : 1; - unsigned int SDMA1_GFX_RB_RPTR : 1; - unsigned int SDMA1_GFX_RB_WPTR : 1; - unsigned int SDMA1_GFX_RB_WPTR_POLL_CNTL : 1; - unsigned int SDMA1_GFX_RB_WPTR_POLL_ADDR_HI : 1; - unsigned int SDMA1_GFX_RB_WPTR_POLL_ADDR_LO : 1; - unsigned int SDMA1_GFX_RB_RPTR_ADDR_HI : 1; - unsigned int SDMA1_GFX_RB_RPTR_ADDR_LO : 1; - unsigned int SDMA1_GFX_IB_CNTL : 1; - unsigned int SDMA1_GFX_IB_RPTR : 1; - unsigned int SDMA1_GFX_IB_OFFSET : 1; - unsigned int SDMA1_GFX_IB_BASE_LO : 1; - unsigned int SDMA1_GFX_IB_BASE_HI : 1; - unsigned int SDMA1_GFX_IB_SIZE : 1; - unsigned int SDMA1_GFX_SKIP_CNTL : 1; - unsigned int SDMA1_GFX_CONTEXT_STATUS : 1; - unsigned int SDMA1_GFX_DOORBELL : 1; - unsigned int SDMA1_GFX_CONTEXT_CNTL : 1; - unsigned int RESERVED : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_CONTEXT_REG_TYPE1__VI { - struct { - unsigned int VOID_REG0 : 7; - unsigned int SDMA1_GFX_VIRTUAL_ADDR : 1; - unsigned int SDMA1_GFX_APE1_CNTL : 1; - unsigned int SDMA1_GFX_DOORBELL_LOG : 1; - unsigned int SDMA1_GFX_WATERMARK : 1; - unsigned int VOID_REG2 : 1; - unsigned int SDMA1_GFX_CSA_ADDR_LO : 1; - unsigned int SDMA1_GFX_CSA_ADDR_HI : 1; - unsigned int VOID_REG3 : 1; - unsigned int SDMA1_GFX_IB_SUB_REMAIN : 1; - unsigned int SDMA1_GFX_PREEMPT : 1; - unsigned int SDMA1_GFX_DUMMY_REG : 1; - unsigned int RESERVED : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_CONTEXT_REG_TYPE2__VI { - struct { - unsigned int SDMA1_GFX_MIDCMD_DATA0 : 1; - unsigned int SDMA1_GFX_MIDCMD_DATA1 : 1; - unsigned int SDMA1_GFX_MIDCMD_DATA2 : 1; - unsigned int SDMA1_GFX_MIDCMD_DATA3 : 1; - unsigned int SDMA1_GFX_MIDCMD_DATA4 : 1; - unsigned int SDMA1_GFX_MIDCMD_DATA5 : 1; - unsigned int SDMA1_GFX_MIDCMD_CNTL : 1; - unsigned int RESERVED : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_EDC_CONFIG__VI { - struct { - unsigned int : 1; - unsigned int DIS_EDC : 1; - unsigned int ECC_INT_ENABLE : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_CSA_ADDR_HI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_CSA_ADDR_LO__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_DOORBELL__VI { - struct { - unsigned int OFFSET : 21; - unsigned int : 7; - unsigned int ENABLE : 1; - unsigned int : 1; - unsigned int CAPTURED : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_DOORBELL_LOG__VI { - struct { - unsigned int BE_ERROR : 1; - unsigned int : 1; - unsigned int DATA : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_DUMMY_REG__VI { - struct { - unsigned int DUMMY : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_IB_SUB_REMAIN__VI { - struct { - unsigned int SIZE : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_MIDCMD_CNTL__VI { - struct { - unsigned int DATA_VALID : 1; - unsigned int COPY_MODE : 1; - unsigned int : 2; - unsigned int SPLIT_STATE : 4; - unsigned int ALLOW_PREEMPT : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_MIDCMD_DATA0__VI { - struct { - unsigned int DATA0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_MIDCMD_DATA1__VI { - struct { - unsigned int DATA1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_MIDCMD_DATA2__VI { - struct { - unsigned int DATA2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_MIDCMD_DATA3__VI { - struct { - unsigned int DATA3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_MIDCMD_DATA4__VI { - struct { - unsigned int DATA4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_MIDCMD_DATA5__VI { - struct { - unsigned int DATA5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_PREEMPT__VI { - struct { - unsigned int IB_PREEMPT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_GFX_WATERMARK__VI { - struct { - unsigned int RD_OUTSTANDING : 12; - unsigned int : 4; - unsigned int WR_OUTSTANDING : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_ID__VI { - struct { - unsigned int DEVICE_ID : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_PERF_REG_TYPE0__VI { - struct { - unsigned int SDMA1_PERFMON_CNTL : 1; - unsigned int SDMA1_PERFCOUNTER0_RESULT : 1; - unsigned int SDMA1_PERFCOUNTER1_RESULT : 1; - unsigned int RESERVED_31_3 : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_POWER_CNTL_IDLE__VI { - struct { - unsigned int DELAY1 : 16; - unsigned int DELAY2 : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_PUB_REG_TYPE0__VI { - struct { - unsigned int SDMA1_UCODE_ADDR : 1; - unsigned int SDMA1_UCODE_DATA : 1; - unsigned int SDMA1_POWER_CNTL : 1; - unsigned int SDMA1_CLK_CTRL : 1; - unsigned int SDMA1_CNTL : 1; - unsigned int SDMA1_CHICKEN_BITS : 1; - unsigned int SDMA1_TILING_CONFIG : 1; - unsigned int SDMA1_HASH : 1; - unsigned int : 1; - unsigned int SDMA1_SEM_WAIT_FAIL_TIMER_CNTL : 1; - unsigned int SDMA1_RB_RPTR_FETCH : 1; - unsigned int SDMA1_IB_OFFSET_FETCH : 1; - unsigned int SDMA1_PROGRAM : 1; - unsigned int SDMA1_STATUS_REG : 1; - unsigned int SDMA1_STATUS1_REG : 1; - unsigned int SDMA1_RD_BURST_CNTL : 1; - unsigned int RESERVED_16 : 1; - unsigned int RESERVED_17 : 1; - unsigned int SDMA1_F32_CNTL : 1; - unsigned int SDMA1_FREEZE : 1; - unsigned int SDMA1_PHASE0_QUANTUM : 1; - unsigned int SDMA1_PHASE1_QUANTUM : 1; - unsigned int VOID_REG0 : 4; - unsigned int SDMA1_EDC_CONFIG : 1; - unsigned int SDMA1_BA_THRESHOLD : 1; - unsigned int SDMA1_DEVICE_ID : 1; - unsigned int : 1; - unsigned int RESERVED : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_PUB_REG_TYPE1__VI { - struct { - unsigned int SDMA1_VM_CNTL : 1; - unsigned int SDMA1_VM_CTX_LO : 1; - unsigned int SDMA1_VM_CTX_HI : 1; - unsigned int SDMA1_STATUS2_REG : 1; - unsigned int SDMA1_VM_CTX_CNTL : 1; - unsigned int RESERVED : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RD_BURST_CNTL__VI { - struct { - unsigned int RD_BURST : 2; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_CSA_ADDR_HI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_CSA_ADDR_LO__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_DUMMY_REG__VI { - struct { - unsigned int DUMMY : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_IB_SUB_REMAIN__VI { - struct { - unsigned int SIZE : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_MIDCMD_CNTL__VI { - struct { - unsigned int DATA_VALID : 1; - unsigned int COPY_MODE : 1; - unsigned int : 2; - unsigned int SPLIT_STATE : 4; - unsigned int ALLOW_PREEMPT : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_MIDCMD_DATA0__VI { - struct { - unsigned int DATA0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_MIDCMD_DATA1__VI { - struct { - unsigned int DATA1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_MIDCMD_DATA2__VI { - struct { - unsigned int DATA2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_MIDCMD_DATA3__VI { - struct { - unsigned int DATA3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_MIDCMD_DATA4__VI { - struct { - unsigned int DATA4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_MIDCMD_DATA5__VI { - struct { - unsigned int DATA5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_PREEMPT__VI { - struct { - unsigned int IB_PREEMPT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC0_WATERMARK__VI { - struct { - unsigned int RD_OUTSTANDING : 12; - unsigned int : 4; - unsigned int WR_OUTSTANDING : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_CSA_ADDR_HI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_CSA_ADDR_LO__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_DUMMY_REG__VI { - struct { - unsigned int DUMMY : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_IB_SUB_REMAIN__VI { - struct { - unsigned int SIZE : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_MIDCMD_CNTL__VI { - struct { - unsigned int DATA_VALID : 1; - unsigned int COPY_MODE : 1; - unsigned int : 2; - unsigned int SPLIT_STATE : 4; - unsigned int ALLOW_PREEMPT : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_MIDCMD_DATA0__VI { - struct { - unsigned int DATA0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_MIDCMD_DATA1__VI { - struct { - unsigned int DATA1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_MIDCMD_DATA2__VI { - struct { - unsigned int DATA2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_MIDCMD_DATA3__VI { - struct { - unsigned int DATA3 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_MIDCMD_DATA4__VI { - struct { - unsigned int DATA4 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_MIDCMD_DATA5__VI { - struct { - unsigned int DATA5 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_PREEMPT__VI { - struct { - unsigned int IB_PREEMPT : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_RLC1_WATERMARK__VI { - struct { - unsigned int RD_OUTSTANDING : 12; - unsigned int : 4; - unsigned int WR_OUTSTANDING : 9; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_STATUS2_REG__VI { - struct { - unsigned int ID : 2; - unsigned int F32_INSTR_PTR : 14; - unsigned int CMD_OP : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_VERSION__VI { - struct { - unsigned int VALUE : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_VF_ENABLE__VI { - struct { - unsigned int VF_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_VIRT_RESET_REQ__VI { - struct { - unsigned int VF : 16; - unsigned int : 15; - unsigned int PF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_VM_CNTL__VI { - struct { - unsigned int CMD : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_VM_CTX_CNTL__VI { - struct { - unsigned int PRIV : 1; - unsigned int : 3; - unsigned int VMID : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_VM_CTX_HI__VI { - struct { - unsigned int ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SDMA1_VM_CTX_LO__VI { - struct { - unsigned int : 2; - unsigned int ADDR : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_ACTIVE_FCN_ID__VI { - struct { - unsigned int VFID : 4; - unsigned int : 27; - unsigned int VF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_MAILBOX_CLIENTCONFIG_EXTRA__VI { - struct { - unsigned int VCE1_CLIENT0 : 5; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_PERFCOUNTER0_RESULT__VI { - struct { - unsigned int PERF_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_PERFCOUNTER1_RESULT__VI { - struct { - unsigned int PERF_COUNT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_PERFMON_CNTL__VI { - struct { - unsigned int PERF_ENABLE0 : 1; - unsigned int PERF_CLEAR0 : 1; - unsigned int PERF_SEL0 : 8; - unsigned int PERF_ENABLE1 : 1; - unsigned int PERF_CLEAR1 : 1; - unsigned int PERF_SEL1 : 8; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_VF_ENABLE__VI { - struct { - unsigned int VALUE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SEM_VIRT_RESET_REQ__VI { - struct { - unsigned int VF : 16; - unsigned int : 15; - unsigned int PF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SE_CAC_CGTT_CLK_CTRL__VI { - struct { - unsigned int ON_DELAY : 4; - unsigned int OFF_HYSTERESIS : 8; - unsigned int : 18; - unsigned int SOFT_OVERRIDE_DYN : 1; - unsigned int SOFT_OVERRIDE_REG : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION0__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION1__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION10__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION11__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION12__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION13__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION14__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION15__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION16__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION17__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION2__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION3__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION4__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION5__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION6__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION7__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION8__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SINK_DESCRIPTION9__VI { - struct { - unsigned int DESCRIPTION : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMBUS_BACO_DUMMY__VI { - struct { - unsigned int SMBUS_BACO_DUMMY_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_BIF_VDDGFX_PWR_STATUS__VI { - struct { - unsigned int VDDGFX_GFX_PWR_OFF : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_CONTROL__VI { - struct { - unsigned int DISPLAY0_FORCE_VBI : 1; - unsigned int DISPLAY1_FORCE_VBI : 1; - unsigned int DISPLAY2_FORCE_VBI : 1; - unsigned int DISPLAY3_FORCE_VBI : 1; - unsigned int DISPLAY4_FORCE_VBI : 1; - unsigned int DISPLAY5_FORCE_VBI : 1; - unsigned int DISPLAY_V0_FORCE_VBI : 1; - unsigned int : 9; - unsigned int SMU_DC_INT_CLEAR : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_DATA_0__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_DATA_1__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_DATA_2__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_DATA_3__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_DATA_4__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_DATA_5__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_DATA_6__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_DATA_7__VI { - struct { - unsigned int SMC_IND_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_INDEX_0__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_INDEX_1__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_INDEX_2__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_INDEX_3__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_INDEX_4__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_INDEX_5__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_INDEX_6__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_IND_INDEX_7__VI { - struct { - unsigned int SMC_IND_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_INTERRUPT_CONTROL__VI { - struct { - unsigned int DC_SMU_INT_ENABLE : 1; - unsigned int : 3; - unsigned int DC_SMU_INT_STATUS : 1; - unsigned int : 11; - unsigned int DC_SMU_INT_EVENT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_MP1_RLC2MP_RESP__VI { - struct { - unsigned int CONTENT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_MP1_SRBM2P_MSG_5__VI { - struct { - unsigned int CONTENT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_0__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_1__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_10__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_100__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_101__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_102__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_103__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_104__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_105__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_106__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_107__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_108__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_109__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_11__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_110__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_111__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_112__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_113__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_114__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_115__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_116__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_117__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_118__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_119__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_12__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_120__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_121__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_122__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_123__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_124__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_125__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_126__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_127__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_13__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_14__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_15__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_16__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_17__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_18__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_19__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_2__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_20__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_21__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_22__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_23__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_24__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_25__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_26__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_27__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_28__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_29__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_3__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_30__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_31__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_32__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_33__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_34__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_35__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_36__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_37__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_38__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_39__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_4__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_40__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_41__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_42__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_43__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_44__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_45__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_46__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_47__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_48__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_49__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_5__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_50__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_51__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_52__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_53__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_54__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_55__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_56__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_57__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_58__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_59__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_6__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_60__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_61__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_62__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_63__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_64__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_65__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_66__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_67__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_68__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_69__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_7__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_70__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_71__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_72__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_73__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_74__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_75__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_76__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_77__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_78__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_79__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_8__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_80__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_81__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_82__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_83__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_84__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_85__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_86__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_87__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_88__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_89__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_9__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_90__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_91__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_92__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_93__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_94__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_95__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_96__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_97__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_98__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_PM_STATUS_99__VI { - struct { - unsigned int DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SMU_RLC_RESPONSE__VI { - struct { - unsigned int RESP : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SM_CONTROL2__VI { - struct { - unsigned int SM_MODE : 3; - unsigned int : 1; - unsigned int SM_FRAME_ALTERNATE : 1; - unsigned int SM_FIELD_ALTERNATE : 1; - unsigned int : 2; - unsigned int SM_FORCE_NEXT_FRAME_POL : 2; - unsigned int : 6; - unsigned int SM_FORCE_NEXT_TOP_POL : 2; - unsigned int : 6; - unsigned int SM_CURRENT_FRAME_POL : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_1__VI { - struct { - unsigned int RefClockFrequency : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_10__VI { - struct { - unsigned int G5TrainTime : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_11__VI { - struct { - unsigned int DelayMpllPwron : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_12__VI { - struct { - unsigned int VoltageChangeTimeout : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_13__VI { - struct { - unsigned int HandshakeDisables : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_14__VI { - struct { - unsigned int DisplayPhy4Config : 8; - unsigned int DisplayPhy3Config : 8; - unsigned int DisplayPhy2Config : 8; - unsigned int DisplayPhy1Config : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_15__VI { - struct { - unsigned int DisplayPhy8Config : 8; - unsigned int DisplayPhy7Config : 8; - unsigned int DisplayPhy6Config : 8; - unsigned int DisplayPhy5Config : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_16__VI { - struct { - unsigned int AverageGraphicsActivity : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_17__VI { - struct { - unsigned int AverageMemoryActivity : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_18__VI { - struct { - unsigned int AverageGioActivity : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_19__VI { - struct { - unsigned int PCIeDpmEnabledLevels : 8; - unsigned int LClkDpmEnabledLevels : 8; - unsigned int MClkDpmEnabledLevels : 8; - unsigned int SClkDpmEnabledLevels : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_2__VI { - struct { - unsigned int PmTimerPeriod : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_20__VI { - struct { - unsigned int VCEDpmEnabledLevels : 8; - unsigned int ACPDpmEnabledLevels : 8; - unsigned int SAMUDpmEnabledLevels : 8; - unsigned int UVDDpmEnabledLevels : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_21__VI { - struct { - unsigned int DRAM_LOG_ADDR_H : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_22__VI { - struct { - unsigned int DRAM_LOG_ADDR_L : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_23__VI { - struct { - unsigned int DRAM_LOG_PHY_ADDR_H : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_24__VI { - struct { - unsigned int DRAM_LOG_PHY_ADDR_L : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_25__VI { - struct { - unsigned int DRAM_LOG_BUFF_SIZE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_26__VI { - struct { - unsigned int UlvEnterCount : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_27__VI { - struct { - unsigned int UlvTime : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_28__VI { - struct { - unsigned int UcodeLoadStatus : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_29__VI { - struct { - unsigned int Reserved_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_3__VI { - struct { - unsigned int FeatureEnables : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_30__VI { - struct { - unsigned int Reserved_1 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_4__VI { - struct { - unsigned int PreVBlankGap : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_5__VI { - struct { - unsigned int VBlankTimeout : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_6__VI { - struct { - unsigned int TrainTimeGap : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_7__VI { - struct { - unsigned int MvddSwitchTime : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_8__VI { - struct { - unsigned int LongestAcpiTrainTime : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SOFT_REGISTERS_TABLE_9__VI { - struct { - unsigned int AcpiDelay : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_COMPUTE_WF_CTX_SAVE__VI { - struct { - unsigned int INITIATE : 1; - unsigned int GDS_INTERRUPT_EN : 1; - unsigned int DONE_INTERRUPT_EN : 1; - unsigned int : 27; - unsigned int GDS_REQ_BUSY : 1; - unsigned int SAVE_BUSY : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_CONFIG_CNTL_2__VI { - struct { - unsigned int CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD : 4; - unsigned int CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD : 4; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_DSM_CNTL__VI { - struct { - unsigned int Sel_DSM_SPI_Irritator_data0 : 1; - unsigned int Sel_DSM_SPI_Irritator_data1 : 1; - unsigned int SPI_Enable_Single_Write : 1; - unsigned int UNUSED : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_EDC_CNT__VI { - struct { - unsigned int SED : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_GFX_CNTL__VI { - struct { - unsigned int RESET_COUNTS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_12__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_13__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_14__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_CU_15__VI { - struct { - unsigned int VGPR : 4; - unsigned int SGPR : 4; - unsigned int LDS : 4; - unsigned int WAVES : 3; - unsigned int BARRIERS : 4; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_12__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_13__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_14__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_RESOURCE_RESERVE_EN_CU_15__VI { - struct { - unsigned int EN : 1; - unsigned int TYPE_MASK : 15; - unsigned int QUEUE_MASK : 8; - unsigned int RESERVE_SPACE_ONLY : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPI_START_PHASE__VI { - struct { - unsigned int VGPR_START_PHASE : 2; - unsigned int SGPR_START_PHASE : 2; - unsigned int WAVE_START_PHASE : 2; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_CONFIG0_0__VI { - struct { - unsigned int SPMI_ENABLE : 1; - unsigned int : 1; - unsigned int SPMI_PATH_NUM_TIMING_FLOPS : 5; - unsigned int SPMI_SIGNALING_DELAY_CYCLES : 5; - unsigned int SPMI_SIGNALING_HOLD_CYCLES : 5; - unsigned int SPMI_PATH_ENABLE_DELAY_CYCLES : 5; - unsigned int SPMI_PATH_DISABLE_DELAY_CYCLES : 5; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_CONFIG1_0__VI { - struct { - unsigned int SPMI_SIGNALING_RESET_HOLD_CYCLES : 5; - unsigned int SPMI_CHAIN_SIZE : 11; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_FORCE_CLOCK_GATERS__VI { - struct { - unsigned int : 1; - unsigned int : 7; - unsigned int : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_SPARE__VI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_SPARE_EX__VI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPMI_SRAM_CLK_GATER__VI { - struct { - unsigned int : 1; - unsigned int : 10; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SPU_PORT_STATUS__VI { - struct { - unsigned int RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQC_ATC_EDC_GATCL1_CNT__VI { - struct { - unsigned int ICACHE_DATA_SEC : 8; - unsigned int : 8; - unsigned int DCACHE_DATA_SEC : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQC_DSM_CNTL__VI { - struct { - unsigned int SEL_DATA_ICACHE_BANKA : 2; - unsigned int EN_SINGLE_WR_ICACHE_BANKA : 1; - unsigned int SEL_DATA_ICACHE_BANKB : 2; - unsigned int EN_SINGLE_WR_ICACHE_BANKB : 1; - unsigned int SEL_DATA_ICACHE_BANKC : 2; - unsigned int EN_SINGLE_WR_ICACHE_BANKC : 1; - unsigned int SEL_DATA_ICACHE_BANKD : 2; - unsigned int EN_SINGLE_WR_ICACHE_BANKD : 1; - unsigned int SEL_DATA_ICACHE_GATCL1 : 2; - unsigned int EN_SINGLE_WR_ICACHE_GATCL1 : 1; - unsigned int SEL_DATA_DCACHE_BANKA : 2; - unsigned int EN_SINGLE_WR_DCACHE_BANKA : 1; - unsigned int SEL_DATA_DCACHE_BANKB : 2; - unsigned int EN_SINGLE_WR_DCACHE_BANKB : 1; - unsigned int SEL_DATA_DCACHE_BANKC : 2; - unsigned int EN_SINGLE_WR_DCACHE_BANKC : 1; - unsigned int SEL_DATA_DCACHE_BANKD : 2; - unsigned int EN_SINGLE_WR_DCACHE_BANKD : 1; - unsigned int SEL_DATA_DCACHE_GATCL1 : 2; - unsigned int EN_SINGLE_WR_DCACHE_GATCL1 : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQC_EDC_CNT__VI { - struct { - unsigned int INST_SEC : 8; - unsigned int INST_DED : 8; - unsigned int DATA_SEC : 8; - unsigned int DATA_DED : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQC_GATCL1_CNTL__VI { - struct { - unsigned int RESERVED : 18; - unsigned int DCACHE_INVALIDATE_ALL_VMID : 1; - unsigned int DCACHE_FORCE_MISS : 1; - unsigned int DCACHE_FORCE_IN_ORDER : 1; - unsigned int DCACHE_REDUCE_FIFO_DEPTH_BY_2 : 2; - unsigned int DCACHE_REDUCE_CACHE_SIZE_BY_2 : 2; - unsigned int ICACHE_INVALIDATE_ALL_VMID : 1; - unsigned int ICACHE_FORCE_MISS : 1; - unsigned int ICACHE_FORCE_IN_ORDER : 1; - unsigned int ICACHE_REDUCE_FIFO_DEPTH_BY_2 : 2; - unsigned int ICACHE_REDUCE_CACHE_SIZE_BY_2 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQC_WRITEBACK__VI { - struct { - unsigned int DWB : 1; - unsigned int DIRTY : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_DSM_CNTL__VI { - struct { - unsigned int WAVEFRONT_STALL_0 : 1; - unsigned int WAVEFRONT_STALL_1 : 1; - unsigned int SPI_BACKPRESSURE_0 : 1; - unsigned int SPI_BACKPRESSURE_1 : 1; - unsigned int : 4; - unsigned int SEL_DSM_SGPR_IRRITATOR_DATA0 : 1; - unsigned int SEL_DSM_SGPR_IRRITATOR_DATA1 : 1; - unsigned int SGPR_ENABLE_SINGLE_WRITE : 1; - unsigned int : 5; - unsigned int SEL_DSM_LDS_IRRITATOR_DATA0 : 1; - unsigned int SEL_DSM_LDS_IRRITATOR_DATA1 : 1; - unsigned int LDS_ENABLE_SINGLE_WRITE01 : 1; - unsigned int SEL_DSM_LDS_IRRITATOR_DATA2 : 1; - unsigned int SEL_DSM_LDS_IRRITATOR_DATA3 : 1; - unsigned int LDS_ENABLE_SINGLE_WRITE23 : 1; - unsigned int : 2; - unsigned int SEL_DSM_SP_IRRITATOR_DATA0 : 1; - unsigned int SEL_DSM_SP_IRRITATOR_DATA1 : 1; - unsigned int SP_ENABLE_SINGLE_WRITE : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_EDC_DED_CNT__VI { - struct { - unsigned int LDS_DED : 8; - unsigned int SGPR_DED : 8; - unsigned int VGPR_DED : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_EDC_INFO__VI { - struct { - unsigned int WAVE_ID : 4; - unsigned int SIMD_ID : 2; - unsigned int SOURCE : 3; - unsigned int VM_ID : 4; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_EDC_SEC_CNT__VI { - struct { - unsigned int LDS_SEC : 8; - unsigned int SGPR_SEC : 8; - unsigned int VGPR_SEC : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_M0_GPR_IDX_WORD__VI { - struct { - unsigned int INDEX : 8; - unsigned int : 4; - unsigned int VSRC0_REL : 1; - unsigned int VSRC1_REL : 1; - unsigned int VSRC2_REL : 1; - unsigned int VDST_REL : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_SMEM_0__VI { - struct { - unsigned int SBASE : 6; - unsigned int SDATA : 7; - unsigned int : 3; - unsigned int GLC : 1; - unsigned int IMM : 1; - unsigned int OP : 8; - unsigned int ENCODING : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_SMEM_1__VI { - struct { - unsigned int OFFSET : 20; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_VOP_DPP__VI { - struct { - unsigned int SRC0 : 8; - unsigned int DPP_CTRL : 9; - unsigned int : 2; - unsigned int BOUND_CTRL : 1; - unsigned int SRC0_NEG : 1; - unsigned int SRC0_ABS : 1; - unsigned int SRC1_NEG : 1; - unsigned int SRC1_ABS : 1; - unsigned int BANK_MASK : 4; - unsigned int ROW_MASK : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_VOP_SDWA__VI { - struct { - unsigned int SRC0 : 8; - unsigned int DST_SEL : 3; - unsigned int DST_UNUSED : 2; - unsigned int CLAMP : 1; - unsigned int : 2; - unsigned int SRC0_SEL : 3; - unsigned int SRC0_SEXT : 1; - unsigned int SRC0_NEG : 1; - unsigned int SRC0_ABS : 1; - unsigned int : 2; - unsigned int SRC1_SEL : 3; - unsigned int SRC1_SEXT : 1; - unsigned int SRC1_NEG : 1; - unsigned int SRC1_ABS : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WAVE_IB_DBG1__VI { - struct { - unsigned int IXNACK : 1; - unsigned int XNACK : 1; - unsigned int TA_NEED_RESET : 1; - unsigned int : 1; - unsigned int XCNT : 4; - unsigned int QCNT : 4; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WREXEC_EXEC_HI__VI { - struct { - unsigned int ADDR_HI : 16; - unsigned int : 10; - unsigned int FIRST_WAVE : 1; - unsigned int ATC : 1; - unsigned int MTYPE : 3; - unsigned int MSB : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SQ_WREXEC_EXEC_LO__VI { - struct { - unsigned int ADDR_LO : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_CREDIT_RECOVER__VI { - struct { - unsigned int CREDIT_RECOVER_BIF : 1; - unsigned int CREDIT_RECOVER_SMU : 1; - unsigned int CREDIT_RECOVER_DC : 1; - unsigned int CREDIT_RECOVER_GIONB : 1; - unsigned int CREDIT_RECOVER_ACP : 1; - unsigned int CREDIT_RECOVER_XDMA : 1; - unsigned int CREDIT_RECOVER_ODE : 1; - unsigned int CREDIT_RECOVER_REGBB : 1; - unsigned int CREDIT_RECOVER_VP8 : 1; - unsigned int CREDIT_RECOVER_GRBM : 1; - unsigned int CREDIT_RECOVER_UVD : 1; - unsigned int CREDIT_RECOVER_VCE0 : 1; - unsigned int CREDIT_RECOVER_VCE1 : 1; - unsigned int CREDIT_RECOVER_ISP : 1; - unsigned int CREDIT_RECOVER_SAM : 1; - unsigned int CREDIT_RECOVER_MCB : 1; - unsigned int CREDIT_RECOVER_MCC0 : 1; - unsigned int CREDIT_RECOVER_MCC1 : 1; - unsigned int CREDIT_RECOVER_MCC2 : 1; - unsigned int CREDIT_RECOVER_MCC3 : 1; - unsigned int CREDIT_RECOVER_MCC4 : 1; - unsigned int CREDIT_RECOVER_MCC5 : 1; - unsigned int CREDIT_RECOVER_MCC6 : 1; - unsigned int CREDIT_RECOVER_MCC7 : 1; - unsigned int CREDIT_RECOVER_MCD0 : 1; - unsigned int CREDIT_RECOVER_MCD1 : 1; - unsigned int CREDIT_RECOVER_MCD2 : 1; - unsigned int CREDIT_RECOVER_MCD3 : 1; - unsigned int CREDIT_RECOVER_MCD4 : 1; - unsigned int CREDIT_RECOVER_MCD5 : 1; - unsigned int CREDIT_RECOVER_MCD6 : 1; - unsigned int CREDIT_RECOVER_MCD7 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_CREDIT_RECOVER_CNTL__VI { - struct { - unsigned int CREDIT_RECOVER_TIME : 12; - unsigned int : 19; - unsigned int CREDIT_RECOVER_ENABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_CREDIT_RESET__VI { - struct { - unsigned int CREDIT_RESET_BIF : 1; - unsigned int CREDIT_RESET_SMU : 1; - unsigned int CREDIT_RESET_DC : 1; - unsigned int CREDIT_RESET_GIONB : 1; - unsigned int CREDIT_RESET_ACP : 1; - unsigned int CREDIT_RESET_XDMA : 1; - unsigned int CREDIT_RESET_ODE : 1; - unsigned int CREDIT_RESET_REGBB : 1; - unsigned int CREDIT_RESET_VP8 : 1; - unsigned int CREDIT_RESET_GRBM : 1; - unsigned int CREDIT_RESET_UVD : 1; - unsigned int CREDIT_RESET_VCE0 : 1; - unsigned int CREDIT_RESET_VCE1 : 1; - unsigned int CREDIT_RESET_ISP : 1; - unsigned int CREDIT_RESET_SAM : 1; - unsigned int CREDIT_RESET_MCB : 1; - unsigned int CREDIT_RESET_MCC0 : 1; - unsigned int CREDIT_RESET_MCC1 : 1; - unsigned int CREDIT_RESET_MCC2 : 1; - unsigned int CREDIT_RESET_MCC3 : 1; - unsigned int CREDIT_RESET_MCC4 : 1; - unsigned int CREDIT_RESET_MCC5 : 1; - unsigned int CREDIT_RESET_MCC6 : 1; - unsigned int CREDIT_RESET_MCC7 : 1; - unsigned int CREDIT_RESET_MCD0 : 1; - unsigned int CREDIT_RESET_MCD1 : 1; - unsigned int CREDIT_RESET_MCD2 : 1; - unsigned int CREDIT_RESET_MCD3 : 1; - unsigned int CREDIT_RESET_MCD4 : 1; - unsigned int CREDIT_RESET_MCD5 : 1; - unsigned int CREDIT_RESET_MCD6 : 1; - unsigned int CREDIT_RESET_MCD7 : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_DEBUG_SNAPSHOT2__VI { - struct { - unsigned int VCE1_RDY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_DSM_TRIG_CNTL0__VI { - struct { - unsigned int DSM_TRIG_ADDR : 16; - unsigned int DSM_TRIG_OP : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_DSM_TRIG_CNTL1__VI { - struct { - unsigned int DSM_TRIG_WD : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_DSM_TRIG_MASK0__VI { - struct { - unsigned int DSM_TRIG_ADDR_MASK : 16; - unsigned int DSM_TRIG_OP_MASK : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_DSM_TRIG_MASK1__VI { - struct { - unsigned int DSM_TRIG_WD_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_FIREWALL_ERROR_ADDR__VI { - struct { - unsigned int : 2; - unsigned int ACCESS_ADDRESS : 16; - unsigned int : 1; - unsigned int ACCESS_VF : 1; - unsigned int ACCESS_VFID : 4; - unsigned int : 7; - unsigned int FIREWALL_VIOLATION : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_FIREWALL_ERROR_SRC__VI { - struct { - unsigned int ACCESS_REQUESTER_BIF : 1; - unsigned int ACCESS_REQUESTER_ACP : 1; - unsigned int ACCESS_REQUESTER_SAMSCP : 1; - unsigned int ACCESS_REQUESTER_SAMMSP : 1; - unsigned int : 1; - unsigned int ACCESS_REQUESTER_TST : 1; - unsigned int ACCESS_REQUESTER_SDMA3 : 1; - unsigned int ACCESS_REQUESTER_SDMA2 : 1; - unsigned int ACCESS_REQUESTER_SDMA1 : 1; - unsigned int ACCESS_REQUESTER_SDMA0 : 1; - unsigned int ACCESS_REQUESTER_UVD : 1; - unsigned int ACCESS_REQUESTER_VCE0 : 1; - unsigned int ACCESS_REQUESTER_GRBM : 1; - unsigned int ACCESS_REQUESTER_SMU : 1; - unsigned int ACCESS_REQUESTER_PEER : 1; - unsigned int ACCESS_REQUESTER_CPU : 1; - unsigned int ACCESS_REQUESTER_ISP : 1; - unsigned int ACCESS_REQUESTER_VCE1 : 1; - unsigned int ACCESS_REQUESTER_RLCHYP : 1; - unsigned int ACCESS_REQUESTER_SMUHYP : 1; - unsigned int ACCESS_REQUESTER_BIFHYP : 1; - unsigned int : 3; - unsigned int RAERR_FIREWALL_VIOLATION : 1; - unsigned int RAERR_HAR_REGIONSIZE_OVERFLOW : 1; - unsigned int RAERR_BIF_ADDR_OVERFLOW : 1; - unsigned int RAERR_P2SRP_REGIONSIZE_OVERFLOW : 1; - unsigned int RAERR_P2SRP_FIREWALL_VIOLATION : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_GFX_CNTL_DATA__VI { - struct { - unsigned int PIPEID : 2; - unsigned int MEID : 2; - unsigned int VMID : 4; - unsigned int QUEUEID : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_GFX_CNTL_SELECT__VI { - struct { - unsigned int SRBM_GFX_CNTL_SEL : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_ISP_CLKEN_CNTL__VI { - struct { - unsigned int PREFIX_DELAY_CNT : 4; - unsigned int : 4; - unsigned int POST_DELAY_CNT : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_ISP_DOMAIN_ADDR0__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_ISP_DOMAIN_ADDR1__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_ISP_DOMAIN_ADDR2__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_MC_DOMAIN_ADDR0__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_MC_DOMAIN_ADDR1__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_MC_DOMAIN_ADDR2__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_MC_DOMAIN_ADDR3__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_MC_DOMAIN_ADDR4__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_MC_DOMAIN_ADDR5__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_MC_DOMAIN_ADDR6__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_READ_CNTL__VI { - struct { - unsigned int READ_TIMEOUT : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_READ_ERROR2__VI { - struct { - unsigned int READ_REQUESTER_ACP : 1; - unsigned int READ_REQUESTER_ISP : 1; - unsigned int READ_REQUESTER_VCE1 : 1; - unsigned int : 20; - unsigned int READ_VF : 1; - unsigned int READ_VFID : 4; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SAM_DOMAIN_ADDR0__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SAM_DOMAIN_ADDR1__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SAM_DOMAIN_ADDR2__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SDMA_DOMAIN_ADDR0__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SDMA_DOMAIN_ADDR1__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SDMA_DOMAIN_ADDR2__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SDMA_DOMAIN_ADDR3__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_STATUS3__VI { - struct { - unsigned int MCC0_BUSY : 1; - unsigned int MCC1_BUSY : 1; - unsigned int MCC2_BUSY : 1; - unsigned int MCC3_BUSY : 1; - unsigned int MCC4_BUSY : 1; - unsigned int MCC5_BUSY : 1; - unsigned int MCC6_BUSY : 1; - unsigned int MCC7_BUSY : 1; - unsigned int MCD0_BUSY : 1; - unsigned int MCD1_BUSY : 1; - unsigned int MCD2_BUSY : 1; - unsigned int MCD3_BUSY : 1; - unsigned int MCD4_BUSY : 1; - unsigned int MCD5_BUSY : 1; - unsigned int MCD6_BUSY : 1; - unsigned int MCD7_BUSY : 1; - unsigned int : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SYS_DOMAIN_ADDR0__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SYS_DOMAIN_ADDR1__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SYS_DOMAIN_ADDR2__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SYS_DOMAIN_ADDR3__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SYS_DOMAIN_ADDR4__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SYS_DOMAIN_ADDR5__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_SYS_DOMAIN_ADDR6__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_UVD_DOMAIN_ADDR0__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_UVD_DOMAIN_ADDR1__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_UVD_DOMAIN_ADDR2__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_VCE_DOMAIN_ADDR0__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_VCE_DOMAIN_ADDR1__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_VCE_DOMAIN_ADDR2__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_VF_ENABLE__VI { - struct { - unsigned int VF_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_VIRT_CNTL__VI { - struct { - unsigned int VF_WRITE_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_VIRT_RESET_REQ__VI { - struct { - unsigned int VF : 16; - unsigned int : 15; - unsigned int PF : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_VP8_CLKEN_CNTL__VI { - struct { - unsigned int PREFIX_DELAY_CNT : 4; - unsigned int : 4; - unsigned int POST_DELAY_CNT : 5; - unsigned int : 19; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SRBM_VP8_DOMAIN_ADDR0__VI { - struct { - unsigned int ADDR_LO : 16; - unsigned int ADDR_HI : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_COMMAND_0__VI { - struct { - unsigned int : 15; - unsigned int BIF_STRAPREG_RESET : 1; - unsigned int BIF0_GLOBAL_RESET : 1; - unsigned int BIF0_CALIB_RESET : 1; - unsigned int BIF0_CORE_RESET : 1; - unsigned int BIF0_REGISTER_RESET : 1; - unsigned int BIF0_PHY_RESET : 1; - unsigned int BIF0_STICKY_RESET : 1; - unsigned int BIF0_CONFIG_RESET : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_COMMAND_1__VI { - struct { - unsigned int SWITCHCLK : 1; - unsigned int : 1; - unsigned int RESETLANEMUX : 1; - unsigned int RESETWRAPREGS : 1; - unsigned int RESETSRBM0 : 1; - unsigned int RESETSRBM1 : 1; - unsigned int RESETLC : 1; - unsigned int : 1; - unsigned int SYNCIDLEPIF0 : 1; - unsigned int SYNCIDLEPIF1 : 1; - unsigned int : 3; - unsigned int RESETMNTR : 1; - unsigned int RESETHLTR : 1; - unsigned int RESETCPM : 1; - unsigned int RESETPIF0 : 1; - unsigned int RESETPIF1 : 1; - unsigned int : 2; - unsigned int RESETIMPARB0 : 1; - unsigned int RESETIMPARB1 : 1; - unsigned int : 2; - unsigned int RESETPHY0 : 1; - unsigned int RESETPHY1 : 1; - unsigned int : 2; - unsigned int TOGGLESTRAP : 1; - unsigned int CMDCFGEN : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_COMMAND_STATUS__VI { - struct { - unsigned int RECONFIGURE : 1; - unsigned int ATOMIC_RESET : 1; - unsigned int : 14; - unsigned int RESET_COMPLETE : 1; - unsigned int WAIT_STATE : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_CONTROL_0__VI { - struct { - unsigned int : 15; - unsigned int BIF_STRAPREG_RESETRCEN : 1; - unsigned int BIF0_GLOBAL_RESETRCEN : 1; - unsigned int BIF0_CALIB_RESETRCEN : 1; - unsigned int BIF0_CORE_RESETRCEN : 1; - unsigned int BIF0_REGISTER_RESETRCEN : 1; - unsigned int BIF0_PHY_RESETRCEN : 1; - unsigned int BIF0_STICKY_RESETRCEN : 1; - unsigned int BIF0_CONFIG_RESETRCEN : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_CONTROL_1__VI { - struct { - unsigned int SWITCHCLK_RCEN : 1; - unsigned int : 1; - unsigned int RESETLANEMUX_RCEN : 1; - unsigned int RESETWRAPREGS_RCEN : 1; - unsigned int RESETSRBM0_RCEN : 1; - unsigned int RESETSRBM1_RCEN : 1; - unsigned int RESETLC_RCEN : 1; - unsigned int : 1; - unsigned int SYNCIDLEPIF0_RCEN : 1; - unsigned int SYNCIDLEPIF1_RCEN : 1; - unsigned int : 3; - unsigned int RESETMNTR_RCEN : 1; - unsigned int RESETHLTR_RCEN : 1; - unsigned int RESETCPM_RCEN : 1; - unsigned int RESETPIF0_RCEN : 1; - unsigned int RESETPIF1_RCEN : 1; - unsigned int : 2; - unsigned int RESETIMPARB0_RCEN : 1; - unsigned int RESETIMPARB1_RCEN : 1; - unsigned int : 2; - unsigned int RESETPHY0_RCEN : 1; - unsigned int RESETPHY1_RCEN : 1; - unsigned int : 2; - unsigned int STRAPVLD_RCEN : 1; - unsigned int CMDCFG_RCEN : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_CONTROL_2__VI { - struct { - unsigned int : 15; - unsigned int BIF_STRAPREG_RESETATEN : 1; - unsigned int BIF0_GLOBAL_RESETATEN : 1; - unsigned int BIF0_CALIB_RESETATEN : 1; - unsigned int BIF0_CORE_RESETATEN : 1; - unsigned int BIF0_REGISTER_RESETATEN : 1; - unsigned int BIF0_PHY_RESETATEN : 1; - unsigned int BIF0_STICKY_RESETATEN : 1; - unsigned int BIF0_CONFIG_RESETATEN : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_CONTROL_3__VI { - struct { - unsigned int SWITCHCLK_ATEN : 1; - unsigned int : 1; - unsigned int RESETLANEMUX_ATEN : 1; - unsigned int RESETWRAPREGS_ATEN : 1; - unsigned int RESETSRBM0_ATEN : 1; - unsigned int RESETSRBM1_ATEN : 1; - unsigned int RESETLC_ATEN : 1; - unsigned int : 1; - unsigned int SYNCIDLEPIF0_ATEN : 1; - unsigned int SYNCIDLEPIF1_ATEN : 1; - unsigned int : 3; - unsigned int RESETMNTR_ATEN : 1; - unsigned int RESETHLTR_ATEN : 1; - unsigned int RESETCPM_ATEN : 1; - unsigned int RESETPIF0_ATEN : 1; - unsigned int RESETPIF1_ATEN : 1; - unsigned int : 2; - unsigned int RESETIMPARB0_ATEN : 1; - unsigned int RESETIMPARB1_ATEN : 1; - unsigned int : 2; - unsigned int RESETPHY0_ATEN : 1; - unsigned int RESETPHY1_ATEN : 1; - unsigned int : 2; - unsigned int STRAPVLD_ATEN : 1; - unsigned int CMDCFG_ATEN : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_CONTROL_4__VI { - struct { - unsigned int : 14; - unsigned int BIF_STRAPREG_WRRESETEN : 1; - unsigned int : 1; - unsigned int BIF0_GLOBAL_WRRESETEN : 1; - unsigned int BIF0_CALIB_WRRESETEN : 1; - unsigned int BIF0_CORE_WRRESETEN : 1; - unsigned int BIF0_REGISTER_WRRESETEN : 1; - unsigned int BIF0_PHY_WRRESETEN : 1; - unsigned int BIF0_STICKY_WRRESETEN : 1; - unsigned int BIF0_CONFIG_WRRESETEN : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_CONTROL_5__VI { - struct { - unsigned int WRSWITCHCLK_EN : 1; - unsigned int : 1; - unsigned int WRRESETLANEMUX_EN : 1; - unsigned int WRRESETWRAPREGS_EN : 1; - unsigned int WRRESETSRBM0_EN : 1; - unsigned int WRRESETSRBM1_EN : 1; - unsigned int WRRESETLC_EN : 1; - unsigned int : 1; - unsigned int WRSYNCIDLEPIF0_EN : 1; - unsigned int WRSYNCIDLEPIF1_EN : 1; - unsigned int : 3; - unsigned int WRRESETMNTR_EN : 1; - unsigned int WRRESETHLTR_EN : 1; - unsigned int WRRESETCPM_EN : 1; - unsigned int WRRESETPIF0_EN : 1; - unsigned int WRRESETPIF1_EN : 1; - unsigned int : 2; - unsigned int WRRESETIMPARB0_EN : 1; - unsigned int WRRESETIMPARB1_EN : 1; - unsigned int : 2; - unsigned int WRRESETPHY0_EN : 1; - unsigned int WRRESETPHY1_EN : 1; - unsigned int : 2; - unsigned int WRSTRAPVLD_EN : 1; - unsigned int WRCMDCFG_EN : 1; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_CONTROL_6__VI { - struct { - unsigned int WARMRESET_EN : 1; - unsigned int : 7; - unsigned int CONNECTWITHWRAPREGS_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_EP_COMMAND_0__VI { - struct { - unsigned int EP_CFG_RESET_ONLY : 1; - unsigned int EP_SOFT_RESET : 1; - unsigned int EP_DRV_RESET : 1; - unsigned int : 5; - unsigned int EP_HOT_RESET : 1; - unsigned int EP_LNKDWN_RESET : 1; - unsigned int EP_LNKDIS_RESET : 1; - unsigned int : 5; - unsigned int EP_FLR0_RESET : 1; - unsigned int EP_FLR1_RESET : 1; - unsigned int EP_FLR2_RESET : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_EP_CONTROL_0__VI { - struct { - unsigned int EP_CFG_RESET_ONLY_EN : 1; - unsigned int EP_SOFT_RESET_EN : 1; - unsigned int EP_DRV_RESET_EN : 1; - unsigned int : 5; - unsigned int EP_HOT_RESET_EN : 1; - unsigned int EP_LNKDWN_RESET_EN : 1; - unsigned int EP_LNKDIS_RESET_EN : 1; - unsigned int : 5; - unsigned int EP_FLR0_RESET_EN : 1; - unsigned int EP_FLR1_RESET_EN : 1; - unsigned int EP_FLR2_RESET_EN : 1; - unsigned int EP_CFG_WR_RESET_EN : 1; - unsigned int EP_FLR_DISABLE_CFG_RST : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SWRST_GENERAL_CONTROL__VI { - struct { - unsigned int RECONFIGURE_EN : 1; - unsigned int ATOMIC_RESET_EN : 1; - unsigned int RESET_PERIOD : 3; - unsigned int : 3; - unsigned int WAIT_LINKUP : 1; - unsigned int FORCE_REGIDLE : 1; - unsigned int BLOCK_ON_IDLE : 1; - unsigned int : 1; - unsigned int CONFIG_XFER_MODE : 1; - unsigned int MUXSEL_XFER_MODE : 1; - unsigned int HLDTRAIN_XFER_MODE : 1; - unsigned int : 1; - unsigned int BYPASS_HOLD : 1; - unsigned int BYPASS_PIF_HOLD : 1; - unsigned int : 10; - unsigned int EP_COMPLT_CHK_EN : 1; - unsigned int EP_COMPLT_WAIT_TMR : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_BLEND_OPT_CONTROL__VI { - struct { - unsigned int MRT0_COLOR_OPT_DISABLE : 1; - unsigned int MRT0_ALPHA_OPT_DISABLE : 1; - unsigned int : 2; - unsigned int MRT1_COLOR_OPT_DISABLE : 1; - unsigned int MRT1_ALPHA_OPT_DISABLE : 1; - unsigned int : 2; - unsigned int MRT2_COLOR_OPT_DISABLE : 1; - unsigned int MRT2_ALPHA_OPT_DISABLE : 1; - unsigned int : 2; - unsigned int MRT3_COLOR_OPT_DISABLE : 1; - unsigned int MRT3_ALPHA_OPT_DISABLE : 1; - unsigned int : 2; - unsigned int MRT4_COLOR_OPT_DISABLE : 1; - unsigned int MRT4_ALPHA_OPT_DISABLE : 1; - unsigned int : 2; - unsigned int MRT5_COLOR_OPT_DISABLE : 1; - unsigned int MRT5_ALPHA_OPT_DISABLE : 1; - unsigned int : 2; - unsigned int MRT6_COLOR_OPT_DISABLE : 1; - unsigned int MRT6_ALPHA_OPT_DISABLE : 1; - unsigned int : 2; - unsigned int MRT7_COLOR_OPT_DISABLE : 1; - unsigned int MRT7_ALPHA_OPT_DISABLE : 1; - unsigned int : 1; - unsigned int PIXEN_ZERO_OPT_DISABLE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_BLEND_OPT_EPSILON__VI { - struct { - unsigned int MRT0_EPSILON : 4; - unsigned int MRT1_EPSILON : 4; - unsigned int MRT2_EPSILON : 4; - unsigned int MRT3_EPSILON : 4; - unsigned int MRT4_EPSILON : 4; - unsigned int MRT5_EPSILON : 4; - unsigned int MRT6_EPSILON : 4; - unsigned int MRT7_EPSILON : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_MRT0_BLEND_OPT__VI { - struct { - unsigned int COLOR_SRC_OPT : 3; - unsigned int : 1; - unsigned int COLOR_DST_OPT : 3; - unsigned int : 1; - unsigned int COLOR_COMB_FCN : 3; - unsigned int : 5; - unsigned int ALPHA_SRC_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_DST_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_MRT1_BLEND_OPT__VI { - struct { - unsigned int COLOR_SRC_OPT : 3; - unsigned int : 1; - unsigned int COLOR_DST_OPT : 3; - unsigned int : 1; - unsigned int COLOR_COMB_FCN : 3; - unsigned int : 5; - unsigned int ALPHA_SRC_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_DST_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_MRT2_BLEND_OPT__VI { - struct { - unsigned int COLOR_SRC_OPT : 3; - unsigned int : 1; - unsigned int COLOR_DST_OPT : 3; - unsigned int : 1; - unsigned int COLOR_COMB_FCN : 3; - unsigned int : 5; - unsigned int ALPHA_SRC_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_DST_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_MRT3_BLEND_OPT__VI { - struct { - unsigned int COLOR_SRC_OPT : 3; - unsigned int : 1; - unsigned int COLOR_DST_OPT : 3; - unsigned int : 1; - unsigned int COLOR_COMB_FCN : 3; - unsigned int : 5; - unsigned int ALPHA_SRC_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_DST_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_MRT4_BLEND_OPT__VI { - struct { - unsigned int COLOR_SRC_OPT : 3; - unsigned int : 1; - unsigned int COLOR_DST_OPT : 3; - unsigned int : 1; - unsigned int COLOR_COMB_FCN : 3; - unsigned int : 5; - unsigned int ALPHA_SRC_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_DST_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_MRT5_BLEND_OPT__VI { - struct { - unsigned int COLOR_SRC_OPT : 3; - unsigned int : 1; - unsigned int COLOR_DST_OPT : 3; - unsigned int : 1; - unsigned int COLOR_COMB_FCN : 3; - unsigned int : 5; - unsigned int ALPHA_SRC_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_DST_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_MRT6_BLEND_OPT__VI { - struct { - unsigned int COLOR_SRC_OPT : 3; - unsigned int : 1; - unsigned int COLOR_DST_OPT : 3; - unsigned int : 1; - unsigned int COLOR_COMB_FCN : 3; - unsigned int : 5; - unsigned int ALPHA_SRC_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_DST_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_MRT7_BLEND_OPT__VI { - struct { - unsigned int COLOR_SRC_OPT : 3; - unsigned int : 1; - unsigned int COLOR_DST_OPT : 3; - unsigned int : 1; - unsigned int COLOR_COMB_FCN : 3; - unsigned int : 5; - unsigned int ALPHA_SRC_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_DST_OPT : 3; - unsigned int : 1; - unsigned int ALPHA_COMB_FCN : 3; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SX_PS_DOWNCONVERT__VI { - struct { - unsigned int MRT0 : 4; - unsigned int MRT1 : 4; - unsigned int MRT2 : 4; - unsigned int MRT3 : 4; - unsigned int MRT4 : 4; - unsigned int MRT5 : 4; - unsigned int MRT6 : 4; - unsigned int MRT7 : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SYMCLKA_CLOCK_ENABLE__VI { - struct { - unsigned int SYMCLKA_CLOCK_ENABLE : 1; - unsigned int : 3; - unsigned int SYMCLKA_FE_FORCE_EN : 1; - unsigned int : 3; - unsigned int SYMCLKA_FE_FORCE_SRC : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SYMCLKB_CLOCK_ENABLE__VI { - struct { - unsigned int SYMCLKB_CLOCK_ENABLE : 1; - unsigned int : 3; - unsigned int SYMCLKB_FE_FORCE_EN : 1; - unsigned int : 3; - unsigned int SYMCLKB_FE_FORCE_SRC : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SYMCLKC_CLOCK_ENABLE__VI { - struct { - unsigned int SYMCLKC_CLOCK_ENABLE : 1; - unsigned int : 3; - unsigned int SYMCLKC_FE_FORCE_EN : 1; - unsigned int : 3; - unsigned int SYMCLKC_FE_FORCE_SRC : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SYMCLKD_CLOCK_ENABLE__VI { - struct { - unsigned int SYMCLKD_CLOCK_ENABLE : 1; - unsigned int : 3; - unsigned int SYMCLKD_FE_FORCE_EN : 1; - unsigned int : 3; - unsigned int SYMCLKD_FE_FORCE_SRC : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SYMCLKE_CLOCK_ENABLE__VI { - struct { - unsigned int SYMCLKE_CLOCK_ENABLE : 1; - unsigned int : 3; - unsigned int SYMCLKE_FE_FORCE_EN : 1; - unsigned int : 3; - unsigned int SYMCLKE_FE_FORCE_SRC : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SYMCLKF_CLOCK_ENABLE__VI { - struct { - unsigned int SYMCLKF_CLOCK_ENABLE : 1; - unsigned int : 3; - unsigned int SYMCLKF_FE_FORCE_EN : 1; - unsigned int : 3; - unsigned int SYMCLKF_FE_FORCE_SRC : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SYMCLKG_CLOCK_ENABLE__VI { - struct { - unsigned int SYMCLKG_CLOCK_ENABLE : 1; - unsigned int : 3; - unsigned int SYMCLKG_FE_FORCE_EN : 1; - unsigned int : 3; - unsigned int SYMCLKG_FE_FORCE_SRC : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SYS_GRBM_GFX_INDEX_DATA__VI { - struct { - unsigned int INSTANCE_INDEX : 8; - unsigned int SH_INDEX : 8; - unsigned int SE_INDEX : 8; - unsigned int : 5; - unsigned int SH_BROADCAST_WRITES : 1; - unsigned int INSTANCE_BROADCAST_WRITES : 1; - unsigned int SE_BROADCAST_WRITES : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union SYS_GRBM_GFX_INDEX_SELECT__VI { - struct { - unsigned int SYS_GRBM_GFX_INDEX_SEL : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_DSM_CNTL__VI { - struct { - unsigned int CACHE_RAM_IRRITATOR_DATA_SEL : 2; - unsigned int CACHE_RAM_IRRITATOR_SINGLE_WRITE : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_EDC_CNT__VI { - struct { - unsigned int SEC_COUNT : 8; - unsigned int : 8; - unsigned int DED_COUNT : 8; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCC_EXE_DISABLE__VI { - struct { - unsigned int : 1; - unsigned int EXE_DISABLE : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_ATC_EDC_GATCL1_CNT__VI { - struct { - unsigned int DATA_SEC : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_CNTL2__VI { - struct { - unsigned int LS_DISABLE_CLOCKS : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_DSM_CNTL__VI { - struct { - unsigned int CACHE_RAM_IRRITATOR_DATA_SEL : 2; - unsigned int CACHE_RAM_IRRITATOR_SINGLE_WRITE : 1; - unsigned int LFIFO_RAM_IRRITATOR_DATA_SEL : 2; - unsigned int LFIFO_RAM_IRRITATOR_SINGLE_WRITE : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_EDC_CNT__VI { - struct { - unsigned int SEC_COUNT : 8; - unsigned int LFIFO_SED_COUNT : 8; - unsigned int DED_COUNT : 8; - unsigned int UNUSED : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_GATCL1_CNTL__VI { - struct { - unsigned int : 25; - unsigned int INVALIDATE_ALL_VMID : 1; - unsigned int FORCE_MISS : 1; - unsigned int FORCE_IN_ORDER : 1; - unsigned int REDUCE_FIFO_DEPTH_BY_2 : 2; - unsigned int REDUCE_CACHE_SIZE_BY_2 : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TCP_GATCL1_DSM_CNTL__VI { - struct { - unsigned int SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0 : 1; - unsigned int SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1 : 1; - unsigned int TCP_GATCL1_ENABLE_SINGLE_WRITE_A : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TDC_MV_AVERAGE__VI { - struct { - unsigned int IDD : 16; - unsigned int IDDC : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TDC_STATUS__VI { - struct { - unsigned int VDD_Boost : 8; - unsigned int VDD_Throttle : 8; - unsigned int VDDC_Boost : 8; - unsigned int VDDC_Throttle : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TDC_VRM_LIMIT__VI { - struct { - unsigned int IDD : 16; - unsigned int IDDC : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union TD_DSM_CNTL__VI { - struct { - unsigned int FORCE_SEDB_0 : 1; - unsigned int FORCE_SEDB_1 : 1; - unsigned int EN_SINGLE_WR_SEDB : 1; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON0_STATUS__VI { - struct { - unsigned int CURRENT_RDI : 5; - unsigned int MEAS_DONE : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON1_STATUS__VI { - struct { - unsigned int CURRENT_RDI : 5; - unsigned int MEAS_DONE : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_CSR_RD__VI { - struct { - unsigned int READ_DATA : 12; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_CSR_WR__VI { - struct { - unsigned int CSR_WRITE : 1; - unsigned int CSR_READ : 1; - unsigned int CSR_ADDR : 10; - unsigned int WRITE_DATA : 12; - unsigned int SPARE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_CTRL__VI { - struct { - unsigned int POWER_DOWN : 1; - unsigned int BGADJ : 8; - unsigned int BGADJ_MODE : 1; - unsigned int TMON_PAUSE : 1; - unsigned int INT_MEAS_EN : 1; - unsigned int DEBUG_MODE : 1; - unsigned int EN_CFG_SERDES : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_CTRL2__VI { - struct { - unsigned int RDIL_PRESENT : 16; - unsigned int RDIR_PRESENT : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_DEBUG__VI { - struct { - unsigned int DEBUG_RDI : 5; - unsigned int DEBUG_Z : 11; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_INT_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL0_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL10_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL11_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL12_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL13_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL14_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL15_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL1_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL2_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL3_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL4_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL5_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL6_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL7_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL8_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIL9_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR0_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR10_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR11_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR12_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR13_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR14_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR15_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR1_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR2_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR3_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR4_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR5_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR6_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR7_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR8_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_RDIR9_DATA__VI { - struct { - unsigned int Z : 11; - unsigned int VALID : 1; - unsigned int TEMP : 12; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union THM_TMON2_STATUS__VI { - struct { - unsigned int CURRENT_RDI : 5; - unsigned int MEAS_DONE : 1; - unsigned int : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYA_CHANNEL_XBAR_CNTL__VI { - struct { - unsigned int UNIPHY_CHANNEL0_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL1_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL2_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL3_XBAR_SOURCE : 2; - unsigned int : 2; - unsigned int UNIPHY_LINK_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYA_LINK_CNTL__VI { - struct { - unsigned int UNIPHY_PFREQCHG : 1; - unsigned int : 3; - unsigned int UNIPHY_PIXVLD_RESET : 1; - unsigned int : 3; - unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3; - unsigned int : 1; - unsigned int UNIPHY_CHANNEL0_INVERT : 1; - unsigned int UNIPHY_CHANNEL1_INVERT : 1; - unsigned int UNIPHY_CHANNEL2_INVERT : 1; - unsigned int UNIPHY_CHANNEL3_INVERT : 1; - unsigned int : 4; - unsigned int UNIPHY_LANE_STAGGER_DELAY : 3; - unsigned int : 1; - unsigned int UNIPHY_LINK_ENABLE_HPD_MASK : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYB_CHANNEL_XBAR_CNTL__VI { - struct { - unsigned int UNIPHY_CHANNEL0_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL1_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL2_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL3_XBAR_SOURCE : 2; - unsigned int : 2; - unsigned int UNIPHY_LINK_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYB_LINK_CNTL__VI { - struct { - unsigned int UNIPHY_PFREQCHG : 1; - unsigned int : 3; - unsigned int UNIPHY_PIXVLD_RESET : 1; - unsigned int : 3; - unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3; - unsigned int : 1; - unsigned int UNIPHY_CHANNEL0_INVERT : 1; - unsigned int UNIPHY_CHANNEL1_INVERT : 1; - unsigned int UNIPHY_CHANNEL2_INVERT : 1; - unsigned int UNIPHY_CHANNEL3_INVERT : 1; - unsigned int : 4; - unsigned int UNIPHY_LANE_STAGGER_DELAY : 3; - unsigned int : 1; - unsigned int UNIPHY_LINK_ENABLE_HPD_MASK : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYC_CHANNEL_XBAR_CNTL__VI { - struct { - unsigned int UNIPHY_CHANNEL0_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL1_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL2_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL3_XBAR_SOURCE : 2; - unsigned int : 2; - unsigned int UNIPHY_LINK_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYC_LINK_CNTL__VI { - struct { - unsigned int UNIPHY_PFREQCHG : 1; - unsigned int : 3; - unsigned int UNIPHY_PIXVLD_RESET : 1; - unsigned int : 3; - unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3; - unsigned int : 1; - unsigned int UNIPHY_CHANNEL0_INVERT : 1; - unsigned int UNIPHY_CHANNEL1_INVERT : 1; - unsigned int UNIPHY_CHANNEL2_INVERT : 1; - unsigned int UNIPHY_CHANNEL3_INVERT : 1; - unsigned int : 4; - unsigned int UNIPHY_LANE_STAGGER_DELAY : 3; - unsigned int : 1; - unsigned int UNIPHY_LINK_ENABLE_HPD_MASK : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYD_CHANNEL_XBAR_CNTL__VI { - struct { - unsigned int UNIPHY_CHANNEL0_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL1_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL2_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL3_XBAR_SOURCE : 2; - unsigned int : 2; - unsigned int UNIPHY_LINK_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYD_LINK_CNTL__VI { - struct { - unsigned int UNIPHY_PFREQCHG : 1; - unsigned int : 3; - unsigned int UNIPHY_PIXVLD_RESET : 1; - unsigned int : 3; - unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3; - unsigned int : 1; - unsigned int UNIPHY_CHANNEL0_INVERT : 1; - unsigned int UNIPHY_CHANNEL1_INVERT : 1; - unsigned int UNIPHY_CHANNEL2_INVERT : 1; - unsigned int UNIPHY_CHANNEL3_INVERT : 1; - unsigned int : 4; - unsigned int UNIPHY_LANE_STAGGER_DELAY : 3; - unsigned int : 1; - unsigned int UNIPHY_LINK_ENABLE_HPD_MASK : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYE_CHANNEL_XBAR_CNTL__VI { - struct { - unsigned int UNIPHY_CHANNEL0_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL1_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL2_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL3_XBAR_SOURCE : 2; - unsigned int : 2; - unsigned int UNIPHY_LINK_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYE_LINK_CNTL__VI { - struct { - unsigned int UNIPHY_PFREQCHG : 1; - unsigned int : 3; - unsigned int UNIPHY_PIXVLD_RESET : 1; - unsigned int : 3; - unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3; - unsigned int : 1; - unsigned int UNIPHY_CHANNEL0_INVERT : 1; - unsigned int UNIPHY_CHANNEL1_INVERT : 1; - unsigned int UNIPHY_CHANNEL2_INVERT : 1; - unsigned int UNIPHY_CHANNEL3_INVERT : 1; - unsigned int : 4; - unsigned int UNIPHY_LANE_STAGGER_DELAY : 3; - unsigned int : 1; - unsigned int UNIPHY_LINK_ENABLE_HPD_MASK : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYF_CHANNEL_XBAR_CNTL__VI { - struct { - unsigned int UNIPHY_CHANNEL0_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL1_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL2_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL3_XBAR_SOURCE : 2; - unsigned int : 2; - unsigned int UNIPHY_LINK_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYF_LINK_CNTL__VI { - struct { - unsigned int UNIPHY_PFREQCHG : 1; - unsigned int : 3; - unsigned int UNIPHY_PIXVLD_RESET : 1; - unsigned int : 3; - unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3; - unsigned int : 1; - unsigned int UNIPHY_CHANNEL0_INVERT : 1; - unsigned int UNIPHY_CHANNEL1_INVERT : 1; - unsigned int UNIPHY_CHANNEL2_INVERT : 1; - unsigned int UNIPHY_CHANNEL3_INVERT : 1; - unsigned int : 4; - unsigned int UNIPHY_LANE_STAGGER_DELAY : 3; - unsigned int : 1; - unsigned int UNIPHY_LINK_ENABLE_HPD_MASK : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYG_CHANNEL_XBAR_CNTL__VI { - struct { - unsigned int UNIPHY_CHANNEL0_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL1_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL2_XBAR_SOURCE : 2; - unsigned int : 6; - unsigned int UNIPHY_CHANNEL3_XBAR_SOURCE : 2; - unsigned int : 2; - unsigned int UNIPHY_LINK_ENABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHYG_LINK_CNTL__VI { - struct { - unsigned int UNIPHY_PFREQCHG : 1; - unsigned int : 3; - unsigned int UNIPHY_PIXVLD_RESET : 1; - unsigned int : 3; - unsigned int UNIPHY_MINIMUM_PIXVLD_LOW_DURATION : 3; - unsigned int : 1; - unsigned int UNIPHY_CHANNEL0_INVERT : 1; - unsigned int UNIPHY_CHANNEL1_INVERT : 1; - unsigned int UNIPHY_CHANNEL2_INVERT : 1; - unsigned int UNIPHY_CHANNEL3_INVERT : 1; - unsigned int : 4; - unsigned int UNIPHY_LANE_STAGGER_DELAY : 3; - unsigned int : 1; - unsigned int UNIPHY_LINK_ENABLE_HPD_MASK : 2; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_ANG_BIST_CNTL__VI { - struct { - unsigned int UNIPHY_TEST_RX_EN : 1; - unsigned int UNIPHY_ANG_BIST_RESET : 1; - unsigned int : 6; - unsigned int UNIPHY_RX_BIAS : 4; - unsigned int : 4; - unsigned int UNIPHY_ANG_BIST_ERROR : 5; - unsigned int : 3; - unsigned int UNIPHY_PRESETB : 1; - unsigned int UNIPHY_BIST_EN : 1; - unsigned int UNIPHY_CLK_CH_EN4_DFT : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_DEBUG__VI { - struct { - unsigned int : 12; - unsigned int DEBUG0 : 10; - unsigned int DEBUG1 : 3; - unsigned int DBG_SEL : 2; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_PSW_AB__VI { - struct { - unsigned int UNIPHY_IMPCAL_PSW_LINKA : 15; - unsigned int : 1; - unsigned int UNIPHY_IMPCAL_PSW_LINKB : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_PSW_CD__VI { - struct { - unsigned int UNIPHY_IMPCAL_PSW_LINKC : 15; - unsigned int : 1; - unsigned int UNIPHY_IMPCAL_PSW_LINKD : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_IMPCAL_PSW_EF__VI { - struct { - unsigned int UNIPHY_IMPCAL_PSW_LINKE : 15; - unsigned int : 1; - unsigned int UNIPHY_IMPCAL_PSW_LINKF : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED0__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED1__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED10__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED11__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED12__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED13__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED14__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED15__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED16__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED17__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED18__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED19__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED2__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED20__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED21__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED22__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED23__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED24__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED25__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED26__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED27__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED28__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED29__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED3__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED30__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED31__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED4__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED5__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED6__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED7__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED8__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_MACRO_CNTL_RESERVED9__VI { - struct { - unsigned int UNIPHY_MACRO_CNTL_RESERVED : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_PLL_CONTROL1__VI { - struct { - unsigned int UNIPHY_PLL_ENABLE : 1; - unsigned int UNIPHY_PLL_RESET : 1; - unsigned int UNIPHY_PLL_EXT_RESET_EN : 1; - unsigned int UNIPHY_PLL_CLK_EN : 1; - unsigned int UNIPHY_PLL_CLKPH_EN : 4; - unsigned int UNIPHY_PLL_LF_CNTL : 7; - unsigned int : 1; - unsigned int UNIPHY_PLL_BW_CNTL : 8; - unsigned int UNIPHY_PLL_TEST_BYPCLK_SRC : 1; - unsigned int UNIPHY_PLL_TEST_BYPCLK_EN : 1; - unsigned int UNIPHY_PLL_TEST_VCTL_ADC_EN : 1; - unsigned int : 1; - unsigned int UNIPHY_VCO_MODE : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_PLL_CONTROL2__VI { - struct { - unsigned int UNIPHY_PLL_DISPCLK_MODE : 2; - unsigned int UNIPHY_DPLLSEL : 2; - unsigned int UNIPHY_IDCLK_SEL : 1; - unsigned int UNIPHY_IPCIE_REFCLK_SEL : 1; - unsigned int UNIPHY_IXTALIN_SEL : 1; - unsigned int : 1; - unsigned int UNIPHY_PLL_REFCLK_SRC : 3; - unsigned int UNIPHY_PCIEREF_CLK_EN : 1; - unsigned int UNIPHY_IDCLK_EN : 1; - unsigned int UNIPHY_CLKINV : 1; - unsigned int : 2; - unsigned int UNIPHY_PLL_VTOI_BIAS_CNTL : 1; - unsigned int : 2; - unsigned int UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS : 1; - unsigned int UNIPHY_PDIVFRAC_SEL : 1; - unsigned int : 3; - unsigned int UNIPHY_PLL_REFDIV : 5; - unsigned int UNIPHY_PDIV_SEL : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_PLL_FBDIV__VI { - struct { - unsigned int : 2; - unsigned int UNIPHY_PLL_FBDIV_FRACTION : 14; - unsigned int UNIPHY_PLL_FBDIV : 12; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_PLL_SS_CNTL__VI { - struct { - unsigned int UNIPHY_PLL_SS_STEP_NUM : 12; - unsigned int UNIPHY_PLL_DSMOD_EN : 1; - unsigned int UNIPHY_PLL_SS_EN : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_PLL_SS_STEP_SIZE__VI { - struct { - unsigned int UNIPHY_PLL_SS_STEP_SIZE : 26; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_POWER_CONTROL__VI { - struct { - unsigned int UNIPHY_BGPDN : 1; - unsigned int UNIPHY_RST_LOGIC : 1; - unsigned int UNIPHY_BIASREF_SEL : 1; - unsigned int : 5; - unsigned int UNIPHY_BGADJ1P00 : 4; - unsigned int UNIPHY_BGADJ1P25 : 4; - unsigned int UNIPHY_BGADJ0P45 : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_REG_TEST_OUTPUT2__VI { - struct { - unsigned int UNIPHY_TX : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_TPG_CONTROL__VI { - struct { - unsigned int UNIPHY_STATIC_TEST_PATTERN : 10; - unsigned int : 6; - unsigned int UNIPHY_TPG_EN : 1; - unsigned int UNIPHY_TPG_SEL : 3; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_TPG_SEED__VI { - struct { - unsigned int UNIPHY_TPG_SEED : 23; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_TX_CONTROL1__VI { - struct { - unsigned int UNIPHY_PREMPH_STR0 : 3; - unsigned int : 1; - unsigned int UNIPHY_PREMPH_STR1 : 3; - unsigned int : 1; - unsigned int UNIPHY_PREMPH_STR2 : 3; - unsigned int : 1; - unsigned int UNIPHY_PREMPH_STR3 : 3; - unsigned int : 1; - unsigned int UNIPHY_PREMPH_STR4 : 3; - unsigned int : 1; - unsigned int UNIPHY_TX_VS0 : 2; - unsigned int UNIPHY_TX_VS1 : 2; - unsigned int UNIPHY_TX_VS2 : 2; - unsigned int UNIPHY_TX_VS3 : 2; - unsigned int UNIPHY_TX_VS4 : 2; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_TX_CONTROL2__VI { - struct { - unsigned int UNIPHY_PREMPH0_PC : 2; - unsigned int : 2; - unsigned int UNIPHY_PREMPH1_PC : 2; - unsigned int : 2; - unsigned int UNIPHY_PREMPH2_PC : 2; - unsigned int : 2; - unsigned int UNIPHY_PREMPH3_PC : 2; - unsigned int : 2; - unsigned int UNIPHY_PREMPH4_PC : 2; - unsigned int : 2; - unsigned int UNIPHY_PREMPH_SEL : 1; - unsigned int UNIPHY_RT0_CPSEL : 2; - unsigned int UNIPHY_RT1_CPSEL : 2; - unsigned int UNIPHY_RT2_CPSEL : 2; - unsigned int UNIPHY_RT3_CPSEL : 2; - unsigned int UNIPHY_RT4_CPSEL : 2; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_TX_CONTROL3__VI { - struct { - unsigned int UNIPHY_PREMPH_PW_CLK : 2; - unsigned int UNIPHY_PREMPH_PW_DAT : 2; - unsigned int UNIPHY_PREMPH_CS_CLK : 4; - unsigned int UNIPHY_PREMPH_CS_DAT : 4; - unsigned int UNIPHY_PREMPH_STR_CLK : 3; - unsigned int : 1; - unsigned int UNIPHY_PREMPH_STR_DAT : 3; - unsigned int : 1; - unsigned int UNIPHY_PESEL0 : 1; - unsigned int UNIPHY_PESEL1 : 1; - unsigned int UNIPHY_PESEL2 : 1; - unsigned int UNIPHY_PESEL3 : 1; - unsigned int UNIPHY_TX_VS_ADJ : 5; - unsigned int : 2; - unsigned int UNIPHY_LVDS_PULLDWN : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNIPHY_TX_CONTROL4__VI { - struct { - unsigned int UNIPHY_TX_NVS_CLK : 5; - unsigned int UNIPHY_TX_NVS_DAT : 5; - unsigned int : 2; - unsigned int UNIPHY_TX_PVS_CLK : 5; - unsigned int UNIPHY_TX_PVS_DAT : 5; - unsigned int : 2; - unsigned int UNIPHY_TX_OP_CLK : 3; - unsigned int : 1; - unsigned int UNIPHY_TX_OP_DAT : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_CRC_CONTROL__VI { - struct { - unsigned int UNP_CRC_ENABLE : 1; - unsigned int : 1; - unsigned int UNP_CRC_SOURCE_SEL : 3; - unsigned int : 3; - unsigned int UNP_CRC_LINE_SEL : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_CRC_CURRENT__VI { - struct { - unsigned int UNP_CRC_CURRENT : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_CRC_LAST__VI { - struct { - unsigned int UNP_CRC_LAST : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_CRC_MASK__VI { - struct { - unsigned int UNP_CRC_MASK : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_DEBUG__VI { - struct { - unsigned int UNP_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_DEBUG2__VI { - struct { - unsigned int UNP_DEBUG2 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_CONTROL__VI { - struct { - unsigned int GRPH_DEPTH : 2; - unsigned int GRPH_NUM_BANKS : 2; - unsigned int GRPH_Z : 2; - unsigned int GRPH_BANK_WIDTH : 2; - unsigned int GRPH_FORMAT : 3; - unsigned int GRPH_BANK_HEIGHT : 2; - unsigned int GRPH_TILE_SPLIT : 3; - unsigned int GRPH_ADDRESS_TRANSLATION_ENABLE : 1; - unsigned int GRPH_PRIVILEGED_ACCESS_ENABLE : 1; - unsigned int GRPH_MACRO_TILE_ASPECT : 2; - unsigned int GRPH_ARRAY_MODE : 4; - unsigned int GRPH_PIPE_CONFIG : 5; - unsigned int GRPH_MICRO_TILE_MODE : 2; - unsigned int GRPH_COLOR_EXPANSION_MODE : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_CONTROL_EXP__VI { - struct { - unsigned int VIDEO_FORMAT : 3; - unsigned int : 29; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_DFQ_CONTROL__VI { - struct { - unsigned int GRPH_DFQ_RESET : 1; - unsigned int : 3; - unsigned int GRPH_DFQ_SIZE : 3; - unsigned int : 1; - unsigned int GRPH_DFQ_MIN_FREE_ENTRIES : 3; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_DFQ_STATUS__VI { - struct { - unsigned int GRPH_PRIMARY_DFQ_NUM_ENTRIES : 4; - unsigned int GRPH_SECONDARY_DFQ_NUM_ENTRIES : 4; - unsigned int GRPH_DFQ_RESET_FLAG : 1; - unsigned int GRPH_DFQ_RESET_ACK : 1; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_ENABLE__VI { - struct { - unsigned int GRPH_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_FLIP_RATE_CNTL__VI { - struct { - unsigned int GRPH_FLIP_RATE : 3; - unsigned int GRPH_FLIP_RATE_ENABLE : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_INTERRUPT_CONTROL__VI { - struct { - unsigned int GRPH_PFLIP_INT_MASK : 1; - unsigned int : 7; - unsigned int GRPH_PFLIP_INT_TYPE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_INTERRUPT_STATUS__VI { - struct { - unsigned int GRPH_PFLIP_INT_OCCURRED : 1; - unsigned int : 7; - unsigned int GRPH_PFLIP_INT_CLEAR : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_PITCH_C__VI { - struct { - unsigned int GRPH_PITCH_C : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_PITCH_L__VI { - struct { - unsigned int GRPH_PITCH_L : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__VI { - struct { - unsigned int GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C : 1; - unsigned int : 7; - unsigned int GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI { - struct { - unsigned int GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI { - struct { - unsigned int GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__VI { - struct { - unsigned int GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L : 1; - unsigned int : 7; - unsigned int GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__VI { - struct { - unsigned int GRPH_PRIMARY_DFQ_ENABLE_C : 1; - unsigned int : 7; - unsigned int GRPH_PRIMARY_SURFACE_ADDRESS_C : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__VI { - struct { - unsigned int GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__VI { - struct { - unsigned int GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__VI { - struct { - unsigned int GRPH_PRIMARY_DFQ_ENABLE_L : 1; - unsigned int : 7; - unsigned int GRPH_PRIMARY_SURFACE_ADDRESS_L : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__VI { - struct { - unsigned int GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C : 1; - unsigned int : 7; - unsigned int GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI { - struct { - unsigned int GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI { - struct { - unsigned int GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__VI { - struct { - unsigned int GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L : 1; - unsigned int : 7; - unsigned int GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__VI { - struct { - unsigned int GRPH_SECONDARY_DFQ_ENABLE_C : 1; - unsigned int : 7; - unsigned int GRPH_SECONDARY_SURFACE_ADDRESS_C : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__VI { - struct { - unsigned int GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__VI { - struct { - unsigned int GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__VI { - struct { - unsigned int GRPH_SECONDARY_DFQ_ENABLE_L : 1; - unsigned int : 7; - unsigned int GRPH_SECONDARY_SURFACE_ADDRESS_L : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_STEREOSYNC_FLIP__VI { - struct { - unsigned int GRPH_STEREOSYNC_FLIP_EN : 1; - unsigned int : 3; - unsigned int GRPH_STEREOSYNC_FLIP_MODE : 2; - unsigned int : 2; - unsigned int GRPH_STACK_INTERLACE_FLIP_EN : 1; - unsigned int : 3; - unsigned int GRPH_STACK_INTERLACE_FLIP_MODE : 2; - unsigned int : 2; - unsigned int GRPH_PRIMARY_SURFACE_PENDING : 1; - unsigned int GRPH_SECONDARY_SURFACE_PENDING : 1; - unsigned int GRPH_PRIMARY_BOTTOM_SURFACE_PENDING : 1; - unsigned int GRPH_SECONDARY_BOTTOM_SURFACE_PENDING : 1; - unsigned int : 8; - unsigned int GRPH_STEREOSYNC_SELECT_DISABLE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__VI { - struct { - unsigned int GRPH_SURFACE_ADDRESS_HIGH_INUSE_C : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__VI { - struct { - unsigned int GRPH_SURFACE_ADDRESS_HIGH_INUSE_L : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SURFACE_ADDRESS_INUSE_C__VI { - struct { - unsigned int : 8; - unsigned int GRPH_SURFACE_ADDRESS_INUSE_C : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SURFACE_ADDRESS_INUSE_L__VI { - struct { - unsigned int : 8; - unsigned int GRPH_SURFACE_ADDRESS_INUSE_L : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SURFACE_OFFSET_X_C__VI { - struct { - unsigned int GRPH_SURFACE_OFFSET_X_C : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SURFACE_OFFSET_X_L__VI { - struct { - unsigned int GRPH_SURFACE_OFFSET_X_L : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SURFACE_OFFSET_Y_C__VI { - struct { - unsigned int GRPH_SURFACE_OFFSET_Y_C : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SURFACE_OFFSET_Y_L__VI { - struct { - unsigned int GRPH_SURFACE_OFFSET_Y_L : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_SWAP_CNTL__VI { - struct { - unsigned int GRPH_ENDIAN_SWAP : 2; - unsigned int : 2; - unsigned int GRPH_RED_CROSSBAR : 2; - unsigned int GRPH_GREEN_CROSSBAR : 2; - unsigned int GRPH_BLUE_CROSSBAR : 2; - unsigned int : 22; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_UPDATE__VI { - struct { - unsigned int GRPH_MODE_UPDATE_PENDING : 1; - unsigned int GRPH_MODE_UPDATE_TAKEN : 1; - unsigned int GRPH_SURFACE_UPDATE_PENDING : 1; - unsigned int GRPH_SURFACE_UPDATE_TAKEN : 1; - unsigned int : 12; - unsigned int GRPH_UPDATE_LOCK : 1; - unsigned int : 3; - unsigned int GRPH_SURFACE_IGNORE_UPDATE_LOCK : 1; - unsigned int : 3; - unsigned int GRPH_MODE_DISABLE_MULTIPLE_UPDATE : 1; - unsigned int : 3; - unsigned int GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE : 1; - unsigned int : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_X_END_C__VI { - struct { - unsigned int GRPH_X_END_C : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_X_END_L__VI { - struct { - unsigned int GRPH_X_END_L : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_X_START_C__VI { - struct { - unsigned int GRPH_X_START_C : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_X_START_L__VI { - struct { - unsigned int GRPH_X_START_L : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_Y_END_C__VI { - struct { - unsigned int GRPH_Y_END_C : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_Y_END_L__VI { - struct { - unsigned int GRPH_Y_END_L : 15; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_Y_START_C__VI { - struct { - unsigned int GRPH_Y_START_C : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_GRPH_Y_START_L__VI { - struct { - unsigned int GRPH_Y_START_L : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_HW_ROTATION__VI { - struct { - unsigned int ROTATION_ANGLE : 3; - unsigned int : 1; - unsigned int PIXEL_DROP : 1; - unsigned int : 3; - unsigned int BUFFER_MODE : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_LB_DATA_GAP_BETWEEN_CHUNK__VI { - struct { - unsigned int : 4; - unsigned int UNP_LB_GAP_BETWEEN_CHUNK : 5; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_TEST_DEBUG_DATA__VI { - struct { - unsigned int UNP_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UNP_TEST_DEBUG_INDEX__VI { - struct { - unsigned int UNP_TEST_DEBUG_INDEX : 8; - unsigned int UNP_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_CGC_CTRL2__VI { - struct { - unsigned int DYN_OCLK_RAMP_EN : 1; - unsigned int DYN_RCLK_RAMP_EN : 1; - unsigned int GATER_DIV_ID : 3; - unsigned int : 27; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_CGC_MEM_CTRL__VI { - struct { - unsigned int LMI_MC_LS_EN : 1; - unsigned int MPC_LS_EN : 1; - unsigned int MPRD_LS_EN : 1; - unsigned int WCB_LS_EN : 1; - unsigned int UDEC_RE_LS_EN : 1; - unsigned int UDEC_CM_LS_EN : 1; - unsigned int UDEC_IT_LS_EN : 1; - unsigned int UDEC_DB_LS_EN : 1; - unsigned int UDEC_MP_LS_EN : 1; - unsigned int SYS_LS_EN : 1; - unsigned int VCPU_LS_EN : 1; - unsigned int SCPU_LS_EN : 1; - unsigned int MIF_LS_EN : 1; - unsigned int LCM_LS_EN : 1; - unsigned int JPEG_LS_EN : 1; - unsigned int JPEG2_LS_EN : 1; - unsigned int LS_SET_DELAY : 4; - unsigned int LS_CLEAR_DELAY : 4; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_CGC_UDEC_STATUS__VI { - struct { - unsigned int RE_SCLK : 1; - unsigned int RE_DCLK : 1; - unsigned int RE_VCLK : 1; - unsigned int CM_SCLK : 1; - unsigned int CM_DCLK : 1; - unsigned int CM_VCLK : 1; - unsigned int IT_SCLK : 1; - unsigned int IT_DCLK : 1; - unsigned int IT_VCLK : 1; - unsigned int DB_SCLK : 1; - unsigned int DB_DCLK : 1; - unsigned int DB_VCLK : 1; - unsigned int MP_SCLK : 1; - unsigned int MP_DCLK : 1; - unsigned int MP_VCLK : 1; - unsigned int JPEG_VCLK : 1; - unsigned int JPEG_SCLK : 1; - unsigned int JPEG2_VCLK : 1; - unsigned int JPEG2_SCLK : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_JPEG_ADDR_CONFIG__VI { - struct { - unsigned int NUM_PIPES : 3; - unsigned int : 1; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int BANK_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_SHADER_ENGINES : 2; - unsigned int : 2; - unsigned int SHADER_ENGINE_TILE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_GPUS : 3; - unsigned int : 1; - unsigned int MULTI_GPU_TILE_SIZE : 2; - unsigned int : 2; - unsigned int ROW_SIZE : 2; - unsigned int NUM_LOWER_PIPES : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_ADDR_EXT2__VI { - struct { - unsigned int SCPU_ADDR_EXT : 4; - unsigned int SCPU_VM_ADDR_EXT : 4; - unsigned int SCPU_NC0_ADDR_EXT : 4; - unsigned int SCPU_NC1_ADDR_EXT : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_RBC_IB_64BIT_BAR_HIGH__VI { - struct { - unsigned int BITS_63_32 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_RBC_IB_64BIT_BAR_LOW__VI { - struct { - unsigned int BITS_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_RBC_IB_VMID__VI { - struct { - unsigned int IB_VMID : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_RBC_RB_64BIT_BAR_HIGH__VI { - struct { - unsigned int BITS_63_32 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_RBC_RB_64BIT_BAR_LOW__VI { - struct { - unsigned int BITS_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_RBC_RB_VMID__VI { - struct { - unsigned int RB_VMID : 4; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_SWAP_CNTL2__VI { - struct { - unsigned int SCPU_R_MC_SWAP : 2; - unsigned int SCPU_W_MC_SWAP : 2; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__VI { - struct { - unsigned int BITS_63_32 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__VI { - struct { - unsigned int BITS_31_0 : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_VMID_INTERNAL__VI { - struct { - unsigned int VCPU_NC0_VMID : 4; - unsigned int VCPU_NC1_VMID : 4; - unsigned int DPB_VMID : 4; - unsigned int DBW_VMID : 4; - unsigned int LBSI_VMID : 4; - unsigned int IDCT_VMID : 4; - unsigned int JPEG_VMID : 4; - unsigned int JPEG2_VMID : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_VMID_INTERNAL2__VI { - struct { - unsigned int MIF_GPGPU_VMID : 4; - unsigned int MIF_CURR_VMID : 4; - unsigned int MIF_REF_VMID : 4; - unsigned int MIF_DBW_VMID : 4; - unsigned int MIF_CM_COLOC_VMID : 4; - unsigned int MIF_BSD_VMID : 4; - unsigned int MIF_BSP_VMID : 4; - unsigned int VDMA_VMID : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_LMI_VMID_INTERNAL3__VI { - struct { - unsigned int MIF_GEN_RD0_VMID : 4; - unsigned int MIF_GEN_RD1_VMID : 4; - unsigned int MIF_GEN_WR0_VMID : 4; - unsigned int MIF_GEN_WR1_VMID : 4; - unsigned int MIF_SCLR_VMID : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MIF_CURR_ADDR_CONFIG__VI { - struct { - unsigned int NUM_PIPES : 3; - unsigned int : 1; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int BANK_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_SHADER_ENGINES : 2; - unsigned int : 2; - unsigned int SHADER_ENGINE_TILE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_GPUS : 3; - unsigned int : 1; - unsigned int MULTI_GPU_TILE_SIZE : 2; - unsigned int : 2; - unsigned int ROW_SIZE : 2; - unsigned int NUM_LOWER_PIPES : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MIF_RECON1_ADDR_CONFIG__VI { - struct { - unsigned int NUM_PIPES : 3; - unsigned int : 1; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int BANK_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_SHADER_ENGINES : 2; - unsigned int : 2; - unsigned int SHADER_ENGINE_TILE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_GPUS : 3; - unsigned int : 1; - unsigned int MULTI_GPU_TILE_SIZE : 2; - unsigned int : 2; - unsigned int ROW_SIZE : 2; - unsigned int NUM_LOWER_PIPES : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MIF_REF_ADDR_CONFIG__VI { - struct { - unsigned int NUM_PIPES : 3; - unsigned int : 1; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int BANK_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_SHADER_ENGINES : 2; - unsigned int : 2; - unsigned int SHADER_ENGINE_TILE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_GPUS : 3; - unsigned int : 1; - unsigned int MULTI_GPU_TILE_SIZE : 2; - unsigned int : 2; - unsigned int ROW_SIZE : 2; - unsigned int NUM_LOWER_PIPES : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_MIF_SCLR_ADDR_CONFIG__VI { - struct { - unsigned int NUM_PIPES : 3; - unsigned int : 1; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int BANK_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_SHADER_ENGINES : 2; - unsigned int : 2; - unsigned int SHADER_ENGINE_TILE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_GPUS : 3; - unsigned int : 1; - unsigned int MULTI_GPU_TILE_SIZE : 2; - unsigned int : 2; - unsigned int ROW_SIZE : 2; - unsigned int NUM_LOWER_PIPES : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_PGFSM_CONFIG__VI { - struct { - unsigned int UVD_PGFSM_FSM_ADDR : 8; - unsigned int UVD_PGFSM_POWER_DOWN : 1; - unsigned int UVD_PGFSM_POWER_UP : 1; - unsigned int UVD_PGFSM_P1_SELECT : 1; - unsigned int UVD_PGFSM_P2_SELECT : 1; - unsigned int UVD_PGFSM_WRITE : 1; - unsigned int UVD_PGFSM_READ : 1; - unsigned int : 14; - unsigned int UVD_PGFSM_REG_ADDR : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_PGFSM_READ_TILE1__VI { - struct { - unsigned int UVD_PGFSM_READ_TILE1_VALUE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_PGFSM_READ_TILE2__VI { - struct { - unsigned int UVD_PGFSM_READ_TILE2_VALUE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_PGFSM_READ_TILE3__VI { - struct { - unsigned int UVD_PGFSM_READ_TILE3_VALUE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_PGFSM_READ_TILE4__VI { - struct { - unsigned int UVD_PGFSM_READ_TILE4_VALUE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_PGFSM_READ_TILE5__VI { - struct { - unsigned int UVD_PGFSM_READ_TILE5_VALUE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_PGFSM_READ_TILE6__VI { - struct { - unsigned int UVD_PGFSM_READ_TILE6_VALUE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_PGFSM_READ_TILE7__VI { - struct { - unsigned int UVD_PGFSM_READ_TILE7_VALUE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_PGFSM_WRITE__VI { - struct { - unsigned int : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_POWER_STATUS__VI { - struct { - unsigned int UVD_POWER_STATUS : 2; - unsigned int UVD_PG_MODE : 1; - unsigned int UVD_STATUS_CHECK_TIMEOUT : 1; - unsigned int PWR_ON_CHECK_TIMEOUT : 1; - unsigned int PWR_OFF_CHECK_TIMEOUT : 1; - unsigned int UVD_PGFSM_TIMEOUT_MODE : 2; - unsigned int UVD_PG_EN : 1; - unsigned int PAUSE_DPG_REQ : 1; - unsigned int PAUSE_DPG_ACK : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SUVD_CGC_CTRL__VI { - struct { - unsigned int SRE_MODE : 1; - unsigned int SIT_MODE : 1; - unsigned int SMP_MODE : 1; - unsigned int SCM_MODE : 1; - unsigned int SDB_MODE : 1; - unsigned int SCLR_MODE : 1; - unsigned int UVD_SC_MODE : 1; - unsigned int : 25; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SUVD_CGC_GATE__VI { - struct { - unsigned int SRE : 1; - unsigned int SIT : 1; - unsigned int SMP : 1; - unsigned int SCM : 1; - unsigned int SDB : 1; - unsigned int SRE_H264 : 1; - unsigned int SRE_HEVC : 1; - unsigned int SIT_H264 : 1; - unsigned int SIT_HEVC : 1; - unsigned int SCM_H264 : 1; - unsigned int SCM_HEVC : 1; - unsigned int SDB_H264 : 1; - unsigned int SDB_HEVC : 1; - unsigned int SCLR : 1; - unsigned int UVD_SC : 1; - unsigned int : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_SUVD_CGC_STATUS__VI { - struct { - unsigned int SRE_VCLK : 1; - unsigned int SRE_DCLK : 1; - unsigned int SIT_DCLK : 1; - unsigned int SMP_DCLK : 1; - unsigned int SCM_DCLK : 1; - unsigned int SDB_DCLK : 1; - unsigned int SRE_H264_VCLK : 1; - unsigned int SRE_HEVC_VCLK : 1; - unsigned int SIT_H264_DCLK : 1; - unsigned int SIT_HEVC_DCLK : 1; - unsigned int SCM_H264_DCLK : 1; - unsigned int SCM_HEVC_DCLK : 1; - unsigned int SDB_H264_DCLK : 1; - unsigned int SDB_HEVC_DCLK : 1; - unsigned int SCLR_DCLK : 1; - unsigned int UVD_SC : 1; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_UDEC_ADDR_CONFIG__VI { - struct { - unsigned int NUM_PIPES : 3; - unsigned int : 1; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int BANK_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_SHADER_ENGINES : 2; - unsigned int : 2; - unsigned int SHADER_ENGINE_TILE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_GPUS : 3; - unsigned int : 1; - unsigned int MULTI_GPU_TILE_SIZE : 2; - unsigned int : 2; - unsigned int ROW_SIZE : 2; - unsigned int NUM_LOWER_PIPES : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_UDEC_DBW_ADDR_CONFIG__VI { - struct { - unsigned int NUM_PIPES : 3; - unsigned int : 1; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int BANK_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_SHADER_ENGINES : 2; - unsigned int : 2; - unsigned int SHADER_ENGINE_TILE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_GPUS : 3; - unsigned int : 1; - unsigned int MULTI_GPU_TILE_SIZE : 2; - unsigned int : 2; - unsigned int ROW_SIZE : 2; - unsigned int NUM_LOWER_PIPES : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union UVD_UDEC_DB_ADDR_CONFIG__VI { - struct { - unsigned int NUM_PIPES : 3; - unsigned int : 1; - unsigned int PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int BANK_INTERLEAVE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_SHADER_ENGINES : 2; - unsigned int : 2; - unsigned int SHADER_ENGINE_TILE_SIZE : 3; - unsigned int : 1; - unsigned int NUM_GPUS : 3; - unsigned int : 1; - unsigned int MULTI_GPU_TILE_SIZE : 2; - unsigned int : 2; - unsigned int ROW_SIZE : 2; - unsigned int NUM_LOWER_PIPES : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_INT_STATUS__VI { - struct { - unsigned int : 16; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 13; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_LMI_CACHE_CTRL__VI { - struct { - unsigned int VCPU_EN : 1; - unsigned int : 1; - unsigned int : 30; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_LMI_CTRL__VI { - struct { - unsigned int : 11; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 5; - unsigned int : 1; - unsigned int VCPU_DATA_COHERENCY_EN : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_LMI_CTRL2__VI { - struct { - unsigned int : 1; - unsigned int STALL_ARB : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 3; - unsigned int : 1; - unsigned int STALL_ARB_UMC : 1; - unsigned int : 2; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_LMI_SWAP_CNTL__VI { - struct { - unsigned int VCPU_W_MC_SWAP : 2; - unsigned int WR_MC_CID_SWAP : 12; - unsigned int : 6; - unsigned int : 6; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_LMI_SWAP_CNTL1__VI { - struct { - unsigned int VCPU_R_MC_SWAP : 2; - unsigned int RD_MC_CID_SWAP : 12; - unsigned int : 6; - unsigned int : 6; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_LMI_SWAP_CNTL2__VI { - struct { - unsigned int WR_MC_CID_SWAP : 8; - unsigned int : 6; - unsigned int : 4; - unsigned int : 2; - unsigned int : 4; - unsigned int : 2; - unsigned int : 4; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_LMI_SWAP_CNTL3__VI { - struct { - unsigned int RD_MC_CID_SWAP : 2; - unsigned int : 12; - unsigned int : 1; - unsigned int : 5; - unsigned int : 1; - unsigned int : 5; - unsigned int : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_LMI_VCPU_CACHE_40BIT_BAR__VI { - struct { - unsigned int BAR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_OUT_RB_WPTR__VI { - struct { - unsigned int : 4; - unsigned int : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_ARB_CTRL__VI { - struct { - unsigned int : 9; - unsigned int : 7; - unsigned int VCE_CGTT_OVERRIDE : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_BASE_HI__VI { - struct { - unsigned int RB_BASE_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_BASE_HI2__VI { - struct { - unsigned int RB_BASE_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_BASE_HI3__VI { - struct { - unsigned int RB_BASE_HI : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_BASE_LO__VI { - struct { - unsigned int : 6; - unsigned int RB_BASE_LO : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_BASE_LO2__VI { - struct { - unsigned int : 6; - unsigned int RB_BASE_LO : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_BASE_LO3__VI { - struct { - unsigned int : 6; - unsigned int RB_BASE_LO : 26; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_RPTR__VI { - struct { - unsigned int : 4; - unsigned int RB_RPTR : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_RPTR2__VI { - struct { - unsigned int : 4; - unsigned int RB_RPTR : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_RPTR3__VI { - struct { - unsigned int : 4; - unsigned int RB_RPTR : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_SIZE__VI { - struct { - unsigned int : 4; - unsigned int RB_SIZE : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_SIZE2__VI { - struct { - unsigned int : 4; - unsigned int RB_SIZE : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_SIZE3__VI { - struct { - unsigned int : 4; - unsigned int RB_SIZE : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_WPTR__VI { - struct { - unsigned int : 4; - unsigned int RB_WPTR : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_WPTR2__VI { - struct { - unsigned int : 4; - unsigned int RB_WPTR : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_RB_WPTR3__VI { - struct { - unsigned int : 4; - unsigned int RB_WPTR : 19; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_SOFT_RESET__VI { - struct { - unsigned int ECPU_SOFT_RESET : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_STATUS__VI { - struct { - unsigned int JOB_BUSY : 1; - unsigned int VCPU_REPORT : 7; - unsigned int UENC_BUSY : 1; - unsigned int : 13; - unsigned int VCE_CONFIGURATION : 2; - unsigned int VCE_INSTANCE_ID : 2; - unsigned int : 4; - unsigned int : 1; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_SYS_INT_ACK__VI { - struct { - unsigned int : 1; - unsigned int : 2; - unsigned int VCE_SYS_INT_TRAP_INTERRUPT_ACK : 1; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_SYS_INT_EN__VI { - struct { - unsigned int : 1; - unsigned int : 2; - unsigned int VCE_SYS_INT_TRAP_INTERRUPT_EN : 1; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_SYS_INT_STATUS__VI { - struct { - unsigned int : 1; - unsigned int : 2; - unsigned int VCE_SYS_INT_TRAP_INTERRUPT_INT : 1; - unsigned int : 1; - unsigned int : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 14; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_UENC_DMA_DCLK_CTRL__VI { - struct { - unsigned int WRDMCLK_FORCEON : 1; - unsigned int RDDMCLK_FORCEON : 1; - unsigned int REGCLK_FORCEON : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_VCPU_CACHE_OFFSET0__VI { - struct { - unsigned int OFFSET : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_VCPU_CACHE_OFFSET1__VI { - struct { - unsigned int OFFSET : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_VCPU_CACHE_OFFSET2__VI { - struct { - unsigned int OFFSET : 28; - unsigned int : 4; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_VCPU_CACHE_SIZE0__VI { - struct { - unsigned int SIZE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_VCPU_CACHE_SIZE1__VI { - struct { - unsigned int SIZE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_VCPU_CACHE_SIZE2__VI { - struct { - unsigned int SIZE : 24; - unsigned int : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VCE_VCPU_CNTL__VI { - struct { - unsigned int CLK_EN : 1; - unsigned int : 1; - unsigned int : 14; - unsigned int : 1; - unsigned int : 1; - unsigned int RBBM_SOFT_RESET : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 11; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VDDGFX_IDLE_CONTROL__VI { - struct { - unsigned int VDDGFX_IDLE_EN : 1; - unsigned int VDDGFX_IDLE_DETECT : 1; - unsigned int FORCE_VDDGFX_IDLE_EXIT : 1; - unsigned int SMC_VDDGFX_IDLE_STATE : 1; - unsigned int : 28; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VDDGFX_IDLE_EXIT__VI { - struct { - unsigned int BIF_EXIT_REQ : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VDDGFX_IDLE_PARAMETER__VI { - struct { - unsigned int VDDGFX_IDLE_THRESHOLD : 16; - unsigned int VDDGFX_IDLE_THRESHOLD_UNIT : 4; - unsigned int : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA25_PPLL_ANALOG__VI { - struct { - unsigned int VGA25_CAL_MODE : 5; - unsigned int VGA25_PPLL_PFD_PULSE_SEL : 2; - unsigned int : 1; - unsigned int VGA25_PPLL_CP : 4; - unsigned int VGA25_PPLL_LF_MODE : 9; - unsigned int : 3; - unsigned int VGA25_PPLL_IBIAS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA28_PPLL_ANALOG__VI { - struct { - unsigned int VGA28_CAL_MODE : 5; - unsigned int VGA28_PPLL_PFD_PULSE_SEL : 2; - unsigned int : 1; - unsigned int VGA28_PPLL_CP : 4; - unsigned int VGA28_PPLL_LF_MODE : 9; - unsigned int : 3; - unsigned int VGA28_PPLL_IBIAS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGA41_PPLL_ANALOG__VI { - struct { - unsigned int VGA41_CAL_MODE : 5; - unsigned int VGA41_PPLL_PFD_PULSE_SEL : 2; - unsigned int : 1; - unsigned int VGA41_PPLL_CP : 4; - unsigned int VGA41_PPLL_LF_MODE : 9; - unsigned int : 3; - unsigned int VGA41_PPLL_IBIAS : 8; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_DISPATCH_DRAW_INDEX__VI { - struct { - unsigned int MATCH_INDEX : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VGT_TESS_DISTRIBUTION__VI { - struct { - unsigned int ACCUM_ISOLINE : 8; - unsigned int ACCUM_TRI : 8; - unsigned int ACCUM_QUAD : 8; - unsigned int DONUT_SPLIT : 5; - unsigned int TRAP_SPLIT : 3; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VIEWPORT_START_SECONDARY__VI { - struct { - unsigned int VIEWPORT_Y_START_SECONDARY : 14; - unsigned int : 2; - unsigned int VIEWPORT_X_START_SECONDARY : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_INIT_STATUS__VI { - struct { - unsigned int VM_INIT_STATUS : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_BANK_SELECT_RESERVED_CID__VI { - struct { - unsigned int RESERVED_READ_CLIENT_ID : 9; - unsigned int : 1; - unsigned int RESERVED_WRITE_CLIENT_ID : 9; - unsigned int : 1; - unsigned int ENABLE : 1; - unsigned int : 3; - unsigned int RESERVED_CACHE_INVALIDATION_MODE : 1; - unsigned int RESERVED_CACHE_PRIVATE_INVALIDATION : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_BANK_SELECT_RESERVED_CID2__VI { - struct { - unsigned int RESERVED_READ_CLIENT_ID : 9; - unsigned int : 1; - unsigned int RESERVED_WRITE_CLIENT_ID : 9; - unsigned int : 1; - unsigned int ENABLE : 1; - unsigned int : 3; - unsigned int RESERVED_CACHE_INVALIDATION_MODE : 1; - unsigned int RESERVED_CACHE_PRIVATE_INVALIDATION : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union VM_L2_CNTL4__VI { - struct { - unsigned int L2_CACHE_4K_PARTITION_COUNT : 6; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 1; - unsigned int : 20; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WB_DBG_MODE__VI { - struct { - unsigned int WB_DBG_MODE_EN : 1; - unsigned int WB_DBG_DIN_FMT : 1; - unsigned int WB_DBG_36MODE : 1; - unsigned int WB_DBG_CMAP : 1; - unsigned int : 4; - unsigned int WB_DBG_PXLRATE_ERROR : 1; - unsigned int : 7; - unsigned int WB_DBG_SOURCE_WIDTH : 15; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WB_DEBUG_CTRL__VI { - struct { - unsigned int WB_DEBUG_EN : 1; - unsigned int : 5; - unsigned int WB_DEBUG_SEL : 2; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WB_EC_CONFIG__VI { - struct { - unsigned int DISPCLK_R_WB_GATE_DIS : 1; - unsigned int DISPCLK_G_WB_GATE_DIS : 1; - unsigned int DISPCLK_G_WBSCL_GATE_DIS : 1; - unsigned int DISPCLK_R_WB_RAMP_DIS : 1; - unsigned int DISPCLK_G_WB_RAMP_DIS : 1; - unsigned int DISPCLK_G_WBSCL_RAMP_DIS : 1; - unsigned int WB_LB_LS_DIS : 1; - unsigned int WB_LB_SD_DIS : 1; - unsigned int WB_LUT_LS_DIS : 1; - unsigned int WBSCL_LB_MEM_PWR_MODE_SEL : 2; - unsigned int : 1; - unsigned int WB_TEST_CLK_SEL : 4; - unsigned int WBSCL_LB_MEM_PWR_DIS : 1; - unsigned int WBSCL_LB_MEM_PWR_FORCE : 2; - unsigned int WBSCL_LB_MEM_PWR_STATE : 2; - unsigned int : 2; - unsigned int WB_RAM_PW_SAVE_MODE : 1; - unsigned int : 4; - unsigned int LB_MEM_PWR_STATE : 2; - unsigned int LUT_MEM_PWR_STATE : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WB_ENABLE__VI { - struct { - unsigned int WB_ENABLE : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WB_HW_DEBUG__VI { - struct { - unsigned int WB_HW_DEBUG : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WB_SOFT_RESET__VI { - struct { - unsigned int WB_SOFT_RESET : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_REG10__VI { - struct { - unsigned int ttp_pd_patch_rts : 1; - unsigned int ttp_pd_is_event : 1; - unsigned int ttp_pd_eopg : 1; - unsigned int ttp_pd_eop : 1; - unsigned int pipe0_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int donut_en_p1_q : 1; - unsigned int donut_se_switch_p2 : 1; - unsigned int patch_se_switch_p2 : 1; - unsigned int last_donut_switch_p2 : 1; - unsigned int last_donut_of_patch_p2 : 1; - unsigned int is_event_p1_q : 1; - unsigned int eopg_p1_q : 1; - unsigned int eop_p1_q : 1; - unsigned int patch_accum_q : 8; - unsigned int wd_te11_out_se0_fifo_full : 1; - unsigned int wd_te11_out_se0_fifo_empty : 1; - unsigned int wd_te11_out_se1_fifo_full : 1; - unsigned int wd_te11_out_se1_fifo_empty : 1; - unsigned int wd_te11_out_se2_fifo_full : 1; - unsigned int wd_te11_out_se2_fifo_empty : 1; - unsigned int wd_te11_out_se3_fifo_full : 1; - unsigned int wd_te11_out_se3_fifo_empty : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_REG6__VI { - struct { - unsigned int WD_IA_draw_eop : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_REG7__VI { - struct { - unsigned int SE0VGT_WD_thdgrp_send_in : 1; - unsigned int wd_arb_se0_input_fifo_re : 1; - unsigned int wd_arb_se0_input_fifo_empty : 1; - unsigned int wd_arb_se0_input_fifo_full : 1; - unsigned int SE1VGT_WD_thdgrp_send_in : 1; - unsigned int wd_arb_se1_input_fifo_re : 1; - unsigned int wd_arb_se1_input_fifo_empty : 1; - unsigned int wd_arb_se1_input_fifo_full : 1; - unsigned int SPARE1 : 4; - unsigned int SPARE2 : 4; - unsigned int te11_arb_state_q : 3; - unsigned int SPARE5 : 1; - unsigned int se0_thdgrp_is_event : 1; - unsigned int se0_thdgrp_eop : 1; - unsigned int se1_thdgrp_is_event : 1; - unsigned int se1_thdgrp_eop : 1; - unsigned int SPARE6 : 4; - unsigned int tfreq_arb_tgroup_rtr : 1; - unsigned int arb_tfreq_tgroup_rts : 1; - unsigned int arb_tfreq_tgroup_event : 1; - unsigned int te11_arb_busy : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_REG8__VI { - struct { - unsigned int pipe0_dr : 1; - unsigned int pipe1_dr : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int tfreq_tg_fifo_empty : 1; - unsigned int tfreq_tg_fifo_full : 1; - unsigned int tf_data_fifo_busy_q : 1; - unsigned int tf_data_fifo_rtr_q : 1; - unsigned int tf_skid_fifo_empty : 1; - unsigned int tf_skid_fifo_full : 1; - unsigned int wd_tc_rdreq_rtr_q : 1; - unsigned int last_req_of_tg_p2 : 1; - unsigned int se0spi_wd_hs_done_cnt_q : 6; - unsigned int event_flag_p1_q : 1; - unsigned int null_flag_p1_q : 1; - unsigned int tf_data_fifo_cnt_q : 7; - unsigned int second_tf_ret_data_q : 1; - unsigned int first_req_of_tg_p1_q : 1; - unsigned int WD_TC_rdreq_send_out : 1; - unsigned int WD_TC_rdnfo_stall_out : 1; - unsigned int TC_WD_rdret_valid_in : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_DEBUG_REG9__VI { - struct { - unsigned int pipe0_dr : 1; - unsigned int pipec_tf_dr : 1; - unsigned int pipe2_dr : 1; - unsigned int event_or_null_flags_p0_q : 1; - unsigned int pipe0_rtr : 1; - unsigned int pipe1_rtr : 1; - unsigned int pipec_tf_rtr : 1; - unsigned int pipe2_rtr : 1; - unsigned int ttp_patch_fifo_full : 1; - unsigned int ttp_patch_fifo_empty : 1; - unsigned int ttp_tf_fifo_empty : 1; - unsigned int SPARE0 : 5; - unsigned int tf_fetch_state_q : 3; - unsigned int last_patch_of_tg : 1; - unsigned int tf_pointer_p0_q : 4; - unsigned int dynamic_hs_p0_q : 1; - unsigned int first_fetch_of_tg_p0_q : 1; - unsigned int mem_is_even : 1; - unsigned int SPARE1 : 1; - unsigned int SPARE2 : 2; - unsigned int pipe4_dr : 1; - unsigned int pipe4_rtr : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union WD_QOS__VI { - struct { - unsigned int DRAW_STALL : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_AON_TEST_DEBUG_DATA__VI { - struct { - unsigned int XDMA_AON_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_AON_TEST_DEBUG_INDEX__VI { - struct { - unsigned int XDMA_AON_TEST_DEBUG_INDEX : 8; - unsigned int XDMA_AON_TEST_DEBUG_WRITE_EN : 1; - unsigned int XDMA_DEBUG_SEL : 1; - unsigned int XDMA_DEBUG_OUT_EN : 1; - unsigned int : 21; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_CLOCK_GATING_CNTL__VI { - struct { - unsigned int XDMA_SCLK_TURN_ON_DELAY : 4; - unsigned int XDMA_SCLK_TURN_OFF_DELAY : 8; - unsigned int : 3; - unsigned int XDMA_SCLK_GATE_DIS : 1; - unsigned int XDMA_SCLK_REG_GATE_DIS : 1; - unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0 : 1; - unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1 : 1; - unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2 : 1; - unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3 : 1; - unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4 : 1; - unsigned int XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5 : 1; - unsigned int XDMA_SCLK_G_SDYN_GATE_DIS : 1; - unsigned int XDMA_SCLK_G_MSTAT_GATE_DIS : 1; - unsigned int XDMA_SCLK_G_SSTAT_GATE_DIS : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_IF_BIF_STATUS__VI { - struct { - unsigned int XDMA_IF_BIF_ERROR_STATUS : 4; - unsigned int : 4; - unsigned int XDMA_IF_BIF_ERROR_CLEAR : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_IF_STATUS__VI { - struct { - unsigned int XDMA_MC_PCIEWR_BUSY : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_INTERRUPT__VI { - struct { - unsigned int : 8; - unsigned int XDMA_MSTR_MEM_URGENT_STAT : 1; - unsigned int XDMA_MSTR_MEM_URGENT_MASK : 1; - unsigned int XDMA_MSTR_MEM_URGENT_ACK : 1; - unsigned int : 5; - unsigned int XDMA_SLV_READ_URGENT_STAT : 1; - unsigned int XDMA_SLV_READ_URGENT_MASK : 1; - unsigned int XDMA_SLV_READ_URGENT_ACK : 1; - unsigned int : 1; - unsigned int XDMA_PERF_MEAS_STAT : 1; - unsigned int XDMA_PERF_MEAS_MASK : 1; - unsigned int XDMA_PERF_MEAS_ACK : 1; - unsigned int : 9; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_LOCAL_SURFACE_TILING1__VI { - struct { - unsigned int XDMA_LOCAL_ARRAY_MODE : 4; - unsigned int XDMA_LOCAL_TILE_SPLIT : 3; - unsigned int : 1; - unsigned int XDMA_LOCAL_BANK_WIDTH : 2; - unsigned int XDMA_LOCAL_BANK_HEIGHT : 2; - unsigned int XDMA_LOCAL_MACRO_TILE_ASPECT : 2; - unsigned int : 6; - unsigned int XDMA_LOCAL_NUM_BANKS : 2; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_LOCAL_SURFACE_TILING2__VI { - struct { - unsigned int XDMA_LOCAL_PIPE_INTERLEAVE_SIZE : 3; - unsigned int : 17; - unsigned int XDMA_LOCAL_MICRO_TILE_MODE : 3; - unsigned int : 4; - unsigned int XDMA_LOCAL_PIPE_CONFIG : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MC_PCIE_CLIENT_CONFIG__VI { - struct { - unsigned int : 8; - unsigned int XDMA_MC_PCIE_SWAP : 2; - unsigned int : 2; - unsigned int XDMA_MC_PCIE_VMID : 4; - unsigned int XDMA_MC_PCIE_PRIV : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MEM_POWER_CNTL__VI { - struct { - unsigned int XDMA_MEM_CORE_IDLE_STATE : 2; - unsigned int XDMA_MEM_IF_IDLE_STATE : 2; - unsigned int : 15; - unsigned int XDMA_MEM_IF_PCIE_STATE : 2; - unsigned int XDMA_MEM_IF_PCIE_TRANS : 1; - unsigned int XDMA_MEM_IF_RD_STATE : 2; - unsigned int : 1; - unsigned int XDMA_MEM_IF_RD_TRANS : 1; - unsigned int XDMA_MEM_IF_WR_STATE : 2; - unsigned int XDMA_MEM_IF_WR_TRANS : 1; - unsigned int XDMA_MEM_IF_BIF_STATE : 2; - unsigned int XDMA_MEM_IF_BIF_TRANS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_CACHE__VI { - struct { - unsigned int XDMA_MSTR_CACHE_PITCH : 14; - unsigned int : 15; - unsigned int XDMA_MSTR_CACHE_TLB_PG_STATE : 2; - unsigned int XDMA_MSTR_CACHE_TLB_PG_TRANS : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_CACHE_BASE_ADDR__VI { - struct { - unsigned int XDMA_MSTR_CACHE_BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI { - struct { - unsigned int XDMA_MSTR_CACHE_BASE_ADDR_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_CHANNEL_DIM__VI { - struct { - unsigned int XDMA_MSTR_CHANNEL_WIDTH : 14; - unsigned int : 2; - unsigned int XDMA_MSTR_CHANNEL_HEIGHT : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_CHANNEL_START__VI { - struct { - unsigned int XDMA_MSTR_CHANNEL_START_X : 14; - unsigned int : 2; - unsigned int XDMA_MSTR_CHANNEL_START_Y : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_CMD_URGENT_CNTL__VI { - struct { - unsigned int XDMA_MSTR_CMD_CLIENT_STALL : 1; - unsigned int : 7; - unsigned int XDMA_MSTR_CMD_URGENT_LEVEL : 4; - unsigned int XDMA_MSTR_CMD_STALL_DELAY : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_CNTL__VI { - struct { - unsigned int : 12; - unsigned int XDMA_MSTR_ALPHA_POSITION : 2; - unsigned int XDMA_MSTR_MEM_READY : 1; - unsigned int : 1; - unsigned int XDMA_MSTR_ENABLE : 1; - unsigned int : 1; - unsigned int XDMA_MSTR_DEBUG_MODE : 1; - unsigned int : 1; - unsigned int XDMA_MSTR_SOFT_RESET : 1; - unsigned int XDMA_MSTR_BIF_STALL_EN : 1; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_HEIGHT__VI { - struct { - unsigned int XDMA_MSTR_ACTIVE_HEIGHT : 14; - unsigned int : 2; - unsigned int XDMA_MSTR_FRAME_HEIGHT : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__VI { - struct { - unsigned int XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__VI { - struct { - unsigned int XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_LOCAL_SURFACE_PITCH__VI { - struct { - unsigned int XDMA_MSTR_LOCAL_SURFACE_PITCH : 14; - unsigned int : 18; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_MEM_CLIENT_CONFIG__VI { - struct { - unsigned int : 8; - unsigned int XDMA_MSTR_MEM_CLIENT_SWAP : 2; - unsigned int : 2; - unsigned int XDMA_MSTR_MEM_CLIENT_VMID : 4; - unsigned int XDMA_MSTR_MEM_CLIENT_PRIV : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_MEM_NACK_STATUS__VI { - struct { - unsigned int XDMA_MSTR_MEM_NACK_TAG : 10; - unsigned int : 2; - unsigned int XDMA_MSTR_MEM_NACK : 2; - unsigned int : 2; - unsigned int XDMA_MSTR_MEM_NACK_CLR : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_MEM_URGENT_CNTL__VI { - struct { - unsigned int XDMA_MSTR_MEM_CLIENT_STALL : 1; - unsigned int : 3; - unsigned int XDMA_MSTR_MEM_URGENT_LIMIT : 4; - unsigned int XDMA_MSTR_MEM_URGENT_LEVEL : 4; - unsigned int XDMA_MSTR_MEM_STALL_DELAY : 4; - unsigned int XDMA_MSTR_MEM_URGENT_TIMER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_PCIE_NACK_STATUS__VI { - struct { - unsigned int XDMA_MSTR_PCIE_NACK_TAG : 10; - unsigned int : 2; - unsigned int XDMA_MSTR_PCIE_NACK : 2; - unsigned int : 2; - unsigned int XDMA_MSTR_PCIE_NACK_CLR : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_PERFMEAS_CNTL__VI { - struct { - unsigned int XDMA_MSTR_CACHE_BW_MEAS_ITER : 12; - unsigned int XDMA_MSTR_CACHE_BW_SEGID_SEL : 5; - unsigned int XDMA_MSTR_CACHE_BW_COUNTER_RST : 1; - unsigned int : 1; - unsigned int XDMA_MSTR_LT_MEAS_ITER : 12; - unsigned int XDMA_MSTR_LT_COUNTER_RST : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_PERFMEAS_STATUS__VI { - struct { - unsigned int XDMA_MSTR_PERFMEAS_DATA : 24; - unsigned int XDMA_MSTR_PERFMEAS_INDEX : 3; - unsigned int : 3; - unsigned int XDMA_MSTR_PERFMEAS_INDEX_MODE : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_PIPE_CNTL__VI { - struct { - unsigned int XDMA_MSTR_CACHE_LINES : 8; - unsigned int XDMA_MSTR_READ_REQUEST : 1; - unsigned int XDMA_MSTR_PIPE_FRAME_MODE : 1; - unsigned int XDMA_MSTR_PIPE_SOFT_RESET : 1; - unsigned int XDMA_MSTR_CACHE_INVALIDATE : 1; - unsigned int XDMA_MSTR_REQUEST_CHANNEL_ID : 3; - unsigned int XDMA_MSTR_FLIP_MODE : 1; - unsigned int XDMA_MSTR_REQUEST_MIN : 8; - unsigned int XDMA_MSTR_PIPE_ACTIVE : 1; - unsigned int XDMA_MSTR_PIPE_FLUSHING : 1; - unsigned int XDMA_MSTR_PIPE_FLIP_PENDING : 1; - unsigned int XDMA_MSTR_VSYNC_GSL_ENABLE : 1; - unsigned int XDMA_MSTR_SUPERAA_ENABLE : 1; - unsigned int XDMA_MSTR_HSYNC_GSL_GROUP : 2; - unsigned int XDMA_MSTR_GSL_GROUP_MASTER : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_READ_COMMAND__VI { - struct { - unsigned int XDMA_MSTR_REQUEST_SIZE : 14; - unsigned int : 2; - unsigned int XDMA_MSTR_REQUEST_PREFETCH : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_REMOTE_GPU_ADDRESS__VI { - struct { - unsigned int XDMA_MSTR_REMOTE_GPU_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI { - struct { - unsigned int XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_REMOTE_SURFACE_BASE__VI { - struct { - unsigned int XDMA_MSTR_REMOTE_SURFACE_BASE : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI { - struct { - unsigned int XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_STATUS__VI { - struct { - unsigned int XDMA_MSTR_VCOUNT_CURRENT : 14; - unsigned int : 2; - unsigned int XDMA_MSTR_WRITE_LINE_CURRENT : 12; - unsigned int XDMA_MSTR_STATUS_SELECT : 3; - unsigned int : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_MSTR_VSYNC_GSL_CHECK__VI { - struct { - unsigned int XDMA_MSTR_VSYNC_GSL_CHECK_SEL : 3; - unsigned int : 5; - unsigned int XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT : 14; - unsigned int : 10; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_PERF_MEAS_STATUS__VI { - struct { - unsigned int XDMA_PERF_MEAS_STATUS : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_PG_CONTROL__VI { - struct { - unsigned int XDMA_PG_CONTROL : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_PG_STATUS__VI { - struct { - unsigned int XDMA_SERDES_RDATA : 24; - unsigned int XDMA_PGFSM_READ_READY : 1; - unsigned int XDMA_SERDES_BUSY : 1; - unsigned int XDMA_SERDES_SMU_POWER_STATUS : 1; - unsigned int : 5; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_PG_WDATA__VI { - struct { - unsigned int XDMA_PG_WDATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_RBBMIF_RDWR_CNTL__VI { - struct { - unsigned int XDMA_RBBMIF_RDWR_DELAY : 3; - unsigned int XDMA_RBBMIF_RDWR_TIMEOUT_DIS : 1; - unsigned int : 11; - unsigned int XDMA_RBBMIF_TIMEOUT_DELAY : 17; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_CHANNEL_CNTL__VI { - struct { - unsigned int XDMA_SLV_CHANNEL_WEIGHT : 9; - unsigned int : 7; - unsigned int XDMA_SLV_STOP_TRANSFER : 1; - unsigned int XDMA_SLV_CHANNEL_SOFT_RESET : 1; - unsigned int : 6; - unsigned int XDMA_SLV_CHANNEL_ACTIVE : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_CNTL__VI { - struct { - unsigned int XDMA_SLV_READ_LINES : 1; - unsigned int : 8; - unsigned int XDMA_SLV_MEM_READY : 1; - unsigned int XDMA_SLV_ACTIVE : 1; - unsigned int : 1; - unsigned int XDMA_SLV_ALPHA_POSITION : 2; - unsigned int : 2; - unsigned int XDMA_SLV_ENABLE : 1; - unsigned int : 2; - unsigned int XDMA_SLV_READ_LAT_TEST_EN : 1; - unsigned int XDMA_SLV_SOFT_RESET : 1; - unsigned int : 3; - unsigned int XDMA_SLV_REQ_MAXED_OUT : 1; - unsigned int XDMA_SLV_WB_BURST_RESET : 1; - unsigned int : 6; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_FLIP_PENDING__VI { - struct { - unsigned int XDMA_SLV_FLIP_PENDING : 1; - unsigned int : 31; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_MEM_CLIENT_CONFIG__VI { - struct { - unsigned int : 8; - unsigned int XDMA_SLV_MEM_CLIENT_SWAP : 2; - unsigned int : 2; - unsigned int XDMA_SLV_MEM_CLIENT_VMID : 4; - unsigned int XDMA_SLV_MEM_CLIENT_PRIV : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_MEM_NACK_STATUS__VI { - struct { - unsigned int XDMA_SLV_MEM_NACK_TAG : 16; - unsigned int XDMA_SLV_MEM_NACK : 2; - unsigned int : 13; - unsigned int XDMA_SLV_MEM_NACK_CLR : 1; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_PCIE_NACK_STATUS__VI { - struct { - unsigned int XDMA_SLV_PCIE_NACK_TAG : 10; - unsigned int : 2; - unsigned int XDMA_SLV_PCIE_NACK : 2; - unsigned int : 2; - unsigned int XDMA_SLV_PCIE_NACK_CLR : 1; - unsigned int : 15; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_RDRET_BUF_STATUS__VI { - struct { - unsigned int XDMA_SLV_RDRET_FREE_ENTRIES : 10; - unsigned int : 2; - unsigned int XDMA_SLV_RDRET_BUF_SIZE : 10; - unsigned int XDMA_SLV_RDRET_PG_STATE : 2; - unsigned int XDMA_SLV_RDRET_PG_TRANS : 1; - unsigned int : 7; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_READ_LATENCY_AVE__VI { - struct { - unsigned int XDMA_SLV_READ_LATENCY_ACC : 20; - unsigned int XDMA_SLV_READ_LATENCY_COUNT : 12; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_READ_LATENCY_MINMAX__VI { - struct { - unsigned int XDMA_SLV_READ_LATENCY_MIN : 16; - unsigned int XDMA_SLV_READ_LATENCY_MAX : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_READ_LATENCY_TIMER__VI { - struct { - unsigned int XDMA_SLV_READ_LATENCY_TIMER : 16; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_READ_URGENT_CNTL__VI { - struct { - unsigned int XDMA_SLV_READ_CLIENT_STALL : 1; - unsigned int : 3; - unsigned int XDMA_SLV_READ_URGENT_LIMIT : 4; - unsigned int XDMA_SLV_READ_URGENT_LEVEL : 4; - unsigned int XDMA_SLV_READ_STALL_DELAY : 4; - unsigned int XDMA_SLV_READ_URGENT_TIMER : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_REMOTE_GPU_ADDRESS__VI { - struct { - unsigned int XDMA_SLV_REMOTE_GPU_ADDRESS : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI { - struct { - unsigned int XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH : 8; - unsigned int : 24; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_SLS_PITCH__VI { - struct { - unsigned int XDMA_SLV_SLS_PITCH : 14; - unsigned int : 2; - unsigned int XDMA_SLV_SLS_WIDTH : 14; - unsigned int : 2; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_WB_RATE_CNTL__VI { - struct { - unsigned int XDMA_SLV_WB_BURST_SIZE : 9; - unsigned int : 7; - unsigned int XDMA_SLV_WB_BURST_PERIOD : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_SLV_WRITE_URGENT_CNTL__VI { - struct { - unsigned int XDMA_SLV_WRITE_STALL : 1; - unsigned int : 7; - unsigned int XDMA_SLV_WRITE_URGENT_LEVEL : 4; - unsigned int XDMA_SLV_WRITE_STALL_DELAY : 4; - unsigned int : 16; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_TEST_DEBUG_DATA__VI { - struct { - unsigned int XDMA_TEST_DEBUG_DATA : 32; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - - union XDMA_TEST_DEBUG_INDEX__VI { - struct { - unsigned int XDMA_TEST_DEBUG_INDEX : 8; - unsigned int XDMA_TEST_DEBUG_WRITE_EN : 1; - unsigned int : 23; - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; - }; - -} // inline namespace Chip -} // namespace Gfx6 -} // namespace Pal - -#endif diff --git a/tools/vop_generator/vop_generator.lpr b/tools/vop_generator/vop_generator.lpr index c7f9809b..5fd5f52b 100644 --- a/tools/vop_generator/vop_generator.lpr +++ b/tools/vop_generator/vop_generator.lpr @@ -181,6 +181,9 @@ var S,Name:RawByteString; pre,post:RawByteString; + releflags:RawByteString; + vpp_offset:RawByteString; + rele:ptruint; F:THandle; @@ -189,6 +192,7 @@ var state:Integer; links,maxlen:SizeUInt; + vpnum:Integer; begin EnumList:=TStringList.Create; @@ -258,12 +262,13 @@ begin end; 1:begin //value + rele:=0; repeat case Name of 'IN':; 'OUT':; 'INOUT':; - 'WILLRELE':; + 'WILLRELE':rele:=1; 'struct':; 'const':; else @@ -304,7 +309,7 @@ begin if (Length(S)>Enum.namelen) then Enum.namelen:=Length(S); - Enum.AddPair(S,Name); + Enum.AddPair(S,Name,TObject(rele)); Writeln(S,':',Name); end; end; @@ -315,14 +320,18 @@ begin F:=FileCreate(ChangeFileExt(fname,'.pas')); - S:='unit '+ChangeFileExt(ExtractFileName(fname),'')+';'#13#10#13#10+ - 'interface'#13#10#13#10+ - '{$mode objfpc}{$H+}'#13#10+ - '{$CALLING SysV_ABI_CDecl}'#13#10#13#10; - FileWrite(F,Pchar(S)^,Length(S)); + S:='{This file is automatically generated by "vop_generator"}'#13#10; + S:=S+#13#10; + S:=S+'unit '+ChangeFileExt(ExtractFileName(fname),'')+';'#13#10; + S:=S+#13#10; + S:=S+'interface'#13#10; + S:=S+#13#10; + S:=S+'{$mode objfpc}{$H+}'#13#10; + S:=S+'{$CALLING SysV_ABI_CDecl}'#13#10; + S:=S+#13#10; - S:='uses'#13#10; - S:=S+' vfs_vnode,'#13#10; + S:=S+'uses'#13#10; + S:=S+' vnode,'#13#10; S:=S+' vnamei,'#13#10; S:=S+' vfile,'#13#10; S:=S+' vuio,'#13#10; @@ -330,9 +339,8 @@ begin S:=S+' vfcntl,'#13#10; S:=S+' vsocketvar;'#13#10; S:=S+#13#10; - FileWrite(F,Pchar(S)^,Length(S)); - S:='type'#13#10; + S:=S+'type'#13#10; S:=S+' PPPtrUint =^PPtrUint;'#13#10; S:=S+' pp_bufobj =Pointer;'#13#10; S:=S+' daddr_t =PtrUint;'#13#10; @@ -355,21 +363,22 @@ begin Enum:=TEnum(EnumList.Objects[i]); S:=' p_'+Enum.name+'_args=^'+Enum.name+'_args;'#13#10; - FileWrite(F,Pchar(S)^,Length(S)); - - S:=' '+Enum.name+'_args=record'#13#10; + S:=S+' '+Enum.name+'_args=record'#13#10; FileWrite(F,Pchar(S)^,Length(S)); if (Length(Enum.name)>maxlen) then maxlen:=Length(Enum.name); + if Length('gen')>Enum.namelen then Enum.namelen:=Length('gen'); + + S:=' a_gen'+Space(Enum.namelen-Length('gen'))+':p_vnodeop_desc;'#13#10; + For x:=0 to Enum.Count-1 do begin Name:=Enum.Names[x]; - S:=' a_'+Name+Space(Enum.namelen-Length(Name))+':'+Enum.ValueFromIndex[x]+';'#13#10; - FileWrite(F,Pchar(S)^,Length(S)); + S:=S+' a_'+Name+Space(Enum.namelen-Length(Name))+':'+Enum.ValueFromIndex[x]+';'#13#10; end; - S:=' end;'#13#10#13#10; + S:=S+' end;'#13#10#13#10; FileWrite(F,Pchar(S)^,Length(S)); end; @@ -386,16 +395,16 @@ begin FileWrite(F,Pchar(S)^,Length(S)); //list - For i:=0 to EnumList.Count-1 do - begin - Enum:=TEnum(EnumList.Objects[i]); + //For i:=0 to EnumList.Count-1 do + //begin + // Enum:=TEnum(EnumList.Objects[i]); + // + // S:='//'+Enum.name+Space(maxlen-Length(Enum.name))+':Pointer;'#13#10; + // FileWrite(F,Pchar(S)^,Length(S)); + //end; - S:='//'+Enum.name+Space(maxlen-Length(Enum.name))+':Pointer;'#13#10; - FileWrite(F,Pchar(S)^,Length(S)); - end; - - S:=#13#10; - FileWrite(F,Pchar(S)^,Length(S)); + //S:=#13#10; + //FileWrite(F,Pchar(S)^,Length(S)); //functions header For i:=0 to EnumList.Count-1 do @@ -405,7 +414,7 @@ begin Name:=FixFuncName(Enum.name); Name:=Upcase(Name); - S:='function '+Name+'('; + S:='function '+Name+Space(maxlen-Length(Name))+'('; FileWrite(F,Pchar(S)^,Length(S)); For x:=0 to Enum.Count-1 do @@ -423,9 +432,166 @@ begin FileWrite(F,Pchar(S)^,Length(S)); end; - S:=#13#10'implementation'#13#10#13#10; + //const + S:=#13#10'const'#13#10; + FileWrite(F,Pchar(S)^,Length(S)); + + //vp_offsets + For i:=0 to EnumList.Count-1 do + begin + Enum:=TEnum(EnumList.Objects[i]); + + S:=' '+Enum.name+'_vp_offsets'+Space(maxlen-Length(Enum.name))+':array[0..'; + + //calc count + vpnum:=0; + For x:=0 to Enum.Count-1 do + begin + Name:=Enum.ValueFromIndex[x]; + if (Name='p_vnode') then + begin + Inc(vpnum); + end; + end; + Assert(vpnum<>0); + + S:=S+IntToStr(vpnum)+'] of Byte=('; + + //offsets + vpnum:=0; + For x:=0 to Enum.Count-1 do + begin + Name:=Enum.ValueFromIndex[x]; + if (Name='p_vnode') then + begin + if (vpnum<>0) then + begin + S:=S+','; + end; + + Name:=Enum.Names[x]; + Name:='a_'+Name; + + S:=S+'Byte(ptrint(@p_'+Enum.name+'_args(nil)^.'+Name+'))'; + + Inc(vpnum); + end; + end; + + S:=S+',Byte(-1));'#13#10; + + FileWrite(F,Pchar(S)^,Length(S)); + end; + + S:=#13#10; + S:=S+' vop_default_desc:t_vnodeop_desc=('#13#10; + S:=S+' vdesc_name :''default'';'#13#10; + S:=S+' vdesc_call :nil;'#13#10; + S:=S+' vdesc_vp_offsets :nil;'#13#10; + S:=S+' vdesc_flags :0;'#13#10; + S:=S+' vdesc_vpp_offset :-1;'#13#10; + S:=S+' );'#13#10; + FileWrite(F,Pchar(S)^,Length(S)); + + //vnodeop_desc + For i:=0 to EnumList.Count-1 do + begin + Enum:=TEnum(EnumList.Objects[i]); + + //releflags + vpnum:=0; + releflags:=''; + For x:=0 to Enum.Count-1 do + begin + Name:=Enum.ValueFromIndex[x]; + if (Name='p_vnode') then + begin + if (Enum.Objects[x]<>nil) then //rele + begin + if (releflags<>'') then + begin + releflags:=releflags+' or '; + end; + releflags:=releflags+'VDESC_VP'+IntToStr(vpnum)+'_WILLRELE'; + end; + Inc(vpnum); + end; + end; + + //vppwillrele,vpp_offset + vpp_offset:=''; + For x:=0 to Enum.Count-1 do + begin + Name:=Enum.ValueFromIndex[x]; + if (Name='pp_vnode') then + begin + if (vpp_offset='') then + begin + Name:=Enum.Names[x]; + Name:='a_'+Name; + + vpp_offset:='Integer(ptrint(@p_'+Enum.name+'_args(nil)^.'+Name+'))'; + end; + + if (Enum.Objects[x]<>nil) then //rele + begin + if (releflags<>'') then + begin + releflags:=releflags+' or '; + end; + releflags:=releflags+'VDESC_VPP_WILLRELE'; + Break; + end; + end; + end; + + if (releflags='') then releflags:='0'; + if (vpp_offset='') then vpp_offset:='-1'; + + S:=#13#10; + S:=S+' '+Enum.name+'_desc:t_vnodeop_desc=('#13#10; + S:=S+' vdesc_name :'''+Enum.name+''';'#13#10; + S:=S+' vdesc_call :@p_vop_vector(nil)^.'+Enum.name+';'#13#10; + S:=S+' vdesc_vp_offsets :@'+Enum.name+'_vp_offsets;'#13#10; + S:=S+' vdesc_flags :'+releflags+';'#13#10; + S:=S+' vdesc_vpp_offset :'+vpp_offset+';'#13#10; + S:=S+' );'#13#10; + FileWrite(F,Pchar(S)^,Length(S)); + end; + + S:=#13#10; + S:=S+'implementation'#13#10; + S:=S+#13#10; S:=S+'uses'#13#10; - S:=S+' vfs_subr;'#13#10#13#10; + S:=S+' errno,'#13#10; + S:=S+' vfs_subr;'#13#10; + S:=S+#13#10; + + S:=S+'function get_vp_cb(vp:p_vnode;offset:Pointer):Pointer; inline;'#13#10; + S:=S+'var'#13#10; + S:=S+' v:p_vop_vector;'#13#10; + S:=S+' p:Pointer;'#13#10; + S:=S+'begin'#13#10; + S:=S+' Result:=nil;'#13#10; + S:=S+' if (vp=nil) then Exit;'#13#10; + S:=S+' v:=vp^.v_op;'#13#10; + S:=S+' while (v<>nil) do'#13#10; + S:=S+' begin'#13#10; + S:=S+' p:=PPointer(Pointer(v)+ptrint(offset))^;'#13#10; + S:=S+' if (p<>nil) then'#13#10; + S:=S+' begin'#13#10; + S:=S+' Exit(p);'#13#10; + S:=S+' end;'#13#10; + S:=S+' p:=v^.vop_bypass;'#13#10; + S:=S+' if (p<>nil) then'#13#10; + S:=S+' begin'#13#10; + S:=S+' Exit(p);'#13#10; + S:=S+' end;'#13#10; + S:=S+' v:=v^.vop_default;'#13#10; + S:=S+' end;'#13#10; + S:=S+'end;'#13#10; + S:=S+#13#10; + FileWrite(F,Pchar(S)^,Length(S)); //functions body @@ -457,17 +623,15 @@ begin //var S:='var'#13#10; - S:=S+' v:p_vop_vector;'#13#10; - FileWrite(F,Pchar(S)^,Length(S)); - //var - if (Enum.Count>1) then + if (Upcase(Enum.name)='VOP_WRITE') then begin - S:=' a:'+Enum.name+'_args;'#13#10; - FileWrite(F,Pchar(S)^,Length(S)); + S:=S+' osize,ooffset:Int64;'#13#10; end; - S:=' s:Boolean;'#13#10; + S:=S+' c:Pointer;'#13#10; + S:=S+' a:'+Enum.name+'_args;'#13#10; + S:=S+' s:Boolean;'#13#10; FileWrite(F,Pchar(S)^,Length(S)); //body @@ -477,62 +641,51 @@ begin Name:=FixFuncName(Enum.name); Name:=Upcase(Name); - S:=' v:='+FixFieldName(Enum.Names[0])+'^.v_op;'#13#10; - S:=S+' while (v<>nil) do'#13#10; - S:=S+' begin'#13#10; - S:=S+' if (v^.'+Enum.name+'<>nil) or (v^.vop_bypass<>nil) then Break;'#13#10; - S:=S+' v:=v^.vop_default;'#13#10; - S:=S+' end;'#13#10; - S:=S+' Assert(v<>nil,'+''''+Name+''''+');'#13#10; + S:=' c:=get_vp_cb('+FixFieldName(Enum.Names[0])+','+Enum.name+'_desc.vdesc_call);'#13#10; + S:=S+' Assert(c<>nil,'+''''+Name+''''+');'#13#10; FileWrite(F,Pchar(S)^,Length(S)); - if (Enum.Count>1) then - begin - //set val - For x:=0 to Enum.Count-1 do - begin - Name:=Enum.Names[x]; + //set val + S:=' a.a_gen'+Space(Enum.namelen-Length('gen'))+':=@'+Enum.name+'_desc;'#13#10; - S:=' a.a_'+Name+Space(Enum.namelen-Length(Name))+':='+FixFieldName(Name)+';'#13#10; - FileWrite(F,Pchar(S)^,Length(S)); - end; + For x:=0 to Enum.Count-1 do + begin + Name:=Enum.Names[x]; + + S:=S+' a.a_'+Name+Space(Enum.namelen-Length(Name))+':='+FixFieldName(Name)+';'#13#10; end; - if (Enum.Count>1) then - begin - Name:='a'; - end else - begin - Name:=FixFieldName(Enum.Names[0]); - end; + FileWrite(F,Pchar(S)^,Length(S)); //pre if (Enum.pre<>'') then begin - S:=' '+Enum.pre+'(@'+Name+');'#13#10; + S:=' '+Enum.pre+'(@'+'a'; + if (Upcase(Enum.name)='VOP_WRITE') then + begin + S:=S+',osize,ooffset'; + end; + S:=S+');'#13#10; FileWrite(F,Pchar(S)^,Length(S)); end; S:=' s:=VFS_PROLOGUE('+FixFieldName(Enum.Names[0])+'^.v_mount);'#13#10; - FileWrite(F,Pchar(S)^,Length(S)); //call - S:=' if (v^.'+Enum.name+'<>nil) then'#13#10; - S:=S+' begin'#13#10; - S:=S+' Result:='+Enum.name+'_t(v^.'+Enum.name+')(@'+Name+');'#13#10; - S:=S+' end else'#13#10; - S:=S+' begin'#13#10; - S:=S+' Result:='+Enum.name+'_t(v^.vop_bypass)(@'+Name+');'#13#10; - S:=S+' end;'#13#10; - FileWrite(F,Pchar(S)^,Length(S)); + S:=S+' Result:='+Enum.name+'_t(c)(@a);'#13#10; - S:=' VFS_EPILOGUE(s);'#13#10; + S:=S+' VFS_EPILOGUE(s);'#13#10; FileWrite(F,Pchar(S)^,Length(S)); //post if (Enum.post<>'') then begin - S:=' '+Enum.post+'(@'+Name+',Result);'#13#10; + S:=' '+Enum.post+'(@a,Result'; + if (Upcase(Enum.name)='VOP_WRITE') then + begin + S:=S+',osize,ooffset'; + end; + S:=S+');'#13#10; FileWrite(F,Pchar(S)^,Length(S)); end;