mirror of https://github.com/red-prig/fpPS4.git
This commit is contained in:
Pavel
parent
0af0357ff5
commit
228118c15e
183
chip/pm4_me.pas
183
chip/pm4_me.pas
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@ -208,18 +208,12 @@ end;
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var
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FCmdPool:TvCmdPool;
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procedure pm4_DrawPrepare(SH_REG:PSH_REG_GROUP;
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CX_REG:PCONTEXT_REG_GROUP;
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UC_REG:PUSERCONFIG_REG_SHORT;
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procedure pm4_DrawPrepare(var rt_info:t_pm4_rt_info;
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CmdBuffer:TvCmdBuffer;
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RenderCmd:TvRenderTargets);
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var
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i:Integer;
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GPU_REGS:TGPU_REGS;
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FShaderGroup:TvShaderGroup;
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FAttrBuilder:TvAttrBuilder;
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FUniformBuilder:TvUniformBuilder;
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@ -227,8 +221,6 @@ var
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RP_KEY:TvRenderPassKey;
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RP:TvRenderPass2;
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BI:TBLEND_INFO;
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GP_KEY:TvGraphicsPipelineKey;
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GP:TvGraphicsPipeline2;
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@ -247,52 +239,25 @@ var
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FDescriptorGroup:TvDescriptorGroup;
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begin
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GPU_REGS:=Default(TGPU_REGS);
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GPU_REGS.SH_REG:=SH_REG;
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GPU_REGS.CX_REG:=CX_REG;
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GPU_REGS.UC_REG:=UC_REG;
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for i:=0 to 31 do
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begin
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if (CX_REG^.SPI_PS_INPUT_CNTL[i].OFFSET<>0) and (CX_REG^.SPI_PS_INPUT_CNTL[i].OFFSET<>i) then
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begin
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Assert(false, 'SPI_PS_INPUT_CNTL['+IntToStr(i)+'].OFFSET=' +IntToStr(CX_REG^.SPI_PS_INPUT_CNTL[i].OFFSET ));
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end;
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Assert(CX_REG^.SPI_PS_INPUT_CNTL[i].DEFAULT_VAL =0,'SPI_PS_INPUT_CNTL['+IntToStr(i)+'].DEFAULT_VAL=' +IntToStr(CX_REG^.SPI_PS_INPUT_CNTL[i].DEFAULT_VAL ));
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Assert(CX_REG^.SPI_PS_INPUT_CNTL[i].FLAT_SHADE =0,'SPI_PS_INPUT_CNTL['+IntToStr(i)+'].FLAT_SHADE=' +IntToStr(CX_REG^.SPI_PS_INPUT_CNTL[i].FLAT_SHADE ));
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Assert(CX_REG^.SPI_PS_INPUT_CNTL[i].FP16_INTERP_MODE=0,'SPI_PS_INPUT_CNTL['+IntToStr(i)+'].FP16_INTERP_MODE='+IntToStr(CX_REG^.SPI_PS_INPUT_CNTL[i].FP16_INTERP_MODE));
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end;
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{fdump_ps:=}DumpPS(GPU_REGS);
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{fdump_vs:=}DumpVS(GPU_REGS);
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FShaderGroup:=FetchShaderGroup(GPU_REGS,nil{@pa});
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Assert(FShaderGroup<>nil);
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RP_KEY.Clear;
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RenderCmd.RT_COUNT:=0;
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RenderCmd.RT_COUNT:=rt_info.RT_COUNT;
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if GPU_REGS.COMP_ENABLE then
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For i:=0 to GPU_REGS.GET_HI_RT do
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if (rt_info.RT_COUNT<>0) then
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For i:=0 to rt_info.RT_COUNT-1 do
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begin
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RenderCmd.RT_INFO[RenderCmd.RT_COUNT]:=GPU_REGS.GET_RT_INFO(i);
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RenderCmd.RT_INFO[i]:=rt_info.RT_INFO[i];
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//hack
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//RT_INFO[RT_COUNT].IMAGE_USAGE:=TM_CLEAR or TM_WRITE;
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//
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RP_KEY.AddColorAt(RenderCmd.RT_INFO[RenderCmd.RT_COUNT].attachment,
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RenderCmd.RT_INFO[RenderCmd.RT_COUNT].FImageInfo.cformat,
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RenderCmd.RT_INFO[RenderCmd.RT_COUNT].IMAGE_USAGE,
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RenderCmd.RT_INFO[RenderCmd.RT_COUNT].FImageInfo.params.samples);
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Inc(RenderCmd.RT_COUNT);
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RP_KEY.AddColorAt(RenderCmd.RT_INFO[i].attachment,
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RenderCmd.RT_INFO[i].FImageInfo.cformat,
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RenderCmd.RT_INFO[i].IMAGE_USAGE,
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RenderCmd.RT_INFO[i].FImageInfo.params.samples);
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end;
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if GPU_REGS.DB_ENABLE then
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if rt_info.DB_ENABLE then
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begin
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RenderCmd.DB_INFO:=GPU_REGS.GET_DB_INFO;
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RenderCmd.DB_INFO:=rt_info.DB_INFO;
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RP_KEY.AddDepthAt(RenderCmd.RT_COUNT, //add to last attachment id
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RenderCmd.DB_INFO.FImageInfo.cformat,
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@ -305,22 +270,20 @@ begin
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RP:=FetchRenderPass(CmdBuffer,@RP_KEY);
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BI:=GPU_REGS.GET_BLEND_INFO;
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GP_KEY.Clear;
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GP_KEY.FRenderPass :=RP;
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GP_KEY.FShaderGroup:=FShaderGroup;
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GP_KEY.FShaderGroup:=rt_info.ShaderGroup;
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GP_KEY.SetBlendInfo(BI.logicOp,@BI.blendConstants);
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GP_KEY.SetBlendInfo(rt_info.BLEND_INFO.logicOp,@rt_info.BLEND_INFO.blendConstants);
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GP_KEY.SetPrimType (GPU_REGS.GET_PRIM_TYPE);
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GP_KEY.SetPrimReset(GPU_REGS.GET_PRIM_RESET);
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GP_KEY.SetPrimType (TVkPrimitiveTopology(rt_info.PRIM_TYPE));
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GP_KEY.SetPrimReset(rt_info.PRIM_RESET);
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For i:=0 to 15 do
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if GPU_REGS.VP_ENABLE(i) then
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if (rt_info.VP_COUNT<>0) then
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For i:=0 to rt_info.VP_COUNT-1 do
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begin
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GP_KEY.AddVPort(GPU_REGS.GET_VPORT(i),GPU_REGS.GET_SCISSOR(i));
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GP_KEY.AddVPort(rt_info.VPORT[i],rt_info.SCISSOR[i]);
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end;
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if (RenderCmd.RT_COUNT<>0) then
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@ -330,19 +293,19 @@ begin
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end;
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FAttrBuilder:=Default(TvAttrBuilder);
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FShaderGroup.ExportAttrBuilder(FAttrBuilder,GPU_REGS);
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rt_info.ShaderGroup.ExportAttrBuilder(FAttrBuilder,@rt_info.USERDATA);
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if not limits.VK_EXT_vertex_input_dynamic_state then
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begin
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GP_KEY.SetVertexInput(FAttrBuilder);
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end;
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GP_KEY.rasterizer :=GPU_REGS.GET_RASTERIZATION;
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GP_KEY.multisampling:=GPU_REGS.GET_MULTISAMPLE;
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GP_KEY.rasterizer :=rt_info.RASTERIZATION;
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GP_KEY.multisampling:=rt_info.MULTISAMPLE;
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GP_KEY.SetProvoking(GPU_REGS.GET_PROVOKING);
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GP_KEY.SetProvoking(TVkProvokingVertexModeEXT(rt_info.PROVOKING));
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if GPU_REGS.DB_ENABLE then
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if rt_info.DB_ENABLE then
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begin
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GP_KEY.DepthStencil:=RenderCmd.DB_INFO.ds_state;
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end;
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@ -354,7 +317,7 @@ begin
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FB_KEY:=Default(TvFramebufferImagelessKey);
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FB_KEY.SetRenderPass(RP);
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FB_KEY.SetSize(GPU_REGS.GET_SCREEN_SIZE);
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FB_KEY.SetSize(rt_info.SCREEN_SIZE);
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if (RenderCmd.RT_COUNT<>0) then
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For i:=0 to RenderCmd.RT_COUNT-1 do
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@ -362,7 +325,7 @@ begin
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FB_KEY.AddImageAt(RenderCmd.RT_INFO[i].FImageInfo);
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end;
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if GPU_REGS.DB_ENABLE then
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if rt_info.DB_ENABLE then
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begin
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FB_KEY.AddImageAt(RenderCmd.DB_INFO.FImageInfo);
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end;
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@ -371,13 +334,13 @@ begin
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FB_KEY2:=Default(TvFramebufferBindedKey);
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FB_KEY2.SetRenderPass(RP);
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FB_KEY2.SetSize(GPU_REGS.GET_SCREEN_SIZE);
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FB_KEY2.SetSize(rt_info.SCREEN_SIZE);
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end;
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RenderCmd.FRenderPass:=RP;
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RenderCmd.FPipeline :=GP;
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RenderCmd.FRenderArea:=GPU_REGS.GET_SCREEN;
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RenderCmd.FRenderArea:=rt_info.SCREEN_RECT;
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if limits.VK_KHR_imageless_framebuffer then
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begin
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@ -422,7 +385,7 @@ begin
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end;
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if GPU_REGS.DB_ENABLE then
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if rt_info.DB_ENABLE then
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begin
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RenderCmd.AddClearColor(RenderCmd.DB_INFO.CLEAR_VALUE);
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@ -459,7 +422,7 @@ begin
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////////
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FUniformBuilder:=Default(TvUniformBuilder);
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FShaderGroup.ExportUnifBuilder(FUniformBuilder,GPU_REGS);
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rt_info.ShaderGroup.ExportUnifBuilder(FUniformBuilder,@rt_info.USERDATA);
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if (Length(FUniformBuilder.FImages)<>0) then
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begin
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@ -515,7 +478,7 @@ begin
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if (FDescriptorGroup=nil) then
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begin
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FDescriptorGroup:=FetchDescriptorGroup(CmdBuffer,FShaderGroup.FLayout);
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FDescriptorGroup:=FetchDescriptorGroup(CmdBuffer,rt_info.ShaderGroup.FLayout);
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end;
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FDescriptorGroup.FSets[fset].BindImg(bind,0,
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@ -537,7 +500,7 @@ begin
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if (FDescriptorGroup=nil) then
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begin
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FDescriptorGroup:=FetchDescriptorGroup(CmdBuffer,FShaderGroup.FLayout);
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FDescriptorGroup:=FetchDescriptorGroup(CmdBuffer,rt_info.ShaderGroup.FLayout);
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end;
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FDescriptorGroup.FSets[fset].BindSmp(bind,0,sm.FHandle);
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@ -573,7 +536,7 @@ begin
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if (FDescriptorGroup=nil) then
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begin
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FDescriptorGroup:=FetchDescriptorGroup(CmdBuffer,FShaderGroup.FLayout);
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FDescriptorGroup:=FetchDescriptorGroup(CmdBuffer,rt_info.ShaderGroup.FLayout);
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end;
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FDescriptorGroup.FSets[fset].BindBuf(bind,0,
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@ -592,8 +555,6 @@ begin
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CmdBuffer.BindSets(VK_PIPELINE_BIND_POINT_GRAPHICS,FDescriptorGroup);
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end;
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CmdBuffer.FinstanceCount:=GPU_REGS.UC_REG^.VGT_NUM_INSTANCES;
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CmdBuffer.FINDEX_TYPE :=GPU_REGS.GET_INDEX_TYPE;
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end;
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procedure pm4_Writeback(CmdBuffer:TvCmdBuffer;
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@ -679,7 +640,7 @@ begin
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//write back
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end;
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procedure pm4_DrawIndex2(node:p_pm4_node_DrawIndex2);
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procedure pm4_Draw(node:p_pm4_node_draw);
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var
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RenderCmd:TvRenderTargets;
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@ -703,72 +664,26 @@ begin
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RenderCmd:=TvRenderTargets.Create;
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pm4_DrawPrepare(@node^.SH_REG,
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@node^.CX_REG,
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@node^.UC_REG,
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pm4_DrawPrepare(node^.rt_info,
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CmdBuffer,
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RenderCmd);
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CmdBuffer.DrawIndex2(node^.addr,
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node^.UC_REG.VGT_NUM_INDICES);
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/////////
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CmdBuffer.FinstanceCount:=node^.numInstances;
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CmdBuffer.FINDEX_TYPE :=TVkIndexType(node^.INDEX_TYPE);
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CmdBuffer.EndRenderPass;
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pm4_Writeback(CmdBuffer,RenderCmd);
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r:=CmdBuffer.QueueSubmit;
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if (r<>VK_SUCCESS) then
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begin
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Assert(false,'QueueSubmit');
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case node^.ntype of
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ntDrawIndex2:
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begin
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CmdBuffer.DrawIndex2(Pointer(node^.indexBase),node^.indexCount);
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end;
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ntDrawIndexAuto:
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begin
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CmdBuffer.DrawIndexAuto(node^.indexCount);
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end;
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else;
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Assert(false);
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end;
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Writeln('QueueSubmit:',r);
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r:=CmdBuffer.Wait(QWORD(-1));
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Writeln('CmdBuffer:',r);
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r:=RenderQueue.WaitIdle;
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Writeln('WaitIdle:',r);
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CmdBuffer.ReleaseResource;
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CmdBuffer.Free;
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end;
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procedure pm4_DrawIndexAuto(node:p_pm4_node_DrawIndexAuto);
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var
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RenderCmd:TvRenderTargets;
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CmdBuffer:TvCmdBuffer;
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r:TVkResult;
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begin
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StartFrameCapture;
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//
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if (FCmdPool=nil) then
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begin
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FCmdPool:=TvCmdPool.Create(VulkanApp.FGFamily);
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end;
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CmdBuffer:=TvCmdBuffer.Create(FCmdPool,RenderQueue);
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//CmdBuffer.submit_id:=submit_id;
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//
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RenderCmd:=TvRenderTargets.Create;
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pm4_DrawPrepare(@node^.SH_REG,
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@node^.CX_REG,
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@node^.UC_REG,
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CmdBuffer,
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RenderCmd);
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CmdBuffer.DrawIndexAuto(node^.UC_REG.VGT_NUM_INDICES);
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/////////
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CmdBuffer.EndRenderPass;
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@ -887,8 +802,8 @@ begin
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Writeln('+',node^.ntype);
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case node^.ntype of
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ntDrawIndex2 :pm4_DrawIndex2 (Pointer(node));
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ntDrawIndexAuto:pm4_DrawIndexAuto(Pointer(node));
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ntDrawIndex2 :pm4_Draw (Pointer(node));
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ntDrawIndexAuto:pm4_Draw (Pointer(node));
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ntEventWriteEop:pm4_EventWriteEop(Pointer(node),me);
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ntSubmitFlipEop:pm4_SubmitFlipEop(Pointer(node),me);
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else
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@ -1300,7 +1300,6 @@ end;
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procedure onIndexBufferSize(pctx:p_pfp_ctx;Body:PPM4CMDDRAWINDEXBUFFERSIZE);
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begin
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pctx^.CX_REG.VGT_DMA_SIZE :=Body^.numIndices;
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pctx^.UC_REG.VGT_NUM_INDICES:=Body^.numIndices;
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end;
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@ -1325,9 +1324,6 @@ begin
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end;
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procedure onDrawIndex2(pctx:p_pfp_ctx;Body:PPM4CMDDRAWINDEX2);
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var
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addr:Pointer;
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size:QWORD;
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begin
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if (DWORD(Body^.drawInitiator)<>0) then
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begin
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@ -1341,19 +1337,7 @@ begin
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pctx^.UC_REG.VGT_NUM_INDICES :=Body^.indexCount;
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pctx^.CX_REG.VGT_DRAW_INITIATOR :=Body^.drawInitiator;
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addr:=nil;
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size:=0;
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if get_dmem_ptr(PPointer(@Body^.indexBaseLo)^,@addr,@size) then
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begin
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//
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end else
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begin
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Assert(false,'addr:0x'+HexStr(PPointer(@Body^.indexBaseLo)^)+' not in dmem!');
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end;
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pctx^.stream_dcb.DrawIndex2(addr,
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pctx^.SH_REG,
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pctx^.stream_dcb.DrawIndex2(pctx^.SH_REG,
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pctx^.CX_REG,
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pctx^.UC_REG);
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end;
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@ -1439,6 +1423,9 @@ begin
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mmCB_COLOR6_DCC_BASE,
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mmCB_COLOR7_DCC_BASE,
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mmDB_STENCIL_CLEAR,
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mmDB_RENDER_CONTROL,
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mmDB_HTILE_SURFACE:
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begin
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if pctx^.print_hint then
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@ -6,6 +6,7 @@ unit pm4_stream;
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interface
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uses
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sysutils,
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mqueue,
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LFQueue,
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md_map,
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@ -14,7 +15,30 @@ uses
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si_ci_vi_merged_offset,
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si_ci_vi_merged_enum,
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si_ci_vi_merged_registers,
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si_ci_vi_merged_groups;
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si_ci_vi_merged_groups,
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Vulkan,
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vDevice,
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vBuffer,
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vHostBufferManager,
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vImage,
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vImageManager,
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vRender,
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vRenderPassManager,
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vPipelineManager,
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vFramebufferManager,
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vShader,
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vShaderExt,
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vShaderManager,
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vRegs2Vulkan,
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vCmdBuffer,
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vPipeline,
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vSetsPoolManager,
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vSampler,
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vSamplerManager,
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shader_dump
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;
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type
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t_cache_block_allocator=object
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@ -50,6 +74,34 @@ type
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Procedure Free;
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end;
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p_pm4_rt_info=^t_pm4_rt_info;
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t_pm4_rt_info=object
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USERDATA:TGPU_USERDATA;
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ShaderGroup:TvShaderGroup;
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RT_INFO:array[0..7] of TRT_INFO;
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DB_INFO:TDB_INFO;
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BLEND_INFO:TBLEND_INFO;
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VPORT :array[0..15] of TVkViewport;
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SCISSOR:array[0..15] of TVkRect2D;
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RASTERIZATION:TVkPipelineRasterizationStateCreateInfo;
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MULTISAMPLE :TVkPipelineMultisampleStateCreateInfo;
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SCREEN_RECT:TVkRect2D;
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SCREEN_SIZE:TVkExtent2D;
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RT_COUNT :Byte;
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DB_ENABLE :Boolean;
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PRIM_TYPE :Byte;
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PRIM_RESET:Byte;
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VP_COUNT :Byte;
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PROVOKING :Byte;
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end;
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|
||||
t_pm4_node_type=(
|
||||
ntLoadConstRam,
|
||||
ntEventWrite,
|
||||
|
|
@ -143,20 +195,17 @@ type
|
|||
CX_REG:TCONTEXT_REG_GROUP; // 0xA000
|
||||
end;
|
||||
|
||||
p_pm4_node_DrawIndex2=^t_pm4_node_DrawIndex2;
|
||||
t_pm4_node_DrawIndex2=object(t_pm4_node)
|
||||
addr :Pointer;
|
||||
//
|
||||
SH_REG:TSH_REG_GROUP; // 0x2C00
|
||||
CX_REG:TCONTEXT_REG_GROUP; // 0xA000
|
||||
UC_REG:TUSERCONFIG_REG_SHORT; // 0xC000
|
||||
end;
|
||||
p_pm4_node_draw=^t_pm4_node_draw;
|
||||
t_pm4_node_draw=object(t_pm4_node)
|
||||
rt_info:t_pm4_rt_info;
|
||||
|
||||
p_pm4_node_DrawIndexAuto=^t_pm4_node_DrawIndexAuto;
|
||||
t_pm4_node_DrawIndexAuto=object(t_pm4_node)
|
||||
SH_REG:TSH_REG_GROUP; // 0x2C00
|
||||
CX_REG:TCONTEXT_REG_GROUP; // 0xA000
|
||||
UC_REG:TUSERCONFIG_REG_SHORT; // 0xC000
|
||||
indexBase :QWORD;
|
||||
indexOffset :DWORD;
|
||||
indexCount :DWORD;
|
||||
numInstances:DWORD;
|
||||
|
||||
INDEX_TYPE:Byte;
|
||||
SWAP_MODE :Byte;
|
||||
end;
|
||||
|
||||
p_pm4_node_DispatchDirect=^t_pm4_node_DispatchDirect;
|
||||
|
|
@ -188,10 +237,14 @@ type
|
|||
procedure FastClear (var CX_REG:TCONTEXT_REG_GROUP);
|
||||
procedure Resolve (var CX_REG:TCONTEXT_REG_GROUP);
|
||||
function ColorControl (var CX_REG:TCONTEXT_REG_GROUP):Boolean;
|
||||
procedure DrawIndex2 (addr:Pointer;
|
||||
procedure Build_rt_info(var rt_info:t_pm4_rt_info;var GPU_REGS:TGPU_REGS);
|
||||
procedure BuildDraw (ntype:t_pm4_node_type;
|
||||
var SH_REG:TSH_REG_GROUP;
|
||||
var CX_REG:TCONTEXT_REG_GROUP;
|
||||
var UC_REG:TUSERCONFIG_REG_SHORT);
|
||||
procedure DrawIndex2 (var SH_REG:TSH_REG_GROUP;
|
||||
var CX_REG:TCONTEXT_REG_GROUP;
|
||||
var UC_REG:TUSERCONFIG_REG_SHORT);
|
||||
procedure DrawIndexAuto(var SH_REG:TSH_REG_GROUP;
|
||||
var CX_REG:TCONTEXT_REG_GROUP;
|
||||
var UC_REG:TUSERCONFIG_REG_SHORT);
|
||||
|
|
@ -399,42 +452,120 @@ begin
|
|||
|
||||
end;
|
||||
|
||||
procedure t_pm4_stream.DrawIndex2(addr:Pointer;
|
||||
var SH_REG:TSH_REG_GROUP;
|
||||
procedure t_pm4_stream.Build_rt_info(var rt_info:t_pm4_rt_info;var GPU_REGS:TGPU_REGS);
|
||||
var
|
||||
i:Integer;
|
||||
begin
|
||||
for i:=0 to 31 do
|
||||
begin
|
||||
if (GPU_REGS.CX_REG^.SPI_PS_INPUT_CNTL[i].OFFSET<>0) and (GPU_REGS.CX_REG^.SPI_PS_INPUT_CNTL[i].OFFSET<>i) then
|
||||
begin
|
||||
Assert(false, 'SPI_PS_INPUT_CNTL['+IntToStr(i)+'].OFFSET=' +IntToStr(GPU_REGS.CX_REG^.SPI_PS_INPUT_CNTL[i].OFFSET ));
|
||||
end;
|
||||
Assert(GPU_REGS.CX_REG^.SPI_PS_INPUT_CNTL[i].DEFAULT_VAL =0,'SPI_PS_INPUT_CNTL['+IntToStr(i)+'].DEFAULT_VAL=' +IntToStr(GPU_REGS.CX_REG^.SPI_PS_INPUT_CNTL[i].DEFAULT_VAL ));
|
||||
Assert(GPU_REGS.CX_REG^.SPI_PS_INPUT_CNTL[i].FLAT_SHADE =0,'SPI_PS_INPUT_CNTL['+IntToStr(i)+'].FLAT_SHADE=' +IntToStr(GPU_REGS.CX_REG^.SPI_PS_INPUT_CNTL[i].FLAT_SHADE ));
|
||||
Assert(GPU_REGS.CX_REG^.SPI_PS_INPUT_CNTL[i].FP16_INTERP_MODE=0,'SPI_PS_INPUT_CNTL['+IntToStr(i)+'].FP16_INTERP_MODE='+IntToStr(GPU_REGS.CX_REG^.SPI_PS_INPUT_CNTL[i].FP16_INTERP_MODE));
|
||||
end;
|
||||
|
||||
GPU_REGS.export_user_data(@rt_info.USERDATA);
|
||||
|
||||
{fdump_ps:=}DumpPS(GPU_REGS);
|
||||
{fdump_vs:=}DumpVS(GPU_REGS);
|
||||
|
||||
rt_info.ShaderGroup:=FetchShaderGroupRT(GPU_REGS,nil{@pa});
|
||||
Assert(rt_info.ShaderGroup<>nil);
|
||||
|
||||
rt_info.RT_COUNT:=0;
|
||||
|
||||
if GPU_REGS.COMP_ENABLE then
|
||||
For i:=0 to GPU_REGS.GET_HI_RT do
|
||||
begin
|
||||
rt_info.RT_INFO[rt_info.RT_COUNT]:=GPU_REGS.GET_RT_INFO(i);
|
||||
|
||||
Inc(rt_info.RT_COUNT);
|
||||
end;
|
||||
|
||||
rt_info.DB_ENABLE:=GPU_REGS.DB_ENABLE;
|
||||
|
||||
if rt_info.DB_ENABLE then
|
||||
begin
|
||||
rt_info.DB_INFO:=GPU_REGS.GET_DB_INFO;
|
||||
end;
|
||||
|
||||
rt_info.BLEND_INFO:=GPU_REGS.GET_BLEND_INFO;
|
||||
|
||||
rt_info.PRIM_TYPE :=ord(GPU_REGS.GET_PRIM_TYPE);
|
||||
rt_info.PRIM_RESET:=GPU_REGS.GET_PRIM_RESET;
|
||||
|
||||
rt_info.VP_COUNT:=0;
|
||||
|
||||
For i:=0 to 15 do
|
||||
if GPU_REGS.VP_ENABLE(i) then
|
||||
begin
|
||||
rt_info.VPORT [rt_info.VP_COUNT]:=GPU_REGS.GET_VPORT(i);
|
||||
rt_info.SCISSOR[rt_info.VP_COUNT]:=GPU_REGS.GET_SCISSOR(i) ;
|
||||
|
||||
Inc(rt_info.VP_COUNT);
|
||||
end;
|
||||
|
||||
rt_info.RASTERIZATION:=GPU_REGS.GET_RASTERIZATION;
|
||||
rt_info.MULTISAMPLE :=GPU_REGS.GET_MULTISAMPLE;
|
||||
|
||||
rt_info.PROVOKING:=ord(GPU_REGS.GET_PROVOKING);
|
||||
|
||||
rt_info.SCREEN_RECT:=GPU_REGS.GET_SCREEN;
|
||||
rt_info.SCREEN_SIZE:=GPU_REGS.GET_SCREEN_SIZE;
|
||||
|
||||
end;
|
||||
|
||||
procedure t_pm4_stream.BuildDraw(ntype:t_pm4_node_type;
|
||||
var SH_REG:TSH_REG_GROUP;
|
||||
var CX_REG:TCONTEXT_REG_GROUP;
|
||||
var UC_REG:TUSERCONFIG_REG_SHORT);
|
||||
var
|
||||
GPU_REGS:TGPU_REGS;
|
||||
|
||||
node:p_pm4_node_draw;
|
||||
|
||||
begin
|
||||
GPU_REGS:=Default(TGPU_REGS);
|
||||
GPU_REGS.SH_REG:=@SH_REG;
|
||||
GPU_REGS.CX_REG:=@CX_REG;
|
||||
GPU_REGS.UC_REG:=@UC_REG;
|
||||
|
||||
node:=allocator.Alloc(SizeOf(t_pm4_node_draw));
|
||||
|
||||
node^.ntype :=ntype;
|
||||
|
||||
Build_rt_info(node^.rt_info,GPU_REGS);
|
||||
|
||||
node^.indexBase :=CX_REG.VGT_DMA_BASE or (QWORD(CX_REG.VGT_DMA_BASE_HI.BASE_ADDR) shl 32);
|
||||
node^.indexOffset :=CX_REG.VGT_INDX_OFFSET;
|
||||
node^.indexCount :=UC_REG.VGT_NUM_INDICES;
|
||||
node^.numInstances:=UC_REG.VGT_NUM_INSTANCES;
|
||||
|
||||
node^.INDEX_TYPE:=ord(GPU_REGS.GET_INDEX_TYPE);
|
||||
node^.SWAP_MODE :=CX_REG.VGT_DMA_INDEX_TYPE.SWAP_MODE;
|
||||
|
||||
add_node(node);
|
||||
end;
|
||||
|
||||
procedure t_pm4_stream.DrawIndex2(var SH_REG:TSH_REG_GROUP;
|
||||
var CX_REG:TCONTEXT_REG_GROUP;
|
||||
var UC_REG:TUSERCONFIG_REG_SHORT);
|
||||
var
|
||||
node:p_pm4_node_DrawIndex2;
|
||||
begin
|
||||
if ColorControl(CX_REG) then Exit;
|
||||
|
||||
node:=allocator.Alloc(SizeOf(t_pm4_node_DrawIndex2));
|
||||
|
||||
node^.ntype :=ntDrawIndex2;
|
||||
node^.addr :=addr;
|
||||
node^.SH_REG:=SH_REG;
|
||||
node^.CX_REG:=CX_REG;
|
||||
node^.UC_REG:=UC_REG;
|
||||
|
||||
add_node(node);
|
||||
BuildDraw(ntDrawIndex2,SH_REG,CX_REG,UC_REG);
|
||||
end;
|
||||
|
||||
procedure t_pm4_stream.DrawIndexAuto(var SH_REG:TSH_REG_GROUP;
|
||||
var CX_REG:TCONTEXT_REG_GROUP;
|
||||
var UC_REG:TUSERCONFIG_REG_SHORT);
|
||||
var
|
||||
node:p_pm4_node_DrawIndexAuto;
|
||||
begin
|
||||
if ColorControl(CX_REG) then Exit;
|
||||
|
||||
node:=allocator.Alloc(SizeOf(t_pm4_node_DrawIndexAuto));
|
||||
|
||||
node^.ntype :=ntDrawIndexAuto;
|
||||
node^.SH_REG:=SH_REG;
|
||||
node^.CX_REG:=CX_REG;
|
||||
node^.UC_REG:=UC_REG;
|
||||
|
||||
add_node(node);
|
||||
BuildDraw(ntDrawIndexAuto,SH_REG,CX_REG,UC_REG);
|
||||
end;
|
||||
|
||||
procedure t_pm4_stream.DispatchDirect(var SH_REG:TSH_REG_GROUP);
|
||||
|
|
|
|||
|
|
@ -129,9 +129,9 @@ type
|
|||
//Procedure dmaData(src:DWORD;dst:Pointer;byteCount:DWORD;isBlocking:Boolean);
|
||||
//Procedure writeAtEndOfShader(eventType:Byte;dst:Pointer;value:DWORD);
|
||||
|
||||
Procedure DrawIndexOffset2(Addr:Pointer;OFFSET,INDICES:DWORD);
|
||||
Procedure DrawIndex2(Addr:Pointer;INDICES:DWORD);
|
||||
Procedure DrawIndexAuto(INDICES:DWORD);
|
||||
Procedure DrawIndexOffset2(IndexBase:Pointer;indexOffset,indexCount:DWORD);
|
||||
Procedure DrawIndex2(IndexBase:Pointer;indexCount:DWORD);
|
||||
Procedure DrawIndexAuto(indexCount:DWORD);
|
||||
end;
|
||||
|
||||
implementation
|
||||
|
|
@ -879,8 +879,9 @@ begin
|
|||
end;
|
||||
end;
|
||||
|
||||
Procedure TvCmdBuffer.DrawIndexOffset2(Addr:Pointer;OFFSET,INDICES:DWORD);
|
||||
Procedure TvCmdBuffer.DrawIndexOffset2(IndexBase:Pointer;indexOffset,indexCount:DWORD);
|
||||
var
|
||||
Addr:Pointer;
|
||||
rb:TvHostBuffer;
|
||||
Size:TVkDeviceSize;
|
||||
BufOffset:TVkDeviceSize;
|
||||
|
|
@ -893,7 +894,13 @@ begin
|
|||
|
||||
if (FinstanceCount=0) then FinstanceCount:=1;
|
||||
|
||||
Size:=(OFFSET+INDICES)*GET_INDEX_TYPE_SIZE(FINDEX_TYPE);
|
||||
Size:=(indexOffset+indexCount)*GET_INDEX_TYPE_SIZE(FINDEX_TYPE);
|
||||
|
||||
Addr:=nil;
|
||||
if not get_dmem_ptr(IndexBase,@Addr,nil) then
|
||||
begin
|
||||
Assert(false,'addr:0x'+HexStr(IndexBase)+' not in dmem!');
|
||||
end;
|
||||
|
||||
rb:=FetchHostBuffer(Self,QWORD(Addr),Size,ord(VK_BUFFER_USAGE_INDEX_BUFFER_BIT));
|
||||
Assert(rb<>nil);
|
||||
|
|
@ -915,17 +922,17 @@ begin
|
|||
begin
|
||||
vkCmdDrawIndexed(
|
||||
Fcmdbuf,
|
||||
INDICES, //indexCount
|
||||
indexCount, //indexCount
|
||||
FinstanceCount, //instanceCount
|
||||
OFFSET, //firstIndex
|
||||
indexOffset, //firstIndex
|
||||
0, //vertexOffset
|
||||
0); //firstInstance
|
||||
end;
|
||||
DI_PT_QUADLIST:
|
||||
begin
|
||||
Assert(FinstanceCount<=1,'instance DI_PT_QUADLIST');
|
||||
Assert(OFFSET=0,'OFFSET DI_PT_QUADLIST');
|
||||
h:=INDICES div 4;
|
||||
Assert(indexOffset=0,'OFFSET DI_PT_QUADLIST');
|
||||
h:=indexCount div 4;
|
||||
if (h>0) then h:=h-1;
|
||||
For i:=0 to h do
|
||||
begin
|
||||
|
|
@ -944,12 +951,12 @@ begin
|
|||
|
||||
end;
|
||||
|
||||
Procedure TvCmdBuffer.DrawIndex2(Addr:Pointer;INDICES:DWORD);
|
||||
Procedure TvCmdBuffer.DrawIndex2(IndexBase:Pointer;indexCount:DWORD);
|
||||
begin
|
||||
DrawIndexOffset2(Addr,0,INDICES);
|
||||
DrawIndexOffset2(IndexBase,0,indexCount);
|
||||
end;
|
||||
|
||||
Procedure TvCmdBuffer.DrawIndexAuto(INDICES:DWORD);
|
||||
Procedure TvCmdBuffer.DrawIndexAuto(indexCount:DWORD);
|
||||
var
|
||||
i,h:DWORD;
|
||||
begin
|
||||
|
|
@ -965,7 +972,7 @@ begin
|
|||
begin
|
||||
vkCmdDraw(
|
||||
FCmdbuf,
|
||||
INDICES, //vertexCount
|
||||
indexCount, //vertexCount
|
||||
FinstanceCount, //instanceCount
|
||||
0, //firstVertex
|
||||
0); //firstInstance
|
||||
|
|
@ -983,7 +990,7 @@ begin
|
|||
//0 1 2
|
||||
//0 2 3
|
||||
|
||||
h:=INDICES div 3;
|
||||
h:=indexCount div 3;
|
||||
if (h>0) then h:=h-1;
|
||||
For i:=0 to h do
|
||||
begin
|
||||
|
|
@ -1001,7 +1008,7 @@ begin
|
|||
DI_PT_QUADLIST:
|
||||
begin
|
||||
Assert(FinstanceCount<=1,'instance DI_PT_QUADLIST');
|
||||
h:=INDICES div 4;
|
||||
h:=indexCount div 4;
|
||||
if (h>0) then h:=h-1;
|
||||
For i:=0 to h do
|
||||
begin
|
||||
|
|
|
|||
|
|
@ -76,6 +76,8 @@ type
|
|||
PCONTEXT_REG_GROUP =^TCONTEXT_REG_GROUP;
|
||||
PUSERCONFIG_REG_SHORT=^TUSERCONFIG_REG_SHORT;
|
||||
|
||||
PGPU_USERDATA=^TGPU_USERDATA;
|
||||
|
||||
PGPU_REGS=^TGPU_REGS;
|
||||
TGPU_REGS=packed object
|
||||
SH_REG:PSH_REG_GROUP; // 0x2C00
|
||||
|
|
@ -111,6 +113,12 @@ type
|
|||
|
||||
Function get_code_addr(FStage:TvShaderStage):Pointer;
|
||||
Function get_user_data(FStage:TvShaderStage):Pointer;
|
||||
procedure export_user_data(dst:PGPU_USERDATA);
|
||||
end;
|
||||
|
||||
TGPU_USERDATA=packed object
|
||||
A:array[TvShaderStage] of TSPI_USER_DATA;
|
||||
Function get_user_data(FStage:TvShaderStage):Pointer;
|
||||
end;
|
||||
|
||||
function GET_INDEX_TYPE_SIZE(i:TVkIndexType):Byte;
|
||||
|
|
@ -1476,6 +1484,22 @@ begin
|
|||
end;
|
||||
end;
|
||||
|
||||
procedure TGPU_REGS.export_user_data(dst:PGPU_USERDATA);
|
||||
begin
|
||||
dst^.A[vShaderStageLs]:=SH_REG^.SPI_SHADER_USER_DATA_LS;
|
||||
dst^.A[vShaderStageHs]:=SH_REG^.SPI_SHADER_USER_DATA_HS;
|
||||
dst^.A[vShaderStageEs]:=SH_REG^.SPI_SHADER_USER_DATA_ES;
|
||||
dst^.A[vShaderStageGs]:=SH_REG^.SPI_SHADER_USER_DATA_GS;
|
||||
dst^.A[vShaderStageVs]:=SH_REG^.SPI_SHADER_USER_DATA_VS;
|
||||
dst^.A[vShaderStagePs]:=SH_REG^.SPI_SHADER_USER_DATA_PS;
|
||||
dst^.A[vShaderStageCs]:=SH_REG^.COMPUTE_USER_DATA;
|
||||
end;
|
||||
|
||||
Function TGPU_USERDATA.get_user_data(FStage:TvShaderStage):Pointer;
|
||||
begin
|
||||
Result:=@A[FStage];
|
||||
end;
|
||||
|
||||
///
|
||||
|
||||
function _get_vsharp_cformat(PV:PVSharpResource4):TVkFormat;
|
||||
|
|
|
|||
|
|
@ -215,8 +215,8 @@ type
|
|||
FLayout:TvPipelineLayout;
|
||||
Procedure Clear;
|
||||
Function Compile:Boolean;
|
||||
Procedure ExportAttrBuilder(var AttrBuilder:TvAttrBuilder;var GPU_REGS:TGPU_REGS);
|
||||
Procedure ExportUnifBuilder(var UniformBuilder:TvUniformBuilder;var GPU_REGS:TGPU_REGS);
|
||||
Procedure ExportAttrBuilder(var AttrBuilder :TvAttrBuilder ;GPU_USERDATA:PGPU_USERDATA);
|
||||
Procedure ExportUnifBuilder(var UniformBuilder:TvUniformBuilder;GPU_USERDATA:PGPU_USERDATA);
|
||||
end;
|
||||
|
||||
function GetSharpByPatch(pData:Pointer;const addr:ADataLayout):Pointer;
|
||||
|
|
@ -1203,18 +1203,18 @@ begin
|
|||
Result:=(FLayout<>nil);
|
||||
end;
|
||||
|
||||
Procedure TvShaderGroup.ExportAttrBuilder(var AttrBuilder:TvAttrBuilder;var GPU_REGS:TGPU_REGS);
|
||||
Procedure TvShaderGroup.ExportAttrBuilder(var AttrBuilder:TvAttrBuilder;GPU_USERDATA:PGPU_USERDATA);
|
||||
var
|
||||
Shader:TvShaderExt;
|
||||
begin
|
||||
Shader:=FKey.FShaders[vShaderStageVs];
|
||||
if (Shader<>nil) then
|
||||
begin
|
||||
Shader.EnumVertLayout(@AttrBuilder.AddAttr,Shader.FDescSetId,GPU_REGS.get_user_data(vShaderStageVs))
|
||||
Shader.EnumVertLayout(@AttrBuilder.AddAttr,Shader.FDescSetId,GPU_USERDATA^.get_user_data(vShaderStageVs))
|
||||
end;
|
||||
end;
|
||||
|
||||
Procedure TvShaderGroup.ExportUnifBuilder(var UniformBuilder:TvUniformBuilder;var GPU_REGS:TGPU_REGS);
|
||||
Procedure TvShaderGroup.ExportUnifBuilder(var UniformBuilder:TvUniformBuilder;GPU_USERDATA:PGPU_USERDATA);
|
||||
var
|
||||
Shader:TvShaderExt;
|
||||
i:TvShaderStage;
|
||||
|
|
@ -1224,7 +1224,7 @@ begin
|
|||
Shader:=FKey.FShaders[i];
|
||||
if (Shader<>nil) then
|
||||
begin
|
||||
Shader.EnumUnifLayout(@UniformBuilder.AddAttr,Shader.FDescSetId,GPU_REGS.get_user_data(i));
|
||||
Shader.EnumUnifLayout(@UniformBuilder.AddAttr,Shader.FDescSetId,GPU_USERDATA^.get_user_data(i));
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
|
|
|
|||
|
|
@ -72,7 +72,8 @@ type
|
|||
|
||||
function FetchShader(FStage:TvShaderStage;FDescSetId:Integer;var GPU_REGS:TGPU_REGS;pc:PPushConstAllocator):TvShaderExt;
|
||||
function FetchShaderGroup(F:PvShadersKey):TvShaderGroup;
|
||||
function FetchShaderGroup(var GPU_REGS:TGPU_REGS;pc:PPushConstAllocator):TvShaderGroup;
|
||||
function FetchShaderGroupRT(var GPU_REGS:TGPU_REGS;pc:PPushConstAllocator):TvShaderGroup;
|
||||
function FetchShaderGroupCS(var GPU_REGS:TGPU_REGS;pc:PPushConstAllocator):TvShaderGroup;
|
||||
|
||||
implementation
|
||||
|
||||
|
|
@ -577,7 +578,7 @@ begin
|
|||
FShaderGroupSet.Unlock_wr;
|
||||
end;
|
||||
|
||||
function FetchShaderGroup(var GPU_REGS:TGPU_REGS;pc:PPushConstAllocator):TvShaderGroup;
|
||||
function FetchShaderGroupRT(var GPU_REGS:TGPU_REGS;pc:PPushConstAllocator):TvShaderGroup;
|
||||
var
|
||||
FShadersKey:TvShadersKey;
|
||||
i:TvShaderStage;
|
||||
|
|
@ -600,5 +601,16 @@ begin
|
|||
Result:=FetchShaderGroup(@FShadersKey);
|
||||
end;
|
||||
|
||||
function FetchShaderGroupCS(var GPU_REGS:TGPU_REGS;pc:PPushConstAllocator):TvShaderGroup;
|
||||
var
|
||||
FShadersKey:TvShadersKey;
|
||||
begin
|
||||
FShadersKey:=Default(TvShadersKey);
|
||||
|
||||
FShadersKey.FShaders[vShaderStageCs]:=FetchShader(vShaderStageCs,0,GPU_REGS,pc);
|
||||
|
||||
Result:=FetchShaderGroup(@FShadersKey);
|
||||
end;
|
||||
|
||||
end.
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue