mirror of https://github.com/red-prig/fpPS4.git
346 lines
7.4 KiB
Plaintext
346 lines
7.4 KiB
Plaintext
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unit emit_SOP2;
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{$mode objfpc}{$H+}
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interface
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uses
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sysutils,
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ps4_pssl,
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srTypes,
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srConst,
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srReg,
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SprvEmit,
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emit_op;
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type
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TEmit_SOP2=object(TEmitOp)
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procedure _emit_SOP2;
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procedure _emit_S_ADD_I32;
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procedure _emit_S_MUL_I32;
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procedure _emit_S_LSHL_B32;
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procedure _emit_S_LSHR_B32;
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procedure _emit_S_AND_B32;
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procedure _emit_S_AND_B64;
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procedure _emit_S_ANDN2_B64;
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procedure _emit_S_OR_B64;
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procedure _emit_S_NOR_B64;
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procedure _emit_S_CSELECT_B32;
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procedure _emit_S_BFE_U32;
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end;
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implementation
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procedure TEmit_SOP2._emit_S_ADD_I32;
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Var
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dst,car:PsrRegSlot;
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src:array[0..1] of PsrRegNode;
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begin
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dst:=FRegsStory.get_sdst7(FSPI.SOP2.SDST);
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car:=@FRegsStory.SCC;
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtInt32);
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emit_OpIAddExt(dst,car,src[0],src[1]);
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end;
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procedure TEmit_SOP2._emit_S_MUL_I32;
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Var
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dst:PsrRegSlot;
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src:array[0..1] of PsrRegNode;
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begin
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dst:=FRegsStory.get_sdst7(FSPI.SOP2.SDST);
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtInt32);
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emit_OpIMul(dst,src[0],src[1]);
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end;
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procedure TEmit_SOP2._emit_S_LSHL_B32; //SCC = (sdst.u != 0)
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Var
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dst,tmp:PsrRegSlot;
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src:array[0..2] of PsrRegNode;
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begin
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dst:=FRegsStory.get_sdst7(FSPI.SOP2.SDST);
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tmp:=@FRegsStory.FUnattach;
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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src[2]:=FetchReg(FConsts.Fetch(dtUInt32,31));
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emit_OpBitwiseAnd(tmp,src[1],src[2]);
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src[1]:=MakeRead(tmp,dtUInt32);
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emit_OpShl(dst,src[0],src[1]);
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//dst = dtUint32
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tmp:=@FRegsStory.SCC;
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MakeCopy(tmp,dst^.current);
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tmp^.current^.dtype:=dtBool;
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//dst^.current^.mark_read;
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//emit_IntToBool(line,FRegsStory.SCC.New(dtBool),dst^.current);
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end;
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procedure TEmit_SOP2._emit_S_LSHR_B32; //SCC = (sdst.u != 0)
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Var
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dst,tmp:PsrRegSlot;
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src:array[0..2] of PsrRegNode;
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begin
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dst:=FRegsStory.get_sdst7(FSPI.SOP2.SDST);
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tmp:=@FRegsStory.FUnattach;
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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src[2]:=FetchReg(FConsts.Fetch(dtUInt32,31));
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emit_OpBitwiseAnd(tmp,src[1],src[2]);
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src[1]:=MakeRead(tmp,dtUInt32);
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emit_OpShr(dst,src[0],src[1]);
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tmp:=@FRegsStory.SCC;
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MakeCopy(tmp,dst^.current);
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tmp^.current^.dtype:=dtBool;
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end;
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procedure TEmit_SOP2._emit_S_AND_B32; //SCC = (sdst.u != 0)
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Var
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dst,tmp:PsrRegSlot;
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src:array[0..1] of PsrRegNode;
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begin
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dst:=FRegsStory.get_sdst7(FSPI.SOP2.SDST);
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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emit_OpBitwiseAnd(dst,src[0],src[1]);
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tmp:=@FRegsStory.SCC;
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MakeCopy(tmp,dst^.current);
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tmp^.current^.dtype:=dtBool;
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end;
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procedure TEmit_SOP2._emit_S_AND_B64; //SCC = (sdst[2] != 0)
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Var
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dst:array[0..1] of PsrRegSlot;
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src0,src1,src2:array[0..1] of PsrRegNode;
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begin
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if not FRegsStory.get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(@src0,FSPI.SOP2.SSRC0,dtUInt32) then Assert(False);
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if not fetch_ssrc9_pair(@src1,FSPI.SOP2.SSRC1,dtUInt32) then Assert(False);
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emit_OpBitwiseAnd(dst[0],src0[0],src1[0]);
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emit_OpBitwiseAnd(dst[1],src0[1],src1[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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src2[0]^.mark_read;
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src2[1]^.mark_read;
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emit_OpLogicalOr(@FRegsStory.SCC,src2[0],src2[1]); //implict cast (int != 0)
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end;
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procedure TEmit_SOP2._emit_S_ANDN2_B64; //SCC = (sdst[2] != 0)
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Var
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dst:array[0..1] of PsrRegSlot;
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tmp:PsrRegSlot;
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src0,src1,src2:array[0..1] of PsrRegNode;
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begin
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if not FRegsStory.get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(@src0,FSPI.SOP2.SSRC0,dtUInt32) then Assert(False);
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if not fetch_ssrc9_pair(@src1,FSPI.SOP2.SSRC1,dtUInt32) then Assert(False);
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tmp:=@FRegsStory.FUnattach;
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emit_OpNot(tmp,src1[0]);
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src1[0]:=MakeRead(tmp,dtUnknow);
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emit_OpNot(tmp,src1[1]);
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src1[1]:=MakeRead(tmp,dtUnknow);
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emit_OpBitwiseAnd(dst[0],src0[0],src1[0]);
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emit_OpBitwiseAnd(dst[1],src0[1],src1[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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src2[0]^.mark_read;
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src2[1]^.mark_read;
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emit_OpLogicalOr(@FRegsStory.SCC,src2[0],src2[1]); //implict cast (int != 0)
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end;
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procedure TEmit_SOP2._emit_S_OR_B64; //SCC = (sdst[2] != 0)
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Var
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dst:array[0..1] of PsrRegSlot;
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src0,src1,src2:array[0..1] of PsrRegNode;
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begin
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if not FRegsStory.get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(@src0,FSPI.SOP2.SSRC0,dtUInt32) then Assert(False);
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if not fetch_ssrc9_pair(@src1,FSPI.SOP2.SSRC1,dtUInt32) then Assert(False);
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emit_OpBitwiseOr(dst[0],src0[0],src1[0]);
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emit_OpBitwiseOr(dst[1],src0[1],src1[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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src2[0]^.mark_read;
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src2[1]^.mark_read;
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emit_OpLogicalOr(@FRegsStory.SCC,src2[0],src2[1]); //implict cast (int != 0)
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end;
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procedure TEmit_SOP2._emit_S_NOR_B64; //SCC = (sdst[2] != 0)
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Var
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dst:array[0..1] of PsrRegSlot;
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src0,src1,src2:array[0..1] of PsrRegNode;
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begin
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if not FRegsStory.get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(@src0,FSPI.SOP2.SSRC0,dtUInt32) then Assert(False);
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if not fetch_ssrc9_pair(@src1,FSPI.SOP2.SSRC1,dtUInt32) then Assert(False);
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emit_OpBitwiseOr(dst[0],src0[0],src1[0]);
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emit_OpBitwiseOr(dst[1],src0[1],src1[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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src2[0]^.mark_read;
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src2[1]^.mark_read;
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emit_OpNot(dst[0],src2[0]);
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emit_OpNot(dst[1],src2[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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src2[0]^.mark_read;
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src2[1]^.mark_read;
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emit_OpLogicalOr(@FRegsStory.SCC,src2[0],src2[1]); //implict cast (int != 0)
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end;
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procedure TEmit_SOP2._emit_S_CSELECT_B32; //sdst = SCC ? ssrc0 : ssrc1
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Var
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dst:PsrRegSlot;
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src:array[0..2] of PsrRegNode;
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begin
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dst:=FRegsStory.get_sdst7(FSPI.SOP2.SDST);
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUnknow);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUnknow);
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src[2]:=MakeRead(@FRegsStory.SCC,dtBool);
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emit_OpSelect(dst,src[0],src[1],src[2]);
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end;
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//offset = ssrc1[4:0].u and 31
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//width = ssrc1[22:16].u shr 16
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procedure TEmit_SOP2._emit_S_BFE_U32; //sdst.u = bitFieldExtract(ssrc0); SCC = (sdst.u != 0)
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Var
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dst,tmp:PsrRegSlot;
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src:array[0..1] of PsrRegNode;
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num_31,num_16:PsrRegNode;
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offset,count:PsrRegNode;
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begin
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dst:=FRegsStory.get_sdst7(FSPI.SOP2.SDST);
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tmp:=@FRegsStory.FUnattach;
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUint32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUint32);
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num_31:=FetchReg(FConsts.Fetch(dtUInt32,31));
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emit_OpBitwiseAnd(tmp,src[1],num_31);
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offset:=MakeRead(tmp,dtUInt32);
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num_16:=FetchReg(FConsts.Fetch(dtUInt32,16));
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src[1]^.mark_read;
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emit_OpShr(tmp,src[1],num_16);
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count:=MakeRead(tmp,dtUInt32);
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emit_OpBfeU(dst,src[0],offset,count);
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tmp:=@FRegsStory.SCC;
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MakeCopy(tmp,dst^.current);
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tmp^.current^.dtype:=dtBool;
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end;
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procedure TEmit_SOP2._emit_SOP2;
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begin
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Case FSPI.SOP2.OP of
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S_ADD_I32:
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begin
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_emit_S_ADD_I32;
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end;
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S_MUL_I32: //& 0xFFFFFFFF
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begin
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_emit_S_MUL_I32;
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end;
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S_LSHL_B32: //SCC = (sdst.u != 0)
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begin
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_emit_S_LSHL_B32;
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end;
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S_LSHR_B32:
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begin
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_emit_S_LSHR_B32;
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end;
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S_AND_B32:
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begin
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_emit_S_AND_B32;
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end;
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S_AND_B64:
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begin
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_emit_S_AND_B64;
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end;
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S_ANDN2_B64:
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begin
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_emit_S_ANDN2_B64;
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end;
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S_OR_B64:
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begin
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_emit_S_OR_B64;
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end;
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S_NOR_B64:
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begin
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_emit_S_NOR_B64;
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end;
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S_CSELECT_B32:
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begin
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_emit_S_CSELECT_B32;
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end;
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S_BFE_U32:
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begin
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_emit_S_BFE_U32;
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end;
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else
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Assert(False,'SOP2?'+IntToStr(FSPI.SOP2.OP));
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end;
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end;
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end.
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