2022-05-31 07:17:14 +00:00
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unit emit_VOP1;
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{$mode objfpc}{$H+}
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interface
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uses
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sysutils,
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ps4_pssl,
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srTypes,
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srReg,
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spirv,
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SprvEmit,
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emit_op;
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type
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TEmit_VOP1=object(TEmitOp)
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procedure _emit_VOP1;
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procedure _emit_V_MOV_B32;
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2022-06-30 09:59:08 +00:00
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procedure _emit_V_CVT(OpId:DWORD;dst_type,src_type:TsrDataType);
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2022-05-31 07:17:14 +00:00
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procedure _emit_V_CVT_OFF_F32_I4;
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2022-06-30 09:59:08 +00:00
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procedure _emit_V_EXT_F32(OpId:DWORD);
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2022-05-31 07:17:14 +00:00
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procedure _emit_V_RCP_F32;
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end;
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implementation
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procedure TEmit_VOP1._emit_V_MOV_B32;
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Var
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dst:PsrRegSlot;
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src:PsrRegNode;
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begin
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dst:=FRegsStory.get_vdst8(FSPI.VOP1.VDST);
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src:=fetch_ssrc9(FSPI.VOP1.SRC0,dtUnknow);
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_MakeCopy(dst,src);
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end;
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2022-06-30 09:59:08 +00:00
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procedure TEmit_VOP1._emit_V_CVT(OpId:DWORD;dst_type,src_type:TsrDataType);
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2022-05-31 07:17:14 +00:00
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Var
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dst:PsrRegSlot;
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src:PsrRegNode;
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begin
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dst:=FRegsStory.get_vdst8(FSPI.VOP1.VDST);
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2022-06-30 09:59:08 +00:00
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src:=fetch_ssrc9(FSPI.VOP1.SRC0,src_type);
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emit_Op1(OpId,dst_type,dst,src);
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2022-05-31 07:17:14 +00:00
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end;
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//V_CVT_OFF_F32_I4
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//([0..3]-8)/16
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procedure TEmit_VOP1._emit_V_CVT_OFF_F32_I4;
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Var
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dst,tmp:PsrRegSlot;
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src:PsrRegNode;
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num_8:PsrRegNode;
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num_15:PsrRegNode;
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num_16:PsrRegNode;
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subi,subf:PsrRegNode;
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begin
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dst:=FRegsStory.get_vdst8(FSPI.VOP1.VDST);
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src:=fetch_ssrc9(FSPI.VOP1.SRC0,dtUInt32);
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tmp:=@FRegsStory.FUnattach;
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num_15:=FetchReg(FConsts.Fetch(dtUInt32,15));
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emit_OpBitwiseAnd(tmp,src,num_15);
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src:=MakeRead(tmp,dtUInt32);
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num_8:=FetchReg(FConsts.Fetch(dtInt32,8));
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subi:=dst^.New(line,dtInt32);
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_emit_OpISub(line,subi,src,num_8);
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subi^.mark_read;
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subf:=dst^.New(line,dtFloat32);
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_emit_Op1(line,Op.OpConvertSToF,subf,subi);
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subf^.mark_read;
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num_16:=FetchReg(FConsts.Fetchf(dtFloat32,16));
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emit_OpFDiv(dst,subf,num_16);
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end;
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2022-06-30 09:59:08 +00:00
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procedure TEmit_VOP1._emit_V_EXT_F32(OpId:DWORD);
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2022-05-31 07:17:14 +00:00
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Var
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dst:PsrRegSlot;
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src:PsrRegNode;
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begin
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dst:=FRegsStory.get_vdst8(FSPI.VOP1.VDST);
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src:=fetch_ssrc9(FSPI.VOP1.SRC0,dtFloat32);
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2022-06-30 09:59:08 +00:00
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emit_OpExt1(OpId,dtFloat32,dst,src);
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2022-05-31 07:17:14 +00:00
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end;
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procedure TEmit_VOP1._emit_V_RCP_F32;
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Var
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dst:PsrRegSlot;
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src:PsrRegNode;
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one:PsrRegNode;
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begin
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dst:=FRegsStory.get_vdst8(FSPI.VOP1.VDST);
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src:=fetch_ssrc9(FSPI.VOP1.SRC0,dtFloat32);
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one:=FetchReg(FConsts.Fetchf(dtFloat32,1));
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emit_OpFDiv(dst,one,src);
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end;
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procedure TEmit_VOP1._emit_VOP1;
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begin
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Case FSPI.VOP1.OP of
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2022-06-30 09:59:08 +00:00
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V_NOP:;
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2022-05-31 07:17:14 +00:00
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V_MOV_B32:
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begin
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_emit_V_MOV_B32;
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end;
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2022-06-30 09:59:08 +00:00
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V_CVT_F32_I32: _emit_V_CVT(Op.OpConvertSToF,dtFloat32,dtInt32);
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V_CVT_F32_U32: _emit_V_CVT(Op.OpConvertUToF,dtFloat32,dtUInt32);
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V_CVT_U32_F32: _emit_V_CVT(Op.OpConvertFToU,dtUInt32 ,dtFloat32);
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V_CVT_I32_F32: _emit_V_CVT(Op.OpConvertFToS,dtInt32 ,dtFloat32);
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2022-05-31 07:17:14 +00:00
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V_CVT_OFF_F32_I4:
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begin
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_emit_V_CVT_OFF_F32_I4;
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end;
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2022-06-30 09:59:08 +00:00
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V_FRACT_F32: _emit_V_EXT_F32(GlslOp.Fract);
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V_TRUNC_F32: _emit_V_EXT_F32(GlslOp.Trunc);
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V_CEIL_F32 : _emit_V_EXT_F32(GlslOp.Ceil);
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2022-05-31 07:17:14 +00:00
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2022-06-30 09:59:08 +00:00
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V_FLOOR_F32: _emit_V_EXT_F32(GlslOp.Floor);
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V_EXP_F32 : _emit_V_EXT_F32(GlslOp.Exp2);
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V_LOG_F32 : _emit_V_EXT_F32(GlslOp.Log2);
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2022-05-31 07:17:14 +00:00
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2022-06-30 09:59:08 +00:00
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V_RSQ_F32 : _emit_V_EXT_F32(GlslOp.InverseSqrt);
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2022-05-31 07:17:14 +00:00
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2022-06-30 09:59:08 +00:00
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V_SQRT_F32 : _emit_V_EXT_F32(GlslOp.Sqrt);
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2022-05-31 07:17:14 +00:00
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2022-06-30 09:59:08 +00:00
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V_SIN_F32 : _emit_V_EXT_F32(GlslOp.Sin);
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V_COS_F32 : _emit_V_EXT_F32(GlslOp.Cos);
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2022-05-31 07:17:14 +00:00
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V_RCP_F32:
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begin
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_emit_V_RCP_F32;
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end;
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else
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Assert(false,'VOP1?'+IntToStr(FSPI.VOP1.OP));
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end;
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end;
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end.
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